Hello community, here is the log from the commit of package mcelog for openSUSE:Factory checked in at 2014-05-18 06:50:06 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/mcelog (Old) and /work/SRC/openSUSE:Factory/.mcelog.new (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "mcelog" Changes: -------- --- /work/SRC/openSUSE:Factory/mcelog/mcelog.changes 2014-05-02 14:00:51.000000000 +0200 +++ /work/SRC/openSUSE:Factory/.mcelog.new/mcelog.changes 2014-05-18 06:50:14.000000000 +0200 @@ -1,0 +2,14 @@ +Fri May 16 15:47:18 UTC 2014 - [email protected] + +- Add mce decoding support for latest AMD CPUs (bnc#871881). +- Implementation done by Borislav Petkov <[email protected]> + * Add patches/Start-consolidating-AMD-specific-stuff.patch + * Add add-defines.patch + * Add add-f10h-support.patch + * Add add-f11h-support.patch + * Add add-f12h-support.patch + * Add add-f14h-support.patch + * Add add-f15h-support.patch + * Add add-f16h-support.patch + +------------------------------------------------------------------- New: ---- Start-consolidating-AMD-specific-stuff.patch add-defines.patch add-f10h-support.patch add-f11h-support.patch add-f12h-support.patch add-f14h-support.patch add-f15h-support.patch add-f16h-support.patch ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ mcelog.spec ++++++ --- /var/tmp/diff_new_pack.v3jhD2/_old 2014-05-18 06:50:15.000000000 +0200 +++ /var/tmp/diff_new_pack.v3jhD2/_new 2014-05-18 06:50:15.000000000 +0200 @@ -35,6 +35,14 @@ Source6: README.email_setup Patch1: email.patch Patch2: mcelog_invert_prefill_db_warning.patch +Patch3: Start-consolidating-AMD-specific-stuff.patch +Patch4: patches/add-defines.patch +Patch5: patches/add-f10h-support.patch +Patch6: patches/add-f11h-support.patch +Patch7: patches/add-f12h-support.patch +Patch8: patches/add-f14h-support.patch +Patch9: patches/add-f15h-support.patch +Patch10: patches/add-f16h-support.patch BuildRoot: %{_tmppath}/%{name}-%{version}-build PreReq: %fillup_prereq Url: https://git.kernel.org/cgit/utils/cpu/mce/mcelog.git @@ -62,6 +70,14 @@ %setup -q %patch1 -p1 %patch2 -p1 +%patch3 -p1 +%patch4 -p1 +%patch5 -p1 +%patch6 -p1 +%patch7 -p1 +%patch8 -p1 +%patch9 -p1 +%patch10 -p1 %build export SUSE_ASNEEDED=0 ++++++ Start-consolidating-AMD-specific-stuff.patch ++++++ ++++ 665 lines (skipped) ++++++ add-defines.patch ++++++ Add AMD-specific defines and helpers Signed-off-by: Borislav Petkov <[email protected]> Index: mcelog/amd.h =================================================================== --- mcelog.orig/amd.h 2014-05-08 01:10:26.000000000 +0200 +++ mcelog/amd.h 2014-05-08 01:18:50.000000000 +0200 @@ -10,5 +10,65 @@ int mce_filter_k8(struct mce *m); #define K8_MCELOG_THRESHOLD_L3_CACHE (4 * 9 + 2) #define K8_MCELOG_THRESHOLD_FBDIMM (4 * 9 + 3) +#define EC(x) ((x) & 0xffff) +#define XEC(x, mask) (((x) >> 16) & mask) + +#define LOW_SYNDROME(x) (((x) >> 15) & 0xff) +#define HIGH_SYNDROME(x) (((x) >> 24) & 0xff) + +#define TLB_ERROR(x) (((x) & 0xFFF0) == 0x0010) +#define MEM_ERROR(x) (((x) & 0xFF00) == 0x0100) +#define BUS_ERROR(x) (((x) & 0xF800) == 0x0800) +#define INT_ERROR(x) (((x) & 0xF4FF) == 0x0400) + +#define TT(x) (((x) >> 2) & 0x3) +#define TT_MSG(x) tt_msgs[TT(x)] +#define II(x) (((x) >> 2) & 0x3) +#define II_MSG(x) ii_msgs[II(x)] +#define LL(x) ((x) & 0x3) +#define LL_MSG(x) ll_msgs[LL(x)] +#define TO(x) (((x) >> 8) & 0x1) +#define TO_MSG(x) to_msgs[TO(x)] +#define PP(x) (((x) >> 9) & 0x3) +#define PP_MSG(x) pp_msgs[PP(x)] +#define UU(x) (((x) >> 8) & 0x3) +#define UU_MSG(x) uu_msgs[UU(x)] + +#define R4(x) (((x) >> 4) & 0xf) +#define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] : "Wrong R4!") + #define CASE_AMD_CPUS \ case CPU_K8 + +enum tt_ids { + TT_INSTR = 0, + TT_DATA, + TT_GEN, + TT_RESV, +}; + +enum ll_ids { + LL_RESV = 0, + LL_L1, + LL_L2, + LL_LG, +}; + +enum ii_ids { + II_MEM = 0, + II_RESV, + II_IO, + II_GEN, +}; + +enum rrrr_ids { + R4_GEN = 0, + R4_RD, + R4_WR, + R4_DRD, + R4_DWR, + R4_IRD, + R4_PREF, + R4_EVICT, + R4_SNOOP, +}; ++++++ add-f10h-support.patch ++++++ ++++ 728 lines (skipped) ++++++ add-f11h-support.patch ++++++ Add F11h decoding support Signed-off-by: Borislav Petkov <[email protected]> Index: mcelog-1.0.1/amd.c =================================================================== --- mcelog-1.0.1.orig/amd.c +++ mcelog-1.0.1/amd.c @@ -155,6 +155,8 @@ enum cputype select_amd_cputype(u32 fami return CPU_K8; case 0x10: return CPU_F10H; + case 0x11: + return CPU_F11H; default: break; } @@ -367,6 +369,16 @@ static bool f10h_mc0_mce(u16 ec, u8 xec) return f12h_mc0_mce(ec, xec); } +static bool k8_mc0_mce(u16 ec, u8 xec) +{ + if (BUS_ERROR(ec)) { + Wprintf("during system linefill.\n"); + return true; + } + + return f10h_mc0_mce(ec, xec); +} + static void decode_mc0_mce(struct amd_decoder_ops *ops, struct mce *m) { u16 ec = EC(m->status); @@ -630,6 +642,12 @@ struct amd_decoder_ops fam_ops[] = { .mc1_mce = k8_mc1_mce, .mc2_mce = k8_mc2_mce, }, + [AMD_F11H] = { + .cpu = AMD_F11H, + .mc0_mce = k8_mc0_mce, + .mc1_mce = k8_mc1_mce, + .mc2_mce = k8_mc2_mce, + }, }; static void __decode_amd_mc(enum cputype cpu, struct mce *mce) @@ -640,6 +658,9 @@ static void __decode_amd_mc(enum cputype case CPU_F10H: ops = &fam_ops[AMD_F10H]; break; + case CPU_F11H: + ops = &fam_ops[AMD_F11H]; + break; default: Eprintf("Huh? What family is it: 0x%x?!\n", cpu); return; Index: mcelog-1.0.1/amd.h =================================================================== --- mcelog-1.0.1.orig/amd.h +++ mcelog-1.0.1/amd.h @@ -93,4 +93,5 @@ enum rrrr_ids { #define CASE_AMD_CPUS \ case CPU_K8: \ - case CPU_F10H + case CPU_F10H: \ + case CPU_F11H Index: mcelog-1.0.1/mcelog.h =================================================================== --- mcelog-1.0.1.orig/mcelog.h +++ mcelog-1.0.1/mcelog.h @@ -108,6 +108,7 @@ enum cputype { CPU_CORE2, /* 65nm and 45nm */ CPU_K8, CPU_F10H, + CPU_F11H, CPU_P4, CPU_NEHALEM, CPU_DUNNINGTON, Index: mcelog-1.0.1/mcelog.c =================================================================== --- mcelog-1.0.1.orig/mcelog.c +++ mcelog-1.0.1/mcelog.c @@ -223,6 +223,7 @@ static char *cputype_name[] = { [CPU_CORE2] = "Intel Core", /* 65nm and 45nm */ [CPU_K8] = "AMD K8 and derivates", [CPU_F10H] = "AMD Greyhound", + [CPU_F11H] = "AMD Griffin", [CPU_P4] = "Intel P4", [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7 (\"Nehalem/Westmere\")", [CPU_DUNNINGTON] = "Intel Xeon 7400 series", @@ -242,6 +243,7 @@ static struct config_choice cpu_choices[ { "core2", CPU_CORE2 }, { "k8", CPU_K8 }, { "f10h", CPU_F10H }, + { "f11h", CPU_F11H }, { "p4", CPU_P4 }, { "dunnington", CPU_DUNNINGTON }, { "xeon74xx", CPU_DUNNINGTON }, ++++++ add-f12h-support.patch ++++++ Add F12h decoding support Signed-off-by: Borislav Petkov <[email protected]> Index: mcelog-1.0.1/amd.c =================================================================== --- mcelog-1.0.1.orig/amd.c +++ mcelog-1.0.1/amd.c @@ -157,6 +157,8 @@ enum cputype select_amd_cputype(u32 fami return CPU_F10H; case 0x11: return CPU_F11H; + case 0x12: + return CPU_F12H; default: break; } @@ -648,6 +650,12 @@ struct amd_decoder_ops fam_ops[] = { .mc1_mce = k8_mc1_mce, .mc2_mce = k8_mc2_mce, }, + [AMD_F12H] = { + .cpu = AMD_F12H, + .mc0_mce = f12h_mc0_mce, + .mc1_mce = k8_mc1_mce, + .mc2_mce = k8_mc2_mce, + }, }; static void __decode_amd_mc(enum cputype cpu, struct mce *mce) @@ -661,6 +669,9 @@ static void __decode_amd_mc(enum cputype case CPU_F11H: ops = &fam_ops[AMD_F11H]; break; + case CPU_F12H: + ops = &fam_ops[AMD_F12H]; + break; default: Eprintf("Huh? What family is it: 0x%x?!\n", cpu); return; Index: mcelog-1.0.1/amd.h =================================================================== --- mcelog-1.0.1.orig/amd.h +++ mcelog-1.0.1/amd.h @@ -9,6 +9,7 @@ enum amdcpu { AMD_K8 = 0, AMD_F10H, AMD_F11H, + AMD_F12H, AMD_F14H, AMD_F15H, AMD_F16H, @@ -94,4 +95,5 @@ enum rrrr_ids { #define CASE_AMD_CPUS \ case CPU_K8: \ case CPU_F10H: \ - case CPU_F11H + case CPU_F11H: \ + case CPU_F12H Index: mcelog-1.0.1/mcelog.h =================================================================== --- mcelog-1.0.1.orig/mcelog.h +++ mcelog-1.0.1/mcelog.h @@ -109,6 +109,7 @@ enum cputype { CPU_K8, CPU_F10H, CPU_F11H, + CPU_F12H, CPU_P4, CPU_NEHALEM, CPU_DUNNINGTON, Index: mcelog-1.0.1/mcelog.c =================================================================== --- mcelog-1.0.1.orig/mcelog.c +++ mcelog-1.0.1/mcelog.c @@ -224,6 +224,7 @@ static char *cputype_name[] = { [CPU_K8] = "AMD K8 and derivates", [CPU_F10H] = "AMD Greyhound", [CPU_F11H] = "AMD Griffin", + [CPU_F12H] = "AMD Llano", [CPU_P4] = "Intel P4", [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7 (\"Nehalem/Westmere\")", [CPU_DUNNINGTON] = "Intel Xeon 7400 series", @@ -244,6 +245,7 @@ static struct config_choice cpu_choices[ { "k8", CPU_K8 }, { "f10h", CPU_F10H }, { "f11h", CPU_F11H }, + { "f12h", CPU_F12H }, { "p4", CPU_P4 }, { "dunnington", CPU_DUNNINGTON }, { "xeon74xx", CPU_DUNNINGTON }, ++++++ add-f14h-support.patch ++++++ Add F14h decoding support Signed-off-by: Borislav Petkov <[email protected]> Index: mcelog-1.0.1/amd.c =================================================================== --- mcelog-1.0.1.orig/amd.c +++ mcelog-1.0.1/amd.c @@ -159,6 +159,8 @@ enum cputype select_amd_cputype(u32 fami return CPU_F11H; case 0x12: return CPU_F12H; + case 0x14: + return CPU_F14H; default: break; } @@ -381,6 +383,58 @@ static bool k8_mc0_mce(u16 ec, u8 xec) return f10h_mc0_mce(ec, xec); } +static bool cat_mc0_mce(u16 ec, u8 xec) +{ + u8 r4 = R4(ec); + bool ret = true; + + if (MEM_ERROR(ec)) { + + if (TT(ec) != TT_DATA || LL(ec) != LL_L1) + return false; + + switch (r4) { + case R4_DRD: + case R4_DWR: + Wprintf("Data/Tag parity error due to %s.\n", + (r4 == R4_DRD ? "load/hw prf" : "store")); + break; + case R4_EVICT: + Wprintf("Copyback parity error on a tag miss.\n"); + break; + case R4_SNOOP: + Wprintf("Tag parity error during snoop.\n"); + break; + default: + ret = false; + } + } else if (BUS_ERROR(ec)) { + + if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG) + return false; + + Wprintf("System read data error on a "); + + switch (r4) { + case R4_RD: + Wprintf("TLB reload.\n"); + break; + case R4_DWR: + Wprintf("store.\n"); + break; + case R4_DRD: + Wprintf("load.\n"); + break; + default: + ret = false; + } + } else { + ret = false; + } + + return ret; +} + static void decode_mc0_mce(struct amd_decoder_ops *ops, struct mce *m) { u16 ec = EC(m->status); @@ -402,6 +456,31 @@ static void decode_mc0_mce(struct amd_de Eprintf("Corrupted MC0 MCE info?\n"); } +static bool cat_mc1_mce(u16 ec, u8 xec) +{ + u8 r4 = R4(ec); + bool ret = true; + + if (!MEM_ERROR(ec)) + return false; + + if (TT(ec) != TT_INSTR) + return false; + + if (r4 == R4_IRD) + Wprintf("Data/tag array parity error for a tag hit.\n"); + else if (r4 == R4_SNOOP) + Wprintf("Tag error during snoop/victimization.\n"); + else if (xec == 0x0) + Wprintf("Tag parity error from victim castout.\n"); + else if (xec == 0x2) + Wprintf("Microcode patch RAM parity error.\n"); + else + ret = false; + + return ret; +} + static void decode_mc1_mce(struct amd_decoder_ops *ops, struct mce *m) { u16 ec = EC(m->status); @@ -656,6 +735,12 @@ struct amd_decoder_ops fam_ops[] = { .mc1_mce = k8_mc1_mce, .mc2_mce = k8_mc2_mce, }, + [AMD_F14H] = { + .cpu = AMD_F14H, + .mc0_mce = cat_mc0_mce, + .mc1_mce = cat_mc1_mce, + .mc2_mce = k8_mc2_mce, + }, }; static void __decode_amd_mc(enum cputype cpu, struct mce *mce) @@ -672,6 +757,9 @@ static void __decode_amd_mc(enum cputype case CPU_F12H: ops = &fam_ops[AMD_F12H]; break; + case CPU_F14H: + ops = &fam_ops[AMD_F14H]; + break; default: Eprintf("Huh? What family is it: 0x%x?!\n", cpu); return; Index: mcelog-1.0.1/mcelog.h =================================================================== --- mcelog-1.0.1.orig/mcelog.h +++ mcelog-1.0.1/mcelog.h @@ -110,6 +110,7 @@ enum cputype { CPU_F10H, CPU_F11H, CPU_F12H, + CPU_F14H, CPU_P4, CPU_NEHALEM, CPU_DUNNINGTON, Index: mcelog-1.0.1/amd.h =================================================================== --- mcelog-1.0.1.orig/amd.h +++ mcelog-1.0.1/amd.h @@ -96,4 +96,5 @@ enum rrrr_ids { case CPU_K8: \ case CPU_F10H: \ case CPU_F11H: \ - case CPU_F12H + case CPU_F12H: \ + case CPU_F14H Index: mcelog-1.0.1/mcelog.c =================================================================== --- mcelog-1.0.1.orig/mcelog.c +++ mcelog-1.0.1/mcelog.c @@ -225,6 +225,7 @@ static char *cputype_name[] = { [CPU_F10H] = "AMD Greyhound", [CPU_F11H] = "AMD Griffin", [CPU_F12H] = "AMD Llano", + [CPU_F14H] = "AMD Bobcat", [CPU_P4] = "Intel P4", [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7 (\"Nehalem/Westmere\")", [CPU_DUNNINGTON] = "Intel Xeon 7400 series", @@ -246,6 +247,7 @@ static struct config_choice cpu_choices[ { "f10h", CPU_F10H }, { "f11h", CPU_F11H }, { "f12h", CPU_F12H }, + { "f14h", CPU_F14H }, { "p4", CPU_P4 }, { "dunnington", CPU_DUNNINGTON }, { "xeon74xx", CPU_DUNNINGTON }, ++++++ add-f15h-support.patch ++++++ Add F15h decoding support Signed-off-by: Borislav Petkov <[email protected]> Index: mcelog-1.0.1/amd.c =================================================================== --- mcelog-1.0.1.orig/amd.c +++ mcelog-1.0.1/amd.c @@ -72,6 +72,43 @@ static char *nbextendederr[] = { "L3 Cache LRU Error" }; +static const char * const f15h_mc1_mce_desc[] = { + "UC during a demand linefill from L2", + "Parity error during data load from IC", + "Parity error for IC valid bit", + "Main tag parity error", + "Parity error in prediction queue", + "PFB data/address parity error", + "Parity error in the branch status reg", + "PFB promotion address error", + "Tag error during probe/victimization", + "Parity error for IC probe tag valid bit", + "PFB non-cacheable bit parity error", + "PFB valid bit parity error", /* xec = 0xd */ + "Microcode Patch Buffer", /* xec = 010 */ + "uop queue", + "insn buffer", + "predecode buffer", + "fetch address FIFO" +}; + +static const char * const f15h_mc2_mce_desc[] = { + "Fill ECC error on data fills", /* xec = 0x4 */ + "Fill parity error on insn fills", + "Prefetcher request FIFO parity error", + "PRQ address parity error", + "PRQ data parity error", + "WCC Tag ECC error", + "WCC Data ECC error", + "WCB Data parity error", + "VB Data ECC or parity error", + "L2 Tag ECC error", /* xec = 0x10 */ + "Hard L2 Tag ECC error", + "Multiple hits on L2 tag", + "XAB parity error", + "PRB address parity error" +}; + static const char * const mc4_mce_desc[] = { "DRAM ECC error detected on the NB", "CRC error detected on HT link", @@ -161,6 +198,8 @@ enum cputype select_amd_cputype(u32 fami return CPU_F12H; case 0x14: return CPU_F14H; + case 0x15: + return CPU_F15H; default: break; } @@ -435,6 +474,53 @@ static bool cat_mc0_mce(u16 ec, u8 xec) return ret; } +static bool f15h_mc0_mce(u16 ec, u8 xec) +{ + bool ret = true; + + if (MEM_ERROR(ec)) { + + switch (xec) { + case 0x0: + Wprintf("Data Array access error.\n"); + break; + + case 0x1: + Wprintf("UC error during a linefill from L2/NB.\n"); + break; + + case 0x2: + case 0x11: + Wprintf("STQ access error.\n"); + break; + + case 0x3: + Wprintf("SCB access error.\n"); + break; + + case 0x10: + Wprintf("Tag error.\n"); + break; + + case 0x12: + Wprintf("LDQ access error.\n"); + break; + + default: + ret = false; + } + } else if (BUS_ERROR(ec)) { + + if (!xec) + Wprintf("System Read Data Error.\n"); + else + Wprintf(" Internal error condition type %d.\n", xec); + } else + ret = false; + + return ret; +} + static void decode_mc0_mce(struct amd_decoder_ops *ops, struct mce *m) { u16 ec = EC(m->status); @@ -481,6 +567,36 @@ static bool cat_mc1_mce(u16 ec, u8 xec) return ret; } +static bool f15h_mc1_mce(u16 ec, u8 xec) +{ + bool ret = true; + + if (!MEM_ERROR(ec)) + return false; + + switch (xec) { + case 0x0 ... 0xa: + Wprintf("%s.\n", f15h_mc1_mce_desc[xec]); + break; + + case 0xd: + Wprintf("%s.\n", f15h_mc1_mce_desc[xec-2]); + break; + + case 0x10: + Wprintf("%s.\n", f15h_mc1_mce_desc[xec-4]); + break; + + case 0x11 ... 0x14: + Wprintf("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]); + break; + + default: + ret = false; + } + return ret; +} + static void decode_mc1_mce(struct amd_decoder_ops *ops, struct mce *m) { u16 ec = EC(m->status); @@ -537,6 +653,40 @@ static bool k8_mc2_mce(u16 ec, u8 xec) return ret; } +static bool f15h_mc2_mce(u16 ec, u8 xec) +{ + bool ret = true; + + if (TLB_ERROR(ec)) { + if (xec == 0x0) + Wprintf("Data parity TLB read error.\n"); + else if (xec == 0x1) + Wprintf("Poison data provided for TLB fill.\n"); + else + ret = false; + } else if (BUS_ERROR(ec)) { + if (xec > 2) + ret = false; + + Wprintf("Error during attempted NB data read.\n"); + } else if (MEM_ERROR(ec)) { + switch (xec) { + case 0x4 ... 0xc: + Wprintf("%s.\n", f15h_mc2_mce_desc[xec - 0x4]); + break; + + case 0x10 ... 0x14: + Wprintf("%s.\n", f15h_mc2_mce_desc[xec - 0x7]); + break; + + default: + ret = false; + } + } + + return ret; +} + static void decode_mc2_mce(struct amd_decoder_ops *ops, struct mce *m) { u16 ec = EC(m->status); @@ -741,6 +891,12 @@ struct amd_decoder_ops fam_ops[] = { .mc1_mce = cat_mc1_mce, .mc2_mce = k8_mc2_mce, }, + [AMD_F15H] = { + .cpu = AMD_F15H, + .mc0_mce = f15h_mc0_mce, + .mc1_mce = f15h_mc1_mce, + .mc2_mce = f15h_mc2_mce, + }, }; static void __decode_amd_mc(enum cputype cpu, struct mce *mce) @@ -760,6 +916,10 @@ static void __decode_amd_mc(enum cputype case CPU_F14H: ops = &fam_ops[AMD_F14H]; break; + case CPU_F15H: + xec_mask = 0x1f; + ops = &fam_ops[AMD_F15H]; + break; default: Eprintf("Huh? What family is it: 0x%x?!\n", cpu); return; Index: mcelog-1.0.1/mcelog.h =================================================================== --- mcelog-1.0.1.orig/mcelog.h +++ mcelog-1.0.1/mcelog.h @@ -111,6 +111,7 @@ enum cputype { CPU_F11H, CPU_F12H, CPU_F14H, + CPU_F15H, CPU_P4, CPU_NEHALEM, CPU_DUNNINGTON, Index: mcelog-1.0.1/amd.h =================================================================== --- mcelog-1.0.1.orig/amd.h +++ mcelog-1.0.1/amd.h @@ -97,4 +97,5 @@ enum rrrr_ids { case CPU_F10H: \ case CPU_F11H: \ case CPU_F12H: \ - case CPU_F14H + case CPU_F14H: \ + case CPU_F15H Index: mcelog-1.0.1/mcelog.c =================================================================== --- mcelog-1.0.1.orig/mcelog.c +++ mcelog-1.0.1/mcelog.c @@ -226,6 +226,7 @@ static char *cputype_name[] = { [CPU_F11H] = "AMD Griffin", [CPU_F12H] = "AMD Llano", [CPU_F14H] = "AMD Bobcat", + [CPU_F15H] = "AMD Bulldozer", [CPU_P4] = "Intel P4", [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7 (\"Nehalem/Westmere\")", [CPU_DUNNINGTON] = "Intel Xeon 7400 series", @@ -248,6 +249,7 @@ static struct config_choice cpu_choices[ { "f11h", CPU_F11H }, { "f12h", CPU_F12H }, { "f14h", CPU_F14H }, + { "f15h", CPU_F15H }, { "p4", CPU_P4 }, { "dunnington", CPU_DUNNINGTON }, { "xeon74xx", CPU_DUNNINGTON }, ++++++ add-f16h-support.patch ++++++ Add F16h decoding support Signed-off-by: Borislav Petkov <[email protected]> Index: mcelog-1.0.1/amd.c =================================================================== --- mcelog-1.0.1.orig/amd.c +++ mcelog-1.0.1/amd.c @@ -200,6 +200,8 @@ enum cputype select_amd_cputype(u32 fami return CPU_F14H; case 0x15: return CPU_F15H; + case 0x16: + return CPU_F16H; default: break; } @@ -687,6 +689,47 @@ static bool f15h_mc2_mce(u16 ec, u8 xec) return ret; } +static bool f16h_mc2_mce(u16 ec, u8 xec) +{ + u8 r4 = R4(ec); + + if (!MEM_ERROR(ec)) + return false; + + switch (xec) { + case 0x04 ... 0x05: + Wprintf("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O'); + break; + + case 0x09 ... 0x0b: + case 0x0d ... 0x0f: + Wprintf("ECC error in L2 tag (%s).\n", + ((r4 == R4_GEN) ? "BankReq" : + ((r4 == R4_SNOOP) ? "Prb" : "Fill"))); + break; + + case 0x10 ... 0x19: + case 0x1b: + Wprintf("ECC error in L2 data array (%s).\n", + (((r4 == R4_RD) && !(xec & 0x3)) ? "Hit" : + ((r4 == R4_GEN) ? "Attr" : + ((r4 == R4_EVICT) ? "Vict" : "Fill")))); + break; + + case 0x1c ... 0x1d: + case 0x1f: + Wprintf("Parity error in L2 attribute bits (%s).\n", + ((r4 == R4_RD) ? "Hit" : + ((r4 == R4_GEN) ? "Attr" : "Fill"))); + break; + + default: + return false; + } + + return true; +} + static void decode_mc2_mce(struct amd_decoder_ops *ops, struct mce *m) { u16 ec = EC(m->status); @@ -897,6 +940,12 @@ struct amd_decoder_ops fam_ops[] = { .mc1_mce = f15h_mc1_mce, .mc2_mce = f15h_mc2_mce, }, + [AMD_F16H] = { + .cpu = AMD_F16H, + .mc0_mce = cat_mc0_mce, + .mc1_mce = cat_mc1_mce, + .mc2_mce = f16h_mc2_mce, + }, }; static void __decode_amd_mc(enum cputype cpu, struct mce *mce) @@ -920,6 +969,10 @@ static void __decode_amd_mc(enum cputype xec_mask = 0x1f; ops = &fam_ops[AMD_F15H]; break; + case CPU_F16H: + xec_mask = 0x1f; + ops = &fam_ops[AMD_F16H]; + break; default: Eprintf("Huh? What family is it: 0x%x?!\n", cpu); return; Index: mcelog-1.0.1/mcelog.h =================================================================== --- mcelog-1.0.1.orig/mcelog.h +++ mcelog-1.0.1/mcelog.h @@ -112,6 +112,7 @@ enum cputype { CPU_F12H, CPU_F14H, CPU_F15H, + CPU_F16H, CPU_P4, CPU_NEHALEM, CPU_DUNNINGTON, Index: mcelog-1.0.1/amd.h =================================================================== --- mcelog-1.0.1.orig/amd.h +++ mcelog-1.0.1/amd.h @@ -98,4 +98,5 @@ enum rrrr_ids { case CPU_F11H: \ case CPU_F12H: \ case CPU_F14H: \ - case CPU_F15H + case CPU_F15H: \ + case CPU_F16H Index: mcelog-1.0.1/mcelog.c =================================================================== --- mcelog-1.0.1.orig/mcelog.c +++ mcelog-1.0.1/mcelog.c @@ -227,6 +227,7 @@ static char *cputype_name[] = { [CPU_F12H] = "AMD Llano", [CPU_F14H] = "AMD Bobcat", [CPU_F15H] = "AMD Bulldozer", + [CPU_F16H] = "AMD Jaguar", [CPU_P4] = "Intel P4", [CPU_NEHALEM] = "Intel Xeon 5500 series / Core i3/5/7 (\"Nehalem/Westmere\")", [CPU_DUNNINGTON] = "Intel Xeon 7400 series", @@ -250,6 +251,7 @@ static struct config_choice cpu_choices[ { "f12h", CPU_F12H }, { "f14h", CPU_F14H }, { "f15h", CPU_F15H }, + { "f16h", CPU_F16H }, { "p4", CPU_P4 }, { "dunnington", CPU_DUNNINGTON }, { "xeon74xx", CPU_DUNNINGTON }, ++++++ mcelog.systemd ++++++ --- /var/tmp/diff_new_pack.v3jhD2/_old 2014-05-18 06:50:15.000000000 +0200 +++ /var/tmp/diff_new_pack.v3jhD2/_new 2014-05-18 06:50:15.000000000 +0200 @@ -4,7 +4,6 @@ [Service] EnvironmentFile=-/etc/sysconfig/mcelog -#warning: if this fails is due to a known kernel bug, fix that instead ! ExecStart=/usr/sbin/mcelog --ignorenodev --daemon --foreground StandardOutput=syslog -- To unsubscribe, e-mail: [email protected] For additional commands, e-mail: [email protected]
