Hello community, here is the log from the commit of package uhd for openSUSE:Factory checked in at 2014-10-29 21:10:27 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Comparing /work/SRC/openSUSE:Factory/uhd (Old) and /work/SRC/openSUSE:Factory/.uhd.new (New) ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Package is "uhd" Changes: -------- --- /work/SRC/openSUSE:Factory/uhd/uhd.changes 2014-09-05 13:00:17.000000000 +0200 +++ /work/SRC/openSUSE:Factory/.uhd.new/uhd.changes 2014-10-29 21:11:25.000000000 +0100 @@ -1,0 +2,6 @@ +Thu Oct 23 19:51:56 UTC 2014 - [email protected] + +- Update to version 3.7.3 + * firmware images are from 3.7.2 + +------------------------------------------------------------------- Old: ---- uhd-source_003.007.002-release.tar.gz New: ---- uhd-source_003.007.003-release.tar.gz ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Other differences: ------------------ ++++++ uhd.spec ++++++ --- /var/tmp/diff_new_pack.xbc8Pn/_old 2014-10-29 21:11:26.000000000 +0100 +++ /var/tmp/diff_new_pack.xbc8Pn/_new 2014-10-29 21:11:26.000000000 +0100 @@ -18,15 +18,16 @@ Name: uhd %define libname libuhd003 -Version: 3.7.2 +Version: 3.7.3 Release: 0 -%define src_ver 003.007.002 +%define src_ver 003.007.003 +%define img_ver 003.007.002 Summary: The driver for USRP SDR boards License: GPL-3.0+ Group: Hardware/Other Url: http://ettus-apps.sourcerepo.com/redmine/ettus/projects/uhd/wiki Source0: http://files.ettus.com/binaries/uhd_stable/uhd_%{src_ver}-release/uhd-source_%{src_ver}-release.tar.gz -Source1: http://files.ettus.com/binaries/uhd_stable/uhd_%{src_ver}-release/uhd-images_%{src_ver}-release.tar.gz +Source1: http://files.ettus.com/binaries/uhd_stable/uhd_%{img_ver}-release/uhd-images_%{img_ver}-release.tar.gz BuildRequires: boost-devel >= 1.36 BuildRequires: cmake >= 2.6 BuildRequires: docutils @@ -150,7 +151,7 @@ # extract firmware mkdir -p %{buildroot}%{_datadir}/uhd -tar -xzvf %{SOURCE1} --transform="s,^uhd-images_%{src_ver}-release/share/uhd/,," --show-transformed-names -C %{buildroot}%{_datadir}/uhd +tar -xzvf %{SOURCE1} --transform="s,^uhd-images_%{img_ver}-release/share/uhd/,," --show-transformed-names -C %{buildroot}%{_datadir}/uhd # find dupes %fdupes -s %{buildroot}%{_bindir} ++++++ uhd-source_003.007.002-release.tar.gz -> uhd-source_003.007.003-release.tar.gz ++++++ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/CMakeLists.txt new/uhd-source_003.007.003-release/CMakeLists.txt --- old/uhd-source_003.007.002-release/CMakeLists.txt 2014-08-21 00:18:48.000000000 +0200 +++ new/uhd-source_003.007.003-release/CMakeLists.txt 2014-05-18 21:21:52.000000000 +0200 @@ -209,9 +209,8 @@ ######################################################################## # Images download directory for utils/uhd_images_downloader.py ######################################################################## - -SET(UHD_IMAGES_MD5SUM "1e92df755dd71575ac238cd8bea3ea21") -SET(UHD_IMAGES_DOWNLOAD_SRC "http://files.ettus.com/binaries/maint_images/archive/uhd-images_003.007.002-release.zip";) +SET(UHD_IMAGES_MD5SUM "b1e06e7d6fe3eacf49d16e2acca98275") +SET(UHD_IMAGES_DOWNLOAD_SRC "http://files.ettus.com/binaries/maint_images/archive/uhd-images_003.007.003-release.zip";) ######################################################################## # Register top level components diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/cmake/Modules/UHDVersion.cmake new/uhd-source_003.007.003-release/cmake/Modules/UHDVersion.cmake --- old/uhd-source_003.007.002-release/cmake/Modules/UHDVersion.cmake 2014-07-23 16:09:00.000000000 +0200 +++ new/uhd-source_003.007.003-release/cmake/Modules/UHDVersion.cmake 2014-05-18 21:21:52.000000000 +0200 @@ -27,7 +27,7 @@ ######################################################################## SET(UHD_VERSION_MAJOR 003) SET(UHD_VERSION_MINOR 007) -SET(UHD_VERSION_PATCH 002) +SET(UHD_VERSION_PATCH 003) ######################################################################## # Set up trimmed version numbers for DLL resource files and packages diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/docs/images.rst new/uhd-source_003.007.003-release/docs/images.rst --- old/uhd-source_003.007.002-release/docs/images.rst 2014-03-17 14:44:08.000000000 +0100 +++ new/uhd-source_003.007.003-release/docs/images.rst 2014-05-18 21:21:52.000000000 +0200 @@ -1,12 +1,12 @@ -======================================================================== +=============================================== UHD - Firmware and FPGA Image Application Notes -======================================================================== +=============================================== .. contents:: Table of Contents ------------------------------------------------------------------------- +--------------- Images Overview ------------------------------------------------------------------------- +--------------- Every USRP device must be loaded with special firmware and FPGA images. The methods of loading images into the device vary among devices: @@ -19,9 +19,9 @@ * **USRP-X Series:** The user programs an image into on-board storage, which then is automatically loaded at runtime. ------------------------------------------------------------------------- +---------------- Pre-built Images ------------------------------------------------------------------------- +---------------- Pre-built images are available for download. @@ -33,9 +33,9 @@ * bundled with UHD software in a platform-specific installer * stand-alone platform-independent archive files -^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^^^^ UHD Images Downloader -^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^^^^ The UHD images downloader downloads UHD images compatible with the host code and places them in the default images directory. @@ -44,16 +44,16 @@ By default, it installs images to: **<install-path>/share/uhd/images** -^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^^ Platform installers -^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^^ The UNIX-based installers will install the images into **/usr/share/uhd/images**. The Windows installers will install the images into **C:/Program Files/UHD/share/uhd/images**. -^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^ Archive install -^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^ When installing images from an archive, there are two options: **Option 1:** @@ -67,18 +67,18 @@ Unpack the archive anywhere and set the **UHD_IMAGES_PATH** environment variable. **UHD_IMAGES_PATH** may contain a list of directories to search for image files. ------------------------------------------------------------------------- +--------------- Building Images ------------------------------------------------------------------------- +--------------- The UHD source repository comes with the source code necessary to build both firmware and FPGA images for all supported devices. The build commands for a particular image can be found in **<uhd-repo-path>/images/Makefile**. -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^ Xilinx FPGA builds -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^ USRP Xilinx FPGA images are built with two different versions of ISE, depending on the device. @@ -86,40 +86,40 @@ Make sure that **xtclsh** from the Xilinx ISE bin directory is in your **$PATH**. -**Xilinx ISE 14.4** +**Xilinx ISE 14.7** * USRP X3x0 Series +* USRP B2x0 See **<uhd-repo-path>/fpga/usrp3/top/**. **Xilinx ISE 12.2** * USRP N2x0 -* USRP B2x0 * USRP B1x0 * USRP E1x0 * USRP2 See **<uhd-repo-path>/fpga/usrp2/top/**. -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^^ ZPU firmware builds -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^^ The ZPU GCC compiler is required to build the ZPU firmware images. The build requires that you have a UNIX-like environment with **CMake** and **Make**. Make sure that **zpu-elf-gcc** is in your **$PATH**. See **<uhd-repo-path>/firmware/zpu**. -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^ Altera FPGA builds -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^ Quartus is required to build the Altera FPGA image for the USRP1. Pre-built images can also be found in **<uhd-repo-path>/fpga/usrp1/rbf**. See **<uhd-repo-path>/fpga/usrp1/toplevel/***. -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^^ FX2 firmware builds -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +^^^^^^^^^^^^^^^^^^^ The SDCC compiler is required to build the FX2 firmware images. The build requires that you have a UNIX-like environment with **CMake** and **Make**. diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/examples/rx_samples_to_file.cpp new/uhd-source_003.007.003-release/examples/rx_samples_to_file.cpp --- old/uhd-source_003.007.002-release/examples/rx_samples_to_file.cpp 2014-08-28 16:55:25.000000000 +0200 +++ new/uhd-source_003.007.003-release/examples/rx_samples_to_file.cpp 2014-05-18 21:21:52.000000000 +0200 @@ -140,6 +140,9 @@ break; } } + + stream_cmd.stream_mode = uhd::stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS; + rx_stream->issue_stream_cmd(stream_cmd); if (outfile.is_open()) outfile.close(); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/include/uhd/property_tree.hpp new/uhd-source_003.007.003-release/include/uhd/property_tree.hpp --- old/uhd-source_003.007.002-release/include/uhd/property_tree.hpp 2014-08-11 17:15:56.000000000 +0200 +++ new/uhd-source_003.007.003-release/include/uhd/property_tree.hpp 2014-05-18 21:21:52.000000000 +0200 @@ -113,6 +113,7 @@ }; UHD_API fs_path operator/(const fs_path &, const fs_path &); +UHD_API fs_path operator/(const fs_path &, size_t); /*! * The property tree provides a file system structure for accessing properties. diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/include/uhd/utils/log.hpp new/uhd-source_003.007.003-release/include/uhd/utils/log.hpp --- old/uhd-source_003.007.002-release/include/uhd/utils/log.hpp 2014-03-17 14:44:08.000000000 +0100 +++ new/uhd-source_003.007.003-release/include/uhd/utils/log.hpp 2014-05-18 21:21:52.000000000 +0200 @@ -21,8 +21,10 @@ #include <uhd/config.hpp> #include <uhd/utils/pimpl.hpp> #include <boost/current_function.hpp> +#include <boost/format.hpp> #include <ostream> #include <string> +#include <sstream> /*! \file log.hpp * The UHD logging facility. @@ -55,7 +57,7 @@ * Usage: UHD_LOGV(very_rarely) << "the log message" << std::endl; */ #define UHD_LOGV(verbosity) \ - uhd::_log::log(uhd::_log::verbosity, __FILE__, __LINE__, BOOST_CURRENT_FUNCTION)() + uhd::_log::log(uhd::_log::verbosity, __FILE__, __LINE__, BOOST_CURRENT_FUNCTION) /*! * A UHD logger macro with default verbosity. @@ -78,7 +80,7 @@ }; //! Internal logging object (called by UHD_LOG macros) - class UHD_API log{ + class UHD_API log { public: log( const verbosity_t verbosity, @@ -86,10 +88,29 @@ const unsigned int line, const std::string &function ); + ~log(void); - std::ostream &operator()(void); + + // Macro for overloading insertion operators to avoid costly + // conversion of types if not logging. + #define INSERTION_OVERLOAD(x) log& operator<< (x) \ + { \ + if(_log_it) _ss << val; \ + return *this; \ + } + + // General insertion overload + template <typename T> + INSERTION_OVERLOAD(T val); + + // Insertion overloads for std::ostream manipulators + INSERTION_OVERLOAD(std::ostream& (*val)(std::ostream&)); + INSERTION_OVERLOAD(std::ios& (*val)(std::ios&)); + INSERTION_OVERLOAD(std::ios_base& (*val)(std::ios_base&)); + private: - UHD_PIMPL_DECL(impl) _impl; + std::ostringstream _ss; + bool _log_it; }; }} //namespace uhd::_log diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/lib/property_tree.cpp new/uhd-source_003.007.003-release/lib/property_tree.cpp --- old/uhd-source_003.007.002-release/lib/property_tree.cpp 2014-03-17 14:44:08.000000000 +0100 +++ new/uhd-source_003.007.003-release/lib/property_tree.cpp 2014-05-18 21:21:52.000000000 +0200 @@ -65,6 +65,12 @@ return fs_path(lhs + "/" + rhs); } +fs_path uhd::operator/(const fs_path &lhs, size_t rhs) +{ + fs_path rhs_str = boost::lexical_cast<std::string>(rhs); + return lhs / rhs_str; +} + /*********************************************************************** * Property tree implementation **********************************************************************/ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/lib/usrp/b200/b200_impl.cpp new/uhd-source_003.007.003-release/lib/usrp/b200/b200_impl.cpp --- old/uhd-source_003.007.002-release/lib/usrp/b200/b200_impl.cpp 2014-08-18 23:11:10.000000000 +0200 +++ new/uhd-source_003.007.003-release/lib/usrp/b200/b200_impl.cpp 2014-05-18 21:21:52.000000000 +0200 @@ -123,6 +123,21 @@ new_addr["type"] = "b200"; new_addr["name"] = mb_eeprom["name"]; new_addr["serial"] = handle->get_serial(); + if (not mb_eeprom["product"].empty()) + { + switch (boost::lexical_cast<boost::uint16_t>(mb_eeprom["product"])) + { + case 0x0001: + case 0x7737: + new_addr["product"] = "B200"; + break; + case 0x7738: + case 0x0002: + new_addr["product"] = "B210"; + break; + default: UHD_MSG(error) << "B200 unknown product code: " << mb_eeprom["product"] << std::endl; + } + } //this is a found b200 when the hint serial and name match or blank if ( (not hint.has_key("name") or hint["name"] == new_addr["name"]) and @@ -304,7 +319,6 @@ } else { - UHD_MSG(status) << "not found" << std::endl; _local_ctrl->poke32(TOREG(SR_CORE_GPSDO_ST), B200_GPSDO_ST_NONE); } } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/lib/usrp/cores/radio_ctrl_core_3000.cpp new/uhd-source_003.007.003-release/lib/usrp/cores/radio_ctrl_core_3000.cpp --- old/uhd-source_003.007.002-release/lib/usrp/cores/radio_ctrl_core_3000.cpp 2014-03-17 14:44:09.000000000 +0100 +++ new/uhd-source_003.007.003-release/lib/usrp/cores/radio_ctrl_core_3000.cpp 2014-05-18 21:21:52.000000000 +0200 @@ -52,7 +52,6 @@ ACK_TIMEOUT), _resp_queue(128/*max response msgs*/), _resp_queue_size( _resp_xport ? _resp_xport->get_num_recv_frames() : 3) { - UHD_LOG<< "radio_ctrl_core_3000_impl() " << _name << std::endl; if (resp_xport) { while (resp_xport->get_recv_buff(0.0)) {} //flush @@ -63,7 +62,6 @@ ~radio_ctrl_core_3000_impl(void) { - UHD_LOG << "~radio_ctrl_core_3000_impl() " << _name << std::endl; _timeout = ACK_TIMEOUT; //reset timeout to something small UHD_SAFE_CALL( this->peek32(0);//dummy peek with the purpose of ack'ing all packets @@ -77,8 +75,6 @@ void poke32(const wb_addr_type addr, const boost::uint32_t data) { boost::mutex::scoped_lock lock(_mutex); - UHD_LOGV(always) << _name << std::hex << " addr 0x" << addr << " data 0x" << data << std::dec << std::endl; - this->send_pkt(addr/4, data); this->wait_for_ack(false); } @@ -86,7 +82,6 @@ boost::uint32_t peek32(const wb_addr_type addr) { boost::mutex::scoped_lock lock(_mutex); - UHD_LOGV(always) << _name << std::hex << " addr 0x" << addr << std::dec << std::endl; this->send_pkt(SR_READBACK, addr/8); const boost::uint64_t res = this->wait_for_ack(true); const boost::uint32_t lo = boost::uint32_t(res & 0xffffffff); @@ -97,8 +92,6 @@ boost::uint64_t peek64(const wb_addr_type addr) { boost::mutex::scoped_lock lock(_mutex); - UHD_LOGV(always) << _name << std::hex << " addr 0x" << addr << std::dec << std::endl; - this->send_pkt(SR_READBACK, addr/8); return this->wait_for_ack(true); } @@ -174,7 +167,6 @@ { while (readback or (_outstanding_seqs.size() >= _resp_queue_size)) { - UHD_LOGV(always) << _name << " wait_for_ack: " << "readback = " << readback << " outstanding_seqs.size() " << _outstanding_seqs.size() << std::endl; //get seq to ack from outstanding packets list UHD_ASSERT_THROW(not _outstanding_seqs.empty()); const size_t seq_to_ack = _outstanding_seqs.front(); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/lib/usrp/dboard/db_cbx.cpp new/uhd-source_003.007.003-release/lib/usrp/dboard/db_cbx.cpp --- old/uhd-source_003.007.002-release/lib/usrp/dboard/db_cbx.cpp 2014-08-11 17:15:56.000000000 +0200 +++ new/uhd-source_003.007.003-release/lib/usrp/dboard/db_cbx.cpp 2014-05-18 21:21:52.000000000 +0200 @@ -19,6 +19,7 @@ #include "max2870_regs.hpp" #include "db_sbx_common.hpp" #include <boost/algorithm/string.hpp> +#include <boost/math/special_functions/round.hpp> using namespace uhd; using namespace uhd::usrp; @@ -94,10 +95,10 @@ vco_freq *= 2; RFdiv *= 2; } - + /* * The goal here is to loop though possible R dividers, - * band select clock dividers, N (int) dividers, and FRAC + * band select clock dividers, N (int) dividers, and FRAC * (frac) dividers. * * Calculate the N and F dividers for each set of values. @@ -122,7 +123,7 @@ N = int(vco_freq/pfd_freq); //Fractional-N calculation - FRAC = int((vco_freq/pfd_freq - N)*MOD); + FRAC = int(boost::math::round((vco_freq/pfd_freq - N)*MOD)); if(is_int_n) { if (FRAC > (MOD / 2)) { //Round integer such that actual freq is closest to target @@ -197,7 +198,8 @@ regs.r_counter_10_bit = R; regs.reference_divide_by_2 = T; regs.reference_doubler = D; - regs.band_select_clock_div = BS; + regs.band_select_clock_div = (BS & 0x0FF); + regs.bs_msb = (BS & 0x300) >>8; UHD_ASSERT_THROW(rfdivsel_to_enum.has_key(RFdiv)); regs.rf_divider_select = rfdivsel_to_enum[RFdiv]; regs.int_n_mode = (is_int_n) ? max2870_regs_t::INT_N_MODE_INT_N : max2870_regs_t::INT_N_MODE_FRAC_N; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/lib/usrp/dboard/db_sbx_common.cpp new/uhd-source_003.007.003-release/lib/usrp/dboard/db_sbx_common.cpp --- old/uhd-source_003.007.002-release/lib/usrp/dboard/db_sbx_common.cpp 2014-08-11 17:15:56.000000000 +0200 +++ new/uhd-source_003.007.003-release/lib/usrp/dboard/db_sbx_common.cpp 2014-05-18 21:21:52.000000000 +0200 @@ -54,7 +54,7 @@ int iobits = ((~attn_code) << RX_ATTN_SHIFT) & RX_ATTN_MASK; UHD_LOGV(often) << boost::format( - "SBX TX Attenuation: %f dB, Code: %d, IO Bits %x, Mask: %x" + "SBX RX Attenuation: %f dB, Code: %d, IO Bits %x, Mask: %x" ) % attn % attn_code % (iobits & RX_ATTN_MASK) % RX_ATTN_MASK << std::endl; //the actual gain setting diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/lib/usrp/e100/e100_impl.cpp new/uhd-source_003.007.003-release/lib/usrp/e100/e100_impl.cpp --- old/uhd-source_003.007.002-release/lib/usrp/e100/e100_impl.cpp 2014-03-17 14:44:09.000000000 +0100 +++ new/uhd-source_003.007.003-release/lib/usrp/e100/e100_impl.cpp 2014-05-18 21:21:52.000000000 +0200 @@ -1,5 +1,5 @@ // -// Copyright 2010-2012 Ettus Research LLC +// Copyright 2010-2012,2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -259,7 +259,6 @@ } if (_gps and _gps->gps_detected()) { - UHD_MSG(status) << "found" << std::endl; BOOST_FOREACH(const std::string &name, _gps->get_sensors()) { _tree->create<sensor_value_t>(mb_path / "sensors" / name) @@ -268,7 +267,6 @@ } else { - UHD_MSG(status) << "not found" << std::endl; std::ofstream(GPSDO_VOLATILE_PATH.string().c_str(), std::ofstream::binary) << "42" << std::endl; } } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/lib/usrp/usrp2/usrp2_impl.cpp new/uhd-source_003.007.003-release/lib/usrp/usrp2/usrp2_impl.cpp --- old/uhd-source_003.007.002-release/lib/usrp/usrp2/usrp2_impl.cpp 2014-08-18 23:11:10.000000000 +0200 +++ new/uhd-source_003.007.003-release/lib/usrp/usrp2/usrp2_impl.cpp 2014-05-18 21:21:52.000000000 +0200 @@ -523,7 +523,6 @@ } if (_mbc[mb].gps and _mbc[mb].gps->gps_detected()) { - UHD_MSG(status) << "found" << std::endl; BOOST_FOREACH(const std::string &name, _mbc[mb].gps->get_sensors()) { _tree->create<sensor_value_t>(mb_path / "sensors" / name) @@ -532,7 +531,6 @@ } else { - UHD_MSG(status) << "not found" << std::endl; _mbc[mb].iface->pokefw(U2_FW_REG_HAS_GPSDO, dont_look_for_gpsdo); } } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/lib/usrp/x300/x300_adc_ctrl.cpp new/uhd-source_003.007.003-release/lib/usrp/x300/x300_adc_ctrl.cpp --- old/uhd-source_003.007.002-release/lib/usrp/x300/x300_adc_ctrl.cpp 2014-03-17 14:44:09.000000000 +0100 +++ new/uhd-source_003.007.003-release/lib/usrp/x300/x300_adc_ctrl.cpp 2014-05-18 21:21:52.000000000 +0200 @@ -1,5 +1,5 @@ // -// Copyright 2010-2013 Ettus Research LLC +// Copyright 2010-2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -34,6 +34,11 @@ x300_adc_ctrl_impl(uhd::spi_iface::sptr iface, const size_t slaveno): _iface(iface), _slaveno(slaveno) { + init(); + } + + void init() + { //power-up adc _ads62p48_regs.reset = 1; this->send_ads62p48_reg(0x00); //issue a reset to the ADC @@ -46,8 +51,8 @@ _ads62p48_regs.lvds_cmos = ads62p48_regs_t::LVDS_CMOS_DDR_LVDS; _ads62p48_regs.channel_control = ads62p48_regs_t::CHANNEL_CONTROL_INDEPENDENT; _ads62p48_regs.data_format = ads62p48_regs_t::DATA_FORMAT_2S_COMPLIMENT; - _ads62p48_regs.clk_out_pos_edge = ads62p48_regs_t::CLK_OUT_POS_EDGE_MINUS7_26; - _ads62p48_regs.clk_out_neg_edge = ads62p48_regs_t::CLK_OUT_NEG_EDGE_MINUS7_26; + _ads62p48_regs.clk_out_pos_edge = ads62p48_regs_t::CLK_OUT_POS_EDGE_MINUS7_26; + _ads62p48_regs.clk_out_neg_edge = ads62p48_regs_t::CLK_OUT_NEG_EDGE_MINUS7_26; this->send_ads62p48_reg(0); @@ -72,6 +77,11 @@ } + void reset() + { + init(); + } + double set_gain(const double &gain) { const meta_range_t gain_range = meta_range_t(0, 6.0, 0.5); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/lib/usrp/x300/x300_adc_ctrl.hpp new/uhd-source_003.007.003-release/lib/usrp/x300/x300_adc_ctrl.hpp --- old/uhd-source_003.007.002-release/lib/usrp/x300/x300_adc_ctrl.hpp 2014-08-11 17:15:56.000000000 +0200 +++ new/uhd-source_003.007.003-release/lib/usrp/x300/x300_adc_ctrl.hpp 2014-05-18 21:21:52.000000000 +0200 @@ -1,5 +1,5 @@ // -// Copyright 2010-2013 Ettus Research LLC +// Copyright 2010-2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -39,6 +39,7 @@ virtual void set_test_word(const std::string &patterna, const std::string &patternb, const boost::uint32_t = 0) = 0; + virtual void reset(void) = 0; }; #endif /* INCLUDED_X300_ADC_CTRL_HPP */ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/lib/usrp/x300/x300_clock_ctrl.cpp new/uhd-source_003.007.003-release/lib/usrp/x300/x300_clock_ctrl.cpp --- old/uhd-source_003.007.002-release/lib/usrp/x300/x300_clock_ctrl.cpp 2014-08-18 23:11:10.000000000 +0200 +++ new/uhd-source_003.007.003-release/lib/usrp/x300/x300_clock_ctrl.cpp 2014-05-18 21:21:52.000000000 +0200 @@ -295,8 +295,6 @@ // Register 3 _lmk04816_regs.CLKout6_7_DIV = vco_div; _lmk04816_regs.CLKout6_7_OSCin_Sel = lmk04816_regs_t::CLKOUT6_7_OSCIN_SEL_VCO; - _lmk04816_regs.CLKout6_ADLY_SEL = lmk04816_regs_t::CLKOUT6_ADLY_SEL_D_EV_X; - _lmk04816_regs.CLKout7_ADLY_SEL = lmk04816_regs_t::CLKOUT7_ADLY_SEL_D_EV_X; // Register 4 _lmk04816_regs.CLKout8_9_DIV = vco_div; // Register 5 @@ -318,9 +316,6 @@ _lmk04816_regs.CLKout6_TYPE = lmk04816_regs_t::CLKOUT6_TYPE_LVPECL_700MVPP; //DB0_DAC _lmk04816_regs.CLKout7_TYPE = lmk04816_regs_t::CLKOUT7_TYPE_LVPECL_700MVPP; //DB1_DAC _lmk04816_regs.CLKout8_TYPE = lmk04816_regs_t::CLKOUT8_TYPE_LVPECL_700MVPP; //DB0_ADC - // Analog delay of 900ps to synchronize the DAC reference clocks with the source synchronous DAC clocks. - // This delay may need to vary due to temperature. Tested and verified at room temperature only. - _lmk04816_regs.CLKout6_7_ADLY = 0x10; // Register 8 _lmk04816_regs.CLKout9_TYPE = lmk04816_regs_t::CLKOUT9_TYPE_LVPECL_700MVPP; //DB1_ADC @@ -340,6 +335,7 @@ _lmk04816_regs.NO_SYNC_CLKout0_1 = lmk04816_regs_t::NO_SYNC_CLKOUT0_1_CLOCK_XY_SYNC; _lmk04816_regs.NO_SYNC_CLKout2_3 = lmk04816_regs_t::NO_SYNC_CLKOUT2_3_CLOCK_XY_SYNC; _lmk04816_regs.NO_SYNC_CLKout4_5 = lmk04816_regs_t::NO_SYNC_CLKOUT4_5_CLOCK_XY_SYNC; + _lmk04816_regs.NO_SYNC_CLKout6_7 = lmk04816_regs_t::NO_SYNC_CLKOUT6_7_CLOCK_XY_SYNC; _lmk04816_regs.NO_SYNC_CLKout8_9 = lmk04816_regs_t::NO_SYNC_CLKOUT8_9_CLOCK_XY_SYNC; _lmk04816_regs.NO_SYNC_CLKout10_11 = lmk04816_regs_t::NO_SYNC_CLKOUT10_11_CLOCK_XY_SYNC; _lmk04816_regs.SYNC_EN_AUTO = lmk04816_regs_t::SYNC_EN_AUTO_SYNC_INT_GEN; diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/lib/usrp/x300/x300_dac_ctrl.cpp new/uhd-source_003.007.003-release/lib/usrp/x300/x300_dac_ctrl.cpp --- old/uhd-source_003.007.002-release/lib/usrp/x300/x300_dac_ctrl.cpp 2014-03-17 14:44:09.000000000 +0100 +++ new/uhd-source_003.007.003-release/lib/usrp/x300/x300_dac_ctrl.cpp 2014-05-18 21:21:52.000000000 +0200 @@ -1,5 +1,5 @@ // -// Copyright 2010-2013 Ettus Research LLC +// Copyright 2010-2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -39,7 +39,13 @@ { public: x300_dac_ctrl_impl(uhd::spi_iface::sptr iface, const size_t slaveno, const double refclk): - _iface(iface), _slaveno(slaveno) + _iface(iface), _slaveno(slaveno), _refclk(refclk) + { + init(); + check_pll(); + } + + void init() { write_ad9146_reg(0x00, 0x20); // Take DAC into reset. write_ad9146_reg(0x00, 0x80); // Enable SPI reads and come out of reset @@ -47,43 +53,31 @@ // Calculate N0 to be VCO friendly. // Aim for VCO between 1 and 2GHz, assert otherwise. - // const int N1 = 4; - const int N1 = 4; + // const int N1 = 4; + const int N1 = 4; int N0_val, N0; for (N0_val = 0; N0_val < 3; N0_val++) { N0 = (1 << N0_val); //1, 2, 4 - if ((refclk * N0 * N1) >= 1e9) break; + if ((_refclk * N0 * N1) >= 1e9) break; } - UHD_ASSERT_THROW((refclk * N0 * N1) >= 1e9); - UHD_ASSERT_THROW((refclk * N0 * N1) <= 2e9); + UHD_ASSERT_THROW((_refclk * N0 * N1) >= 1e9); + UHD_ASSERT_THROW((_refclk * N0 * N1) <= 2e9); /* Start PLL */ //write_ad9146_reg(0x0C, 0xD1); // Narrow PLL loop filter, Midrange charge pump. write_ad9146_reg(0x0D, 0xD1 | (N0_val << 2)); // N1=4, N2=16, N0 as calculated - //write_ad9146_reg(0x0D, 0x90 | (N0_val << 2)); // N1=2, N2=8, N0 as calculated + //write_ad9146_reg(0x0D, 0x90 | (N0_val << 2)); // N1=2, N2=8, N0 as calculated write_ad9146_reg(0x0A, 0xCF); // Auto init VCO band training as per datasheet write_ad9146_reg(0x0A, 0xA0); // See above. - // Verify PLL is Locked. 1 sec timeout. - // NOTE: Data sheet inconsistant about which pins give PLL lock status. FIXME! - const time_spec_t exit_time = time_spec_t::get_system_time() + time_spec_t(1.0); - while (true) - { - const size_t reg_e = read_ad9146_reg(0x0E); /* Expect bit 7 = 1 */ - if ((exit_time < time_spec_t::get_system_time()) && ((reg_e & (1 << 7)) == 0)) - throw uhd::runtime_error("x300_dac_ctrl: timeout waiting for DAC PLL to lock"); - else if ((reg_e & ((1 << 7) | (1 << 6))) != 0) break; - boost::this_thread::sleep(boost::posix_time::milliseconds(10)); - } - /* Skew DCI signal to find stable data eye */ //write_ad9146_reg(0x16, 0x04); //Disable delay in DCI //write_ad9146_reg(0x16, 0x00); //165ps delay in DCI //write_ad9146_reg(0x16, 0x01); //375ps delay in DCI write_ad9146_reg(0x16, 0x02); //615ps delay in DCI //write_ad9146_reg(0x16, 0x03); //720ps delay in DCI - + write_ad9146_reg(0x03, 0x00); // 2's comp, I first, byte wide interface //fpga wants I,Q in the sample word: @@ -93,7 +87,14 @@ write_ad9146_reg(0x03, (1 << 6)); //2s comp, i first, byte mode write_ad9146_reg(0x10, 0x48); // Disable SYNC mode. - write_ad9146_reg(0x17, 0x04); // FIFO write pointer offset + + // FIFO write pointer offset + // It was found that the read was happening before the write + // so the FIFO was maintainining a depth of 3 during operation. + // Setting it to 5 to ensure it maintains the ideal depth of 4. + // TODO: Investigate RefClk -> DCI clock timing. + write_ad9146_reg(0x17, 0x05); + write_ad9146_reg(0x18, 0x02); // Request soft FIFO align write_ad9146_reg(0x18, 0x00); // (See above) write_ad9146_reg(0x1B, 0xE4); // Bypass: Modulator, InvSinc, IQ Bal @@ -102,6 +103,8 @@ write_ad9146_reg(0x1C, 0x00); // Configure HB1 write_ad9146_reg(0x1D, 0x00); // Configure HB2 + // Clear event flags + write_ad9146_reg(0x06, 0xFF); } @@ -114,27 +117,71 @@ ) } - void arm_dac_sync(void) - { - // - // Attempt to synchronize AD9146's - // - write_ad9146_reg(0x10, 0xCF); // Enable SYNC mode. Sync Averaging set to 128. - - const time_spec_t exit_time = time_spec_t::get_system_time() + time_spec_t(1.0); - while (true) - { - const size_t reg_12 = read_ad9146_reg(0x12); /* Expect bit 7 = 0, bit 6 = 1 */ - if ((exit_time < time_spec_t::get_system_time()) && (((reg_12 & (1 << 6)) == 0) || ((reg_12 & (1 << 7)) != 0))) - throw uhd::runtime_error("x300_dac_ctrl: timeout waiting for backend synchronization"); - else if (((reg_12 & (1 << 6)) != 0) && ((reg_12 & (1 << 7)) == 0)) break; - boost::this_thread::sleep(boost::posix_time::milliseconds(10)); - } - } + void arm_dac_sync(void) + { + // + // Attempt to synchronize AD9146's + // + write_ad9146_reg(0x10, 0x48); // Disable SYNC mode. + write_ad9146_reg(0x06, 0x30); // Clear Sync event flags + write_ad9146_reg(0x10, 0xCF); // Enable SYNC mode. Sync Averaging set to 128. + } + + void reset() + { + init(); + } + + void check_pll() + { + // Verify PLL is Locked. 1 sec timeout. + // NOTE: Data sheet inconsistant about which pins give PLL lock status. FIXME! + const time_spec_t exit_time = time_spec_t::get_system_time() + time_spec_t(1.0); + while (true) + { + const size_t reg_e = read_ad9146_reg(0x0E); // PLL Status (Expect bit 7 = 1) + const size_t reg_6 = read_ad9146_reg(0x06); // Event Flags (Expect bit 7 = 0 and bit 6 = 1) + if ((((reg_e >> 7) & 0x1) == 0x1) && (((reg_6 >> 6) & 0x3) == 0x1)) + break; + if (exit_time < time_spec_t::get_system_time()) + throw uhd::runtime_error("x300_dac_ctrl: timeout waiting for DAC PLL to lock"); + if (reg_6 & (1 << 7)) // Sync lost? + write_ad9146_reg(0x06, 0xC0); // Clear PLL event flags + boost::this_thread::sleep(boost::posix_time::milliseconds(10)); + } + } + + void check_dac_sync() + { + const time_spec_t exit_time = time_spec_t::get_system_time() + time_spec_t(1.0); + while (true) + { + boost::this_thread::sleep(boost::posix_time::milliseconds(1)); // wait for sync to complete + const size_t reg_12 = read_ad9146_reg(0x12); // Sync Status (Expect bit 7 = 0, bit 6 = 1) + const size_t reg_6 = read_ad9146_reg(0x06); // Event Flags (Expect bit 5 = 0 and bit 4 = 1) + if ((((reg_12 >> 6) & 0x3) == 0x1) && (((reg_6 >> 4) & 0x3) == 0x1)) + break; + if (exit_time < time_spec_t::get_system_time()) + throw uhd::runtime_error("x300_dac_ctrl: timeout waiting for backend synchronization"); + if (reg_12 & (1 << 7)) // Sync acquired and lost? + arm_dac_sync(); // Re-arm and try again + else if (reg_6 & (1 << 5)) + write_ad9146_reg(0x06, 0x30); // Clear Sync event flags + } + } + + void check_frontend_sync() + { + // Register 0x19 has a thermometer indicator of the FIFO depth + const size_t reg_19 = read_ad9146_reg(0x19); + if ((reg_19 & 0xFF) != 0xF) + UHD_MSG(warning) << "x300_dac_ctrl: unexpected FIFO depth [0x" << std::hex << (reg_19 & 0xFF) << std::dec << "]" << std::endl; + } private: uhd::spi_iface::sptr _iface; const size_t _slaveno; + const double _refclk; }; /*********************************************************************** diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/lib/usrp/x300/x300_dac_ctrl.hpp new/uhd-source_003.007.003-release/lib/usrp/x300/x300_dac_ctrl.hpp --- old/uhd-source_003.007.002-release/lib/usrp/x300/x300_dac_ctrl.hpp 2014-08-11 17:15:56.000000000 +0200 +++ new/uhd-source_003.007.003-release/lib/usrp/x300/x300_dac_ctrl.hpp 2014-05-18 21:21:52.000000000 +0200 @@ -1,5 +1,5 @@ // -// Copyright 2010-2013 Ettus Research LLC +// Copyright 2010-2014 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -37,6 +37,18 @@ // ! Arm the sync feature in DAC virtual void arm_dac_sync(void) = 0; + + // ! Check for successful backend sync + virtual void check_dac_sync(void) = 0; + + // ! Reset the DAC + virtual void reset(void) = 0; + + // ! Check for PLL lock + virtual void check_pll(void) = 0; + + // ! Check for successful frontend sync + virtual void check_frontend_sync(void) = 0; }; #endif /* INCLUDED_X300_DAC_CTRL_HPP */ diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/lib/usrp/x300/x300_dboard_iface.cpp new/uhd-source_003.007.003-release/lib/usrp/x300/x300_dboard_iface.cpp --- old/uhd-source_003.007.002-release/lib/usrp/x300/x300_dboard_iface.cpp 2014-03-17 14:44:09.000000000 +0100 +++ new/uhd-source_003.007.003-release/lib/usrp/x300/x300_dboard_iface.cpp 2014-05-18 21:21:52.000000000 +0200 @@ -180,7 +180,7 @@ } } -void x300_dboard_iface::set_clock_enabled(unit_t unit, bool enb) +void x300_dboard_iface::set_clock_enabled(UHD_UNUSED(unit_t unit), UHD_UNUSED(bool enb)) { // TODO Variable DBoard clock control needs to be implemented for X300. } diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/lib/usrp/x300/x300_impl.cpp new/uhd-source_003.007.003-release/lib/usrp/x300/x300_impl.cpp --- old/uhd-source_003.007.002-release/lib/usrp/x300/x300_impl.cpp 2014-08-18 23:11:10.000000000 +0200 +++ new/uhd-source_003.007.003-release/lib/usrp/x300/x300_impl.cpp 2014-05-18 21:21:52.000000000 +0200 @@ -735,6 +735,7 @@ // setup time sources and properties //////////////////////////////////////////////////////////////////// _tree->create<std::string>(mb_path / "time_source" / "value") + .set("internal") .subscribe(boost::bind(&x300_impl::update_time_source, this, boost::ref(mb), _1)); static const std::vector<std::string> time_sources = boost::assign::list_of("internal")("external")("gpsdo"); _tree->create<std::vector<std::string> >(mb_path / "time_source" / "options").set(time_sources); @@ -748,7 +749,10 @@ // setup clock sources and properties //////////////////////////////////////////////////////////////////// _tree->create<std::string>(mb_path / "clock_source" / "value") - .subscribe(boost::bind(&x300_impl::update_clock_source, this, boost::ref(mb), _1)); + .set("internal") + .subscribe(boost::bind(&x300_impl::update_clock_source, this, boost::ref(mb), _1)) + .subscribe(boost::bind(&x300_impl::reset_clocks, this, boost::ref(mb))) + .subscribe(boost::bind(&x300_impl::reset_radios, this, boost::ref(mb))); static const std::vector<std::string> clock_source_options = boost::assign::list_of("internal")("external")("gpsdo"); _tree->create<std::vector<std::string> >(mb_path / "clock_source" / "options").set(clock_source_options); @@ -825,15 +829,6 @@ const time_t tp = time_t(mb.gps->get_sensor("gps_time").to_int()+1); _tree->access<time_spec_t>(mb_path / "time" / "pps").set(time_spec_t(tp)); } else { - _tree->access<std::string>(mb_path / "clock_source" / "value").set("internal"); - try { - wait_for_ref_locked(mb.zpu_ctrl, 1.0); - } catch (uhd::exception::runtime_error &e) { - // Ignore for now - It can sometimes take longer than 1 second to lock and that is OK. - //UHD_MSG(warning) << "Clock reference failed to lock to internal source during device initialization. " << - // "Check for the lock before operation or ignore this warning if using another clock source." << std::endl; - } - _tree->access<std::string>(mb_path / "time_source" / "value").set("internal"); UHD_MSG(status) << "References initialized to internal sources" << std::endl; } } @@ -1395,6 +1390,51 @@ */ } +void x300_impl::reset_clocks(mboard_members_t &mb) +{ + mb.clock->reset_clocks(); + + if (mb.hw_rev > 4) + { + try { + wait_for_ref_locked(mb.zpu_ctrl, 30.0); + } catch (uhd::runtime_error &e) { + //failed to lock on reference + throw uhd::runtime_error((boost::format("PLL failed to lock to reference clock.")).str()); + } + } +} + +void x300_impl::reset_radios(mboard_members_t &mb) +{ + // reset ADCs and DACs + BOOST_FOREACH (radio_perifs_t& perif, mb.radio_perifs) + { + perif.adc->reset(); + perif.dac->reset(); + } + + // check PLL locks + BOOST_FOREACH (radio_perifs_t& perif, mb.radio_perifs) + { + perif.dac->check_pll(); + } + + // Sync DACs + BOOST_FOREACH (radio_perifs_t& perif, mb.radio_perifs) + { + perif.dac->arm_dac_sync(); + } + BOOST_FOREACH (radio_perifs_t& perif, mb.radio_perifs) + { + perif.dac->check_dac_sync(); + // Arm FRAMEP/N sync pulse + // TODO: Investigate timing of the sync frame pulse. + perif.ctrl->poke32(TOREG(SR_DACSYNC), 0x1); + perif.dac->check_frontend_sync(); + } +} + void x300_impl::update_time_source(mboard_members_t &mb, const std::string &source) { if (source == "internal") { diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/lib/usrp/x300/x300_impl.hpp new/uhd-source_003.007.003-release/lib/usrp/x300/x300_impl.hpp --- old/uhd-source_003.007.002-release/lib/usrp/x300/x300_impl.hpp 2014-07-28 16:26:20.000000000 +0200 +++ new/uhd-source_003.007.003-release/lib/usrp/x300/x300_impl.hpp 2014-05-18 21:21:52.000000000 +0200 @@ -343,6 +343,8 @@ void set_time_source_out(mboard_members_t&, const bool); void update_clock_source(mboard_members_t&, const std::string &); void update_time_source(mboard_members_t&, const std::string &); + void reset_clocks(mboard_members_t&); + void reset_radios(mboard_members_t&); uhd::sensor_value_t get_ref_locked(uhd::wb_iface::sptr); void wait_for_ref_locked(uhd::wb_iface::sptr, double timeout = 0.0); diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/lib/utils/log.cpp new/uhd-source_003.007.003-release/lib/utils/log.cpp --- old/uhd-source_003.007.002-release/lib/utils/log.cpp 2014-05-12 16:18:53.000000000 +0200 +++ new/uhd-source_003.007.003-release/lib/utils/log.cpp 2014-05-18 21:21:52.000000000 +0200 @@ -23,6 +23,7 @@ #include <boost/format.hpp> #include <boost/thread/mutex.hpp> #include <boost/date_time/posix_time/posix_time.hpp> +#include <boost/thread/locks.hpp> #ifdef BOOST_MSVC //whoops! https://svn.boost.org/trac/boost/ticket/5287 //enjoy this useless dummy class instead @@ -37,7 +38,6 @@ #include <boost/interprocess/sync/file_lock.hpp> #endif #include <fstream> -#include <sstream> #include <cctype> namespace fs = boost::filesystem; @@ -70,13 +70,13 @@ } ~log_resource_type(void){ - boost::mutex::scoped_lock lock(_mutex); + boost::lock_guard<boost::mutex> lock(_mutex); _file_stream.close(); if (_file_lock != NULL) delete _file_lock; } void log_to_file(const std::string &log_msg){ - boost::mutex::scoped_lock lock(_mutex); + boost::lock_guard<boost::mutex> lock(_mutex); if (_file_lock == NULL){ const std::string log_path = (fs::path(uhd::get_tmp_path()) / "uhd.log").string(); _file_stream.open(log_path.c_str(), std::fstream::out | std::fstream::app); @@ -126,39 +126,40 @@ return rel_path.string(); } -struct uhd::_log::log::impl{ - std::ostringstream ss; - verbosity_t verbosity; -}; uhd::_log::log::log( const verbosity_t verbosity, const std::string &file, const unsigned int line, const std::string &function -){ - _impl = UHD_PIMPL_MAKE(impl, ()); - _impl->verbosity = verbosity; - const std::string time = pt::to_simple_string(pt::microsec_clock::local_time()); - const std::string header1 = str(boost::format("-- %s - level %d") % time % int(verbosity)); - const std::string header2 = str(boost::format("-- %s") % function).substr(0, 80); - const std::string header3 = str(boost::format("-- %s:%u") % get_rel_file_path(file) % line); - const std::string border = std::string(std::max(std::max(header1.size(), header2.size()), header3.size()), '-'); - _impl->ss - << std::endl - << border << std::endl - << header1 << std::endl - << header2 << std::endl - << header3 << std::endl - << border << std::endl - ; + ) +{ + _log_it = (verbosity >= log_rs().level); + if (_log_it) + { + const std::string time = pt::to_simple_string(pt::microsec_clock::local_time()); + const std::string header1 = str(boost::format("-- %s - level %d") % time % int(verbosity)); + const std::string header2 = str(boost::format("-- %s") % function).substr(0, 80); + const std::string header3 = str(boost::format("-- %s:%u") % get_rel_file_path(file) % line); + const std::string border = std::string(std::max(std::max(header1.size(), header2.size()), header3.size()), '-'); + _ss << std::endl + << border << std::endl + << header1 << std::endl + << header2 << std::endl + << header3 << std::endl + << border << std::endl + ; + } } -uhd::_log::log::~log(void){ - if (_impl->verbosity < log_rs().level) return; - _impl->ss << std::endl; +uhd::_log::log::~log(void) +{ + if (not _log_it) + return; + + _ss << std::endl; try{ - log_rs().log_to_file(_impl->ss.str()); + log_rs().log_to_file(_ss.str()); } catch(const std::exception &e){ /*! @@ -174,7 +175,3 @@ ; } } - -std::ostream & uhd::_log::log::operator()(void){ - return _impl->ss; -} diff -urN '--exclude=CVS' '--exclude=.cvsignore' '--exclude=.svn' '--exclude=.svnignore' old/uhd-source_003.007.002-release/tests/property_test.cpp new/uhd-source_003.007.003-release/tests/property_test.cpp --- old/uhd-source_003.007.002-release/tests/property_test.cpp 2014-03-17 14:44:09.000000000 +0100 +++ new/uhd-source_003.007.003-release/tests/property_test.cpp 2014-05-18 21:21:52.000000000 +0200 @@ -173,3 +173,24 @@ BOOST_CHECK_EQUAL_COLLECTIONS(tree_dirs2.begin(), tree_dirs2.end(), subtree2_dirs.begin(), subtree2_dirs.end()); } + + +BOOST_AUTO_TEST_CASE(test_prop_operators) +{ + uhd::fs_path path1 = "/root/"; + path1 = path1 / "leaf"; + BOOST_CHECK_EQUAL(path1, "/root/leaf"); + + uhd::fs_path path2 = "/root"; + path2 = path2 / "leaf"; + BOOST_CHECK_EQUAL(path2, "/root/leaf"); + + uhd::fs_path path3 = "/root/"; + path3 = path3 / "/leaf/"; + BOOST_CHECK_EQUAL(path3, "/root/leaf/"); + + uhd::fs_path path4 = "/root/"; + size_t x = 2; + path4 = path4 / x; + BOOST_CHECK_EQUAL(path4, "/root/2"); +} -- To unsubscribe, e-mail: [email protected] For additional commands, e-mail: [email protected]
