Ken,
On Fri, Jul 3, 2009 at 10:01 PM, Kenneth Hoste<kenneth.ho...@ugent.be> wrote:
>
> On Jul 1, 2009, at 07:03 , stephane eranian wrote:
>
>> Kenneth,
>>
>> Let me check on this with Intel.
>
> Thanks! Any news yet?
>
I can confirm that the following events do indeed overcount on Intel Core i7:
- L1D_CACHE_LOCK : overcounts by 3x
- L1D_CACHE_LD : overcounts because "This event counts load
uops at dispatch. Consequently loads "
which are blocked and then
re-dispatched will be counted multiple times."
- L1D_CACHE_ST : overcounts for the same reason as L1D_CACHE_LD
For D-cache misses, it is recommended you use MEM_LOAD_RETIRED which
is what you did.
As for your approximation using this event, you may also want to add HIT_LFB.
I have not yet received confirmation about your initial posting about
L1I:MISSES but it is likely
it also overcounts.
Those issues are known but the SDM Vol3b has not yet been updated to
reflect them.
Thanks for your patience.
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