Ventana's Veyron CPUs support sdtrig ISA extension. By default, enable the sdtrig extension and disable the debug property for these CPUs.
Signed-off-by: Himanshu Chauhan <hchau...@ventanamicro.com> --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4231f36c1b..c9dda73748 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -569,6 +569,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) cpu->cfg.cbom_blocksize = 64; cpu->cfg.cboz_blocksize = 64; cpu->cfg.ext_zicboz = true; + cpu->cfg.ext_sdtrig = true; cpu->cfg.ext_smaia = true; cpu->cfg.ext_ssaia = true; cpu->cfg.ext_sscofpmf = true; -- 2.34.1