From: Frank Chang <[email protected]>
The current Zjpm implementation has the following issues:
1. The address is shifted before obtaining the correct PMLEN value.
2. riscv_pm_get_pmm() does not handle effective privilege mode correctly.
3. mstatus.MPRV does not affect virtual-machine load/store instructions.
4. Sign extension for virtual-machine load/store instructions (HLV.* and
HSV.*) must be performed when vsatp.MODE != Bare.
This patchset fixes the above issues and also renames
riscv_pm_get_virt_pmm() to riscv_pm_get_vm_ldst_pmm(), as the helper
is only used when checking the PMM configuration for virtual-machine
load/store instructions, rather than for VS/VU modes.
Changelog:
v3:
* Move riscv_cpu_eff_priv() to the header file and declare it as a
static inline function.
* Fix the MXR check bugs pointed out by Radim Krčmář.
v2:
* Check effective privilege mode in riscv_pm_get_pmm().
* Fix pointer masking for virtual-machine load/store instructions
(HLV.* and HSV.*).
* Rename riscv_pm_get_virt_pmm() to riscv_pm_get_vm_ldst_pmm().
Frank Chang (5):
target/riscv: Add a helper to return the current effective priv mode
target/riscv: Fix pointer masking PMM field selection logic
target/riscv: Fix pointer masking for virtual-machine load/store insns
target/riscv: Rename riscv_pm_get_virt_pmm() to
riscv_pm_get_vm_ldst_pmm()
target/riscv: Fix pointer masking translation mode check bug
Yong-Xuan Wang (1):
target/riscv: fix address masking
target/riscv/cpu.h | 41 +++++++++++++-
target/riscv/cpu_helper.c | 110 +++++++++++++++++++++++++++----------
target/riscv/internals.h | 8 +--
target/riscv/tcg/tcg-cpu.c | 4 +-
4 files changed, 124 insertions(+), 39 deletions(-)
--
2.43.0
