Richard Sandiford wrote: > Thiemo Seufer <[EMAIL PROTECTED]> writes: > > Richard Sandiford wrote: > >> All MIPS COP1X instructions currently require the FPU to be in 64-bit > >> mode. My understanding is that this is too restrictive, and that the > >> base conditions are different for different revisions of the ISA: > >> > >> MIPS IV: > >> COP1X instructions are available when the XX (CU3) bit of the > >> status register is set. This bit can be set independently of > >> UX and FR, and controls the core MIPS IV instructions as well > >> as the FPU ones. > > > > This part is, sadly, not fully correct. It depends on the CPU > > implementation what effect, the CU3 bit has. IIRC it behaves on some > > CPUs as you describe, while it is a nop on others. > > Sorry. I'll take your word for it. > > > (I don't know offhand which CPU did what there.) > > (FWIW, the r10k and VR5500 do as described, and I'm pretty sure the > RM7000 and RM9000 did too.) > > > Looks reasonable to me, apart from that one misassumption. > > What should the patch do instead for MIPS IV? Enable them unconditionally?
Given that it is currently theoretical, as the only MIPS IV CPU supported is the VR5432: Add a comment to the MIPS IV test that it is too restrictive for some CPUs. Thiemo