Blue Swirl wrote: > The attached patch enables most TCG ops for Qemu Sparc32/64 target. > Sparc32 softmmu and linux-user are OK, but Sparc64 and Sparc32plus > targets do not work. > > Comments? > > It would be nice to get rid of T2 usage in std (also stda and > casa/casxa) but I don't know how to pass a 64-bit value from legacy op > to TCG stores and loads on a 32-bit target and host.
> Index: qemu/target-sparc/translate.c > =================================================================== > --- qemu.orig/target-sparc/translate.c 2008-02-21 20:00:28.000000000 > +0000 > +++ qemu/target-sparc/translate.c 2008-02-21 20:02:07.000000000 +0000 > @@ -44,6 +44,81 @@ > #define JUMP_PC 2 /* dynamic pc value which takes only two values > according to jump_pc[T2] */ > > +#ifdef TARGET_SPARC64 > +#define TCG_TYPE_TL TCG_TYPE_I64 > +#define tcg_gen_movi_tl tcg_gen_movi_i64 > +#define tcg_gen_mov_tl tcg_gen_mov_i64 > +#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 > +#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 > +#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 > +#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 > +#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 > +#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 > +#define tcg_gen_ld_tl tcg_gen_ld_i64 > +#define tcg_gen_st8_tl tcg_gen_st8_i64 > +#define tcg_gen_st16_tl tcg_gen_st16_i64 > +#define tcg_gen_st32_tl tcg_gen_st32_i64 > +#define tcg_gen_st_tl tcg_gen_st_i64 > +#define tcg_gen_add_tl tcg_gen_add_i64 > +#define tcg_gen_addi_tl tcg_gen_addi_i64 > +#define tcg_gen_sub_tl tcg_gen_sub_i64 > +#define tcg_gen_subi_tl tcg_gen_subi_i64 > +#define tcg_gen_and_tl tcg_gen_and_i64 > +#define tcg_gen_andi_tl tcg_gen_andi_i64 > +#define tcg_gen_or_tl tcg_gen_or_i64 > +#define tcg_gen_ori_tl tcg_gen_ori_i64 > +#define tcg_gen_xor_tl tcg_gen_xor_i64 > +#define tcg_gen_xori_tl tcg_gen_xori_i64 > +#define tcg_gen_shl_tl tcg_gen_shl_i64 > +#define tcg_gen_shli_tl tcg_gen_shli_i64 > +#define tcg_gen_shr_tl tcg_gen_shr_i64 > +#define tcg_gen_shri_tl tcg_gen_shri_i64 > +#define tcg_gen_sar_tl tcg_gen_sar_i64 > +#define tcg_gen_sari_tl tcg_gen_sari_i64 > +#else > +#define TCG_TYPE_TL TCG_TYPE_I32 > +#define tcg_gen_movi_tl tcg_gen_movi_i32 > +#define tcg_gen_mov_tl tcg_gen_mov_i32 > +#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 > +#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 > +#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 > +#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 > +#define tcg_gen_ld32u_tl tcg_gen_ld_i32 > +#define tcg_gen_ld32s_tl tcg_gen_ld_i32 > +#define tcg_gen_ld_tl tcg_gen_ld_i32 > +#define tcg_gen_st8_tl tcg_gen_st8_i32 > +#define tcg_gen_st16_tl tcg_gen_st16_i32 > +#define tcg_gen_st32_tl tcg_gen_st_i32 > +#define tcg_gen_st_tl tcg_gen_st_i32 > +#define tcg_gen_add_tl tcg_gen_add_i32 > +#define tcg_gen_addi_tl tcg_gen_addi_i32 > +#define tcg_gen_sub_tl tcg_gen_sub_i32 > +#define tcg_gen_subi_tl tcg_gen_subi_i32 > +#define tcg_gen_and_tl tcg_gen_and_i32 > +#define tcg_gen_andi_tl tcg_gen_andi_i32 > +#define tcg_gen_or_tl tcg_gen_or_i32 > +#define tcg_gen_ori_tl tcg_gen_ori_i32 > +#define tcg_gen_xor_tl tcg_gen_xor_i32 > +#define tcg_gen_xori_tl tcg_gen_xori_i32 > +#define tcg_gen_shl_tl tcg_gen_shl_i32 > +#define tcg_gen_shli_tl tcg_gen_shli_i32 > +#define tcg_gen_shr_tl tcg_gen_shr_i32 > +#define tcg_gen_shri_tl tcg_gen_shri_i32 > +#define tcg_gen_sar_tl tcg_gen_sar_i32 > +#define tcg_gen_sari_tl tcg_gen_sari_i32 > +#endif This whole lot should probably move to generic code (conditionalized on TARGET_LONG_BITS), I have the same code in my MIPS prototype. Thiemo