On Wed, 2017-09-20 at 11:40 +0200, Cédric Le Goater wrote: > > Plus, this doesn't seem right. Shouldn't this > > recheck the CPPR against the PIPR, in case a higher priority irq has > > been delivered since the one the cpu is acking. > > If a higher priority is delivered, it means that the CPPR was more > privileged and that we have now two bits set in the IPB by the time > the interrupt is acked. The high priority PIPR will become the new > CPPR and the IBP will be modified keeping only the lower priority. > > if the CPPR is modified to the lower priority level, then the > first interrupt will be delivered again. > > I think this is fine.
Also remember the HW PIPR behaviour, its a bit odd, it will be clamped by the CPPR. So if CPPR is 0 PIPR will be 0. If CPPR is 7, PIPR will be <= 7, etc... Cheers, Ben.