Hello,
I am able to run the RTEMS real time system on the TI Stellaris LM3S6965
with a working system tick. I used the attached local hacks and patches
with the Qemu development branch from today.
Have a nice day!
--
Sebastian Huber, embedded brains GmbH
Address : Obere Lagerstr. 30, D-82178 Puchheim, Germany
Phone : +49 89 18 90 80 79-6
Fax : +49 89 18 90 80 79-9
E-Mail : sebastian.hu...@embedded-brains.de
PGP : Public key available on request.
Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.
>From 0c8e700376cec0c7b5a70f999b5e286efc321423 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.hu...@embedded-brains.de>
Date: Fri, 16 Dec 2011 19:46:40 +0100
Subject: [PATCH 1/4] target-arm: Fixed ARMv7-M SHPR access
According to "ARMv7-M Architecture Reference Manual" issue D section
"B3.2.10 System Handler Prioriy Register 1, SHPR1", "B3.2.11 System
Handler Prioriy Register 2, SHPR2", and "B3.2.12 System Handler Prioriy
Register 3, SHPR3".
Signed-off-by: Sebastian Huber <sebastian.hu...@embedded-brains.de>
---
hw/arm_gic.c | 16 ++++++++++++++--
hw/armv7m_nvic.c | 19 -------------------
2 files changed, 14 insertions(+), 21 deletions(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 9b52119..5139d95 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -356,6 +356,11 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
if (GIC_TEST_TRIGGER(irq + i))
res |= (2 << (i * 2));
}
+#else
+ } else if (0xd18 <= offset && offset < 0xd24) {
+ /* System Handler Priority. */
+ irq = offset - 0xd14;
+ res = GIC_GET_PRIORITY(irq, cpu);
#endif
} else if (offset < 0xfe0) {
goto bad_reg;
@@ -387,7 +392,8 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
gic_state *s = (gic_state *)opaque;
uint32_t addr;
addr = offset;
- if (addr < 0x100 || addr > 0xd00)
+ if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c
+ && addr != 0xd20))
return nvic_readl(s, addr);
#endif
val = gic_dist_readw(opaque, offset);
@@ -528,6 +534,11 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
GIC_CLEAR_TRIGGER(irq + i);
}
}
+#else
+ } else if (0xd18 <= offset && offset < 0xd24) {
+ /* System Handler Priority. */
+ irq = offset - 0xd14;
+ s->priority1[irq][0] = value & 0xff;
#endif
} else {
/* 0xf00 is only handled for 32-bit writes. */
@@ -553,7 +564,8 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
#ifdef NVIC
uint32_t addr;
addr = offset;
- if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
+ if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c
+ && addr != 0xd20 && addr != 0xf00)) {
nvic_writel(s, addr, value);
return;
}
diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
index bf8c3c5..65b575e 100644
--- a/hw/armv7m_nvic.c
+++ b/hw/armv7m_nvic.c
@@ -195,14 +195,6 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset)
case 0xd14: /* Configuration Control. */
/* TODO: Implement Configuration Control bits. */
return 0;
- case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */
- irq = offset - 0xd14;
- val = 0;
- val |= s->gic.priority1[irq++][0];
- val |= s->gic.priority1[irq++][0] << 8;
- val |= s->gic.priority1[irq++][0] << 16;
- val |= s->gic.priority1[irq][0] << 24;
- return val;
case 0xd24: /* System Handler Status. */
val = 0;
if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
@@ -335,17 +327,6 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
case 0xd14: /* Configuration Control. */
/* TODO: Implement control registers. */
goto bad_reg;
- case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */
- {
- int irq;
- irq = offset - 0xd14;
- s->gic.priority1[irq++][0] = value & 0xff;
- s->gic.priority1[irq++][0] = (value >> 8) & 0xff;
- s->gic.priority1[irq++][0] = (value >> 16) & 0xff;
- s->gic.priority1[irq][0] = (value >> 24) & 0xff;
- gic_update(&s->gic);
- }
- break;
case 0xd24: /* System Handler Control. */
/* TODO: Real hardware allows you to set/clear the active bits
under some circumstances. We don't implement this. */
--
1.7.1
>From 5f562d098d84e12d4688272dcf68a2d0318721a7 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.hu...@embedded-brains.de>
Date: Fri, 16 Dec 2011 20:00:59 +0100
Subject: [PATCH 2/4] target-arm: Disable priority_mask feature
This is unused for the ARMv7-M NVIC.
Signed-off-by: Sebastian Huber <sebastian.hu...@embedded-brains.de>
---
hw/arm_gic.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index 5139d95..cafcc81 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -707,7 +707,11 @@ static void gic_reset(gic_state *s)
int i;
memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));
for (i = 0 ; i < NUM_CPU(s); i++) {
+#ifdef NVIC
+ s->priority_mask[i] = 0x100;
+#else
s->priority_mask[i] = 0xf0;
+#endif
s->current_pending[i] = 1023;
s->running_irq[i] = 1023;
s->running_priority[i] = 0x100;
--
1.7.1
>From 78e85bb79c02b14170c3f39d9bb9cccd4d625890 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.hu...@embedded-brains.de>
Date: Fri, 16 Dec 2011 20:12:29 +0100
Subject: [PATCH 3/4] target-arm: Evil hack for BASEPRI and BASEPRI_MAX
This is only a quick and dirty fix to get the ARMv7-M BASEPRI and
BASEPRI_MAX feature working.
Signed-off-by: Sebastian Huber <sebastian.hu...@embedded-brains.de>
---
cpu-exec.c | 4 ++--
target-arm/helper.c | 12 +++++-------
2 files changed, 7 insertions(+), 9 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index a9fa608..6ca9aab 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -408,8 +408,8 @@ int cpu_exec(CPUState *env)
We avoid this by disabling interrupts when
pc contains a magic address. */
if (interrupt_request & CPU_INTERRUPT_HARD
- && ((IS_M(env) && env->regs[15] < 0xfffffff0)
- || !(env->uncached_cpsr & CPSR_I))) {
+ && !(env->uncached_cpsr & CPSR_I)
+ && (!IS_M(env) || env->regs[15] < 0xfffffff0)) {
env->exception_index = EXCP_IRQ;
do_interrupt(env);
next_tb = 0;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 65f4fbf..be2e6db 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2163,7 +2163,7 @@ uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
return (env->uncached_cpsr & CPSR_I) != 0;
case 17: /* BASEPRI */
case 18: /* BASEPRI_MAX */
- return env->v7m.basepri;
+ return (env->uncached_cpsr & CPSR_I) != 0;
case 19: /* FAULTMASK */
return (env->uncached_cpsr & CPSR_F) != 0;
case 20: /* CONTROL */
@@ -2218,13 +2218,11 @@ void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
env->uncached_cpsr &= ~CPSR_I;
break;
case 17: /* BASEPRI */
- env->v7m.basepri = val & 0xff;
- break;
case 18: /* BASEPRI_MAX */
- val &= 0xff;
- if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
- env->v7m.basepri = val;
- break;
+ if (val)
+ env->uncached_cpsr |= CPSR_I;
+ else
+ env->uncached_cpsr &= ~CPSR_I;
case 19: /* FAULTMASK */
if (val & 1)
env->uncached_cpsr |= CPSR_F;
--
1.7.1
>From e06edd436a336e5db5188eb7ffac594138fc825a Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.hu...@embedded-brains.de>
Date: Fri, 16 Dec 2011 20:19:45 +0100
Subject: [PATCH 4/4] target-arm: Evil hack to increase the RAM size
This increases the RAM of the Stellaris LM3S6965 in a brute force way.
It would be nice to be able to override the default RAM size with
command line options. The default RAM size is to small to run complex
test suites.
Signed-off-by: Sebastian Huber <sebastian.hu...@embedded-brains.de>
---
hw/stellaris.c | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/hw/stellaris.c b/hw/stellaris.c
index ce62a98..dd7b7d7 100644
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -1219,7 +1219,8 @@ static stellaris_board_info stellaris_boards[] = {
{ "LM3S6965EVB",
0x10010002,
0x1073402e,
- 0x00ff007f, /* dc0 */
+ /* FIXME */
+ 0xffffffff, /* dc0 */
0x001133ff,
0x030f5317,
0x0f0f87ff,
--
1.7.1
