[coreboot] [PATCH] Add clobber regs to AMD CAR
Hello,
Following patch adds proper inline assembly register clobbers to the AMD CAR
code. The reason is that the GCC expects some values to be still valid, but
those are overwritten by the inline code (ecx). The memcopy implementation is
taken from linux kernel 2.6.32. The EBP relocation is to needed because the code
does not use frame pointer. As an extra safety I added a clobber of all
available registers. To make GCC extra sure that no value is valid, which should
catch pointers to variables on the stack too.
Can someone test this change on something else than model 0fh please?
Signed-off-by: Rudolf Marek r.ma...@assembler.cz
Thanks,
Rudolf
Index: src/cpu/amd/car/disable_cache_as_ram.c
===
--- src/cpu/amd/car/disable_cache_as_ram.c (revision 5009)
+++ src/cpu/amd/car/disable_cache_as_ram.c (working copy)
@@ -2,62 +2,49 @@
/* be warned, this file will be used other cores and core 0 / node 0 */
static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
{
-
-__asm__ volatile (
-
+__asm__ __volatile__ (
/* We don't need cache as ram for now on */
/* disable cache */
-movl%cr0, %eax\n\t
-orl$(0x130),%eax\n\t
-movl%eax, %cr0\n\t
+movl%%cr0, %%eax\n\t
+orl$(0x130),%%eax\n\t
+movl%%eax, %%cr0\n\t
/* clear sth */
-movl$0x269, %ecx\n\t /* fix4k_c8000*/
-xorl%edx, %edx\n\t
-xorl%eax, %eax\n\t
+movl$0x269, %%ecx\n\t /* fix4k_c8000*/
+xorl%%edx, %%edx\n\t
+xorl%%eax, %%eax\n\t
wrmsr\n\t
#if CONFIG_DCACHE_RAM_SIZE 0x8000
- movl$0x268, %ecx\n\t /* fix4k_c*/
+ movl$0x268, %%ecx\n\t /* fix4k_c*/
wrmsr\n\t
#endif
/* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
-movl$0xC0010010, %ecx\n\t
+movl$0xC0010010, %%ecx\n\t
//movl$SYSCFG_MSR, %ecx\n\t
rdmsr\n\t
-andl$(~(318)), %eax\n\t
+andl$(~(318)), %%eax\n\t
//andl$(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t
wrmsr\n\t
/* Set the default memory type and disable fixed and enable variable MTRRs */
-movl$0x2ff, %ecx\n\t
+movl$0x2ff, %%ecx\n\t
//movl$MTRRdefType_MSR, %ecx\n\t
-xorl%edx, %edx\n\t
+xorl%%edx, %%edx\n\t
/* Enable Variable and Disable Fixed MTRRs */
-movl$0x0800, %eax\n\t
+movl$0x0800, %%eax\n\t
wrmsr\n\t
/* enable cache */
-movl%cr0, %eax\n\t
-andl$0x9fff,%eax\n\t
-movl%eax, %cr0\n\t
-
+movl%%cr0, %%eax\n\t
+andl$0x9fff,%%eax\n\t
+movl%%eax, %%cr0\n\t
+::: memory, eax, ecx, edx
);
}
static void disable_cache_as_ram_bsp(void)
{
- __asm__ volatile (
-// pushl %eax\n\t
- pushl %edx\n\t
- pushl %ecx\n\t
- );
-
disable_cache_as_ram();
-__asm__ volatile (
-popl %ecx\n\t
-popl %edx\n\t
-//popl %eax\n\t
-);
}
Index: src/cpu/amd/car/post_cache_as_ram.c
===
--- src/cpu/amd/car/post_cache_as_ram.c (revision 5009)
+++ src/cpu/amd/car/post_cache_as_ram.c (working copy)
@@ -12,12 +12,16 @@
static void inline __attribute__((always_inline)) memcopy(void *dest, const void *src, unsigned long bytes)
{
-__asm__ volatile(
-cld\n\t
-rep; movsl\n\t
-: /* No outputs */
-: S (src), D (dest), c ((bytes)2)
-);
+ int d0, d1, d2;
+ asm volatile(cld ; rep ; movsl\n\t
+ movl %4,%%ecx\n\t
+ andl $3,%%ecx\n\t
+ jz 1f\n\t
+ rep ; movsb\n\t
+ 1:
+ : =c (d0), =D (d1), =S (d2)
+ : 0 (bytes / 4), g (bytes), 1 ((long)dest), 2 ((long)src)
+ : memory, cc);
}
/* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 */
@@ -51,6 +55,7 @@
unsigned testx = 0x5a5a5a5a;
print_debug_pcar(testx = , testx);
+
/* copy data from cache as ram to
ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead.
*/
@@ -66,28 +71,16 @@
/* from here don't store more data in CAR */
vErrata343();
-#if 0
-__asm__ volatile (
- pushl %eax\n\t
-);
-#endif
-
memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
//dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
__asm__ volatile (
/* set new esp */ /* before CONFIG_RAMBASE */
-subl %0, %%ebp\n\t
subl %0, %%esp\n\t
::a( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
-
[coreboot] [PATCH] Add clobber regs to AMD CAR
Hello,
Following patch adds proper inline assembly register clobbers to the AMD CAR
code. The reason is that the GCC expects some values to be still valid, but
those are overwritten by the inline code (ecx). The memcopy implementation is
taken from linux kernel 2.6.32. The EBP relocation is to needed because the code
does not use frame pointer. As an extra safety I added a clobber of all
available registers. To make GCC extra sure that no value is valid, which should
catch pointers to variables on the stack too.
Can someone test this change on something else than model 0fh please?
Signed-off-by: Rudolf Marek r.ma...@assembler.cz
Thanks,
Rudolf
Index: src/cpu/amd/car/disable_cache_as_ram.c
===
--- src/cpu/amd/car/disable_cache_as_ram.c (revision 5009)
+++ src/cpu/amd/car/disable_cache_as_ram.c (working copy)
@@ -2,62 +2,49 @@
/* be warned, this file will be used other cores and core 0 / node 0 */
static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
{
-
-__asm__ volatile (
-
+__asm__ __volatile__ (
/* We don't need cache as ram for now on */
/* disable cache */
-movl%cr0, %eax\n\t
-orl$(0x130),%eax\n\t
-movl%eax, %cr0\n\t
+movl%%cr0, %%eax\n\t
+orl$(0x130),%%eax\n\t
+movl%%eax, %%cr0\n\t
/* clear sth */
-movl$0x269, %ecx\n\t /* fix4k_c8000*/
-xorl%edx, %edx\n\t
-xorl%eax, %eax\n\t
+movl$0x269, %%ecx\n\t /* fix4k_c8000*/
+xorl%%edx, %%edx\n\t
+xorl%%eax, %%eax\n\t
wrmsr\n\t
#if CONFIG_DCACHE_RAM_SIZE 0x8000
- movl$0x268, %ecx\n\t /* fix4k_c*/
+ movl$0x268, %%ecx\n\t /* fix4k_c*/
wrmsr\n\t
#endif
/* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
-movl$0xC0010010, %ecx\n\t
+movl$0xC0010010, %%ecx\n\t
//movl$SYSCFG_MSR, %ecx\n\t
rdmsr\n\t
-andl$(~(318)), %eax\n\t
+andl$(~(318)), %%eax\n\t
//andl$(~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn)), %eax\n\t
wrmsr\n\t
/* Set the default memory type and disable fixed and enable variable MTRRs */
-movl$0x2ff, %ecx\n\t
+movl$0x2ff, %%ecx\n\t
//movl$MTRRdefType_MSR, %ecx\n\t
-xorl%edx, %edx\n\t
+xorl%%edx, %%edx\n\t
/* Enable Variable and Disable Fixed MTRRs */
-movl$0x0800, %eax\n\t
+movl$0x0800, %%eax\n\t
wrmsr\n\t
/* enable cache */
-movl%cr0, %eax\n\t
-andl$0x9fff,%eax\n\t
-movl%eax, %cr0\n\t
-
+movl%%cr0, %%eax\n\t
+andl$0x9fff,%%eax\n\t
+movl%%eax, %%cr0\n\t
+::: memory, eax, ecx, edx
);
}
static void disable_cache_as_ram_bsp(void)
{
- __asm__ volatile (
-// pushl %eax\n\t
- pushl %edx\n\t
- pushl %ecx\n\t
- );
-
disable_cache_as_ram();
-__asm__ volatile (
-popl %ecx\n\t
-popl %edx\n\t
-//popl %eax\n\t
-);
}
Index: src/cpu/amd/car/post_cache_as_ram.c
===
--- src/cpu/amd/car/post_cache_as_ram.c (revision 5009)
+++ src/cpu/amd/car/post_cache_as_ram.c (working copy)
@@ -12,12 +12,16 @@
static void inline __attribute__((always_inline)) memcopy(void *dest, const void *src, unsigned long bytes)
{
-__asm__ volatile(
-cld\n\t
-rep; movsl\n\t
-: /* No outputs */
-: S (src), D (dest), c ((bytes)2)
-);
+ int d0, d1, d2;
+ asm volatile(cld ; rep ; movsl\n\t
+ movl %4,%%ecx\n\t
+ andl $3,%%ecx\n\t
+ jz 1f\n\t
+ rep ; movsb\n\t
+ 1:
+ : =c (d0), =D (d1), =S (d2)
+ : 0 (bytes / 4), g (bytes), 1 ((long)dest), 2 ((long)src)
+ : memory, cc);
}
/* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 */
@@ -51,6 +55,7 @@
unsigned testx = 0x5a5a5a5a;
print_debug_pcar(testx = , testx);
+
/* copy data from cache as ram to
ram need to set CONFIG_RAMTOP to 2M and use var mtrr instead.
*/
@@ -66,28 +71,16 @@
/* from here don't store more data in CAR */
vErrata343();
-#if 0
-__asm__ volatile (
- pushl %eax\n\t
-);
-#endif
-
memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline
//dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00);
__asm__ volatile (
/* set new esp */ /* before CONFIG_RAMBASE */
-subl %0, %%ebp\n\t
subl %0, %%esp\n\t
::a( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- (CONFIG_RAMTOP) )
-
Re: [coreboot] Seabios problems
On Sat, Jan 16, 2010 at 12:06:01PM +0100, conged...@voila.fr wrote: Hello Kevin, I can't give you the full log for the keyboard problem. I think this is a timeout issue: when I run Seabios in debuglevel=8, no problem, but if debuglevel=1 or even 4, my keyboard don't want to initialize most of the time. So, I suppose that sending debug data to the port gives time to the keyboard to initialize correctly. Okay - can you send a log with a failure when at debug level 4 then? The attachment files are the logs you asked me reporting the Vista booting error. Do you use DMA since version 0.5.1 to boot ? Okay - I'll take a look. It seems there is an issue with DMA on your board. What's 'lspci' report for your machine? -Kevin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot and MSM800BEV
2010/1/15 Peter Stuge pe...@stuge.se: 0x2018 = 0x100770144840 0x2019 = 0x18006a7332a3 0x201a = 0x130cd101 0x201b = 0x 0x201c = 0x00ff00ff 0x201d = 0x1000 0x4c0f = 0x83f100aa569603c4 0x4c14 = 0x049c07de000c I am going to analyze it ... If msrtool didn't decode these for you then that's a bug. Did you get something similar to the following output? # MC_CF07_DATA 0x2018 = 0x100770144840 ... No, I didn't. I just got that lines with information about unrecognized registers. It seems that msrtool doesn't have suitable definitions in its database. -- Piotr Piwko http://www.embedded-engineering.pl/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5010 - trunk/src/pc80
Author: stepan
Date: 2010-01-16 14:27:39 +0100 (Sat, 16 Jan 2010)
New Revision: 5010
Modified:
trunk/src/pc80/mc146818rtc.c
Log:
RTC: Don't drop the alpha specific code but get it in shape for our Kconfig
scheme.
(trivial)
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified: trunk/src/pc80/mc146818rtc.c
===
--- trunk/src/pc80/mc146818rtc.c2010-01-15 10:07:05 UTC (rev 5009)
+++ trunk/src/pc80/mc146818rtc.c2010-01-16 13:27:39 UTC (rev 5010)
@@ -121,15 +121,15 @@
cmos_write(((sum 0) 0x0ff), cks_loc+1);
}
+#if CONFIG_ARCH_X86
#define RTC_CONTROL_DEFAULT (RTC_24H)
#define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ)
-
-#if 0 /* alpha setup */
-#undef RTC_CONTROL_DEFAULT
-#undef RTC_FREQ_SELECT_DEFAULT
+#else
+#if CONFIG_ARCH_ALPHA
#define RTC_CONTROL_DEFAULT (RTC_SQWE | RTC_24H)
#define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ)
#endif
+#endif
void rtc_init(int invalid)
{
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5012 - trunk/src/cpu/intel/model_106cx
Author: stepan Date: 2010-01-16 14:47:07 +0100 (Sat, 16 Jan 2010) New Revision: 5012 Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c Log: Micro-optimization: movl $0 -- xorl. Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc === --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc2010-01-16 13:42:43 UTC (rev 5011) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc2010-01-16 13:47:07 UTC (rev 5012) @@ -71,7 +71,7 @@ /* Set cache as ram mask */ movl$(MTRRphysMask_MSR(0)), %ecx movl$(~((CACHE_AS_RAM_SIZE-1)) | (1 11)), %eax - movl$0x, %edx + xorl%edx, %edx wrmsr post_code(0x25) @@ -113,7 +113,7 @@ #if defined(CONFIG_XIP_ROM_SIZE) defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ movl$MTRRphysBase_MSR(1), %ecx -xorl%edx, %edx + xorl%edx, %edx #if defined(CONFIG_TINY_BOOTBLOCK) CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else @@ -124,7 +124,7 @@ wrmsr movl$MTRRphysMask_MSR(1), %ecx -movl$0x, %edx + xorl%edx, %edx movl$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE CONFIG_XIP_ROM_BASE */ Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c === --- trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c 2010-01-16 13:42:43 UTC (rev 5011) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c 2010-01-16 13:47:07 UTC (rev 5012) @@ -60,7 +60,7 @@ wrmsr\n movl $MTRRphysMask_MSR(0), %ecx\n movl $(~(1024*1024 -1) | (1 11)), %eax\n - movl $0x, %edx\n + xorl %edx, %edx\n wrmsr\n movb $0x35, %al\noutb %al, $0x80\n #endif @@ -97,7 +97,7 @@ wrmsr\n movl $MTRRphysMask_MSR(0), %ecx\n movl $(~(1024*1024 -1) | (1 11)), %eax\n - movl $0x, %edx\n + xorl %edx, %edx\n wrmsr\n movb $0x39, %al\noutb %al, $0x80\n -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] is this a supported board?
Hello, I'm trying to find out if I can use coreboot on an old P3 500MHz server board. I *think* this is a Intel board with a 440BX chipset. Attached is the output of lspci, superiotool, and flashrom. Thanks in advance! -[:00]-+-00.0 Intel Corporation 440BX/ZX/DX - 82443BX/ZX/DX Host bridge [8086:7190] +-01.0-[:01]-- +-0b.0 C-Media Electronics Inc CM8738 [13f6:0111] +-0c.0 Linksys Gigabit Network Adapter [1737:1032] +-0d.0 LSI Logic / Symbios Logic 53c875 [1000:000f] +-0e.0 nVidia Corporation NV34 [GeForce FX 5200] [10de:0322] +-0f.0 Intel Corporation 82557/8/9/0/1 Ethernet Pro 100 [8086:1229] +-10.0 Promise Technology, Inc. PDC40775 (SATA 300 TX2plus) [105a:3d73] +-12.0 Intel Corporation 82371AB/EB/MB PIIX4 ISA [8086:7110] +-12.1 Intel Corporation 82371AB/EB/MB PIIX4 IDE [8086:7111] +-12.2 Intel Corporation 82371AB/EB/MB PIIX4 USB [8086:7112] +-12.3 Intel Corporation 82371AB/EB/MB PIIX4 ACPI [8086:7113] \-14.0 Cirrus Logic GD 5480 [1013:00bc] superiotool r3844 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0x, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0x, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x, id=0x0fe0 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x, id=0x Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xe00f, rev=0x0 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xe00f, rev=0x0 Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xe00f, rev=0x0 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xe00f, rev=0x0 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0x, rev=0xf Probing for NSC Super I/O at 0x2e... Found NSC PC87309 (sid=0xe0, srid=0x22) at 0x2e Register dump: idx 20 21 22 27 2e val e0 0f 50 22 00 def e0 MM 00 NA RR LDN 0x00 (Floppy) idx 30 31 60 61 70 71 74 75 f0 f1 val 01 00 03 f0 06 03 02 04 20 00 def MM 00 03 f2 06 03 02 04 20 00 LDN 0x01 (Parallel port) idx 30 31 60 61 70 71 74 75 f0 val 01 00 03 78 07 02 03 04 82 def 00 00 02 78 07 00 04 04 f2 LDN 0x02 (COM2 / IR) idx 30 31 60 61 70 71 74 75 f0 val 01 00 02 f8 03 03 04 04 02 def 00 00 02 f8 03 03 04 04 02 LDN 0x03 (COM1) idx 30 31 60 61 70 71 74 75 f0 val 01 00 03 f8 04 03 04 04 02 def 00 00 03 f8 04 03 04 04 02 LDN 0x04 (Power management) idx 30 31 60 61 74 75 val 00 00 01 10 04 04 def 00 00 00 00 04 04 LDN 0x05 (Mouse) idx 30 70 71 74 75 val 01 0c 03 04 04 def 00 0c 02 04 04 LDN 0x06 (Keyboard) idx 30 31 60 61 62 63 70 71 74 75 f0 val 01 00 00 60 00 64 01 03 04 04 40 def 01 00 00 60 00 64 01 02 04 04 40 Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xe0, rev=0x0f Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xe0/0x00, rev=0x0f Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xe0/0x00, rev=0x0f Probing for
[coreboot] [PATCH] ectool - add support for dumping EC index ram
See patch
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: i...@coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
ectool: Support for dumping EC index ram
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: util/ectool/ectool.c
===
--- util/ectool/ectool.c(revision 5009)
+++ util/ectool/ectool.c(working copy)
@@ -99,5 +99,14 @@
}
printf(\n\n);
+ printf(EC IDX RAM:\n);
+ for (i = 0; i 0x1; i++) {
+ if ((i % 0x10) == 0)
+ printf(\n%04x: , i);
+ printf(%02x , ec_idx_read(i));
+ }
+ printf(\n\n);
+
+
return 0;
}
Index: util/ectool/ec.c
===
--- util/ectool/ec.c(revision 5009)
+++ util/ectool/ec.c(working copy)
@@ -114,3 +114,13 @@
return send_ec_data(data);
}
+
+uint8_t ec_idx_read(uint16_t addr)
+{
+ uint16_t lpc_idx = 0x380;
+
+ outb(addr 0xff, lpc_idx + 2);
+ outb(addr 8, lpc_idx + 1);
+
+ return inb(lpc_idx + 3);
+}
Index: util/ectool/ec.h
===
--- util/ectool/ec.h(revision 5009)
+++ util/ectool/ec.h(working copy)
@@ -47,4 +47,5 @@
uint8_t recv_ec_data(void);
uint8_t ec_read(uint8_t addr);
+uint8_t ec_idx_read(uint16_t addr);
#endif
--
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http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] buildgcc - reference toolchain update
See patch
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: i...@coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
Update reference toolchain to
gcc 4.4.2
binutils 2.20
gdb 7.0
and add mingw support.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: util/crossgcc/patches/binutils-2.20_no-i386-svr4-asm-comments.patch
===
--- util/crossgcc/patches/binutils-2.20_no-i386-svr4-asm-comments.patch
(revision 0)
+++ util/crossgcc/patches/binutils-2.20_no-i386-svr4-asm-comments.patch
(revision 0)
@@ -0,0 +1,10 @@
+--- binutils-2.20/gas/config/tc-i386.c~2009-01-20 14:19:04.0
+0100
binutils-2.20/gas/config/tc-i386.c 2009-01-20 14:20:47.0 +0100
+@@ -318,6 +318,7 @@
+ !defined (TE_GNU) \
+ !defined (TE_LINUX) \
+ !defined (TE_NETWARE) \
++0 \
+ !defined (TE_FreeBSD) \
+ !defined (TE_NetBSD)))
+ /* This array holds the chars that always start a comment. If the
Index: util/crossgcc/patches/gcc-4.4.2_less-junk-in-crtbegin.patch
===
--- util/crossgcc/patches/gcc-4.4.2_less-junk-in-crtbegin.patch (revision 0)
+++ util/crossgcc/patches/gcc-4.4.2_less-junk-in-crtbegin.patch (revision 0)
@@ -0,0 +1,50 @@
+--- t/gcc-4.4.2/gcc/crtstuff.c Fr. Apr 10 01:23:07 2009
gcc-4.4.2/gcc/crtstuff.c Di. Jul 28 16:43:28 2009
+@@ -204,6 +204,7 @@
+ = { (func_ptr) (-1) };
+ #endif /* __DTOR_LIST__ alternatives */
+
++#if 0
+ #ifdef USE_EH_FRAME_REGISTRY
+ /* Stick a label at the beginning of the frame unwind info so we can register
+and deregister it with the exception handling library code. */
+@@ -219,6 +220,7 @@
+ __attribute__ ((unused, section(JCR_SECTION_NAME), aligned(sizeof(void*
+ = { };
+ #endif /* JCR_SECTION_NAME */
++#endif
+
+ #if defined(INIT_SECTION_ASM_OP) || defined(INIT_ARRAY_SECTION_ASM_OP)
+
+@@ -309,6 +311,7 @@
+ }
+ #endif /* !defined(FINI_ARRAY_SECTION_ASM_OP) */
+
++#if 0
+ #ifdef USE_EH_FRAME_REGISTRY
+ #ifdef CRT_GET_RFIB_DATA
+ /* If we used the new __register_frame_info_bases interface,
+@@ -320,6 +323,7 @@
+ __deregister_frame_info (__EH_FRAME_BEGIN__);
+ #endif
+ #endif
++#endif
+
+ completed = 1;
+ }
+@@ -333,6 +337,7 @@
+ = { __do_global_dtors_aux };
+ #endif /* !defined(FINI_SECTION_ASM_OP) */
+
++#if 0
+ #if defined(USE_EH_FRAME_REGISTRY) || defined(JCR_SECTION_NAME)
+ /* Stick a call to __register_frame_info into the .init section. For some
+reason calls with no arguments work more reliably in .init, so stick the
+@@ -364,6 +369,7 @@
+ }
+ #endif /* JCR_SECTION_NAME */
+ }
++#endif
+
+ #ifdef INIT_SECTION_ASM_OP
+ CRT_CALL_STATIC_FUNCTION (INIT_SECTION_ASM_OP, frame_dummy)
Index: util/crossgcc/buildgcc
===
--- util/crossgcc/buildgcc (revision 5009)
+++ util/crossgcc/buildgcc (working copy)
@@ -28,10 +28,12 @@
# version numbers
GMP_VERSION=4.3.1
-MPFR_VERSION=2.4.1
-GCC_VERSION=4.4.1
-BINUTILS_VERSION=2.19.1
-GDB_VERSION=6.8
+MPFR_VERSION=2.4.2
+GCC_VERSION=4.4.2
+BINUTILS_VERSION=2.20
+GDB_VERSION=7.0
+W32API_VERSION=3.13
+MINGWRT_VERSION=3.16
# archive locations
GMP_ARCHIVE=ftp://ftp.gmplib.org/pub/gmp-${GMP_VERSION}/gmp-${GMP_VERSION}.tar.bz2;
@@ -39,12 +41,16 @@
GCC_ARCHIVE=ftp://ftp.gwdg.de/pub/gnu/ftp/gnu/gcc/gcc-${GCC_VERSION}/gcc-core-${GCC_VERSION}.tar.bz2;
BINUTILS_ARCHIVE=http://ftp.gnu.org/gnu/binutils/binutils-${BINUTILS_VERSION}.tar.bz2;
GDB_ARCHIVE=http://ftp.gnu.org/gnu/gdb/gdb-${GDB_VERSION}.tar.bz2;
+W32API_ARCHIVE=http://downloads.sourceforge.net/project/mingw/MinGW%20API%20for%20MS-Windows/Current%20Release_%20w32api-${W32API_VERSION}/w32api-${W32API_VERSION}-mingw32-src.tar.gz;
+MINGWRT_ARCHIVE=http://downloads.sourceforge.net/project/mingw/MinGW%20Runtime/mingwrt-${MINGWRT_VERSION}/mingwrt-${MINGWRT_VERSION}-mingw32-src.tar.gz;
GMP_DIR=gmp-${GMP_VERSION}
MPFR_DIR=mpfr-${MPFR_VERSION}
GCC_DIR=gcc-${GCC_VERSION}
BINUTILS_DIR=binutils-${BINUTILS_VERSION}
GDB_DIR=gdb-${GDB_VERSION}
+W32API_DIR=w32api-${W32API_VERSION}-mingw32
+MINGWRT_DIR=mingwrt-${MINGWRT_VERSION}-mingw32
SAVETEMPS=0
@@ -82,7 +88,7 @@
cleanup()
{
printf Cleaning up temporary files...
- rm -rf build-* combined gcc-* gmp-* mpfr-* binutils-* gdb-*
+ rm -rf build-* combined gcc-* gmp-* mpfr-* binutils-* gdb-* w32api-*
mingwrt-*
printf ${green}ok${NC}\n
}
@@ -158,9 +164,14 @@
esac
done
+MINGW_ARCHIVES=
+if [ $TARGETARCH = i386-mingw32 ]; then
+ MINGW_ARCHIVES=$W32API_ARCHIVE $MINGWRT_ARCHIVE
+fi
+
printf
Re: [coreboot] [PATCH] buildgcc - reference toolchain update
Am 16.01.2010 17:13, schrieb Stefan Reinauer: See patch Acked-by: Patrick Georgi patrick.geo...@coresystems.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5016 - in trunk/src: mainboard/intel/d945gclf mainboard/intel/eagleheights mainboard/kontron/986lcd-m northbridge/intel/i945 southbridge/intel/i82801gx
Author: stepan
Date: 2010-01-16 17:35:38 +0100 (Sat, 16 Jan 2010)
New Revision: 5016
Added:
trunk/src/northbridge/intel/i945/debug.c
Removed:
trunk/src/mainboard/intel/d945gclf/debug.c
trunk/src/mainboard/intel/d945gclf/power_reset_check.c
trunk/src/mainboard/intel/d945gclf/reset.c
trunk/src/mainboard/intel/eagleheights/power_reset_check.c
trunk/src/mainboard/kontron/986lcd-m/debug.c
trunk/src/mainboard/kontron/986lcd-m/power_reset_check.c
trunk/src/mainboard/kontron/986lcd-m/reset.c
Modified:
trunk/src/mainboard/intel/d945gclf/Config.lb
trunk/src/mainboard/intel/d945gclf/Makefile.inc
trunk/src/mainboard/intel/d945gclf/auto.c
trunk/src/mainboard/kontron/986lcd-m/Config.lb
trunk/src/mainboard/kontron/986lcd-m/Makefile.inc
trunk/src/mainboard/kontron/986lcd-m/auto.c
trunk/src/southbridge/intel/i82801gx/i82801gx_reset.c
Log:
* drop reset files from 945 mainboards (and use southbridge specific reset)
* drop debug.c files from 945 mainboards (and share it in the northbridge code)
* adapt the mainboard and auto.c files for above changes.
Rather trivial
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified: trunk/src/mainboard/intel/d945gclf/Config.lb
===
--- trunk/src/mainboard/intel/d945gclf/Config.lb2010-01-16 14:57:32 UTC
(rev 5015)
+++ trunk/src/mainboard/intel/d945gclf/Config.lb2010-01-16 16:35:38 UTC
(rev 5016)
@@ -60,8 +60,6 @@
object ./dsdt.o
end
-object reset.o
-
if CONFIG_USE_INIT
makerule ./auto.o
Modified: trunk/src/mainboard/intel/d945gclf/Makefile.inc
===
--- trunk/src/mainboard/intel/d945gclf/Makefile.inc 2010-01-16 14:57:32 UTC
(rev 5015)
+++ trunk/src/mainboard/intel/d945gclf/Makefile.inc 2010-01-16 16:35:38 UTC
(rev 5016)
@@ -24,7 +24,6 @@
driver-y += mainboard.o
driver-y += rtl8168.o
-#obj-y += ../../../southbridge/intel/i82801gx/i82801gx_reset.c
obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o
obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
obj-$(CONFIG_GENERATE_ACPI_TABLES) += dsdt.o
Modified: trunk/src/mainboard/intel/d945gclf/auto.c
===
--- trunk/src/mainboard/intel/d945gclf/auto.c 2010-01-16 14:57:32 UTC (rev
5015)
+++ trunk/src/mainboard/intel/d945gclf/auto.c 2010-01-16 16:35:38 UTC (rev
5016)
@@ -20,6 +20,10 @@
// __PRE_RAM__ means: use unsigned for device, not a struct.
#define __PRE_RAM__
+/* Configuration of the i945 driver */
+#define CHIPSET_I945GC 1
+#define CHANNEL_XOR_RANDOMIZATION 1
+
#include stdint.h
#include string.h
#include arch/io.h
@@ -45,7 +49,6 @@
#include lib/ramtest.c
#include southbridge/intel/i82801gx/i82801gx_early_smbus.c
-#include reset.c
#include superio/smsc/lpc47m15x/lpc47m15x_early_serial.c
#include northbridge/intel/i945/udelay.c
@@ -77,12 +80,11 @@
return smbus_read_byte(device, address);
}
-#define CHANNEL_XOR_RANDOMIZATION 1
#include northbridge/intel/i945/raminit.h
#include northbridge/intel/i945/raminit.c
#include northbridge/intel/i945/reset_test.c
#include northbridge/intel/i945/errata.c
-#include debug.c
+#include northbridge/intel/i945/debug.c
static void ich7_enable_lpc(void)
{
Deleted: trunk/src/mainboard/intel/d945gclf/debug.c
===
--- trunk/src/mainboard/intel/d945gclf/debug.c 2010-01-16 14:57:32 UTC (rev
5015)
+++ trunk/src/mainboard/intel/d945gclf/debug.c 2010-01-16 16:35:38 UTC (rev
5016)
@@ -1,126 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define SMBUS_MEM_DEVICE_START 0x50
-#define SMBUS_MEM_DEVICE_END 0x53
-#define SMBUS_MEM_DEVICE_INC 1
-
-static void print_pci_devices(void)
-{
- device_t dev;
- for(dev = PCI_DEV(0, 0, 0);
- dev = PCI_DEV(0, 0x1f, 0x7);
- dev += PCI_DEV(0,0,1)) {
- uint32_t id;
- id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (((id 0x) == 0x) || ((id 0x) == 0x) ||
- (((id 16) 0x) == 0x) ||
-
[coreboot] [commit] r5017 - trunk/src/southbridge/intel/i82801gx
Author: stepan
Date: 2010-01-16 17:37:27 +0100 (Sat, 16 Jan 2010)
New Revision: 5017
Modified:
trunk/src/southbridge/intel/i82801gx/cmos_failover.c
Log:
(trivial) cosmetics for i82801gx cmos failover.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified: trunk/src/southbridge/intel/i82801gx/cmos_failover.c
===
--- trunk/src/southbridge/intel/i82801gx/cmos_failover.c2010-01-16
16:35:38 UTC (rev 5016)
+++ trunk/src/southbridge/intel/i82801gx/cmos_failover.c2010-01-16
16:37:27 UTC (rev 5017)
@@ -20,13 +20,12 @@
#include i82801gx.h
-#define RTC_FAILED(1 2)
-#define GEN_PMCON_3 0xa4
+#define RTC_FAILED (1 2)
+#define GEN_PMCON_30xa4
static void check_cmos_failed(void)
{
- u8 byte;
- byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+ u8 byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
if (byte RTC_FAILED) {
// clear bit 1 and bit 2
byte = cmos_read(RTC_BOOT_BYTE);
--
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[coreboot] [commit] r5018 - trunk/src/mainboard/intel/d945gclf
Author: stepan Date: 2010-01-16 17:39:50 +0100 (Sat, 16 Jan 2010) New Revision: 5018 Modified: trunk/src/mainboard/intel/d945gclf/Kconfig trunk/src/mainboard/intel/d945gclf/acpi_tables.c Log: Intel D945GCLF: Enable SMI and ACPI in Kconfig, too (it's enabled in newconfig) and guard SMI specific parts of the ACPI code. (trivial) Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Modified: trunk/src/mainboard/intel/d945gclf/Kconfig === --- trunk/src/mainboard/intel/d945gclf/Kconfig 2010-01-16 16:37:27 UTC (rev 5017) +++ trunk/src/mainboard/intel/d945gclf/Kconfig 2010-01-16 16:39:50 UTC (rev 5018) @@ -31,8 +31,8 @@ select USE_PRINTK_IN_CAR select AP_IN_SIPI_WAIT select UDELAY_LAPIC - #select HAVE_ACPI_TABLES - #select HAVE_SMI_HANDLER + select HAVE_ACPI_TABLES + select HAVE_SMI_HANDLER select BOARD_ROMSIZE_KB_1024 config MAINBOARD_DIR Modified: trunk/src/mainboard/intel/d945gclf/acpi_tables.c === --- trunk/src/mainboard/intel/d945gclf/acpi_tables.c2010-01-16 16:37:27 UTC (rev 5017) +++ trunk/src/mainboard/intel/d945gclf/acpi_tables.c2010-01-16 16:39:50 UTC (rev 5018) @@ -192,7 +192,9 @@ return current; } +#if CONFIG_HAVE_SMI_HANDLER void smm_setup_structures(void *gnvs, void *tcg, void *smi1); +#endif #define ALIGN_CURRENT current = ((current + 0x0f) -0x10) unsigned long write_acpi_tables(unsigned long start) @@ -311,8 +313,10 @@ current += 0x100; ALIGN_CURRENT; +#if CONFIG_HAVE_SMI_HANDLER /* And tell SMI about it */ smm_setup_structures((void *)current, NULL, NULL); +#endif /* We patched up the DSDT, so we need to recalculate the checksum */ dsdt-checksum = 0; -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Seabios problems
On Sat, Jan 16, 2010 at 12:23:09AM -0500, Kevin O'Connor wrote: On Fri, Jan 15, 2010 at 02:27:39PM +0100, conged...@voila.fr wrote: 0.5.1 : same problem as 0.5.0 and Vista don't want to boot I don't have any problems with my previous version pre-0.4.3. I run coreboot rev5007 on my asus m2v-mx_se. Your machine seems to have two hard drives. Is only one hard drive showing the boot issue, or are both drives not booting? -Kevin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5020 - trunk/util/msrtool
Author: stuge
Date: 2010-01-16 18:21:17 +0100 (Sat, 16 Jan 2010)
New Revision: 5020
Modified:
trunk/util/msrtool/msrtool.c
Log:
msrtool: Remove indent by using continue inside for() to avoid an if block
The only actual code change is from
if (.. = 1) {
}
to
if (.. 1)
continue
so this is pretty trivial.
Signed-off-by: Peter Stuge pe...@stuge.se
Acked-by: Peter Stuge pe...@stuge.se
Modified: trunk/util/msrtool/msrtool.c
===
--- trunk/util/msrtool/msrtool.c2010-01-16 16:44:20 UTC (rev 5019)
+++ trunk/util/msrtool/msrtool.c2010-01-16 17:21:17 UTC (rev 5020)
@@ -182,7 +182,7 @@
int do_diff(const char *difffn) {
char tmpfn[20], line[512];
size_t start, len;
- int ret = 1, tmp;
+ int ret = 1, found, tmp;
FILE *fin = NULL, *fout = stdout;
uint8_t rev = 0;
uint32_t addr, linenum;
@@ -203,19 +203,20 @@
goto done;
for (linenum = 1; NULL != fgets(line, sizeof(line), fin); ++linenum) {
start = (0 == strncmp(0x, line, 2)) ? 2 : 0;
- if (sscanf(line + start, %8x %n%*x, addr, tmp) = 1) {
- start += tmp;
- for (len = strlen(line) - 1; NULL != strchr(\r\n,
line[len]); --len)
- line[len] = 0;
- if (!str2msr(line + start, mf)) {
- fprintf(stderr, %s:%d: invalid MSR value
'%s'\n, difffn, linenum, line + start);
- continue;
- }
- if (!sys-rdmsr(cpu, addr, mhw))
- goto done;
- if (diff_msr(fout, addr, rev ? mhw : mf, rev ? mf :
mhw))
- fprintf(fout, \n);
+ found = sscanf(line + start, %8x %n%*x, addr, tmp);
+ if (found 1)
+ continue;
+ start += tmp;
+ for (len = strlen(line) - 1; NULL != strchr(\r\n, line[len]);
--len)
+ line[len] = 0;
+ if (!str2msr(line + start, mf)) {
+ fprintf(stderr, %s:%d: invalid MSR value '%s'\n,
difffn, linenum, line + start);
+ continue;
}
+ if (!sys-rdmsr(cpu, addr, mhw))
+ goto done;
+ if (diff_msr(fout, addr, rev ? mhw : mf, rev ? mf : mhw))
+ fprintf(fout, \n);
}
if (!feof(fin))
fprintf(stderr, %s:%d: fgets: %s\n, difffn, linenum,
strerror(errno));
--
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Re: [coreboot] Seabios problems
I tried with only my Vista HDD and seabios doesn't want to boot Windows boot manager. For info, my linux-grub2 is on a sata hdd, but Vista isn't. It is a pata hdd on an udma100. Message du 16/01/10 à 18h06 De : Kevin O'Connor ke...@koconnor.net A : conged...@voila.fr Copie à : seab...@seabios.org, coreboot coreboot@coreboot.org Objet : Re: [coreboot] Seabios problems On Sat, Jan 16, 2010 at 12:23:09AM -0500, Kevin O'Connor wrote: On Fri, Jan 15, 2010 at 02:27:39PM +0100, conged...@voila.fr wrote: 0.5.1 : same problem as 0.5.0 and Vista don't want to boot I don't have any problems with my previous version pre-0.4.3. I run coreboot rev5007 on my asus m2v-mx_se. Your machine seems to have two hard drives. Is only one hard drive showing the boot issue, or are both drives not booting? -Kevin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot Vous n’avez pas encore adressé vos voeux ? Retrouvez nos cartes sur http://carte-de-voeux.voila.fr -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] ectool - add support for dumping EC index ram
Acked-by: Ronald G. Minnich rminn...@gmail.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [1/2] coreboot cleanup: readl - read32, writel - write32
Wow! 5000 and up version numbers mean Cleanup time! :-) Acked-by: Ronald G. Minnich rminn...@gmail.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] ectool - add support for dumping EC index ram
On 1/16/10 6:38 PM, ron minnich wrote: Acked-by: Ronald G. Minnich rminn...@gmail.com Thanks, r5021 -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5022 - in trunk/src: arch/i386/include/arch arch/i386/lib lib mainboard/amd/db800 mainboard/artecgroup/dbe61 mainboard/digitallogic/msm800sev mainboard/iei/pcisa-lx-800-r10 mainbo
Author: stepan
Date: 2010-01-16 18:53:38 +0100 (Sat, 16 Jan 2010)
New Revision: 5022
Modified:
trunk/src/arch/i386/include/arch/io.h
trunk/src/arch/i386/include/arch/romcc_io.h
trunk/src/arch/i386/lib/console.c
trunk/src/arch/i386/lib/printk_init.c
trunk/src/lib/usbdebug_direct.c
trunk/src/mainboard/amd/db800/cache_as_ram_auto.c
trunk/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c
trunk/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c
trunk/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c
trunk/src/mainboard/intel/eagleheights/auto.c
trunk/src/mainboard/intel/eagleheights/mptable.c
trunk/src/mainboard/lippert/roadrunner-lx/cache_as_ram_auto.c
trunk/src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c
trunk/src/mainboard/pcengines/alix1c/cache_as_ram_auto.c
trunk/src/northbridge/amd/gx1/northbridge.c
trunk/src/northbridge/amd/gx1/raminit.c
trunk/src/southbridge/amd/amd8111/amd8111_nic.c
trunk/src/southbridge/amd/cs5530/cs5530_vga.c
trunk/src/southbridge/amd/cs5536/cs5536.c
trunk/src/southbridge/amd/sb600/sb600_hda.c
trunk/src/southbridge/amd/sb600/sb600_sata.c
trunk/src/southbridge/amd/sb600/sb600_usb.c
trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c
trunk/src/southbridge/intel/i82801gx/i82801gx_azalia.c
trunk/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
trunk/src/southbridge/intel/i82801gx/i82801gx_usb_ehci.c
trunk/src/southbridge/nvidia/ck804/ck804_nic.c
trunk/src/southbridge/nvidia/mcp55/mcp55_aza.c
trunk/src/southbridge/nvidia/mcp55/mcp55_nic.c
trunk/src/southbridge/sis/sis966/sis966_aza.c
trunk/src/southbridge/sis/sis966/sis966_nic.c
trunk/src/southbridge/sis/sis966/sis966_usb2.c
Log:
coreboot used to have two different APIs for memory accesses:
read32(unsigned long addr) vs readl(void *addr)
and
write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void
*addr)
read32 was only available in __PRE_RAM__ stage, while readl was used in stage2.
Some unclean implementations then made readl available to __PRE_RAM__ too which
results in really messy includes and code.
This patch fixes all code to use the read32/write32 variant, so that we can
remove readl/writel in another patch.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Ronald G. Minnich rminn...@gmail.com
Modified: trunk/src/arch/i386/include/arch/io.h
===
--- trunk/src/arch/i386/include/arch/io.h 2010-01-16 17:50:55 UTC (rev
5021)
+++ trunk/src/arch/i386/include/arch/io.h 2010-01-16 17:53:38 UTC (rev
5022)
@@ -136,6 +136,14 @@
);
}
+/* XXX XXX XXX This is a story from the evil API from hell XXX XXX XXX
+ * We have different functions for memory access in pre-ram stage and ram
+ * stage. Those in pre-ram stage are called write32 and expect the address
+ * first and the address as a pointer type. Those in ram stage are called
+ * writel and expect the datum first and the address as an integer type.
+ * Until all code is checked and fixed, I'll add both versions here now.
+ */
+
static inline void writeb(uint8_t b, volatile void *addr)
{
*(volatile uint8_t *) addr = b;
@@ -166,5 +174,37 @@
return *(volatile uint32_t *) addr;
}
+#if !defined(__PRE_RAM__)
+static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr)
+{
+ return *((volatile uint8_t *)(addr));
+}
+
+static inline __attribute__((always_inline)) uint16_t read16(unsigned long
addr)
+{
+ return *((volatile uint16_t *)(addr));
+}
+
+static inline __attribute__((always_inline)) uint32_t read32(unsigned long
addr)
+{
+ return *((volatile uint32_t *)(addr));
+}
+
+static inline __attribute__((always_inline)) void write8(unsigned long addr,
uint8_t value)
+{
+ *((volatile uint8_t *)(addr)) = value;
+}
+
+static inline __attribute__((always_inline)) void write16(unsigned long addr,
uint16_t value)
+{
+ *((volatile uint16_t *)(addr)) = value;
+}
+
+static inline __attribute__((always_inline)) void write32(unsigned long addr,
uint32_t value)
+{
+ *((volatile uint32_t *)(addr)) = value;
+}
#endif
+#endif
+
Modified: trunk/src/arch/i386/include/arch/romcc_io.h
===
--- trunk/src/arch/i386/include/arch/romcc_io.h 2010-01-16 17:50:55 UTC (rev
5021)
+++ trunk/src/arch/i386/include/arch/romcc_io.h 2010-01-16 17:53:38 UTC (rev
5022)
@@ -3,7 +3,7 @@
#include stdint.h
-
+#ifdef __PRE_RAM__
static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr)
{
return *((volatile uint8_t *)(addr));
@@ -33,6 +33,7 @@
{
*((volatile uint32_t *)(addr)) = value;
}
+#endif
#if CONFIG_MMCONF_SUPPORT
Modified: trunk/src/arch/i386/lib/console.c
===
--- trunk/src/arch/i386/lib/console.c 2010-01-16 17:50:55
Re: [coreboot] [1/2] coreboot cleanup: readl - read32, writel - write32
On 1/16/10 6:41 PM, ron minnich wrote: Wow! 5000 and up version numbers mean Cleanup time! :-) Acked-by: Ronald G. Minnich rminn...@gmail.com :-) We are preparing for another board release, and taking the chance to push some cleanups along the way. Thanks, this went in as r5022. Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Seabios problems
On Sat, Jan 16, 2010 at 12:06:01PM +0100, conged...@voila.fr wrote: Hello Kevin, I can't give you the full log for the keyboard problem. I think this is a timeout issue: when I run Seabios in debuglevel=8, no problem, but if debuglevel=1 or even 4, my keyboard don't want to initialize most of the time. So, I suppose that sending debug data to the port gives time to the keyboard to initialize correctly. The attachment files are the logs you asked me reporting the Vista booting error. Do you use DMA since version 0.5.1 to boot ? Lets try a couple of things. For the keyboard, can you see if this change improves things? In either case, can you send the output it produces? --- a/src/ps2port.c +++ b/src/ps2port.c @@ -62,7 +62,7 @@ i8042_flush(void) return 0; udelay(50); u8 data = inb(PORT_PS2_DATA); -dprintf(7, i8042 flushed %x (status=%x)\n, data, status); +dprintf(1, i8042 flushed %x (status=%x)\n, data, status); } dprintf(1, i8042 timeout on flush\n); Your ps2 port has stale data in it, and I think that is causing the init process to get confused. For the DMA issue, it looks like your drive isn't ready for it. Can you see if this change improves things? --- a/src/ata.c +++ b/src/ata.c @@ -856,6 +856,15 @@ init_drive_ata(struct drive_s *dummy, u16 *buffer) // Register with bcv system. add_bcv_internal(drive_g); +// XXX - set dma mode +struct ata_pio_command cmd; +memset(cmd, 0, sizeof(cmd)); +cmd.command = ATA_CMD_SET_FEATURES; +cmd.feature = 0x03; +cmd.sector_count = 0x22; // mwDMA mode 2 +ret = ata_cmd_nondata(drive_g, cmd); +dprintf(1, set drive=%p dma=%d\n, drive_g, ret); + return drive_g; } Thanks, -Kevin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [2/2] coreboot cleanup: generic IOAPIC setup
Wonderful. Hope we can get some testing :-) Acked-by: Ronald G. Minnich rminn...@gmail.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5023 - in trunk/src: arch/i386 arch/i386/include/arch arch/i386/smp mainboard/asi/mb_5blmp mainboard/bcom/winnetp680 mainboard/gigabyte/ga_2761gxdk mainboard/jetway/j7f24 mainboar
Author: stepan Date: 2010-01-16 19:31:34 +0100 (Sat, 16 Jan 2010) New Revision: 5023 Added: trunk/src/arch/i386/include/arch/ioapic.h Modified: trunk/src/arch/i386/Config.lb trunk/src/arch/i386/include/arch/acpi.h trunk/src/arch/i386/smp/Config.lb trunk/src/arch/i386/smp/Makefile.inc trunk/src/arch/i386/smp/ioapic.c trunk/src/mainboard/asi/mb_5blmp/Options.lb trunk/src/mainboard/bcom/winnetp680/Options.lb trunk/src/mainboard/gigabyte/ga_2761gxdk/Options.lb trunk/src/mainboard/jetway/j7f24/Options.lb trunk/src/mainboard/via/epia-cn/Options.lb trunk/src/mainboard/via/pc2500e/Options.lb trunk/src/northbridge/via/cx700/cx700_lpc.c trunk/src/southbridge/amd/amd8111/amd8111_lpc.c trunk/src/southbridge/amd/sb600/sb600_sm.c trunk/src/southbridge/intel/esb6300/esb6300_lpc.c trunk/src/southbridge/intel/esb6300/esb6300_pic.c trunk/src/southbridge/intel/i3100/i3100_lpc.c trunk/src/southbridge/intel/i82801er/i82801er_lpc.c trunk/src/southbridge/intel/pxhd/pxhd_bridge.c trunk/src/southbridge/nvidia/ck804/ck804_lpc.c trunk/src/southbridge/nvidia/mcp55/mcp55_lpc.c trunk/src/southbridge/sis/sis966/sis966_lpc.c trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Log: coreboot has 13 instances of IOAPIC setup distributed across a lot of components. This patch is a rewrite of the generic IOAPIC setup code. Additionally it drops the other 12 instances of IOAPIC setup code and makes the components use the generic code. Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Ronald G. Minnich rminn...@gmail.com Modified: trunk/src/arch/i386/Config.lb === --- trunk/src/arch/i386/Config.lb 2010-01-16 17:53:38 UTC (rev 5022) +++ trunk/src/arch/i386/Config.lb 2010-01-16 18:31:34 UTC (rev 5023) @@ -70,6 +70,4 @@ dir lib dir boot -if CONFIG_SMP - dir smp -end +dir smp Modified: trunk/src/arch/i386/include/arch/acpi.h === --- trunk/src/arch/i386/include/arch/acpi.h 2010-01-16 17:53:38 UTC (rev 5022) +++ trunk/src/arch/i386/include/arch/acpi.h 2010-01-16 18:31:34 UTC (rev 5023) @@ -425,8 +425,6 @@ gsi_base+=4;\ } while(0); -#define IO_APIC_ADDR 0xfec0UL - #else // CONFIG_GENERATE_ACPI_TABLES #define write_acpi_tables(start) (start) Added: trunk/src/arch/i386/include/arch/ioapic.h === --- trunk/src/arch/i386/include/arch/ioapic.h (rev 0) +++ trunk/src/arch/i386/include/arch/ioapic.h 2010-01-16 18:31:34 UTC (rev 5023) @@ -0,0 +1,46 @@ +/* + * coreboot IOAPIC support + * + * Copyright (C) 2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __I386_ARCH_IOAPIC_H +#define __I386_ARCH_IOAPIC_H + +#define IO_APIC_ADDR 0xfec0UL +#define IO_APIC_INTERRUPTS 24 + +#define ALL(0xff 24) +#define NONE (0) +#define DISABLED (1 16) +#define ENABLED(0 16) +#define TRIGGER_EDGE (0 15) +#define TRIGGER_LEVEL (1 15) +#define POLARITY_HIGH (0 13) +#define POLARITY_LOW (1 13) +#define PHYSICAL_DEST (0 11) +#define LOGICAL_DEST (1 11) +#define ExtINT (7 8) +#define NMI(4 8) +#define SMI(2 8) +#define INT(1 8) + +void setup_ioapic(u32 ioapic_base, u8 ioapic_id); +void clear_ioapic(u32 ioapic_base); + +#endif Modified: trunk/src/arch/i386/smp/Config.lb === --- trunk/src/arch/i386/smp/Config.lb 2010-01-16 17:53:38 UTC (rev 5022) +++ trunk/src/arch/i386/smp/Config.lb 2010-01-16 18:31:34 UTC (rev 5023) @@ -1,8 +1,10 @@ uses CONFIG_GENERATE_MP_TABLE +uses CONFIG_IOAPIC if CONFIG_GENERATE_MP_TABLE object mpspec.o end -#object ioapic.o CONFIG_IOAPIC +if CONFIG_IOAPIC + object ioapic.o +end - Modified: trunk/src/arch/i386/smp/Makefile.inc === --- trunk/src/arch/i386/smp/Makefile.inc2010-01-16 17:53:38 UTC (rev 5022) +++ trunk/src/arch/i386/smp/Makefile.inc2010-01-16 18:31:34 UTC (rev 5023) @@ -1,4 +1,3 @@ obj-$(CONFIG_GENERATE_MP_TABLE) += mpspec.o
[coreboot] [commit] r5024 - trunk/util/msrtool
Author: stuge
Date: 2010-01-16 19:39:35 +0100 (Sat, 16 Jan 2010)
New Revision: 5024
Modified:
trunk/util/msrtool/msrtool.c
Log:
msrtool: More trivial rearrangement
Rename some variables
Remove the 'found' variable which turns out not to be needed anyway
Signed-off-by: Peter Stuge pe...@stuge.se
Acked-by: Peter Stuge pe...@stuge.se
Modified: trunk/util/msrtool/msrtool.c
===
--- trunk/util/msrtool/msrtool.c2010-01-16 18:31:34 UTC (rev 5023)
+++ trunk/util/msrtool/msrtool.c2010-01-16 18:39:35 UTC (rev 5024)
@@ -180,13 +180,13 @@
}
int do_diff(const char *difffn) {
- char tmpfn[20], line[512];
- size_t start, len;
- int ret = 1, found, tmp;
+ char tmpfn[20], line[512], *m1start;
+ size_t len;
+ int ret = 1, tmp, m1pos;
FILE *fin = NULL, *fout = stdout;
uint8_t rev = 0;
uint32_t addr, linenum;
- struct msr mf = MSR1(0), mhw = MSR1(0);
+ struct msr m1 = MSR1(0), m2 = MSR1(0);
if (':' == difffn[0]) {
rev = 1;
@@ -202,20 +202,19 @@
if (!sys-open(cpu, SYS_RDONLY))
goto done;
for (linenum = 1; NULL != fgets(line, sizeof(line), fin); ++linenum) {
- start = (0 == strncmp(0x, line, 2)) ? 2 : 0;
- found = sscanf(line + start, %8x %n%*x, addr, tmp);
- if (found 1)
+ tmp = strncmp(0x, line, 2) ? 0 : 2;
+ if (sscanf(line + tmp, %8x %n%*x, addr, m1pos) 1)
continue;
- start += tmp;
- for (len = strlen(line) - 1; NULL != strchr(\r\n, line[len]);
--len)
- line[len] = 0;
- if (!str2msr(line + start, mf)) {
- fprintf(stderr, %s:%d: invalid MSR value '%s'\n,
difffn, linenum, line + start);
+ m1start = line + tmp + m1pos;
+ for (len = strlen(m1start) - 1; NULL != strchr(\r\n,
m1start[len]); --len)
+ m1start[len] = 0;
+ if (!str2msr(m1start, m1)) {
+ fprintf(stderr, %s:%d: invalid MSR value '%s'\n,
difffn, linenum, m1start);
continue;
}
- if (!sys-rdmsr(cpu, addr, mhw))
+ if (!sys-rdmsr(cpu, addr, m2))
goto done;
- if (diff_msr(fout, addr, rev ? mhw : mf, rev ? mf : mhw))
+ if (diff_msr(fout, addr, rev ? m2 : m1, rev ? m1 : m2))
fprintf(fout, \n);
}
if (!feof(fin))
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [ANNOUNCE] Roda RK886EX (Rocky III+) notebook support
Ladies and Gentlemen, coreboot® is running on a multitude of different computers, ranging from tiny embedded systems as small as the palm of your hand over desktop and server systems to super computers with thousands of nodes. However, one might say that in the area of mobile computers coreboot has to catch up, compared to its support of other devices. Thus, I am especially glad to announce that coresystems GmbH is releasing coreboot® for the Roda RK886EX a.k.a Rocky III+ notebook today. It's a rugged notebook, protected against shock, vibration, dust and humidity: http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html We have been testing various Linux distributions as well as Windows XP and Windows 7 booting on this nice notebook. I want to sincerely thank those who made this project possible with their funding: - secunet Security Networks AG - Bundesamt für Sicherheit in der Informationstechnologie (Federal Office for Information Security, BSI) A big thank you also goes to everyone who worked with coresystems on this project. Best regards, Stefan Reinauer -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] [1/7] Roda RK886EX support: i945 updates
See patch
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: i...@coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
Support a few more i945 variants. With this framework in place it should
be possible to support i955 and i975 relatively easy, too.
early_init.c | 39 +--
raminit.c| 609 ---
2 files changed, 433 insertions(+), 215 deletions(-)
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/northbridge/intel/i945/early_init.c
===
--- src/northbridge/intel/i945/early_init.c (revision 5016)
+++ src/northbridge/intel/i945/early_init.c (working copy)
@@ -92,22 +92,29 @@
u8 reg8;
printk_info(\nIntel(R) );
- reg8 = pci_read_config8(PCI_DEV(0, 0x00, 0), 0x8);
+
+ reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) 5) 4) |
((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) 4) 3);
switch (reg8) {
case 0:
case 1:
printk_info(82945G);
break;
case 2:
- printk_info(82945G/GZ/GC);
+ case 3:
+ printk_info(82945P);
break;
- case 0x80:
- case 0x81:
- case 0x82:
- printk_info(82945P/PL);
+ case 4:
+ printk_info(82945GC);
break;
+ case 5:
+ printk_info(82945GZ);
+ break;
+ case 6:
+ case 7:
+ printk_info(82945PL);
+ break;
default:
- printk_info(Unknown (%02x), reg8);/* Others unknown. */
+ break;
}
printk_info( Chipset\n);
@@ -794,32 +801,26 @@
reg32 |= (1 16);
EPBAR32(EPESD) = reg32;
- EPBAR32(EPLE1D) |= (1 16);
+ EPBAR32(EPLE1D) |= (1 16) | (1 0);
- EPBAR32(EPLE1D) |= (1 0);
-
EPBAR32(EPLE1A) = DEFAULT_DMIBAR;
-#if 0
- EPBAR32(EPLE2D) |= (1 16);
-#endif
- EPBAR32(EPLE2D) |= (1 0);
+ EPBAR32(EPLE2D) |= (1 16) | (1 0);
/* DMI Port Root Topology */
+
reg32 = DMIBAR32(DMILE1D);
reg32 = 0x00ff;
- DMIBAR32(DMILE1D) = reg32;
- reg32 = DMIBAR32(DMILE1D);
reg32 = 0xff00;
reg32 |= (2 16);
+
+ reg32 |= (1 0);
DMIBAR32(DMILE1D) = reg32;
- DMIBAR32(DMILE1D) |= (1 0);
-
DMIBAR32(DMILE1A) = DEFAULT_RCBA;
- DMIBAR32(DMILE2D) |= (1 0);
+ DMIBAR32(DMILE2D) |= (1 16) | (1 0);
DMIBAR32(DMILE2A) = DEFAULT_EPBAR;
Index: src/northbridge/intel/i945/raminit.c
===
--- src/northbridge/intel/i945/raminit.c(revision 5016)
+++ src/northbridge/intel/i945/raminit.c(working copy)
@@ -87,6 +87,46 @@
}
#endif
+static int memclk(void)
+{
+ int offset = 0;
+#ifdef CHIPSET_I945GM
+ offset++;
+#endif
+ switch (((MCHBAR32(CLKCFG) 4) 7) - offset) {
+ case 1: return 400;
+ case 2: return 533;
+ case 3: return 667;
+ default: printk_debug(memclk: unknown register value %x\n,
((MCHBAR32(CLKCFG) 4) 7) - offset);
+ }
+ return -1;
+}
+
+#ifdef CHIPSET_I945GM
+static int fsbclk(void)
+{
+ switch (MCHBAR32(CLKCFG) 7) {
+ case 0: return 400;
+ case 1: return 533;
+ case 3: return 667;
+ default: printk_debug(fsbclk: unknown register value %x\n,
MCHBAR32(CLKCFG) 7);
+ }
+ return -1;
+}
+#endif
+#ifdef CHIPSET_I945GC
+static int fsbclk(void)
+{
+ switch (MCHBAR32(CLKCFG) 7) {
+ case 0: return 1066;
+ case 1: return 533;
+ case 2: return 800;
+ default: printk_debug(fsbclk: unknown register value %x\n,
MCHBAR32(CLKCFG) 7);
+ }
+ return -1;
+}
+#endif
+
static int sdram_capabilities_max_supported_memory_frequency(void)
{
u32 reg32;
@@ -434,6 +474,9 @@
case 667: max_ram_speed = 2; break;
}
+ if (fsbclk() == 533)
+ max_ram_speed = 1;
+
sysinfo-memory_frequency = 0;
sysinfo-cas = 0;
@@ -827,184 +870,274 @@
MCHBAR32(offset+(i*4)) = slew_rate_table[i];
}
-static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
-{
- static const u32 dq2030[] = {
- 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
- 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
- 0x0a090908, 0x0c0b0b0a, 0x0e0d0d0c, 0x1211100f,
- 0x19171513, 0x211f1d1b, 0x2d292623, 0x3f393531
- };
+static const u32 dq2030[] = {
+ 0x08070706, 0x0a090908, 0x0d0c0b0a, 0x12100f0e,
+ 0x1a181614, 0x22201e1c, 0x2a282624, 0x3934302d,
+ 0x0a090908, 0x0c0b0b0a,
[coreboot] [PATCH] [2/7] Roda RK886EX support: ICH7 updates
See patch
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: i...@coresystems.de • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866
ICH7 update
* change the code to use macros names instead of constants in many places
* SMI/ACPI: rework power-off code to work with old Linux kernels (2.6.12.x)
* SMI: Add support for mainboard GPI handler
* SMI: immediate power-off on power button press, if OSPM is not active
* Add fix for some USB errata
* Some register tweaks for mobile systems
* Enable configure SCI on interrupt 9 correctly.
acpi/sleepstates.asl | 10 +++---
i82801gx.h| 31
i82801gx_lpc.c| 54
i82801gx_smi.c| 39 ++
i82801gx_smihandler.c | 75 +++---
i82801gx_usb.c|4 ++
6 files changed, 175 insertions(+), 38 deletions(-)
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Index: src/southbridge/intel/i82801gx/i82801gx.h
===
--- src/southbridge/intel/i82801gx/i82801gx.h (revision 5016)
+++ src/southbridge/intel/i82801gx/i82801gx.h (working copy)
@@ -32,6 +32,8 @@
/* TODO Make sure these don't get changed by stage2 */
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
+
+#define IO_APIC_ADDR 0xfec0
#define HPET_ADDR 0xfed0
#define DEFAULT_RCBA 0xfed1c000
@@ -276,7 +278,20 @@
/* ICH7 PMBASE */
#define PM1_STS0x00
+#define WAK_STS (1 15)
+#define PCIEXPWAK_STS(1 14)
+#define PRBTNOR_STS (1 11)
+#define RTC_STS (1 10)
+#define PWRBTN_STS (1 8)
+#define GBL_STS (1 5)
+#define BM_STS (1 4)
+#define TMROF_STS(1 0)
#define PM1_EN 0x02
+#define PCIEXPWAK_DIS(1 14)
+#define RTC_EN (1 10)
+#define PWRBTN_EN(1 8)
+#define GBL_EN (1 5)
+#define TMROF_EN (1 0)
#define PM1_CNT0x04
#define SLP_EN (1 13)
#define SLP_TYP (7 10)
@@ -290,8 +305,24 @@
#define LV40x16
#define PM2_CNT0x20 // mobile only
#define GPE0_STS 0x28
+#define USB4_STS (1 14)
+#define PME_B0_STS (1 13)
+#define USB3_STS (1 12)
+#define PME_STS (1 11)
+#define BATLOW_STS (1 10)
+#define PCI_EXP_STS (1 9)
+#define RI_STS (1 8)
+#define SMB_WAK_STS (1 7)
+#define TCOSCI_STS (1 6)
+#define AC97_STS (1 5)
+#define USB2_STS (1 4)
+#define USB1_STS (1 3)
+#define SWGPE_STS(1 2)
+#define HOT_PLUG_STS (1 1)
+#define THRM_STS (1 0)
#define GPE0_EN0x2c
#define PME_B0_EN(1 13)
+#define PME_EN (1 11)
#define SMI_EN 0x30
#define EL_SMI_EN (1 25) // Intel Quick Resume Technology
#define INTEL_USB2_EN (1 18) // Intel-Specific USB2 SMI logic
Index: src/southbridge/intel/i82801gx/i82801gx_smihandler.c
===
--- src/southbridge/intel/i82801gx/i82801gx_smihandler.c(revision 5016)
+++ src/southbridge/intel/i82801gx/i82801gx_smihandler.c(working copy)
@@ -25,14 +25,15 @@
#include console/console.h
#include cpu/x86/cache.h
#include cpu/x86/smm.h
+#include device/pci_def.h
#include i82801gx.h
#include i82801gx_power.h
#define DEBUG_SMI
#define APM_CNT0xb2
-#define CST_CONTROL 0x85 // 0x85 crashes the box
-#define PST_CONTROL 0x80 // 0x80 crashes the box
+#define CST_CONTROL 0x85
+#define PST_CONTROL 0x80
#define ACPI_DISABLE 0x1e
#define ACPI_ENABLE 0xe1
#define GNVS_UPDATE 0xea
@@ -88,6 +89,8 @@
if (pm1_sts (1 4)) printk_spew(BM );
if (pm1_sts (1 0)) printk_spew(TMROF );
printk_spew(\n);
+ int reg16 = inw(pmbase + PM1_EN);
+ printk_spew(PM1_EN: %x\n, reg16);
}
/**
@@ -245,7 +248,42 @@
outb(reg8, pmbase + SMI_EN);
}
+static void busmaster_disable_on_bus(int bus)
+{
+int slot, func;
+unsigned int val;
+unsigned char hdr;
+for (slot = 0; slot 0x20; slot++) {
+for (func = 0; func 8; func++) {
+u32 reg32;
+device_t dev = PCI_DEV(bus, slot, func);
+
+val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+if (val == 0x || val == 0x ||
+val == 0x || val == 0x)
+continue;
+
+/* Disable Bus Mastering for this one device */
+reg32 = pci_read_config32(dev, PCI_COMMAND);
+reg32 =
[coreboot] [PATCH] [3/7] Roda RK886EX support: SMSC LPC47N227
See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Add support for the SMSC LPC47n227 SuperI/O chip Kconfig|2 Makefile.inc |1 lpc47n227/Config.lb| 21 ++ lpc47n227/Makefile.inc | 20 ++ lpc47n227/chip.h | 29 +++ lpc47n227/lpc47n227.h | 29 +++ lpc47n227/lpc47n227_early_serial.c | 150 +++ lpc47n227/superio.c| 352 + 8 files changed, 604 insertions(+) Signed-off-by: Stefan Reinauer ste...@coresystems.de Index: src/superio/smsc/Kconfig === --- src/superio/smsc/Kconfig(revision 5016) +++ src/superio/smsc/Kconfig(working copy) @@ -10,5 +10,7 @@ bool config SUPERIO_SMSC_LPC47N217 bool +config SUPERIO_SMSC_LPC47N227 + bool config SUPERIO_SMSC_SMSCSUPERIO bool Index: src/superio/smsc/lpc47n227/Config.lb === --- src/superio/smsc/lpc47n227/Config.lb(revision 0) +++ src/superio/smsc/lpc47n227/Config.lb(revision 0) @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config chip.h +object superio.o Index: src/superio/smsc/lpc47n227/Makefile.inc === --- src/superio/smsc/lpc47n227/Makefile.inc (revision 0) +++ src/superio/smsc/lpc47n227/Makefile.inc (revision 0) @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +obj-$(CONFIG_SUPERIO_SMSC_LPC47N227) += superio.o Index: src/superio/smsc/lpc47n227/superio.c === --- src/superio/smsc/lpc47n227/superio.c(revision 0) +++ src/superio/smsc/lpc47n227/superio.c(revision 0) @@ -0,0 +1,352 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Digital Design Corporation + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM-based driver for SMSC LPC47N227 Super I/O chip. */ + +#include arch/io.h +#include device/device.h +#include device/pnp.h +#include console/console.h +#include device/smbus.h +#include string.h +#include bitops.h +#include uart8250.h +#include assert.h +#include stdlib.h +#include chip.h +#include lpc47n227.h + +// Forward declarations +static void enable_dev(device_t dev); +void lpc47n227_pnp_set_resources(device_t dev); +void lpc47n227_pnp_enable_resources(device_t dev); +void lpc47n227_pnp_enable(device_t dev); +static void
[coreboot] [PATCH] [4/7] Roda RK886EX support: EC Renesas M3885X
See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Add support for Renesas M3885x Embedded Controller Kconfig |1 Makefile.inc|1 renesas/Kconfig |2 + renesas/Makefile.inc|1 renesas/m3885x/Config.lb| 21 +++ renesas/m3885x/Makefile.inc | 20 +++ renesas/m3885x/chip.h | 28 +++ renesas/m3885x/superio.c| 79 8 files changed, 153 insertions(+) Signed-off-by: Stefan Reinauer ste...@coresystems.de Index: src/superio/Makefile.inc === --- src/superio/Makefile.inc(revision 5016) +++ src/superio/Makefile.inc(working copy) @@ -2,6 +2,7 @@ subdirs-y += intel subdirs-y += ite subdirs-y += nsc +subdirs-y += renesas # subdirs-y += serverengines subdirs-y += smsc subdirs-y += via Index: src/superio/Kconfig === --- src/superio/Kconfig (revision 5016) +++ src/superio/Kconfig (working copy) @@ -2,6 +2,7 @@ source src/superio/intel/Kconfig source src/superio/ite/Kconfig source src/superio/nsc/Kconfig +source src/superio/renesas/Kconfig source src/superio/serverengines/Kconfig source src/superio/smsc/Kconfig source src/superio/via/Kconfig Index: src/superio/renesas/Kconfig === --- src/superio/renesas/Kconfig (revision 0) +++ src/superio/renesas/Kconfig (revision 0) @@ -0,0 +1,2 @@ +config SUPERIO_RENESAS_M3885X + bool Index: src/superio/renesas/Makefile.inc === --- src/superio/renesas/Makefile.inc(revision 0) +++ src/superio/renesas/Makefile.inc(revision 0) @@ -0,0 +1 @@ +subdirs-y += m3885x Index: src/superio/renesas/m3885x/Config.lb === --- src/superio/renesas/m3885x/Config.lb(revision 0) +++ src/superio/renesas/m3885x/Config.lb(revision 0) @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config chip.h +object superio.o Index: src/superio/renesas/m3885x/Makefile.inc === --- src/superio/renesas/m3885x/Makefile.inc (revision 0) +++ src/superio/renesas/m3885x/Makefile.inc (revision 0) @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +obj-$(CONFIG_SUPERIO_RENESAS_M3885X) += superio.o Index: src/superio/renesas/m3885x/superio.c === --- src/superio/renesas/m3885x/superio.c(revision 0) +++ src/superio/renesas/m3885x/superio.c(revision 0) @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR
[coreboot] [PATCH] [5/7] Roda RK886EX support: Texas Instruments PCI7420
See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Add support for the Texas Instruments Cardbus+Firewire bridge TI PCI7420 Kconfig |1 Makefile.inc |1 ti/Kconfig| 20 ++ ti/Makefile.inc | 20 ++ ti/pci7420/Config.lb | 22 +++ ti/pci7420/Kconfig| 22 +++ ti/pci7420/Makefile.inc | 22 +++ ti/pci7420/chip.h | 29 + ti/pci7420/pci7420.h | 48 +++ ti/pci7420/pci7420_cardbus.c | 127 ++ ti/pci7420/pci7420_firewire.c | 67 ++ 11 files changed, 379 insertions(+) Signed-off-by: Stefan Reinauer ste...@coresystems.de Index: src/southbridge/Makefile.inc === --- src/southbridge/Makefile.inc(revision 5016) +++ src/southbridge/Makefile.inc(working copy) @@ -4,4 +4,5 @@ subdirs-y += nvidia subdirs-y += ricoh subdirs-y += sis +subdirs-y += ti subdirs-y += via Index: src/southbridge/Kconfig === --- src/southbridge/Kconfig (revision 5016) +++ src/southbridge/Kconfig (working copy) @@ -4,4 +4,5 @@ source src/southbridge/nvidia/Kconfig source src/southbridge/ricoh/Kconfig source src/southbridge/sis/Kconfig +source src/southbridge/ti/Kconfig source src/southbridge/via/Kconfig Index: src/southbridge/ti/Kconfig === --- src/southbridge/ti/Kconfig (revision 0) +++ src/southbridge/ti/Kconfig (revision 0) @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +source src/southbridge/ti/pci7420/Kconfig Index: src/southbridge/ti/Makefile.inc === --- src/southbridge/ti/Makefile.inc (revision 0) +++ src/southbridge/ti/Makefile.inc (revision 0) @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-$(CONFIG_SOUTHBRIDGE_TI_PCI7420) += pci7420 Index: src/southbridge/ti/pci7420/Kconfig === --- src/southbridge/ti/pci7420/Kconfig (revision 0) +++ src/southbridge/ti/pci7420/Kconfig (revision 0) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config SOUTHBRIDGE_TI_PCI7420 + bool + Index: src/southbridge/ti/pci7420/Config.lb
[coreboot] [PATCH] [6/7] Roda RK886EX support: PCIe tuning
See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 Initial PCIe tuning: Enable Active State Power Management (ASPM) pciexp_device.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) Signed-off-by: Stefan Reinauer ste...@coresystems.de Index: src/devices/pciexp_device.c === --- src/devices/pciexp_device.c (revision 5016) +++ src/devices/pciexp_device.c (working copy) @@ -34,8 +34,16 @@ /* error... */ return; } - // printk_debug(PCIe: tuning %s\n, dev_path(dev)); - /* TODO: Implement PCI Express tuning. */ +#ifdef CONFIG_PCIE_TUNING + printk_debug(PCIe: tuning %s\n, dev_path(dev)); + + // TODO make this depending on ASPM + /* Enable ASPM Role Based Error Reporting */ + u32 reg32; + reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP); + reg32 |= PCI_EXP_DEVCAP_RBER; + pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32); +#endif } unsigned int pciexp_scan_bus(struct bus *bus, -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] [1/7] Roda RK886EX support: i945 updates
I'm good with acking the entire series Acked-by: Ronald G. Minnich rminn...@gmail.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] msrtool: Read both values in diff mode from file [was: coreboot and MSM800BEV]
Stefan Reinauer wrote:
(It would be nice to have msrtool diff mode available in coreinfo,
using a file stored in cbfs for comparison!)
I think a diff mode would be better implemented in msrtool itself
The diff mode has been implemented in msrtool already since first
committed rc1. :) But currently it assumes that diff should always be
between a file and the machine that msrtool is running on.
-- If the machine is able to boot coreinfo, it's quite likely
already that it can also boot a kernel.
This is true!
If not, you're stuck with printk debugging anyways.
Yep. Patches attached for reading both values from the file.
//Peter
From e69272b38a3beeadcf1052ab50631de4750fffaf Mon Sep 17 00:00:00 2001
From: Peter Stuge pe...@stuge.se
Date: Sat, 16 Jan 2010 20:03:16 +0100
Subject: [PATCH 1/2] msrtool: Add endptr to str2msr() showing how many
characters were parsed
This also introduces a small change in the user interface for immediate
mode (-i). Previously, whitespace could separate high and low words in
an MSR as such:
msrtool -i 4c0f='f2f100ff 56960004'
That is no longer allowed, a space character now ends the MSR value. Any
other character can still be used as separator however, so the following
syntax still works as expected:
msrtool -i 4c0f=f2f100ff:56960004
Signed-off-by: Peter Stuge pe...@stuge.se
---
msrtool.c |4 ++--
msrtool.h |2 +-
msrutils.c |9 +
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/msrtool.c b/msrtool.c
index 570f1fb..41e7e2c 100644
--- a/msrtool.c
+++ b/msrtool.c
@@ -208,7 +208,7 @@ int do_diff(const char *difffn) {
m1start = line + tmp + m1pos;
for (len = strlen(m1start) - 1; NULL != strchr(\r\n,
m1start[len]); --len)
m1start[len] = 0;
- if (!str2msr(m1start, m1)) {
+ if (!str2msr(m1start, m1, NULL)) {
fprintf(stderr, %s:%d: invalid MSR value '%s'\n,
difffn, linenum, m1start);
continue;
}
@@ -288,7 +288,7 @@ int main(int argc, char *argv[]) {
fprintf(stderr, missing value in -i
argument!\n);
break;
}
- if (!str2msr(++optarg, msrval))
+ if (!str2msr(++optarg, msrval, NULL))
fprintf(stderr, invalid value in -i
argument!\n);
break;
case 's':
diff --git a/msrtool.h b/msrtool.h
index d8fc00f..cf77b49 100644
--- a/msrtool.h
+++ b/msrtool.h
@@ -170,7 +170,7 @@ const struct msrdef *findmsrdef(const uint32_t addr);
uint32_t msraddrbyname(const char *name);
void dumpmsrdefs(const struct targetdef *t);
int dumpmsrdefsvals(FILE *f, const struct targetdef *t, const uint8_t cpu);
-uint8_t str2msr(char *str, struct msr *msr);
+uint8_t str2msr(char *str, struct msr *msr, char **endptr);
void decodemsr(const uint8_t cpu, const uint32_t addr, const struct msr val);
uint8_t diff_msr(FILE *fout, const uint32_t addr, const struct msr a, const
struct msr b);
diff --git a/msrutils.c b/msrutils.c
index dfb6617..5a5fbd8 100644
--- a/msrutils.c
+++ b/msrutils.c
@@ -193,7 +193,7 @@ int dumpmsrdefsvals(FILE *f, const struct targetdef *t,
const uint8_t cpu) {
* Parse a hexadecimal string into an MSR value.
*
* Leading 0x or 0X is optional, the string is always parsed as hexadecimal.
- * Any non-hexadecimal character can be used to separate the high 32 bits and
+ * Any non-hexadecimal character except ' ' can separate the high 32 bits and
* the low 32 bits. If there is such a separator, high and low values do not
* need to be zero padded. If there is no separator, the last =8 digits are
* the low 32 bits and any characters before them are the high 32 bits.
@@ -205,15 +205,16 @@ int dumpmsrdefsvals(FILE *f, const struct targetdef *t,
const uint8_t cpu) {
* @param str The string to parse. The string must be writable but will be
* restored before return.
* @param msr Pointer to the struct msr where the value will be stored.
+ * @param endptr If endpotr is not NULL, *endptr will point to after the MSR.
* @return 1 on success, 0 on parse failure. msr is unchanged on failure.
*/
-uint8_t str2msr(char *str, struct msr *msr) {
+uint8_t str2msr(char *str, struct msr *msr, char **endptr) {
char c;
size_t len, lo;
if (0 == strncmp(str, 0x, 2) || 0 == strncmp(str, 0X, 2))
str += 2;
len = strspn(str, HEXCHARS);
- if (len = 8 0 == str[len]) {
+ if (len = 8 (0 == str[len] || ' ' == str[len])) {
msr-hi = 0;
lo = 0;
} else if (len = 8) {
@@ -231,7 +232,7 @@ uint8_t str2msr(char *str, struct msr *msr) {
msr-hi = strtoul(str, NULL, 16);
str[lo] = c;
}
- msr-lo = strtoul(str + lo, NULL, 16);
+ msr-lo = strtoul(str + lo, endptr, 16);
Re: [coreboot] [PATCH] [2/7] Roda RK886EX support: ICH7 updates
Stefan Reinauer wrote: ICH7 update * change the code to use macros names instead of constants in many places * SMI/ACPI: rework power-off code to work with old Linux kernels (2.6.12.x) * SMI: Add support for mainboard GPI handler * SMI: immediate power-off on power button press, if OSPM is not active * Add fix for some USB errata * Some register tweaks for mobile systems * Enable configure SCI on interrupt 9 correctly. acpi/sleepstates.asl | 10 +++--- i82801gx.h| 31 i82801gx_lpc.c| 54 i82801gx_smi.c| 39 ++ i82801gx_smihandler.c | 75 +++--- i82801gx_usb.c|4 ++ 6 files changed, 175 insertions(+), 38 deletions(-) Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Peter Stuge pe...@stuge.se -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] [3/7] Roda RK886EX support: SMSC LPC47N227
Stefan Reinauer wrote: Add support for the SMSC LPC47n227 SuperI/O chip Kconfig|2 Makefile.inc |1 lpc47n227/Config.lb| 21 ++ lpc47n227/Makefile.inc | 20 ++ lpc47n227/chip.h | 29 +++ lpc47n227/lpc47n227.h | 29 +++ lpc47n227/lpc47n227_early_serial.c | 150 +++ lpc47n227/superio.c| 352 + 8 files changed, 604 insertions(+) Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Peter Stuge pe...@stuge.se -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] [4/7] Roda RK886EX support: EC Renesas M3885X
Stefan Reinauer wrote: Add support for Renesas M3885x Embedded Controller Kconfig |1 Makefile.inc|1 renesas/Kconfig |2 + renesas/Makefile.inc|1 renesas/m3885x/Config.lb| 21 +++ renesas/m3885x/Makefile.inc | 20 +++ renesas/m3885x/chip.h | 28 +++ renesas/m3885x/superio.c| 79 8 files changed, 153 insertions(+) Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Peter Stuge pe...@stuge.se -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] [5/7] Roda RK886EX support: Texas Instruments PCI7420
Stefan Reinauer wrote: Add support for the Texas Instruments Cardbus+Firewire bridge TI PCI7420 Kconfig |1 Makefile.inc |1 ti/Kconfig| 20 ++ ti/Makefile.inc | 20 ++ ti/pci7420/Config.lb | 22 +++ ti/pci7420/Kconfig| 22 +++ ti/pci7420/Makefile.inc | 22 +++ ti/pci7420/chip.h | 29 + ti/pci7420/pci7420.h | 48 +++ ti/pci7420/pci7420_cardbus.c | 127 ++ ti/pci7420/pci7420_firewire.c | 67 ++ 11 files changed, 379 insertions(+) Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Peter Stuge pe...@stuge.se -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] [6/7] Roda RK886EX support: PCIe tuning
Stefan Reinauer wrote: Initial PCIe tuning: Enable Active State Power Management (ASPM) pciexp_device.c | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Peter Stuge pe...@stuge.se -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] [7/7] Roda RK886EX support: mainboard and build target
Stefan Reinauer wrote:
+++ src/mainboard/roda/rk886ex/Kconfig(revision 0)
@@ -0,0 +1,62 @@
+config BOARD_RODA_RK886EX
+ bool RK886EX
+ select ARCH_X86
+ select CPU_INTEL_CORE
+ select CPU_INTEL_SOCKET_MFCPGA478
+ select NORTHBRIDGE_INTEL_I945
+ select SOUTHBRIDGE_INTEL_I82801GX
+ select SUPERIO_WINBOND_W83627THG
Shouldn't this also select the EC with SUPERIO_RENESAS_.. ?
+config MAINBOARD_DIR
+ string
+ default kontron/986lcd-m
+ depends on BOARD_RODA_RK886EX
Hmm.
+ /* Pack GNVS into the ACPI table area */
+ for (i=0; i dsdt-length; i++) {
+ if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
:)
+ printk_info(ACPI: done.\n);
For another day it would be nice to somehow factor out most of this
ACPI stuff into a generic acpi_write_tables().
+++ src/mainboard/roda/rk886ex/auto.c (revision 0)
..
+static void init_artec_dongle(void)
+{
+ // Enable 4MB decoding
+ outb(0xf1, 0x88);
+ outb(0xf4, 0x88);
+}
Could this go in lib/ or something? It's useful for all boards after
all..
+#include cbmem.h
+
+// Now, this needs to be included because it relies on the symbol
+// __PRE_RAM__ being set during CAR stage (in order to compile the
+// BSS free versions of the functions). Either rewrite the code
+// to be always BSS free, or invent a flag that's better suited than
+// __PRE_RAM__ to determine whether we're in ram init stage (stage 1)
+//
+#include lib/cbmem.c
Huh?
+void real_main(unsigned long bist)
+{
..
+ /* This has to happen after i945_early_initialization() */
+ init_artec_dongle();
Should this call be there?
+++ src/mainboard/roda/rk886ex/rtl8168.c (revision 0)
..
+/* This code should work for all ICH* southbridges with a NIC. */
Better to have it in southbridge/ than mainboard/ then?
+static void nic_init(struct device *dev)
+{
+ printk_debug(Initializing RTL8168 Gigabit Ethernet\n);
+ // Nothing to do yet, but this has to be here to keep
+ // coreboot from trying to execute an option ROM.
+}
Ouuch.. Really? That's something I would like to set in devicetree.cb
instead.
In general though, it is
Acked-by: Peter Stuge pe...@stuge.se
--
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Re: [coreboot] [PATCH] [7/7] Roda RK886EX support: mainboard and build target
So who wants to write the slashdot article for German gov't funds coreboot port for laptop? Cool laptop -- if you're strong enough to carry it :-) ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [ANNOUNCE] Roda RK886EX (Rocky III+) notebook support
Hi Stefan, Absolutely awesome! Congratulations! This is really great news. On 16.01.2010 20:09, Stefan Reinauer wrote: I am especially glad to announce that coresystems GmbH is releasing coreboot® for the Roda RK886EX a.k.a Rocky III+ notebook today. It's a rugged notebook, protected against shock, vibration, dust and humidity: http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html We have been testing various Linux distributions as well as Windows XP and Windows 7 booting on this nice notebook. And full Windows/Linux support also means this is a device that can be used by non-technical people who do not know anything about coreboot. It also is a great vehicle to demonstrate to vendors how well coreboot can work. Regards, Carl-Daniel -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
