Re: [RFC PATCH v5 0/1] drivers: mfd: Versatile Express SPC support
On Tue, 2013-07-16 at 17:05 +0100, Lorenzo Pieralisi wrote: /drivers/mfd is probably not the right place for this code as it stands (but probably will be when the entire driver, with DVFS and config interface, is complete). Not that it really matters now, but my vexpress-sysreg rework will - most likely - leave only skeleton in the MFD (registering mfd_cells) and other stuff is going to be spread all around. Then I'm planning to move the remaining of the vexpress-specific initialization to drivers/platform/arm/vexpress.c, so maybe sticking vexpress-spc.c to this (non-existing yet) directory would be the right thing to do? Other than that: Acked-by: Pawel Moll pawel.m...@arm.com Thanks! Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [RFC PATCH v5 0/1] drivers: mfd: Versatile Express SPC support
On Wed, 2013-07-17 at 13:33 +0100, Nicolas Pitre wrote: If this is really miscelaneous code that really doesn't fit anywhere else, it should rather go into drivers/misc/ as a last resort. Interestingly enough drivers/misc was my first choice for all the vexpress stuff, but it wasn't received well... Anyway, the SPC driver as it is now seem to be a power management system driver. Maybe a relevant directory would be in place? Wouldn't PSCI belong there as well? (there are two psci.c files in arch/arm and arch/arm64, surprisingly similar ones ;-) The bottom line is: today it is not an MFD driver. Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [RFC PATCH v5 0/1] drivers: mfd: Versatile Express SPC support
On Wed, 2013-07-17 at 15:16 +0100, Nicolas Pitre wrote: On Wed, 17 Jul 2013, Pawel Moll wrote: On Wed, 2013-07-17 at 13:33 +0100, Nicolas Pitre wrote: If this is really miscelaneous code that really doesn't fit anywhere else, it should rather go into drivers/misc/ as a last resort. Interestingly enough drivers/misc was my first choice for all the vexpress stuff, but it wasn't received well... Anyway, the SPC driver as it is now seem to be a power management system driver. Maybe a relevant directory would be in place? Wouldn't PSCI belong there as well? (there are two psci.c files in arch/arm and arch/arm64, surprisingly similar ones ;-) The bottom line is: today it is not an MFD driver. But we know it will, right? So better save some churn by storing the initial code where it would end up anyway once complete. Not in that form, no. The code living in mfd will just register mfd_cells while functional parts are going to live elsewhere. This is how I understand what Samuel asked me to do and that's what is happening to vexpress-sysreg now. Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [RFC PATCH v3 0/2] drivers: mfd: Versatile Express SPC support
On Wed, 2013-06-19 at 13:37 +0100, Arnd Bergmann wrote: I think when vexpress-sysreg was created, we didn't have the syscon driver yet, otherwise I think we should have used that, and put separate drivers on top. Not sure if it's too late for changing it to that now, given that we already have a binding. I will have a look try to use the syscon stuff for generic configuration bits and pieces... That would end up eliminating the sysreg driver, aside from maybe a one-line change to the syscon driver to allow it to probe the right device. ... but sysreg does more than just that. In particular it provides a pseudo-gpio controller (I don't think you want to hide this behind the syscon) *and* it can act as a bridge to the configuration bus - see below. In short - no, I don't think sysreg driver can disappear. It can be reduced in size, yes. 3. Move vexpress-config into drivers/bus as it is (however I see no one in MAINTAINERS for this directory) ISTR that Arnd originally created that directory, so he may help here. Arnd also had some concerns about implementing this code as a bus, mostly about it not being a discoverable bus. IMHO that's a valid concern, and this is why you ended up putting it under MFD which can be seen as some sort of platform devices bus. But I still believe the bus API would make this code look cleaner and easier to maintain. Sorry, I don't see why it would be a bus. I assume that there is code missing somewhere that is not yet merged, right? Well, different VE components (configuration microcontrollers on motherboard and daughterboards in particular) talk to each other over a bus (an SPI derivative, in case you were wondering). So there is a bus. A non-discoverable one, but it does 42 (approximately ;-) different things. We already have: clk, hwmon, regulator and reset drivers using it. And, to make things more complicated, the SPC in question, can act as a bridge to *some* of the functions as well. What's a difference? About 190ms, in at least one case - accessing the energy monitor data (hwmon) can take up to 200ms going through sysreg and about 10ms going through SPC. And there are people interesting in getting this numbers as often as possible. But (obviously, to make things even more complex() only the daughterboard's components can be accessed through it. Eg. the motherboard clock generators must still be accessed through sysregs. Hope you see why the problem is not trivial. Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [RFC PATCH v3 0/2] drivers: mfd: Versatile Express SPC support
On Wed, 2013-06-19 at 16:03 +0100, Arnd Bergmann wrote: On Wednesday 19 June 2013, Pawel Moll wrote: ... but sysreg does more than just that. In particular it provides a pseudo-gpio controller (I don't think you want to hide this behind the syscon) and it can act as a bridge to the configuration bus - see below. In short - no, I don't think sysreg driver can disappear. It can be reduced in size, yes. As I said, the gpio part can be a separate driver that just handles gpio, I've already promised Samuel that. and I think the configuration bridge can be part of the vexpress-config driver, building on top of syscon. I'm not completely sure about the latter part. I don't think so, no. I appreciate what you are trying to say, but I object to mixing ideas for the sake of reducing number of files. The config infrastructure is completely independent from the sysreg. Each of them can exist on its own. The only common thing is a (slightly baroque) communication interface between those two. 3. Move vexpress-config into drivers/bus as it is (however I see no one in MAINTAINERS for this directory) ISTR that Arnd originally created that directory, so he may help here. Arnd also had some concerns about implementing this code as a bus, mostly about it not being a discoverable bus. IMHO that's a valid concern, and this is why you ended up putting it under MFD which can be seen as some sort of platform devices bus. But I still believe the bus API would make this code look cleaner and easier to maintain. Sorry, I don't see why it would be a bus. I assume that there is code missing somewhere that is not yet merged, right? Well, different VE components (configuration microcontrollers on motherboard and daughterboards in particular) talk to each other over a bus (an SPI derivative, in case you were wondering). So there is a bus. A non-discoverable one, but it does 42 (approximately ;-) different things. We already have: clk, hwmon, regulator and reset drivers using it. Ah, got it. In this case I think what you are looking for is a custom 'regmap' interface that abstracts those devices. Regmap can already cover i2c, spi and mmio based sets of registers (syscon is one example for mmio), and IIRC there is a simple way of extending it to other register-level interfaces like this one. This is an interesting idea. The thing that worries me the most is its early (pre-slab) availability, but I will give it a try. Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [RFC PATCH v3 0/2] drivers: mfd: Versatile Express SPC support
Morning, Samuel, On Tue, 2013-06-18 at 10:09 +0100, Samuel Ortiz wrote: Hi Pawell, Double l in the wrong place ;-) If you feel strongly about it, I'm ready to split it into mfd_cells and move the gpio and leds code into separate drivers, however I'm not convinced that it's worth the effort. Well, after seeing your last patch for ifdef'ing the GPIO and LED code, I think it is worth the effort. Good point. But as this - obviously - won't happen on time for 3.11, I hope you would be kind enough to take the #ifdef patch in for now. Now, as to the vexpress-config.c... The first time I've posted the series, all parts lived in driver/misc(/vexpress), but (if I remember correctly) Arnd had some feelings about misc existence at all... I was thinking about a separate directory for random system/platform/machine configuration drivers, but the idea didn't get any traction. drivers/misc would already have been a nicer option imo. Ok. Quite conveniently Arnd is the driver/misc maintainer so I'll get first-hand feedback on this. Not only that, but the whole vexpress-config code design is not the nicest piece of code I've ever seen. And I'm usually not picky. e.g. the whole vexpress-config ad-hoc API is awkward and I wonder if it could be implemented as a bus instead. Funny you mention this :-) Again, the first version actually was a vexpress-config bus. The feedback was - a whole bus_type is over the top (I'm simplifying the letter slightly but this was the spirit). I think it would make sense to have it under drivers/bus/. It might be a little over the top, but when I look at the current code I'd be really happy to read an over-the-top bus driver instead. At least we'd know straight away what youre trying to achieve with this code and it would probably remove a fair chunk of the weird bridge API (the registering and the function reference stuff). Do you have a reference for the patch first version ? http://thread.gmane.org/gmane.linux.ports.arm.kernel/185014/focus=185019 So to summarize - I'm open to any suggestions and ready to spend time on this stuff. I'd say splitting the sysreg driver and leaving only the MFD bits in the MFD driver would be a first step. Also, re-considering the bus implementation for the config part would also be interesting. Ok, so what I'll do: 1. Split vexpress-sysreg into * gpio driver * leds driver * the rest (still in mfd though) 2. Move the vexpress-sysreg platform management functions into misc (unless we get any better place for it) 3. Move vexpress-config into drivers/bus as it is (however I see no one in MAINTAINERS for this directory) 4. *Try* to use more of the standard bus (aka bus_type) infrastructure, however this will be the trickiest part of this all - as I've mentioned the code must be functional before SLAB is up... You shall see some patches before 3.11-rc1. Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [RFC PATCH v3 2/2] drivers: mfd: vexpress: add Serial Power Controller (SPC) support
On Thu, 2013-06-13 at 23:52 +0100, Olof Johansson wrote: + reg = 0 0x7FFF 0 0x1000; #size-cells 2 on the parent bus? That's somewhat unusual. LPAE == 40 bit physical addresses == potential 32 bit sizes (memory blocks 4GB) Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [RFC PATCH v3 0/2] drivers: mfd: Versatile Express SPC support
On Thu, 2013-06-13 at 01:13 +0100, Samuel Ortiz wrote: Now, about the driver itself, besides the really odd code design, the static variables all over the place, the nasty init hacks and the unneeded long function names, someone should refresh my memory and explain to me why is this guy under mfd. I can see it somehow supports IP blocks providing different functions, but the design is not sharing anything with most of the rest of the mfd drivers. I belive the vexpress-sysreg.c is a Multi Function Device by all means. It does so many things that only a water fountain is missing ;-) If you feel strongly about it, I'm ready to split it into mfd_cells and move the gpio and leds code into separate drivers, however I'm not convinced that it's worth the effort. Now, as to the vexpress-config.c... The first time I've posted the series, all parts lived in driver/misc(/vexpress), but (if I remember correctly) Arnd had some feelings about misc existence at all... I was thinking about a separate directory for random system/platform/machine configuration drivers, but the idea didn't get any traction. Not only that, but the whole vexpress-config code design is not the nicest piece of code I've ever seen. And I'm usually not picky. e.g. the whole vexpress-config ad-hoc API is awkward and I wonder if it could be implemented as a bus instead. Funny you mention this :-) Again, the first version actually was a vexpress-config bus. The feedback was - a whole bus_type is over the top (I'm simplifying the letter slightly but this was the spirit). FWIW I take the blame here for not reviewing the initial driver submission that Arnd kindly sent to me...But now that I'm looking at it, I think it really is on the edge of being staging material. Any thought on that ? I'm more than happy to improve it. The infrastructure (as in: the hardware) itself is slightly strange and the code pretty much reflects the situation. There is also a very good reason for some of the oddities like static bridges array etc - the infrastructure must be functional very early, long before slab is available (this also caused a lot of issues with the bus-based implementation, as the device model does kmalloc all over the place). So to summarize - I'm open to any suggestions and ready to spend time on this stuff. Regards and thanks for your time! Pawel ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[RFC v2] video: ARM CLCD: Add DT CDF support
This patch adds basic DT bindings for the PL11x CLCD cells
and make their fbdev driver use them, together with the
Common Display Framework.
The DT provides information about the hardware configuration
and limitations (eg. the largest supported resolution)
but the video modes come exclusively from the Common
Display Framework drivers, referenced to by the standard CDF
binding.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
.../devicetree/bindings/video/arm,pl11x.txt| 35 +++
drivers/video/Kconfig |1 +
drivers/video/amba-clcd.c | 247
include/linux/amba/clcd.h |2 +
4 files changed, 285 insertions(+)
create mode 100644 Documentation/devicetree/bindings/video/arm,pl11x.txt
diff --git a/Documentation/devicetree/bindings/video/arm,pl11x.txt
b/Documentation/devicetree/bindings/video/arm,pl11x.txt
new file mode 100644
index 000..ee9534a
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/arm,pl11x.txt
@@ -0,0 +1,35 @@
+* ARM PrimeCell Color LCD Controller (CLCD) PL110/PL111
+
+Required properties:
+
+- compatible : must be one of:
+ arm,pl110, arm,primecell
+ arm,pl111, arm,primecell
+- reg : base address and size of the control registers block
+- interrupts : the combined interrupt
+- clocks : phandles to the CLCD (pixel) clock and the APB clocks
+- clock-names : clcdclk, apb_pclk
+- display : phandle to the display entity connected to the controller
+
+Optional properties:
+
+- label : string describing the controller location and/or usage
+- video-ram : phandle to DT node of the specialized video RAM to be used
+- max-hactive : maximum frame buffer width in pixels
+- max-vactive : maximum frame buffer height in pixels
+- max-bpp : maximum number of bits per pixel
+- big-endian-pixels : defining this property makes the pixel bytes being
+ accessed in Big Endian organization
+
+Example:
+
+ clcd@1f {
+ compatible = arm,pl111, arm,primecell;
+ reg = 0x1f 0x1000;
+ interrupts = 14;
+ clocks = v2m_oscclk1, smbclk;
+ clock-names = clcdclk, apb_pclk;
+ label = IOFPGA CLCD;
+ video-ram = v2m_vram;
+ display = v2m_muxfpga;
+ };
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 281e548..bad8166 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -340,6 +340,7 @@ config FB_ARMCLCD
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
+ select FB_MODE_HELPERS if OF
help
This framebuffer device driver is for the ARM PrimeCell PL110
Colour LCD controller. ARM PrimeCells provide the building
diff --git a/drivers/video/amba-clcd.c b/drivers/video/amba-clcd.c
index 0a2cce7..853f74c 100644
--- a/drivers/video/amba-clcd.c
+++ b/drivers/video/amba-clcd.c
@@ -25,6 +25,11 @@
#include linux/amba/clcd.h
#include linux/clk.h
#include linux/hardirq.h
+#include linux/dma-mapping.h
+#include linux/of.h
+#include linux/of_address.h
+#include video/display.h
+#include video/videomode.h
#include asm/sizes.h
@@ -62,6 +67,10 @@ static void clcdfb_disable(struct clcd_fb *fb)
{
u32 val;
+ if (fb-panel-display)
+ display_entity_set_state(fb-panel-display,
+ DISPLAY_ENTITY_STATE_OFF);
+
if (fb-board-disable)
fb-board-disable(fb);
@@ -115,6 +124,11 @@ static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
*/
if (fb-board-enable)
fb-board-enable(fb);
+
+ if (fb-panel-display)
+ display_entity_set_state(fb-panel-display,
+ DISPLAY_ENTITY_STATE_ON);
+
}
static int
@@ -304,6 +318,13 @@ static int clcdfb_set_par(struct fb_info *info)
clcdfb_enable(fb, regs.cntl);
+ if (fb-panel-display) {
+ struct videomode mode;
+
+ videomode_from_fb_var_screeninfo(fb-fb.var, mode);
+ display_entity_update(fb-panel-display, mode);
+ }
+
#ifdef DEBUG
printk(KERN_INFO
CLCD: Registers set to\n
@@ -542,6 +563,229 @@ static int clcdfb_register(struct clcd_fb *fb)
return ret;
}
+#if defined(CONFIG_OF)
+static int clcdfb_of_get_tft_parallel_panel(struct clcd_panel *panel,
+ struct display_entity_interface_params *params)
+{
+ int r = params-p.tft_parallel.r_bits;
+ int g = params-p.tft_parallel.g_bits;
+ int b = params-p.tft_parallel.b_bits;
+
+ /* Bypass pixel clock divider, data output on the falling edge */
+ panel-tim2 = TIM2_BCD | TIM2_IPC
[RFC 00/10] Versatile Express CLCD DVI output support
Hello All, This series implements support for the Versatile Express video output pipeline, which is not the simplest one available... It is meant as a RFC only and I'm hoping to attract all possible feedback (*including* naming ;-). The VE's MultiMedia Bus [1] comprises three video signal sources (motherboard's CLCD cell and a implementation-specific driver on each of the daugtherboards) and a FPGA multiplexer routing data from one of the sources to DVI/HDMI formatter chip (Sii9022). +-+ | DB1 |--+ DVI connector +-+ | +--+ +--+ +--| | |oo| +-+ | mux |+-+|oo| | DB2 |-| |--| sii9022 |--|oo| +-+ | FPGA |+-+|oo| +--| | |oo| +-+ | +--+ +--+ | MB |--+ +-+ The series is based on Laurent Pinchart's Common Display Framework patch (not in mainline yet, v2 discussed here: [2]) and extends it by adding DT bindings and basic support for TFT panels. The CLCD driver has been adapted to work with the framework and the Device Tree information. Also a set of drivers for the VE-specific components is included (note that the sii9022 is now driven via the moterboard firmware; this is intended to be replaced by a proper I2C driver for the chip). It is worth mentioning that the CDF caters for both fbdev and DRM so the solution should be suitable for all potential DRM-driven display controllers. [1] http://infocenter.arm.com/help/topic/com.arm.doc.dui0447h/CHDEHEAA.html#CACGIGGC [2] http://thread.gmane.org/gmane.linux.drivers.video-input-infrastructure/57298 Laurent Pinchart (1): video: Add generic display entity core Pawel Moll (9): video: display: Update the display with the video mode data video: display: Add Device Tree bindings video: display: Add generic TFT display type fbmon: Add extra video helper video: ARM CLCD: Add DT CDF support mfd: vexpress: Allow external drivers to parse site ids video: Versatile Express MUXFPGA driver video: Versatile Express DVI mode driver ARM: vexpress: Add CLCD Device Tree properties .../testing/sysfs-driver-video-vexpress-muxfpga|5 + .../devicetree/bindings/video/arm,pl11x.txt| 35 ++ .../devicetree/bindings/video/display-bindings.txt | 75 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi| 17 +- arch/arm/boot/dts/vexpress-v2m.dtsi| 17 +- arch/arm/boot/dts/vexpress-v2p-ca9.dts |5 + drivers/mfd/vexpress-sysreg.c |5 + drivers/video/Kconfig |2 + drivers/video/Makefile |5 + drivers/video/amba-clcd.c | 244 +++ drivers/video/display/Kconfig |4 + drivers/video/display/Makefile |1 + drivers/video/display/display-core.c | 447 drivers/video/fbmon.c | 29 ++ drivers/video/vexpress-dvimode.c | 158 +++ drivers/video/vexpress-muxfpga.c | 228 ++ include/linux/amba/clcd.h |2 + include/linux/fb.h |3 + include/linux/vexpress.h |2 + include/video/display.h| 172 20 files changed, 1448 insertions(+), 8 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-driver-video-vexpress-muxfpga create mode 100644 Documentation/devicetree/bindings/video/arm,pl11x.txt create mode 100644 Documentation/devicetree/bindings/video/display-bindings.txt create mode 100644 drivers/video/display/Kconfig create mode 100644 drivers/video/display/Makefile create mode 100644 drivers/video/display/display-core.c create mode 100644 drivers/video/vexpress-dvimode.c create mode 100644 drivers/video/vexpress-muxfpga.c create mode 100644 include/video/display.h -- 1.7.10.4 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[RFC 03/10] video: display: Add Device Tree bindings
Modelled after the common clock solution, the bindings
are based on the idea of display entity providers and
consumers.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
.../devicetree/bindings/video/display-bindings.txt | 75 +
drivers/video/display/display-core.c | 84
include/video/display.h| 11 +++
3 files changed, 170 insertions(+)
create mode 100644 Documentation/devicetree/bindings/video/display-bindings.txt
diff --git a/Documentation/devicetree/bindings/video/display-bindings.txt
b/Documentation/devicetree/bindings/video/display-bindings.txt
new file mode 100644
index 000..6d8b888
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/display-bindings.txt
@@ -0,0 +1,75 @@
+[this is an RFC]
+
+Common Display Framework define a display entity (eg. LCD panel),
+being a sink for video data generated by a video signal generator
+(eg. LCD controller/driver).
+
+This set of bindings allow to represent connections between them
+in the Device Tree.
+
+Devices nodes representing display sinks are called display
+providers and nodes representing display sources are called
+display consumers.
+
+Notice that in both cases a device represented by a node can
+provide or consume more than one display entity. For example
+a LCD controller can be able to driver more than one LCD
+panel at the same time, while a panel (or a special signal
+multiplexer) may have more than one input (sink) and switch
+between them.
+
+== Display provider ==
+
+Required properties:
+
+* #clock-cells:Number of cells in the display specifier. Typically
+ 0 for nodes providing single display entity and 1
+ for nodes providing multiple displays.
+
+Example:
+ dvi-output: dvi-output@0 {
+ #display-cells = 0;
+ };
+
+== Display consumer ==
+
+Required properties:
+
+* display: List of phandle and clock specifier pairs, one pair
+ for each display (sink). Note: if the display provider
+ specifies '0' for #display-cells, then only the phandle
+ portion of the pair will appear.
+
+Example:
+
+ display-driver {
+ display = dvi-output;
+ };
+
+== Larger example ==
+
+ clcd@1002 {
+ compatible = arm,pl111, arm,primecell;
+ reg = 0x1002 0x1000;
+ interrupts = 0 44 4;
+ clocks = oscclk1, oscclk2;
+ clock-names = clcdclk, apb_pclk;
+ label = V2P-CA9 CLCD;
+ display = v2m_muxfpga 0xf;
+ max-hactive = 1024;
+ max-vactive = 768;
+ max-bpp = 16;
+ };
+
+ v2m_muxfpga: muxfpga@0 {
+ compatible = arm,vexpress-muxfpga;
+ arm,vexpress-sysreg,func = 7 0;
+ #display-cells = 1;
+ display = v2m_dvimode;
+ };
+
+ v2m_dvimode: dvimode@0 {
+ compatible = arm,vexpress-dvimode;
+ arm,vexpress-sysreg,func = 11 0;
+ #display-cells = 0;
+ };
diff --git a/drivers/video/display/display-core.c
b/drivers/video/display/display-core.c
index 4b8e45a..9827a5d 100644
--- a/drivers/video/display/display-core.c
+++ b/drivers/video/display/display-core.c
@@ -15,6 +15,7 @@
#include linux/list.h
#include linux/module.h
#include linux/mutex.h
+#include linux/slab.h
#include video/display.h
#include video/videomode.h
@@ -230,6 +231,89 @@ void display_entity_put(struct display_entity *entity)
}
EXPORT_SYMBOL_GPL(display_entity_put);
+#if defined(CONFIG_OF)
+struct of_display_entity_provider {
+ struct list_head list;
+ struct device_node *node;
+ struct display_entity *(*get)(struct of_phandle_args *spec, void *data);
+ void *data;
+};
+
+static LIST_HEAD(of_display_entity_providers);
+static DEFINE_MUTEX(of_display_entity_providers_lock);
+
+int of_display_entity_add_provider(struct device_node *node,
+ struct display_entity *(*get)(struct of_phandle_args *spec,
+ void *data), void *data)
+{
+ struct of_display_entity_provider *provider =
+ kzalloc(sizeof(*provider), GFP_KERNEL);
+
+ if (!provider)
+ return -ENOMEM;
+
+ provider-node = of_node_get(node);
+ provider-get = get;
+ provider-data = data;
+
+ mutex_lock(of_display_entity_providers_lock);
+ list_add(provider-list
[RFC 01/10] video: Add generic display entity core
From: Laurent Pinchart laurent.pinchart+rene...@ideasonboard.com
Signed-off-by: Laurent Pinchart laurent.pinch...@ideasonboard.com
---
drivers/video/Kconfig|1 +
drivers/video/Makefile |1 +
drivers/video/display/Kconfig|4 +
drivers/video/display/Makefile |1 +
drivers/video/display/display-core.c | 362 ++
include/video/display.h | 150 ++
6 files changed, 519 insertions(+)
create mode 100644 drivers/video/display/Kconfig
create mode 100644 drivers/video/display/Makefile
create mode 100644 drivers/video/display/display-core.c
create mode 100644 include/video/display.h
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 4c1546f..281e548 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -2456,6 +2456,7 @@ source drivers/video/omap2/Kconfig
source drivers/video/exynos/Kconfig
source drivers/video/mmp/Kconfig
source drivers/video/backlight/Kconfig
+source drivers/video/display/Kconfig
if VT
source drivers/video/console/Kconfig
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 9df3873..b989e8e 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -15,6 +15,7 @@ fb-objs := $(fb-y)
obj-$(CONFIG_VT) += console/
obj-$(CONFIG_LOGO) += logo/
obj-y+= backlight/
+obj-y+= display/
obj-$(CONFIG_EXYNOS_VIDEO) += exynos/
diff --git a/drivers/video/display/Kconfig b/drivers/video/display/Kconfig
new file mode 100644
index 000..1d533e7
--- /dev/null
+++ b/drivers/video/display/Kconfig
@@ -0,0 +1,4 @@
+menuconfig DISPLAY_CORE
+ tristate Display Core
+ ---help---
+ Support common display framework for graphics devices.
diff --git a/drivers/video/display/Makefile b/drivers/video/display/Makefile
new file mode 100644
index 000..bd93496
--- /dev/null
+++ b/drivers/video/display/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_DISPLAY_CORE) += display-core.o
diff --git a/drivers/video/display/display-core.c
b/drivers/video/display/display-core.c
new file mode 100644
index 000..d2daa15
--- /dev/null
+++ b/drivers/video/display/display-core.c
@@ -0,0 +1,362 @@
+/*
+ * Display Core
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * Contacts: Laurent Pinchart laurent.pinch...@ideasonboard.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/export.h
+#include linux/kernel.h
+#include linux/list.h
+#include linux/module.h
+#include linux/mutex.h
+
+#include video/display.h
+#include video/videomode.h
+
+static LIST_HEAD(display_entity_list);
+static LIST_HEAD(display_entity_notifiers);
+static DEFINE_MUTEX(display_entity_mutex);
+
+/*
-
+ * Control operations
+ */
+
+/**
+ * display_entity_set_state - Set the display entity operation state
+ * @entity: The display entity
+ * @state: Display entity operation state
+ *
+ * See enum display_entity_state for information regarding the entity states.
+ *
+ * Return 0 on success or a negative error code otherwise.
+ */
+int display_entity_set_state(struct display_entity *entity,
+enum display_entity_state state)
+{
+ int ret;
+
+ if (entity-state == state)
+ return 0;
+
+ if (!entity-ops.ctrl || !entity-ops.ctrl-set_state)
+ return 0;
+
+ ret = entity-ops.ctrl-set_state(entity, state);
+ if (ret 0)
+ return ret;
+
+ entity-state = state;
+ return 0;
+}
+EXPORT_SYMBOL_GPL(display_entity_set_state);
+
+/**
+ * display_entity_update - Update the display
+ * @entity: The display entity
+ *
+ * Make the display entity ready to receive pixel data and start frame
transfer.
+ * This operation can only be called if the display entity is in STANDBY or ON
+ * state.
+ *
+ * The display entity will call the upstream entity in the video chain to start
+ * the video stream.
+ *
+ * Return 0 on success or a negative error code otherwise.
+ */
+int display_entity_update(struct display_entity *entity)
+{
+ if (!entity-ops.ctrl || !entity-ops.ctrl-update)
+ return 0;
+
+ return entity-ops.ctrl-update(entity);
+}
+EXPORT_SYMBOL_GPL(display_entity_update);
+
+/**
+ * display_entity_get_modes - Get video modes supported by the display entity
+ * @entity The display entity
+ * @modes: Pointer to an array of modes
+ *
+ * Fill the modes argument with a pointer to an array of video modes. The array
+ * is owned by the display entity.
+ *
+ * Return the number of supported modes on success (including 0 if no mode is
+ * supported) or a negative error code otherwise.
+ */
+int
[RFC 05/10] fbmon: Add extra video helper
This function converts the fb_var_screeninfo to the videomode
structure, to be used in fbdev drivers working with the
Common Display Framework.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
drivers/video/fbmon.c | 29 +
include/linux/fb.h|3 +++
2 files changed, 32 insertions(+)
diff --git a/drivers/video/fbmon.c b/drivers/video/fbmon.c
index 7f67099..f0ff2bf 100644
--- a/drivers/video/fbmon.c
+++ b/drivers/video/fbmon.c
@@ -1424,6 +1424,35 @@ int fb_videomode_from_videomode(const struct videomode
*vm,
return 0;
}
EXPORT_SYMBOL_GPL(fb_videomode_from_videomode);
+
+void videomode_from_fb_var_screeninfo(const struct fb_var_screeninfo *var,
+ struct videomode *vm)
+{
+ vm-pixelclock = PICOS2KHZ(var-pixclock) * 1000;
+
+ vm-hactive = var-xres;
+ vm-hfront_porch = var-right_margin;
+ vm-hback_porch = var-left_margin;
+ vm-hsync_len = var-hsync_len;
+
+ vm-vactive = var-yres;
+ vm-vfront_porch = var-lower_margin;
+ vm-vback_porch = var-upper_margin;
+ vm-vsync_len = var-vsync_len;
+
+ vm-dmt_flags = 0;
+ if (var-sync FB_SYNC_HOR_HIGH_ACT)
+ vm-dmt_flags |= VESA_DMT_HSYNC_HIGH;
+ if (var-sync FB_SYNC_VERT_HIGH_ACT)
+ vm-dmt_flags |= VESA_DMT_VSYNC_HIGH;
+
+ vm-data_flags = 0;
+ if (var-vmode FB_VMODE_INTERLACED)
+ vm-data_flags |= DISPLAY_FLAGS_INTERLACED;
+ if (var-vmode FB_VMODE_DOUBLE)
+ vm-data_flags |= DISPLAY_FLAGS_DOUBLESCAN;
+}
+EXPORT_SYMBOL_GPL(videomode_from_fb_var_screeninfo);
#endif
#if IS_ENABLED(CONFIG_OF_VIDEOMODE)
diff --git a/include/linux/fb.h b/include/linux/fb.h
index 58b9860..aae2ed3 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -721,6 +721,9 @@ extern int of_get_fb_videomode(struct device_node *np,
int index);
extern int fb_videomode_from_videomode(const struct videomode *vm,
struct fb_videomode *fbmode);
+extern void videomode_from_fb_var_screeninfo(
+ const struct fb_var_screeninfo *var,
+ struct videomode *vm);
/* drivers/video/modedb.c */
#define VESA_MODEDB_SIZE 34
--
1.7.10.4
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[RFC 04/10] video: display: Add generic TFT display type
TFT panels may be interfaced via a simple parallel interface
carrying RGB data, pixel clock and synchronisation signals.
From the video generator point of view the width of the data
channels (number of bits per R/G/B components) may be an
important factor in setting up the display model.
Above information is based on the presentations by Dave Anders
available here: http://elinux.org/Elc-lcd
This patch adds the parallel TFT display type and basic parameters
structure. Maybe it should be split into a separate header, eg.
include/video/tft.h? Or maybe it's just the INTERFACE_DPI I'm
talking about?
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
include/video/display.h |9 +
1 file changed, 9 insertions(+)
diff --git a/include/video/display.h b/include/video/display.h
index 7fe8b2f..875e230 100644
--- a/include/video/display.h
+++ b/include/video/display.h
@@ -69,10 +69,19 @@ enum display_entity_stream_state {
enum display_entity_interface_type {
DISPLAY_ENTITY_INTERFACE_DPI,
+ DISPLAY_ENTITY_INTERFACE_TFT_PARALLEL,
+};
+
+struct tft_parallel_interface_params {
+ int r_bits, g_bits, b_bits;
+ int r_b_swapped;
};
struct display_entity_interface_params {
enum display_entity_interface_type type;
+ union {
+ struct tft_parallel_interface_params tft_parallel;
+ } p;
};
struct display_entity_control_ops {
--
1.7.10.4
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[RFC 02/10] video: display: Update the display with the video mode data
The display entity (sink) may need to know about the mode being
changed, eg. to update timings.
Alternatively there could be a separate set_mode() operation...
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
drivers/video/display/display-core.c |5 +++--
include/video/display.h |6 --
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/video/display/display-core.c
b/drivers/video/display/display-core.c
index d2daa15..4b8e45a 100644
--- a/drivers/video/display/display-core.c
+++ b/drivers/video/display/display-core.c
@@ -69,12 +69,13 @@ EXPORT_SYMBOL_GPL(display_entity_set_state);
*
* Return 0 on success or a negative error code otherwise.
*/
-int display_entity_update(struct display_entity *entity)
+int display_entity_update(struct display_entity *entity,
+const struct videomode *mode)
{
if (!entity-ops.ctrl || !entity-ops.ctrl-update)
return 0;
- return entity-ops.ctrl-update(entity);
+ return entity-ops.ctrl-update(entity, mode);
}
EXPORT_SYMBOL_GPL(display_entity_update);
diff --git a/include/video/display.h b/include/video/display.h
index 90d18ca..64f84d5 100644
--- a/include/video/display.h
+++ b/include/video/display.h
@@ -77,7 +77,8 @@ struct display_entity_interface_params {
struct display_entity_control_ops {
int (*set_state)(struct display_entity *ent,
enum display_entity_state state);
- int (*update)(struct display_entity *ent);
+ int (*update)(struct display_entity *ent,
+const struct videomode *mode);
int (*get_modes)(struct display_entity *ent,
const struct videomode **modes);
int (*get_params)(struct display_entity *ent,
@@ -111,7 +112,8 @@ struct display_entity {
int display_entity_set_state(struct display_entity *entity,
enum display_entity_state state);
-int display_entity_update(struct display_entity *entity);
+int display_entity_update(struct display_entity *entity,
+const struct videomode *mode);
int display_entity_get_modes(struct display_entity *entity,
const struct videomode **modes);
int display_entity_get_params(struct display_entity *entity,
--
1.7.10.4
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[RFC 09/10] video: Versatile Express DVI mode driver
Versatile Express DVI output is driven by a Sii9022 chip. It can be
controller to a limited extend by the Motherboard Config Controller,
and that's what the driver is doing now. It is a temporary measure
till there's a full I2C driver for the chip.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
drivers/video/Makefile |1 +
drivers/video/vexpress-dvimode.c | 158 ++
2 files changed, 159 insertions(+)
create mode 100644 drivers/video/vexpress-dvimode.c
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 84c6083..9347e00 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -179,3 +179,4 @@ obj-$(CONFIG_OF_VIDEOMODE) += of_videomode.o
# platform specific output drivers
obj-$(CONFIG_VEXPRESS_CONFIG)+= vexpress-muxfpga.o
+obj-$(CONFIG_VEXPRESS_CONFIG)+= vexpress-dvimode.o
diff --git a/drivers/video/vexpress-dvimode.c b/drivers/video/vexpress-dvimode.c
new file mode 100644
index 000..85d5608
--- /dev/null
+++ b/drivers/video/vexpress-dvimode.c
@@ -0,0 +1,158 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2013 ARM Limited
+ */
+
+#define pr_fmt(fmt) vexpress-dvimode: fmt
+
+#include linux/fb.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/vexpress.h
+#include video/display.h
+#include video/videomode.h
+
+
+static struct vexpress_config_func *vexpress_dvimode_func;
+
+
+static int vexpress_dvimode_display_update(struct display_entity *display,
+ const struct videomode *mode)
+{
+ static const struct {
+ u32 hactive, vactive, dvimode;
+ } dvimodes[] = {
+ { 640, 480, 0 }, /* VGA */
+ { 800, 600, 1 }, /* SVGA */
+ { 1024, 768, 2 }, /* XGA */
+ { 1280, 1024, 3 }, /* SXGA */
+ { 1600, 1200, 4 }, /* UXGA */
+ { 1920, 1080, 5 }, /* HD1080 */
+ };
+ int err = -ENOENT;
+ int i;
+
+ for (i = 0; i ARRAY_SIZE(dvimodes); i++) {
+ if (dvimodes[i].hactive == mode-hactive
+ dvimodes[i].vactive == mode-vactive) {
+ pr_debug(mode: %ux%u = %d\n, mode-hactive,
+ mode-vactive, dvimodes[i].dvimode);
+ err = vexpress_config_write(vexpress_dvimode_func, 0,
+ dvimodes[i].dvimode);
+ break;
+ }
+ }
+
+ if (err)
+ pr_warn(Failed to set %ux%u mode! (%d)\n, mode-hactive,
+ mode-vactive, err);
+
+ return err;
+}
+
+static int vexpress_dvimode_display_get_modes(struct display_entity *display,
+ const struct videomode **modes)
+{
+ static const struct videomode m[] = {
+ {
+ /* VGA */
+ .pixelclock = 25175000,
+ .hactive= 640,
+ .hback_porch= 40,
+ .hfront_porch = 24,
+ .vfront_porch = 11,
+ .hsync_len = 96,
+ .vactive= 480,
+ .vback_porch= 32,
+ .vsync_len = 2,
+ }, {
+ /* XGA */
+ .pixelclock = 63500127,
+ .hactive= 1024,
+ .hback_porch= 152,
+ .hfront_porch = 48,
+ .hsync_len = 104,
+ .vactive= 768,
+ .vback_porch= 23,
+ .vfront_porch = 3,
+ .vsync_len = 4,
+ }, {
+ /* SXGA */
+ .pixelclock = 10800,
+ .hactive= 1280,
+ .hback_porch= 248,
+ .hfront_porch = 48,
+ .hsync_len = 112,
+ .vactive= 1024,
+ .vback_porch= 38,
+ .vfront_porch = 1,
+ .vsync_len = 3,
+ },
+ };
+
+ *modes = m;
+
+ return ARRAY_SIZE(m);
+}
+
+static int vexpress_dvimode_display_get_params(struct display_entity *display,
+ struct display_entity_interface_params *params)
+{
+ params-type = DISPLAY_ENTITY_INTERFACE_TFT_PARALLEL;
+ params
[RFC 06/10] video: ARM CLCD: Add DT CDF support
This patch adds basic DT bindings for the PL11x CLCD cells
and make their fbdev driver use them, together with the
Common Display Framework.
The DT provides information about the hardware configuration
and limitations (eg. the largest supported resolution)
but the video modes come exclusively from the Common
Display Framework drivers, referenced to by the standard CDF
binding.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
.../devicetree/bindings/video/arm,pl11x.txt| 35 +++
drivers/video/Kconfig |1 +
drivers/video/amba-clcd.c | 244
include/linux/amba/clcd.h |2 +
4 files changed, 282 insertions(+)
create mode 100644 Documentation/devicetree/bindings/video/arm,pl11x.txt
diff --git a/Documentation/devicetree/bindings/video/arm,pl11x.txt
b/Documentation/devicetree/bindings/video/arm,pl11x.txt
new file mode 100644
index 000..ee9534a
--- /dev/null
+++ b/Documentation/devicetree/bindings/video/arm,pl11x.txt
@@ -0,0 +1,35 @@
+* ARM PrimeCell Color LCD Controller (CLCD) PL110/PL111
+
+Required properties:
+
+- compatible : must be one of:
+ arm,pl110, arm,primecell
+ arm,pl111, arm,primecell
+- reg : base address and size of the control registers block
+- interrupts : the combined interrupt
+- clocks : phandles to the CLCD (pixel) clock and the APB clocks
+- clock-names : clcdclk, apb_pclk
+- display : phandle to the display entity connected to the controller
+
+Optional properties:
+
+- label : string describing the controller location and/or usage
+- video-ram : phandle to DT node of the specialized video RAM to be used
+- max-hactive : maximum frame buffer width in pixels
+- max-vactive : maximum frame buffer height in pixels
+- max-bpp : maximum number of bits per pixel
+- big-endian-pixels : defining this property makes the pixel bytes being
+ accessed in Big Endian organization
+
+Example:
+
+ clcd@1f {
+ compatible = arm,pl111, arm,primecell;
+ reg = 0x1f 0x1000;
+ interrupts = 14;
+ clocks = v2m_oscclk1, smbclk;
+ clock-names = clcdclk, apb_pclk;
+ label = IOFPGA CLCD;
+ video-ram = v2m_vram;
+ display = v2m_muxfpga;
+ };
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 281e548..bad8166 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -340,6 +340,7 @@ config FB_ARMCLCD
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
+ select FB_MODE_HELPERS if OF
help
This framebuffer device driver is for the ARM PrimeCell PL110
Colour LCD controller. ARM PrimeCells provide the building
diff --git a/drivers/video/amba-clcd.c b/drivers/video/amba-clcd.c
index 0a2cce7..778dc03 100644
--- a/drivers/video/amba-clcd.c
+++ b/drivers/video/amba-clcd.c
@@ -25,6 +25,11 @@
#include linux/amba/clcd.h
#include linux/clk.h
#include linux/hardirq.h
+#include linux/dma-mapping.h
+#include linux/of.h
+#include linux/of_address.h
+#include video/display.h
+#include video/videomode.h
#include asm/sizes.h
@@ -62,6 +67,10 @@ static void clcdfb_disable(struct clcd_fb *fb)
{
u32 val;
+ if (fb-panel-display)
+ display_entity_set_state(fb-panel-display,
+ DISPLAY_ENTITY_STATE_OFF);
+
if (fb-board-disable)
fb-board-disable(fb);
@@ -115,6 +124,11 @@ static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
*/
if (fb-board-enable)
fb-board-enable(fb);
+
+ if (fb-panel-display)
+ display_entity_set_state(fb-panel-display,
+ DISPLAY_ENTITY_STATE_ON);
+
}
static int
@@ -304,6 +318,13 @@ static int clcdfb_set_par(struct fb_info *info)
clcdfb_enable(fb, regs.cntl);
+ if (fb-panel-display) {
+ struct videomode mode;
+
+ videomode_from_fb_var_screeninfo(fb-fb.var, mode);
+ display_entity_update(fb-panel-display, mode);
+ }
+
#ifdef DEBUG
printk(KERN_INFO
CLCD: Registers set to\n
@@ -542,6 +563,226 @@ static int clcdfb_register(struct clcd_fb *fb)
return ret;
}
+#if defined(CONFIG_OF)
+static int clcdfb_of_get_tft_parallel_panel(struct clcd_panel *panel,
+ struct display_entity_interface_params *params)
+{
+ int r = params-p.tft_parallel.r_bits;
+ int g = params-p.tft_parallel.g_bits;
+ int b = params-p.tft_parallel.b_bits;
+
+ /* Bypass pixel clock divider, data output on the falling edge */
+ panel-tim2 = TIM2_BCD | TIM2_IPC
[RFC 10/10] ARM: vexpress: Add CLCD Device Tree properties
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 17 +
arch/arm/boot/dts/vexpress-v2m.dtsi | 17 +
arch/arm/boot/dts/vexpress-v2p-ca9.dts |5 +
3 files changed, 31 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index ac870fb..aac9459 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -41,7 +41,7 @@
bank-width = 4;
};
- vram@2, {
+ v2m_vram: vram@2, {
compatible = arm,vexpress-vram;
reg = 2 0x 0x0080;
};
@@ -233,6 +233,12 @@
interrupts = 14;
clocks = v2m_oscclk1, smbclk;
clock-names = clcdclk, apb_pclk;
+ label = IOFPGA CLCD;
+ video-ram = v2m_vram;
+ display = v2m_muxfpga 0;
+ max-hactive = 640;
+ max-vactive = 480;
+ max-bpp = 16;
};
};
@@ -282,7 +288,7 @@
/* CLCD clock */
compatible = arm,vexpress-osc;
arm,vexpress-sysreg,func = 1 1;
- freq-range = 2375 6350;
+ freq-range = 2375 6500;
#clock-cells = 0;
clock-output-names = v2m:oscclk1;
};
@@ -317,9 +323,11 @@
arm,vexpress-sysreg,func = 5 0;
};
- muxfpga@0 {
+ v2m_muxfpga: muxfpga@0 {
compatible = arm,vexpress-muxfpga;
arm,vexpress-sysreg,func = 7 0;
+ #display-cells = 1;
+ display = v2m_dvimode;
};
shutdown@0 {
@@ -332,9 +340,10 @@
arm,vexpress-sysreg,func = 9 0;
};
- dvimode@0 {
+ v2m_dvimode: dvimode@0 {
compatible = arm,vexpress-dvimode;
arm,vexpress-sysreg,func = 11 0;
+ #display-cells = 0;
};
};
};
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi
b/arch/arm/boot/dts/vexpress-v2m.dtsi
index f142036..4d080d0 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -40,7 +40,7 @@
bank-width = 4;
};
- vram@3, {
+ v2m_vram: vram@3, {
compatible = arm,vexpress-vram;
reg = 3 0x 0x0080;
};
@@ -232,6 +232,12 @@
interrupts = 14;
clocks = v2m_oscclk1, smbclk;
clock-names = clcdclk, apb_pclk;
+ label = IOFPGA CLCD;
+ video-ram = v2m_vram;
+ display = v2m_muxfpga 0;
+ max-hactive = 640;
+ max-vactive = 480;
+ max-bpp = 16;
};
};
@@ -281,7 +287,7 @@
/* CLCD clock */
compatible = arm,vexpress-osc;
arm,vexpress-sysreg,func = 1 1;
- freq-range = 2375 6350;
+ freq-range = 2375 6500;
#clock-cells = 0;
clock-output-names = v2m:oscclk1;
};
@@ -316,9 +322,11 @@
arm,vexpress-sysreg,func = 5 0;
};
- muxfpga@0 {
+ v2m_muxfpga: muxfpga@0 {
compatible = arm,vexpress-muxfpga;
arm,vexpress-sysreg,func = 7 0;
+ #display-cells = 1;
+ display = v2m_dvimode;
};
shutdown@0 {
@@ -331,9 +339,10 @@
arm,vexpress-sysreg,func = 9 0;
};
- dvimode@0 {
+ v2m_dvimode: dvimode@0
[RFC 07/10] mfd: vexpress: Allow external drivers to parse site ids
... by providing a function translating the MASTER
value into the currently valid site number and
a _LAST constant providing all possible site id values.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
drivers/mfd/vexpress-sysreg.c |5 +
include/linux/vexpress.h |2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/mfd/vexpress-sysreg.c b/drivers/mfd/vexpress-sysreg.c
index bf75e96..4158e26 100644
--- a/drivers/mfd/vexpress-sysreg.c
+++ b/drivers/mfd/vexpress-sysreg.c
@@ -81,6 +81,11 @@ void vexpress_flags_set(u32 data)
writel(data, vexpress_sysreg_base + SYS_FLAGSSET);
}
+u32 vexpress_get_site(int site)
+{
+ return site == VEXPRESS_SITE_MASTER ? vexpress_master_site : site;
+}
+
u32 vexpress_get_procid(int site)
{
if (site == VEXPRESS_SITE_MASTER)
diff --git a/include/linux/vexpress.h b/include/linux/vexpress.h
index 7581874..1ebbcf5 100644
--- a/include/linux/vexpress.h
+++ b/include/linux/vexpress.h
@@ -19,6 +19,7 @@
#define VEXPRESS_SITE_MB 0
#define VEXPRESS_SITE_DB1 1
#define VEXPRESS_SITE_DB2 2
+#define __VEXPRESS_SITE_LAST 3
#define VEXPRESS_SITE_MASTER 0xf
#define VEXPRESS_CONFIG_STATUS_DONE0
@@ -103,6 +104,7 @@ int vexpress_config_write(struct vexpress_config_func
*func, int offset,
/* Platform control */
+u32 vexpress_get_site(int site);
u32 vexpress_get_procid(int site);
u32 vexpress_get_hbi(int site);
void *vexpress_get_24mhz_clock_base(void);
--
1.7.10.4
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[RFC 08/10] video: Versatile Express MUXFPGA driver
Versatile Express' DVI video output can be connected to one the three
sources - motherboard's CLCD controller or a video signal generated
by one of the daughterboards.
This driver provides a Common Display Framework driver for the
muxer FPGA, which acts as a switch selecting one of the video data
sources. The default source is selected basing on the priority
list (which itself can be modified via module paramter), but
the user can make his own decision about it using the device's
sysfs source attribute.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
.../testing/sysfs-driver-video-vexpress-muxfpga|5 +
drivers/video/Makefile |3 +
drivers/video/vexpress-muxfpga.c | 228
3 files changed, 236 insertions(+)
create mode 100644
Documentation/ABI/testing/sysfs-driver-video-vexpress-muxfpga
create mode 100644 drivers/video/vexpress-muxfpga.c
diff --git a/Documentation/ABI/testing/sysfs-driver-video-vexpress-muxfpga
b/Documentation/ABI/testing/sysfs-driver-video-vexpress-muxfpga
new file mode 100644
index 000..bfd568d
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-video-vexpress-muxfpga
@@ -0,0 +1,5 @@
+What: /sys/bus/platform/drivers/vexpress-muxfpga/muxfpga
device/source
+Date: April 2013
+Contant: Pawel Moll pawel.m...@arm.com
+Description: This file stores the id of the video signal source
+ supposed to be routed to the board's DVI output.
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index b989e8e..84c6083 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -176,3 +176,6 @@ obj-$(CONFIG_DISPLAY_TIMING) += display_timing.o
obj-$(CONFIG_OF_DISPLAY_TIMING) += of_display_timing.o
obj-$(CONFIG_VIDEOMODE) += videomode.o
obj-$(CONFIG_OF_VIDEOMODE) += of_videomode.o
+
+# platform specific output drivers
+obj-$(CONFIG_VEXPRESS_CONFIG)+= vexpress-muxfpga.o
diff --git a/drivers/video/vexpress-muxfpga.c b/drivers/video/vexpress-muxfpga.c
new file mode 100644
index 000..1731ad0
--- /dev/null
+++ b/drivers/video/vexpress-muxfpga.c
@@ -0,0 +1,228 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2013 ARM Limited
+ */
+
+#define pr_fmt(fmt) vexpress-muxfpga: fmt
+
+#include linux/fb.h
+#include linux/of.h
+#include linux/of_device.h
+#include linux/vexpress.h
+#include video/display.h
+#include video/videomode.h
+
+
+static struct vexpress_config_func *vexpress_muxfpga_func;
+static struct display_entity *vexpress_muxfpga_output;
+
+
+static struct vexpress_muxfpga_source {
+ struct display_entity display;
+ struct videomode mode;
+ bool updated;
+} vexpress_muxfpga_sources[__VEXPRESS_SITE_LAST];
+static u32 vexpress_muxfpga_source_site = VEXPRESS_SITE_MB;
+static bool vexpress_muxfpga_source_stored;
+
+
+static int vexpress_muxfpga_set_site(u32 site)
+{
+ int err;
+
+ if (site = ARRAY_SIZE(vexpress_muxfpga_sources))
+ return -EINVAL;
+
+ err = vexpress_config_write(vexpress_muxfpga_func, 0, site);
+ if (!err) {
+ pr_debug(Selected site %d as source\n, site);
+ vexpress_muxfpga_source_site = site;
+ } else {
+ pr_warn(Failed to select site %d as source! (%d)\n,
+ site, err);
+ }
+
+ return err;
+}
+
+static unsigned int vexpress_muxfpga_preferred_sites[] = {
+ VEXPRESS_SITE_MASTER,
+ VEXPRESS_SITE_DB1,
+ VEXPRESS_SITE_DB2,
+ VEXPRESS_SITE_MB,
+};
+static unsigned int vexpress_muxfpga_preferred_sites_num =
+ ARRAY_SIZE(vexpress_muxfpga_preferred_sites);
+module_param_array_named(preferred_sites, vexpress_muxfpga_preferred_sites,
+ uint, vexpress_muxfpga_preferred_sites_num, S_IRUGO);
+MODULE_PARM_DESC(preferred_sites, Preferred order of MUXFPGA (DVI output)
+ sources; values can be a daughterboard site ID (1-2), the
+ motherboard ID (0) or a value describing the master site
+ (0xf).);
+
+static int vexpress_muxfpga_get_priority(u32 site)
+{
+ int i;
+
+ for (i = 0; i vexpress_muxfpga_preferred_sites_num; i++) {
+ u32 preference = vexpress_muxfpga_preferred_sites[i];
+
+ if (site == vexpress_get_site(preference))
+ return i;
+ }
+
+ return INT_MAX;
+}
+
+static void vexpress_muxfpga_set_preffered_site(u32 site)
+{
+ int current_priority = vexpress_muxfpga_get_priority
Re: [RFC PATCH 1/3] amba-clcd: Add Device Tree support to amba-clcd driver
On Fri, 2012-09-21 at 11:35 +0100, Ryan Harkin wrote: Good point. Sorry for my ignorance, but is there a place I should put such documentation? Documentation/devicetree/bindings/fb/amba-clcd.txt :-) When the A9 CoreTile uses the on-tile CLCD controller, it can use DMA to handle the framebuffer. DMA is not available to the motherboard CLCD controller. Uh, you probably mean that the motherboard CLCD must use the specialised video memory, while the one in the test chip would normally use a buffer allocated via the DMA API... I was trying to keep the properties simple, but they are more complex than just the two settings: use_dma and framebuffer. If use_dma is specified, the framebuffer property is not used; in this case, the framebuffer is allocated by the DMA framework and the framebuffer property is ignored. If use_dma is not present or is set to 0, the code uses the framebuffer property to specify the address. I'm not sure if the framebuffer property is really needed, at least in the form you have it there now. I think I know you where you get it from - HDLCD driver, right? It was sort-of-needed there, because we had to reserve memory for the framebuffer, because you couldn't allocate big enough (8MB if I remember correctly) area using the DMA alloc function. But now, with the CMA in place it should be possible, so I believe it's not even necessary in that case. Simply speaking - if the driver is not told what address to use, it should get the memory on its own. Now, as to the motherboard CLCD... That's where you actually could use this property in the way you have there, to enforce the address of the video RAM as the framebuffer. But maybe it would be better to have a phandle to the video RAM node? Cheers! Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v2 08/13] mfd: Versatile Express system registers driver
On Wed, 2012-09-19 at 12:17 +0100, Arnd Bergmann wrote: On Wednesday 19 September 2012, Pawel Moll wrote: On Tue, 2012-09-18 at 16:24 +0100, Arnd Bergmann wrote: On Tuesday 18 September 2012, Pawel Moll wrote: Yes, but I2C devices are created by of_i2c_register_devices() which knows how to interpret the reg property. And here, as these are normal platform devices now (as you suggested), the of_platform_bus_create() will treat it as a normal address, translate it via ranges and create IORESOURCE_MEM out of it... And that's what I wanted to avoid. Maybe unnecessarily? You are right, this is a bit nasty, it should not attempt to do this. Basically the reg parsing logic has a hack to work around apply PowerMac firmware that misses some ranges properties. I think we should change the DT parsing code to not create those resources if there is a bus that can't be translated. Well, I actually think the current solution is fine - the default bus is the platform one, I'm creating a platform device, so the code can assume that reg is a normal address and create an IORESOURCE_MEM from it. It's just that my platform device is not memory mapped, so I don't really want this to happen. One way of working this around would be not using simple-bus as the parent of my config devices, so that normal of_platform_populate() will not create them, and then have a simple dcc driver that will do nothing except for creating platform devices in a custom way. Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [RFC PATCH 2/3] ARM: vexpress: Add device tree support for CLCD driver
On Wed, 2012-09-19 at 17:04 +0100, Ryan Harkin wrote:
Add support for device tree in the amba-clcd PL111 video driver.
Special case support is added for the A9 CoreTile which uses the legacy
address map and has a PL111 device on-board. The default case is to configure
the device on the motherboard.
Oscillator support is added for the A9 CoreTile's CLCD driver.
Signed-off-by: Ryan Harkin ryan.har...@linaro.org
---
arch/arm/mach-vexpress/v2m.c | 58
++
1 file changed, 58 insertions(+)
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 37608f2..799e00e 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -3,6 +3,7 @@
*/
#include linux/device.h
#include linux/amba/bus.h
+#include linux/amba/clcd.h
#include linux/amba/mmci.h
#include linux/io.h
#include linux/init.h
@@ -37,6 +38,7 @@
#include mach/ct-ca9x4.h
#include mach/motherboard.h
+#include plat/clcd.h
#include plat/sched_clock.h
#include core.h
@@ -541,6 +543,54 @@ MACHINE_END
#if defined(CONFIG_ARCH_VEXPRESS_DT)
+static struct v2m_osc v2m_dt_clcd_osc = {
+ .rate_min = 1000,
+ .rate_max = 16500,
+ .rate_default = 2375,
+};
+
+static int v2m_dt_clcd_init(void)
+{
+ struct device_node *node;
+ u32 osc;
+ u32 clcd_site;
+ u32 dvimode;
+ const __be32 *prop;
+ int len, na, ns;
+ phys_addr_t reg_base;
+
+ node = of_find_compatible_node(NULL, NULL, arm,pl111);
+ if (!node)
+ return -ENODEV;
+
+ na = of_n_addr_cells(node);
+ ns = of_n_size_cells(node);
+
+ prop = of_get_property(node, reg, len);
+ if (WARN_ON(!prop || len (na + ns) * sizeof(*prop)))
+ return -EINVAL;
+ reg_base = of_read_number(prop, na);
+
+ switch (reg_base) {
+ case CT_CA9X4_CLCDC:
+ clcd_site = v2m_get_master_site();
+ dvimode = 2;
+ break;
+ default:
+ clcd_site = SYS_CFG_SITE_MB;
+ dvimode = 0;
+ break;
+ }
+
+ if (of_property_read_u32(node, arm,vexpress-osc, osc) != 0)
+ return -EINVAL;
+ v2m_dt_clcd_osc.site = clcd_site;
+ v2m_dt_clcd_osc.osc = osc;
+ v2m_cfg_write(SYS_CFG_MUXFPGA | clcd_site, clcd_site);
+ v2m_cfg_write(SYS_CFG_DVIMODE | clcd_site, dvimode);
+ return 0;
+}
+
static struct map_desc v2m_rs1_io_desc __initdata = {
.virtual= V2M_PERIPH,
.pfn= __phys_to_pfn(0x1c00),
@@ -598,6 +648,8 @@ void __init v2m_dt_init_early(void)
pr_warning(vexpress: DT HBI (%x) is not matching
hardware (%x)!\n, dt_hbi, hbi);
}
+
+ v2m_dt_clcd_init();
}
static struct of_device_id vexpress_irq_match[] __initdata = {
@@ -631,6 +683,12 @@ static void __init v2m_dt_timer_init(void)
if (arch_timer_sched_clock_init() != 0)
versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ,
2400);
+
+ if (v2m_dt_clcd_osc.site) {
+ /* core tile clcd controller for A9 */
+ clk = v2m_osc_register(1002.clcd, v2m_dt_clcd_osc);
+ clk_register_clkdev(clk, NULL, 1002.clcd);
+ }
}
static struct sys_timer v2m_dt_timer = {
When (if ;-) the changes I proposed recently make their way into
mainline, all this stuff will not be necessary - both clocking and
display control are sorted there.
Pawel
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Re: [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
On Thu, 2012-01-19 at 16:46 +, David Vrabel wrote: __create_page_tables has only mapped the single physical page at 0x1c09 and thus the test for the UART in the other memory map faults. I got to the bottom of the problem... The mapping created by the DEBUG_LL code in __create_page_tables is actually a section (1MB) so covers both possible accesses (0xf8009000 and 0xf809). The difference between model and hardware is that real RS1 VE has a DAP ROM located between 0xf800 and 0xf800 so the 0xf8009000 succeeds (returning some irrelevant data), while model is empty in that space, so it faults. Anyway, I have an idea how to solve (or rather work around) the problem and will get if working on models in the next version of the series. I'll send you a modified version of the relevant patch before that so you can test it. Thanks for your time! Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
On Thu, 2012-01-19 at 17:00 +, David Vrabel wrote:
Ok, /include/ skeleton.dtsi is gone then :-)
The problem wasn't with including skeleton.dtsi. With
CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended
DTB using information from the ATAGs (see atags_to_fdt()).
If there's an ATAG giving the amount of RAM the DTB's memory node is
replaced with a new one. Since the vexpress DTBs don't have a memory
node it's added and the DTB ends up with two nodes describing memory.
As it turned out it was just the skeleton.dtsi problem after all - I
mean the fact that there where two device_type=memory nodes in the
tree.
The decompressor's setprop()
(arch/arm/boot/compressed/atags_to_fdt.c:12) uses libfdt's
fdt_setprop(), which correctly ignores the @ component of the
node name and sets the reg property as expected. So as long as there is
exactly one memory[@address] node in the tree,
CONFIG_ARM_ATAG_DTB_COMPAT is happy.
I will remove the /include/ from the dts files for VE (see below) in the
v3.3-rc1 based series.
Thanks for spotting this!
Paweł
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 02cada5..2a690f2 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -9,13 +9,15 @@
/dts-v1/;
-/include/ skeleton.dtsi
-
/ {
model = V2P-CA15;
arm,hbi = 0x237;
compatible = arm,vexpress,v2p-ca15,tc1, arm,vexpress,v2p-ca15,
arm,vexpress;
interrupt-parent = gic;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ chosen { };
aliases {
serial0 = v2m_serial0;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index da26a13..d4c5322 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -9,13 +9,15 @@
/dts-v1/;
-/include/ skeleton.dtsi
-
/ {
model = V2P-CA5s;
arm,hbi = 0x225;
compatible = arm,vexpress,v2p-ca5s, arm,vexpress;
interrupt-parent = gic;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ chosen { };
aliases {
serial0 = v2m_serial0;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 84542e7..5d90ce5 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -9,13 +9,15 @@
/dts-v1/;
-/include/ skeleton.dtsi
-
/ {
model = V2P-CA9;
arm,hbi = 0x191;
compatible = arm,vexpress,v2p-ca9, arm,vexpress;
interrupt-parent = gic;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ chosen { };
aliases {
serial0 = v2m_serial0;
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Re: [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
Hi, Sorry about lng delay - I've been on holiday. On Wed, 2012-01-04 at 16:35 +, David Vrabel wrote: On 15/12/11 14:02, Pawel Moll wrote: This patch adds support for RS1 memory map based Versatile Express motherboard. [...] --- a/arch/arm/mach-vexpress/include/mach/debug-macro.S +++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S @@ -10,12 +10,41 @@ * published by the Free Software Foundation. */ -#define DEBUG_LL_UART_OFFSET 0x9000 +#define DEBUG_LL_PHYS_BASE 0x1000 +#define DEBUG_LL_UART_OFFSET 0x9000 + +#define DEBUG_LL_PHYS_BASE_RS1 0x1c00 +#define DEBUG_LL_UART_OFFSET_RS1 0x0009 + +#define DEBUG_LL_VIRT_BASE 0xf800 .macro addruart,rp,rv,tmp - mov \rp, #DEBUG_LL_UART_OFFSET - orr \rv, \rp, #0xf800 @ virtual base - orr \rp, \rp, #0x1000 @ physical base + + @ Check the MMU state +#if defined(CONFIG_MMU) + mrc p15, 0, \tmp, c1, c0@ SCTRL + tst \tmp, #1@ MMU enabled? + moveq \tmp, #DEBUG_LL_PHYS_BASE + movne \tmp, #DEBUG_LL_VIRT_BASE +#else + mov \tmp, #DEBUG_LL_PHYS_BASE +#endif + + @ PL011 present in original place? + orr \tmp, \tmp, #DEBUG_LL_UART_OFFSET + ldr \tmp, [\tmp, #0xfe0]@ PeriphID0 This doesn't work with CONFIG_EARLY_PRINTK=y on a system with the RS1 memory map. It does for me: # zcat /proc/config.gz | grep EARLY_PRINTK CONFIG_EARLY_PRINTK=y # cat /proc/device-tree/motherboard/arm,v2m-memory-map echo rs1 # Can you tell me what exactly is going wrong in your case? Does it hang without any warning? Do you get at least part of the boot log? Can you send me (privately probably) your kernel config? __create_page_tables has only mapped the single physical page at 0x1c09 and thus the test for the UART in the other memory map faults. I investigated this when writing the code and I vaguely remember it was fine, partly by accident. I'll dig in again and let you know my findings. Thanks for trying this out! Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
On Thu, 2012-01-19 at 13:34 +, Rob Herring wrote: You're right - the skeleton.dtsi contains memory mode... Funnily enough originally I was using that name, but then Rob Herring suggested changing it to @8000, which seemed reasonable. Now I wonder - is the memory node special and should not contain @address, or the skelton shouldn't contain the empty memory node... Hummm... I guess you should just use memory if you are using skeleton.dtsi. Well, I don't mind _not_ using skeleton, but I had an impression the general policy was to use it? Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
On Thu, 2012-01-19 at 14:01 +, Rob Herring wrote: On 01/19/2012 07:43 AM, Pawel Moll wrote: On Thu, 2012-01-19 at 13:34 +, Rob Herring wrote: You're right - the skeleton.dtsi contains memory mode... Funnily enough originally I was using that name, but then Rob Herring suggested changing it to @8000, which seemed reasonable. Now I wonder - is the memory node special and should not contain @address, or the skelton shouldn't contain the empty memory node... Hummm... I guess you should just use memory if you are using skeleton.dtsi. Well, I don't mind _not_ using skeleton, but I had an impression the general policy was to use it? Either way is fine. I don't really think it buys you much. Ok, /include/ skeleton.dtsi is gone then :-) Cheers! Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
On Thu, 2012-01-19 at 17:00 +, David Vrabel wrote: The problem wasn't with including skeleton.dtsi. Including as it is creates two device_type=memory nodes, one with regs=0 0, which is definitely wrong. With CONFIG_ARM_ATAG_DTB_COMPAT the zImage decompressor modifies the appended DTB using information from the ATAGs (see atags_to_fdt()). If there's an ATAG giving the amount of RAM the DTB's memory node is replaced with a new one. Since the vexpress DTBs don't have a memory node it's added and the DTB ends up with two nodes describing memory. The memory@address node name is in my opinion perfectly legal - p. 3.4 of the DT spec says The name component of the node name (see 2.2.1) shall be memory.. So the decompressor code may be wrong in looking for adress-less memory node... One way or the other, I'll get this fixed. Thanks for letting me know! Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
On Thu, 2012-01-19 at 16:46 +, David Vrabel wrote: It does for me: # zcat /proc/config.gz | grep EARLY_PRINTK CONFIG_EARLY_PRINTK=y # cat /proc/device-tree/motherboard/arm,v2m-memory-map echo rs1 # earlyprintk needs to be on the kernel command line to enable it. Without this option it will work fine. # cat /proc/cmdline console=ttyAMA0,38400 earlyprintk rootwait root=/dev/mmcblk0p2 mmci.fmax=1200 debug I'll investigate the matter to the bottom, though. Your kernel config would be helpful, thanks! It's also a problem when running as a guest under a hypervisor as there won't be any stage 2 translation table entries for non-existent peripherals. I think there needs to be someway of finding out from the DTB which UART to use. Yess... The DT+earlyprintk problem was discussed several times already, without any happy resolution so far... Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v6 0/9] Versatile Express DT support
Hi All, This is the last (at least this year) version of the patches. I've added Tested-by: Tixy to the patches that hasn't change since v5. I didn't add Arnd's and Rob's Acked-bys as the code changed significantly since. If still applicable, I'll add then on the first opportunity. Arnd, Russell, if you think that the code is ready enough for 3.3, please pull from this branch based on today's tip (v3.2-rc5+): 8- The following changes since commit 55b02d2f4445ad625213817a1736bf2884d32547: Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux (2011-12-14 19:45:40 -0800) are available in the git repository at: git://git.linaro.org/people/pawelmoll/linux.git vexpress-dt 8- I also have a vexpress-dt-rmk-devel-stable branch there, based on today's Russell's devel-stable. The only difference is handle_irq added to DT machine description. If there are still some issues I'll address them once I'm back from holiday (today it's the last day before I loose all access to the Internet for a month). Changes since v5: * As suggested by Russell, DT-based local timers take precedence over statically defined ones (so the twd_base if overwritten). * Minor redactorial changes in DT-based SMP initialization (the logic stays the same). * Added last missing device node to the V2M trees: arm,vexpress-vram. * Similarly to arm,vexpress-cf added arm,vexpress-psram to the relevant node, just in case we need to detect it in future. Tested on: - V2P-CA9 with ATAGs (both with a ATAGs-only and ATAGs+DT kernels). - V2P-CA9 with DT - V2P-CA5s with DT - V2P-CA15 with DT - V2F-2XV6 Cortex-A7 SMM with DT Thanks to all involved for your help! 8- Pawel Moll (9): ARM: versatile: Add missing ENDPROC to headsmp.S ARM: vexpress: Get rid of MMIO_P2V ARM: versatile: Map local timers using Device Tree when possible ARM: vexpress: Use FDT data in platform SMP calls ARM: vexpress: Add Device Tree support ARM: vexpress: Motherboard RS1 memory map support ARM: vexpress: Add Device Tree for V2P-CA5s core tile ARM: vexpress: Add Device Tree for V2P-CA9 core tile ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant) Documentation/devicetree/bindings/arm/vexpress.txt | 144 ++ arch/arm/Kconfig |2 +- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi| 201 ++ arch/arm/boot/dts/vexpress-v2m.dtsi| 200 ++ arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts| 155 +++ arch/arm/boot/dts/vexpress-v2p-ca5s.dts| 160 +++ arch/arm/boot/dts/vexpress-v2p-ca9.dts | 190 + arch/arm/include/asm/hardware/arm_timer.h |5 + arch/arm/mach-realview/platsmp.c |3 +- arch/arm/mach-vexpress/Kconfig | 45 +++- arch/arm/mach-vexpress/Makefile.boot |6 + arch/arm/mach-vexpress/core.h |9 +- arch/arm/mach-vexpress/ct-ca9x4.c | 48 +--- arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 +- arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 +++- arch/arm/mach-vexpress/include/mach/irqs.h |2 +- arch/arm/mach-vexpress/include/mach/motherboard.h | 58 +++-- arch/arm/mach-vexpress/include/mach/uncompress.h | 13 +- arch/arm/mach-vexpress/platsmp.c | 153 ++- arch/arm/mach-vexpress/v2m.c | 282 ++-- arch/arm/mm/Kconfig|2 +- arch/arm/plat-versatile/headsmp.S |1 + arch/arm/plat-versatile/localtimer.c | 12 + 23 files changed, 1621 insertions(+), 120 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/vexpress.txt create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts -- 1.7.5.4 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v6 1/9] ARM: versatile: Add missing ENDPROC to headsmp.S
Once the ENDPROC is in place, BSYM() in not longer necessary to get correct pointer to versatile_secondary_startup(). Tested-by: Jon Medhurst t...@linaro.org Signed-off-by: Pawel Moll pawel.m...@arm.com --- arch/arm/mach-realview/platsmp.c |3 +-- arch/arm/mach-vexpress/platsmp.c |4 +--- arch/arm/plat-versatile/headsmp.S |1 + 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index e83c654..17c878d 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -17,7 +17,6 @@ #include asm/hardware/gic.h #include asm/mach-types.h #include asm/smp_scu.h -#include asm/unified.h #include mach/board-eb.h #include mach/board-pb11mp.h @@ -75,6 +74,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) * until it receives a soft interrupt, and then the * secondary CPU branches to this address. */ - __raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)), + __raw_writel(virt_to_phys(versatile_secondary_startup), __io_address(REALVIEW_SYS_FLAGSSET)); } diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c index 2b5f7ac..124ffb1 100644 --- a/arch/arm/mach-vexpress/platsmp.c +++ b/arch/arm/mach-vexpress/platsmp.c @@ -13,8 +13,6 @@ #include linux/smp.h #include linux/io.h -#include asm/unified.h - #include mach/motherboard.h #define V2M_PA_CS7 0x1000 @@ -46,6 +44,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) * secondary CPU branches to this address. */ writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR)); - writel(BSYM(virt_to_phys(versatile_secondary_startup)), + writel(virt_to_phys(versatile_secondary_startup), MMIO_P2V(V2M_SYS_FLAGSSET)); } diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S index d397a1f..dd703ef 100644 --- a/arch/arm/plat-versatile/headsmp.S +++ b/arch/arm/plat-versatile/headsmp.S @@ -38,3 +38,4 @@ pen: ldr r7, [r6] .align 1: .long . .long pen_release +ENDPROC(versatile_secondary_startup) -- 1.7.5.4 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v6 2/9] ARM: vexpress: Get rid of MMIO_P2V
This patch gets rid of the MMIO_P2V and __MMIO_P2V macros,
defining constant virtual base for motherboard and tile
peripherals instead.
Additionally, in preparation for the new motherboard memory
map, the motherboard peripherals are using base pointers
calculated in runtime, instead of compile-time calculated
values.
Tested-by: Jon Medhurst t...@linaro.org
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/include/asm/hardware/arm_timer.h |5 ++
arch/arm/mach-vexpress/core.h |9 ++-
arch/arm/mach-vexpress/ct-ca9x4.c | 48 +++
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h| 13 ++---
arch/arm/mach-vexpress/include/mach/motherboard.h | 52
arch/arm/mach-vexpress/platsmp.c |5 +-
arch/arm/mach-vexpress/v2m.c | 68 ++---
7 files changed, 98 insertions(+), 102 deletions(-)
diff --git a/arch/arm/include/asm/hardware/arm_timer.h
b/arch/arm/include/asm/hardware/arm_timer.h
index c0f4e7b..d6030ff 100644
--- a/arch/arm/include/asm/hardware/arm_timer.h
+++ b/arch/arm/include/asm/hardware/arm_timer.h
@@ -9,7 +9,12 @@
*
* Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
* can have 16-bit or 32-bit selectable via a bit in the control register.
+ *
+ * Every SP804 contains two identical timers.
*/
+#define TIMER_1_BASE 0x00
+#define TIMER_2_BASE 0x20
+
#define TIMER_LOAD 0x00/* ACVR rw */
#define TIMER_VALUE0x04/* ACVR ro */
#define TIMER_CTRL 0x08/* ACVR rw */
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index f439715..75a640a 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -1,6 +1,3 @@
-#define __MMIO_P2V(x) (((x) 0xf) | (((x) 0x0f00) 4) |
0xf800)
-#define MMIO_P2V(x)((void __iomem *)__MMIO_P2V(x))
-
#define AMBA_DEVICE(name,busid,base,plat) \
struct amba_device name##_device = { \
.dev= { \
@@ -17,3 +14,9 @@ struct amba_device name##_device = { \
.irq= IRQ_##base, \
/* .dma = DMA_##base,*/ \
}
+
+/* 2MB large area for motherboard's peripherals static mapping */
+#define V2M_PERIPH ((void __iomem *)0xf800)
+
+/* Tile's peripherals static mappings should start here */
+#define V2T_PERIPH ((void __iomem *)0xf820)
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c
b/arch/arm/mach-vexpress/ct-ca9x4.c
index 2b1e836..743a147 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -30,57 +30,29 @@
#include plat/clcd.h
-#define V2M_PA_CS7 0x1000
-
static struct map_desc ct_ca9x4_io_desc[] __initdata = {
{
- .virtual= __MMIO_P2V(CT_CA9X4_MPIC),
- .pfn= __phys_to_pfn(CT_CA9X4_MPIC),
- .length = SZ_16K,
- .type = MT_DEVICE,
- }, {
- .virtual= __MMIO_P2V(CT_CA9X4_SP804_TIMER),
- .pfn= __phys_to_pfn(CT_CA9X4_SP804_TIMER),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual= __MMIO_P2V(CT_CA9X4_L2CC),
- .pfn= __phys_to_pfn(CT_CA9X4_L2CC),
- .length = SZ_4K,
- .type = MT_DEVICE,
+ .virtual= (unsigned long)V2T_PERIPH,
+ .pfn= __phys_to_pfn(CT_CA9X4_MPIC),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
},
};
static void __init ct_ca9x4_map_io(void)
{
#ifdef CONFIG_LOCAL_TIMERS
- twd_base = MMIO_P2V(A9_MPCORE_TWD);
+ twd_base = V2T_PERIPH + A9_MPCORE_TWD;
#endif
iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
}
static void __init ct_ca9x4_init_irq(void)
{
- gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
-MMIO_P2V(A9_MPCORE_GIC_CPU));
-}
-
-#if 0
-static void __init ct_ca9x4_timer_init(void)
-{
- writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
- writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
-
- sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), ct-timer1);
- sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
- ct-timer0);
+ gic_init(0, 29, V2T_PERIPH + A9_MPCORE_GIC_DIST,
+V2T_PERIPH + A9_MPCORE_GIC_CPU);
}
-static struct sys_timer ct_ca9x4_timer = {
- .init = ct_ca9x4_timer_init,
-};
-#endif
-
static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
{
v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
@@ -201,7 +173,7 @@ static void __init ct_ca9x4_init(void)
int i;
#ifdef CONFIG_CACHE_L2X0
- void __iomem *l2x0_base = MMIO_P2V
[PATCH v6 3/9] ARM: versatile: Map local timers using Device Tree when possible
Try to map TWD registers basing on a arm,smp-twd Device Tree
node (compatible value as used in Highbank's DT). This overrides
existing twd_base value.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/plat-versatile/localtimer.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-versatile/localtimer.c
b/arch/arm/plat-versatile/localtimer.c
index 0fb3961..8f0dc10 100644
--- a/arch/arm/plat-versatile/localtimer.c
+++ b/arch/arm/plat-versatile/localtimer.c
@@ -11,6 +11,8 @@
#include linux/init.h
#include linux/smp.h
#include linux/clockchips.h
+#include linux/of.h
+#include linux/of_address.h
#include asm/smp_twd.h
#include asm/localtimer.h
@@ -21,6 +23,16 @@
*/
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
+#if defined(CONFIG_OF)
+ struct device_node *node = of_find_compatible_node(NULL,
+ NULL, arm,smp-twd);
+
+ if (node)
+ twd_base = of_iomap(node, 0);
+#endif
+ if (!twd_base)
+ return -ENXIO;
+
evt-irq = IRQ_LOCALTIMER;
twd_timer_setup(evt);
return 0;
--
1.7.5.4
___
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devicetree-discuss@lists.ozlabs.org
https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v6 4/9] ARM: vexpress: Use FDT data in platform SMP calls
If ct_desc is not set (so a board was booted with DT machine ID)
try to look for arm,cortex-a9-scu node and initialize the SCU
using base address in reg property.
Otherwise assume that there is no special SCU initialization
required and initialize CPUs basing on numbers of cpu type
devices in cpus node of the Device Tree.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/mach-vexpress/platsmp.c | 148 +-
1 files changed, 146 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index a1ed6d6..d49e800d 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -12,6 +12,11 @@
#include linux/errno.h
#include linux/smp.h
#include linux/io.h
+#include linux/of_fdt.h
+
+#include asm/smp_scu.h
+#include asm/hardware/gic.h
+#include asm/mach/map.h
#include mach/motherboard.h
@@ -19,13 +24,149 @@
extern void versatile_secondary_startup(void);
+#if defined(CONFIG_OF)
+
+static enum {
+ UNKNOWN_SCU,
+ GENERIC_SCU,
+ CORTEX_A9_SCU,
+} vexpress_dt_scu = UNKNOWN_SCU;
+
+static void __init vexpress_dt_init_cpu_map(int ncores)
+{
+ int i;
+
+ if (ncores nr_cpu_ids) {
+ pr_warn(SMP: %u cores greater than maximum (%u), clipping\n,
+ ncores, nr_cpu_ids);
+ ncores = nr_cpu_ids;
+ }
+
+ for (i = 0; i ncores; ++i)
+ set_cpu_possible(i, true);
+}
+
+static struct map_desc vexpress_dt_cortex_a9_scu_map[] __initdata = {
+ {
+ .virtual= (unsigned long)V2T_PERIPH,
+ /* .pfn set in vexpress_dt_init_cortex_a9_scu() */
+ .length = SZ_128,
+ .type = MT_DEVICE,
+ },
+};
+
+static int __init vexpress_dt_find_scu(unsigned long node,
+ const char *uname, int depth, void *data)
+{
+ if (of_flat_dt_is_compatible(node, arm,cortex-a9-scu)) {
+ __be32 *reg = of_get_flat_dt_prop(node, reg, NULL);
+
+ if (WARN_ON(!reg))
+ return -EINVAL;
+
+ vexpress_dt_cortex_a9_scu_map[0].pfn =
+ __phys_to_pfn(be32_to_cpup(reg));
+ iotable_init(vexpress_dt_cortex_a9_scu_map,
+ ARRAY_SIZE(vexpress_dt_cortex_a9_scu_map));
+
+ vexpress_dt_init_cpu_map(scu_get_core_count(V2T_PERIPH));
+ set_smp_cross_call(gic_raise_softirq);
+
+ vexpress_dt_scu = CORTEX_A9_SCU;
+
+ return 1;
+ }
+
+ return 0;
+}
+
+static int __init vexpress_dt_nr_cpus(unsigned long node, const char *uname,
+ int depth, void *data)
+{
+ static int prev_depth = -1;
+ static int nr_cpus = -1;
+
+ if (prev_depth depth nr_cpus 0)
+ return nr_cpus;
+
+ if (nr_cpus 0 strcmp(uname, cpus) == 0)
+ nr_cpus = 0;
+
+ if (nr_cpus = 0) {
+ const char *device_type = of_get_flat_dt_prop(node,
+ device_type, NULL);
+
+ if (device_type strcmp(device_type, cpu) == 0)
+ nr_cpus++;
+ }
+
+ prev_depth = depth;
+
+ return 0;
+}
+
+static void __init vexpress_dt_smp_init_cpus(void)
+{
+ int res = of_scan_flat_dt(vexpress_dt_find_scu, NULL);
+
+ if (WARN_ON(res 0))
+ return;
+
+ if (vexpress_dt_scu == UNKNOWN_SCU) {
+ int ncores = of_scan_flat_dt(vexpress_dt_nr_cpus, NULL);
+ if (ncores 2)
+ return;
+
+ vexpress_dt_scu = GENERIC_SCU;
+
+ vexpress_dt_init_cpu_map(ncores);
+ set_smp_cross_call(gic_raise_softirq);
+ }
+}
+
+static void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
+{
+ int i;
+
+ switch (vexpress_dt_scu) {
+ case GENERIC_SCU:
+ for (i = 0; i max_cpus; i++)
+ set_cpu_present(i, true);
+ break;
+ case CORTEX_A9_SCU:
+ scu_enable(V2T_PERIPH);
+ break;
+ default:
+ WARN_ON(1);
+ break;
+ }
+}
+
+#else
+
+static void __init vexpress_dt_smp_init_cpus(void)
+{
+ WARN_ON(1);
+}
+
+void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
+{
+ WARN_ON(1);
+}
+
+#endif
+
/*
* Initialise the CPU possible map early - this describes the CPUs
* which may be present or become present in the system.
*/
void __init smp_init_cpus(void)
{
- ct_desc-init_cpu_map();
+ if (ct_desc)
+ ct_desc-init_cpu_map();
+ else
+ vexpress_dt_smp_init_cpus();
+
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
@@ -34,7 +175,10 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* Initialise the present map
[PATCH v6 5/9] ARM: vexpress: Add Device Tree support
This patch adds generic Versatile Express DT machine description,
Device Tree description for the motherboard and documentation for
the bindings.
Tested-by: Jon Medhurst t...@linaro.org
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
Documentation/devicetree/bindings/arm/vexpress.txt | 144 ++
arch/arm/Kconfig |2 +-
arch/arm/boot/dts/vexpress-v2m.dtsi| 200
arch/arm/mach-vexpress/Kconfig | 45 -
arch/arm/mach-vexpress/Makefile.boot |2 +
arch/arm/mach-vexpress/include/mach/motherboard.h |6 +
arch/arm/mach-vexpress/v2m.c | 152 +++-
arch/arm/mm/Kconfig|2 +-
8 files changed, 546 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/vexpress.txt
create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
diff --git a/Documentation/devicetree/bindings/arm/vexpress.txt
b/Documentation/devicetree/bindings/arm/vexpress.txt
new file mode 100644
index 000..87b9ee7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vexpress.txt
@@ -0,0 +1,144 @@
+ARM Versatile Express boards family
+---
+
+ARM's Versatile Express platform consists of a motherboard and one
+or more daughterboards (tiles). The motherboard provides a set of
+peripherals. Processor and RAM live on the tiles.
+
+The motherboard and each core tile should be described by a separate
+Device Tree source file, with the tile's description including
+the motherboard file using a /include/ directive. As the motherboard
+can be initialized in one of two different configurations (memory
+maps), care must be taken to include the correct one.
+
+Required properties in the root node:
+- compatible value:
+ compatible = arm,vexpress,model, arm,vexpress;
+ where model is the full tile model name (as used in the tile's
+Technical Reference Manual), eg.:
+- for Coretile Express A5x2 (V2P-CA5s):
+ compatible = arm,vexpress,v2p-ca5s, arm,vexpress;
+- for Coretile Express A9x4 (V2P-CA9):
+ compatible = arm,vexpress,v2p-ca9, arm,vexpress;
+ If a tile comes in several variants or can be used in more then one
+ configuration, the compatible value should be:
+ compatible = arm,vexpress,model,variant, \
+ arm,vexpress,model, arm,vexpress;
+ eg:
+- Coretile Express A15x2 (V2P-CA15) with Tech Chip 1:
+ compatible = arm,vexpress,v2p-ca15,tc1, \
+ arm,vexpress,v2p-ca15, arm,vexpress;
+- LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM:
+ compatible = arm,vexpress,v2f-2xv6,ca7x3, \
+ arm,vexpress,v2f-2xv6, arm,vexpress;
+
+Optional properties in the root node:
+- tile model name (use name from the tile's Technical Reference
+ Manual, eg. V2P-CA5s)
+ model = model;
+- tile's HBI number (unique ARM's board model ID, visible on the
+ PCB's silkscreen) in hexadecimal transcription:
+ arm,hbi = 0xhbi
+ eg:
+ - for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
+ arm,hbi = 0x191;
+ - Coretile Express A9x4 (V2P-CA9) HBI-0225:
+ arm,hbi = 0x225;
+
+Top-level standard cpus node is required. It must contain a node
+with device_type = cpu property for every available core, eg.:
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a5;
+ reg = 0;
+ };
+ };
+
+The motherboard description file provides a single motherboard node
+using 2 address cells corresponding to the Static Memory Bus used
+between the motherboard and the tile. The first cell defines the Chip
+Select (CS) line number, the second cell address offset within the CS.
+All interrupt lines between the motherboard and the tile are active
+high and are described using single cell.
+
+Optional properties of the motherboard node:
+- motherboard's memory map variant:
+ arm,v2m-memory-map = name;
+ where name is one of:
+ - rs1 - for RS1 map (i.a. peripherals on CS3); this map is also
+referred to as ARM Cortex-A Series memory map:
+ arm,v2m-memory-map = rs1;
+ When this property is missing, the motherboard is using the original
+ memory map (also known as the Legacy memory map, primarily used
+ with the original CoreTile Express A9x4) with peripherals on CS7.
+
+Motherboard .dtsi files provide a set of labelled peripherals that
+can be used to obtain required phandle in the tile's aliases node:
+- UARTs, note that the numbers correspond to the physical connectors
+ on the motherboard's back panel:
+ v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3
+- I2C controllers:
+ v2m_i2c_dvi and v2m_i2c_pcie
+- SP804 timers
[PATCH v6 6/9] ARM: vexpress: Motherboard RS1 memory map support
This patch adds support for RS1 memory map based Versatile Express
motherboard.
Tested-by: Jon Medhurst t...@linaro.org
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 201 +
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 -
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 ++-
arch/arm/mach-vexpress/v2m.c | 64 +++-
4 files changed, 309 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
new file mode 100644
index 000..16076e2
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -0,0 +1,201 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * RS1 memory map (ARM Cortex-A Series memory map in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * original variant (vexpress-v2m.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m.dtsi!
+ */
+
+/ {
+ aliases {
+ arm,v2m_timer = v2m_timer01;
+ };
+
+ motherboard {
+ compatible = simple-bus;
+ arm,v2m-memory-map = rs1;
+ #address-cells = 2; /* SMB chipselect number and offset */
+ #size-cells = 1;
+ #interrupt-cells = 1;
+
+ flash@0, {
+ compatible = arm,vexpress-flash, cfi-flash;
+ reg = 0 0x 0x0400,
+ 4 0x 0x0400;
+ bank-width = 4;
+ };
+
+ psram@1, {
+ compatible = arm,vexpress-psram, mtd-ram;
+ reg = 1 0x 0x0200;
+ bank-width = 4;
+ };
+
+ vram@2, {
+ compatible = arm,vexpress-vram;
+ reg = 2 0x 0x0080;
+ };
+
+ ethernet@2,0200 {
+ compatible = smsc,lan9118, smsc,lan9115;
+ reg = 2 0x0200 0x1;
+ interrupts = 15;
+ phy-mode = mii;
+ reg-io-width = 4;
+ smsc,irq-active-high;
+ smsc,irq-push-pull;
+ };
+
+ usb@2,0300 {
+ compatible = nxp,usb-isp1761;
+ reg = 2 0x0300 0x2;
+ interrupts = 16;
+ port1-otg;
+ };
+
+ iofpga@3, {
+ compatible = arm,amba-bus, simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 3 0 0x20;
+
+ sysreg@01 {
+ compatible = arm,vexpress-sysreg;
+ reg = 0x01 0x1000;
+ };
+
+ sysctl@02 {
+ compatible = arm,sp810, arm,primecell;
+ reg = 0x02 0x1000;
+ };
+
+ /* PCI-E I2C bus */
+ v2m_i2c_pcie: i2c@03 {
+ compatible = arm,versatile-i2c;
+ reg = 0x03 0x1000;
+
+ #address-cells = 1;
+ #size-cells = 0;
+
+ pcie-switch@60 {
+ compatible = idt,89hpes32h8;
+ reg = 0x60;
+ };
+ };
+
+ aaci@04 {
+ compatible = arm,pl041, arm,primecell;
+ reg = 0x04 0x1000;
+ interrupts = 11;
+ };
+
+ mmci@05 {
+ compatible = arm,pl180, arm,primecell;
+ reg = 0x05 0x1000;
+ interrupts = 9 10;
+ };
+
+ kmi@06 {
+ compatible = arm,pl050, arm,primecell;
+ reg = 0x06 0x1000;
+ interrupts = 12;
+ };
+
+ kmi@07 {
+ compatible = arm,pl050, arm,primecell;
+ reg = 0x07 0x1000;
+ interrupts
[PATCH v6 7/9] ARM: vexpress: Add Device Tree for V2P-CA5s core tile
This patch adds Device Tree file for the CoreTile Express A5x2 (V2P-CA5s).
Tested-by: Jon Medhurst t...@linaro.org
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 160 +++
arch/arm/mach-vexpress/Makefile.boot|2 +
2 files changed, 162 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
new file mode 100644
index 000..da26a13
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -0,0 +1,160 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A5x2
+ * Cortex-A5 MPCore (V2P-CA5s)
+ *
+ * HBI-0225B
+ */
+
+/dts-v1/;
+
+/include/ skeleton.dtsi
+
+/ {
+ model = V2P-CA5s;
+ arm,hbi = 0x225;
+ compatible = arm,vexpress,v2p-ca5s, arm,vexpress;
+ interrupt-parent = gic;
+
+ aliases {
+ serial0 = v2m_serial0;
+ serial1 = v2m_serial1;
+ serial2 = v2m_serial2;
+ serial3 = v2m_serial3;
+ i2c0 = v2m_i2c_dvi;
+ i2c1 = v2m_i2c_pcie;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a5;
+ reg = 0;
+ next-level-cache = L2;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a5;
+ reg = 1;
+ next-level-cache = L2;
+ };
+ };
+
+ memory@8000 {
+ device_type = memory;
+ reg = 0x8000 0x4000;
+ };
+
+ hdlcd@2a11 {
+ compatible = arm,hdlcd;
+ reg = 0x2a11 0x1000;
+ interrupts = 0 85 4;
+ };
+
+ memory-controller@2a15 {
+ compatible = arm,pl341, arm,primecell;
+ reg = 0x2a15 0x1000;
+ };
+
+ memory-controller@2a19 {
+ compatible = arm,pl354, arm,primecell;
+ reg = 0x2a19 0x1000;
+ interrupts = 0 86 4,
+0 87 4;
+ };
+
+ scu@2c00 {
+ compatible = arm,cortex-a9-scu;
+ reg = 0x2c00 0x58;
+ };
+
+ timer@2c000600 {
+ compatible = arm,smp-twd;
+ reg = 0x2c000600 0x38;
+ interrupts = 1 2 0x304,
+1 3 0x304;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = arm,cortex-a9-gic;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x2c001000 0x1000,
+ 0x2c000100 0x100;
+ };
+
+ L2: cache-controller@2c0f {
+ compatible = arm,pl310-cache;
+ reg = 0x2c0f 0x1000;
+ interrupts = 0 84 4;
+ cache-level = 2;
+ };
+
+ pmu {
+ compatible = arm,cortex-a9-pmu;
+ interrupts = 0 68 4,
+0 69 4;
+ };
+
+ motherboard {
+ ranges = 0 0 0x0800 0x0400,
+1 0 0x1400 0x0400,
+2 0 0x1800 0x0400,
+3 0 0x1c00 0x0400,
+4 0 0x0c00 0x0400,
+5 0 0x1000 0x0400;
+
+ interrupt-map-mask = 0 0 63;
+ interrupt-map = 0 0 0 gic 0 0 4,
+ 0 0 1 gic 0 1 4,
+ 0 0 2 gic 0 2 4,
+ 0 0 3 gic 0 3 4,
+ 0 0 4 gic 0 4 4,
+ 0 0 5 gic 0 5 4,
+ 0 0 6 gic 0 6 4,
+ 0 0 7 gic 0 7 4,
+ 0 0 8 gic 0 8 4,
+ 0 0 9 gic 0 9 4,
+ 0 0 10 gic 0 10 4,
+ 0 0 11 gic 0 11 4,
+ 0 0 12 gic 0 12 4,
+ 0 0 13 gic 0 13 4,
+ 0 0 14 gic 0 14 4,
+ 0 0 15 gic 0 15 4,
+ 0 0 16 gic 0 16 4,
+ 0 0 17 gic 0 17 4,
+ 0 0 18 gic 0 18 4,
+ 0 0 19 gic 0 19 4,
+ 0 0 20 gic 0 20 4,
+ 0 0 21 gic 0 21 4,
+ 0 0 22 gic 0 22 4,
+ 0 0 23 gic 0 23 4,
+ 0 0
[PATCH v6 8/9] ARM: vexpress: Add Device Tree for V2P-CA9 core tile
This patch adds Device Tree file for the CoreTile Express A9x4 (V2P-CA9).
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 190
arch/arm/mach-vexpress/Makefile.boot |3 +-
2 files changed, 192 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
new file mode 100644
index 000..84542e7
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -0,0 +1,190 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A9x4
+ * Cortex-A9 MPCore (V2P-CA9)
+ *
+ * HBI-0191B
+ */
+
+/dts-v1/;
+
+/include/ skeleton.dtsi
+
+/ {
+ model = V2P-CA9;
+ arm,hbi = 0x191;
+ compatible = arm,vexpress,v2p-ca9, arm,vexpress;
+ interrupt-parent = gic;
+
+ aliases {
+ serial0 = v2m_serial0;
+ serial1 = v2m_serial1;
+ serial2 = v2m_serial2;
+ serial3 = v2m_serial3;
+ i2c0 = v2m_i2c_dvi;
+ i2c1 = v2m_i2c_pcie;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 0;
+ next-level-cache = L2;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 1;
+ next-level-cache = L2;
+ };
+
+ cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 2;
+ next-level-cache = L2;
+ };
+
+ cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 3;
+ next-level-cache = L2;
+ };
+ };
+
+ memory@6000 {
+ device_type = memory;
+ reg = 0x6000 0x4000;
+ };
+
+ clcd@1002 {
+ compatible = arm,pl111, arm,primecell;
+ reg = 0x1002 0x1000;
+ interrupts = 0 44 4;
+ };
+
+ memory-controller@100e {
+ compatible = arm,pl341, arm,primecell;
+ reg = 0x100e 0x1000;
+ };
+
+ memory-controller@100e1000 {
+ compatible = arm,pl354, arm,primecell;
+ reg = 0x100e1000 0x1000;
+ interrupts = 0 45 4,
+0 46 4;
+ };
+
+ timer@100e4000 {
+ compatible = arm,sp804, arm,primecell;
+ reg = 0x100e4000 0x1000;
+ interrupts = 0 48 4,
+0 49 4;
+ };
+
+ watchdog@100e5000 {
+ compatible = arm,sp805, arm,primecell;
+ reg = 0x100e5000 0x1000;
+ interrupts = 0 51 4;
+ };
+
+ scu@1e00 {
+ compatible = arm,cortex-a9-scu;
+ reg = 0x1e00 0x58;
+ };
+
+ timer@1e000600 {
+ compatible = arm,smp-twd;
+ reg = 0x1e000600 0x20;
+ interrupts = 1 2 0xf04,
+1 3 0xf04;
+ };
+
+ gic: interrupt-controller@1e001000 {
+ compatible = arm,cortex-a9-gic;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x1e001000 0x1000,
+ 0x1e000100 0x100;
+ };
+
+ L2: cache-controller@1e00a000 {
+ compatible = arm,pl310-cache;
+ reg = 0x1e00a000 0x1000;
+ interrupts = 0 43 4;
+ cache-level = 2;
+ arm,data-latency = 1 1 1;
+ arm,tag-latency = 1 1 1;
+ };
+
+ pmu {
+ compatible = arm,cortex-a9-pmu;
+ interrupts = 0 60 4,
+0 61 4,
+0 62 4,
+0 63 4;
+ };
+
+ motherboard {
+ ranges = 0 0 0x4000 0x0400,
+1 0 0x4400 0x0400,
+2 0 0x4800 0x0400,
+3 0 0x4c00 0x0400,
+7 0 0x1000 0x0002;
+
+ interrupt-map-mask = 0 0 63;
+ interrupt-map = 0 0 0 gic 0 0 4,
+ 0 0 1 gic 0 1 4,
+ 0 0 2 gic 0 2 4,
+ 0 0 3 gic 0 3 4,
+ 0 0 4 gic 0 4 4,
+ 0 0 5 gic 0 5 4,
+ 0 0 6 gic 0 6 4
Re: [PATCH v6 3/9] ARM: versatile: Map local timers using Device Tree when possible
On Thu, 2011-12-15 at 14:53 +, Rob Herring wrote:
@@ -21,6 +23,16 @@
*/
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
+#if defined(CONFIG_OF)
+ struct device_node *node = of_find_compatible_node(NULL,
+ NULL, arm,smp-twd);
+
+ if (node)
+ twd_base = of_iomap(node, 0);
+#endif
I think your previous version was more correct. This is going to find
the node and do ioremap N times where N is the number of cores. It does
work though because that is what I did initially too.
Right, how about that, then:
@@ -21,6 +23,22 @@
*/
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
+#if defined(CONFIG_OF)
+ static int dt_node_probed;
+
+ if (!dt_node_probed) {
+ struct device_node *node = of_find_compatible_node(NULL,
+ NULL, arm,smp-twd);
+
+ if (node)
+ twd_base = of_iomap(node, 0);
+
+ dt_node_probed = 1;
+ }
+#endif
+ if (!twd_base)
+ return -ENXIO;
+
evt-irq = IRQ_LOCALTIMER;
twd_timer_setup(evt);
return 0;
Cheers!
Paweł
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Re: [PATCH v6 3/9] ARM: versatile: Map local timers using Device Tree when possible
On Thu, 2011-12-15 at 15:25 +, Pawel Moll wrote:
I think your previous version was more correct. This is going to find
the node and do ioremap N times where N is the number of cores. It does
work though because that is what I did initially too.
Right, how about that, then:
@@ -21,6 +23,22 @@
*/
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
+#if defined(CONFIG_OF)
+ static int dt_node_probed;
+
+ if (!dt_node_probed) {
+ struct device_node *node = of_find_compatible_node(NULL,
+ NULL, arm,smp-twd);
+
+ if (node)
+ twd_base = of_iomap(node, 0);
+
+ dt_node_probed = 1;
+ }
+#endif
+ if (!twd_base)
+ return -ENXIO;
+
evt-irq = IRQ_LOCALTIMER;
twd_timer_setup(evt);
return 0;
Ok, so I have updated the both vexpress-dt and
vexpress-dt-rmk-devel-stable branches like that.
Arnd, Russell, the new pull request below.
I'll see you all next year!
Cheers!
Paweł
8---
The following changes since commit 55b02d2f4445ad625213817a1736bf2884d32547:
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
(2011-12-14 19:45:40 -0800)
are available in the git repository at:
git://git.linaro.org/people/pawelmoll/linux.git vexpress-dt
Pawel Moll (9):
ARM: versatile: Add missing ENDPROC to headsmp.S
ARM: vexpress: Get rid of MMIO_P2V
ARM: versatile: Map local timers using Device Tree when possible
ARM: vexpress: Use FDT data in platform SMP calls
ARM: vexpress: Add Device Tree support
ARM: vexpress: Motherboard RS1 memory map support
ARM: vexpress: Add Device Tree for V2P-CA5s core tile
ARM: vexpress: Add Device Tree for V2P-CA9 core tile
ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
Documentation/devicetree/bindings/arm/vexpress.txt | 144 ++
arch/arm/Kconfig |2 +-
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi| 201 ++
arch/arm/boot/dts/vexpress-v2m.dtsi| 200 ++
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts| 155 +++
arch/arm/boot/dts/vexpress-v2p-ca5s.dts| 160 +++
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 190 +
arch/arm/include/asm/hardware/arm_timer.h |5 +
arch/arm/mach-realview/platsmp.c |3 +-
arch/arm/mach-vexpress/Kconfig | 45 +++-
arch/arm/mach-vexpress/Makefile.boot |6 +
arch/arm/mach-vexpress/core.h |9 +-
arch/arm/mach-vexpress/ct-ca9x4.c | 48 +---
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 +-
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 +++-
arch/arm/mach-vexpress/include/mach/irqs.h |2 +-
arch/arm/mach-vexpress/include/mach/motherboard.h | 58 +++--
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 +-
arch/arm/mach-vexpress/platsmp.c | 153 ++-
arch/arm/mach-vexpress/v2m.c | 282 ++--
arch/arm/mm/Kconfig|2 +-
arch/arm/plat-versatile/headsmp.S |1 +
arch/arm/plat-versatile/localtimer.c | 19 ++
23 files changed, 1628 insertions(+), 120 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/vexpress.txt
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
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Re: [PATCH v5 5/9] ARM: versatile: Map local timers using Device Tree when possible
Morning,
On Sat, 2011-12-10 at 15:27 +, Sergei Shtylyov wrote:
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
+#if defined(CONFIG_OF)
+ if (!twd_base) {
+ struct device_node *np = of_find_compatible_node(NULL,
+ NULL, arm,smp-twd);
+
+ twd_base = of_iomap(np, 0);
+ if (!twd_base)
+ return -ENXIO;
-ENOMEM.
Hm. What I did simply mimics this (arch/arm/include/asm/localtimer.h):
#ifdef CONFIG_LOCAL_TIMERS
[...]
#else
static inline int local_timer_setup(struct clock_event_device *evt)
{
return -ENXIO;
}
Now, I had a look at include/asm-generic/errno-base.h:
#define ENXIO6 /* No such device or address */
[...]
#define ENOMEM 12 /* Out of memory */
and to be honest, ENXIO makes more sense to me, but I really have no
strong feelings either way... Do you?
Thanks for your time!
Paweł
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Re: [PATCH v5 5/9] ARM: versatile: Map local timers using Device Tree when possible
On Mon, 2011-12-12 at 11:18 +, Sergei Shtylyov wrote:
I think if of_iomap() fails, it's because the system is out of memory, so
-ENOMEM seems more proper error in this case. Although... it's not the only
case when of_iomap() fails.
I actually think that in this use case it's much more likely that
of_iomap() returns NULL because of_address_to_resource() fails:
void __iomem *of_iomap(struct device_node *np, int index)
{
struct resource res;
if (of_address_to_resource(np, index, res))
return NULL;
and this will - again most likely - happen when np == NULL (so
of_find_compatible_node() returns nothing). That's what makes ENXIO look
good to me there...
Cheers!
Paweł
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Re: [PATCH v5 5/9] ARM: versatile: Map local timers using Device Tree when possible
On Mon, 2011-12-12 at 14:04 +, Russell King - ARM Linux wrote: On Fri, Dec 09, 2011 at 07:03:48PM +, Pawel Moll wrote: If twd_base is not set, try to map the TWD registers from arm,smp-twd Device Tree node (compatible value as used in Highbank's DT). Please do it the other way around - allow DT to override twd_base if the DT node is present. Ok, will do. Thanks! Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v5 0/9] Versatile Express DT support
Good Evening, As usually it took more time than I though, but the changes are quite extensive: Changes since v4: * Breaking news: we have a generic vexpress machine now! * TWD DT-based initialization was moved to platform's local timers file * SCU (and generally SMP) initialization was moved to platsmp.c file; when there is no memory-mapped SCU (A7/A15) the number of available cores is worked in generic way from the tree (cpus node) * ... and there was very little left in the tile file, so it just nicely folded into v2m.c. * Main compatible value is now arm,vexpress, so we are back in the point we started :-) * The tiles' trees are now separate patches, but I may fold them into one if this is preferred. Tested on: - V2P-CA9 with ATAGs - V2P-CA9 with DT - V2P-CA5s with DT - V2P-CA15 with DT - V2F-2XV6 Cortex-A7 SMM with DT Previous versions have been tested by Ryan Harkin and provisionally acked by Rob Herring and Arnd Bergmann. Thanks for all your help, especially to Dave and Arnd for their continuous support! Pawel Moll (9): ARM: versatile: Add missing ENDPROC to headsmp.S ARM: vexpress: Get rid of MMIO_P2V ARM: vexpress: Add Device Tree support ARM: vexpress: Motherboard RS1 memory map support ARM: versatile: Map local timers using Device Tree when possible ARM: vexpress: Use FDT data in platform SMP calls ARM: vexpress: Add Device Tree for V2P-CA5s core tile ARM: vexpress: Add Device Tree for V2P-CA9 core tile ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant) Documentation/devicetree/bindings/arm/vexpress.txt | 144 ++ arch/arm/Kconfig |2 +- arch/arm/boot/dts/vexpress-v2m-rs1.dtsi| 196 ++ arch/arm/boot/dts/vexpress-v2m.dtsi| 195 ++ arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts| 155 +++ arch/arm/boot/dts/vexpress-v2p-ca5s.dts| 160 +++ arch/arm/boot/dts/vexpress-v2p-ca9.dts | 190 + arch/arm/include/asm/hardware/arm_timer.h |5 + arch/arm/mach-realview/platsmp.c |3 +- arch/arm/mach-vexpress/Kconfig | 45 +++- arch/arm/mach-vexpress/Makefile.boot |6 + arch/arm/mach-vexpress/core.h |9 +- arch/arm/mach-vexpress/ct-ca9x4.c | 48 +--- arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 +- arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 +++- arch/arm/mach-vexpress/include/mach/irqs.h |2 +- arch/arm/mach-vexpress/include/mach/motherboard.h | 58 +++-- arch/arm/mach-vexpress/include/mach/uncompress.h | 13 +- arch/arm/mach-vexpress/platsmp.c | 151 ++- arch/arm/mach-vexpress/v2m.c | 282 ++-- arch/arm/mm/Kconfig|2 +- arch/arm/plat-versatile/headsmp.S |1 + arch/arm/plat-versatile/localtimer.c | 12 + 23 files changed, 1609 insertions(+), 120 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/vexpress.txt create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts -- 1.7.5.4 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v5 1/9] ARM: versatile: Add missing ENDPROC to headsmp.S
Once the ENDPROC is in place, BSYM() in not longer necessary to get correct pointer to versatile_secondary_startup(). Signed-off-by: Pawel Moll pawel.m...@arm.com --- arch/arm/mach-realview/platsmp.c |3 +-- arch/arm/mach-vexpress/platsmp.c |4 +--- arch/arm/plat-versatile/headsmp.S |1 + 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index e83c654..17c878d 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -17,7 +17,6 @@ #include asm/hardware/gic.h #include asm/mach-types.h #include asm/smp_scu.h -#include asm/unified.h #include mach/board-eb.h #include mach/board-pb11mp.h @@ -75,6 +74,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) * until it receives a soft interrupt, and then the * secondary CPU branches to this address. */ - __raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)), + __raw_writel(virt_to_phys(versatile_secondary_startup), __io_address(REALVIEW_SYS_FLAGSSET)); } diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c index 2b5f7ac..124ffb1 100644 --- a/arch/arm/mach-vexpress/platsmp.c +++ b/arch/arm/mach-vexpress/platsmp.c @@ -13,8 +13,6 @@ #include linux/smp.h #include linux/io.h -#include asm/unified.h - #include mach/motherboard.h #define V2M_PA_CS7 0x1000 @@ -46,6 +44,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) * secondary CPU branches to this address. */ writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR)); - writel(BSYM(virt_to_phys(versatile_secondary_startup)), + writel(virt_to_phys(versatile_secondary_startup), MMIO_P2V(V2M_SYS_FLAGSSET)); } diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S index d397a1f..dd703ef 100644 --- a/arch/arm/plat-versatile/headsmp.S +++ b/arch/arm/plat-versatile/headsmp.S @@ -38,3 +38,4 @@ pen: ldr r7, [r6] .align 1: .long . .long pen_release +ENDPROC(versatile_secondary_startup) -- 1.7.5.4 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v5 2/9] ARM: vexpress: Get rid of MMIO_P2V
This patch gets rid of the MMIO_P2V and __MMIO_P2V macros,
defining constant virtual base for motherboard and tile
peripherals instead.
Additionally, in preparation for the new motherboard memory
map, the motherboard peripherals are using base pointers
calculated in runtime, instead of compile-time calculated
values.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/include/asm/hardware/arm_timer.h |5 ++
arch/arm/mach-vexpress/core.h |9 ++-
arch/arm/mach-vexpress/ct-ca9x4.c | 48 +++
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h| 13 ++---
arch/arm/mach-vexpress/include/mach/motherboard.h | 52
arch/arm/mach-vexpress/platsmp.c |5 +-
arch/arm/mach-vexpress/v2m.c | 68 ++---
7 files changed, 98 insertions(+), 102 deletions(-)
diff --git a/arch/arm/include/asm/hardware/arm_timer.h
b/arch/arm/include/asm/hardware/arm_timer.h
index c0f4e7b..d6030ff 100644
--- a/arch/arm/include/asm/hardware/arm_timer.h
+++ b/arch/arm/include/asm/hardware/arm_timer.h
@@ -9,7 +9,12 @@
*
* Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
* can have 16-bit or 32-bit selectable via a bit in the control register.
+ *
+ * Every SP804 contains two identical timers.
*/
+#define TIMER_1_BASE 0x00
+#define TIMER_2_BASE 0x20
+
#define TIMER_LOAD 0x00/* ACVR rw */
#define TIMER_VALUE0x04/* ACVR ro */
#define TIMER_CTRL 0x08/* ACVR rw */
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index f439715..75a640a 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -1,6 +1,3 @@
-#define __MMIO_P2V(x) (((x) 0xf) | (((x) 0x0f00) 4) |
0xf800)
-#define MMIO_P2V(x)((void __iomem *)__MMIO_P2V(x))
-
#define AMBA_DEVICE(name,busid,base,plat) \
struct amba_device name##_device = { \
.dev= { \
@@ -17,3 +14,9 @@ struct amba_device name##_device = { \
.irq= IRQ_##base, \
/* .dma = DMA_##base,*/ \
}
+
+/* 2MB large area for motherboard's peripherals static mapping */
+#define V2M_PERIPH ((void __iomem *)0xf800)
+
+/* Tile's peripherals static mappings should start here */
+#define V2T_PERIPH ((void __iomem *)0xf820)
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c
b/arch/arm/mach-vexpress/ct-ca9x4.c
index 2b1e836..743a147 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -30,57 +30,29 @@
#include plat/clcd.h
-#define V2M_PA_CS7 0x1000
-
static struct map_desc ct_ca9x4_io_desc[] __initdata = {
{
- .virtual= __MMIO_P2V(CT_CA9X4_MPIC),
- .pfn= __phys_to_pfn(CT_CA9X4_MPIC),
- .length = SZ_16K,
- .type = MT_DEVICE,
- }, {
- .virtual= __MMIO_P2V(CT_CA9X4_SP804_TIMER),
- .pfn= __phys_to_pfn(CT_CA9X4_SP804_TIMER),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual= __MMIO_P2V(CT_CA9X4_L2CC),
- .pfn= __phys_to_pfn(CT_CA9X4_L2CC),
- .length = SZ_4K,
- .type = MT_DEVICE,
+ .virtual= (unsigned long)V2T_PERIPH,
+ .pfn= __phys_to_pfn(CT_CA9X4_MPIC),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
},
};
static void __init ct_ca9x4_map_io(void)
{
#ifdef CONFIG_LOCAL_TIMERS
- twd_base = MMIO_P2V(A9_MPCORE_TWD);
+ twd_base = V2T_PERIPH + A9_MPCORE_TWD;
#endif
iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
}
static void __init ct_ca9x4_init_irq(void)
{
- gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
-MMIO_P2V(A9_MPCORE_GIC_CPU));
-}
-
-#if 0
-static void __init ct_ca9x4_timer_init(void)
-{
- writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
- writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
-
- sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), ct-timer1);
- sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
- ct-timer0);
+ gic_init(0, 29, V2T_PERIPH + A9_MPCORE_GIC_DIST,
+V2T_PERIPH + A9_MPCORE_GIC_CPU);
}
-static struct sys_timer ct_ca9x4_timer = {
- .init = ct_ca9x4_timer_init,
-};
-#endif
-
static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
{
v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
@@ -201,7 +173,7 @@ static void __init ct_ca9x4_init(void)
int i;
#ifdef CONFIG_CACHE_L2X0
- void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
+ void __iomem
[PATCH v5 3/9] ARM: vexpress: Add Device Tree support
This patch adds generic Versatile Express DT machine description,
Device Tree description for the motherboard and documentation for
the bindings.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
Documentation/devicetree/bindings/arm/vexpress.txt | 144 +++
arch/arm/Kconfig |2 +-
arch/arm/boot/dts/vexpress-v2m.dtsi| 195
arch/arm/mach-vexpress/Kconfig | 45 +-
arch/arm/mach-vexpress/Makefile.boot |2 +
arch/arm/mach-vexpress/include/mach/motherboard.h |6 +
arch/arm/mach-vexpress/v2m.c | 152 +++-
arch/arm/mm/Kconfig|2 +-
8 files changed, 541 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/vexpress.txt
create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
diff --git a/Documentation/devicetree/bindings/arm/vexpress.txt
b/Documentation/devicetree/bindings/arm/vexpress.txt
new file mode 100644
index 000..87b9ee7
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vexpress.txt
@@ -0,0 +1,144 @@
+ARM Versatile Express boards family
+---
+
+ARM's Versatile Express platform consists of a motherboard and one
+or more daughterboards (tiles). The motherboard provides a set of
+peripherals. Processor and RAM live on the tiles.
+
+The motherboard and each core tile should be described by a separate
+Device Tree source file, with the tile's description including
+the motherboard file using a /include/ directive. As the motherboard
+can be initialized in one of two different configurations (memory
+maps), care must be taken to include the correct one.
+
+Required properties in the root node:
+- compatible value:
+ compatible = arm,vexpress,model, arm,vexpress;
+ where model is the full tile model name (as used in the tile's
+Technical Reference Manual), eg.:
+- for Coretile Express A5x2 (V2P-CA5s):
+ compatible = arm,vexpress,v2p-ca5s, arm,vexpress;
+- for Coretile Express A9x4 (V2P-CA9):
+ compatible = arm,vexpress,v2p-ca9, arm,vexpress;
+ If a tile comes in several variants or can be used in more then one
+ configuration, the compatible value should be:
+ compatible = arm,vexpress,model,variant, \
+ arm,vexpress,model, arm,vexpress;
+ eg:
+- Coretile Express A15x2 (V2P-CA15) with Tech Chip 1:
+ compatible = arm,vexpress,v2p-ca15,tc1, \
+ arm,vexpress,v2p-ca15, arm,vexpress;
+- LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM:
+ compatible = arm,vexpress,v2f-2xv6,ca7x3, \
+ arm,vexpress,v2f-2xv6, arm,vexpress;
+
+Optional properties in the root node:
+- tile model name (use name from the tile's Technical Reference
+ Manual, eg. V2P-CA5s)
+ model = model;
+- tile's HBI number (unique ARM's board model ID, visible on the
+ PCB's silkscreen) in hexadecimal transcription:
+ arm,hbi = 0xhbi
+ eg:
+ - for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
+ arm,hbi = 0x191;
+ - Coretile Express A9x4 (V2P-CA9) HBI-0225:
+ arm,hbi = 0x225;
+
+Top-level standard cpus node is required. It must contain a node
+with device_type = cpu property for every available core, eg.:
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a5;
+ reg = 0;
+ };
+ };
+
+The motherboard description file provides a single motherboard node
+using 2 address cells corresponding to the Static Memory Bus used
+between the motherboard and the tile. The first cell defines the Chip
+Select (CS) line number, the second cell address offset within the CS.
+All interrupt lines between the motherboard and the tile are active
+high and are described using single cell.
+
+Optional properties of the motherboard node:
+- motherboard's memory map variant:
+ arm,v2m-memory-map = name;
+ where name is one of:
+ - rs1 - for RS1 map (i.a. peripherals on CS3); this map is also
+referred to as ARM Cortex-A Series memory map:
+ arm,v2m-memory-map = rs1;
+ When this property is missing, the motherboard is using the original
+ memory map (also known as the Legacy memory map, primarily used
+ with the original CoreTile Express A9x4) with peripherals on CS7.
+
+Motherboard .dtsi files provide a set of labelled peripherals that
+can be used to obtain required phandle in the tile's aliases node:
+- UARTs, note that the numbers correspond to the physical connectors
+ on the motherboard's back panel:
+ v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3
+- I2C controllers:
+ v2m_i2c_dvi and v2m_i2c_pcie
+- SP804 timers:
+ v2m_timer01 and v2m_timer23
+
+Current Linux
[PATCH v5 4/9] ARM: vexpress: Motherboard RS1 memory map support
This patch adds support for RS1 memory map based Versatile Express
motherboard.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 196 +
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 -
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 ++-
arch/arm/mach-vexpress/v2m.c | 64 +++-
4 files changed, 304 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
new file mode 100644
index 000..a7d385f
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -0,0 +1,196 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * RS1 memory map (ARM Cortex-A Series memory map in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * original variant (vexpress-v2m.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m.dtsi!
+ */
+
+/ {
+ aliases {
+ arm,v2m_timer = v2m_timer01;
+ };
+
+ motherboard {
+ compatible = simple-bus;
+ arm,v2m-memory-map = rs1;
+ #address-cells = 2; /* SMB chipselect number and offset */
+ #size-cells = 1;
+ #interrupt-cells = 1;
+
+ flash@0, {
+ compatible = arm,vexpress-flash, cfi-flash;
+ reg = 0 0x 0x0400,
+ 4 0x 0x0400;
+ bank-width = 4;
+ };
+
+ psram@1, {
+ compatible = mtd-ram;
+ reg = 1 0x 0x0200;
+ bank-width = 4;
+ };
+
+ ethernet@2,0200 {
+ compatible = smsc,lan9118, smsc,lan9115;
+ reg = 2 0x0200 0x1;
+ interrupts = 15;
+ phy-mode = mii;
+ reg-io-width = 4;
+ smsc,irq-active-high;
+ smsc,irq-push-pull;
+ };
+
+ usb@2,0300 {
+ compatible = nxp,usb-isp1761;
+ reg = 2 0x0300 0x2;
+ interrupts = 16;
+ port1-otg;
+ };
+
+ iofpga@3, {
+ compatible = arm,amba-bus, simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 3 0 0x20;
+
+ sysreg@01 {
+ compatible = arm,vexpress-sysreg;
+ reg = 0x01 0x1000;
+ };
+
+ sysctl@02 {
+ compatible = arm,sp810, arm,primecell;
+ reg = 0x02 0x1000;
+ };
+
+ /* PCI-E I2C bus */
+ v2m_i2c_pcie: i2c@03 {
+ compatible = arm,versatile-i2c;
+ reg = 0x03 0x1000;
+
+ #address-cells = 1;
+ #size-cells = 0;
+
+ pcie-switch@60 {
+ compatible = idt,89hpes32h8;
+ reg = 0x60;
+ };
+ };
+
+ aaci@04 {
+ compatible = arm,pl041, arm,primecell;
+ reg = 0x04 0x1000;
+ interrupts = 11;
+ };
+
+ mmci@05 {
+ compatible = arm,pl180, arm,primecell;
+ reg = 0x05 0x1000;
+ interrupts = 9 10;
+ };
+
+ kmi@06 {
+ compatible = arm,pl050, arm,primecell;
+ reg = 0x06 0x1000;
+ interrupts = 12;
+ };
+
+ kmi@07 {
+ compatible = arm,pl050, arm,primecell;
+ reg = 0x07 0x1000;
+ interrupts = 13;
+ };
+
+ v2m_serial0: uart@09 {
+ compatible = arm,pl011, arm,primecell;
+ reg = 0x09 0x1000
[PATCH v5 5/9] ARM: versatile: Map local timers using Device Tree when possible
If twd_base is not set, try to map the TWD registers from
arm,smp-twd Device Tree node (compatible value as used in
Highbank's DT).
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/plat-versatile/localtimer.c | 12
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/plat-versatile/localtimer.c
b/arch/arm/plat-versatile/localtimer.c
index 0fb3961..e3da322 100644
--- a/arch/arm/plat-versatile/localtimer.c
+++ b/arch/arm/plat-versatile/localtimer.c
@@ -11,6 +11,8 @@
#include linux/init.h
#include linux/smp.h
#include linux/clockchips.h
+#include linux/of.h
+#include linux/of_address.h
#include asm/smp_twd.h
#include asm/localtimer.h
@@ -21,6 +23,16 @@
*/
int __cpuinit local_timer_setup(struct clock_event_device *evt)
{
+#if defined(CONFIG_OF)
+ if (!twd_base) {
+ struct device_node *np = of_find_compatible_node(NULL,
+ NULL, arm,smp-twd);
+
+ twd_base = of_iomap(np, 0);
+ if (!twd_base)
+ return -ENXIO;
+ }
+#endif
evt-irq = IRQ_LOCALTIMER;
twd_timer_setup(evt);
return 0;
--
1.7.5.4
___
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[PATCH v5 6/9] ARM: vexpress: Use FDT data in platform SMP calls
If ct_desc is not set (so a board was booted with DT machine ID)
try to look for arm,cortex-a9-scu node and initialize the SCU
using base address in reg property. Otherwise assume that
there is no specific SCU initialization required and initialize
cpus based numbers of cpu type devices in cpus node.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/mach-vexpress/platsmp.c | 146 +-
1 files changed, 144 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index a1ed6d6..d89589f 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -12,6 +12,11 @@
#include linux/errno.h
#include linux/smp.h
#include linux/io.h
+#include linux/of_fdt.h
+
+#include asm/smp_scu.h
+#include asm/hardware/gic.h
+#include asm/mach/map.h
#include mach/motherboard.h
@@ -19,13 +24,147 @@
extern void versatile_secondary_startup(void);
+#if defined(CONFIG_OF)
+
+static enum {
+ UNKNOWN_SCU,
+ GENERIC_SCU,
+ CORTEX_A9_SCU,
+} vexpress_dt_scu = UNKNOWN_SCU;
+
+static void __init vexpress_dt_init_cpu_map(int ncores)
+{
+ int i;
+
+ if (ncores nr_cpu_ids) {
+ pr_warn(SMP: %u cores greater than maximum (%u), clipping\n,
+ ncores, nr_cpu_ids);
+ ncores = nr_cpu_ids;
+ }
+
+ for (i = 0; i ncores; ++i)
+ set_cpu_possible(i, true);
+}
+
+static struct map_desc vexpress_dt_cortex_a9_scu_map[] __initdata = {
+ {
+ .virtual= (unsigned long)V2T_PERIPH,
+ /* .pfn set in vexpress_dt_init_cortex_a9_scu() */
+ .length = SZ_128,
+ .type = MT_DEVICE,
+ },
+};
+
+static int __init vexpress_dt_init_cortex_a9_scu(unsigned long node,
+ const char *uname, int depth, void *data)
+{
+ if (of_flat_dt_is_compatible(node, arm,cortex-a9-scu)) {
+ __be32 *reg = of_get_flat_dt_prop(node, reg, NULL);
+
+ if (WARN_ON(!reg))
+ return -EINVAL;
+
+ vexpress_dt_cortex_a9_scu_map[0].pfn =
+ __phys_to_pfn(be32_to_cpup(reg));
+ iotable_init(vexpress_dt_cortex_a9_scu_map,
+ ARRAY_SIZE(vexpress_dt_cortex_a9_scu_map));
+
+ vexpress_dt_init_cpu_map(scu_get_core_count(V2T_PERIPH));
+ set_smp_cross_call(gic_raise_softirq);
+
+ return CORTEX_A9_SCU;
+ }
+
+ return 0;
+}
+
+static int __init vexpress_dt_nr_cpus(unsigned long node, const char *uname,
+ int depth, void *data)
+{
+ static int prev_depth = -1;
+ static int nr_cpus = -1;
+
+ if (prev_depth depth nr_cpus 0)
+ return nr_cpus;
+
+ if (nr_cpus 0 strcmp(uname, cpus) == 0)
+ nr_cpus = 0;
+
+ if (nr_cpus = 0) {
+ const char *device_type = of_get_flat_dt_prop(node,
+ device_type, NULL);
+
+ if (device_type strcmp(device_type, cpu) == 0)
+ nr_cpus++;
+ }
+
+ prev_depth = depth;
+
+ return 0;
+}
+
+static void __init vexpress_dt_smp_init_cpus(void)
+{
+ int ncores;
+
+ vexpress_dt_scu = of_scan_flat_dt(vexpress_dt_init_cortex_a9_scu, NULL);
+
+ if (WARN_ON(vexpress_dt_scu 0) || vexpress_dt_scu != UNKNOWN_SCU)
+ return;
+
+ ncores = of_scan_flat_dt(vexpress_dt_nr_cpus, NULL);
+ if (ncores 2)
+ return;
+
+ vexpress_dt_scu = GENERIC_SCU;
+
+ vexpress_dt_init_cpu_map(ncores);
+ set_smp_cross_call(gic_raise_softirq);
+}
+
+static void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
+{
+ int i;
+
+ switch (vexpress_dt_scu) {
+ case GENERIC_SCU:
+ for (i = 0; i max_cpus; i++)
+ set_cpu_present(i, true);
+ break;
+ case CORTEX_A9_SCU:
+ scu_enable(V2T_PERIPH);
+ break;
+ default:
+ WARN_ON(1);
+ break;
+ }
+}
+
+#else
+
+static void __init vexpress_dt_smp_init_cpus(void)
+{
+ WARN_ON(1);
+}
+
+void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
+{
+ WARN_ON(1);
+}
+
+#endif
+
/*
* Initialise the CPU possible map early - this describes the CPUs
* which may be present or become present in the system.
*/
void __init smp_init_cpus(void)
{
- ct_desc-init_cpu_map();
+ if (ct_desc)
+ ct_desc-init_cpu_map();
+ else
+ vexpress_dt_smp_init_cpus();
+
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
@@ -34,7 +173,10 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* Initialise the present map, which describes the set of CPUs
* actually populated
[PATCH v5 7/9] ARM: vexpress: Add Device Tree for V2P-CA5s core tile
This patch adds Device Tree file for the CoreTile Express A5x2 (V2P-CA5s).
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 160 +++
arch/arm/mach-vexpress/Makefile.boot|2 +
2 files changed, 162 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
new file mode 100644
index 000..da26a13
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -0,0 +1,160 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A5x2
+ * Cortex-A5 MPCore (V2P-CA5s)
+ *
+ * HBI-0225B
+ */
+
+/dts-v1/;
+
+/include/ skeleton.dtsi
+
+/ {
+ model = V2P-CA5s;
+ arm,hbi = 0x225;
+ compatible = arm,vexpress,v2p-ca5s, arm,vexpress;
+ interrupt-parent = gic;
+
+ aliases {
+ serial0 = v2m_serial0;
+ serial1 = v2m_serial1;
+ serial2 = v2m_serial2;
+ serial3 = v2m_serial3;
+ i2c0 = v2m_i2c_dvi;
+ i2c1 = v2m_i2c_pcie;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a5;
+ reg = 0;
+ next-level-cache = L2;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a5;
+ reg = 1;
+ next-level-cache = L2;
+ };
+ };
+
+ memory@8000 {
+ device_type = memory;
+ reg = 0x8000 0x4000;
+ };
+
+ hdlcd@2a11 {
+ compatible = arm,hdlcd;
+ reg = 0x2a11 0x1000;
+ interrupts = 0 85 4;
+ };
+
+ memory-controller@2a15 {
+ compatible = arm,pl341, arm,primecell;
+ reg = 0x2a15 0x1000;
+ };
+
+ memory-controller@2a19 {
+ compatible = arm,pl354, arm,primecell;
+ reg = 0x2a19 0x1000;
+ interrupts = 0 86 4,
+0 87 4;
+ };
+
+ scu@2c00 {
+ compatible = arm,cortex-a9-scu;
+ reg = 0x2c00 0x58;
+ };
+
+ timer@2c000600 {
+ compatible = arm,smp-twd;
+ reg = 0x2c000600 0x38;
+ interrupts = 1 2 0x304,
+1 3 0x304;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = arm,cortex-a9-gic;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x2c001000 0x1000,
+ 0x2c000100 0x100;
+ };
+
+ L2: cache-controller@2c0f {
+ compatible = arm,pl310-cache;
+ reg = 0x2c0f 0x1000;
+ interrupts = 0 84 4;
+ cache-level = 2;
+ };
+
+ pmu {
+ compatible = arm,cortex-a9-pmu;
+ interrupts = 0 68 4,
+0 69 4;
+ };
+
+ motherboard {
+ ranges = 0 0 0x0800 0x0400,
+1 0 0x1400 0x0400,
+2 0 0x1800 0x0400,
+3 0 0x1c00 0x0400,
+4 0 0x0c00 0x0400,
+5 0 0x1000 0x0400;
+
+ interrupt-map-mask = 0 0 63;
+ interrupt-map = 0 0 0 gic 0 0 4,
+ 0 0 1 gic 0 1 4,
+ 0 0 2 gic 0 2 4,
+ 0 0 3 gic 0 3 4,
+ 0 0 4 gic 0 4 4,
+ 0 0 5 gic 0 5 4,
+ 0 0 6 gic 0 6 4,
+ 0 0 7 gic 0 7 4,
+ 0 0 8 gic 0 8 4,
+ 0 0 9 gic 0 9 4,
+ 0 0 10 gic 0 10 4,
+ 0 0 11 gic 0 11 4,
+ 0 0 12 gic 0 12 4,
+ 0 0 13 gic 0 13 4,
+ 0 0 14 gic 0 14 4,
+ 0 0 15 gic 0 15 4,
+ 0 0 16 gic 0 16 4,
+ 0 0 17 gic 0 17 4,
+ 0 0 18 gic 0 18 4,
+ 0 0 19 gic 0 19 4,
+ 0 0 20 gic 0 20 4,
+ 0 0 21 gic 0 21 4,
+ 0 0 22 gic 0 22 4,
+ 0 0 23 gic 0 23 4,
+ 0 0 24 gic 0 24 4
[PATCH v5 8/9] ARM: vexpress: Add Device Tree for V2P-CA9 core tile
This patch adds Device Tree file for the CoreTile Express A9x4 (V2P-CA9).
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 190
arch/arm/mach-vexpress/Makefile.boot |3 +-
2 files changed, 192 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
new file mode 100644
index 000..84542e7
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -0,0 +1,190 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A9x4
+ * Cortex-A9 MPCore (V2P-CA9)
+ *
+ * HBI-0191B
+ */
+
+/dts-v1/;
+
+/include/ skeleton.dtsi
+
+/ {
+ model = V2P-CA9;
+ arm,hbi = 0x191;
+ compatible = arm,vexpress,v2p-ca9, arm,vexpress;
+ interrupt-parent = gic;
+
+ aliases {
+ serial0 = v2m_serial0;
+ serial1 = v2m_serial1;
+ serial2 = v2m_serial2;
+ serial3 = v2m_serial3;
+ i2c0 = v2m_i2c_dvi;
+ i2c1 = v2m_i2c_pcie;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 0;
+ next-level-cache = L2;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 1;
+ next-level-cache = L2;
+ };
+
+ cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 2;
+ next-level-cache = L2;
+ };
+
+ cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a9;
+ reg = 3;
+ next-level-cache = L2;
+ };
+ };
+
+ memory@6000 {
+ device_type = memory;
+ reg = 0x6000 0x4000;
+ };
+
+ clcd@1002 {
+ compatible = arm,pl111, arm,primecell;
+ reg = 0x1002 0x1000;
+ interrupts = 0 44 4;
+ };
+
+ memory-controller@100e {
+ compatible = arm,pl341, arm,primecell;
+ reg = 0x100e 0x1000;
+ };
+
+ memory-controller@100e1000 {
+ compatible = arm,pl354, arm,primecell;
+ reg = 0x100e1000 0x1000;
+ interrupts = 0 45 4,
+0 46 4;
+ };
+
+ timer@100e4000 {
+ compatible = arm,sp804, arm,primecell;
+ reg = 0x100e4000 0x1000;
+ interrupts = 0 48 4,
+0 49 4;
+ };
+
+ watchdog@100e5000 {
+ compatible = arm,sp805, arm,primecell;
+ reg = 0x100e5000 0x1000;
+ interrupts = 0 51 4;
+ };
+
+ scu@1e00 {
+ compatible = arm,cortex-a9-scu;
+ reg = 0x1e00 0x58;
+ };
+
+ timer@1e000600 {
+ compatible = arm,smp-twd;
+ reg = 0x1e000600 0x20;
+ interrupts = 1 2 0xf04,
+1 3 0xf04;
+ };
+
+ gic: interrupt-controller@1e001000 {
+ compatible = arm,cortex-a9-gic;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x1e001000 0x1000,
+ 0x1e000100 0x100;
+ };
+
+ L2: cache-controller@1e00a000 {
+ compatible = arm,pl310-cache;
+ reg = 0x1e00a000 0x1000;
+ interrupts = 0 43 4;
+ cache-level = 2;
+ arm,data-latency = 1 1 1;
+ arm,tag-latency = 1 1 1;
+ };
+
+ pmu {
+ compatible = arm,cortex-a9-pmu;
+ interrupts = 0 60 4,
+0 61 4,
+0 62 4,
+0 63 4;
+ };
+
+ motherboard {
+ ranges = 0 0 0x4000 0x0400,
+1 0 0x4400 0x0400,
+2 0 0x4800 0x0400,
+3 0 0x4c00 0x0400,
+7 0 0x1000 0x0002;
+
+ interrupt-map-mask = 0 0 63;
+ interrupt-map = 0 0 0 gic 0 0 4,
+ 0 0 1 gic 0 1 4,
+ 0 0 2 gic 0 2 4,
+ 0 0 3 gic 0 3 4,
+ 0 0 4 gic 0 4 4,
+ 0 0 5 gic 0 5 4,
+ 0 0 6 gic 0 6 4
[PATCH v5 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)
This patch adds Device Tree file for the CoreTile Express A15x2
(V2P-CA15) with Test Chip 1.
As the chip's GIC has 160 interrupt inputs, NR_IRQS is increased.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 155 +++
arch/arm/mach-vexpress/Makefile.boot|3 +-
arch/arm/mach-vexpress/include/mach/irqs.h |2 +-
3 files changed, 158 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
new file mode 100644
index 000..02cada5
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -0,0 +1,155 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A15x2 (version with Test Chip 1)
+ * Cortex-A15 MPCore (V2P-CA15)
+ *
+ * HBI-0237A
+ */
+
+/dts-v1/;
+
+/include/ skeleton.dtsi
+
+/ {
+ model = V2P-CA15;
+ arm,hbi = 0x237;
+ compatible = arm,vexpress,v2p-ca15,tc1, arm,vexpress,v2p-ca15,
arm,vexpress;
+ interrupt-parent = gic;
+
+ aliases {
+ serial0 = v2m_serial0;
+ serial1 = v2m_serial1;
+ serial2 = v2m_serial2;
+ serial3 = v2m_serial3;
+ i2c0 = v2m_i2c_dvi;
+ i2c1 = v2m_i2c_pcie;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0;
+ };
+
+ cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 1;
+ };
+ };
+
+ memory@8000 {
+ device_type = memory;
+ reg = 0x8000 0x4000;
+ };
+
+ hdlcd@2b00 {
+ compatible = arm,hdlcd;
+ reg = 0x2b00 0x1000;
+ interrupts = 0 85 4;
+ };
+
+ memory-controller@2b0a {
+ compatible = arm,pl341, arm,primecell;
+ reg = 0x2b0a 0x1000;
+ };
+
+ wdt@2b06 {
+ compatible = arm,sp805, arm,primecell;
+ reg = 0x2b06 0x1000;
+ interrupts = 98;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = arm,cortex-a9-gic;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x2c001000 0x1000,
+ 0x2c002000 0x100;
+ };
+
+ memory-controller@7ffd {
+ compatible = arm,pl354, arm,primecell;
+ reg = 0x7ffd 0x1000;
+ interrupts = 0 86 4,
+0 87 4;
+ };
+
+ dma@7ffb {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x7ffb 0x1000;
+ interrupts = 0 92 4,
+0 88 4,
+0 89 4,
+0 90 4,
+0 91 4;
+ };
+
+ pmu {
+ compatible = arm,cortex-a9-pmu;
+ interrupts = 0 68 4,
+0 69 4;
+ };
+
+ motherboard {
+ ranges = 0 0 0x0800 0x0400,
+1 0 0x1400 0x0400,
+2 0 0x1800 0x0400,
+3 0 0x1c00 0x0400,
+4 0 0x0c00 0x0400,
+5 0 0x1000 0x0400;
+
+ interrupt-map-mask = 0 0 63;
+ interrupt-map = 0 0 0 gic 0 0 4,
+ 0 0 1 gic 0 1 4,
+ 0 0 2 gic 0 2 4,
+ 0 0 3 gic 0 3 4,
+ 0 0 4 gic 0 4 4,
+ 0 0 5 gic 0 5 4,
+ 0 0 6 gic 0 6 4,
+ 0 0 7 gic 0 7 4,
+ 0 0 8 gic 0 8 4,
+ 0 0 9 gic 0 9 4,
+ 0 0 10 gic 0 10 4,
+ 0 0 11 gic 0 11 4,
+ 0 0 12 gic 0 12 4,
+ 0 0 13 gic 0 13 4,
+ 0 0 14 gic 0 14 4,
+ 0 0 15 gic 0 15 4,
+ 0 0 16 gic 0 16 4,
+ 0 0 17 gic 0 17 4,
+ 0 0 18 gic 0 18 4,
+ 0 0 19 gic 0 19 4,
+ 0 0 20 gic 0 20 4,
+ 0 0 21 gic 0 21 4,
+ 0 0 22 gic 0 22 4,
+ 0 0 23 gic 0 23 4
Re: [PATCH v4 3/6] ARM: vexpress: Add DT support for the motherboard
On Wed, 2011-12-07 at 22:49 +, Arnd Bergmann wrote:
On Tuesday 06 December 2011 15:43:46 Pawel Moll wrote:
+
+static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
+ OF_DEV_AUXDATA(arm,vexpress-flash, V2M_NOR0, physmap-flash,
+ v2m_flash_data),
+ OF_DEV_AUXDATA(arm,primecell, V2M_MMCI, mb:mmci,
v2m_mmci_data),
+ {}
+};
One more thing I noticed. While I'm not familiar with the progress on
device driver conversion,
I'm aware of these two last non-DT bits and actually already started
working on them, but this won't happen this year (I'm on holiday
starting next Friday without any access to Internet whatsoever :-)
I think you should be using the physmap_of
driver instead of physmap, which will remove the need for the
platform data.
There's one bit missing in the physmap_of. The set_vpp handle which is
used on VE:
static struct physmap_flash_data v2m_flash_data = {
.width = 4,
.set_vpp= v2m_flash_set_vpp,
};
My plan is to extend the physmap_of driver so it could operate VPP via
gpio API and make the sysreg a gpio controller, having Flash VPP, CF
MMC card detects and DVI output control (that's for CLCD) as internal
GPIO lines.
For mmci, it should not be hard to do change the driver so it
understands the device tree, too. The easiest implementation for
that would be to add some code into mmci_probe and allocate
an mmci_platform_data structure that gets filled with the required
attributes.
I've started the implementation already, but it turned out much trickier
that I was hoping... One thing is the status handle (card detect line
virtual gpio I mentioned above), the second problem is the fact that
mmci platform data can take generic caps MMC_CAP_* from
include/linux/mmc/host.h (now even caps2 as well)... This issue was
already briefly mentioned here:
http://article.gmane.org/gmane.linux.kernel.samsung-soc/7639 and as
there was no generic resolution my plan is to reuse as much properties
from other MMC host controllers and forge the missing one (as a superset
of ARM's and STE's cell implementations). But as I said, it's unlikely
to happen this year...
Cheers!
Paweł
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Re: [PATCH v4 5/6] ARM: vexpress: DT-based support for Cortex-A5 and Cortex-A9 based tiles
On Tue, 2011-12-06 at 23:13 +, Arnd Bergmann wrote: Actually, I have to take that back. Looking at both patch 5 and 6, the dt-ca*.c files are almost identical and all the differences are about stuff that you can find in the device tree: You are obviously right - I was rushing with that. Less is better then more ;-) Will respin tomorrow. * The iotable gets initialized from mrc p15, 4, %0, c15, c0, 0, which would be fine if that worked on all machines, but in order to unify the two files, I would recommend searching the flat device tree for the respective node and only map it if present. * You have two ways of finding out the number of cores, but looking in the device tree would just work either way. Those two are actually related, as it's all about memory mapped SCU in case of A5/A9 and CP15-controlled on A7/15 (the *smp_enable() is different as well). I'll probably just define a scu node compatible with arm,cortex-a9-scu and use the A5/A9 SMP callbacks if it's present (and create static mapping for it) or the A7/15 if it's missing. * You set the twd_base unconditionally on a5/a9 but never on a7/a15. This looks correct, but you could just as well see if a twd node exists and use its base address. I'll reuse Rob's Highbank solution and binding. * You only initialize the l2x0 on a5/a9. If a7/a15 don't have a matching l2x0 device, then calling the same function unconditionally should be harmless. Yep, that's not a problem. Thanks for all the other ack-bys and review-bys! Pawel ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v4 5/6] ARM: vexpress: DT-based support for Cortex-A5 and Cortex-A9 based tiles
On Wed, 2011-12-07 at 15:33 +, Dave Martin wrote: Oh, we should select HAVE_PATA_PLATFORM in here somewhere too. But that's not critical for this series. It's already selected in arch/arm/Kconfig: config ARCH_VEXPRESS bool ARM Ltd. Versatile Express family select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_AMBA select ARM_TIMER_SP804 select CLKDEV_LOOKUP select HAVE_MACH_CLKDEV select GENERIC_CLOCKEVENTS select HAVE_CLK select HAVE_PATA_PLATFORM select ICST select PLAT_VERSATILE select PLAT_VERSATILE_CLCD help This enables support for the ARM Ltd Versatile Express boards. Cheers! Pawel ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v4 0/6] Versatile Express DT support
Hello again, Here goes the fourth version of the series, hopefully something that could be merged for 3.3 (all Revieved-by-s and Acked-by-s welcomed!) Changes since v3: * The core tile support has been renamed (no real code change) to support for platforms based on a processor and the DTBs now must be now compatible with arm,vexpress-tile-model and arm,vexpress-processor, the latter being the important bit. Documentation has been updated accordingly (all language suggestions more then welcome). * Added support code for Cortex-A7 and Cortex-A15 based platforms and DTS for V2P-CA15 tile with Test Chip 1. * ARCH_VEXPRESS_RS1 has been dropped and the addresses in Makefile.boot are not modified, so the behaviour of the non-DT code is not changed at any time. ARCH_VEXPRESS_DT now enforces AUTO_ZRELADDR. * Compact Flash is now compatible with arm,vexpress-cf as well as with ata-generic. * V2x_PERIPH macros are now (void _iomem *) pointers and the V2x_PERIPH_P2V macros were dropped. * Wrong ARCH_VEXPRESS_DT-OF selection was fixed to -USE_OF. * PL310-related Kconfig options were aligned to Will's and Dave's changes. * make dtbs compile all provided vexpress-*.dts files now. Tested on: - V2P-CA9 with ATAGs - V2P-CA9 with DT - V2P-CA5s with DT - V2P-CA15 with DT - V2F-2XV6 Cortex-A7 SMM with DT Series v2 has been also tested by Ryan Harkin and provisionally acked by Rob Herring. Thanks for all your help, especially to Dave and Arnd for their continuous support! Pawel Moll (6): ARM: versatile: Add missing ENDPROC to headsmp.S ARM: vexpress: Get rid of MMIO_P2V ARM: vexpress: Add DT support for the motherboard ARM: vexpress: Motherboard RS1 memory map support ARM: vexpress: DT-based support for Cortex-A5 and Cortex-A9 based tiles ARM: vexpress: DT-based support for Cortex-A7 and Cortex-A15 based tiles Documentation/devicetree/bindings/arm/vexpress.txt | 118 + arch/arm/boot/dts/vexpress-v2m-rs1.dtsi| 196 +++ arch/arm/boot/dts/vexpress-v2m.dtsi| 195 +++ arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts| 138 +++ arch/arm/boot/dts/vexpress-v2p-ca5s.dts| 131 ++ arch/arm/boot/dts/vexpress-v2p-ca9.dts | 145 +++ arch/arm/include/asm/hardware/arm_timer.h |5 + arch/arm/mach-realview/platsmp.c |3 +- arch/arm/mach-vexpress/Kconfig | 68 +- arch/arm/mach-vexpress/Makefile|2 + arch/arm/mach-vexpress/Makefile.boot |6 + arch/arm/mach-vexpress/core.h | 19 ++- arch/arm/mach-vexpress/ct-ca9x4.c | 52 +--- arch/arm/mach-vexpress/dt-ca5_ca9.c| 114 + arch/arm/mach-vexpress/dt-ca7_ca15.c | 95 +++ arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 +- arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 +++- arch/arm/mach-vexpress/include/mach/irqs.h |2 +- arch/arm/mach-vexpress/include/mach/motherboard.h | 58 +++-- arch/arm/mach-vexpress/include/mach/uncompress.h | 13 +- arch/arm/mach-vexpress/platsmp.c |7 +- arch/arm/mach-vexpress/v2m.c | 259 ++-- arch/arm/plat-versatile/headsmp.S |1 + 23 files changed, 1557 insertions(+), 120 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/vexpress.txt create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts create mode 100644 arch/arm/mach-vexpress/dt-ca5_ca9.c create mode 100644 arch/arm/mach-vexpress/dt-ca7_ca15.c ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v4 1/6] ARM: versatile: Add missing ENDPROC to headsmp.S
Once the ENDPROC is in place, BSYM() in not longer necessary to get correct pointer to versatile_secondary_startup(). Signed-off-by: Pawel Moll pawel.m...@arm.com --- arch/arm/mach-realview/platsmp.c |3 +-- arch/arm/mach-vexpress/platsmp.c |4 +--- arch/arm/plat-versatile/headsmp.S |1 + 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index e83c654..17c878d 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -17,7 +17,6 @@ #include asm/hardware/gic.h #include asm/mach-types.h #include asm/smp_scu.h -#include asm/unified.h #include mach/board-eb.h #include mach/board-pb11mp.h @@ -75,6 +74,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) * until it receives a soft interrupt, and then the * secondary CPU branches to this address. */ - __raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)), + __raw_writel(virt_to_phys(versatile_secondary_startup), __io_address(REALVIEW_SYS_FLAGSSET)); } diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c index 2b5f7ac..124ffb1 100644 --- a/arch/arm/mach-vexpress/platsmp.c +++ b/arch/arm/mach-vexpress/platsmp.c @@ -13,8 +13,6 @@ #include linux/smp.h #include linux/io.h -#include asm/unified.h - #include mach/motherboard.h #define V2M_PA_CS7 0x1000 @@ -46,6 +44,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) * secondary CPU branches to this address. */ writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR)); - writel(BSYM(virt_to_phys(versatile_secondary_startup)), + writel(virt_to_phys(versatile_secondary_startup), MMIO_P2V(V2M_SYS_FLAGSSET)); } diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S index d397a1f..dd703ef 100644 --- a/arch/arm/plat-versatile/headsmp.S +++ b/arch/arm/plat-versatile/headsmp.S @@ -38,3 +38,4 @@ pen: ldr r7, [r6] .align 1: .long . .long pen_release +ENDPROC(versatile_secondary_startup) -- 1.6.3.3 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v4 2/6] ARM: vexpress: Get rid of MMIO_P2V
This patch gets rid of the MMIO_P2V and __MMIO_P2V macros,
defining constant virtual base for motherboard and tile
peripherals instead.
Additionally, in preparation for the new motherboard memory
map, the motherboard peripherals are using base pointers
calculated in runtime, instead of compile-time calculated
values.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/include/asm/hardware/arm_timer.h |5 ++
arch/arm/mach-vexpress/core.h |9 ++-
arch/arm/mach-vexpress/ct-ca9x4.c | 52
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h| 13 ++---
arch/arm/mach-vexpress/include/mach/motherboard.h | 52
arch/arm/mach-vexpress/platsmp.c |5 +-
arch/arm/mach-vexpress/v2m.c | 68 ++---
7 files changed, 100 insertions(+), 104 deletions(-)
diff --git a/arch/arm/include/asm/hardware/arm_timer.h
b/arch/arm/include/asm/hardware/arm_timer.h
index c0f4e7b..d6030ff 100644
--- a/arch/arm/include/asm/hardware/arm_timer.h
+++ b/arch/arm/include/asm/hardware/arm_timer.h
@@ -9,7 +9,12 @@
*
* Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
* can have 16-bit or 32-bit selectable via a bit in the control register.
+ *
+ * Every SP804 contains two identical timers.
*/
+#define TIMER_1_BASE 0x00
+#define TIMER_2_BASE 0x20
+
#define TIMER_LOAD 0x00/* ACVR rw */
#define TIMER_VALUE0x04/* ACVR ro */
#define TIMER_CTRL 0x08/* ACVR rw */
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index f439715..75a640a 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -1,6 +1,3 @@
-#define __MMIO_P2V(x) (((x) 0xf) | (((x) 0x0f00) 4) |
0xf800)
-#define MMIO_P2V(x)((void __iomem *)__MMIO_P2V(x))
-
#define AMBA_DEVICE(name,busid,base,plat) \
struct amba_device name##_device = { \
.dev= { \
@@ -17,3 +14,9 @@ struct amba_device name##_device = { \
.irq= IRQ_##base, \
/* .dma = DMA_##base,*/ \
}
+
+/* 2MB large area for motherboard's peripherals static mapping */
+#define V2M_PERIPH ((void __iomem *)0xf800)
+
+/* Tile's peripherals static mappings should start here */
+#define V2T_PERIPH ((void __iomem *)0xf820)
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c
b/arch/arm/mach-vexpress/ct-ca9x4.c
index 2b1e836..a9e5e72 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -30,57 +30,26 @@
#include plat/clcd.h
-#define V2M_PA_CS7 0x1000
-
static struct map_desc ct_ca9x4_io_desc[] __initdata = {
{
- .virtual= __MMIO_P2V(CT_CA9X4_MPIC),
- .pfn= __phys_to_pfn(CT_CA9X4_MPIC),
- .length = SZ_16K,
- .type = MT_DEVICE,
- }, {
- .virtual= __MMIO_P2V(CT_CA9X4_SP804_TIMER),
- .pfn= __phys_to_pfn(CT_CA9X4_SP804_TIMER),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual= __MMIO_P2V(CT_CA9X4_L2CC),
- .pfn= __phys_to_pfn(CT_CA9X4_L2CC),
- .length = SZ_4K,
- .type = MT_DEVICE,
+ .virtual= (unsigned long)V2T_PERIPH,
+ .pfn= __phys_to_pfn(CT_CA9X4_MPIC),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
},
};
static void __init ct_ca9x4_map_io(void)
{
-#ifdef CONFIG_LOCAL_TIMERS
- twd_base = MMIO_P2V(A9_MPCORE_TWD);
-#endif
iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
}
static void __init ct_ca9x4_init_irq(void)
{
- gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
-MMIO_P2V(A9_MPCORE_GIC_CPU));
-}
-
-#if 0
-static void __init ct_ca9x4_timer_init(void)
-{
- writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
- writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
-
- sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), ct-timer1);
- sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
- ct-timer0);
+ gic_init(0, 29, V2T_PERIPH + A9_MPCORE_GIC_DIST,
+V2T_PERIPH + A9_MPCORE_GIC_CPU);
}
-static struct sys_timer ct_ca9x4_timer = {
- .init = ct_ca9x4_timer_init,
-};
-#endif
-
static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
{
v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
@@ -193,6 +162,9 @@ static struct platform_device pmu_device = {
static void __init ct_ca9x4_init_early(void)
{
+#ifdef CONFIG_LOCAL_TIMERS
+ twd_base = V2T_PERIPH + A9_MPCORE_TWD;
+#endif
clkdev_add_table(lookups
[PATCH v4 3/6] ARM: vexpress: Add DT support for the motherboard
This patch provides hooks for DT-based tile machine implementations
and adds Flattened Device Tree description for the motherboard.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
Documentation/devicetree/bindings/arm/vexpress.txt | 118
arch/arm/boot/dts/vexpress-v2m.dtsi| 195
arch/arm/mach-vexpress/Kconfig | 12 ++
arch/arm/mach-vexpress/Makefile.boot |2 +
arch/arm/mach-vexpress/core.h | 10 +
arch/arm/mach-vexpress/include/mach/motherboard.h |6 +
arch/arm/mach-vexpress/v2m.c | 129 +-
7 files changed, 470 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/vexpress.txt
create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
diff --git a/Documentation/devicetree/bindings/arm/vexpress.txt
b/Documentation/devicetree/bindings/arm/vexpress.txt
new file mode 100644
index 000..d82c36e
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vexpress.txt
@@ -0,0 +1,118 @@
+ARM Versatile Express boards family
+---
+
+ARM's Versatile Express platform consists of a motherboard and one
+or more daughterboards (tiles). The motherboard provides a set of
+peripherals. Processor and RAM live on the tiles.
+
+The motherboard and each core tile should be described by a separate
+Device Tree source file, with the tile's description including
+the motherboard file using a /include/ directive. As the motherboard
+can be initialized in one of two different configurations (memory
+maps), care must be taken to include the correct one.
+
+Required properties in the root node:
+- compatible value:
+ compatible = arm,vexpress-model, arm,vexpress-processor;
+ where:
+ - processor is type of the tile's processor, one of:
+ - arm,vexpress-cortex_a5 for Cortex-A5 based tile,
+ - arm,vexpress-cortex_a7 for Cortex-A7 based tile,
+ - arm,vexpress-cortex_a9 for Cortex-A9 based tile,
+ - arm,vexpress-cortex_a15 for Cortex-A15 based tile.
+ - model is the full tile model name (as used in the tile's
+Technical Reference Manual), eg.:
+- for Coretile Express A5x2 (V2P-CA5s):
+ compatible = arm,vexpress-v2p-ca5s, arm,vexpress-cortex_a5;
+- Coretile Express A9x4 (V2P-CA9):
+ compatible = arm,vexpress-v2p-ca9, arm,vexpress-cortex_a9;
+- Coretile Express A15x2 (V2P-CA15):
+ compatible = arm,vexpress-v2p-ca15, arm,vexpress-cortex_a15;
+
+Current Linux implementation relies on the processor type value.
+
+Optional properties in the root node:
+- tile model name (use the same names as in the tile's Technical
+ Reference Manuals, eg. V2P-CA5s)
+ model = model;
+- tile's HBI number (unique ARM's board model ID, visible on the
+ PCB's silkscreen) in hexadecimal transcription:
+ arm,hbi = 0xhbi
+ eg:
+ - for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
+ arm,hbi = 0x191;
+ - Coretile Express A9x4 (V2P-CA9) HBI-0225:
+ arm,hbi = 0x225;
+
+The motherboard description file provides a single motherboard node
+using 2 address cells corresponding to the Static Memory Bus used
+between the motherboard and the tile. The first cell defines the Chip
+Select (CS) line number, the second cell address offset within the CS.
+All interrupt lines between the motherboard and the tile are active
+high and are described using single cell.
+
+Optional properties of the motherboard node:
+- motherboard's memory map variant:
+ arm,v2m-memory-map = name;
+ where name is one of:
+ - rs1 - for RS1 map (i.a. peripherals on CS3); this map is also
+referred to as ARM Cortex-A Series memory map:
+ arm,v2m-memory-map = rs1;
+ When this property is missing, the motherboard is using the original
+ memory map (also known as the Legacy memory map, primarily used
+ with the original CoreTile Express A9x4) with peripherals on CS7.
+
+Motherboard .dtsi files provide a set of labelled peripherals that
+can be used to obtain required phandle in the tile's aliases node:
+- UARTs, note that the numbers correspond to the physical connectors
+ on the motherboard's back panel:
+ v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3
+- I2C controllers:
+ v2m_i2c_dvi and v2m_i2c_pcie
+- SP804 timers:
+ v2m_timer01 and v2m_timer23
+
+Current Linux implementation requires a arm,v2m_timer alias
+pointing at one of the motherboard's SP804 timers, if it is to be
+used as the system timer. This alias should be defined in the
+motherboard files.
+
+The tile description must define ranges, interrupt-map-mask and
+interrupt-map properties to translate the motherboard's address
+and interrupt space into one used by the tile's processor.
+
+Abbreviated example:
+
+/dts-v1/;
+
+/include/ skeleton.dtsi
+
+/ {
+ model = V2P-CA5s;
+ arm,hbi = 0x225;
+ compatible = arm,vexpress-v2p-ca5s;
+ interrupt-parent = gic
[PATCH v4 4/6] ARM: vexpress: Motherboard RS1 memory map support
This patch adds support for RS1 memory map based Versatile Express
motherboard.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 196 +
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 -
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 ++-
arch/arm/mach-vexpress/v2m.c | 64 +++-
4 files changed, 304 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
new file mode 100644
index 000..a7d385f
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -0,0 +1,196 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * RS1 memory map (ARM Cortex-A Series memory map in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * original variant (vexpress-v2m.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m.dtsi!
+ */
+
+/ {
+ aliases {
+ arm,v2m_timer = v2m_timer01;
+ };
+
+ motherboard {
+ compatible = simple-bus;
+ arm,v2m-memory-map = rs1;
+ #address-cells = 2; /* SMB chipselect number and offset */
+ #size-cells = 1;
+ #interrupt-cells = 1;
+
+ flash@0, {
+ compatible = arm,vexpress-flash, cfi-flash;
+ reg = 0 0x 0x0400,
+ 4 0x 0x0400;
+ bank-width = 4;
+ };
+
+ psram@1, {
+ compatible = mtd-ram;
+ reg = 1 0x 0x0200;
+ bank-width = 4;
+ };
+
+ ethernet@2,0200 {
+ compatible = smsc,lan9118, smsc,lan9115;
+ reg = 2 0x0200 0x1;
+ interrupts = 15;
+ phy-mode = mii;
+ reg-io-width = 4;
+ smsc,irq-active-high;
+ smsc,irq-push-pull;
+ };
+
+ usb@2,0300 {
+ compatible = nxp,usb-isp1761;
+ reg = 2 0x0300 0x2;
+ interrupts = 16;
+ port1-otg;
+ };
+
+ iofpga@3, {
+ compatible = arm,amba-bus, simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 3 0 0x20;
+
+ sysreg@01 {
+ compatible = arm,vexpress-sysreg;
+ reg = 0x01 0x1000;
+ };
+
+ sysctl@02 {
+ compatible = arm,sp810, arm,primecell;
+ reg = 0x02 0x1000;
+ };
+
+ /* PCI-E I2C bus */
+ v2m_i2c_pcie: i2c@03 {
+ compatible = arm,versatile-i2c;
+ reg = 0x03 0x1000;
+
+ #address-cells = 1;
+ #size-cells = 0;
+
+ pcie-switch@60 {
+ compatible = idt,89hpes32h8;
+ reg = 0x60;
+ };
+ };
+
+ aaci@04 {
+ compatible = arm,pl041, arm,primecell;
+ reg = 0x04 0x1000;
+ interrupts = 11;
+ };
+
+ mmci@05 {
+ compatible = arm,pl180, arm,primecell;
+ reg = 0x05 0x1000;
+ interrupts = 9 10;
+ };
+
+ kmi@06 {
+ compatible = arm,pl050, arm,primecell;
+ reg = 0x06 0x1000;
+ interrupts = 12;
+ };
+
+ kmi@07 {
+ compatible = arm,pl050, arm,primecell;
+ reg = 0x07 0x1000;
+ interrupts = 13;
+ };
+
+ v2m_serial0: uart@09 {
+ compatible = arm,pl011, arm,primecell;
+ reg = 0x09 0x1000
[PATCH v4 5/6] ARM: vexpress: DT-based support for Cortex-A5 and Cortex-A9 based tiles
This patch adds Flattened Device Trees based support for ARM Ltd.
Versatile Express platforms based on Cortex-A5 and Cortex-A9
processors.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 131
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 145 +++
arch/arm/mach-vexpress/Kconfig | 39 +++-
arch/arm/mach-vexpress/Makefile |1 +
arch/arm/mach-vexpress/Makefile.boot|3 +
arch/arm/mach-vexpress/dt-ca5_ca9.c | 114
6 files changed, 428 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
create mode 100644 arch/arm/mach-vexpress/dt-ca5_ca9.c
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
new file mode 100644
index 000..205d9a0
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -0,0 +1,131 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A5x2
+ * Cortex-A5 MPCore (V2P-CA5s)
+ *
+ * HBI-0225B
+ */
+
+/dts-v1/;
+
+/include/ skeleton.dtsi
+
+/ {
+ model = V2P-CA5s;
+ arm,hbi = 0x225;
+ compatible = arm,vexpress-v2p-ca5s, arm,vexpress-cortex_a5;
+ interrupt-parent = gic;
+
+ aliases {
+ serial0 = v2m_serial0;
+ serial1 = v2m_serial1;
+ serial2 = v2m_serial2;
+ serial3 = v2m_serial3;
+ i2c0 = v2m_i2c_dvi;
+ i2c1 = v2m_i2c_pcie;
+ };
+
+ memory@8000 {
+ device_type = memory;
+ reg = 0x8000 0x4000;
+ };
+
+ hdlcd@2a11 {
+ compatible = arm,hdlcd;
+ reg = 0x2a11 0x1000;
+ interrupts = 0 85 4;
+ };
+
+ memory-controller@2a15 {
+ compatible = arm,pl341, arm,primecell;
+ reg = 0x2a15 0x1000;
+ };
+
+ memory-controller@2a19 {
+ compatible = arm,pl354, arm,primecell;
+ reg = 0x2a19 0x1000;
+ interrupts = 0 86 4,
+0 87 4;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = arm,cortex-a9-gic;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x2c001000 0x1000,
+ 0x2c000100 0x100;
+ };
+
+ L2: cache-controller@2c0f {
+ compatible = arm,pl310-cache;
+ reg = 0x2c0f 0x1000;
+ interrupts = 0 84 4;
+ cache-level = 2;
+ arm,data-latency = 0;
+ arm,tag-latency = 0;
+ };
+
+ pmu {
+ compatible = arm,cortex-a9-pmu;
+ interrupts = 0 68 4,
+0 69 4;
+ };
+
+ motherboard {
+ ranges = 0 0 0x0800 0x0400,
+1 0 0x1400 0x0400,
+2 0 0x1800 0x0400,
+3 0 0x1c00 0x0400,
+4 0 0x0c00 0x0400,
+5 0 0x1000 0x0400;
+
+ interrupt-map-mask = 0 0 63;
+ interrupt-map = 0 0 0 gic 0 0 4,
+ 0 0 1 gic 0 1 4,
+ 0 0 2 gic 0 2 4,
+ 0 0 3 gic 0 3 4,
+ 0 0 4 gic 0 4 4,
+ 0 0 5 gic 0 5 4,
+ 0 0 6 gic 0 6 4,
+ 0 0 7 gic 0 7 4,
+ 0 0 8 gic 0 8 4,
+ 0 0 9 gic 0 9 4,
+ 0 0 10 gic 0 10 4,
+ 0 0 11 gic 0 11 4,
+ 0 0 12 gic 0 12 4,
+ 0 0 13 gic 0 13 4,
+ 0 0 14 gic 0 14 4,
+ 0 0 15 gic 0 15 4,
+ 0 0 16 gic 0 16 4,
+ 0 0 17 gic 0 17 4,
+ 0 0 18 gic 0 18 4,
+ 0 0 19 gic 0 19 4,
+ 0 0 20 gic 0 20 4,
+ 0 0 21 gic 0 21 4,
+ 0 0 22 gic 0 22 4,
+ 0 0 23 gic 0 23 4,
+ 0 0 24 gic 0 24 4,
+ 0 0 25 gic 0 25 4,
+ 0 0 26 gic 0 26 4,
+ 0 0 27 gic 0 27 4,
+ 0 0 28 gic 0 28 4,
+ 0 0 29 gic 0 29 4,
+ 0 0 30 gic 0 30 4,
+ 0 0 31 gic 0 31 4
[PATCH v4 6/6] ARM: vexpress: DT-based support for Cortex-A7 and Cortex-A15 based tiles
This patch adds Flattened Device Trees based support for ARM Ltd.
Versatile Express platforms based on Cortex-A7 and Cortex-A15
processors.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts | 138 +++
arch/arm/mach-vexpress/Kconfig | 19
arch/arm/mach-vexpress/Makefile |1 +
arch/arm/mach-vexpress/Makefile.boot|1 +
arch/arm/mach-vexpress/dt-ca7_ca15.c| 95 ++
arch/arm/mach-vexpress/include/mach/irqs.h |2 +-
6 files changed, 255 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
create mode 100644 arch/arm/mach-vexpress/dt-ca7_ca15.c
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
new file mode 100644
index 000..b19bb81
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -0,0 +1,138 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A15x2 (version with Test Chip 1)
+ * Cortex-A15 MPCore (V2P-CA15)
+ *
+ * HBI-0237A
+ */
+
+/dts-v1/;
+
+/include/ skeleton.dtsi
+
+/ {
+ model = V2P-CA15;
+ arm,hbi = 0x237;
+ compatible = arm,vexpress-v2p-ca15-tc1, arm,vexpress-v2p-ca15,
arm,vexpress-cortex_a15;
+ interrupt-parent = gic;
+
+ aliases {
+ serial0 = v2m_serial0;
+ serial1 = v2m_serial1;
+ serial2 = v2m_serial2;
+ serial3 = v2m_serial3;
+ i2c0 = v2m_i2c_dvi;
+ i2c1 = v2m_i2c_pcie;
+ };
+
+ memory@8000 {
+ device_type = memory;
+ reg = 0x8000 0x4000;
+ };
+
+ hdlcd@2b00 {
+ compatible = arm,hdlcd;
+ reg = 0x2b00 0x1000;
+ interrupts = 0 85 4;
+ };
+
+ memory-controller@2b0a {
+ compatible = arm,pl341, arm,primecell;
+ reg = 0x2b0a 0x1000;
+ };
+
+ wdt@2b06 {
+ compatible = arm,sp805, arm,primecell;
+ reg = 0x2b06 0x1000;
+ interrupts = 98;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = arm,cortex-a9-gic;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x2c001000 0x1000,
+ 0x2c002000 0x100;
+ };
+
+ memory-controller@7ffd {
+ compatible = arm,pl354, arm,primecell;
+ reg = 0x7ffd 0x1000;
+ interrupts = 0 86 4,
+0 87 4;
+ };
+
+ dma@7ffb {
+ compatible = arm,pl330, arm,primecell;
+ reg = 0x7ffb 0x1000;
+ interrupts = 0 92 4,
+0 88 4,
+0 89 4,
+0 90 4,
+0 91 4;
+ };
+
+ pmu {
+ compatible = arm,cortex-a9-pmu;
+ interrupts = 0 68 4,
+0 69 4;
+ };
+
+ motherboard {
+ ranges = 0 0 0x0800 0x0400,
+1 0 0x1400 0x0400,
+2 0 0x1800 0x0400,
+3 0 0x1c00 0x0400,
+4 0 0x0c00 0x0400,
+5 0 0x1000 0x0400;
+
+ interrupt-map-mask = 0 0 63;
+ interrupt-map = 0 0 0 gic 0 0 4,
+ 0 0 1 gic 0 1 4,
+ 0 0 2 gic 0 2 4,
+ 0 0 3 gic 0 3 4,
+ 0 0 4 gic 0 4 4,
+ 0 0 5 gic 0 5 4,
+ 0 0 6 gic 0 6 4,
+ 0 0 7 gic 0 7 4,
+ 0 0 8 gic 0 8 4,
+ 0 0 9 gic 0 9 4,
+ 0 0 10 gic 0 10 4,
+ 0 0 11 gic 0 11 4,
+ 0 0 12 gic 0 12 4,
+ 0 0 13 gic 0 13 4,
+ 0 0 14 gic 0 14 4,
+ 0 0 15 gic 0 15 4,
+ 0 0 16 gic 0 16 4,
+ 0 0 17 gic 0 17 4,
+ 0 0 18 gic 0 18 4,
+ 0 0 19 gic 0 19 4,
+ 0 0 20 gic 0 20 4,
+ 0 0 21 gic 0 21 4,
+ 0 0 22 gic 0 22 4,
+ 0 0 23 gic 0 23 4,
+ 0 0 24 gic 0 24 4,
+ 0 0 25 gic 0 25 4,
+ 0 0 26 gic 0 26 4,
+ 0 0 27 gic 0 27 4
Re: [PATCH v3 3/5] ARM: vexpress: Add DT support in v2m
On Mon, 2011-12-05 at 16:25 +, Dave Martin wrote:
On Tue, Nov 29, 2011 at 03:11:11PM +, Pawel Moll wrote:
This patch provides hooks for DT-based tile machine implementations
and adds Device Tree description for the motherboard.
[...]
+static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
+ OF_DEV_AUXDATA(arm,vexpress-flash, V2M_NOR0, physmap-flash,
+ v2m_flash_data),
+ OF_DEV_AUXDATA(arm,primecell, V2M_MMCI, mb:mmci, v2m_mmci_data),
+ {}
Are we missing some AUXDATA here? I thought we had a lot more drivers
which are not converted to OF, such as ambakmi and many more.
No, as Rob suggested I removed all the devices that don't need platform
data and were there only for the clocks sake and created explicit lookup
tables for them. The ambakmi you have mentioned doesn't take any
platform data, just the resources and clock, so it works fine.
I notice some things explicitly failing, e.g.:
clcd-pl11x: probe of 1002.clcd failed with error -22
clcd-pl11x: probe of 1001f000.clcd failed with error -22
...I haven't tracked down exactly what is going on here, yet.
CLCD is the only device that doesn't work right now. I've skipped it
intentionally as it was configured in a non-trivial way on a per-tile
basis (and passing two separate sets of auxdata is tricky) and the work
on bindings for the driver is ongoing.
Probably this should be mentioned in the patch description. Will do.
Cheers!
Paweł
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Re: [PATCH v3 5/5] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4
On Thu, 2011-12-01 at 12:21 +, Dave Martin wrote:
That will work, but we should make it clear that this option does not
provide board support all by itself, maybe:
Provides common dependencies for VE platforms based on Cortex-A5 or
Cortex-A9 processors. In order to build a working kernel, you must also
enable one or more core tile support options.
Actually, the longer I think about it the more it seems that this code
doesn't support a particular tile, but rather a particular processor...
After all _exactly_ the same code will work with any SMM based on FPGA
Logic Tile (V2F-2XV6), even if it was very different from the coretile,
eg. A9 with RS1 memory map. In such case making it compatible with
V2P-CA9 would be logically wrong...
I have an idea of spinning the compatible values again to get something
like that:
compatible = arm,vexpress-v2p-ca5s, arm,vexpress-cortex_a5;
compatible = arm,vexpress-v2p-ca9, arm,vexpress-cortex_a9;
compatible = arm,vexpress-v2p-ca15, arm,vexpress-cortex_a15;
and the board code would simply have:
static const char *dt_ca5_ca9_dt_match[] __initdata = {
arm,vexpress-cortex_a5,
arm,vexpress-cortex_a9,
NULL,
};
I've already tried that (adding tree for A15 tile as well) and it
actually simplifies a lot of things. I'll clean the patches, test them
and post tomorrow. Of course if anyone thinks it's a bad idea I'm happy
to get back to where we were last week.
Cheers!
Paweł
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Re: [PATCH v3 5/5] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4
On Mon, 2011-12-05 at 17:37 +, Dave Martin wrote:
I have an idea of spinning the compatible values again to get something
like that:
compatible = arm,vexpress-v2p-ca5s, arm,vexpress-cortex_a5;
compatible = arm,vexpress-v2p-ca9, arm,vexpress-cortex_a9;
compatible = arm,vexpress-v2p-ca15, arm,vexpress-cortex_a15;
The trouble is, node { compatible = x } means node is an x, not node
has an x.
Yes...
So, we should be careful do document what e.g. arm,vexpress-cortex_a5
actually means. It doesn't mean Cortex-A5, but instead it represents
a whole jumble of characteristics which we expect to be common to all
vexpress-based A5 platforms.
... so I'd translate it as is a Versatile Express platform based on
Cortex-A5 processor and document it as such. As I said - patches
tomorrow.
It feels that in practice arm,vexpress-cortex_a5 actually means
exactly the same thing as arm,vexpress-v2p-ca5s. Are you sure these
two are really independent? (In other words, do we expect multiple
different vexpress variants based on A5, and so on?)
The examples for A5 I can quota are two different SMMs I used (one on a
small, second one on a large FPGA board), but they were very similar
to the A5 core tile - so similar that you could (probably) use the core
tile DTB to drive them. The A9 SMM with RS1 memory map I've mentioned is
much more interesting case - A9 platform but nothing like original A9
core tile... Also the A15 looks interesting as we will most likely get
the same tiles (as in: PCB) with different processors (as in: different
silicon). This will be fun :-)
Cheers!
Paweł
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Re: [PATCH v3 3/5] ARM: vexpress: Add DT support in v2m
On Tue, 2011-11-29 at 21:19 +, Arnd Bergmann wrote:
On Tuesday 29 November 2011, Pawel Moll wrote:
+ compact-flash@1a000 {
+ compatible = ata-generic;
+ reg = 0x1a000 0x100
+ 0x1a100 0xf00;
+ reg-shift = 2;
+ };
Shouldn't there also be a more specific compatible value, in case we have
to detect this CF slot for some reason?
It was the compatible-value-of-choice in
drivers/ata/pata_of_platform.c, unfortunately undocumented - as I have
just realized - in the Documentation/devicetree/bindings...
Is there actually no interrupt?
No, polling mode only. And yes, it works ;-)
Cheers!
Paweł
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Re: [PATCH v3 0/5] Versatile Express DT support
On Wed, 2011-11-30 at 12:08 +, Dave Martin wrote: Your suggestion fixes it -- I suggest we keep the config this way round; this means that OF gets turned on when enabling a coretile which requires it, and those coretiles are offered as choices even before OF is turned on. That feels like a sensible behaviour for the config. Ok. While we're about this, building of the applicable dtbs is not currently enabled. Can we add this, so that make dtbs works? diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot index 05b77a5..b89ffde 100644 --- a/arch/arm/mach-vexpress/Makefile.boot +++ b/arch/arm/mach-vexpress/Makefile.boot @@ -7,3 +7,7 @@ else params_phys-y:= 0x6100 initrd_phys-y:= 0x6080 endif + +dtb-$(CONFIG_ARCH_VEXPRESS_V2P_CA5S_CA9) += \ + vexpress-v2p-ca5s.dtb \ + vexpress-v2p-ca9.dtb Yes, I already have more-or-less the same thing. Cheers! Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v3 3/5] ARM: vexpress: Add DT support in v2m
On Wed, 2011-11-30 at 13:34 +, Arnd Bergmann wrote:
On Wednesday 30 November 2011, Pawel Moll wrote:
On Tue, 2011-11-29 at 21:19 +, Arnd Bergmann wrote:
On Tuesday 29 November 2011, Pawel Moll wrote:
+ compact-flash@1a000 {
+ compatible = ata-generic;
+ reg = 0x1a000 0x100
+ 0x1a100 0xf00;
+ reg-shift = 2;
+ };
Shouldn't there also be a more specific compatible value, in case we
have
to detect this CF slot for some reason?
It was the compatible-value-of-choice in
drivers/ata/pata_of_platform.c, unfortunately undocumented - as I have
just realized - in the Documentation/devicetree/bindings...
You should certainly *also* have ata-generic in there as the value
that is used by the existing driver, but it usually makes sense to have
a more specific value in addition, just as a precaution for the future,
in case that the specific hardware is not entirely identical to all others
and we have to do a separate workaround.
Ok, as the actual interface hardware is a custom design for VE, I'll
make it:
compatible = arm,vexpress-cf, ata-generic;
Does it make sense?
Cheers!
Paweł
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Re: [PATCH v3 4/5] ARM: vexpress: Initial RS1 memory map support
On Wed, 2011-11-30 at 17:54 +, Dave Martin wrote: It would be nice to know what's going on here, but I'm reasonably convinced that we're just booting the kernel in a silly way here, and U-Boot really needs to be fixed to avoid the fixed-load-address limitation. If you send me (privately, probably) your U-boot binary I will have a look tomorrow. I'd like to be sure I understand what is going wrong... Cheers Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v3 5/5] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4
On Tue, 2011-11-29 at 16:40 +, Dave Martin wrote: Note that select PL310_ERRATA_753970 if CACHE_PL310 also needs to be propagated to ARCH_VEXPRESS_CA9X4. Maybe we should have a common symbol which selects/depends on the common stuff instead of duplicating it for every coretile -- they will tend to get out of sync. How about that? 8-- menu Versatile Express platform type depends on ARCH_VEXPRESS config ARCH_VEXPRESS_CORTEX_A5_A9 bool select ARM_ERRATA_720789 select ARM_ERRATA_751472 select ARM_GIC select CPU_V7 select HAVE_L2X0_L2CC select PL310_ERRATA_753970 if CACHE_PL310 help VE platforms based on Cortex-A5 or Cortex-A9 processors. config ARCH_VEXPRESS_CA9X4 bool Versatile Express Cortex-A9x4 tile select ARCH_VEXPRESS_CORTEX_A5_A9 help This option enabled support for VE system using original CoreTile Express A9x4 (V2P-CA9) initialized with ATAGs. config ARCH_VEXPRESS_RS1 bool select ARM_PATCH_PHYS_VIRT select AUTO_ZRELADDR help RS1 VE memory map (i.a. motherboard peripherals at 0x1c00, RAM at 0x8000). config ARCH_VEXPRESS_DT bool select USE_OF help VE platforms *requiring* Flattened Device Tree to boot. config ARCH_VEXPRESS_V2P_CA5S_CA9 bool CoreTile Express A5x2 and A9x4 based platform support select ARCH_VEXPRESS_CORTEX_A5_A9 select ARCH_VEXPRESS_DT select ARCH_VEXPRESS_RS1 help This option enables support for systems using any of the following ARM core tiles on the Versatile Express motherboard: - CoreTile Express A5x2 (V2P-CA5s) - CoreTile Express A9x4 (V2P-CA9) You must boot using a Flattened Device Tree in order to use these platforms. The traditional (ATAGs) boot method is not usable on these boards with this option. If you want your kernel to run on one of these platforms and your bootloader supports Flattened Device Tree based booting, say Y. endmenu 8-- Cheers! Pawel ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v3 3/5] ARM: vexpress: Add DT support in v2m
On Wed, 2011-11-30 at 15:58 +, Dave Martin wrote: Now that a person may fail to boot on a supported board simply due to failing to supply a device tree, it may be a good idea to have a more helpful panic message for that situation, perhaps something like the following. If you don't think this fits in this series, I can always follow up later. diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 6965f64..9dda482 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c @@ -434,8 +434,11 @@ static void __init v2m_populate_ct_desc(void) ct_desc = ct_descs[i]; if (!ct_desc) - panic(vexpress: failed to populate core tile description - for tile ID 0x%8x\n, current_tile_id); + panic(vexpress: this kernel does not support core tile ID + 0x%08x when booting via ATAGs.\n + You may need a device tree blob or a different kernel + to boot on this board.\n, + current_tile_id); } static void __init v2m_map_io(void) No, that's cool with me, will add that. Thanks! Pawel ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v3 0/5] Versatile Express DT support
Hi All, Another, hopefully close to the final, version of the series... Changes from v2: * new patch adding ENDPROC at the end of arch/arm/plat-versatile/headsmp.S and removing use of BSYM() realview and vexpress platform SMP calls * updated binding documentation according to Dave's comments * changed motherboard labels prefix from mb_ to v2m_ (to be consistent across code and DT files) * reworked v2m timer initialization (again) so no #ifdefs are required in non-DT code * renamed (to vendor- and platform-specific arm,v2m-timer) and moved (to vexpress-v2m*.dtsi files) timer DT alias, as it is actually motherboard specific and the tile DTS shouldn't have to care; documentation updated accordingly Tested on V2P-CA9 with ATAGs and DT and on V2P-CA5s with DT. Previous version has been also tested by Ryan Harkin and provisionally acked by Rob Herring. Thanks for all your help, especially to Dave for his continuous support! Pawel Moll (5): ARM: versatile: Add missing ENDPROC to headsmp.S ARM: vexpress: Get rid of MMIO_P2V ARM: vexpress: Add DT support in v2m ARM: vexpress: Initial RS1 memory map support ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4 Documentation/devicetree/bindings/arm/vexpress.txt | 108 + arch/arm/boot/dts/vexpress-v2m-rs1.dtsi| 196 +++ arch/arm/boot/dts/vexpress-v2m.dtsi| 195 +++ arch/arm/boot/dts/vexpress-v2p-ca5s.dts| 131 ++ arch/arm/boot/dts/vexpress-v2p-ca9.dts | 145 +++ arch/arm/include/asm/hardware/arm_timer.h |5 + arch/arm/mach-realview/platsmp.c |3 +- arch/arm/mach-vexpress/Kconfig | 37 +++ arch/arm/mach-vexpress/Makefile|1 + arch/arm/mach-vexpress/Makefile.boot |6 + arch/arm/mach-vexpress/core.h | 21 ++- arch/arm/mach-vexpress/ct-ca9x4.c | 52 +--- arch/arm/mach-vexpress/include/mach/ct-ca9x4.h | 13 +- arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 +++- arch/arm/mach-vexpress/include/mach/motherboard.h | 58 +++-- arch/arm/mach-vexpress/include/mach/uncompress.h | 13 +- arch/arm/mach-vexpress/platsmp.c |7 +- arch/arm/mach-vexpress/v2m.c | 255 ++-- arch/arm/mach-vexpress/v2p-ca5s_ca9.c | 115 + arch/arm/plat-versatile/headsmp.S |1 + 20 files changed, 1286 insertions(+), 113 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/vexpress.txt create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts create mode 100644 arch/arm/mach-vexpress/v2p-ca5s_ca9.c ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v3 1/5] ARM: versatile: Add missing ENDPROC to headsmp.S
Once the ENDPROC is in place, BSYM() in not longer necessary to get correct pointer to versatile_secondary_startup(). Signed-off-by: Pawel Moll pawel.m...@arm.com --- arch/arm/mach-realview/platsmp.c |3 +-- arch/arm/mach-vexpress/platsmp.c |4 +--- arch/arm/plat-versatile/headsmp.S |1 + 3 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index e83c654..17c878d 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c @@ -17,7 +17,6 @@ #include asm/hardware/gic.h #include asm/mach-types.h #include asm/smp_scu.h -#include asm/unified.h #include mach/board-eb.h #include mach/board-pb11mp.h @@ -75,6 +74,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) * until it receives a soft interrupt, and then the * secondary CPU branches to this address. */ - __raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)), + __raw_writel(virt_to_phys(versatile_secondary_startup), __io_address(REALVIEW_SYS_FLAGSSET)); } diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c index 2b5f7ac..124ffb1 100644 --- a/arch/arm/mach-vexpress/platsmp.c +++ b/arch/arm/mach-vexpress/platsmp.c @@ -13,8 +13,6 @@ #include linux/smp.h #include linux/io.h -#include asm/unified.h - #include mach/motherboard.h #define V2M_PA_CS7 0x1000 @@ -46,6 +44,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus) * secondary CPU branches to this address. */ writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR)); - writel(BSYM(virt_to_phys(versatile_secondary_startup)), + writel(virt_to_phys(versatile_secondary_startup), MMIO_P2V(V2M_SYS_FLAGSSET)); } diff --git a/arch/arm/plat-versatile/headsmp.S b/arch/arm/plat-versatile/headsmp.S index d397a1f..dd703ef 100644 --- a/arch/arm/plat-versatile/headsmp.S +++ b/arch/arm/plat-versatile/headsmp.S @@ -38,3 +38,4 @@ pen: ldr r7, [r6] .align 1: .long . .long pen_release +ENDPROC(versatile_secondary_startup) -- 1.6.3.3 ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v3 2/5] ARM: vexpress: Get rid of MMIO_P2V
This patch gets rid of the MMIO_P2V and __MMPIO_P2V macros,
defining constant virtual base for motherboard and tile
peripherals instead.
Additionally, in preparation for the new motherboard memory
map, the motherboard peripherals are using base pointers
calculated in runtime, instead of compile-time calculated
values.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/include/asm/hardware/arm_timer.h |5 ++
arch/arm/mach-vexpress/core.h | 11 +++-
arch/arm/mach-vexpress/ct-ca9x4.c | 52
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h| 13 ++---
arch/arm/mach-vexpress/include/mach/motherboard.h | 52
arch/arm/mach-vexpress/platsmp.c |5 +-
arch/arm/mach-vexpress/v2m.c | 68 ++---
7 files changed, 102 insertions(+), 104 deletions(-)
diff --git a/arch/arm/include/asm/hardware/arm_timer.h
b/arch/arm/include/asm/hardware/arm_timer.h
index c0f4e7b..d6030ff 100644
--- a/arch/arm/include/asm/hardware/arm_timer.h
+++ b/arch/arm/include/asm/hardware/arm_timer.h
@@ -9,7 +9,12 @@
*
* Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
* can have 16-bit or 32-bit selectable via a bit in the control register.
+ *
+ * Every SP804 contains two identical timers.
*/
+#define TIMER_1_BASE 0x00
+#define TIMER_2_BASE 0x20
+
#define TIMER_LOAD 0x00/* ACVR rw */
#define TIMER_VALUE0x04/* ACVR ro */
#define TIMER_CTRL 0x08/* ACVR rw */
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index f439715..d3dd491 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -1,6 +1,3 @@
-#define __MMIO_P2V(x) (((x) 0xf) | (((x) 0x0f00) 4) |
0xf800)
-#define MMIO_P2V(x)((void __iomem *)__MMIO_P2V(x))
-
#define AMBA_DEVICE(name,busid,base,plat) \
struct amba_device name##_device = { \
.dev= { \
@@ -17,3 +14,11 @@ struct amba_device name##_device = { \
.irq= IRQ_##base, \
/* .dma = DMA_##base,*/ \
}
+
+/* 2MB large area for motherboard's peripherals static mapping */
+#define V2M_PERIPH 0xf800
+#define V2M_PERIPH_P2V(offset) ((void __iomem *)(V2M_PERIPH | (offset)))
+
+/* Tile's peripherals static mappings should start here */
+#define V2T_PERIPH 0xf820
+#define V2T_PERIPH_P2V(offset) ((void __iomem *)(V2T_PERIPH | (offset)))
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c
b/arch/arm/mach-vexpress/ct-ca9x4.c
index 2b1e836..bfd3919 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -30,57 +30,26 @@
#include plat/clcd.h
-#define V2M_PA_CS7 0x1000
-
static struct map_desc ct_ca9x4_io_desc[] __initdata = {
{
- .virtual= __MMIO_P2V(CT_CA9X4_MPIC),
- .pfn= __phys_to_pfn(CT_CA9X4_MPIC),
- .length = SZ_16K,
- .type = MT_DEVICE,
- }, {
- .virtual= __MMIO_P2V(CT_CA9X4_SP804_TIMER),
- .pfn= __phys_to_pfn(CT_CA9X4_SP804_TIMER),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual= __MMIO_P2V(CT_CA9X4_L2CC),
- .pfn= __phys_to_pfn(CT_CA9X4_L2CC),
- .length = SZ_4K,
- .type = MT_DEVICE,
+ .virtual= V2T_PERIPH,
+ .pfn= __phys_to_pfn(CT_CA9X4_MPIC),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
},
};
static void __init ct_ca9x4_map_io(void)
{
-#ifdef CONFIG_LOCAL_TIMERS
- twd_base = MMIO_P2V(A9_MPCORE_TWD);
-#endif
iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
}
static void __init ct_ca9x4_init_irq(void)
{
- gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
-MMIO_P2V(A9_MPCORE_GIC_CPU));
-}
-
-#if 0
-static void __init ct_ca9x4_timer_init(void)
-{
- writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
- writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
-
- sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), ct-timer1);
- sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
- ct-timer0);
+ gic_init(0, 29, V2T_PERIPH_P2V(A9_MPCORE_GIC_DIST),
+V2T_PERIPH_P2V(A9_MPCORE_GIC_CPU));
}
-static struct sys_timer ct_ca9x4_timer = {
- .init = ct_ca9x4_timer_init,
-};
-#endif
-
static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
{
v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
@@ -193,6 +162,9 @@ static struct platform_device pmu_device = {
static void __init ct_ca9x4_init_early(void)
{
+#ifdef
[PATCH v3 3/5] ARM: vexpress: Add DT support in v2m
This patch provides hooks for DT-based tile machine implementations
and adds Device Tree description for the motherboard.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
Documentation/devicetree/bindings/arm/vexpress.txt | 108 +++
arch/arm/boot/dts/vexpress-v2m.dtsi| 195
arch/arm/mach-vexpress/Kconfig |6 +
arch/arm/mach-vexpress/core.h | 10 +
arch/arm/mach-vexpress/include/mach/motherboard.h |6 +
arch/arm/mach-vexpress/v2m.c | 125 +
6 files changed, 450 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/vexpress.txt
create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
diff --git a/Documentation/devicetree/bindings/arm/vexpress.txt
b/Documentation/devicetree/bindings/arm/vexpress.txt
new file mode 100644
index 000..1c57844
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/vexpress.txt
@@ -0,0 +1,108 @@
+ARM Versatile Express boards family
+---
+
+ARM's Versatile Express platform consists of a motherboard and one
+or more daughterboards (tiles). The motherboard provides a set of
+peripherals. Processor and RAM live on the tiles.
+
+The motherboard and each core tile should be described by a separate
+Device Tree source file, with the tile's description including
+the motherboard file using a /include/ directive. As the motherboard
+can be initialized in one of two different configurations (memory
+maps), care must be taken to include the correct one.
+
+Required properties in the root node:
+- compatible value:
+ compatible = arm,vexpress-model;
+ where model is the full tile model name (as used in the tiles's
+ Technical Reference Manual):
+ - for Coretile Express A5x2 (V2P-CA5s):
+ compatible = arm,vexpress-v2p-ca5s;
+ - Coretile Express A9x4 (V2P-CA9):
+ compatible = arm,vexpress-v2p-ca9;
+
+Optional properties in the root node:
+- tile model name (use the same names as in the tile's Technical
+ Reference Manuals, eg. V2P-CA5s)
+ model = model;
+- tile's HBI number (unique ARM's board model ID, visible on the
+ PCB's silkscreen) in hexadecimal transcription:
+ arm,hbi = 0xhbi
+ eg:
+ - for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
+ arm,hbi = 0x191;
+ - Coretile Express A9x4 (V2P-CA9) HBI-0225:
+ arm,hbi = 0x225;
+
+The motherboard description file provides a single motherboard node
+using 2 address cells corresponding to the Static Memory Bus used
+between the motherboard and the tile. The first cell defines the Chip
+Select (CS) line number, the second cell address offset within the CS.
+All interrupt lines between the motherboard and the tile are active
+high and are described using single cell.
+
+Optional properties of the motherboard node:
+- motherboard's memory map variant:
+ arm,v2m-memory-map = name;
+ where name is one of:
+ - rs1 - for RS1 map (i.a. peripherals on CS3); this map is also
+referred to as ARM Cortex-A Series memory map:
+ arm,v2m-memory-map = rs1;
+ When this property is missing, the motherboard is using the original
+ memory map (also known as the Legacy memory map, primarily used
+ with the original CoreTile Express A9x4) with peripherals on CS7.
+
+Motherboard .dtsi files provide a set of labelled peripherals that
+can be used to obtain required phandle in the tile's aliases node:
+- UARTs, note that the numbers correspond to the physical connectors
+ on the motherboard's back panel:
+ v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3
+- I2C controllers:
+ v2m_i2c_dvi and v2m_i2c_pcie
+- SP804 timers:
+ v2m_timer01 and v2m_timer23
+
+Current Linux implementation requires a arm,v2m_timer alias
+pointing at one of the motherboard's SP804 timers, if it is to be
+used as the system timer. This alias should be defined in the
+motherboard files.
+
+The tile description must define ranges, interrupt-map-mask and
+interrupt-map properties to translate the motherboard's address
+and interrupt space into one used by the tile's processor.
+
+Abbreviated example:
+
+/dts-v1/;
+
+/include/ skeleton.dtsi
+
+/ {
+ model = V2P-CA5s;
+ arm,hbi = 0x225;
+ compatible = arm,vexpress-v2p-ca5s;
+ interrupt-parent = gic;
+
+ aliases {
+ serial0 = v2m_serial0;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = arm,cortex-a9-gic;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x2c001000 0x1000,
+ 0x2c000100 0x100;
+ };
+
+ motherboard {
+ /* CS0 is visible at 0x0800 */
+ ranges = 0 0 0x0800 0x0400;
+ interrupt-map-mask = 0 0 63;
+ /* Active high IRQ 0 is connected to GIC's SPI0 */
+ interrupt-map
[PATCH v3 4/5] ARM: vexpress: Initial RS1 memory map support
This patch adds support for RS1 memory map based Versatile Express
motherboard.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 196 +
arch/arm/mach-vexpress/Kconfig|8 +
arch/arm/mach-vexpress/Makefile.boot |6 +
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 -
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 ++-
arch/arm/mach-vexpress/v2m.c | 64 +++-
6 files changed, 318 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
new file mode 100644
index 000..a75ebc3
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -0,0 +1,196 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * RS1 memory map (ARM Cortex-A Series memory map in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * original variant (vexpress-v2m.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m.dtsi!
+ */
+
+/ {
+ aliases {
+ arm,v2m_timer = v2m_timer01;
+ };
+
+ motherboard {
+ compatible = simple-bus;
+ arm,v2m-memory-map = rs1;
+ #address-cells = 2; /* SMB chipselect number and offset */
+ #size-cells = 1;
+ #interrupt-cells = 1;
+
+ flash@0, {
+ compatible = arm,vexpress-flash, cfi-flash;
+ reg = 0 0x 0x0400,
+ 4 0x 0x0400;
+ bank-width = 4;
+ };
+
+ psram@1, {
+ compatible = mtd-ram;
+ reg = 1 0x 0x0200;
+ bank-width = 4;
+ };
+
+ ethernet@2,0200 {
+ compatible = smsc,lan9118, smsc,lan9115;
+ reg = 2 0x0200 0x1;
+ interrupts = 15;
+ phy-mode = mii;
+ reg-io-width = 4;
+ smsc,irq-active-high;
+ smsc,irq-push-pull;
+ };
+
+ usb@2,0300 {
+ compatible = nxp,usb-isp1761;
+ reg = 2 0x0300 0x2;
+ interrupts = 16;
+ port1-otg;
+ };
+
+ iofpga@3, {
+ compatible = arm,amba-bus, simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 3 0 0x20;
+
+ sysreg@01 {
+ compatible = arm,vexpress-sysreg;
+ reg = 0x01 0x1000;
+ };
+
+ sysctl@02 {
+ compatible = arm,sp810, arm,primecell;
+ reg = 0x02 0x1000;
+ };
+
+ /* PCI-E I2C bus */
+ v2m_i2c_pcie: i2c@03 {
+ compatible = arm,versatile-i2c;
+ reg = 0x03 0x1000;
+
+ #address-cells = 1;
+ #size-cells = 0;
+
+ pcie-switch@60 {
+ compatible = idt,89hpes32h8;
+ reg = 0x60;
+ };
+ };
+
+ aaci@04 {
+ compatible = arm,pl041, arm,primecell;
+ reg = 0x04 0x1000;
+ interrupts = 11;
+ };
+
+ mmci@05 {
+ compatible = arm,pl180, arm,primecell;
+ reg = 0x05 0x1000;
+ interrupts = 9 10;
+ };
+
+ kmi@06 {
+ compatible = arm,pl050, arm,primecell;
+ reg = 0x06 0x1000;
+ interrupts = 12;
+ };
+
+ kmi@07 {
+ compatible = arm,pl050, arm,primecell;
+ reg = 0x07 0x1000;
+ interrupts = 13;
+ };
+
+ v2m_serial0: uart@09
[PATCH v3 5/5] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4
This patch adds Device Trees for ARM Ltd. CoreTile Express A5x2
and CoreTile Express A9x4 used with V2M motherboard and an initial
implementation of the DT machine support (this code is separate
from the current core tile code).
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 131
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 145 +++
arch/arm/mach-vexpress/Kconfig | 23 +
arch/arm/mach-vexpress/Makefile |1 +
arch/arm/mach-vexpress/v2p-ca5s_ca9.c | 115
5 files changed, 415 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
create mode 100644 arch/arm/mach-vexpress/v2p-ca5s_ca9.c
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
new file mode 100644
index 000..e63c251
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -0,0 +1,131 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A5x2
+ * Cortex-A5 MPCore (V2P-CA5s)
+ *
+ * HBI-0225B
+ */
+
+/dts-v1/;
+
+/include/ skeleton.dtsi
+
+/ {
+ model = V2P-CA5s;
+ arm,hbi = 0x225;
+ compatible = arm,vexpress-v2p-ca5s;
+ interrupt-parent = gic;
+
+ aliases {
+ serial0 = v2m_serial0;
+ serial1 = v2m_serial1;
+ serial2 = v2m_serial2;
+ serial3 = v2m_serial3;
+ i2c0 = v2m_i2c_dvi;
+ i2c1 = v2m_i2c_pcie;
+ };
+
+ memory@8000 {
+ device_type = memory;
+ reg = 0x8000 0x4000;
+ };
+
+ hdlcd@2a11 {
+ compatible = arm,hdlcd;
+ reg = 0x2a11 0x1000;
+ interrupts = 0 85 4;
+ };
+
+ memory-controller@2a15 {
+ compatible = arm,pl341, arm,primecell;
+ reg = 0x2a15 0x1000;
+ };
+
+ memory-controller@2a19 {
+ compatible = arm,pl354, arm,primecell;
+ reg = 0x2a19 0x1000;
+ interrupts = 0 86 4,
+0 87 4;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = arm,cortex-a9-gic;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x2c001000 0x1000,
+ 0x2c000100 0x100;
+ };
+
+ L2: cache-controller@2c0f {
+ compatible = arm,pl310-cache;
+ reg = 0x2c0f 0x1000;
+ interrupts = 0 84 4;
+ cache-level = 2;
+ arm,data-latency = 0;
+ arm,tag-latency = 0;
+ };
+
+ pmu {
+ compatible = arm,cortex-a9-pmu;
+ interrupts = 0 68 4,
+0 69 4;
+ };
+
+ motherboard {
+ ranges = 0 0 0x0800 0x0400,
+1 0 0x1400 0x0400,
+2 0 0x1800 0x0400,
+3 0 0x1c00 0x0400,
+4 0 0x0c00 0x0400,
+5 0 0x1000 0x0400;
+
+ interrupt-map-mask = 0 0 63;
+ interrupt-map = 0 0 0 gic 0 0 4,
+ 0 0 1 gic 0 1 4,
+ 0 0 2 gic 0 2 4,
+ 0 0 3 gic 0 3 4,
+ 0 0 4 gic 0 4 4,
+ 0 0 5 gic 0 5 4,
+ 0 0 6 gic 0 6 4,
+ 0 0 7 gic 0 7 4,
+ 0 0 8 gic 0 8 4,
+ 0 0 9 gic 0 9 4,
+ 0 0 10 gic 0 10 4,
+ 0 0 11 gic 0 11 4,
+ 0 0 12 gic 0 12 4,
+ 0 0 13 gic 0 13 4,
+ 0 0 14 gic 0 14 4,
+ 0 0 15 gic 0 15 4,
+ 0 0 16 gic 0 16 4,
+ 0 0 17 gic 0 17 4,
+ 0 0 18 gic 0 18 4,
+ 0 0 19 gic 0 19 4,
+ 0 0 20 gic 0 20 4,
+ 0 0 21 gic 0 21 4,
+ 0 0 22 gic 0 22 4,
+ 0 0 23 gic 0 23 4,
+ 0 0 24 gic 0 24 4,
+ 0 0 25 gic 0 25 4,
+ 0 0 26 gic 0 26 4,
+ 0 0 27 gic 0 27 4,
+ 0 0 28 gic 0 28 4,
+ 0 0 29 gic 0 29 4,
+ 0 0 30 gic 0 30 4,
+ 0 0 31 gic
Re: [PATCH v3 0/5] Versatile Express DT support
On Tue, 2011-11-29 at 17:00 +, Dave Martin wrote: I'm trying to build... what tree are you basing on? v3.2-rc3: $ git log --oneline HEAD...v3.2-rc3~ 3b9df1e ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4 5a1c565 ARM: vexpress: Initial RS1 memory map support 9355e8a ARM: vexpress: Add DT support in v2m 0529bd6 ARM: vexpress: Get rid of MMIO_P2V 68118cc ARM: versatile: Add missing ENDPROC to headsmp.S caca6a0 Linux 3.2-rc3 With v3.2-rc3 or next, I get OF header failures like the following: arch/arm/kernel/devtree.c: In function ‘arm_dt_memblock_reserve’: arch/arm/kernel/devtree.c:41:7: error: ‘initial_boot_params’ undeclared (first use in this function) arch/arm/kernel/devtree.c:41:7: note: each undeclared identifier is reported only once for each function it appears in [...] Can you send me your config, please? Also, I forgot to mention that you need Rob's of/irq: of_irq_init: add check for parent equal to child node (http://article.gmane.org/gmane.linux.kernel/1221051) to get this working. Cheers! Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v2 2/4] ARM: vexpress: Add DT support in v2m
On Fri, 2011-11-25 at 16:18 +, Dave Martin wrote:
[Since this text is now stable enough to be proofread, I'll list minor
pedantic nits along with the other comments -- they aren't vital to the
meaning though, and the documentation still works if they aren't
acted on.]
[snip]
Most appreciated! I'll process all your suggestions, thanks!
@@ -50,10 +55,34 @@ static void __iomem *v2m_sysreg_base;
static void __init v2m_timer_init(void)
{
- void __iomem *sysctl_base;
- void __iomem *timer01_base;
+ void __iomem *sysctl_base = NULL;
+ void __iomem *timer01_base = NULL;
+ unsigned int timer01_irq = NO_IRQ;
+
+ if (of_have_populated_dt()) {
+#if defined(CONFIG_ARCH_VEXPRESS_DT)
+ int err;
+ const char *path;
+ struct device_node *node;
+
+ node = of_find_compatible_node(NULL, NULL, arm,sp810);
+ if (node)
+ sysctl_base = of_iomap(node, 0);
+
+ err = of_property_read_string(of_aliases, timer, path);
+ if (!err)
+ node = of_find_node_by_path(path);
+ if (node) {
+ timer01_base = of_iomap(node, 0);
+ timer01_irq = irq_of_parse_and_map(node, 0);
+ }
+#endif
+ } else {
+ sysctl_base = ioremap(V2M_SYSCTL, SZ_4K);
+ timer01_base = ioremap(V2M_TIMER01, SZ_4K);
+ timer01_irq = IRQ_V2M_TIMER0;
+ }
Do we even have of_have_populated_dt() in a non-DT kernel?
Maybe change this to
#if defined(CONFIG_ARCH_VEXPRESS_DT)
if (of_have_populated_dt()) {
/* ... */
} else
#endif
/* follow on from previous else */
{
/* ... */
}
...or if that feels a little unclear, maybe do this:
#if defined(CONFIG_ARCH_VEXPRESS_DT)
if (of_have_populated_dt()) {
/* ... */
} else {
#else
{
#endif
/* ... */
}
of_have_populated_dt() is safe, see include/linux/of.h:
#ifdef CONFIG_OF
static inline bool of_have_populated_dt(void)
{
return allnodes != NULL;
}
#else /* CONFIG_OF */
static inline bool of_have_populated_dt(void)
{
return false;
}
#endif /* CONFIG_OF */
@@ -63,20 +92,20 @@ static void __init v2m_timer_init(void)
writel(scctrl, sysctl_base + SCCTRL);
}
- timer01_base = ioremap(V2M_TIMER01, SZ_4K);
- WARN_ON(!timer01_base);
- if (timer01_base) {
+ WARN_ON(!timer01_base || timer01_irq != NO_IRQ);
Is that supposed to be !timer01_base || timer01_irq == NO_IRQ ?
Yes, I spotted and fixed this in the mean time.
If so, is might be better to write
WARN_ON(!(expr));
if (expr) {
...
so that the conditions are clear inverses.
Good point, will do.
@@ -470,3 +499,99 @@ MACHINE_START(VEXPRESS, ARM-Versatile Express)
.timer = v2m_timer,
.init_machine = v2m_init,
MACHINE_END
It would be useful to have a comment somewhere indicating that the
DT_MACHINE_START() entries live in the corresponding ct-*.c files for
DT-enabled coretiles.
Not essential, though ... most people do know how to use grep.
Where exactly would you see that comment?
Thanks for the review!
Paweł
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Re: [PATCH] of/irq: of_irq_init: add check for parent equal to child node
On Sun, 2011-11-27 at 20:49 -0600, Rob Herring wrote: From: Rob Herring rob.herr...@calxeda.com With the revert of of/irq: of_irq_find_parent: check for parent equal to child (dc9372808412edb), we need another way to handle parent node equal to the child node. This can simply be handled in of_irq_init by checking for this condition. Signed-off-by: Rob Herring rob.herr...@calxeda.com Works for me, thanks! Tested-by: Pawel Moll pawel.m...@arm.com Cheers! Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v2 0/4] Versatile Express DT support
On Mon, 2011-11-28 at 14:57 +, Dave Martin wrote: Oh, btw, git am reports a few whitespace errors on the last full post of the series (v2). Can you shove the series through checkpatch.pl and/or git am and fix any minor issues, now that the series is relatively stable? I did, actually: 8 $ scripts/checkpatch.pl 0001-ARM-vexpress-Get-rid-of-MMIO_P2V.patch total: 0 errors, 0 warnings, 363 lines checked 0001-ARM-vexpress-Get-rid-of-MMIO_P2V.patch has no obvious style problems and is ready for submission. $ scripts/checkpatch.pl 0002-ARM-vexpress-Add-DT-support-in-v2m.patch total: 0 errors, 0 warnings, 505 lines checked 0002-ARM-vexpress-Add-DT-support-in-v2m.patch has no obvious style problems and is ready for submission. $ scripts/checkpatch.pl 0003-ARM-vexpress-Initial-RS1-memory-map-support.patch WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt #308: FILE: arch/arm/mach-vexpress/include/mach/uncompress.h:25: +#define AMBA_PERIPH_ID0(base) (*(volatile unsigned char *)((base) + 0xfe0)) total: 0 errors, 1 warnings, 368 lines checked 0003-ARM-vexpress-Initial-RS1-memory-map-support.patch has style problems, please review. If any of these errors are false positives, please report them to the maintainer, see CHECKPATCH in MAINTAINERS. $ scripts/checkpatch.pl 0004-ARM-vexpress-DT-based-support-for-CoreTiles-Express-.patch total: 0 errors, 0 warnings, 424 lines checked 0004-ARM-vexpress-DT-based-support-for-CoreTiles-Express-.patch has no obvious style problems and is ready for submission. 8 In the past I noticed that same - sometimes git am is complaining when chechpatch is clean. I never was determined to figure out why, though... Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v2 0/4] Versatile Express DT support
On Mon, 2011-11-28 at 14:25 +, Rob Herring wrote: Other than Dave's comments, looks good. For the series: Acked-by: Rob Herring rob.herr...@calxeda.com Thanks! There are a number of compatible strings for various peripherals defined without documentation, but you're not really using them so I think it's fine for now. BTW, I believe Dave said he was going to document some of the primecell peripherals. :) Yep, we agreed with Dave that the ones I'll take care of soon are MMCI (PL180) and the VE sysregs, the rest is his :-) On that subject - some time ago I sent a patch adding sil vendor string, as this one the only non-documented one I used: http://article.gmane.org/gmane.linux.drivers.devicetree/9362/ Cheers! Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v2 0/4] Versatile Express DT support
On Mon, 2011-11-28 at 15:39 +, Rob Herring wrote: Okay. I'll apply. But that's just a vendor. There's still binding docs needed for the actual sil9022 device and some others. I think the sil one is the only undocumented device we use now, except for the primecells that Dave and I will take care of? I will also cover the sii9022, if only I get clearance from our legals (the datasheet we got is under NDA) to write a driver for it (the device is quite complex, so I wouldn't like to define bindings without testing them first). Cheers! Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH v2 4/4] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4
On Mon, 2011-11-28 at 16:29 +, Dave Martin wrote: +config ARCH_VEXPRESS_V2P_CA5S_CA9 + bool CoreTile Express A5x2 and A9x4 based platform support + select ARCH_VEXPRESS_RS1 + select ARCH_VEXPRESS_DT Shouldn't we depend on CPU_V7, ARM_GIC and CACHE_PL310 here? I get a lot of moaning from Kconfig about unmet dependencies. I think the coretiles do have a CPU etc. on them... CPU_V7 and ARM_GIC - definitely, thanks for spotting that. CACHE_PL310 - I don't think so, as it's just a special case of CACHE_L2X0, which is optional. The tile works fine with the L2 cache disabled. + select ARM_ERRATA_720789 + select ARM_ERRATA_751472 The workarounds for these errata both erroneously depend on CONFIG_SMP; however, I don't think that's a bug in these patches -- selecting those options here feels correct. Yes, I've just mirrored what the ARCH_VEXPRESS_CA9X4 selects. + select ARM_ERRATA_753970 Will has a patch, now in Russell's fixes branch, which renames this to PL310_ERRATA_753970 for compatibility with other people's patches. This erratum workaround depends on CACHE_PL310, but since the PL310 is a property of the CoreTile which must be configured in, that dependency seems reasonable. As the PL310 is optional I think I'll just do: select PL310_ERRATA_753970 if CACHE_PL310 Cheers! Pawel ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
of_irq_init() stopped working in 3.2-rc3
Hi Rob,
Because your dc9372808412edbc653a675a526c2ee6c0c14a91 of/irq:
of_irq_find_parent: check for parent equal to child got reverted in
3.2-rc3, the of_irq_init() doesn't work, as...
8--
void __init of_irq_init(const struct of_device_id *matches)
{
struct device_node *np, *parent = NULL;
[...]
desc-interrupt_parent = of_irq_find_parent(np);
[...]
/*
* Process all controllers with the current 'parent'.
* First pass will be looking for NULL as the parent.
* The assumption is that NULL parent means a root controller.
*/
list_for_each_entry_safe(desc, temp_desc, intc_desc_list,
list) {
[...]
if (desc-interrupt_parent != parent)
continue;
8
... the desc-interrupt_parent is not NULL for the root interrupt controller
any more...
I've temporarily worked the problem around by re-applying the
of_irq_find_parent() change.
Cheers!
Paweł
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[PATCH v2 0/4] Versatile Express DT support
Hello again, This version of the series (hopefully) addresses all the suggestions made by Dave, Rob and Russell. The compatible values are specific for the tiles now and the memory map variant is defined as a custom property in the motherboard node. Tested on V2P-CA9 coretile both with ATAGs and DT and V2P-CA5s with DT. All comments, as always, welcomed! Pawel Pawel Moll (4): ARM: vexpress: Get rid of MMIO_P2V ARM: vexpress: Add DT support in v2m ARM: vexpress: Initial RS1 memory map support ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4 Documentation/devicetree/bindings/arm/vexpress| 101 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 192 +++ arch/arm/boot/dts/vexpress-v2m.dtsi | 191 +++ arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 132 ++ arch/arm/boot/dts/vexpress-v2p-ca9.dts| 146 +++ arch/arm/include/asm/hardware/arm_timer.h |5 + arch/arm/mach-vexpress/Kconfig| 35 +++ arch/arm/mach-vexpress/Makefile |1 + arch/arm/mach-vexpress/Makefile.boot |6 + arch/arm/mach-vexpress/core.h | 21 ++- arch/arm/mach-vexpress/ct-ca9x4.c | 52 +--- arch/arm/mach-vexpress/include/mach/ct-ca9x4.h| 13 +- arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 +++- arch/arm/mach-vexpress/include/mach/motherboard.h | 58 +++-- arch/arm/mach-vexpress/include/mach/uncompress.h | 13 +- arch/arm/mach-vexpress/platsmp.c |4 +- arch/arm/mach-vexpress/v2m.c | 265 ++--- arch/arm/mach-vexpress/v2p-ca5s_ca9.c | 115 + 18 files changed, 1272 insertions(+), 115 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/vexpress create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts create mode 100644 arch/arm/mach-vexpress/v2p-ca5s_ca9.c ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
[PATCH v2 1/4] ARM: vexpress: Get rid of MMIO_P2V
This patch gets rid of the MMIO_P2V and __MMPIO_P2V macros,
defining constant virtual base for motherboard and tile
peripherals instead.
Additionally, in preparation for the new motherboard memory
map, the motherboard peripherals are using base pointers
calculated in runtime, instead of compile-time calculated
values.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/include/asm/hardware/arm_timer.h |5 ++
arch/arm/mach-vexpress/core.h | 11 ++-
arch/arm/mach-vexpress/ct-ca9x4.c | 52 +++---
arch/arm/mach-vexpress/include/mach/ct-ca9x4.h| 13 ++--
arch/arm/mach-vexpress/include/mach/motherboard.h | 52 +++---
arch/arm/mach-vexpress/platsmp.c |4 +-
arch/arm/mach-vexpress/v2m.c | 76 +
7 files changed, 104 insertions(+), 109 deletions(-)
diff --git a/arch/arm/include/asm/hardware/arm_timer.h
b/arch/arm/include/asm/hardware/arm_timer.h
index c0f4e7b..d6030ff 100644
--- a/arch/arm/include/asm/hardware/arm_timer.h
+++ b/arch/arm/include/asm/hardware/arm_timer.h
@@ -9,7 +9,12 @@
*
* Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
* can have 16-bit or 32-bit selectable via a bit in the control register.
+ *
+ * Every SP804 contains two identical timers.
*/
+#define TIMER_1_BASE 0x00
+#define TIMER_2_BASE 0x20
+
#define TIMER_LOAD 0x00/* ACVR rw */
#define TIMER_VALUE0x04/* ACVR ro */
#define TIMER_CTRL 0x08/* ACVR rw */
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index f439715..d3dd491 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -1,6 +1,3 @@
-#define __MMIO_P2V(x) (((x) 0xf) | (((x) 0x0f00) 4) |
0xf800)
-#define MMIO_P2V(x)((void __iomem *)__MMIO_P2V(x))
-
#define AMBA_DEVICE(name,busid,base,plat) \
struct amba_device name##_device = { \
.dev= { \
@@ -17,3 +14,11 @@ struct amba_device name##_device = { \
.irq= IRQ_##base, \
/* .dma = DMA_##base,*/ \
}
+
+/* 2MB large area for motherboard's peripherals static mapping */
+#define V2M_PERIPH 0xf800
+#define V2M_PERIPH_P2V(offset) ((void __iomem *)(V2M_PERIPH | (offset)))
+
+/* Tile's peripherals static mappings should start here */
+#define V2T_PERIPH 0xf820
+#define V2T_PERIPH_P2V(offset) ((void __iomem *)(V2T_PERIPH | (offset)))
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c
b/arch/arm/mach-vexpress/ct-ca9x4.c
index 2b1e836..bfd3919 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -30,57 +30,26 @@
#include plat/clcd.h
-#define V2M_PA_CS7 0x1000
-
static struct map_desc ct_ca9x4_io_desc[] __initdata = {
{
- .virtual= __MMIO_P2V(CT_CA9X4_MPIC),
- .pfn= __phys_to_pfn(CT_CA9X4_MPIC),
- .length = SZ_16K,
- .type = MT_DEVICE,
- }, {
- .virtual= __MMIO_P2V(CT_CA9X4_SP804_TIMER),
- .pfn= __phys_to_pfn(CT_CA9X4_SP804_TIMER),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual= __MMIO_P2V(CT_CA9X4_L2CC),
- .pfn= __phys_to_pfn(CT_CA9X4_L2CC),
- .length = SZ_4K,
- .type = MT_DEVICE,
+ .virtual= V2T_PERIPH,
+ .pfn= __phys_to_pfn(CT_CA9X4_MPIC),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
},
};
static void __init ct_ca9x4_map_io(void)
{
-#ifdef CONFIG_LOCAL_TIMERS
- twd_base = MMIO_P2V(A9_MPCORE_TWD);
-#endif
iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
}
static void __init ct_ca9x4_init_irq(void)
{
- gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
-MMIO_P2V(A9_MPCORE_GIC_CPU));
-}
-
-#if 0
-static void __init ct_ca9x4_timer_init(void)
-{
- writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
- writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
-
- sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), ct-timer1);
- sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
- ct-timer0);
+ gic_init(0, 29, V2T_PERIPH_P2V(A9_MPCORE_GIC_DIST),
+V2T_PERIPH_P2V(A9_MPCORE_GIC_CPU));
}
-static struct sys_timer ct_ca9x4_timer = {
- .init = ct_ca9x4_timer_init,
-};
-#endif
-
static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
{
v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
@@ -193,6 +162,9 @@ static struct platform_device pmu_device = {
static void __init ct_ca9x4_init_early(void)
{
+#ifdef
[PATCH v2 3/4] ARM: vexpress: Initial RS1 memory map support
This patch adds support for RS1 memory map based Versatile Express
motherboard.
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/boot/dts/vexpress-v2m-rs1.dtsi | 192 +
arch/arm/mach-vexpress/Kconfig|8 +
arch/arm/mach-vexpress/Makefile.boot |6 +
arch/arm/mach-vexpress/include/mach/debug-macro.S | 37 -
arch/arm/mach-vexpress/include/mach/uncompress.h | 13 ++-
arch/arm/mach-vexpress/v2m.c | 64 +++-
6 files changed, 314 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
new file mode 100644
index 000..c8af670
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -0,0 +1,192 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * RS1 memory map (ARM Cortex-A Series memory map in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * original variant (vexpress-v2m.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m.dtsi!
+ */
+
+/ {
+ motherboard {
+ compatible = simple-bus;
+ arm,v2m-memory-map = rs1;
+ #address-cells = 2; /* SMB chipselect number and offset */
+ #size-cells = 1;
+ #interrupt-cells = 1;
+
+ flash@0, {
+ compatible = arm,vexpress-flash, cfi-flash;
+ reg = 0 0x 0x0400,
+ 4 0x 0x0400;
+ bank-width = 4;
+ };
+
+ psram@1, {
+ compatible = mtd-ram;
+ reg = 1 0x 0x0200;
+ bank-width = 4;
+ };
+
+ ethernet@2,0200 {
+ compatible = smsc,lan9118, smsc,lan9115;
+ reg = 2 0x0200 0x1;
+ interrupts = 15;
+ phy-mode = mii;
+ reg-io-width = 4;
+ smsc,irq-active-high;
+ smsc,irq-push-pull;
+ };
+
+ usb@2,0300 {
+ compatible = nxp,usb-isp1761;
+ reg = 2 0x0300 0x2;
+ interrupts = 16;
+ port1-otg;
+ };
+
+ iofpga@3, {
+ compatible = arm,amba-bus, simple-bus;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges = 0 3 0 0x20;
+
+ sysreg@01 {
+ compatible = arm,vexpress-sysreg;
+ reg = 0x01 0x1000;
+ };
+
+ sysctl@02 {
+ compatible = arm,sp810, arm,primecell;
+ reg = 0x02 0x1000;
+ };
+
+ /* PCI-E I2C bus */
+ mb_i2c_pcie: i2c@03 {
+ compatible = arm,versatile-i2c;
+ reg = 0x03 0x1000;
+
+ #address-cells = 1;
+ #size-cells = 0;
+
+ pcie-switch@60 {
+ compatible = idt,89hpes32h8;
+ reg = 0x60;
+ };
+ };
+
+ aaci@04 {
+ compatible = arm,pl041, arm,primecell;
+ reg = 0x04 0x1000;
+ interrupts = 11;
+ };
+
+ mmci@05 {
+ compatible = arm,pl180, arm,primecell;
+ reg = 0x05 0x1000;
+ interrupts = 9 10;
+ };
+
+ kmi@06 {
+ compatible = arm,pl050, arm,primecell;
+ reg = 0x06 0x1000;
+ interrupts = 12;
+ };
+
+ kmi@07 {
+ compatible = arm,pl050, arm,primecell;
+ reg = 0x07 0x1000;
+ interrupts = 13;
+ };
+
+ mb_serial0: uart@09 {
+ compatible = arm,pl011, arm,primecell
[PATCH v2 4/4] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4
This patch adds Device Trees for ARM Ltd. CoreTile Express A5x2
and CoreTile Express A9x4 used with V2M motherboard and an initial
implementation of the DT machine support (this code is separate
from the current core tile code).
Signed-off-by: Pawel Moll pawel.m...@arm.com
---
arch/arm/boot/dts/vexpress-v2p-ca5s.dts | 132
arch/arm/boot/dts/vexpress-v2p-ca9.dts | 146 +++
arch/arm/mach-vexpress/Kconfig | 21 +
arch/arm/mach-vexpress/Makefile |1 +
arch/arm/mach-vexpress/v2p-ca5s_ca9.c | 115
5 files changed, 415 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
create mode 100644 arch/arm/mach-vexpress/v2p-ca5s_ca9.c
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
new file mode 100644
index 000..84e05cd
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -0,0 +1,132 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A5x2
+ * Cortex-A5 MPCore (V2P-CA5s)
+ *
+ * HBI-0225B
+ */
+
+/dts-v1/;
+
+/include/ skeleton.dtsi
+
+/ {
+ model = V2P-CA5s;
+ arm,hbi = 0x225;
+ compatible = arm,vexpress-v2p-ca5s;
+ interrupt-parent = gic;
+
+ aliases {
+ serial0 = mb_serial0;
+ serial1 = mb_serial1;
+ serial2 = mb_serial2;
+ serial3 = mb_serial3;
+ i2c0 = mb_i2c_dvi;
+ i2c1 = mb_i2c_pcie;
+ timer = mb_timer01;
+ };
+
+ memory@8000 {
+ device_type = memory;
+ reg = 0x8000 0x4000;
+ };
+
+ hdlcd@2a11 {
+ compatible = arm,hdlcd;
+ reg = 0x2a11 0x1000;
+ interrupts = 0 85 4;
+ };
+
+ memory-controller@2a15 {
+ compatible = arm,pl341, arm,primecell;
+ reg = 0x2a15 0x1000;
+ };
+
+ memory-controller@2a19 {
+ compatible = arm,pl354, arm,primecell;
+ reg = 0x2a19 0x1000;
+ interrupts = 0 86 4,
+0 87 4;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = arm,cortex-a9-gic;
+ #interrupt-cells = 3;
+ #address-cells = 0;
+ interrupt-controller;
+ reg = 0x2c001000 0x1000,
+ 0x2c000100 0x100;
+ };
+
+ L2: cache-controller@2c0f {
+ compatible = arm,pl310-cache;
+ reg = 0x2c0f 0x1000;
+ interrupts = 0 84 4;
+ cache-level = 2;
+ arm,data-latency = 0;
+ arm,tag-latency = 0;
+ };
+
+ pmu {
+ compatible = arm,cortex-a9-pmu;
+ interrupts = 0 68 4,
+0 69 4;
+ };
+
+ motherboard {
+ ranges = 0 0 0x0800 0x0400,
+1 0 0x1400 0x0400,
+2 0 0x1800 0x0400,
+3 0 0x1c00 0x0400,
+4 0 0x0c00 0x0400,
+5 0 0x1000 0x0400;
+
+ interrupt-map-mask = 0 0 63;
+ interrupt-map = 0 0 0 gic 0 0 4,
+ 0 0 1 gic 0 1 4,
+ 0 0 2 gic 0 2 4,
+ 0 0 3 gic 0 3 4,
+ 0 0 4 gic 0 4 4,
+ 0 0 5 gic 0 5 4,
+ 0 0 6 gic 0 6 4,
+ 0 0 7 gic 0 7 4,
+ 0 0 8 gic 0 8 4,
+ 0 0 9 gic 0 9 4,
+ 0 0 10 gic 0 10 4,
+ 0 0 11 gic 0 11 4,
+ 0 0 12 gic 0 12 4,
+ 0 0 13 gic 0 13 4,
+ 0 0 14 gic 0 14 4,
+ 0 0 15 gic 0 15 4,
+ 0 0 16 gic 0 16 4,
+ 0 0 17 gic 0 17 4,
+ 0 0 18 gic 0 18 4,
+ 0 0 19 gic 0 19 4,
+ 0 0 20 gic 0 20 4,
+ 0 0 21 gic 0 21 4,
+ 0 0 22 gic 0 22 4,
+ 0 0 23 gic 0 23 4,
+ 0 0 24 gic 0 24 4,
+ 0 0 25 gic 0 25 4,
+ 0 0 26 gic 0 26 4,
+ 0 0 27 gic 0 27 4,
+ 0 0 28 gic 0 28 4,
+ 0 0 29 gic 0 29 4,
+ 0 0 30 gic 0 30 4
Re: [PATCH v2 2/4] ARM: vexpress: Add DT support in v2m
On Wed, 2011-11-23 at 15:01 +, Pawel Moll wrote:
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index ee52b35..fd7ee1f 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
[...]
+ node = of_find_compatible_node(NULL, NULL, arm,sp810);
+ if (node)
+ sysctl_base = of_iomap(node, 0);
+
+ err = of_property_read_string(of_aliases, timer, path);
+ if (!err)
+ node = of_find_node_by_path(path);
+ if (node) {
+ timer01_base = of_iomap(node, 0);
+ timer01_irq = irq_of_parse_and_map(node, 0);
+ }
I've just realized that this fragment should actually look like that:
node = of_find_compatible_node(NULL, NULL, arm,sp810);
sysctl_base = of_iomap(node, 0);
err = of_property_read_string(of_aliases, timer, path);
if (!err) {
node = of_find_node_by_path(path);
timer01_base = of_iomap(node, 0);
timer01_irq = irq_of_parse_and_map(node, 0);
}
I will change that.
Cheers!
Pawel
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Re: [PATCH 2/5] ARM: vexpress: Remove platform SMP functions from ct_desc
On Thu, 2011-11-17 at 15:31 +, Russell King - ARM Linux wrote:
On Fri, Nov 11, 2011 at 06:27:03PM +, Pawel Moll wrote:
This patch removes platform SMP callbacks from ct_desc struct
and replaces them with global symbols in preparation for
DT-based support code.
Will and myself discussed how to do this, and we came up with the
ct_desc solution. Now you're doing something different. It seems to
me like there's a disconnect between various different parts of ARM Ltd
between people who have different ideas about how problems are to be
solved.
There are gaps (about 50-100m) between the buildings here indeed. And
you have to cross a road... Thankfully we have some network cables
underneath it.
So, what's the technical reason for this change?
I was remember when Will was adding the tile-detection code. That seemed
the best solution at the time (and spared us getting new mach type
number for every new tile), with no DT at the horizon. Situation changed
since and the tiles are just separate DT-only machine descriptions, as
your original implementation. There will be no more users of the
ct_desc.
I can't see how this improves anything.
It's not a improvement, just a workaround because that:
void __init smp_init_cpus(void)
{
- ct_desc-init_cpu_map();
}
implies existence of the ct_desc. But fair enough, I'll simply create
fake ones for the DT cases so this code won't have to be changed. As
soon as the platform SMP calls are abstracted, which as I understand is
one of steps on the mythical single binary kernel way, the problem
will disappear.
In fact, this patch reintroduces
a bug which have been previously fixed:
+static void ct_ca9x4_init_cpu_map(void)
+{
+ int i, ncores;
+ ncores = scu_get_core_count(V2T_PERIPH_P2V(A9_MPCORE_SCU));
+
+ for (i = 0; i ncores; ++i)
+ set_cpu_possible(i, true);
+
+ set_smp_cross_call(gic_raise_softirq);
+}
vs
-static void ct_ca9x4_init_cpu_map(void)
-{
- int i, ncores = scu_get_core_count(V2TILE_PERIPH_P2V(A9_MPCORE_SCU));
-
- if (ncores nr_cpu_ids) {
- pr_warn(SMP: %u cores greater than maximum (%u), clipping\n,
- ncores, nr_cpu_ids);
- ncores = nr_cpu_ids;
- }
-
- for (i = 0; i ncores; ++i)
- set_cpu_possible(i, true);
-
- set_smp_cross_call(gic_raise_softirq);
-}
When you rebase, please pay better attention to the conflicts.
Thanks for spotting that, fixed.
All comments appreciated as always, thanks!
Pawel
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Re: [PATCH 1/5] ARM: vexpress: Get rid of MMIO_P2V
On Thu, 2011-11-17 at 15:43 +, Russell King - ARM Linux wrote:
+/* Tile's peripherals static mappings should start here */
+#define V2T_PERIPH 0xf820
+#define V2T_PERIPH_P2V(offset) ((void __iomem *)(V2T_PERIPH | (offset)))
+
Please get rid of these blank lines at the end of files.
Patch splitting leftover. Will fix.
+static void __iomem *v2m_sysreg_base;
+
+
+
More useless blank lines.
Ok, will change that. I just like the way that the data are visually
separated from the code like here:
ceade897 (Russell King 2010-02-11 21:44:53 + 68) .init =
v2m_timer_init,
ceade897 (Russell King 2010-02-11 21:44:53 + 69) };
ceade897 (Russell King 2010-02-11 21:44:53 + 70)
ceade897 (Russell King 2010-02-11 21:44:53 + 71)
ceade897 (Russell King 2010-02-11 21:44:53 + 72) static
DEFINE_SPINLOCK(v2m_cfg_lock);
or here:
ceade897 (Russell King 2010-02-11 21:44:53 + 289) rtc_device,
ceade897 (Russell King 2010-02-11 21:44:53 + 290) };
ceade897 (Russell King 2010-02-11 21:44:53 + 291)
ceade897 (Russell King 2010-02-11 21:44:53 + 292)
ceade897 (Russell King 2010-02-11 21:44:53 + 293) static long
v2m_osc_round(struct clk *clk, unsigned long rate)
static void __init v2m_timer_init(void)
{
+ void *sysctl_base;
+ void *timer01_base;
Do you not use sparse? __iomem.
Ok.
+ unsigned int timer01_irq;
u32 scctrl;
+ sysctl_base = ioremap(V2M_SYSCTL, SZ_4K);
+ BUG_ON(!sysctl_base);
+ timer01_base = ioremap(V2M_TIMER01, SZ_4K);
+ BUG_ON(!timer01_base);
+ timer01_irq = IRQ_V2M_TIMER0;
What's going on with the indentation here?
Patch-splitting artefact again, will fix.
@@ -413,6 +431,10 @@ static void __init v2m_populate_ct_desc(void)
static void __init v2m_map_io(void)
{
iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
+
+ /* Will become an ioremap() when possible */
+ v2m_sysreg_base = V2M_PERIPH_P2V(V2M_SYSREGS);
It won't if it stays here.
Excuse my inferior English language capabilities, but what do you
suggest here?
All comments appreciated as always, thanks!
Pawel
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Re: [PATCH 3/5] ARM: vexpress: Add DT support in v2m
On Thu, 2011-11-17 at 15:53 +, Russell King - ARM Linux wrote: You're totally failing to understand the point. That's your opinion, I think otherwise, won't try to convince you. The point is that when Versatile Express first came out, it had a memory map. At this point in time, there was nothing 'legacy' about it, it was the latest and greatest thing. That's right. And then when the new variant was created *hardware designers* decided to call the previous one legacy. I couldn't care less what word was it, could be even bublebee from my point of view. Again, this is _not_ how DT is supposed to work. DT is about describing the hardware, not describing the state of something. And that's exactly what I was trying to do. Describe the hardware, using terminology *used by the hardware designers* - fact that you have chosen to ignore, fair enough. So, get rid of that 'legacy' crap in DT naming. It doesn't belong. Or we'll start talling the Cortex-A5 stuff 'legacy' right now as well. As the compatible values will be limited to the tile name and the information about the motherboard mode will be passed through private node property, I will follow Dave's suggestion of using empty value for legacy/original/whatever variant. Hopefully this will end this topic which is already too long. Thanks for all comments! Pawel ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH 4/5] ARM: vexpress: Initial RS1 memory map support
On Thu, 2011-11-17 at 15:36 +, Russell King - ARM Linux wrote: +config ARCH_VEXPRESS_LEGACY + bool + select AUTO_ZRELADDR + select ARM_PATCH_PHYS_VIRT + +config ARCH_VEXPRESS_RS1 + bool + This doesn't make sense. Why should CA9x4 be forced to use the P2V stuff and the AUTO_ZRELADDR stuff? Hint: it works fine today without. @@ -1,3 +1,3 @@ - zreladdr-y += 0x60008000 -params_phys-y := 0x6100 -initrd_phys-y := 0x6080 + zreladdr-y += 0x80008000 +params_phys-y := 0x8100 +initrd_phys-y := 0x8080 So is this the reason - you don't want to turn this into a config, so you want to force all the automatic zreladdr stuff on? Yes, exactly. You do know that this will probably cause uboot to load the uImage at 0x80008000 instead of 0x60008000, and therefore we'll lose half the RAM on this board? I missed that - I don't use uboot, so I don't build uImages. As the ARCH_VEXPRESS_LEGACY will be no more (see my other response) I'll revert the order, so the _RS1 will enforce P2V, AUTO_ZRELADDR and change the zrealaddr-y friends (as in: 0x6* when no _RS1, 0x8* when _RS1=y). Is there any other way of having single binary kernel booting from both 0x60008000 and 0x80008000? All comments appreciated as always, thanks! Pawel ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH 3/5] ARM: vexpress: Add DT support in v2m
On Wed, 2011-11-16 at 17:57 +, Dave Martin wrote: We should specify a list of all the standard aliases used by the generic motherboard code here, since these are part of the contract between each board-specific device tree and the motherboard code. Is timer the only one, or are there others? One and only. There were more, but I got rid of them. Are the other alises still used? If not, we should perhaps get rid of them, or keep them on an as-needed basis only? I've included the serialX and i2cX aliases purely because the other boards do (including Grant's versatile dts). Since alises are by definition a point of standardisation (otherwise there's no need for an alias) I think they need to be documented alongside bindings wherever we have them. You are right, but I think this is out of the vexpress scope. The serialX aliases, for example, are already used by some drivers: 4 1788 drivers/tty/serial/atmel_serial.c atmel_serial_probe ret = of_alias_get_id(np, serial); 5 1301 drivers/tty/serial/imx.c serial_imx_probe_dt ret = of_alias_get_id(np, serial); so it sounds like a generic policy-to-be-made. For non-interactive config items, can we still please have comments indicating what the item means and how it should be used? Such comments can be very brief, but having at least something makes the configs easier to understand and maintain, in my view. Em, what bits do you refer to? The lines you quoted are not changed... Hmmm, editing snafu there. I think I was referring to the ARCH_VEXPRESS_DT item, which is defined just after the lines I quoted. Ok, will do. Cheers! Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
Re: [PATCH 5/5] ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4
On Wed, 2011-11-16 at 15:36 +, Dave Martin wrote:
+/include/ skeleton.dtsi
+
+/ {
+ model = V2P-CA5s;
+ arm,hbi = 0x225;
Are these part numbers formally hex numbers? Is so, fine. Otherwise
maybe it would me safer to make properties of this kind strings.
Hex values. See
http://infocenter.arm.com/help/topic/com.arm.doc.dui0447e/CACBEHGJ.html
+config ARCH_VEXPRESS_V2P_CA5S_CA9
+ bool DT: CoreTiles Express A5x2 and A9x4
This DT stuff is a bit cryptic -- also it's an implementation feature
rather than part of the core nature of this config option.
Yeah, I know. I just didn't feel very verbose doing the Kconfig changes.
Also, pedaitically, the product name is CoreTile Express.
Ha ha - I wanted to express the plurality of A5 _and_ a9 ;-) Never mind,
will change it.
Finally, this option does not support those core tiles, as such; rather
it supports particular whole-platform configurations involving those
core tiles.
How about CoreTile Express A5x2 and A9x4 based platform support
Fine with me - I'll use your wording :-)
+ select ARCH_VEXPRESS_RS1
+ select ARCH_VEXPRESS_DT
+ select ARM_ERRATA_720789
+ select ARM_ERRATA_751472
+ select ARM_ERRATA_753970
+ help
+ This option enabled Device Tree based support for
+ CoreTile Express A5x2 (V2P-CA5s) and
+ CoreTile Express A9x4 (V2P-CA9).
+
+ Note that you must provide kernel with a valid DTB
+ for the board if you want to use this option.
For the above reasons, the following alternative text might be a bit
more user-friendly:
help
This option enables support for systems using any of the the following
ARM core tiles on the Versatile Express motherboard:
CoreTile Express A5x2 (V2P-CA5s)
CoreTile Express A9x4 (V2P-CA9)
You must boot using a Flattened Device Tree in order to use these
platforms. The traditional (ATAGs) boot method is not usable on
these boards with this option.
If you want your kernel to run on one of these platforms and your
bootloader supports Flattened Device Tree based booting, say Y.
Same here - will copy this :-)
Do we still support the old style V2P-CA9x4 support? If so, we could
add a comment explaining that is available as an alternative, for now.
We do, with the non-DT option (Russell wouldn't be very happy if his
serial port multiplexer stopped working ;-)
endmenu
diff --git a/arch/arm/mach-vexpress/Makefile
b/arch/arm/mach-vexpress/Makefile
index 90551b9..06e3687 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -4,5 +4,6 @@
obj-y := v2m.o
obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
+obj-$(CONFIG_ARCH_VEXPRESS_V2P_CA5S_CA9) += v2p-ca5s_ca9.o
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-vexpress/v2p-ca5s_ca9.c
b/arch/arm/mach-vexpress/v2p-ca5s_ca9.c
[...]
+DT_MACHINE_START(VEXPRESS_V2P_CA5S_CA9, ARM Versatile Express)
We could try to name the platform fully here, but these strings would
get very long -- so I agree it best to leave that to be specified in
the device tree.
Having such machine name here and model in the dts gives such a nice
message in the log:
Machine: ARM Versatile Express, model: V2P-CA9
Which is sort-of-correct.
Cheers!
Paweł
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Re: [PATCH 4/5] ARM: vexpress: Initial RS1 memory map support
On Wed, 2011-11-16 at 15:42 +, Dave Martin wrote:
+config ARCH_VEXPRESS_LEGACY
Brief comment explaining what this is?
+config ARCH_VEXPRESS_RS1
Ditto
Ok.
+ bool
+
config ARCH_VEXPRESS_CA9X4
bool Versatile Express Cortex-A9x4 tile
select CPU_V7
@@ -8,6 +16,7 @@ config ARCH_VEXPRESS_CA9X4
select ARM_ERRATA_720789
select ARM_ERRATA_751472
select ARM_ERRATA_753970
+ select ARCH_VEXPRESS_LEGACY
We should add a brief note to the help text explaining the existence
of the new combined A9x4/A5x2 DT based support, if were planning to
keep both variants. (Probably wise for now, since people may be
temporarily stuck old bootloaders etc.)
If there is no help text yet, we should add some, but it should be
kept brief.
No probs. All suggestions and templates welcomed :-)
[...]
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S
b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index fd9e6c7..adc94ce 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -10,12 +10,41 @@
* published by the Free Software Foundation.
*/
-#define DEBUG_LL_UART_OFFSET 0x9000
+#define VEXPRESS_PHYS_BASE_LEGACY 0x1000
+#define VEXPRESS_UART_OFFSET_LEGACY0x9000
+
+#define VEXPRESS_PHYS_BASE_RS1 0x1c00
+#define VEXPRESS_UART_OFFSET_RS1 0x0009
+
+#define VEXPRESS_VIRT_BASE 0xf800
.macro addruart,rp,rv,tmp
- mov \rp, #DEBUG_LL_UART_OFFSET
- orr \rv, \rp, #0xf800 @ virtual base
- orr \rp, \rp, #0x1000 @ physical base
+
+ @ Check the MMU state
+#if defined(CONFIG_MMU)
+ mrc p15, 0, \tmp, c1, c0@ SCTRL
+ tst \tmp, #1@ MMU enabled?
+ moveq \tmp, #VEXPRESS_PHYS_BASE_LEGACY
+ movne \tmp, #VEXPRESS_VIRT_BASE
+#else
+ mov \tmp, #VEXPRESS_PHYS_BASE_LEGACY
+#endif
+
+ @ PL011 present in legacy place?
+ orr \tmp, \tmp, #VEXPRESS_UART_OFFSET_LEGACY
+ ldr \tmp, [\tmp, #0xfe0]@ PeriphID0
+ teq \tmp, #0x11 @ PL011
+
+ @ Legacy memory map
+ moveq \rp, #VEXPRESS_UART_OFFSET_LEGACY
+ orreq \rv, \rp, #VEXPRESS_VIRT_BASE
+ orreq \rp, \rp, #VEXPRESS_PHYS_BASE_LEGACY
+
+ @ RS1 memory map
+ movne \rp, #VEXPRESS_UART_OFFSET_RS1
+ orrne \rv, \rp, #VEXPRESS_VIRT_BASE
+ orrne \rp, \rp, #VEXPRESS_PHYS_BASE_RS1
I will assume that this works :)
It does, tested :-) The probing order legacy-then-RS1 is carefully
selected - it doesn't work the other way round.
Without grokking the detail, it looks fairly reasonable.
I was considering something similar to
arch/arm/mach-omap2/include/mach/debug-macro.S, but it made the code
even more obscure.
[...]
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
[...]
void __init v2m_dt_init_early(void)
@@ -601,6 +643,10 @@ static struct of_dev_auxdata v2m_dt_auxdata_lookup[]
__initdata = {
OF_DEV_AUXDATA(arm,vexpress-flash, V2M_NOR0, physmap-flash,
v2m_flash_data),
OF_DEV_AUXDATA(arm,primecell, V2M_MMCI, mb:mmci, v2m_mmci_data),
+ /* RS1 memory map */
+ OF_DEV_AUXDATA(arm,vexpress-flash, 0x0800, physmap-flash,
+ v2m_flash_data),
+ OF_DEV_AUXDATA(arm,primecell, 0x1c05, mb:mmci, v2m_mmci_data),
Can we have macros instead of the magic numbers here?
I don't see any point:
1. These value are used only and only here, so #defining them would just
add extra lines of traffic.
2. They correspond to numbers (as in: numbers) in DTS.
3. They will disappear once I'm done with MMCI and sysreg bindings. So
probably long before this series is actually merged...
Cheers!
Paweł
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Re: [PATCH 3/5] ARM: vexpress: Add DT support in v2m
On Wed, 2011-11-16 at 16:26 +, Rob Herring wrote: On 11/16/2011 09:44 AM, Dave Martin wrote: On Fri, Nov 11, 2011 at 06:27:04PM +, Pawel Moll wrote: This patch provides hooks for DT-based tile machine implementations and adds Device Tree description for the motherboard. Signed-off-by: Pawel Moll pawel.m...@arm.com --- Documentation/devicetree/bindings/arm/vexpress| 92 ++ arch/arm/boot/dts/vexpress-v2m-legacy.dtsi| 190 + arch/arm/mach-vexpress/Kconfig|4 + arch/arm/mach-vexpress/core.h |9 + arch/arm/mach-vexpress/include/mach/motherboard.h |8 + arch/arm/mach-vexpress/v2m.c | 140 +++- 6 files changed, 442 insertions(+), 1 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/vexpress create mode 100644 arch/arm/boot/dts/vexpress-v2m-legacy.dtsi diff --git a/Documentation/devicetree/bindings/arm/vexpress b/Documentation/devicetree/bindings/arm/vexpress [...] +Required properties in the root node: +- compatible value: + - for motherboard in legacy mode: + compatible = arm,vexpress-model, arm,vexpress-legacy, arm-vexpress; + - for motherboard in RS1 mode: + compatible = arm,vexpress-model, arm-vexpress; So, we have: arm,vexpress-* implies arm,vexpress arm,vexpress-* may imply arm,vexpress-legacy arm,vexpress-legacy implies arm,vexpress This means we have no bounded test for RS1-only features: the needed test is compatible(node, arm,vexpress) !compatible(node, arm,vexpress-legacy) Unfortunately, if there is someday an rs2 memory map, that will also match the above. Using inverse compatibility in this way feels dangerous, because the condition will pass for an arbitrary set of future conditions that we haven't imagined yet. This means it's, impossible even in principle to panic the kernel cleanly if presented with a device tree for a platform variant which is too new for the kernel to support. Can we instead have a specific arm,vexpress-rs1? compatible = arm,vexpress-model, arm-vexpress-rs1, arm-vexpress; Then, we can be exact about compatibility: universal features are compatible with arm,vexpress; memory-map-specific features are compatible with either arm,vexpress-legacy or arm,vexpress-rs1. Really, legacy is a bad name. http://en.wikipedia.org/wiki/De_gustibus_non_est_disputandum ;-) This is de-facto name we use in ARM. See: http://infocenter.arm.com/help/topic/com.arm.doc.dui0447e/ch04s02s01.html If you defined the property when the original vexpress was designed, it never would have had legacy in the name. Generally speaking you never change bindings on old platforms. So I would have arm,vexpress mean legacy and arm,vexpress-rs1 be the new memory map. I'd rather second Dave's idea of having compatible = arm,vexpress-model, arm-vexpress-rs1, arm-vexpress; and +compatible = arm,vexpress-model, arm,vexpress-legacy, arm-vexpress; Cheers! Paweł ___ devicetree-discuss mailing list devicetree-discuss@lists.ozlabs.org https://lists.ozlabs.org/listinfo/devicetree-discuss
