date:20170107

As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
must be programmed.
Enable bit 12 for programmable header packet.
Enable bit 15 for Y cordinate support.

v2: (Rodrigo)
- move CHICKEN_TRANS_EDP bit set logic right after setup_vsc

v3:(Rodrigo)
- initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0

v4:(Rodrigo)
- initialize chicken_trans=0,add chicken_trans=CHICKEN_TRANS_BIT12

Cc: Rodrigo Vivi 
Cc: Jim Bride 
Signed-off-by: vathsala nagaraju 
Signed-off-by: Patil Deepti 
---
 drivers/gpu/drm/i915/i915_reg.h  | 7 +++
 drivers/gpu/drm/i915/intel_psr.c | 7 +++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7830e6e..5ca506a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6449,6 +6449,13 @@ enum {
 #define  BDW_DPRS_MASK_VBLANK_SRD  (1 << 0)
 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, 
_CHICKEN_PIPESL_1_B)

+#define CHICKEN_TRANS_A 0x420c0
+#define CHICKEN_TRANS_B 0x420c4
+#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, 
CHICKEN_TRANS_B)
+#define TRANS_EDP  3
+#define CHICKEN_TRANS_BIT12(1<<12)
+#define CHICKEN_TRANS_BIT15(1<<15)
+
 #define DISP_ARB_CTL   _MMIO(0x45000)
 #define  DISP_FBC_MEMORY_WAKE  (1<<31)
 #define  DISP_TILE_SURFACE_SWIZZLING   (1<<13)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index b28891b..1e5dd8f 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -475,6 +475,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+   uint32_t chicken_trans = 0;

if (!HAS_PSR(dev_priv)) {
DRM_DEBUG_KMS("PSR not supported on this platform\n");
@@ -505,6 +506,12 @@ void intel_psr_enable(struct intel_dp *intel_dp)
dev_priv->psr.psr2_support = false;
else
skl_psr_setup_su_vsc(intel_dp);
+   /* Set CHICKEN_TRANS_BIT12 for programable header */
+   chicken_trans = CHICKEN_TRANS_BIT12;
+   /* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported 
*/
+   if (dev_priv->psr.y_cord_support)
+   chicken_trans |= CHICKEN_TRANS_BIT15;
+   I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
} else {
/* set up vsc header for psr1 */
hsw_psr_setup_vsc(intel_dp);
-- 
1.9.1

[Bug 99309] [radeonsi]glsl: Override the # of varying slots for ClipDistance and TessLevel*. broke chromium browser

https://bugs.freedesktop.org/show_bug.cgi?id=99309

Arek RuÅniak  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

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[Bug 99309] [radeonsi]glsl: Override the # of varying slots for ClipDistance and TessLevel*. broke chromium browser

https://bugs.freedesktop.org/show_bug.cgi?id=99309

--- Comment #3 from Arek RuÅniak  ---
ok, after commit "Revert recent GLSL slot counting fiasco" this raport should
disappear

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[Bug 99311] [regression, bisected, core] Updating to 1edc53a66b breaks SDDM (white screen on launch)

https://bugs.freedesktop.org/show_bug.cgi?id=99311

Kai  changed:

   What|Removed |Added

  Component|Drivers/Gallium/radeonsi|Mesa core
 CC||kenneth at whitecape.org
Summary|[regression,radeonsi]   |[regression,bisected,core]
   |Updating to 1edc53a66b  |Updating to 1edc53a66b
   |breaks SDDM (white screen   |breaks SDDM (white screen
   |on launch)  |on launch)
   Keywords||bisected
 QA Contact|dri-devel at lists.freedesktop |mesa-dev at 
lists.freedesktop.
   |.org|org
   Assignee|dri-devel at lists.freedesktop |mesa-dev at 
lists.freedesktop.
   |.org|org

--- Comment #1 from Kai  ---
Ok, I finished the bisection:
8b5749f65ac434961308ccb579fb8a816e4f29d5 is the first bad commit
commit 8b5749f65ac434961308ccb579fb8a816e4f29d5
Author: Kenneth Graunke 
Date:   Sun Nov 15 04:37:50 2015 -0800

glsl: Override the # of varying slots for ClipDistance and TessLevel*.

Right now, this shouldn't have any effect, as all drivers use
LowerClipDist and LowerTessFactors to turn the float[] arrays into
vectors.

However, it should help make it possible for drivers to avoid that
lowering.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Jason Ekstrand 
Reviewed-by: Timothy Arceri 

:04 04 1b29c9a54c33c8809e38f8fd99ea7dbb1935107e
5900d84fdc8d64a53dae3b7c4ac01be73b31c614 M  src

The bisection log is:
# bad: [1edc53a66b33e4d17688a3d03b1bdffed2aec414] glsl: fix opt_minmax
redundancy checks against baserange
# good: [c93efb0a4fd7dba8390e066605fe5f4c3e26e767] swr: [rasterizer core]
rename OutputMerger functions
git bisect start '1edc53a66b' 'c93efb0a4f'
# good: [6e7ce1ef55b138ed2cdedb40cbc010b523de8743] gallivm: generalize
4x4f->1x16ub special case conversion
git bisect good 6e7ce1ef55b138ed2cdedb40cbc010b523de8743
# bad: [e6ae19944d977dc91bc45adff679337182c20683] i965: Rework gl_TessLevel*[]
handling to use NIR compact arrays.
git bisect bad e6ae19944d977dc91bc45adff679337182c20683
# bad: [5c580e64cc206ab160e1767c42e4d6c81f67da4d] glsl: Mark whole variable
used for ClipDistance and TessLevel*.
git bisect bad 5c580e64cc206ab160e1767c42e4d6c81f67da4d
# good: [aead6a1e947af84b0af2853c204d5cad6d92bfff] gallium/radeon: use the
internal clear_buffer callback to fix r600g
git bisect good aead6a1e947af84b0af2853c204d5cad6d92bfff
# bad: [8b5749f65ac434961308ccb579fb8a816e4f29d5] glsl: Override the # of
varying slots for ClipDistance and TessLevel*.
git bisect bad 8b5749f65ac434961308ccb579fb8a816e4f29d5
# good: [6aa5cb34d03765b7be8611aa516bc201bd337f73] glsl: Create and use a new
ir_variable::count_attribute_slots() wrapper.
git bisect good 6aa5cb34d03765b7be8611aa516bc201bd337f73
# first bad commit: [8b5749f65ac434961308ccb579fb8a816e4f29d5] glsl: Override
the # of varying slots for ClipDistance and TessLevel*.

I verified this is really the first bad commit by building 1edc53a66b with
8b5749f65a reverted and that gave me a working SDDM again.

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[Bug 99261] Kernel 4.10-rc2 on APU with Kaveri + Topaz : boot hangs on switch to amdgpudrmfb

https://bugs.freedesktop.org/show_bug.cgi?id=99261

Alex Deucher  changed:

   What|Removed |Added

 Resolution|--- |NOTABUG
 Status|NEW |RESOLVED

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[Bug 99316] Radeon crash when laptop on AC power

https://bugs.freedesktop.org/show_bug.cgi?id=99316

--- Comment #3 from Alex Deucher  ---
Possibly a duplicate of bug 98897.  Does attachment 128780 fix the issue?

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[Bug 99316] Radeon crash when laptop on AC power

https://bugs.freedesktop.org/show_bug.cgi?id=99316

--- Comment #2 from Samuel Anderson  ---
Created attachment 128809
  --> https://bugs.freedesktop.org/attachment.cgi?id=128809=edit
AC Power glxgears

The last part of the log, 121 onward is the second failed attempt for glxgears.
The previous part 94-96 is a successful glxgears attempt seconds earlier. These
logs are the only thing that have been consistent from my tests.

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[Bug 99309] [radeonsi]glsl: Override the # of varying slots for ClipDistance and TessLevel*. broke chromium browser

https://bugs.freedesktop.org/show_bug.cgi?id=99309

--- Comment #2 from Edmondo Tommasina  ---
Same here. After updating to mesa-git Chromium with gpu acceleration shows only
garbage.

OpenGL renderer string: Gallium 0.4 on AMD POLARIS10 (DRM 3.8.0 / 4.9.0-gentoo,
LLVM 3.9.0)

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[Bug 99316] Radeon crash when laptop on AC power

https://bugs.freedesktop.org/show_bug.cgi?id=99316

Samuel Anderson  changed:

   What|Removed |Added

 CC||LordSamanon at gmail.com

--- Comment #1 from Samuel Anderson  ---
Created attachment 128808
  --> https://bugs.freedesktop.org/attachment.cgi?id=128808=edit
AC Power Portal 2 dmesg

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[Bug 99316] Radeon crash when laptop on AC power

https://bugs.freedesktop.org/show_bug.cgi?id=99316

Bug ID: 99316
Summary: Radeon crash when laptop on AC power
Product: DRI
Version: unspecified
Hardware: Other
OS: All
Status: NEW
Severity: major
Priority: medium
Component: DRM/Radeon
Assignee: dri-devel at lists.freedesktop.org
Reporter: LordSamanon at gmail.com

Created attachment 128807
--> https://bugs.freedesktop.org/attachment.cgi?id=128807=edit
AC Power Unigine Heaven dmesg

I have a Dell laptop with an Intel iGPU and a Radeon dGPU (a Firepro W5130M,
recognized as a Radeon HD 8830M by lspci).

Whenever I attempt to use the Radeon card via DRI_PRIME=1 while the laptop is
plugged in, the card crashes. When on battery the card performs fine.

One way I have tested this is with glxgears. Often glxgears will work the first
time it is run, but if it is closed and then opened a few seconds later, it
will crash.

I have also tried running programs like Portal 2 and Unigine Heaven. These
always hang. Unfortunately the error messages produced in dmesg are not the
most consistent. Sometimes I get a backtrace, sometimes even a kernel panic on
reboot.

I'll post the various logs I have. One thing I have found is that glxgears does
not crash if I use radeon.runpm=0, however it still hangs when running
something like Portal.

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[Bug 80419] XCOM: Enemy Unknown Causes lockup

https://bugs.freedesktop.org/show_bug.cgi?id=80419

Marek OlÅ¡Ã¡k  changed:

   What|Removed |Added

 Status|NEW |RESOLVED
 Resolution|--- |FIXED

--- Comment #151 from Marek OlÅ¡Ã¡k  ---
OK. The CSO fix did it. Thanks for info. Closing.

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[Bug 80419] XCOM: Enemy Unknown Causes lockup

https://bugs.freedesktop.org/show_bug.cgi?id=80419

--- Comment #150 from ArneJ  ---
I also suffered a lot from this issue on my R9 270X.
I was never able to go past the first tutorial mission because my PC hung
during that mission.

Now I tried it again with mesa 13.0.3 and I was finally able to finish the
first mission and also played 3 more missions after that without any issues.
It looks like this issue is finally resolved.

Thanks a lot Marek!

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[Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

2017-01-07 Thread Chris Wilson

On Sat, Jan 07, 2017 at 11:42:04PM +0530, vathsala nagaraju wrote:
> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
> must be programmed.
> Enable bit 12 for programmable header packet.
> Enable bit 15 for Y cordinate support.
> 
> v2: (Rodrigo)
> - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
> 
> v3:(Rodrigo)
> - initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
> 
> v4:(Rodrigo)
> - initialize chicken_trans=0,add chicken_trans=CHICKEN_TRANS_BIT12

Weird. Just scope the variable properly, use the correct type.

> Cc: Rodrigo Vivi 
> Cc: Jim Bride 
> Signed-off-by: vathsala nagaraju 
> Signed-off-by: Patil Deepti 
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 7 +++
>  drivers/gpu/drm/i915/intel_psr.c | 7 +++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7830e6e..5ca506a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6449,6 +6449,13 @@ enum {
>  #define  BDW_DPRS_MASK_VBLANK_SRD(1 << 0)
>  #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, 
> _CHICKEN_PIPESL_1_B)
>  
> +#define CHICKEN_TRANS_A 0x420c0
> +#define CHICKEN_TRANS_B 0x420c4
> +#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, 
> CHICKEN_TRANS_B)
> +#define TRANS_EDP  3
> +#define CHICKEN_TRANS_BIT12(1<<12)
> +#define CHICKEN_TRANS_BIT15(1<<15)

Useless naming. Either given them proper names or don't.

>   if (!HAS_PSR(dev_priv)) {
u32 chicken;

>   DRM_DEBUG_KMS("PSR not supported on this platform\n");
> @@ -505,6 +506,12 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>   dev_priv->psr.psr2_support = false;
>   else
>   skl_psr_setup_su_vsc(intel_dp);
> + /* Set CHICKEN_TRANS_BIT12 for programable header */
> + chicken_trans = CHICKEN_TRANS_BIT12;

We can see you are setting CHICKEN_TRANS_BIT12, so don't bother
repeating that. What programmable header? Why is this in a chicken bit,
what is the bspec reference, all of those would be useful to answer.

> + /* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported 
> */
> + if (dev_priv->psr.y_cord_support)
> + chicken_trans |= CHICKEN_TRANS_BIT15;

Again. Tell us why, we can read the code. Are the names meaningful? More
meaningful than chicken |= BIT(15); ?

> + I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
>   } else {
>   /* set up vsc header for psr1 */
>   hsw_psr_setup_vsc(intel_dp);
> -- 
> 1.9.1
> 
> ___
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Chris Wilson, Intel Open Source Technology Centre

[Bug 99313] A few amdgpu errors with kernel 4.10-rc2 (Kaveri + Topaz)

https://bugs.freedesktop.org/show_bug.cgi?id=99313

--- Comment #1 from SET  ---
Erratum :

iGPU : 00:01.0 VGA compatible controller: Advanced Micro Devices, Inc.
[AMD/ATI] Kaveri [Radeon R6 Graphics]

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[Bug 99313] A few amdgpu errors with kernel 4.10-rc2 (Kaveri + Topaz)

https://bugs.freedesktop.org/show_bug.cgi?id=99313

Bug ID: 99313
   Summary: A few amdgpu errors with kernel 4.10-rc2 (Kaveri +
Topaz)
   Product: DRI
   Version: XOrg git
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Severity: normal
  Priority: medium
 Component: DRM/AMDgpu
  Assignee: dri-devel at lists.freedesktop.org
  Reporter: nmset at netcourrier.com

Created attachment 128806
  --> https://bugs.freedesktop.org/attachment.cgi?id=128806=edit
dmesg for amdgpu on kernel 4.10-rc2

This is just to report a few errors with amdgpu in kernel 4.10-rc2 on my
laptop, featuring :

APU : AMD A10-7300 Radeon R6, 10 Compute Cores 4C+6G (from /proc/cpuinfo).
iGPU : 00:01.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Kaveri
HDMI/DP Audio Controller
dGPU : 01:00.0 Display controller: Advanced Micro Devices, Inc. [AMD/ATI] Topaz
XT [Radeon R7 M260/M265 / M340/M360 / M440/M445]
Xorg : 1.18.4, on Arch Linux

$(dmesg |grep -i amdgpu) is in the attachement k4.10-rc2_amdgpu_dmesg.txt.
In brief, there are errors related to UVD and IB with Kaveri iGPU.

I do have a normal X session, except that the laptop never suspends, and things
can then go as bad as corrupting the file system beyond recognition by Grub.

I am posting this information in the hope it can be useful to developers.

Regards.

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[Bug 99261] Kernel 4.10-rc2 on APU with Kaveri + Topaz : boot hangs on switch to amdgpudrmfb

https://bugs.freedesktop.org/show_bug.cgi?id=99261

--- Comment #4 from SET  ---
Well, the hang up on switch to amdgpudrmfb was due to the kernel boot parameter
'acpi=off' I had to use to go beyond the 'loading initramfs' step. Initial
hangup in the latter step was due to a UEFI bug of the laptop.

Fortunately, the manufacturer provides a BIOS update with the tag 'UEFI
security enhancement'. After flashing the new BIOS, the laptop boots with
kernel 4.10-rc2, with a few errors related to amdgpu, which I'll report in a
new post.

Sorry for the inconvenience.

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[PATCH 10/10] drm/msm/dsi: Add PHY/PLL for 8x96

Extend the DSI PHY/PLL drivers to support the DSI 14nm PHY/PLL
found on 8x96.

These are picked up from the downstream driver. The PHY part is similar
to the other DSI PHYs. The PLL driver requires some trickery so that
one DSI PLL can drive both the DSIs (i.e, dual DSI mode).

In the case of dual DSI mode. One DSI instance becomes the clock master,
and other the clock slave. The master PLL's output (Byte and Pixel clock)
is fed to both the DSI hosts/PHYs.

When the DSIs are configured in dual DSI mode, the PHY driver communicates
to the PLL driver using msm_dsi_pll_set_usecase() which instance is the
master and which one is the slave. When setting rate, the master PLL also
configures some of the slave PLL/PHY registers which need to be identical
to the master's for correct dual DSI behaviour.

There are 2 PLL post dividers that should have ideally been modelled as
generic clk_divider clocks, but require some customization for dual DSI.
In particular, when the master PLL's post-diviers are set, the slave PLL's
post-dividers need to be set too. The clk_ops for these use clk_divider's
helper ops and flags internally to prevent redundant code.

Cc: Stephen Boyd 
Signed-off-by: Archit Taneja 
---
 drivers/gpu/drm/msm/Kconfig|7 +
 drivers/gpu/drm/msm/Makefile   |2 +
 drivers/gpu/drm/msm/dsi/dsi.h  |8 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c  |2 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h  |2 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c |  168 +
 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c  |   12 +
 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h  |   11 +
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 1067 
 9 files changed, 1279 insertions(+)
 create mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
 create mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c

diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index d96b2b6..50b0c7e 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -71,3 +71,10 @@ config DRM_MSM_DSI_28NM_8960_PHY
help
  Choose this option if the 28nm DSI PHY 8960 variant is used on the
  platform.
+
+config DRM_MSM_DSI_14NM_PHY
+   bool "Enable DSI 14NM PHY driver in MSM DRM (used in MSM8996)"
+   depends on DRM_MSM_DSI
+   default y
+   help
+ Choose this option if DSI PHY on 8996 is used on the platform.
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 90f66c4..e7c0f06 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -74,11 +74,13 @@ msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
 msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
 msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
 msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o
+obj-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o

 ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y)
 msm-y += dsi/pll/dsi_pll.o
 msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o
 msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/pll/dsi_pll_28nm_8960.o
+obj-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/pll/dsi_pll_14nm.o
 endif

 obj-$(CONFIG_DRM_MSM)  += msm.o
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 9465996..3236997 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -35,6 +35,7 @@ enum msm_dsi_phy_type {
MSM_DSI_PHY_28NM_LP,
MSM_DSI_PHY_20NM,
MSM_DSI_PHY_28NM_8960,
+   MSM_DSI_PHY_14NM,
MSM_DSI_PHY_MAX
 };

@@ -117,6 +118,8 @@ int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
 void msm_dsi_pll_save_state(struct msm_dsi_pll *pll);
 int msm_dsi_pll_restore_state(struct msm_dsi_pll *pll);
+int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll,
+   enum msm_dsi_phy_usecase uc);
 #else
 static inline struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device 
*pdev,
 enum msm_dsi_phy_type type, int id) {
@@ -137,6 +140,11 @@ static inline int msm_dsi_pll_restore_state(struct 
msm_dsi_pll *pll)
 {
return 0;
 }
+static inline int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll,
+ enum msm_dsi_phy_usecase uc)
+{
+   return -ENODEV;
+}
 #endif

 /* dsi host */
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 11919bc..410dd3c5 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -391,6 +391,8 @@ static void dsi_phy_disable_resource(struct msm_dsi_phy 
*phy)
{ .compatible = "qcom,dsi-phy-28nm-8960",
  .data = _phy_28nm_8960_cfgs },
 #endif
+   { .compatible = "qcom,dsi-phy-14nm",
+ .data = _phy_14nm_cfgs },
{}
 };

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h

[PATCH 09/10] drm/msm/dsi: Add new method to calculate 14nm PHY timings

From: Hai Li 

The 14nm DSI PHY on 8x96 (called PHY v2 downstream) requires a different
set of calculations for computing D-PHY timing params. Create a
timing_calc_v2 func for the newer v2 PHYs.

Signed-off-by: Hai Li 
Signed-off-by: Archit Taneja 
---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 117 ++
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h |  11 +++-
 2 files changed, 127 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index c9e1a79..11919bc 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -148,6 +148,123 @@ int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing 
*timing,
return 0;
 }

+int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
+   struct msm_dsi_phy_clk_request *clk_req)
+{
+   const unsigned long bit_rate = clk_req->bitclk_rate;
+   const unsigned long esc_rate = clk_req->escclk_rate;
+   s32 ui, ui_x8, lpx;
+   s32 tmax, tmin;
+   s32 pcnt0 = 50;
+   s32 pcnt1 = 50;
+   s32 pcnt2 = 10;
+   s32 pcnt3 = 30;
+   s32 pcnt4 = 10;
+   s32 pcnt5 = 2;
+   s32 coeff = 1000; /* Precision, should avoid overflow */
+   s32 hb_en, hb_en_ckln, pd_ckln, pd;
+   s32 val, val_ckln;
+   s32 temp;
+
+   if (!bit_rate || !esc_rate)
+   return -EINVAL;
+
+   timing->hs_halfbyte_en = 0;
+   hb_en = 0;
+   timing->hs_halfbyte_en_ckln = 0;
+   hb_en_ckln = 0;
+   timing->hs_prep_dly_ckln = (bit_rate > 1) ? 0 : 3;
+   pd_ckln = timing->hs_prep_dly_ckln;
+   timing->hs_prep_dly = (bit_rate > 12000) ? 0 : 1;
+   pd = timing->hs_prep_dly;
+
+   val = (hb_en << 2) + (pd << 1);
+   val_ckln = (hb_en_ckln << 2) + (pd_ckln << 1);
+
+   ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
+   ui_x8 = ui << 3;
+   lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
+
+   temp = S_DIV_ROUND_UP(38 * coeff - val_ckln * ui, ui_x8);
+   tmin = max_t(s32, temp, 0);
+   temp = (95 * coeff - val_ckln * ui) / ui_x8;
+   tmax = max_t(s32, temp, 0);
+   timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
+
+   temp = 300 * coeff - ((timing->clk_prepare << 3) + val_ckln) * ui;
+   tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;
+   tmax = (tmin > 255) ? 511 : 255;
+   timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
+
+   tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
+   temp = 105 * coeff + 12 * ui - 20 * coeff;
+   tmax = (temp + 3 * ui) / ui_x8;
+   timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
+
+   temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui - val * ui, ui_x8);
+   tmin = max_t(s32, temp, 0);
+   temp = (85 * coeff + 6 * ui - val * ui) / ui_x8;
+   tmax = max_t(s32, temp, 0);
+   timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
+
+   temp = 145 * coeff + 10 * ui - ((timing->hs_prepare << 3) + val) * ui;
+   tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;
+   tmax = 255;
+   timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
+
+   tmin = DIV_ROUND_UP(60 * coeff + 4 * ui + 3 * ui, ui_x8);
+   temp = 105 * coeff + 12 * ui - 20 * coeff;
+   tmax = (temp + 3 * ui) / ui_x8;
+   timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
+
+   temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
+   timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
+
+   tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
+   tmax = 255;
+   timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
+
+   temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
+   timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
+
+   temp = 60 * coeff + 52 * ui - 43 * ui;
+   tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
+   tmax = 63;
+   timing->shared_timings.clk_post =
+   linear_inter(tmax, tmin, pcnt2, 0, false);
+
+   temp = 8 * ui + ((timing->clk_prepare << 3) + val_ckln) * ui;
+   temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui;
+   temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
+   (((timing->hs_rqst_ckln << 3) + 8) * ui);
+   tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
+   tmax = 63;
+   if (tmin > tmax) {
+   temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
+   timing->shared_timings.clk_pre = temp >> 1;
+   timing->shared_timings.clk_pre_inc_by_2 = 1;
+   } else {
+   timing->shared_timings.clk_pre =
+   linear_inter(tmax, tmin, pcnt2, 0, false);
+   timing->shared_timings.clk_pre_inc_by_2 = 0;
+   }
+
+   timing->ta_go = 3;
+   timing->ta_sure = 0;
+   timing->ta_get = 4;
+
+

[PATCH 08/10] drm/msm/dsi: Udpate generated headers for 14nm PHY and PLL

Signed-off-by: Archit Taneja 
---
 drivers/gpu/drm/msm/dsi/dsi.xml.h | 252 ++
 1 file changed, 252 insertions(+)

diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h 
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 4958594..234b3b3 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -1304,5 +1304,257 @@ static inline uint32_t 
DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)

 #define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x0018

+#define REG_DSI_14nm_PHY_CMN_REVISION_ID0  0x
+
+#define REG_DSI_14nm_PHY_CMN_REVISION_ID1  0x0004
+
+#define REG_DSI_14nm_PHY_CMN_REVISION_ID2  0x0008
+
+#define REG_DSI_14nm_PHY_CMN_REVISION_ID3  0x000c
+
+#define REG_DSI_14nm_PHY_CMN_CLK_CFG0  0x0010
+#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK   0x000f
+#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT  0
+static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)
+{
+   return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & 
DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK;
+}
+#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK   0x00f0
+#define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT  4
+static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)
+{
+   return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & 
DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK;
+}
+
+#define REG_DSI_14nm_PHY_CMN_CLK_CFG1  0x0014
+#define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL   0x0001
+
+#define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL0x0018
+#define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL  0x0004
+
+#define REG_DSI_14nm_PHY_CMN_CTRL_00x001c
+
+#define REG_DSI_14nm_PHY_CMN_CTRL_10x0020
+
+#define REG_DSI_14nm_PHY_CMN_HW_TRIGGER
0x0024
+
+#define REG_DSI_14nm_PHY_CMN_SW_CFG0   0x0028
+
+#define REG_DSI_14nm_PHY_CMN_SW_CFG1   0x002c
+
+#define REG_DSI_14nm_PHY_CMN_SW_CFG2   0x0030
+
+#define REG_DSI_14nm_PHY_CMN_HW_CFG0   0x0034
+
+#define REG_DSI_14nm_PHY_CMN_HW_CFG1   0x0038
+
+#define REG_DSI_14nm_PHY_CMN_HW_CFG2   0x003c
+
+#define REG_DSI_14nm_PHY_CMN_HW_CFG3   0x0040
+
+#define REG_DSI_14nm_PHY_CMN_HW_CFG4   0x0044
+
+#define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x0048
+#define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START   0x0001
+
+#define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x004c
+#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x003f
+#define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT0
+static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)
+{
+   return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & 
DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK;
+}
+
+static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x + 
0x80*i0; }
+
+static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 
0x + 0x80*i0; }
+#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x00c0
+#define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT6
+static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)
+{
+   return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & 
DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK;
+}
+
+static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 
0x0004 + 0x80*i0; }
+#define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN0x0001
+
+static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 
0x0008 + 0x80*i0; }
+
+static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 
0x000c + 0x80*i0; }
+
+static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 
0x0010 + 0x80*i0; }
+
+static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 
0x0014 + 0x80*i0; }
+
+static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 
0x0018 + 0x80*i0; }
+#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK0x00ff
+#define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT   0
+static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)
+{
+   return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & 
DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK;
+}
+
+static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 
0x001c + 0x80*i0; }
+#define

[PATCH 07/10] drm/msm/dsi: Move PHY operations out of host

From: Hai Li 

Since DSI PHY has been a separate platform device, it should not
depend on the resources in host to be functional. This change is
to trigger PHY operations in manager, instead of host, so that
host and PHY can be completely separated.

Signed-off-by: Hai Li 
Signed-off-by: Archit Taneja 
---
 drivers/gpu/drm/msm/dsi/dsi.h   |  18 ++-
 drivers/gpu/drm/msm/dsi/dsi_host.c  |  46 +++---
 drivers/gpu/drm/msm/dsi/dsi_manager.c   | 178 ++--
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c   |  39 --
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h   |   4 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c  |   4 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c  |   4 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c |   4 +-
 8 files changed, 172 insertions(+), 125 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 9407a68..9465996 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -28,6 +28,7 @@
 #define DSI_MAX2

 struct msm_dsi_phy_shared_timings;
+struct msm_dsi_phy_clk_request;

 enum msm_dsi_phy_type {
MSM_DSI_PHY_28NM_HPM,
@@ -92,10 +93,6 @@ struct msm_dsi {
 void msm_dsi_manager_bridge_destroy(struct drm_bridge *bridge);
 struct drm_connector *msm_dsi_manager_connector_init(u8 id);
 struct drm_connector *msm_dsi_manager_ext_bridge_init(u8 id);
-int msm_dsi_manager_phy_enable(int id,
-   const unsigned long bit_rate, const unsigned long esc_rate,
-   struct msm_dsi_phy_shared_timings *shared_timing);
-void msm_dsi_manager_phy_disable(int id);
 int msm_dsi_manager_cmd_xfer(int id, const struct mipi_dsi_msg *msg);
 bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 dma_base, u32 len);
 void msm_dsi_manager_attach_dsi_device(int id, u32 device_flags);
@@ -155,7 +152,8 @@ void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host 
*host,
u32 dma_base, u32 len);
 int msm_dsi_host_enable(struct mipi_dsi_host *host);
 int msm_dsi_host_disable(struct mipi_dsi_host *host);
-int msm_dsi_host_power_on(struct mipi_dsi_host *host);
+int msm_dsi_host_power_on(struct mipi_dsi_host *host,
+   struct msm_dsi_phy_shared_timings *phy_shared_timings);
 int msm_dsi_host_power_off(struct mipi_dsi_host *host);
 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
struct drm_display_mode *mode);
@@ -167,6 +165,8 @@ struct drm_panel *msm_dsi_host_get_panel(struct 
mipi_dsi_host *host,
 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
struct msm_dsi_pll *src_pll);
 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host);
+void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
+   struct msm_dsi_phy_clk_request *clk_req);
 void msm_dsi_host_destroy(struct mipi_dsi_host *host);
 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
struct drm_device *dev);
@@ -179,10 +179,16 @@ struct msm_dsi_phy_shared_timings {
u32 clk_pre;
bool clk_pre_inc_by_2;
 };
+
+struct msm_dsi_phy_clk_request {
+   unsigned long bitclk_rate;
+   unsigned long escclk_rate;
+};
+
 void msm_dsi_phy_driver_register(void);
 void msm_dsi_phy_driver_unregister(void);
 int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
-   const unsigned long bit_rate, const unsigned long esc_rate);
+   struct msm_dsi_phy_clk_request *clk_req);
 void msm_dsi_phy_disable(struct msm_dsi_phy *phy);
 void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
struct msm_dsi_phy_shared_timings *shared_timing);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index b7fd952..9f9e419 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -2128,6 +2128,15 @@ void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
udelay(100);
 }

+void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
+   struct msm_dsi_phy_clk_request *clk_req)
+{
+   struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+
+   clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;
+   clk_req->escclk_rate = msm_host->esc_clk_rate;
+}
+
 int msm_dsi_host_enable(struct mipi_dsi_host *host)
 {
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
@@ -2175,10 +2184,10 @@ static void msm_dsi_sfpb_config(struct msm_dsi_host 
*msm_host, bool enable)
SFPB_GPREG_MASTER_PORT_EN(en));
 }

-int msm_dsi_host_power_on(struct mipi_dsi_host *host)
+int msm_dsi_host_power_on(struct mipi_dsi_host *host,
+   struct msm_dsi_phy_shared_timings *phy_shared_timings)
 {
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
-   struct msm_dsi_phy_shared_timings phy_shared_timings;
int ret = 0;

[PATCH 06/10] drm/msm/dsi: Reset both PHYs before clock operation for dual DSI

In case of dual DSI, some registers in PHY1 have been programmed
during PLL0 clock's set_rate. The PHY1 reset called by host1 later
will silently reset those PHY1 registers. This change is to reset
and enable both PHYs before any PLL clock operation.

[Originally worked on by Hai Li . Fixed up
by Archit Taneja ]

Signed-off-by: Archit Taneja 
---
 drivers/gpu/drm/msm/dsi/dsi.h |  1 +
 drivers/gpu/drm/msm/dsi/dsi_host.c| 25 +
 drivers/gpu/drm/msm/dsi/dsi_manager.c | 32 +---
 3 files changed, 43 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index d516fe2..9407a68 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -166,6 +166,7 @@ struct drm_panel *msm_dsi_host_get_panel(struct 
mipi_dsi_host *host,
 void msm_dsi_host_unregister(struct mipi_dsi_host *host);
 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
struct msm_dsi_pll *src_pll);
+void msm_dsi_host_reset_phy(struct mipi_dsi_host *host);
 void msm_dsi_host_destroy(struct mipi_dsi_host *host);
 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
struct drm_device *dev);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 6709701..b7fd952 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -691,17 +691,6 @@ static int dsi_calc_clk_rate(struct msm_dsi_host *msm_host)
return 0;
 }

-static void dsi_phy_sw_reset(struct msm_dsi_host *msm_host)
-{
-   DBG("");
-   dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
-   /* Make sure fully reset */
-   wmb();
-   udelay(1000);
-   dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
-   udelay(100);
-}
-
 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
 {
u32 intr;
@@ -2126,6 +2115,19 @@ int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host,
return ret;
 }

+void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
+{
+   struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+
+   DBG("");
+   dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
+   /* Make sure fully reset */
+   wmb();
+   udelay(1000);
+   dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
+   udelay(100);
+}
+
 int msm_dsi_host_enable(struct mipi_dsi_host *host)
 {
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
@@ -2206,7 +2208,6 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host)
goto fail_disable_reg;
}

-   dsi_phy_sw_reset(msm_host);
ret = msm_dsi_manager_phy_enable(msm_host->id,
msm_host->byte_clk_rate * 8,
msm_host->esc_clk_rate,
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index fbd11dc..0c7a631 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -660,13 +660,39 @@ int msm_dsi_manager_phy_enable(int id,
struct msm_dsi_phy_shared_timings *shared_timings)
 {
struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
+   struct msm_dsi *mdsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER);
+   struct msm_dsi *sdsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE);
struct msm_dsi_phy *phy = msm_dsi->phy;
int src_pll_id = IS_DUAL_DSI() ? DSI_CLOCK_MASTER : id;
int ret;

-   ret = msm_dsi_phy_enable(phy, src_pll_id, bit_rate, esc_rate);
-   if (ret)
-   return ret;
+   /* In case of dual DSI, some registers in PHY1 have been programmed
+* during PLL0 clock's set_rate. The PHY1 reset called by host1 here
+* will silently reset those PHY1 registers. Therefore we need to reset
+* and enable both PHYs before any PLL clock operation.
+*/
+   if (IS_DUAL_DSI() && mdsi && sdsi) {
+   if (!mdsi->phy_enabled && !sdsi->phy_enabled) {
+   msm_dsi_host_reset_phy(mdsi->host);
+   msm_dsi_host_reset_phy(sdsi->host);
+   ret = msm_dsi_phy_enable(mdsi->phy, src_pll_id,
+bit_rate, esc_rate);
+   if (ret)
+   return ret;
+   ret = msm_dsi_phy_enable(sdsi->phy, src_pll_id,
+bit_rate, esc_rate);
+   if (ret) {
+   msm_dsi_phy_disable(mdsi->phy);
+   return ret;
+   }
+   }
+   } else {
+   msm_dsi_host_reset_phy(msm_dsi->host);
+   ret = msm_dsi_phy_enable(msm_dsi->phy, src_pll_id, bit_rate,
+   esc_rate);
+

[PATCH 05/10] drm/msm/dsi: Pass down use case to PHY

From: Hai Li 

For some new types of DSI PHY, more settings depend on
use cases controlled by DSI manager. This change allows
DSI manager to setup PHY with a use case.

Signed-off-by: Hai Li 
Signed-off-by: Archit Taneja 
---
 drivers/gpu/drm/msm/dsi/dsi.h |  8 +++
 drivers/gpu/drm/msm/dsi/dsi_manager.c | 43 ---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 30 +++-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h |  1 +
 4 files changed, 52 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index f5e4ccf..d516fe2 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -37,6 +37,12 @@ enum msm_dsi_phy_type {
MSM_DSI_PHY_MAX
 };

+enum msm_dsi_phy_usecase {
+   MSM_DSI_PHY_STANDALONE,
+   MSM_DSI_PHY_MASTER,
+   MSM_DSI_PHY_SLAVE,
+};
+
 #define DSI_DEV_REGULATOR_MAX  8
 #define DSI_BUS_CLK_MAX4

@@ -180,6 +186,8 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int 
src_pll_id,
 void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
struct msm_dsi_phy_shared_timings *shared_timing);
 struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy);
+void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
+enum msm_dsi_phy_usecase uc);

 #endif /* __DSI_CONNECTOR_H__ */

diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c 
b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index ef186f1..fbd11dc 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -72,11 +72,12 @@ static int dsi_mgr_parse_dual_dsi(struct device_node *np, 
int id)
return 0;
 }

-static int dsi_mgr_host_register(int id)
+static int dsi_mgr_setup_components(int id)
 {
struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id);
struct msm_dsi *clk_master_dsi = dsi_mgr_get_dsi(DSI_CLOCK_MASTER);
+   struct msm_dsi *clk_slave_dsi = dsi_mgr_get_dsi(DSI_CLOCK_SLAVE);
struct msm_dsi_pll *src_pll;
int ret;

@@ -85,15 +86,16 @@ static int dsi_mgr_host_register(int id)
if (ret)
return ret;

+   msm_dsi_phy_set_usecase(msm_dsi->phy, MSM_DSI_PHY_STANDALONE);
src_pll = msm_dsi_phy_get_pll(msm_dsi->phy);
ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll);
} else if (!other_dsi) {
ret = 0;
} else {
-   struct msm_dsi *mdsi = IS_MASTER_DSI_LINK(id) ?
-   msm_dsi : other_dsi;
-   struct msm_dsi *sdsi = IS_MASTER_DSI_LINK(id) ?
-   other_dsi : msm_dsi;
+   struct msm_dsi *master_link_dsi = IS_MASTER_DSI_LINK(id) ?
+   msm_dsi : other_dsi;
+   struct msm_dsi *slave_link_dsi = IS_MASTER_DSI_LINK(id) ?
+   other_dsi : msm_dsi;
/* Register slave host first, so that slave DSI device
 * has a chance to probe, and do not block the master
 * DSI device's probe.
@@ -101,14 +103,18 @@ static int dsi_mgr_host_register(int id)
 * because only master DSI device adds the panel to global
 * panel list. The panel's device is the master DSI device.
 */
-   ret = msm_dsi_host_register(sdsi->host, false);
+   ret = msm_dsi_host_register(slave_link_dsi->host, false);
if (ret)
return ret;
-   ret = msm_dsi_host_register(mdsi->host, true);
+   ret = msm_dsi_host_register(master_link_dsi->host, true);
if (ret)
return ret;

/* PLL0 is to drive both 2 DSI link clocks in Dual DSI mode. */
+   msm_dsi_phy_set_usecase(clk_master_dsi->phy,
+   MSM_DSI_PHY_MASTER);
+   msm_dsi_phy_set_usecase(clk_slave_dsi->phy,
+   MSM_DSI_PHY_SLAVE);
src_pll = msm_dsi_phy_get_pll(clk_master_dsi->phy);
ret = msm_dsi_host_set_src_pll(msm_dsi->host, src_pll);
if (ret)
@@ -656,28 +662,12 @@ int msm_dsi_manager_phy_enable(int id,
struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
struct msm_dsi_phy *phy = msm_dsi->phy;
int src_pll_id = IS_DUAL_DSI() ? DSI_CLOCK_MASTER : id;
-   struct msm_dsi_pll *pll = msm_dsi_phy_get_pll(msm_dsi->phy);
int ret;

ret = msm_dsi_phy_enable(phy, src_pll_id, bit_rate, esc_rate);
if (ret)
return ret;

-   /*
-* Reset DSI PHY silently changes its PLL registers to reset status,
-* which will confuse clock driver and

[PATCH 04/10] drm/msm/dsi: Return more timings from PHY to host

From: Hai Li 

The DSI host is required to configure more timings calculated
in PHY. By introducing a shared structure, this change allows
more timing information passed from PHY to host.

Signed-off-by: Hai Li 
Signed-off-by: Archit Taneja 
---
 drivers/gpu/drm/msm/dsi/dsi.h | 13 ++---
 drivers/gpu/drm/msm/dsi/dsi_host.c| 20 +---
 drivers/gpu/drm/msm/dsi/dsi_manager.c |  4 ++--
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 29 ++---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h |  2 ++
 5 files changed, 41 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 81971b3..f5e4ccf 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -27,6 +27,8 @@
 #define DSI_1  1
 #define DSI_MAX2

+struct msm_dsi_phy_shared_timings;
+
 enum msm_dsi_phy_type {
MSM_DSI_PHY_28NM_HPM,
MSM_DSI_PHY_28NM_LP,
@@ -86,7 +88,7 @@ struct msm_dsi {
 struct drm_connector *msm_dsi_manager_ext_bridge_init(u8 id);
 int msm_dsi_manager_phy_enable(int id,
const unsigned long bit_rate, const unsigned long esc_rate,
-   u32 *clk_pre, u32 *clk_post);
+   struct msm_dsi_phy_shared_timings *shared_timing);
 void msm_dsi_manager_phy_disable(int id);
 int msm_dsi_manager_cmd_xfer(int id, const struct mipi_dsi_msg *msg);
 bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 dma_base, u32 len);
@@ -165,13 +167,18 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,

 /* dsi phy */
 struct msm_dsi_phy;
+struct msm_dsi_phy_shared_timings {
+   u32 clk_post;
+   u32 clk_pre;
+   bool clk_pre_inc_by_2;
+};
 void msm_dsi_phy_driver_register(void);
 void msm_dsi_phy_driver_unregister(void);
 int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
const unsigned long bit_rate, const unsigned long esc_rate);
 void msm_dsi_phy_disable(struct msm_dsi_phy *phy);
-void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy,
-   u32 *clk_pre, u32 *clk_post);
+void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
+   struct msm_dsi_phy_shared_timings *shared_timing);
 struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy);

 #endif /* __DSI_CONNECTOR_H__ */
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 210a44f..6709701 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -756,7 +756,7 @@ static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
 }

 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
-   u32 clk_pre, u32 clk_post)
+   struct msm_dsi_phy_shared_timings *phy_shared_timings)
 {
u32 flags = msm_host->mode_flags;
enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
@@ -819,10 +819,16 @@ static void dsi_ctrl_config(struct msm_dsi_host 
*msm_host, bool enable,
data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);

-   data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(clk_post) |
-   DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(clk_pre);
+   data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) |
+   DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre);
dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);

+   if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
+   (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) &&
+   phy_shared_timings->clk_pre_inc_by_2)
+   dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,
+ DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK);
+
data = 0;
if (!(flags & MIPI_DSI_MODE_EOT_PACKET))
data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
@@ -2170,7 +2176,7 @@ static void msm_dsi_sfpb_config(struct msm_dsi_host 
*msm_host, bool enable)
 int msm_dsi_host_power_on(struct mipi_dsi_host *host)
 {
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
-   u32 clk_pre = 0, clk_post = 0;
+   struct msm_dsi_phy_shared_timings phy_shared_timings;
int ret = 0;

mutex_lock(_host->dev_mutex);
@@ -2204,7 +2210,7 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host)
ret = msm_dsi_manager_phy_enable(msm_host->id,
msm_host->byte_clk_rate * 8,
msm_host->esc_clk_rate,
-   _pre, _post);
+   _shared_timings);
dsi_bus_clk_disable(msm_host);
if (ret) {
pr_err("%s: failed to enable phy, %d\n", __func__, ret);
@@ -2226,7 +2232,7 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host)

dsi_timing_setup(msm_host);
dsi_sw_reset(msm_host);
-

[PATCH 03/10] drm/msm/dsi: Add a PHY op that initializes version specific stuff

Create an init() op for dsi_phy which sets up things specific to
a given DSI PHY.

The dsi_phy driver probe expects every DSI version to get a
"dsi_phy_regulator" mmio base. This isn't the case for 8x96.
Creating an init() op will allow us to accommodate such
differences.

Signed-off-by: Archit Taneja 
---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c   | 33 ++---
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h   |  2 ++
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c  |  1 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c  |  2 ++
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c |  1 +
 5 files changed, 30 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index f39386e..03a3549 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -295,6 +295,24 @@ static int dsi_phy_get_id(struct msm_dsi_phy *phy)
return -EINVAL;
 }

+int msm_dsi_phy_init_common(struct msm_dsi_phy *phy)
+{
+   struct platform_device *pdev = phy->pdev;
+   int ret = 0;
+
+   phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
+   "DSI_PHY_REG");
+   if (IS_ERR(phy->reg_base)) {
+   dev_err(>dev, "%s: failed to map phy regulator base\n",
+   __func__);
+   ret = -ENOMEM;
+   goto fail;
+   }
+
+fail:
+   return ret;
+}
+
 static int dsi_phy_driver_probe(struct platform_device *pdev)
 {
struct msm_dsi_phy *phy;
@@ -331,15 +349,6 @@ static int dsi_phy_driver_probe(struct platform_device 
*pdev)
goto fail;
}

-   phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
-   "DSI_PHY_REG");
-   if (IS_ERR(phy->reg_base)) {
-   dev_err(dev, "%s: failed to map phy regulator base\n",
-   __func__);
-   ret = -ENOMEM;
-   goto fail;
-   }
-
ret = dsi_phy_regulator_init(phy);
if (ret) {
dev_err(dev, "%s: failed to init regulator\n", __func__);
@@ -353,6 +362,12 @@ static int dsi_phy_driver_probe(struct platform_device 
*pdev)
goto fail;
}

+   if (phy->cfg->ops.init) {
+   ret = phy->cfg->ops.init(phy);
+   if (ret)
+   goto fail;
+   }
+
/* PLL init will call into clk_register which requires
 * register access, so we need to enable power and ahb clock.
 */
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index f24a854..b9d7d02 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -22,6 +22,7 @@
 #define dsi_phy_write(offset, data) msm_writel((data), (offset))

 struct msm_dsi_phy_ops {
+   int (*init) (struct msm_dsi_phy *phy);
int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
const unsigned long bit_rate, const unsigned long esc_rate);
void (*disable)(struct msm_dsi_phy *phy);
@@ -87,6 +88,7 @@ int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing 
*timing,
const unsigned long bit_rate, const unsigned long esc_rate);
 void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
u32 bit_mask);
+int msm_dsi_phy_init_common(struct msm_dsi_phy *phy);

 #endif /* __DSI_PHY_H__ */

diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
index c757e20..c4a7be5 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
@@ -145,6 +145,7 @@ static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy)
.ops = {
.enable = dsi_20nm_phy_enable,
.disable = dsi_20nm_phy_disable,
+   .init = msm_dsi_phy_init_common,
},
.io_start = { 0xfd998300, 0xfd9a0300 },
.num_dsi_phy = 2,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
index 63d7fba..ea740c5 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c
@@ -144,6 +144,7 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
.ops = {
.enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable,
+   .init = msm_dsi_phy_init_common,
},
.io_start = { 0xfd922b00, 0xfd923100 },
.num_dsi_phy = 2,
@@ -161,6 +162,7 @@ static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
.ops = {
.enable = dsi_28nm_phy_enable,
.disable = dsi_28nm_phy_disable,
+   .init = msm_dsi_phy_init_common,
},
.io_start = { 0x1a98500 },
.num_dsi_phy = 1,
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c

[PATCH 02/10] drm/msm/dsi: Add 8x96 info in dsi_cfg

Add 8x96 DSI data in dsi_cfg. The downstream kernel's dsi_host driver
enables core_mmss_clk. We're seeing some branch clock warnings on
8x96 when enabling this. There doesn't seem to be any negative effect
with not enabling this clock, so use it once we figure out why we
get the warnings.

Signed-off-by: Archit Taneja 
---
 drivers/gpu/drm/msm/dsi/dsi_cfg.c | 25 +
 drivers/gpu/drm/msm/dsi/dsi_cfg.h |  1 +
 2 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c 
b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index 63436d8..a5d75c9 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -94,6 +94,30 @@
.num_dsi = 2,
 };

+/*
+ * TODO: core_mmss_clk fails to enable for some reason, but things work fine
+ * without it too. Figure out why it doesn't enable and uncomment below
+ */
+static const char * const dsi_8996_bus_clk_names[] = {
+   "mdp_core_clk", "iface_clk", "bus_clk", /* "core_mmss_clk", */
+};
+
+static const struct msm_dsi_config msm8996_dsi_cfg = {
+   .io_offset = DSI_6G_REG_SHIFT,
+   .reg_cfg = {
+   .num = 2,
+   .regs = {
+   {"vdda", 18160, 1 },/* 1.25 V */
+   {"vcca", 17000, 32 },   /* 0.925 V */
+   {"vddio", 10, 100 },/* 1.8 V */
+   },
+   },
+   .bus_clk_names = dsi_8996_bus_clk_names,
+   .num_bus_clks = ARRAY_SIZE(dsi_8996_bus_clk_names),
+   .io_start = { 0x994000, 0x996000 },
+   .num_dsi = 2,
+};
+
 static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
{MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064, _dsi_cfg},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0,
@@ -106,6 +130,7 @@
_apq8084_dsi_cfg},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3, _dsi_cfg},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1, _dsi_cfg},
+   {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1, _dsi_cfg},
 };

 const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h 
b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index eeacc323..00a5da2 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -24,6 +24,7 @@
 #define MSM_DSI_6G_VER_MINOR_V1_2  0x1002
 #define MSM_DSI_6G_VER_MINOR_V1_3  0x1003
 #define MSM_DSI_6G_VER_MINOR_V1_3_10x10030001
+#define MSM_DSI_6G_VER_MINOR_V1_4_10x10040001

 #define MSM_DSI_V2_VER_MINOR_8064  0x0

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[PATCH 01/10] drm/msm/dsi: Don't error if a DSI host doesn't have a device connected

The driver returns an error if a DSI DT node is populated, but no device
is connected to it or if the data-lane map isn't present. Ideally, such
a DSI node shouldn't be probed at all (i.e, its status should be set to
"disabled in DT"), but there isn't any harm in registering the DSI device
even if it doesn't have a bridge/panel connected to it.

Signed-off-by: Archit Taneja 
---
 drivers/gpu/drm/msm/dsi/dsi_host.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c 
b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 3538b73..210a44f 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1559,8 +1559,9 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host 
*msm_host,

prop = of_find_property(ep, "data-lanes", );
if (!prop) {
-   dev_dbg(dev, "failed to find data lane mapping\n");
-   return -EINVAL;
+   dev_dbg(dev,
+   "failed to find data lane mapping, using default\n");
+   return 0;
}

num_lanes = len / sizeof(u32);
@@ -1617,7 +1618,7 @@ static int dsi_host_parse_dt(struct msm_dsi_host 
*msm_host)
struct device *dev = _host->pdev->dev;
struct device_node *np = dev->of_node;
struct device_node *endpoint, *device_node;
-   int ret;
+   int ret = 0;

/*
 * Get the endpoint of the output port of the DSI host. In our case,
@@ -1641,8 +1642,7 @@ static int dsi_host_parse_dt(struct msm_dsi_host 
*msm_host)
/* Get panel node from the output port's endpoint data */
device_node = of_graph_get_remote_port_parent(endpoint);
if (!device_node) {
-   dev_err(dev, "%s: no valid device\n", __func__);
-   ret = -ENODEV;
+   dev_dbg(dev, "%s: no valid device\n", __func__);
goto err;
}

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[PATCH 00/10] drm/msm/dsi: Dual DSI and 8x96 PHY/PLL support

This set adds 8x96 PHY/PLL with Dual DSI mode supported too.

Dual DSI on 8x96 requires the DSI host/manager drivers to propagate
some usecase info to the PHY/PLL drivers. Hai Li had worked on
some patches in the past to implement this.

Tested on 8996 MTP Dual DSI panel, and with a LeMaker panel (single DSI)
on DB820c.

Archit Taneja (6):
  drm/msm/dsi: Don't error if a DSI host doesn't have a device connected
  drm/msm/dsi: Add 8x96 info in dsi_cfg
  drm/msm/dsi: Add a PHY op that initializes version specific stuff
  drm/msm/dsi: Reset both PHYs before clock operation for dual DSI
  drm/msm/dsi: Udpate generated headers for 14nm PHY and PLL
  drm/msm/dsi: Add PHY/PLL for 8x96

Hai Li (4):
  drm/msm/dsi: Return more timings from PHY to host
  drm/msm/dsi: Pass down use case to PHY
  drm/msm/dsi: Move PHY operations out of host
  drm/msm/dsi: Add new method to calculate 14nm PHY timings

 drivers/gpu/drm/msm/Kconfig |7 +
 drivers/gpu/drm/msm/Makefile|2 +
 drivers/gpu/drm/msm/dsi/dsi.h   |   46 +-
 drivers/gpu/drm/msm/dsi/dsi.xml.h   |  252 ++
 drivers/gpu/drm/msm/dsi/dsi_cfg.c   |   25 +
 drivers/gpu/drm/msm/dsi/dsi_cfg.h   |1 +
 drivers/gpu/drm/msm/dsi/dsi_host.c  |   95 +-
 drivers/gpu/drm/msm/dsi/dsi_manager.c   |  195 +++--
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c   |  238 -
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h   |   20 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c  |  168 
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c  |5 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c  |6 +-
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c |5 +-
 drivers/gpu/drm/msm/dsi/pll/dsi_pll.c   |   12 +
 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h   |   11 +
 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c  | 1067 +++
 17 files changed, 1985 insertions(+), 170 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c
 create mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c

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[Bug 99312] Long-running OpenCL kernels cause ring stalls and GPU lockups on Kabini

https://bugs.freedesktop.org/show_bug.cgi?id=99312

--- Comment #1 from John Bridgman  ---
If you have not already done so, try disabling the watchdog timer:


MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 1 = 10
seconds, 0 = disable)");
module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);

As part of HSA/ROC development we dropped the priority of compute work relative
to graphics which improved interactivity and *almost* eliminated timeouts
without having to disable the timer  - when I get back in the office I'll dig
up the changes. In the meantime, I think disabling the timer will do what you
need although you will still have sluggish graphics while long-running kernels
are active.

Lowering the priority of compute waves across the board won't be a fully
general solution because there are going to be some cases (eg Valve's recent
work with using high priority compute to improve VR smoothness) where compute
will need to be *higher* priority than graphics but it should cover most cases
other than "simultaneously running GROMACS and VR".

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[Bug 99312] Long-running OpenCL kernels cause ring stalls and GPU lockups on Kabini

https://bugs.freedesktop.org/show_bug.cgi?id=99312

Vedran MiletiÄ  changed:

   What|Removed |Added

   Hardware|Other   |x86-64 (AMD64)
   Severity|normal  |major
Version|13.0|git
 OS|All |Linux (All)

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[Bug 99312] Long-running OpenCL kernels cause ring stalls and GPU lockups on Kabini

https://bugs.freedesktop.org/show_bug.cgi?id=99312

Bug ID: 99312
   Summary: Long-running OpenCL kernels cause ring stalls and GPU
lockups on Kabini
   Product: Mesa
   Version: 13.0
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Gallium/radeonsi
  Assignee: dri-devel at lists.freedesktop.org
  Reporter: vedran at miletic.net
QA Contact: dri-devel at lists.freedesktop.org

Running long lasting OpenCL kernels (e.g. GROMACS with a system of many atoms)
using kernel 4.8.15, Mesa git, and LLVM git on Kabini APU:

vendor_id   : AuthenticAMD
cpu family  : 22
model   : 0
model name  : AMD Athlon(tm) 5350 APU with Radeon(tm) R3
stepping: 1
microcode   : 0x700010b

with GPU:

00:01.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc.
[AMD/ATI] Kabini [Radeon HD 8400 / R3 Series] [1002:9830]

causes GPU lockups like:

[338584.980657] radeon :00:01.0: ring 0 stalled for more than 10351msec
[338584.980811] radeon :00:01.0: GPU lockup (current fence id
0x000827c1 last fence id 0x000827c2 on ring 0)
[338585.484633] radeon :00:01.0: ring 0 stalled for more than 10855msec
[338585.484789] radeon :00:01.0: GPU lockup (current fence id
0x000827c1 last fence id 0x000827c2 on ring 0)
[338585.988632] radeon :00:01.0: ring 0 stalled for more than 11359msec
[338585.988787] radeon :00:01.0: GPU lockup (current fence id
0x000827c1 last fence id 0x000827c2 on ring 0)

Machine does not hang. This is reliably reproducible. Any other info I can
provide?

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[Bug 99311] [regression, radeonsi] Updating to 1edc53a66b breaks SDDM (white screen on launch)

https://bugs.freedesktop.org/show_bug.cgi?id=99311

Bug ID: 99311
   Summary: [regression,radeonsi] Updating to 1edc53a66b breaks
SDDM (white screen on launch)
   Product: Mesa
   Version: git
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Keywords: regression
  Severity: major
  Priority: medium
 Component: Drivers/Gallium/radeonsi
  Assignee: dri-devel at lists.freedesktop.org
  Reporter: kai at dev.carbon-project.org
QA Contact: dri-devel at lists.freedesktop.org

Somewhere between c93efb0a4f and 1edc53a66b a regression was introduced,
causing SDDM launching into a pure white screen instead of the login screen.
There's nothing logged to either /var/log/Xorg.0.log or /var/log/sddm.log and
dmesg is also clear. Downgrading to c93efb0a4f lets me login again.

I have not bisected yet, but maybe this information is already enough to find
the cause. For the full stack affected by this regression, please see below.

GPU: Hawaii PRO [Radeon R9 290] (ChipID = 0x67b1)
Mesa: Git:master/1edc53a66b + the modified version of attachment 127812
libdrm: 2.4.74-1
LLVM: SVN:trunk/r291276 (4.0 devel) +
<https://reviews.llvm.org/D26348?download=true>
X.Org: 2:1.19.0-3
Linux: 4.9.1
Firmware: 20161130-2
libclc: Git:master/b906699f68
DDX (amdgpu): 1.2.0-1+b1

Let me know, if you need anything else (besides a bisect).

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[PATCH] drm: add more document for drm_crtc_from_index()

2017-01-07 Thread Shawn Guo

From: Shawn Guo 

Add a bit more document for function drm_crtc_from_index() to cross
link it with drm_crtc_from_index(), and explain that the function is
useful in vblank code.

While at it, add cross link comment for drm_plane_from_index() as well.

Signed-off-by: Shawn Guo 
---
This is a follow-up patch to address Daniel's comment [1] on my patch
"[PATCH 1/3] drm: add crtc helper drm_crtc_from_index()".

Shawn

[1] http://www.spinics.net/lists/dri-devel/msg128062.html

 drivers/gpu/drm/drm_crtc.c  | 5 -
 drivers/gpu/drm/drm_plane.c | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 5c1bb1f34697..85a7452d0fb4 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -52,7 +52,10 @@
  * @idx: index of registered CRTC to find for
  *
  * Given a CRTC index, return the registered CRTC from DRM device's
- * list of CRTCs with matching index.
+ * list of CRTCs with matching index. This is the inverse of drm_crtc_index().
+ * It's useful in the vblank callbacks (like _driver.enable_vblank or
+ * _driver.disable_vblank), since that still deals with indices instead
+ * of pointers to  drm_crtc."
  */
 struct drm_crtc *drm_crtc_from_index(struct drm_device *dev, int idx)
 {
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index 62b98f386fd1..535dec4f508d 100644
--- a/drivers/gpu/drm/drm_plane.c
+++ b/drivers/gpu/drm/drm_plane.c
@@ -254,7 +254,7 @@ void drm_plane_cleanup(struct drm_plane *plane)
  * @idx: index of registered plane to find for
  *
  * Given a plane index, return the registered plane from DRM device's
- * list of planes with matching index.
+ * list of planes with matching index. This is the inverse of 
drm_plane_index().
  */
 struct drm_plane *
 drm_plane_from_index(struct drm_device *dev, int idx)
-- 
1.9.1

[Bug 99310] Ubuntu 16.04/16.10 AMD Radeonsi - wrong colors (oibaf ppa) in XFCE and eog.

https://bugs.freedesktop.org/show_bug.cgi?id=99310

mr.swaagger at mail.ru changed:

   What|Removed |Added

URL||https://imgur.com/a/A8LDW

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[PATCH] rnndb: dsi: Add DSI PHY 14nm domains

Add DSI PHY 14nm domains for DSI PHY common, DSI PHY lane and
DSI PLL registers. Used in MSM8996.

Signed-off-by: Archit Taneja 
---
 rnndb/dsi/dsi.xml | 128 ++
 1 file changed, 128 insertions(+)

diff --git a/rnndb/dsi/dsi.xml b/rnndb/dsi/dsi.xml
index 65d41a4..c705237 100644
--- a/rnndb/dsi/dsi.xml
+++ b/rnndb/dsi/dsi.xml
@@ -686,4 +686,132 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">

 

+
+   
+   
+   
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+   
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+   
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+   
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+   
+   
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+   
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+
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+   
+   
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+   
+   
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+   
+
+
 
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[Bug 99309] [radeonsi]glsl: Override the # of varying slots for ClipDistance and TessLevel*. broke chromium browser

https://bugs.freedesktop.org/show_bug.cgi?id=99309

--- Comment #1 from Arek RuÅniak  ---
Created attachment 128805
  --> https://bugs.freedesktop.org/attachment.cgi?id=128805=edit
chomium look

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[Bug 99310] Ubuntu 16.04/16.10 AMD Radeonsi - wrong colors (oibaf ppa) in XFCE and eog.

https://bugs.freedesktop.org/show_bug.cgi?id=99310

Bug ID: 99310
   Summary: Ubuntu 16.04/16.10 AMD Radeonsi - wrong colors (oibaf
ppa) in XFCE and eog.
   Product: Mesa
   Version: git
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Gallium/radeonsi
  Assignee: dri-devel at lists.freedesktop.org
  Reporter: mr.swaagger at mail.ru
QA Contact: dri-devel at lists.freedesktop.org

System:

AMD Phenom(tm) II X4 965

8 gigs of Ram

AMD GPU: Radeon HD 7870 GHz Edition


OS: Xubuntu 16.04 LTS/16.10

Screenshots first: 

https://imgur.com/a/A8LDW

This problem concerns the oibaf ppa. Note that this doesn't happen with the
padoka ppa. The problem occurs once I update the

libgbm1 

package from 

Installiert (16.04): 11.2.0-1ubuntu2.2

Installiert (16.10): 12.0.3-1ubuntu2

to the respective (current) version of the oibaf ppa (I figured this out by
installing/reinstalling etc.)

My hypothesis is that this is related to llvm 3.9 <-> llvm 4.0, but I'm not
sure.

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[Bug 99309] [radeonsi]glsl: Override the # of varying slots for ClipDistance and TessLevel*. broke chromium browser

https://bugs.freedesktop.org/show_bug.cgi?id=99309

Bug ID: 99309
   Summary: [radeonsi]glsl: Override the # of varying slots for
ClipDistance and TessLevel*. broke chromium browser
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Gallium/radeonsi
  Assignee: dri-devel at lists.freedesktop.org
  Reporter: arek.rusi at gmail.com
QA Contact: dri-devel at lists.freedesktop.org

Hi, after upgrade mesa-git chromium starts looking like garbage.
I've tested this on polaris and i965(haswell) and only radeon is infected
kernel - 4.9 or 4.10-drm-next-wip
mesa - from git
llvm - r291295
ddx - amdgpu-git

bisecting:

8b5749f65ac434961308ccb579fb8a816e4f29d5 is the first bad commit
commit 8b5749f65ac434961308ccb579fb8a816e4f29d5
Author: Kenneth Graunke 
Date:   Sun Nov 15 04:37:50 2015 -0800

glsl: Override the # of varying slots for ClipDistance and TessLevel*.

Right now, this shouldn't have any effect, as all drivers use
LowerClipDist and LowerTessFactors to turn the float[] arrays into
vectors.

However, it should help make it possible for drivers to avoid that
lowering.
me is the only issue for now
Signed-off-by: Kenneth Graunke 
Reviewed-by: Jason Ekstrand 
Reviewed-by: Timothy Arceri 

after reverting, browser works corectly

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[Bug 191281] [drm:amdgpu_ib_ring_tests] ERROR amdgpu: failed testing IB on ring 12 (-110)

2017-01-07 Thread bugzilla-dae...@bugzilla.kernel.org

https://bugzilla.kernel.org/show_bug.cgi?id=191281

--- Comment #2 from fin4478 at hotmail.com ---
Created attachment 250711
  --> https://bugzilla.kernel.org/attachment.cgi?id=250711=edit
dmesg output with RX460

I have same errors with Gigabyte RX460 and
~agd5f/linux/log/drivers/gpu/drm/amd?h=drm-next-4.10-wip kernel that I cloned
today. Computer seems to work normally, but booting is 3 seconds slower because
of this and cpu firmware bug traces.

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[drm-tip:drm-tip 476/492] include/video/vga.h:22:21: fatal error: asm/vga.h: No such file or directory

2017-01-07 Thread kbuild test robot

tree:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
head:   eb5c556a1e5eff388e48e4b7cf61e95783019e83
commit: 62a0d98a188cc4ebd8ea54b37d274ec20465e464 [476/492] drm: allow to use 
mmuless SoC
config: blackfin-allyesconfig (attached as .config)
compiler: bfin-uclinux-gcc (GCC) 6.2.0
reproduce:
wget 
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
 -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 62a0d98a188cc4ebd8ea54b37d274ec20465e464
# save the attached .config to linux build tree
make.cross ARCH=blackfin 

All errors (new ones prefixed by >>):

   In file included from include/linux/vgaarb.h:34:0,
from drivers/gpu/drm/drm_irq.c:42:
>> include/video/vga.h:22:21: fatal error: asm/vga.h: No such file or directory
#include 
^
   compilation terminated.

vim +22 include/video/vga.h

^1da177e4 Linus Torvalds2005-04-16   6   * Copyright history from vga16fb.c:
^1da177e4 Linus Torvalds2005-04-16   7   *  Copyright 1999 Ben Pfaff and 
Petr Vandrovec
c84e032e1 Justin P. Mattock 2010-08-14   8   *  Based on VGA info at 
http://www.osdever.net/FreeVGA/home.htm 
^1da177e4 Linus Torvalds2005-04-16   9   *  Based on VESA framebuffer (c) 
1998 Gerd Knorr
^1da177e4 Linus Torvalds2005-04-16  10   *
^1da177e4 Linus Torvalds2005-04-16  11   * This file is subject to the 
terms and conditions of the GNU General
^1da177e4 Linus Torvalds2005-04-16  12   * Public License.  See the file 
COPYING in the main directory of this
^1da177e4 Linus Torvalds2005-04-16  13   * archive for more details.  
^1da177e4 Linus Torvalds2005-04-16  14   *
^1da177e4 Linus Torvalds2005-04-16  15   */
^1da177e4 Linus Torvalds2005-04-16  16  
^1da177e4 Linus Torvalds2005-04-16  17  #ifndef __linux_video_vga_h__
^1da177e4 Linus Torvalds2005-04-16  18  #define __linux_video_vga_h__
^1da177e4 Linus Torvalds2005-04-16  19  
^1da177e4 Linus Torvalds2005-04-16  20  #include 
2584cf835 Dan Williams  2015-08-10  21  #include 
^1da177e4 Linus Torvalds2005-04-16 @22  #include 
^1da177e4 Linus Torvalds2005-04-16  23  #include 
^1da177e4 Linus Torvalds2005-04-16  24  
^1da177e4 Linus Torvalds2005-04-16  25  
^1da177e4 Linus Torvalds2005-04-16  26  /* Some of the code below is taken 
from SVGAlib.  The original,
^1da177e4 Linus Torvalds2005-04-16  27 unmodified copyright notice for 
that code is below. */
^1da177e4 Linus Torvalds2005-04-16  28  /* VGAlib version 1.2 - (c) 1993 
Tommy Frandsen*/
^1da177e4 Linus Torvalds2005-04-16  29  /*  
   */
^1da177e4 Linus Torvalds2005-04-16  30  /* This library is free software; 
you can redistribute it and/or   */

:: The code at line 22 was first introduced by commit
:: 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 Linux-2.6.12-rc2

:: TO: Linus Torvalds 
:: CC: Linus Torvalds 

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation
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[Bug 97116] mpv needs VAAPI_DISABLE_INTERLACE=1 for swdecode -vo vaapi since st/va: add conversion for yv12 to nv12in putimage v2

https://bugs.freedesktop.org/show_bug.cgi?id=97116

--- Comment #1 from Andy Furniss  ---
Old bug - mpv --vo=vaapi is unstable with or without the env on current head
and may well have only lucked into apparently working with
VAAPI_DISABLE_INTERLACE=1
all along.

Will open new bug soon(ish).

Reverting this commit from head and running with VAAPI_DISABLE_INTERLACE=0
seems stable.

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[PATCH] drm: fix compilations issues introduced by "drm: allow to use mmuless SoC"

2017-01-07 Thread Benjamin Gaignard

Removing MMU configuration flag from DRM make few automatic
build failed when they answer yes to all flags.

Add asm/vga.h file on Blackfin architecture to not broke compilation.

Signed-off-by: Benjamin Gaignard 
---
 arch/blackfin/include/asm/vga.h | 1 +
 drivers/gpu/drm/Kconfig | 4 ++--
 drivers/gpu/drm/ast/Kconfig | 2 +-
 drivers/gpu/drm/bochs/Kconfig   | 2 +-
 drivers/gpu/drm/cirrus/Kconfig  | 2 +-
 drivers/gpu/drm/gma500/Kconfig  | 2 +-
 drivers/gpu/drm/hisilicon/hibmc/Kconfig | 2 +-
 drivers/gpu/drm/mgag200/Kconfig | 2 +-
 drivers/gpu/drm/nouveau/Kconfig | 2 +-
 drivers/gpu/drm/qxl/Kconfig | 2 +-
 drivers/gpu/drm/virtio/Kconfig  | 2 +-
 drivers/gpu/drm/vmwgfx/Kconfig  | 2 +-
 12 files changed, 13 insertions(+), 12 deletions(-)
 create mode 100644 arch/blackfin/include/asm/vga.h

diff --git a/arch/blackfin/include/asm/vga.h b/arch/blackfin/include/asm/vga.h
new file mode 100644
index 000..89d82fd
--- /dev/null
+++ b/arch/blackfin/include/asm/vga.h
@@ -0,0 +1 @@
+#include 
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 505ca1d..6f3f9e6 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -146,7 +146,7 @@ source "drivers/gpu/drm/arm/Kconfig"

 config DRM_RADEON
tristate "ATI Radeon"
-   depends on DRM && PCI
+   depends on DRM && PCI && MMU
select FW_LOADER
 select DRM_KMS_HELPER
 select DRM_TTM
@@ -166,7 +166,7 @@ source "drivers/gpu/drm/radeon/Kconfig"

 config DRM_AMDGPU
tristate "AMD GPU"
-   depends on DRM && PCI
+   depends on DRM && PCI && MMU
select FW_LOADER
 select DRM_KMS_HELPER
 select DRM_TTM
diff --git a/drivers/gpu/drm/ast/Kconfig b/drivers/gpu/drm/ast/Kconfig
index 15f6ce7..9647e1f 100644
--- a/drivers/gpu/drm/ast/Kconfig
+++ b/drivers/gpu/drm/ast/Kconfig
@@ -1,6 +1,6 @@
 config DRM_AST
tristate "AST server chips"
-   depends on DRM && PCI
+   depends on DRM && PCI && MMU
select DRM_TTM
select DRM_KMS_HELPER
select DRM_TTM
diff --git a/drivers/gpu/drm/bochs/Kconfig b/drivers/gpu/drm/bochs/Kconfig
index f739763..bd27180 100644
--- a/drivers/gpu/drm/bochs/Kconfig
+++ b/drivers/gpu/drm/bochs/Kconfig
@@ -1,6 +1,6 @@
 config DRM_BOCHS
tristate "DRM Support for bochs dispi vga interface (qemu stdvga)"
-   depends on DRM && PCI
+   depends on DRM && PCI && MMU
select DRM_KMS_HELPER
select DRM_TTM
help
diff --git a/drivers/gpu/drm/cirrus/Kconfig b/drivers/gpu/drm/cirrus/Kconfig
index 04b3c16..ca38098 100644
--- a/drivers/gpu/drm/cirrus/Kconfig
+++ b/drivers/gpu/drm/cirrus/Kconfig
@@ -1,6 +1,6 @@
 config DRM_CIRRUS_QEMU
tristate "Cirrus driver for QEMU emulated device"
-   depends on DRM && PCI
+   depends on DRM && PCI && MMU
select DRM_KMS_HELPER
select DRM_TTM
help
diff --git a/drivers/gpu/drm/gma500/Kconfig b/drivers/gpu/drm/gma500/Kconfig
index 8906d67..df11582 100644
--- a/drivers/gpu/drm/gma500/Kconfig
+++ b/drivers/gpu/drm/gma500/Kconfig
@@ -1,6 +1,6 @@
 config DRM_GMA500
tristate "Intel GMA5/600 KMS Framebuffer"
-   depends on DRM && PCI && X86
+   depends on DRM && PCI && X86 && MMU
select DRM_KMS_HELPER
select DRM_TTM
# GMA500 depends on ACPI_VIDEO when ACPI is enabled, just like i915
diff --git a/drivers/gpu/drm/hisilicon/hibmc/Kconfig 
b/drivers/gpu/drm/hisilicon/hibmc/Kconfig
index 380622a..c7129dc 100644
--- a/drivers/gpu/drm/hisilicon/hibmc/Kconfig
+++ b/drivers/gpu/drm/hisilicon/hibmc/Kconfig
@@ -1,6 +1,6 @@
 config DRM_HISI_HIBMC
tristate "DRM Support for Hisilicon Hibmc"
-   depends on DRM && PCI
+   depends on DRM && PCI && MMU
select DRM_KMS_HELPER
select DRM_TTM

diff --git a/drivers/gpu/drm/mgag200/Kconfig b/drivers/gpu/drm/mgag200/Kconfig
index 520e5e6..db58578 100644
--- a/drivers/gpu/drm/mgag200/Kconfig
+++ b/drivers/gpu/drm/mgag200/Kconfig
@@ -1,6 +1,6 @@
 config DRM_MGAG200
tristate "Kernel modesetting driver for MGA G200 server engines"
-   depends on DRM && PCI
+   depends on DRM && PCI && MMU
select DRM_KMS_HELPER
select DRM_TTM
help
diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig
index 0f2f0af..c02a134 100644
--- a/drivers/gpu/drm/nouveau/Kconfig
+++ b/drivers/gpu/drm/nouveau/Kconfig
@@ -1,6 +1,6 @@
 config DRM_NOUVEAU
tristate "Nouveau (NVIDIA) cards"
-   depends on DRM && PCI
+   depends on DRM && PCI && MMU
 select FW_LOADER
select DRM_KMS_HELPER
select DRM_TTM
diff --git a/drivers/gpu/drm/qxl/Kconfig b/drivers/gpu/drm/qxl/Kconfig
index da45b11..378da59 100644
--- a/drivers/gpu/drm/qxl/Kconfig
+++ b/drivers/gpu/drm/qxl/Kconfig
@@ -1,6 +1,6 @@
 config DRM_QXL
tristate "QXL virtual GPU"
-   depends on DRM && PCI
+   depends on

[Bug 99236] System (seems to) completely freeze when interacting with java swing applications.

https://bugs.freedesktop.org/show_bug.cgi?id=99236

--- Comment #8 from Vitaly Ostrosablin  ---
Attempted to run reproducer app in Xephyr. It appears exactly like on host with
Java 8 in attached screenshot. I.e. with white button. However, clicking the
button just adds the text into textarea, as programmed, while doing this
directly on host's Xorg hangs the system.

I think it's possible that app alone is not enough to reproduce the issue, KDE
and it's window manager might be at play here, too. But it's strange, because
this seems to occur on adding text to JTextArea, which is rendered by Swing and
should be least affected by WM and DE (except for window border, which is
absent in Xephyr, since no WM runs there).

But if that's mesa-only bug, shouldn't Ctrl+Alt+F1 work? Here GPU appears to
have stopped output completely (most likely, fullscreen tty opens, but GPU
shows same picture as on moment of freeze).

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[Bug 99236] System (seems to) completely freeze when interacting with java swing applications.

https://bugs.freedesktop.org/show_bug.cgi?id=99236

--- Comment #7 from Vitaly Ostrosablin  ---
Created attachment 128804
  --> https://bugs.freedesktop.org/attachment.cgi?id=128804=edit
Comparison of reproducer app under java 8 and java 7 with git mesa

Checked out two days old revision of mesa. Attached screenshot of what I meant
about reproducer app.

Will try running it in Xephyr.

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[Bug 99236] System (seems to) completely freeze when interacting with java swing applications.

https://bugs.freedesktop.org/show_bug.cgi?id=99236

--- Comment #6 from Vitaly Ostrosablin  ---
Yes, no problem. However, my XOrg was compiled without Xephyr, so I rebuilt it.
Unfortunately, I've decided to update mesa to latest commit as well, but it
seems that one of recent commits breaks everything (I get an unusable desktop
which looks white and can see gray outlines of KDE taskbar, mouse cursor and
login password box cursor). So, I had to temporarily revert to 13.0.3 mesa. But
there some useful info. First, on 13.0.3 I cannot reproduce fault with
reproducer app. Second, reproducer app looks same under 13.0.3 both on Java 7
and Java 8. I found it strange that under Java 7 swing app looks like it should
(Metal look & feel) and under Java 8 it looked different (white buttons instead
of default metallic). But it appears that this was just a rendering artefact.

I will try to get back to working mesa commit and reproduce the problem with
Xephyr now.

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[PATCH] drm/vc4: Fix memory leak of the CRTC state.

2017-01-07 Thread Stefan Wahren

Hi Eric,

could you please resend this patch [1], because it's still not applied in Linux 
4.10-rc2.

Thanks
Stefan

[1] - https://patchwork.kernel.org/patch/9369793/

[PATCH v6] drm: allow to use mmuless SoC

2017-01-07 Thread Daniel Vetter

On Sat, Jan 7, 2017 at 9:57 AM, Benjamin Gaignard
 wrote:
> Some SoC without MMU have display driver where a drm/kms driver
> could be implemented.
>
> Before doing such kind of thing drm/kms must allow to use mmuless devices.
> This patch propose to remove MMU configuration flag.
>
> For all drivers selecting DRM_TTM add a dependency on MMU.
>
> For blackfin architecture add asm/vga.h file to avoid compilation
> issue with Kbuild with blackfin-allyesconfig config.
>
> version 4:
> - add documentation about drm_gem_cma_get_unmapped_area()
> - stub it MMU case
>
> version 5:
> - Make all drivers that select DRM_TTM depends on MMU
>
> version 6:
> - Add asm/vga.h for Blackfin architecture
>
> Signed-off-by: Benjamin Gaignard 
> [danvet: Use recommended struct member references in kernel-doc.]
> Signed-off-by: Daniel Vetter 
> Link: 
> http://patchwork.freedesktop.org/patch/msgid/1483521177-21794-4-git-send-email-benjamin.gaignard
>  at linaro.org

dmr-misc is non-rebasing, which means I need fixup patches, no new versions.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

[PATCH v6] drm: allow to use mmuless SoC

2017-01-07 Thread Benjamin Gaignard

Some SoC without MMU have display driver where a drm/kms driver
could be implemented.

Before doing such kind of thing drm/kms must allow to use mmuless devices.
This patch propose to remove MMU configuration flag.

For all drivers selecting DRM_TTM add a dependency on MMU.

For blackfin architecture add asm/vga.h file to avoid compilation
issue with Kbuild with blackfin-allyesconfig config.

version 4:
- add documentation about drm_gem_cma_get_unmapped_area()
- stub it MMU case

version 5:
- Make all drivers that select DRM_TTM depends on MMU

version 6:
- Add asm/vga.h for Blackfin architecture

Signed-off-by: Benjamin Gaignard 
[danvet: Use recommended struct member references in kernel-doc.]
Signed-off-by: Daniel Vetter 
Link: 
http://patchwork.freedesktop.org/patch/msgid/1483521177-21794-4-git-send-email-benjamin.gaignard
 at linaro.org
---
 Documentation/gpu/drm-mm.rst| 11 +
 arch/blackfin/include/asm/vga.h |  1 +
 drivers/gpu/drm/Kconfig |  8 ++--
 drivers/gpu/drm/ast/Kconfig |  2 +-
 drivers/gpu/drm/bochs/Kconfig   |  2 +-
 drivers/gpu/drm/cirrus/Kconfig  |  2 +-
 drivers/gpu/drm/drm_gem_cma_helper.c| 71 +
 drivers/gpu/drm/gma500/Kconfig  |  2 +-
 drivers/gpu/drm/hisilicon/hibmc/Kconfig |  2 +-
 drivers/gpu/drm/mgag200/Kconfig |  2 +-
 drivers/gpu/drm/nouveau/Kconfig |  2 +-
 drivers/gpu/drm/qxl/Kconfig |  2 +-
 drivers/gpu/drm/virtio/Kconfig  |  2 +-
 drivers/gpu/drm/vmwgfx/Kconfig  |  2 +-
 include/drm/drm_gem_cma_helper.h| 17 
 15 files changed, 114 insertions(+), 14 deletions(-)
 create mode 100644 arch/blackfin/include/asm/vga.h

diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst
index d3c6d77..1ea94fc 100644
--- a/Documentation/gpu/drm-mm.rst
+++ b/Documentation/gpu/drm-mm.rst
@@ -310,6 +310,17 @@ created.
 Drivers that want to map the GEM object upfront instead of handling page
 faults can implement their own mmap file operation handler.

+For platforms without MMU the GEM core provides a helper method
+:c:func:`drm_gem_cma_get_unmapped_area`. The mmap() routines will call
+this to get a proposed address for the mapping.
+
+To use :c:func:`drm_gem_cma_get_unmapped_area`, drivers must fill the
+struct :c:type:`struct file_operations ` get_unmapped_area
+field with a pointer on :c:func:`drm_gem_cma_get_unmapped_area`.
+
+More detailed information about get_unmapped_area can be found in
+Documentation/nommu-mmap.txt
+
 Memory Coherency
 

diff --git a/arch/blackfin/include/asm/vga.h b/arch/blackfin/include/asm/vga.h
new file mode 100644
index 000..89d82fd
--- /dev/null
+++ b/arch/blackfin/include/asm/vga.h
@@ -0,0 +1 @@
+#include 
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index d56b85c..6f3f9e6 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -6,7 +6,7 @@
 #
 menuconfig DRM
tristate "Direct Rendering Manager (XFree86 4.1.0 and higher DRI 
support)"
-   depends on (AGP || AGP=n) && !EMULATED_CMPXCHG && MMU && HAS_DMA
+   depends on (AGP || AGP=n) && !EMULATED_CMPXCHG && HAS_DMA
select HDMI
select FB_CMDLINE
select I2C
@@ -113,7 +113,7 @@ config DRM_LOAD_EDID_FIRMWARE

 config DRM_TTM
tristate
-   depends on DRM
+   depends on DRM && MMU
help
  GPU memory management subsystem for devices with multiple
  GPU memory types. Will be enabled automatically if a device driver
@@ -146,7 +146,7 @@ source "drivers/gpu/drm/arm/Kconfig"

 config DRM_RADEON
tristate "ATI Radeon"
-   depends on DRM && PCI
+   depends on DRM && PCI && MMU
select FW_LOADER
 select DRM_KMS_HELPER
 select DRM_TTM
@@ -166,7 +166,7 @@ source "drivers/gpu/drm/radeon/Kconfig"

 config DRM_AMDGPU
tristate "AMD GPU"
-   depends on DRM && PCI
+   depends on DRM && PCI && MMU
select FW_LOADER
 select DRM_KMS_HELPER
 select DRM_TTM
diff --git a/drivers/gpu/drm/ast/Kconfig b/drivers/gpu/drm/ast/Kconfig
index 15f6ce7..9647e1f 100644
--- a/drivers/gpu/drm/ast/Kconfig
+++ b/drivers/gpu/drm/ast/Kconfig
@@ -1,6 +1,6 @@
 config DRM_AST
tristate "AST server chips"
-   depends on DRM && PCI
+   depends on DRM && PCI && MMU
select DRM_TTM
select DRM_KMS_HELPER
select DRM_TTM
diff --git a/drivers/gpu/drm/bochs/Kconfig b/drivers/gpu/drm/bochs/Kconfig
index f739763..bd27180 100644
--- a/drivers/gpu/drm/bochs/Kconfig
+++ b/drivers/gpu/drm/bochs/Kconfig
@@ -1,6 +1,6 @@
 config DRM_BOCHS
tristate "DRM Support for bochs dispi vga interface (qemu stdvga)"
-   depends on DRM && PCI
+   depends on DRM && PCI && MMU
select DRM_KMS_HELPER
select DRM_TTM
help
diff --git a/drivers/gpu/drm/cirrus/Kconfig b/drivers/gpu/drm/cirrus/Kconfig
index 04b3c16..ca38098 100644
---

[Bug 99195] Random GPU lockup on Fedora 25 Wayland & X sessions with Mobility Radeon HD 5650/5750 Opensource drivers

https://bugs.freedesktop.org/show_bug.cgi?id=99195

--- Comment #4 from Michel DÃ¤nzer  ---
Any chance you can bisect Mesa?

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[PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
must be programmed.
Enable bit 12 for programmable header packet.
Enable bit 15 for Y cordinate support.

v2: (Rodrigo)
- move CHICKEN_TRANS_EDP bit set logic right after setup_vsc

v3:(Rodrigo)
- initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0

v4:(Rodrigo)
- initialize chicken_trans=0,add chicken_trans=CHICKEN_TRANS_BIT12

Cc: Rodrigo Vivi 
Cc: Jim Bride 
Signed-off-by: vathsala nagaraju 
Signed-off-by: Patil Deepti 
---
 drivers/gpu/drm/i915/i915_reg.h  | 7 +++
 drivers/gpu/drm/i915/intel_psr.c | 7 +++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7830e6e..5ca506a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6449,6 +6449,13 @@ enum {
 #define  BDW_DPRS_MASK_VBLANK_SRD  (1 << 0)
 #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, 
_CHICKEN_PIPESL_1_B)

+#define CHICKEN_TRANS_A 0x420c0
+#define CHICKEN_TRANS_B 0x420c4
+#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, 
CHICKEN_TRANS_B)
+#define TRANS_EDP  3
+#define CHICKEN_TRANS_BIT12(1<<12)
+#define CHICKEN_TRANS_BIT15(1<<15)
+
 #define DISP_ARB_CTL   _MMIO(0x45000)
 #define  DISP_FBC_MEMORY_WAKE  (1<<31)
 #define  DISP_TILE_SURFACE_SWIZZLING   (1<<13)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 7020f42..b804066 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -475,6 +475,7 @@ void intel_psr_enable(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dig_port->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
+   uint32_t chicken_trans = 0;

if (!HAS_PSR(dev_priv)) {
DRM_DEBUG_KMS("PSR not supported on this platform\n");
@@ -505,6 +506,12 @@ void intel_psr_enable(struct intel_dp *intel_dp)
dev_priv->psr.psr2_support = false;
else
skl_psr_setup_su_vsc(intel_dp);
+   /* Set CHICKEN_TRANS_BIT12 for programable header */
+   chicken_trans = CHICKEN_TRANS_BIT12;
+   /* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported 
*/
+   if (dev_priv->psr.y_cord_support)
+   chicken_trans |= CHICKEN_TRANS_BIT15;
+   I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
} else {
/* set up vsc header for psr1 */
hsw_psr_setup_vsc(intel_dp);
-- 
1.9.1

[Bug 99236] System (seems to) completely freeze when interacting with java swing applications.

https://bugs.freedesktop.org/show_bug.cgi?id=99236

Michel DÃ¤nzer  changed:

   What|Removed |Added

  Component|DRM/AMDgpu  |Drivers/Gallium/radeonsi
Product|DRI |Mesa
 QA Contact||dri-devel at lists.freedesktop
   ||.org
Version|DRI git |unspecified

--- Comment #5 from Michel DÃ¤nzer  ---
It's most likely a Mesa driver issue.

Can you try running Xephyr something like this:

 GALLIUM_DDEBUG="pipelined 2000" Xephyr :99 -glamor -screen 1024x768

and then run the reproducer app with DISPLAY=:99 . After the hang, a file
should appear in ~/ddebug_dumps/. Please attach that file here.

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Re: [PATCH V7 1/4] Documentation/devicetree/bindings: b850v3_lvds_dp

2017-01-07 Thread Peter Senna Tschudin


On 04 January, 2017 21:39 CET, Rob Herring  wrote: 

> On Tue, Jan 3, 2017 at 5:34 PM, Peter Senna Tschudin
>  wrote:
> >  Hi Rob,
> >
> > Thank you for the review.
> >
> > On 03 January, 2017 23:51 CET, Rob Herring  wrote:
> >
> >> On Sun, Jan 01, 2017 at 09:24:29PM +0100, Peter Senna Tschudin wrote:
> >> > Devicetree bindings documentation for the GE B850v3 LVDS/DP++
> >> > display bridge.
> >> >
> >> > Cc: Martyn Welch 
> >> > Cc: Martin Donnelly 
> >> > Cc: Javier Martinez Canillas 
> >> > Cc: Enric Balletbo i Serra 
> >> > Cc: Philipp Zabel 
> >> > Cc: Rob Herring 
> >> > Cc: Fabio Estevam 
> >> > Signed-off-by: Peter Senna Tschudin 
> >> > ---
> >> > There was an Acked-by from Rob Herring  for V6, but 
> >> > I changed
> >> > the bindings to use i2c_new_secondary_device() so I removed it from the 
> >> > commit
> >> > message.
> >> >
> >> >  .../devicetree/bindings/ge/b850v3-lvds-dp.txt  | 39 
> >> > ++
> >>
> >> Generally, bindings are not organized by vendor. Put in
> >> bindings/display/bridge/... instead.
> >
> > Will change that.
> >
> >>
> >> >  1 file changed, 39 insertions(+)
> >> >  create mode 100644 
> >> > Documentation/devicetree/bindings/ge/b850v3-lvds-dp.txt
> >> >
> >> > diff --git a/Documentation/devicetree/bindings/ge/b850v3-lvds-dp.txt 
> >> > b/Documentation/devicetree/bindings/ge/b850v3-lvds-dp.txt
> >> > new file mode 100644
> >> > index 000..1bc6ebf
> >> > --- /dev/null
> >> > +++ b/Documentation/devicetree/bindings/ge/b850v3-lvds-dp.txt
> >> > @@ -0,0 +1,39 @@
> >> > +Driver for GE B850v3 LVDS/DP++ display bridge
> >> > +
> >> > +Required properties:
> >> > +  - compatible : should be "ge,b850v3-lvds-dp".
> >>
> >> Isn't '-lvds-dp' redundant? The part# should be enough.
> >
> > b850v3 is the name of the product, this is why the proposed name. What 
> > about, b850v3-dp2 dp2 indicating the second DP output?
> 
> Humm, b850v3 is the board name? This node should be the name of the bridge 
> chip.

>From the cover letter:

-- // --
There are two physical bridges on the video signal pipeline: a STDP4028(LVDS to
DP) and a STDP2690(DP to DP++).  The hardware and firmware made it complicated
for this binding to comprise two device tree nodes, as the design goal is to
configure both bridges based on the LVDS signal, which leave the driver
powerless to control the video processing pipeline. The two bridges behaves as
a single bridge, and the driver is only needed for telling the host about EDID /
HPD, and for giving the host powers to ack interrupts. The video signal
pipeline is as follows:

  Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
-- // --

[PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep

Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
should report value 8 , if system enters deep sleep state.

Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
flickering is observed on psr2 panel.

v2: (Ilia Mirkin)
- Remove duplicate bit definition 25:27

v3: rebase

v4: rebase

Cc: Rodrigo Vivi 
Cc: Jim Bride 
Signed-off-by: Vathsala Nagaraju 
Signed-off-by: Patil Deepti 
Reviewed-by: Jim Bride 
---
 drivers/gpu/drm/i915/i915_reg.h  | 10 +++---
 drivers/gpu/drm/i915/intel_psr.c | 29 -
 2 files changed, 27 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5ca506a..272a283 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3597,9 +3597,12 @@ enum {
 #define   EDP_PSR_PERF_CNT_MASK0xff

 #define EDP_PSR_DEBUG_CTL  _MMIO(dev_priv->psr_mmio_base + 0x60)
-#define   EDP_PSR_DEBUG_MASK_LPSP  (1<<27)
-#define   EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
-#define   EDP_PSR_DEBUG_MASK_HPD   (1<<25)
+#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP (1<<28)
+#define   EDP_PSR_DEBUG_MASK_LPSP  (1<<27)
+#define   EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
+#define   EDP_PSR_DEBUG_MASK_HPD   (1<<25)
+#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE(1<<16)
+#define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)

 #define EDP_PSR2_CTL   _MMIO(0x6f900)
 #define   EDP_PSR2_ENABLE  (1<<31)
@@ -3614,6 +3617,7 @@ enum {
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK(0xf<<4)
 #define   EDP_PSR2_IDLE_MASK   0xf
+#define   EDP_FRAMES_BEFORE_SU_ENTRY   (1<<4)

 #define EDP_PSR2_STATUS_CTL_MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 7573c2f..fd151b9 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -338,7 +338,9 @@ static void intel_enable_source_psr2(struct intel_dp 
*intel_dp)
/* FIXME: selective update is probably totally broken because it doesn't
 * mesh at all with our frontbuffer tracking. And the hw alone isn't
 * good enough. */
-   val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE;
+   val |= EDP_PSR2_ENABLE |
+   EDP_SU_TRACK_ENABLE |
+   EDP_FRAMES_BEFORE_SU_ENTRY;

if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR2_TP2_TIME_2500;
@@ -511,18 +513,27 @@ void intel_psr_enable(struct intel_dp *intel_dp)
if (dev_priv->psr.y_cord_support)
chicken_trans |= CHICKEN_TRANS_BIT15;
I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
+   I915_WRITE(EDP_PSR_DEBUG_CTL,
+  EDP_PSR_DEBUG_MASK_MEMUP |
+  EDP_PSR_DEBUG_MASK_HPD |
+  EDP_PSR_DEBUG_MASK_LPSP |
+  EDP_PSR_DEBUG_MASK_MAX_SLEEP |
+  EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
} else {
/* set up vsc header for psr1 */
hsw_psr_setup_vsc(intel_dp);
+   /*
+* Per Spec: Avoid continuous PSR exit by masking MEMUP
+* and HPD. also mask LPSP to avoid dependency on other
+* drivers that might block runtime_pm besides
+* preventing  other hw tracking issues now we can rely
+* on frontbuffer tracking.
+*/
+   I915_WRITE(EDP_PSR_DEBUG_CTL,
+  EDP_PSR_DEBUG_MASK_MEMUP |
+  EDP_PSR_DEBUG_MASK_HPD |
+  EDP_PSR_DEBUG_MASK_LPSP);
}
-   /*
-* Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD.
-* Also mask LPSP to avoid dependency on other drivers that
-* might block runtime_pm besides preventing other hw tracking
-* issues now we can rely on frontbuffer tracking.
-*/
-   I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
-  EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);

/* Enable PSR on the panel */
hsw_psr_enable_sink(intel_dp);
-- 
1.9.1

[PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2