On Tue, 11 May 2021 at 07:18, Bjorn Andersson
wrote:
>
> Some hardware supports clocking 2 pixels per pixel clock pulse, known as
> "widebus". The configuration needs to match between the DPU and the
> interface controller, and the timing parameters must be adjusted.
>
> As a first step towards supporting this, start by adding a INTF mask
> flag to signal the timing configuration code that the INTF_CONFIG2
> register should be written - which will clear the bit, in the case that
> the bootloader left it set.
>
> Signed-off-by: Bjorn Andersson
Reviewed-by: Dmitry Baryshkov
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c| 3 ++-
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 4dfd8a20ad5c..c2f34a4f82d9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -196,12 +196,14 @@ enum {
> * @DPU_INTF_TE INTF block has TE configuration support
> * @DPU_DATA_HCTL_ENAllows data to be transferred at different
> rate
> than video timing
> + * @DPU_INTF_WIDEBUSINTF block supports driving 2 pixels per
> clock
> * @DPU_INTF_MAX
> */
> enum {
> DPU_INTF_INPUT_CTRL = 0x1,
> DPU_INTF_TE,
> DPU_DATA_HCTL_EN,
> + DPU_INTF_WIDEBUS,
> DPU_INTF_MAX
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> index 1599e3f49a4f..933485d8c03c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> @@ -183,7 +183,6 @@ static void dpu_hw_intf_setup_timing_engine(struct
> dpu_hw_intf *ctx,
> if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) {
> intf_cfg2 |= BIT(4);
> display_data_hctl = display_hctl;
> - DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);
> DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl);
> }
>
> @@ -204,6 +203,8 @@ static void dpu_hw_intf_setup_timing_engine(struct
> dpu_hw_intf *ctx,
> DPU_REG_WRITE(c, INTF_FRAME_LINE_COUNT_EN, 0x3);
> DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg);
> DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format);
> + if (ctx->cap->features & (BIT(DPU_DATA_HCTL_EN) |
> BIT(DPU_INTF_WIDEBUS)))
> + DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);
> }
>
> static void dpu_hw_intf_enable_timing_engine(
> --
> 2.29.2
>
--
With best wishes
Dmitry
