Re: [Emc-users] Hardware step generator for 5I20
On Thu, 15 Feb 2007, John Prentice wrote: Date: Thu, 15 Feb 2007 19:07:44 - From: John Prentice [EMAIL PROTECTED] Reply-To: Enhanced Machine Controller (EMC) emc-users@lists.sourceforge.net To: Enhanced Machine Controller (EMC) emc-users@lists.sourceforge.net Subject: Re: [Emc-users] Hardware step generator for 5I20 Hi From: [EMAIL PROTECTED] Peter C. Wallace [EMAIL PROTECTED] wrote: On the step/dir side: some drives require setup and/or hold times for the dir line with respect to the step line. Others have minumum step pulse lengths. Do the generators support this? Min pulse length isn't that hard, but setup and hold time can be a pain. Example: You were running along at +10 steps/sec, then you switch to -10 steps/sec. 99.999% of the time that is fine. But if you make the change a microsecond after the DDS has generated an up step, it will want to generate a down step a microsecond later. (The DDS accumulator will have only added a tiny amount, so once you switch directions, it will only have to subtract a tiny amount.) The HAL software stepgen has more code (crufty code at that) to ensure setup and hold times than is required for the DDS itself. You probably have this in hand but I grappled with it a while ago. The project never got into production but I did lots of 'scope tests and I think the module works properly in the file at: www.castlewoodconsultants.com/Misc/PulseGen.v It has a simple pulse generator and a ShapeSetupHold module that enforces times defined in two registers. HTH Thanks, looks about like what I was imagining and probably some things I missed... John Prentice - Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT business topics through brief surveys-and earn cash http://www.techsay.com/default.php?page=join.phpp=sourceforgeCID=DEVDEV ___ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users Peter Wallace Mesa Electronics (\__/) (='.'=) This is Bunny. Copy and paste bunny into your ()_() signature to help him gain world domination. - Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT business topics through brief surveys-and earn cash http://www.techsay.com/default.php?page=join.phpp=sourceforgeCID=DEVDEV ___ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
[Emc-users] Hardware step generator for 5I20
Finally had a bit of free time to work on this. Still needs testing and more features but here whats there so far: 12 step gens. Each stepgen is 28 bit DDS + FIFO + preset/residue clear logic Step gens overlaid on basic I/O port, Step generators can be individually enabled, or I/O pins left as simple I/O. So for example if the stepgens are all disabled you have a 72 bit I/O port. Step/DIR or quadature output selectable per generator. Step gens are buffered (16 deep x 32 bit wide FIFOs each). This means that real time is not required (at least for step generation), For example at a basic clock of 8 MHz and a frame size (frame size is how many additions are done to step generator DDS per FIFO entry) of 8000, the step gen will consume one FIFO entry per mSec. Since the FIFOs are 16 deep, if we use interrupts or just poll the FIFOhalf full register the interrupt latency or minimum polling time would ge 8 mSec (125 Hz). Also the basic local bus interface has been changed to be 32 bit memory only, and has support for burst transfer mode. Things to do: Add quadrature counters (probably just graft in existing one) Add simplified PWM gens (no fancy signed/unsigned modes) Add SPI channels (for general use plus for our I/O expander and 7I41 stepper interface use SPI) Peter Wallace Mesa Electronics (\__/) (='.'=) This is Bunny. Copy and paste bunny into your ()_() signature to help him gain world domination. - Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT business topics through brief surveys-and earn cash http://www.techsay.com/default.php?page=join.phpp=sourceforgeCID=DEVDEV ___ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
Re: [Emc-users] Hardware step generator for 5I20
[EMAIL PROTECTED] wrote: Peter C. Wallace [EMAIL PROTECTED] wrote: Step/DIR or quadature output selectable per generator. My UPC has had quadrature output available since I developed it. I don't think more than one user actually used the feature, and he was using an absolute minimum driver, just power transistors. But, yes, it seems to have significant advantages over step/direction! Jon - Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT business topics through brief surveys-and earn cash http://www.techsay.com/default.php?page=join.phpp=sourceforgeCID=DEVDEV ___ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
Re: [Emc-users] Hardware step generator for 5I20
Peter, Great news. Will you be able to intermix steppers and PWMs on a single board? If I understand correctly your statement on PWM, that should be adequate for my needs. For my immediate project, I need three axes of steppers and one unidirectional PWM (no encoder) with a frequency between 5Khz and 25Khz. I also recently received a development m5i20 board for this project, and would be glad to help out with the EMC driver, testing, or anywhere else I can assist. Regards, Eric Finally had a bit of free time to work on this. Still needs testing and more features but here whats there so far: 12 step gens. Each stepgen is 28 bit DDS + FIFO + preset/residue clear logic Step gens overlaid on basic I/O port, Step generators can be individually enabled, or I/O pins left as simple I/O. So for example if the stepgens are all disabled you have a 72 bit I/O port. Step/DIR or quadature output selectable per generator. Step gens are buffered (16 deep x 32 bit wide FIFOs each). This means that real time is not required (at least for step generation), For example at a basic clock of 8 MHz and a frame size (frame size is how many additions are done to step generator DDS per FIFO entry) of 8000, the step gen will consume one FIFO entry per mSec. Since the FIFOs are 16 deep, if we use interrupts or just poll the FIFOhalf full register the interrupt latency or minimum polling time would ge 8 mSec (125 Hz). Also the basic local bus interface has been changed to be 32 bit memory only, and has support for burst transfer mode. Things to do: Add quadrature counters (probably just graft in existing one) Add simplified PWM gens (no fancy signed/unsigned modes) Add SPI channels (for general use plus for our I/O expander and 7I41 stepper interface use SPI) - Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT business topics through brief surveys-and earn cash http://www.techsay.com/default.php?page=join.phpp=sourceforgeCID=DEVDEV ___ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
Re: [Emc-users] Hardware step generator for 5I20
Peter C. Wallace wrote: Finally had a bit of free time to work on this. Still needs testing and more features but here whats there so far: Is the VHDL for this going to be made available under the GPL? If so, I'm interested in writing the HAL driver for it. Yes Great! On the step/dir side: some drives require setup and/or hold times for the dir line with respect to the step line. Others have minumum step pulse lengths. Do the generators support this? Min pulse length isn't that hard, but setup and hold time can be a pain. The generator is just the DDS at the moment, it could be followed by a state machine to generate the step pulses (they are just the DDS MSb ATM) Understood... still under construction ;-) The DDS uses a 32 bit control word, the DDS is just 28 bits so there are 4 free bits in the FIFO. 3 of the free bits of that word allow presetting the DDS MSBs (just once at the start of the frame). This allows presetting the DDS to a safe location (no immediate step output change) in case you want to clear the residue, or change direction. Interesting approach. Normally of course you want to retain any fractional step that is in the accumulator, but stuffing a safe velue in there on a direction change could work. It gets hairy if you are writing the new value at about the same time as a step pulse is due to be sent. Unless the FPGA is the overall timing master (with a FIFO, etc) then you won't know if that last pulse got sent before you stuffed the new value. Step gens are buffered (16 deep x 32 bit wide FIFOs each). This means that real time is not required (at least for step generation), For example at a basic clock of 8 MHz and a frame size (frame size is how many additions are done to step generator DDS per FIFO entry) of 8000, the step gen will consume one FIFO entry per mSec. Since the FIFOs are 16 deep, if we use interrupts or just poll the FIFOhalf full register the interrupt latency or minimum polling time would ge 8 mSec (125 Hz). For some applications this might be a feature. For EMC its a bug. We already have hard realtime code, and the system time base comes from the realtime threads in the PC, not from the FPGA. hard realtime is a relative term when relating to MHz pulse streams... Understood - we don't have sub-microsecond realtime. But we don't need it - thats the entire reason for hardware stepgen. EMC treats hardware step generators just like DACs. They are part of a servo loop, which is closed in EMC's servo thread at a typical period of 1mS. Tens of microseconds of jitter in the servo thread causes no real problems. The closed loop resolves any ambiguities about whether a step was sent or not. The only requirement is that the feedback from the FPGA and the output of the drive stay in sync. The main risk is a step that is counted by the feedback in the FPGA, but missed by the drive because of setup or hold or whatever. Jon Elson's boards use the servo scheme - his step outputs are sent to an encoder counter as well as to the drive, and the encoder counter feedback is used to close the loop. Your approach is more open-loop - you rely on the step generator doing exactly what it is told to do, and the FIFO is key to making that possible. If the FIFO runs dry you are in trouble, so you make darned sure it doesn't. But then you have pipeline delays because of the FIFO. For example, consider probing. When probing, we move toward an object until the probe touches, then stop as quickly as possible and back off. If several mS of motion are queued in the FIFO, that quick reaction becomes either less quick, or more complex, or both. We could debate the relative merits of the two approaches for a long time, but let's not. Suffice it to say that EMC has sub-millisecond hard realtime code, and it wants to treat the motor control section as if it was an analog servo. At least at present, it is not possible for EMC to use an external interrupt source to trigger the realtime threads, so synchronizing its code to the FPGA's frames would not be straightforward. Even if we did add external interrupt capability, what happens when there are two devices, each with hardware frames, and each expecting the software to follow its lead? The buffering means that each frame will have a know number of additions, so the DDS after each frame is calculable. I could easily add a non-buffered mode, but then you would have to count the output pulses, In this case it would not be possible to guarantee synchronism down to 1 step between axis, with the buffer this is possible... It is true that the buffered approach is theoreticaly a tiny bit more accurate. A perfect forward transfer function is more accurate (if less robust) than using feedback to compensate for imperfections. Maybe we (EMC) should investigate the possibilities. If we limit ourselves to a maximum of one frame in the buffer, perhaps
Re: [Emc-users] Hardware step generator for 5I20
On Thu, 15 Feb 2007, Eric H. Johnson wrote: Date: Thu, 15 Feb 2007 15:07:17 -0500 From: Eric H. Johnson [EMAIL PROTECTED] Reply-To: Enhanced Machine Controller (EMC) emc-users@lists.sourceforge.net To: 'Enhanced Machine Controller (EMC)' emc-users@lists.sourceforge.net Subject: Re: [Emc-users] Hardware step generator for 5I20 Peter, Great news. Will you be able to intermix steppers and PWMs on a single board? If I understand correctly your statement on PWM, that should be adequate for my needs. For my immediate project, I need three axes of steppers and one unidirectional PWM (no encoder) with a frequency between 5Khz and 25Khz. Yes, I intend to have: Basic I/O StepGen Quadrature counters PWM SPI All in the same configuration I also recently received a development m5i20 board for this project, and would be glad to help out with the EMC driver, testing, or anywhere else I can assist. Regards, Eric Finally had a bit of free time to work on this. Still needs testing and more features but here whats there so far: 12 step gens. Each stepgen is 28 bit DDS + FIFO + preset/residue clear logic Step gens overlaid on basic I/O port, Step generators can be individually enabled, or I/O pins left as simple I/O. So for example if the stepgens are all disabled you have a 72 bit I/O port. Step/DIR or quadature output selectable per generator. Step gens are buffered (16 deep x 32 bit wide FIFOs each). This means that real time is not required (at least for step generation), For example at a basic clock of 8 MHz and a frame size (frame size is how many additions are done to step generator DDS per FIFO entry) of 8000, the step gen will consume one FIFO entry per mSec. Since the FIFOs are 16 deep, if we use interrupts or just poll the FIFOhalf full register the interrupt latency or minimum polling time would ge 8 mSec (125 Hz). Also the basic local bus interface has been changed to be 32 bit memory only, and has support for burst transfer mode. Things to do: Add quadrature counters (probably just graft in existing one) Add simplified PWM gens (no fancy signed/unsigned modes) Add SPI channels (for general use plus for our I/O expander and 7I41 stepper interface use SPI) - Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT business topics through brief surveys-and earn cash http://www.techsay.com/default.php?page=join.phpp=sourceforgeCID=DEVDEV ___ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users Peter Wallace Mesa Electronics (\__/) (='.'=) This is Bunny. Copy and paste bunny into your ()_() signature to help him gain world domination. - Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT business topics through brief surveys-and earn cash http://www.techsay.com/default.php?page=join.phpp=sourceforgeCID=DEVDEV ___ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
Re: [Emc-users] Hardware step generator for 5I20
On Thursday 15 February 2007, Jon Elson wrote: [EMAIL PROTECTED] wrote: Peter C. Wallace [EMAIL PROTECTED] wrote: Step/DIR or quadature output selectable per generator. My UPC has had quadrature output available since I developed it. I don't think more than one user actually used the feature, and he was using an absolute minimum driver, just power transistors. But, yes, it seems to have significant advantages over step/direction! Jon Generally I have to agree Jon, as the smoothest, most accurate mouse any of us has ever used was the decoded quadrature output amiga mouse of yesteryear, but it comes to mind, how does one handle the microstepping when using the quadrature signals if you can't step back and forth through the lookup table of desired currents using that? That would also seem to restrict you to 1/4 step resolutions unless the lookup table was two full cycles wide. Then one almost needs an index pulse too... Or am I miss-understanding the actual implementation? -- Cheers, Gene There are four boxes to be used in defense of liberty: soap, ballot, jury, and ammo. Please use in that order. -Ed Howdershelt (Author) Yahoo.com and AOL/TW attorneys please note, additions to the above message by Gene Heskett are: Copyright 2007 by Maurice Eugene Heskett, all rights reserved. - Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT business topics through brief surveys-and earn cash http://www.techsay.com/default.php?page=join.phpp=sourceforgeCID=DEVDEV ___ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
Re: [Emc-users] Hardware step generator for 5I20
On Thu, 15 Feb 2007, Gene Heskett wrote: Date: Thu, 15 Feb 2007 15:44:32 -0500 From: Gene Heskett [EMAIL PROTECTED] Reply-To: Enhanced Machine Controller (EMC) emc-users@lists.sourceforge.net To: emc-users@lists.sourceforge.net Cc: Jon Elson [EMAIL PROTECTED] Subject: Re: [Emc-users] Hardware step generator for 5I20 On Thursday 15 February 2007, Jon Elson wrote: [EMAIL PROTECTED] wrote: Peter C. Wallace [EMAIL PROTECTED] wrote: Step/DIR or quadature output selectable per generator. My UPC has had quadrature output available since I developed it. I don't think more than one user actually used the feature, and he was using an absolute minimum driver, just power transistors. But, yes, it seems to have significant advantages over step/direction! Jon Generally I have to agree Jon, as the smoothest, most accurate mouse any of us has ever used was the decoded quadrature output amiga mouse of yesteryear, but it comes to mind, how does one handle the microstepping when using the quadrature signals if you can't step back and forth through the lookup table of desired currents using that? Quadrature is just an alternate way of taking steps (or microsteps) in either direction. It has the advantage that it does not have the direction -- step setup time problems that step/direction counters suffer from. This is because is it a 2 bit Grey code where only on bit can change at a time. That would also seem to restrict you to 1/4 step resolutions unless the lookup table was two full cycles wide. Then one almost needs an index pulse too... Or am I miss-understanding the actual implementation? -- Cheers, Gene There are four boxes to be used in defense of liberty: soap, ballot, jury, and ammo. Please use in that order. -Ed Howdershelt (Author) Yahoo.com and AOL/TW attorneys please note, additions to the above message by Gene Heskett are: Copyright 2007 by Maurice Eugene Heskett, all rights reserved. - Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT business topics through brief surveys-and earn cash http://www.techsay.com/default.php?page=join.phpp=sourceforgeCID=DEVDEV ___ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users Peter Wallace Mesa Electronics (\__/) (='.'=) This is Bunny. Copy and paste bunny into your ()_() signature to help him gain world domination. - Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT business topics through brief surveys-and earn cash http://www.techsay.com/default.php?page=join.phpp=sourceforgeCID=DEVDEV ___ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
Re: [Emc-users] Hardware step generator for 5I20
they are strictly talking about using quadrature instead of step-direction as the interface between the card and the stepper drive.. Instead of the direction pin designating which direction the stepper would go - it looks at which signal rises or falls first. Very noise tollerant. Same way you know which direction an encoder is spinning and how far it has rotated. sam - Original Message - From: Gene Heskett [EMAIL PROTECTED] To: emc-users@lists.sourceforge.net Cc: Jon Elson [EMAIL PROTECTED] Sent: Thursday, February 15, 2007 2:44 PM Subject: Re: [Emc-users] Hardware step generator for 5I20 On Thursday 15 February 2007, Jon Elson wrote: [EMAIL PROTECTED] wrote: Peter C. Wallace [EMAIL PROTECTED] wrote: Step/DIR or quadature output selectable per generator. My UPC has had quadrature output available since I developed it. I don't think more than one user actually used the feature, and he was using an absolute minimum driver, just power transistors. But, yes, it seems to have significant advantages over step/direction! Jon Generally I have to agree Jon, as the smoothest, most accurate mouse any of us has ever used was the decoded quadrature output amiga mouse of yesteryear, but it comes to mind, how does one handle the microstepping when using the quadrature signals if you can't step back and forth through the lookup table of desired currents using that? That would also seem to restrict you to 1/4 step resolutions unless the lookup table was two full cycles wide. Then one almost needs an index pulse too... Or am I miss-understanding the actual implementation? -- Cheers, Gene There are four boxes to be used in defense of liberty: soap, ballot, jury, and ammo. Please use in that order. -Ed Howdershelt (Author) Yahoo.com and AOL/TW attorneys please note, additions to the above message by Gene Heskett are: Copyright 2007 by Maurice Eugene Heskett, all rights reserved. - Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT business topics through brief surveys-and earn cash http://www.techsay.com/default.php?page=join.phpp=sourceforgeCID=DEVDEV ___ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users - Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT business topics through brief surveys-and earn cash http://www.techsay.com/default.php?page=join.phpp=sourceforgeCID=DEVDEV ___ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
Re: [Emc-users] Hardware step generator for 5I20
Jon Elson [EMAIL PROTECTED] wrote: [EMAIL PROTECTED] wrote: Jon Elson's boards use the servo scheme - his step outputs are sent to an encoder counter as well as to the drive, and the encoder counter feedback is used to close the loop. It seems to me you HAVE to do this. Unless the clock of the FPGA is somehow linked to the clock of the CPU, or the FPGA is generating a servo update interval for the CPU, then there is always the possibility of a step pulse either being sent or not, before the next update. Eventually, these errors will multiply to large position errors. You'd either have to sync the software threads to the FPGA frames, or do something else clever. I have an idea forming in the back of my mind that might work (and allow the software threads to remain independent), but I haven't thought it thru enough yet to even put it into words yet, let alone analyze it to see if it would really work. Maybe this evening. It is true that the buffered approach is theoreticaly a tiny bit more accurate. A perfect forward transfer function is more accurate (if less robust) than using feedback to compensate for imperfections. Maybe we (EMC) should investigate the possibilities. If we limit ourselves to a maximum of one frame in the buffer, perhaps the delay issue can be avoided. Something to think about. Well, some discussion might be warranted, but it seems that in a real-world machine control, where the operator may need to change feedrate or even abort the procedure at any time, this is just unworkable. Maybe if the counters are there, and are only used to recover position from an abort, it would be functional. Everything is a matter of degree. Nobody is proposing a FIFO with several seconds of motion in it. We're talking about milliseconds. A delay of even several milliseconds on _any_ operator induced action (feed override, abort) is going to be completely undetectable to the operator. Even for E-Stop, one or two milliseconds won't make an important difference. Probing and homing are the cases that matter here. When the probe makes contact, or the home switch trips, we need to know where the machine IS at that instant, not where it is supposed to be, or will be a few milliseconds from now, or was a few milliseconds ago. The measurement error due to the FIFO delay will be equal to the travel velocity times the delay. - Take Surveys. Earn Cash. Influence the Future of IT Join SourceForge.net's Techsay panel and you'll get the chance to share your opinions on IT business topics through brief surveys-and earn cash http://www.techsay.com/default.php?page=join.phpp=sourceforgeCID=DEVDEV ___ Emc-users mailing list Emc-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/emc-users
