Re: [Eug-lug] make question
mytargeta: $(MAKE) -f Makefile.a mytarget mytargetb: $(MAKE) -f Makefile.b mytarget # ... rest of Makefile ... On Tue, Jul 26, 2011 at 4:32 PM, Mike Cherba mche...@gmail.com wrote: I've got a make question I'm hoping someone can help me with. I have three Makefiles Makefile.a Makefile.b and Makefile Makefile contains all the real targets and the .a and .b files simply export a couple of variables and include Makefile. I want to eliminate Makefile.a and Makefile.b by performing those exports dynamically based on the chosen target, so make mytargeta would replace make -f Makefile.a mytarget and make mytargetb would replace make -f Makefile.b mytarget correspondingly. I can easily mimic this with a shell script sitting in front of the Makefile, but I'd like to do it using only make if possible. I'm coming to the conclusion that there's no provision in make for this. The targets are inherited and fairly complex with multiple levels of inclusion, so just rewriting all the makefiles is out of the question. Any suggestions? I may just have to create a build.sh which matches the target given as an argument and invokes make with the correct -f option. -Mike -- Science is the belief in the ignorance of experts. -- Richard Feynman ___ EUGLUG mailing list euglug@euglug.org http://www.euglug.org/mailman/listinfo/euglug -- Bob Miller Kbob k...@jogger-egg.com ___ EUGLUG mailing list euglug@euglug.org http://www.euglug.org/mailman/listinfo/euglug
Re: [Eug-lug] make question
Thanks Bob. I was thinking about trying something similar but hadn't gotten around to it yet. I'll give that a shot. -Mike On Tue, Jul 26, 2011 at 4:38 PM, Bob Miller k...@jogger-egg.com wrote: mytargeta: $(MAKE) -f Makefile.a mytarget mytargetb: $(MAKE) -f Makefile.b mytarget # ... rest of Makefile ... On Tue, Jul 26, 2011 at 4:32 PM, Mike Cherba mche...@gmail.com wrote: I've got a make question I'm hoping someone can help me with. I have three Makefiles Makefile.a Makefile.b and Makefile Makefile contains all the real targets and the .a and .b files simply export a couple of variables and include Makefile. I want to eliminate Makefile.a and Makefile.b by performing those exports dynamically based on the chosen target, so make mytargeta would replace make -f Makefile.a mytarget and make mytargetb would replace make -f Makefile.b mytarget correspondingly. I can easily mimic this with a shell script sitting in front of the Makefile, but I'd like to do it using only make if possible. I'm coming to the conclusion that there's no provision in make for this. The targets are inherited and fairly complex with multiple levels of inclusion, so just rewriting all the makefiles is out of the question. Any suggestions? I may just have to create a build.sh which matches the target given as an argument and invokes make with the correct -f option. -Mike -- Science is the belief in the ignorance of experts. -- Richard Feynman ___ EUGLUG mailing list euglug@euglug.org http://www.euglug.org/mailman/listinfo/euglug -- Bob Miller Kbob k...@jogger-egg.com ___ EUGLUG mailing list euglug@euglug.org http://www.euglug.org/mailman/listinfo/euglug -- Science is the belief in the ignorance of experts. -- Richard Feynman ___ EUGLUG mailing list euglug@euglug.org http://www.euglug.org/mailman/listinfo/euglug
Re: [Eug-lug] make question
Yup. That did the trick. I was getting hung up on trying to remove the need for the Makefile.a and Makefile.b instead of just making their use transparent. -Thanks, -Mike On Tue, Jul 26, 2011 at 4:46 PM, Mike Cherba mche...@gmail.com wrote: Thanks Bob. I was thinking about trying something similar but hadn't gotten around to it yet. I'll give that a shot. -Mike On Tue, Jul 26, 2011 at 4:38 PM, Bob Miller k...@jogger-egg.com wrote: mytargeta: $(MAKE) -f Makefile.a mytarget mytargetb: $(MAKE) -f Makefile.b mytarget # ... rest of Makefile ... On Tue, Jul 26, 2011 at 4:32 PM, Mike Cherba mche...@gmail.com wrote: I've got a make question I'm hoping someone can help me with. I have three Makefiles Makefile.a Makefile.b and Makefile Makefile contains all the real targets and the .a and .b files simply export a couple of variables and include Makefile. I want to eliminate Makefile.a and Makefile.b by performing those exports dynamically based on the chosen target, so make mytargeta would replace make -f Makefile.a mytarget and make mytargetb would replace make -f Makefile.b mytarget correspondingly. I can easily mimic this with a shell script sitting in front of the Makefile, but I'd like to do it using only make if possible. I'm coming to the conclusion that there's no provision in make for this. The targets are inherited and fairly complex with multiple levels of inclusion, so just rewriting all the makefiles is out of the question. Any suggestions? I may just have to create a build.sh which matches the target given as an argument and invokes make with the correct -f option. -Mike -- Science is the belief in the ignorance of experts. -- Richard Feynman ___ EUGLUG mailing list euglug@euglug.org http://www.euglug.org/mailman/listinfo/euglug -- Bob Miller Kbob k...@jogger-egg.com ___ EUGLUG mailing list euglug@euglug.org http://www.euglug.org/mailman/listinfo/euglug -- Science is the belief in the ignorance of experts. -- Richard Feynman -- Science is the belief in the ignorance of experts. -- Richard Feynman ___ EUGLUG mailing list euglug@euglug.org http://www.euglug.org/mailman/listinfo/euglug
