RE: [ARC PATCH] Table-driven ashlsi implementation for better code/rtx_costs.
HI Roger,
It looks good.
Thank you for your contribution,
Claudiu
-Original Message-
From: Roger Sayle
Sent: Sunday, December 24, 2023 1:38 AM
To: gcc-patches@gcc.gnu.org
Cc: 'Claudiu Zissulescu' ; 'Jeff Law'
Subject: [ARC PATCH] Table-driven ashlsi implementation for better
code/rtx_costs.
One of the cool features of the H8 backend is its use of tables to select
optimal shift implementations for different CPU variants. This patch borrows
(plagiarizes) that idiom for SImode left shifts in the ARC backend (for CPUs
without a barrel-shifter). This provides a convenient mechanism for both
selecting the best implementation strategy (for speed vs. size), and providing
accurate rtx_costs [without duplicating a lot of logic].
Left shift RTX costs are especially important for use in synth_mult.
An example improvement is:
int foo(int x) { return 32768*x; }
which is now generated with -O2 -mcpu=em -mswap as:
foo:bmsk_s r0,r0,16
swapr0,r0
j_s.d [blink]
ror r0,r0
where previously the ARC backend would generate a loop:
foo:mov lp_count,15
lp 2f
add r0,r0,r0
nop
2: # end single insn loop
j_s [blink]
Tested with a cross-compiler to arc-linux hosted on x86_64, with no new
(compile-only) regressions from make -k check.
Ok for mainline if this passes Claudiu's and/or Jeff's testing?
[Thanks again to Jeff for finding the typo in my last ARC patch]
2023-12-23 Roger Sayle
gcc/ChangeLog
* config/arc/arc.cc (arc_shift_alg): New enumerated type for
left shift implementation strategies.
(arc_shift_info): Type for each entry of the shift strategy table.
(arc_shift_context_idx): Return a integer value for each code
generation context, used as an index
(arc_ashl_alg): Table indexed by context and shifted bit count.
(arc_split_ashl): Use the arc_ashl_alg table to select SImode
left shift implementation.
(arc_rtx_costs) : Use the arc_ashl_alg table to
provide accurate costs, when optimizing for speed or size.
Thanks in advance,
Roger
--
RE: [ARC PATCH] Add *extvsi_n_0 define_insn_and_split for PR 110717.
Hi Roger,
It looks good to me.
Thank you for your contribution,
Claudiu
-Original Message-
From: Roger Sayle
Sent: Tuesday, December 5, 2023 4:00 PM
To: gcc-patches@gcc.gnu.org
Cc: 'Claudiu Zissulescu'
Subject: [ARC PATCH] Add *extvsi_n_0 define_insn_and_split for PR 110717.
This patch improves the code generated for bitfield sign extensions on ARC cpus
without a barrel shifter.
Compiling the following test case:
int foo(int x) { return (x<<27)>>27; }
with -O2 -mcpu=em, generates two loops:
foo:mov lp_count,27
lp 2f
add r0,r0,r0
nop
2: # end single insn loop
mov lp_count,27
lp 2f
asr r0,r0
nop
2: # end single insn loop
j_s [blink]
and the closely related test case:
struct S { int a : 5; };
int bar (struct S *p) { return p->a; }
generates the slightly better:
bar:ldb_s r0,[r0]
mov_s r2,0;3
add3r0,r2,r0
sexb_s r0,r0
asr_s r0,r0
asr_s r0,r0
j_s.d [blink]
asr_s r0,r0
which uses 6 instructions to perform this particular sign extension.
It turns out that sign extensions can always be implemented using at most three
instructions on ARC (without a barrel shifter) using the idiom
((x)^msb)-msb [as described in section "2-5 Sign Extension"
of Henry Warren's book "Hacker's Delight"]. Using this, the sign extensions
above on ARC's EM both become:
bmsk_s r0,r0,4
xor r0,r0,32
sub r0,r0,32
which takes about 3 cycles, compared to the ~112 cycles for the loops in foo.
Tested with a cross-compiler to arc-linux hosted on x86_64, with no new
(compile-only) regressions from make -k check.
Ok for mainline if this passes Claudiu's nightly testing?
2023-12-05 Roger Sayle
gcc/ChangeLog
* config/arc/arc.md (*extvsi_n_0): New define_insn_and_split to
implement SImode sign extract using a AND, XOR and MINUS sequence.
gcc/testsuite/ChangeLog
* gcc.target/arc/extvsi-1.c: New test case.
* gcc.target/arc/extvsi-2.c: Likewise.
Thanks in advance,
Roger
--
RE: [ARC PATCH] Consistent use of whitespace in assembler templates.
Hi Roger, Apologizes for late reply, I was in a short vacation. Please proceed with your commit. BTW, I consider this type of contribution as obvious, and you can always push it without waiting for my feedback. Thank you for your contribution, Claudiu -Original Message- From: Roger Sayle Sent: Monday, November 6, 2023 8:37 PM To: gcc-patches@gcc.gnu.org Cc: 'Claudiu Zissulescu' Subject: [ARC PATCH] Consistent use of whitespace in assembler templates. This minor clean-up patch tweaks arc.md to use whitespace consistently in output templates, always using a TAB between the mnemonic and its operands, and avoiding spaces after commas between operands. There should be no functional changes with this patch, though several test cases' scan-assembler needed to be updated to use \s+ instead of testing for a TAB or a space explicitly. Tested with a cross-compiler to arc-linux hosted on x86_64, with no new (compile-only) regressions from make -k check. Ok for mainline if this passes Claudiu's nightly testing? 2023-11-06 Roger Sayle gcc/ChangeLog * config/arc/arc.md: Make output template whitespace consistent. gcc/testsuite/ChangeLog * gcc.target/arc/jli-1.c: Update dg-final whitespace. * gcc.target/arc/jli-2.c: Likewise. * gcc.target/arc/naked-1.c: Likewise. * gcc.target/arc/naked-2.c: Likewise. * gcc.target/arc/tmac-1.c: Likewise. * gcc.target/arc/tmac-2.c: Likewise. Thanks again, Roger --
RE: [ARC PATCH] Improved DImode rotates and right shifts by one bit.
Looks good too. Please proceed with your commit.
Thank you for your contribution,
//Claudiu
-Original Message-
From: Roger Sayle
Sent: Monday, November 6, 2023 7:30 PM
To: gcc-patches@gcc.gnu.org
Cc: 'Claudiu Zissulescu'
Subject: [ARC PATCH] Improved DImode rotates and right shifts by one bit.
This patch improves the code generated for DImode right shifts (both arithmetic
and logical) by a single bit, and also for DImode rotates (both left and right)
by a single bit. In approach, this is similar to the recently added DImode
left shift by a single bit patch, but also builds upon i386.md's UNSPEC carry
flag representation:
https://urldefense.com/v3/__https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632169.html__;!!A4F2R9G_pg!fxasivX0MLFBbgzab_TjnY9wQnIao29buOVHUv6gvPzOS-W4IWfIdwse4TRg__ek2AEplJ7BpYrTYBt1hB8mUCM$
The benefits can be seen from the four new test cases:
long long ashr(long long x) { return x >> 1; }
Before:
ashr: asl r2,r1,31
lsr_s r0,r0
or_sr0,r0,r2
j_s.d [blink]
asr_s r1,r1,1
After:
ashr: asr.f r1,r1
j_s.d [blink]
rrc r0,r0
unsigned long long lshr(unsigned long long x) { return x >> 1; }
Before:
lshr: asl r2,r1,31
lsr_s r0,r0
or_sr0,r0,r2
j_s.d [blink]
lsr_s r1,r1
After:
lshr: lsr.f r1,r1
j_s.d [blink]
rrc r0,r0
unsigned long long rotl(unsigned long long x) { return (x<<1) | (x>>63); }
Before:
rotl: lsr r12,r1,31
lsr r2,r0,31
asl_s r3,r0,1
asl_s r1,r1,1
or r0,r12,r3
j_s.d [blink]
or_sr1,r1,r2
After:
rotl: add.f r0,r0,r0
adc.f r1,r1,r1
j_s.d [blink]
add.cs r0,r0,1
unsigned long long rotr(unsigned long long x) { return (x>>1) | (x<<63); }
Before:
rotr: asl r12,r1,31
asl r2,r0,31
lsr_s r3,r0
lsr_s r1,r1
or r0,r12,r3
j_s.d [blink]
or_sr1,r1,r2
After:
rotr: asr.f 0,r0
rrc.f r1,r1
j_s.d [blink]
rrc r0,r0
On CPUs without a barrel shifter the improvements are even better.
Tested with a cross-compiler to arc-linux hosted on x86_64, with no new
(compile-only) regressions from make -k check.
Ok for mainline if this passes Claudiu's nightly testing?
2023-11-06 Roger Sayle
gcc/ChangeLog
* config/arc/arc.md (UNSPEC_ARC_CC_NEZ): New UNSPEC that
represents the carry flag being set if the operand is non-zero.
(adc_f): New define_insn representing adc with updated flags.
(ashrdi3): New define_expand that only handles shifts by 1.
(ashrdi3_cnt1): New pre-reload define_insn_and_split.
(lshrdi3): New define_expand that only handles shifts by 1.
(lshrdi3_cnt1): New pre-reload define_insn_and_split.
(rrcsi2): New define_insn for rrc (SImode rotate right through carry).
(rrcsi2_carry): Likewise for rrc.f, as above but updating flags.
(rotldi3): New define_expand that only handles rotates by 1.
(rotldi3_cnt1): New pre-reload define_insn_and_split.
(rotrdi3): New define_expand that only handles rotates by 1.
(rotrdi3_cnt1): New pre-reload define_insn_and_split.
(lshrsi3_cnt1_carry): New define_insn for lsr.f.
(ashrsi3_cnt1_carry): New define_insn for asr.f.
(btst_0_carry): New define_insn for asr.f without result.
gcc/testsuite/ChangeLog
* gcc.target/arc/ashrdi3-1.c: New test case.
* gcc.target/arc/lshrdi3-1.c: Likewise.
* gcc.target/arc/rotldi3-1.c: Likewise.
* gcc.target/arc/rotrdi3-1.c: Likewise.
Thanks in advance,
Roger
--
RE: [ARC PATCH] Provide a TARGET_FOLD_BUILTIN target hook.
Hi Roger, Looks good. Please proceed with your commit. Thank you, Claudiu -Original Message- From: Roger Sayle Sent: Friday, November 3, 2023 9:43 PM To: gcc-patches@gcc.gnu.org Cc: 'Claudiu Zissulescu' Subject: [ARC PATCH] Provide a TARGET_FOLD_BUILTIN target hook. This patch implements a arc_fold_builtin target hook to allow ARC builtins to be folded at the tree-level. Currently this function converts __builtin_arc_swap into a LROTATE_EXPR at the tree-level, and evaluates __builtin_arc_norm and __builtin_arc_normw of integer constant arguments at compile-time. Because ARC_BUILTIIN_SWAP is now handled at the tree-level, UNSPEC_ARC_SWAP no longer used, allowing it and the "swap" define_insn to be removed. An example benefit of folding things at compile-time is that calling __builtin_arc_swap on the result of __builtin_arc_swap now eliminates both and generates no code, and likewise calling __builtin_arc_swap of a constant integer argument is evaluated at compile-time. Tested with a cross-compiler to arc-linux hosted on x86_64, with no new (compile-only) regressions from make -k check. Ok for mainline if this passes Claudiu's nightly testing? 2023-11-03 Roger Sayle gcc/ChangeLog * config/arc/arc.cc (TARGET_FOLD_BUILTIN): Define to arc_fold_builtin. (arc_fold_builtin): New function. Convert ARC_BUILTIN_SWAP into a rotate. Evaluate ARC_BUILTIN_NORM and ARC_BUILTIN_NORMW of constant arguments. * config/arc/arc.md (UNSPEC_ARC_SWAP): Delete. (normw): Make output template/assembler whitespace consistent. (swap): Remove define_insn, only use of SWAP UNSPEC. * config/arc/builtins.def: Tweak indentation. (SWAP): Expand using rotlsi2_cnt16 instead of using swap. gcc/testsuite/ChangeLog * gcc.target/arc/builtin_norm-1.c: New test case. * gcc.target/arc/builtin_norm-2.c: Likewise. * gcc.target/arc/builtin_normw-1.c: Likewise. * gcc.target/arc/builtin_normw-2.c: Likewise. * gcc.target/arc/builtin_swap-1.c: Likewise. * gcc.target/arc/builtin_swap-2.c: Likewise. * gcc.target/arc/builtin_swap-3.c: Likewise. Thanks in advance, Roger --
Re: [ARC PATCH] Improve DImode left shift by a single bit.
Missed this one.
Ok, please proceed with the commit.
Thank you for your contribution,
Claudiu
On Sat, Oct 28, 2023 at 4:05 PM Roger Sayle wrote:
>
>
> This patch improves the code generated for X << 1 (and for X + X) when
> X is 64-bit DImode, using the same two instruction code sequence used
> for DImode addition.
>
> For the test case:
>
> long long foo(long long x) { return x << 1; }
>
> GCC -O2 currently generates the following code:
>
> foo:lsr r2,r0,31
> asl_s r1,r1,1
> asl_s r0,r0,1
> j_s.d [blink]
> or_sr1,r1,r2
>
> and on CPU without a barrel shifter, i.e. -mcpu=em
>
> foo:add.f 0,r0,r0
> asl_s r1,r1
> rlc r2,0
> asl_s r0,r0
> j_s.d [blink]
> or_sr1,r1,r2
>
> with this patch (both with and without a barrel shifter):
>
> foo:add.f r0,r0,r0
> j_s.d [blink]
> adc r1,r1,r1
>
> [For Jeff Law's benefit a similar optimization is also applicable to
> H8300H, that could also use a two instruction sequence (plus rts) but
> currently GCC generates 16 instructions (plus an rts) for foo above.]
>
> Tested with a cross-compiler to arc-linux hosted on x86_64,
> with no new (compile-only) regressions from make -k check.
> Ok for mainline if this passes Claudiu's nightly testing?
>
> 2023-10-28 Roger Sayle
>
> gcc/ChangeLog
> * config/arc/arc.md (addsi3): Fix GNU-style code formatting.
> (adddi3): Change define_expand to generate an *adddi3.
> (*adddi3): New define_insn_and_split to lower DImode additions
> during the split1 pass (after combine and before reload).
> (ashldi3): New define_expand to (only) generate *ashldi3_cnt1
> for DImode left shifts by a single bit.
> (*ashldi3_cnt1): New define_insn_and_split to lower DImode
> left shifts by one bit to an *adddi3.
>
> gcc/testsuite/ChangeLog
> * gcc.target/arc/adddi3-1.c: New test case.
> * gcc.target/arc/ashldi3-1.c: Likewise.
>
>
> Thanks in advance,
> Roger
> --
>
Re: [ARC PATCH] Convert (signed<<31)>>31 to -(signed&1) without barrel shifter.
Hi Roger,
Do you want to say bmsk_s instead of msk_s here:
+/* { dg-final { scan-assembler "msk_s\\s+r0,r0,0" } } */
Anyhow, the patch looks good. Proceed with your commit.
Thank you,
Claudiu
On Mon, Oct 30, 2023 at 5:05 AM Jeff Law wrote:
>
>
>
> On 10/28/23 10:47, Roger Sayle wrote:
> >
> > This patch optimizes PR middle-end/101955 for the ARC backend. On ARC
> > CPUs with a barrel shifter, using two shifts is (probably) optimal as:
> >
> > asl_s r0,r0,31
> > asr_s r0,r0,31
> >
> > but without a barrel shifter, GCC -O2 -mcpu=em currently generates:
> >
> > and r2,r0,1
> > ror r2,r2
> > add.f 0,r2,r2
> > sbc r0,r0,r0
> >
> > with this patch, we now generate the smaller, faster and non-flags
> > clobbering:
> >
> > bmsk_s r0,r0,0
> > neg_s r0,r0
> >
> > Tested with a cross-compiler to arc-linux hosted on x86_64,
> > with no new (compile-only) regressions from make -k check.
> > Ok for mainline if this passes Claudiu's nightly testing?
> >
> >
> > 2023-10-28 Roger Sayle
> >
> > gcc/ChangeLog
> > PR middle-end/101955
> > * config/arc/arc.md (*extvsi_1_0): New define_insn_and_split
> > to convert sign extract of the least significant bit into an
> > AND $1 then a NEG when !TARGET_BARREL_SHIFTER.
> >
> > gcc/testsuite/ChangeLog
> > PR middle-end/101955
> > * gcc.target/arc/pr101955.c: New test case.
> Good catch. Looking to do something very similar on the H8 based on
> your work here.
>
> One the H8 we can use bld to load a bit from an 8 bit register into the
> C flag. Then we use subtract with carry to get an 8 bit 0/-1 which we
> can then sign extend to 16 or 32 bits. That covers bit positions 0..15
> of an SImode input.
>
> For bits 16..31 we can move the high half into the low half, the use the
> bld sequence.
>
> For bit zero the and+neg is the same number of clocks and size as bld
> based sequence. But it'll simulate faster, so it's special cased.
>
>
> Jeff
>
Re: [ARC PATCH] Improved ARC rtx_costs/insn_cost for SHIFTs and ROTATEs.
Hi Roger,
You have a block of 8 spaces that needs to be replaced by tabs:
gcc/config/arc/arc.cc:5538:0: if (n < 4)
Please fix the above, and proceed with your commit.
Thank you,
Claudiu
On Sun, Oct 29, 2023 at 11:16 AM Roger Sayle wrote:
>
>
> This patch overhauls the ARC backend's insn_cost target hook, and makes
> some related improvements to rtx_costs, BRANCH_COST, etc. The primary
> goal is to allow the backend to indicate that shifts and rotates are
> slow (discouraged) when the CPU doesn't have a barrel shifter. I should
> also acknowledge Richard Sandiford for inspiring the use of set_cost
> in this rewrite of arc_insn_cost; this implementation borrows heavily
> for the target hooks for AArch64 and ARM.
>
> The motivating example is derived from PR rtl-optimization/110717.
>
> struct S { int a : 5; };
> unsigned int foo (struct S *p) {
> return p->a;
> }
>
> With a barrel shifter, GCC -O2 generates the reasonable:
>
> foo:ldb_s r0,[r0]
> asl_s r0,r0,27
> j_s.d [blink]
> asr_s r0,r0,27
>
> What's interesting is that during combine, the middle-end actually
> has two shifts by three bits, and a sign-extension from QI to SI.
>
> Trying 8, 9 -> 11:
> 8: r158:SI=r157:QI#0<<0x3
> REG_DEAD r157:QI
> 9: r159:SI=sign_extend(r158:SI#0)
> REG_DEAD r158:SI
>11: r155:SI=r159:SI>>0x3
> REG_DEAD r159:SI
>
> Whilst it's reasonable to simplify this to two shifts by 27 bits when
> the CPU has a barrel shifter, it's actually a significant pessimization
> when these shifts are implemented by loops. This combination can be
> prevented if the backend provides accurate-ish estimates for insn_cost.
>
>
> Previously, without a barrel shifter, GCC -O2 -mcpu=em generates:
>
> foo:ldb_s r0,[r0]
> mov lp_count,27
> lp 2f
> add r0,r0,r0
> nop
> 2: # end single insn loop
> mov lp_count,27
> lp 2f
> asr r0,r0
> nop
> 2: # end single insn loop
> j_s [blink]
>
> which contains two loops and requires about ~113 cycles to execute.
> With this patch to rtx_cost/insn_cost, GCC -O2 -mcpu=em generates:
>
> foo:ldb_s r0,[r0]
> mov_s r2,0;3
> add3r0,r2,r0
> sexb_s r0,r0
> asr_s r0,r0
> asr_s r0,r0
> j_s.d [blink]
> asr_s r0,r0
>
> which requires only ~6 cycles, for the shorter shifts by 3 and sign
> extension.
>
>
> Tested with a cross-compiler to arc-linux hosted on x86_64,
> with no new (compile-only) regressions from make -k check.
> Ok for mainline if this passes Claudiu's nightly testing?
>
>
> 2023-10-29 Roger Sayle
>
> gcc/ChangeLog
> * config/arc/arc.cc (arc_rtx_costs): Improve cost estimates.
> Provide reasonable values for SHIFTS and ROTATES by constant
> bit counts depending upon TARGET_BARREL_SHIFTER.
> (arc_insn_cost): Use insn attributes if the instruction is
> recognized. Avoid calling get_attr_length for type "multi",
> i.e. define_insn_and_split patterns without explicit type.
> Fall-back to set_rtx_cost for single_set and pattern_cost
> otherwise.
> * config/arc/arc.h (COSTS_N_BYTES): Define helper macro.
> (BRANCH_COST): Improve/correct definition.
> (LOGICAL_OP_NON_SHORT_CIRCUIT): Preserve previous behavior.
>
>
> Thanks again,
> Roger
> --
>
Re: [ARC PATCH] Improved SImode shifts and rotates with -mswap.
Hi Roger, +(define_insn "si2_cnt16" + [(set (match_operand:SI 0 "dest_reg_operand" "=w") Please use "register_operand", and "r" constraint. +(ANY_ROTATE:SI (match_operand:SI 1 "register_operand" "c") Please use "r" constraint instead of "c". + (const_int 16)))] + "TARGET_SWAP" + "swap\\t%0,%1" Otherwise, it looks good to me. Please fix the above and proceed with your commit. Thank you for your contribution, Claudiu
[committed] arc: Remove mpy_dest_reg_operand predicate
The mpy_dest_reg_operand is just a wrapper for
register_operand. Remove it.
gcc/
* config/arc/arc.md (mulsi3_700): Update pattern.
(mulsi3_v2): Likewise.
* config/arc/predicates.md (mpy_dest_reg_operand): Remove it.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.md| 6 +++---
gcc/config/arc/predicates.md | 7 ---
2 files changed, 3 insertions(+), 10 deletions(-)
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 22af0bf47dd..325e4f56b9b 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -2293,7 +2293,7 @@ (define_insn "mulu64"
; registers, since it cannot be the destination of a multi-cycle insn
; like MPY or MPYU.
(define_insn "mulsi3_700"
- [(set (match_operand:SI 0 "mpy_dest_reg_operand""=r, r,r, r,r")
+ [(set (match_operand:SI 0 "register_operand""=r, r,r, r,r")
(mult:SI (match_operand:SI 1 "register_operand" "%0, r,0, 0,r")
(match_operand:SI 2 "nonmemory_operand" "rL,rL,I,Cal,Cal")))]
"TARGET_ARC700_MPY"
@@ -2306,8 +2306,8 @@ (define_insn "mulsi3_700"
; ARCv2 has no penalties between mpy and mpyu. So, we use mpy because of its
; short variant. LP_COUNT constraints are still valid.
(define_insn "mulsi3_v2"
- [(set (match_operand:SI 0 "mpy_dest_reg_operand""=q,q, r, r,r, r,
r")
- (mult:SI (match_operand:SI 1 "register_operand" "%0,q, 0, r,0, 0, c")
+ [(set (match_operand:SI 0 "register_operand""=q,q, r, r,r, r,
r")
+ (mult:SI (match_operand:SI 1 "register_operand" "%0,q, 0, r,0, 0, r")
(match_operand:SI 2 "nonmemory_operand"
"q,0,rL,rL,I,Cal,Cal")))]
"TARGET_MULTI"
"@
diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
index e37d8844979..e0aef86fd24 100644
--- a/gcc/config/arc/predicates.md
+++ b/gcc/config/arc/predicates.md
@@ -23,13 +23,6 @@ (define_predicate "dest_reg_operand"
return register_operand (op, mode);
})
-(define_predicate "mpy_dest_reg_operand"
- (match_code "reg,subreg")
-{
- return register_operand (op, mode);
-})
-
-
;; Returns 1 if OP is a symbol reference.
(define_predicate "symbolic_operand"
(match_code "symbol_ref, label_ref, const")
--
2.30.2
Re: [ARC PATCH] Improved SImode shifts and rotates on !TARGET_BARREL_SHIFTER.
Hi Roger,
Your patch doesn't introduce new regressions. However, before pushing
to the mainline you need to fix some issues:
1. Please fix the trailing spaces and blocks of 8 spaces which should
be replaced with tabs. You can use check_GNU_style.py script to spot
them.
2. Please use capital letters for code iterators (i.e., any_shift_rotate).
Once the above issues are fixed, please proceed with your commit.
Thank you for your contribution,
Claudiu
On Sun, Oct 8, 2023 at 10:07 PM Roger Sayle wrote:
>
>
> This patch completes the ARC back-end's transition to using pre-reload
> splitters for SImode shifts and rotates on targets without a barrel
> shifter. The core part is that the shift_si3 define_insn is no longer
> needed, as shifts and rotates that don't require a loop are split
> before reload, and then because shift_si3_loop is the only caller
> of output_shift, both can be significantly cleaned up and simplified.
> The output_shift function (Claudiu's "the elephant in the room") is
> renamed output_shift_loop, which handles just the four instruction
> zero-overhead loop implementations.
>
> Aside from the clean-ups, the user visible changes are much improved
> implementations of SImode shifts and rotates on affected targets.
>
> For the function:
> unsigned int rotr_1 (unsigned int x) { return (x >> 1) | (x << 31); }
>
> GCC with -O2 -mcpu=em would previously generate:
>
> rotr_1: lsr_s r2,r0
> bmsk_s r0,r0,0
> ror r0,r0
> j_s.d [blink]
> or_sr0,r0,r2
>
> with this patch, we now generate:
>
> j_s.d [blink]
> ror r0,r0
>
> For the function:
> unsigned int rotr_31 (unsigned int x) { return (x >> 31) | (x << 1); }
>
> GCC with -O2 -mcpu=em would previously generate:
>
> rotr_31:
> mov_s r2,r0 ;4
> asl_s r0,r0
> add.f 0,r2,r2
> rlc r2,0
> j_s.d [blink]
> or_sr0,r0,r2
>
> with this patch we now generate an add.f followed by an adc:
>
> rotr_31:
> add.f r0,r0,r0
> j_s.d [blink]
> add.cs r0,r0,1
>
>
> Shifts by constants requiring a loop have been improved for even counts
> by performing two operations in each iteration:
>
> int shl10(int x) { return x >> 10; }
>
> Previously looked like:
>
> shl10: mov.f lp_count, 10
> lpnz2f
> asr r0,r0
> nop
> 2: # end single insn loop
> j_s [blink]
>
>
> And now becomes:
>
> shl10:
> mov lp_count,5
> lp 2f
> asr r0,r0
> asr r0,r0
> 2: # end single insn loop
> j_s [blink]
>
>
> So emulating ARC's SWAP on architectures that don't have it:
>
> unsigned int rotr_16 (unsigned int x) { return (x >> 16) | (x << 16); }
>
> previously required 10 instructions and ~70 cycles:
>
> rotr_16:
> mov_s r2,r0 ;4
> mov.f lp_count, 16
> lpnz2f
> add r0,r0,r0
> nop
> 2: # end single insn loop
> mov.f lp_count, 16
> lpnz2f
> lsr r2,r2
> nop
> 2: # end single insn loop
> j_s.d [blink]
> or_sr0,r0,r2
>
> now becomes just 4 instructions and ~18 cycles:
>
> rotr_16:
> mov lp_count,8
> lp 2f
> ror r0,r0
> ror r0,r0
> 2: # end single insn loop
> j_s [blink]
>
>
> This patch has been tested with a cross-compiler to arc-linux hosted
> on x86_64-pc-linux-gnu and (partially) tested with the compile-only
> portions of the testsuite with no regressions. Ok for mainline, if
> your own testing shows no issues?
>
>
> 2023-10-07 Roger Sayle
>
> gcc/ChangeLog
> * config/arc/arc-protos.h (output_shift): Rename to...
> (output_shift_loop): Tweak API to take an explicit rtx_code.
> (arc_split_ashl): Prototype new function here.
> (arc_split_ashr): Likewise.
> (arc_split_lshr): Likewise.
> (arc_split_rotl): Likewise.
> (arc_split_rotr): Likewise.
> * config/arc/arc.cc (output_shift): Delete local prototype. Rename.
> (output_shift_loop): New function replacing output_shift to output
> a zero overheap loop for SImode shifts and rotates on ARC targets
> without barrel shifter (i.e. no hardware support for these insns).
> (arc_split_ashl): New helper function to split *ashlsi3_nobs.
> (arc_split_ashr): New helper function to split *ashrsi3_nobs.
> (arc_split_lshr): New helper function to split *lshrsi3_nobs.
> (arc_split_rotl): New helper function to split *rotlsi3_nobs.
> (arc_split_rotr): New helper function to split *rotrsi3_nobs.
> * config/arc/arc.md (any_shift_rotate): New define_code_iterator.
> (define_code_attr insn): New code attribute to map to pattern name.
> (si3): New expander unifying previous ashlsi3,
> ashrsi3 and lshrsi3 define_expands. Adds rotlsi3 and rotrsi3.
> (*si3_nobs): New
Re: [ARC PATCH] Split asl dst, 1, src into bset dst, 0, src to implement 1<
Hi Roger,
Indeed, I was missing the patch file.
Approved.
Thank you for your contribution,
Claudiu
On Sun, Oct 15, 2023 at 11:14 AM Roger Sayle wrote:
>
> I’ve done it again. ENOPATCH.
>
>
>
> From: Roger Sayle
> Sent: 15 October 2023 09:13
> To: 'gcc-patches@gcc.gnu.org'
> Cc: 'Claudiu Zissulescu'
> Subject: [ARC PATCH] Split asl dst,1,src into bset dst,0,src to implement
> 1<
>
>
>
>
> This patch adds a pre-reload splitter to arc.md, to use the bset (set
>
> specific bit instruction) to implement 1<
> on ARC processors that don't have a barrel shifter.
>
>
>
> Currently,
>
>
>
> int foo(int x) {
>
> return 1 << x;
>
> }
>
>
>
> when compiled with -O2 -mcpu=em is compiled as a loop:
>
>
>
> foo:mov_s r2,1;3
>
> and.f lp_count,r0, 0x1f
>
> lpnz2f
>
> add r2,r2,r2
>
> nop
>
> 2: # end single insn loop
>
> j_s.d [blink]
>
> mov_s r0,r2 ;4
>
>
>
> with this patch we instead generate a single instruction:
>
>
>
> foo:bsetr0,0,r0
>
> j_s [blink]
>
>
>
>
>
> Finger-crossed this passes Claudiu's nightly testing. This patch
>
> has been minimally tested by building a cross-compiler cc1 to
>
> arc-linux hosted on x86_64-pc-linux-gnu with no additional failures
>
> seen with make -k check. Ok for mainline? Thanks in advance.
>
>
>
>
>
> 2023-10-15 Roger Sayle
>
>
>
> gcc/ChangeLog
>
> * config/arc/arc.md (*ashlsi3_1): New pre-reload splitter to
>
> use bset dst,0,src to implement 1<
>
>
>
>
> Cheers,
>
> Roger
>
> --
>
>
[committed] arc: Refurbish add.f combiner patterns
Refurbish add compare patterns: use 'r' constraint, fix identation,
and fix pattern to match 'if (a+b) { ... }' constructions.
gcc/
* config/arc/arc.cc (arc_select_cc_mode): Match NEG code with
the first operand.
* config/arc/arc.md (addsi_compare): Make pattern canonical.
(addsi_compare_2): Fix identation, constraint letters.
(addsi_compare_3): Likewise.
gcc/testsuite/
* gcc.target/arc/add_f-combine.c: New test.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc| 2 +-
gcc/config/arc/arc.md| 25 ++--
gcc/testsuite/gcc.target/arc/add_f-combine.c | 15
3 files changed, 28 insertions(+), 14 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arc/add_f-combine.c
diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index ecc681cff61..00427d859cc 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -1562,7 +1562,7 @@ arc_select_cc_mode (enum rtx_code op, rtx x, rtx y)
/* add.f for if (a+b) */
if (mode == SImode
- && GET_CODE (y) == NEG
+ && GET_CODE (x) == NEG
&& (op == EQ || op == NE))
return CC_ZNmode;
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index cedb9517bb0..a936a8be53d 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -1102,34 +1102,33 @@ (define_insn "*commutative_binary_cmp0"
; the combiner needs this pattern
(define_insn "*addsi_compare"
[(set (reg:CC_ZN CC_REG)
- (compare:CC_ZN (match_operand:SI 0 "register_operand" "c")
- (neg:SI (match_operand:SI 1 "register_operand" "c"]
+ (compare:CC_ZN (neg:SI
+ (match_operand:SI 0 "register_operand" "r"))
+ (match_operand:SI 1 "register_operand" "r")))]
""
- "add.f 0,%0,%1"
+ "add.f\\t0,%0,%1"
[(set_attr "cond" "set")
(set_attr "type" "compare")
(set_attr "length" "4")])
-; for flag setting 'add' instructions like if (a+b < a) { ...}
-; the combiner needs this pattern
(define_insn "addsi_compare_2"
[(set (reg:CC_C CC_REG)
- (compare:CC_C (plus:SI (match_operand:SI 0 "register_operand" "c,c")
- (match_operand:SI 1 "nonmemory_operand"
"cL,Cal"))
- (match_dup 0)))]
+ (compare:CC_C (plus:SI (match_operand:SI 0 "register_operand" "r,r")
+ (match_operand:SI 1 "nonmemory_operand"
"rL,Cal"))
+ (match_dup 0)))]
""
- "add.f 0,%0,%1"
+ "add.f\\t0,%0,%1"
[(set_attr "cond" "set")
(set_attr "type" "compare")
(set_attr "length" "4,8")])
(define_insn "*addsi_compare_3"
[(set (reg:CC_C CC_REG)
- (compare:CC_C (plus:SI (match_operand:SI 0 "register_operand" "c")
- (match_operand:SI 1 "register_operand" "c"))
- (match_dup 1)))]
+ (compare:CC_C (plus:SI (match_operand:SI 0 "register_operand" "r")
+ (match_operand:SI 1 "register_operand" "r"))
+ (match_dup 1)))]
""
- "add.f 0,%0,%1"
+ "add.f\\t0,%0,%1"
[(set_attr "cond" "set")
(set_attr "type" "compare")
(set_attr "length" "4")])
diff --git a/gcc/testsuite/gcc.target/arc/add_f-combine.c
b/gcc/testsuite/gcc.target/arc/add_f-combine.c
new file mode 100644
index 000..cfa3676f7da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/add_f-combine.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-O1" } */
+
+/* Check if combiner is matching add.f patterns. */
+
+int a1 (int a, int b)
+{
+ if (a + b)
+{
+ return 1;
+}
+ return a + 2;
+}
+
+/* { dg-final { scan-assembler "add.f\\s+0,r\\d+,r\\d+" } } */
--
2.30.2
[committed 4/5] arc: Remove obsolete ccfsm instruction predication mechanism
Remove old ccfsm responsible for conditional execution support in ARC.
This machinery is not needed as the current gcc conditional execution
support is mature.
gcc/
* config/arc/arc-passes.def: Remove arc_ifcvt pass.
* config/arc/arc-protos.h (arc_ccfsm_branch_deleted_p): Remove.
(arc_ccfsm_record_branch_deleted): Likewise.
(arc_ccfsm_cond_exec_p): Likewise.
(arc_ccfsm): Likewise.
(arc_ccfsm_record_condition): Likewise.
(make_pass_arc_ifcvt): Likewise.
* config/arc/arc.cc (arc_ccfsm): Remove.
(arc_ccfsm_current): Likewise.
(ARC_CCFSM_BRANCH_DELETED_P): Likewise.
(ARC_CCFSM_RECORD_BRANCH_DELETED): Likewise.
(ARC_CCFSM_COND_EXEC_P): Likewise.
(CCFSM_ISCOMPACT): Likewise.
(CCFSM_DBR_ISCOMPACT): Likewise.
(machine_function): Remove ccfsm related fields.
(arc_ifcvt): Remove pass.
(arc_print_operand): Remove `#` punct operand and other ccfsm
related code.
(arc_ccfsm_advance): Remove.
(arc_ccfsm_at_label): Likewise.
(arc_ccfsm_record_condition): Likewise.
(arc_ccfsm_post_advance): Likewise.
(arc_ccfsm_branch_deleted_p): Likewise.
(arc_ccfsm_record_branch_deleted): Likewise.
(arc_ccfsm_cond_exec_p): Likewise.
(arc_get_ccfsm_cond): Likewise.
(arc_final_prescan_insn): Remove ccfsm references.
(arc_internal_label): Likewise.
(arc_reorg): Likewise.
(arc_output_libcall): Likewise.
* config/arc/arc.md: Remove ccfsm references and update related
instruction patterns.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc-passes.def | 6 -
gcc/config/arc/arc-protos.h | 7 -
gcc/config/arc/arc.cc | 830 +-
gcc/config/arc/arc.md | 118 +
4 files changed, 41 insertions(+), 920 deletions(-)
diff --git a/gcc/config/arc/arc-passes.def b/gcc/config/arc/arc-passes.def
index 0cb5d56a6d4..3f9222a8099 100644
--- a/gcc/config/arc/arc-passes.def
+++ b/gcc/config/arc/arc-passes.def
@@ -17,12 +17,6 @@
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
-/* First target dependent ARC if-conversion pass. */
-INSERT_PASS_AFTER (pass_delay_slots, 1, pass_arc_ifcvt);
-
-/* Second target dependent ARC if-conversion pass. */
-INSERT_PASS_BEFORE (pass_shorten_branches, 1, pass_arc_ifcvt);
-
/* Find annulled delay insns and convert them to use the appropriate
predicate. This allows branch shortening to size up these
instructions properly. */
diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
index 0e89ac7ae33..026ea99c9c6 100644
--- a/gcc/config/arc/arc-protos.h
+++ b/gcc/config/arc/arc-protos.h
@@ -52,8 +52,6 @@ extern bool arc_can_use_return_insn (void);
extern bool arc_split_move_p (rtx *);
#endif /* RTX_CODE */
-extern bool arc_ccfsm_branch_deleted_p (void);
-extern void arc_ccfsm_record_branch_deleted (void);
void arc_asm_output_aligned_decl_local (FILE *, tree, const char *,
unsigned HOST_WIDE_INT,
@@ -67,7 +65,6 @@ extern bool arc_raw_symbolic_reference_mentioned_p (rtx,
bool);
extern bool arc_is_longcall_p (rtx);
extern bool arc_is_shortcall_p (rtx);
extern bool valid_brcc_with_delay_p (rtx *);
-extern bool arc_ccfsm_cond_exec_p (void);
extern rtx disi_highpart (rtx);
extern int arc_adjust_insn_length (rtx_insn *, int, bool);
extern int arc_corereg_hazard (rtx, rtx);
@@ -76,9 +73,6 @@ extern int arc_write_ext_corereg (rtx);
extern rtx gen_acc1 (void);
extern rtx gen_acc2 (void);
extern bool arc_branch_size_unknown_p (void);
-struct arc_ccfsm;
-extern void arc_ccfsm_record_condition (rtx, bool, rtx_insn *,
- struct arc_ccfsm *);
extern void arc_expand_prologue (void);
extern void arc_expand_epilogue (int);
extern void arc_init_expanders (void);
@@ -104,5 +98,4 @@ extern bool arc_is_jli_call_p (rtx);
extern void arc_file_end (void);
extern bool arc_is_secure_call_p (rtx);
-rtl_opt_pass * make_pass_arc_ifcvt (gcc::context *ctxt);
rtl_opt_pass * make_pass_arc_predicate_delay_insns (gcc::context *ctxt);
diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index a1428eb41c3..ecc681cff61 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -101,16 +101,6 @@ HARD_REG_SET overrideregs;
/* Array of valid operand punctuation characters. */
char arc_punct_chars[256];
-/* State used by arc_ccfsm_advance to implement conditional execution. */
-struct GTY (()) arc_ccfsm
-{
- int state;
- int cc;
- rtx cond;
- rtx_insn *target_insn;
- int target_label;
-};
-
/* Status of the IRQ_CTRL_AUX register. */
typedef struct irq_ctrl_saved_t
{
@@ -143,36 +133,6 @@ static irq_ctrl_saved_t irq_ctrl_saved;
/* Number of registers in second bank for FIRQ support. */
static int rgf_banked_register_count;
-#define arc_ccfsm_curren
[committed 5/5] arc: Update tests predicates when using linux toolchain.
gcc/testsuite:
* gcc.target/arc/enter-dw2-1.c: Remove tests when using linux
build.
* gcc.target/arc/tls-ld.c: Update test.
* gcc.target/arc/tls-le.c: Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/testsuite/gcc.target/arc/enter-dw2-1.c | 18 +-
gcc/testsuite/gcc.target/arc/tls-ld.c | 3 +--
gcc/testsuite/gcc.target/arc/tls-le.c | 2 +-
3 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/gcc/testsuite/gcc.target/arc/enter-dw2-1.c
b/gcc/testsuite/gcc.target/arc/enter-dw2-1.c
index 25d03562198..653ea7231be 100644
--- a/gcc/testsuite/gcc.target/arc/enter-dw2-1.c
+++ b/gcc/testsuite/gcc.target/arc/enter-dw2-1.c
@@ -16,13 +16,13 @@ void foo (void)
}
-/* { dg-final { scan-assembler-times "enter_s" 1 } } */
+/* { dg-final { scan-assembler-times "enter_s" 1 {xfail *-linux-* } } } */
/* { dg-final { scan-assembler-times "\.cfi_def_cfa_offset 32" 1 } } */
-/* { dg-final { scan-assembler-times "\.cfi_offset 31, -32" 1 } } */
-/* { dg-final { scan-assembler-times "\.cfi_offset 13, -28" 1 } } */
-/* { dg-final { scan-assembler-times "\.cfi_offset 14, -24" 1 } } */
-/* { dg-final { scan-assembler-times "\.cfi_offset 15, -20" 1 } } */
-/* { dg-final { scan-assembler-times "\.cfi_offset 16, -16" 1 } } */
-/* { dg-final { scan-assembler-times "\.cfi_offset 17, -12" 1 } } */
-/* { dg-final { scan-assembler-times "\.cfi_offset 18, -8" 1 } } */
-/* { dg-final { scan-assembler-times "\.cfi_offset 19, -4" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 31, -32" 1 {xfail *-linux-*
} } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 13, -28" 1 {xfail *-linux-*
} } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 14, -24" 1 {xfail *-linux-*
} } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 15, -20" 1 {xfail *-linux-*
} } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 16, -16" 1 {xfail *-linux-*
} } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 17, -12" 1 {xfail *-linux-*
} } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 18, -8" 1 {xfail *-linux-*
} } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 19, -4" 1 {xfail *-linux-*
} } } */
diff --git a/gcc/testsuite/gcc.target/arc/tls-ld.c
b/gcc/testsuite/gcc.target/arc/tls-ld.c
index 68ab9bf809c..47c71f5d273 100644
--- a/gcc/testsuite/gcc.target/arc/tls-ld.c
+++ b/gcc/testsuite/gcc.target/arc/tls-ld.c
@@ -13,6 +13,5 @@ int *ae2 (void)
return
}
-/* { dg-final { scan-assembler "add\\s+r0,pcl,@.tbss@tlsgd" } } */
+/* { dg-final { scan-assembler "add\\s+r0,pcl,@e2@tlsgd" } } */
/* { dg-final { scan-assembler "bl\\s+@__tls_get_addr@plt" } } */
-/* { dg-final { scan-assembler "add_s\\s+r0,r0,@e2@dtpoff" } } */
diff --git a/gcc/testsuite/gcc.target/arc/tls-le.c
b/gcc/testsuite/gcc.target/arc/tls-le.c
index ae3089b5070..6deca1a133d 100644
--- a/gcc/testsuite/gcc.target/arc/tls-le.c
+++ b/gcc/testsuite/gcc.target/arc/tls-le.c
@@ -13,4 +13,4 @@ int *ae2 (void)
return
}
-/* { dg-final { scan-assembler "add r0,r25,@e2@tpoff" } } */
+/* { dg-final { scan-assembler "add\\sr0,r25,@e2@tpoff" } } */
--
2.30.2
[committed 3/5] arc: Remove '^' print punct character
The '^' was used to print '@' character in the ouput assembly. This is
not anylonger required by the ARC binutils. Remove it.
gcc/
* config/arc/arc.cc (arc_init): Remove '^' punct char.
(arc_print_operand): Remove related code.
* config/arc/arc.md: Update patterns which uses '%&'.
gcc/testsuite/
* gcc.target/arc/loop-3.c: Update test.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc | 9 -
gcc/config/arc/arc.md | 18 +-
gcc/testsuite/gcc.target/arc/loop-3.c | 2 +-
3 files changed, 10 insertions(+), 19 deletions(-)
diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index 5e597d1bfeb..a1428eb41c3 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -1130,7 +1130,6 @@ arc_init (void)
arc_punct_chars['*'] = 1;
arc_punct_chars['?'] = 1;
arc_punct_chars['!'] = 1;
- arc_punct_chars['^'] = 1;
arc_punct_chars['+'] = 1;
arc_punct_chars['_'] = 1;
}
@@ -4529,7 +4528,6 @@ static int output_sdata = 0;
'V': cache bypass indicator for volatile
'P'
'F'
-'^'
'O': Operator
'o': original symbol - no @ prepending. */
@@ -4953,14 +4951,7 @@ arc_print_operand (FILE *file, rtx x, int code)
case 'F':
fputs (reg_names[REGNO (x)]+1, file);
return;
-case '^':
- /* This punctuation character is needed because label references are
- printed in the output template using %l. This is a front end
- character, and when we want to emit a '@' before it, we have to use
- this '^'. */
- fputc('@',file);
- return;
case 'O':
/* Output an operator. */
switch (GET_CODE (x))
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 2a3ff05b66b..945cc4042d1 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -3934,9 +3934,9 @@ (define_insn "*branch_insn"
{
arc_ccfsm_record_condition (operands[1], false, insn, 0);
if (get_attr_length (insn) == 2)
-return \"b%d1%? %^%l0\";
+return \"b%d1%?\\t%l0\";
else
-return \"b%d1%# %^%l0\";
+return \"b%d1%#\\t%l0\";
}
}"
[(set_attr "type" "branch")
@@ -3984,9 +3984,9 @@ (define_insn "*rev_branch_insn"
{
arc_ccfsm_record_condition (operands[1], true, insn, 0);
if (get_attr_length (insn) == 2)
-return \"b%D1%? %^%l0\";
+return \"b%D1%?\\t%l0\";
else
-return \"b%D1%# %^%l0\";
+return \"b%D1%#\\t%l0\";
}
}"
[(set_attr "type" "branch")
@@ -4026,7 +4026,7 @@ (define_expand "jump"
(define_insn "jump_i"
[(set (pc) (label_ref (match_operand 0 "" "")))]
"!TARGET_LONG_CALLS_SET || !CROSSING_JUMP_P (insn)"
- "b%!%* %^%l0"
+ "b%!%*\\t%l0"
[(set_attr "type" "uncond_branch")
(set (attr "iscompact")
(if_then_else (match_test "get_attr_length (insn) == 2")
@@ -4990,13 +4990,13 @@ (define_insn "cbranchsi4_scratch"
"*
switch (get_attr_length (insn))
{
- case 2: return \"br%d0%? %1, %2, %^%l3\";
- case 4: return \"br%d0%* %1, %B2, %^%l3\";
+ case 2: return \"br%d0%?\\t%1,%2,%l3\";
+ case 4: return \"br%d0%*\\t%1,%B2,%l3\";
case 8: if (!brcc_nolimm_operator (operands[0], VOIDmode))
-return \"br%d0%* %1, %B2, %^%l3\";
+return \"br%d0%*\\t%1,%B2,%l3\";
/* FALLTHRU */
case 6: case 10:
- case 12:return \"cmp%? %1, %B2\\n\\tb%d0%* %^%l3 ;br%d0 out of range\";
+ case 12:return \"cmp%? %1, %B2\\n\\tb%d0%*\\t%l3 ;br%d0 out of range\";
default: fprintf (stderr, \"unexpected length %d\\n\", get_attr_length
(insn)); fflush (stderr); gcc_unreachable ();
}
"
diff --git a/gcc/testsuite/gcc.target/arc/loop-3.c
b/gcc/testsuite/gcc.target/arc/loop-3.c
index 7f55e2f43fa..ae0d6110f18 100644
--- a/gcc/testsuite/gcc.target/arc/loop-3.c
+++ b/gcc/testsuite/gcc.target/arc/loop-3.c
@@ -23,5 +23,5 @@ void fn1(void)
}
}
-/* { dg-final { scan-assembler "bne.*@.L2" } } */
+/* { dg-final { scan-assembler "bne.*\\.L2" } } */
/* { dg-final { scan-assembler-not "add.eq" } } */
--
2.30.2
[committed 2/5] arc: Update/remove ARC specific tests
Update tests and remove old mtune-* tests.
gcc/testsuite
* gcc.target/arc/add_n-combine.c: Recognize add2 instruction.
* gcc.target/arc/firq-4.c: FP register is a temp reg. Update test.
* gcc.target/arc/firq-6.c: Likewise.
* gcc.target/arc/mtune-ARC600.c: Remove test.
* gcc.target/arc/mtune-ARC601.c: Likewise.
* gcc.target/arc/mtune-ARC700-xmac: Likewise.
* gcc.target/arc/mtune-ARC700.c: Likewise.
* gcc.target/arc/mtune-ARC725D.c: Likewise.
* gcc.target/arc/mtune-ARC750D.c: Likewise.
* gcc.target/arc/uncached-7.c: Set it to XFAIL.
Signed-off-by: Claudiu Zissulescu
---
gcc/testsuite/gcc.target/arc/add_n-combine.c | 2 +-
gcc/testsuite/gcc.target/arc/firq-4.c | 1 -
gcc/testsuite/gcc.target/arc/firq-6.c | 1 -
gcc/testsuite/gcc.target/arc/mtune-ARC600.c| 4
gcc/testsuite/gcc.target/arc/mtune-ARC601.c| 4
gcc/testsuite/gcc.target/arc/mtune-ARC700-xmac | 4
gcc/testsuite/gcc.target/arc/mtune-ARC700.c| 4
gcc/testsuite/gcc.target/arc/mtune-ARC725D.c | 4
gcc/testsuite/gcc.target/arc/mtune-ARC750D.c | 4
gcc/testsuite/gcc.target/arc/uncached-7.c | 2 +-
10 files changed, 2 insertions(+), 28 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/arc/mtune-ARC600.c
delete mode 100644 gcc/testsuite/gcc.target/arc/mtune-ARC601.c
delete mode 100644 gcc/testsuite/gcc.target/arc/mtune-ARC700-xmac
delete mode 100644 gcc/testsuite/gcc.target/arc/mtune-ARC700.c
delete mode 100644 gcc/testsuite/gcc.target/arc/mtune-ARC725D.c
delete mode 100644 gcc/testsuite/gcc.target/arc/mtune-ARC750D.c
diff --git a/gcc/testsuite/gcc.target/arc/add_n-combine.c
b/gcc/testsuite/gcc.target/arc/add_n-combine.c
index 84e261ece8f..fd311b3839c 100644
--- a/gcc/testsuite/gcc.target/arc/add_n-combine.c
+++ b/gcc/testsuite/gcc.target/arc/add_n-combine.c
@@ -46,5 +46,5 @@ void f() {
}
/* { dg-final { scan-assembler "@at1\\+1" } } */
-/* { dg-final { scan-assembler "@at2\\+2" } } */
+/* { dg-final { scan-assembler "add2" } } */
/* { dg-final { scan-assembler "add3" } } */
diff --git a/gcc/testsuite/gcc.target/arc/firq-4.c
b/gcc/testsuite/gcc.target/arc/firq-4.c
index 969ee796f03..cd939bf8ca3 100644
--- a/gcc/testsuite/gcc.target/arc/firq-4.c
+++ b/gcc/testsuite/gcc.target/arc/firq-4.c
@@ -28,4 +28,3 @@ handler1 (void)
/* { dg-final { scan-assembler-not "fp,\\\[sp" } } */
/* { dg-final { scan-assembler-not "push.*fp" } } */
-/* { dg-final { scan-assembler "mov_s.*fp,sp" } } */
diff --git a/gcc/testsuite/gcc.target/arc/firq-6.c
b/gcc/testsuite/gcc.target/arc/firq-6.c
index 9421200d630..df04e46dd31 100644
--- a/gcc/testsuite/gcc.target/arc/firq-6.c
+++ b/gcc/testsuite/gcc.target/arc/firq-6.c
@@ -18,4 +18,3 @@ handler1 (void)
"r25", "fp");
}
/* { dg-final { scan-assembler-not
"(s|l)(t|d)d.*r\[0-9\]+,\\\[sp,\[0-9\]+\\\]" } } */
-/* { dg-final { scan-assembler "mov_s.*fp,sp" } } */
diff --git a/gcc/testsuite/gcc.target/arc/mtune-ARC600.c
b/gcc/testsuite/gcc.target/arc/mtune-ARC600.c
deleted file mode 100644
index a483d1435ca..000
--- a/gcc/testsuite/gcc.target/arc/mtune-ARC600.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-mtune=ARC600" } */
-
-/* { dg-final { scan-assembler ".cpu ARC700" } } */
diff --git a/gcc/testsuite/gcc.target/arc/mtune-ARC601.c
b/gcc/testsuite/gcc.target/arc/mtune-ARC601.c
deleted file mode 100644
index ed57bd7092d..000
--- a/gcc/testsuite/gcc.target/arc/mtune-ARC601.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-mtune=ARC601" } */
-
-/* { dg-final { scan-assembler ".cpu ARC700" } } */
diff --git a/gcc/testsuite/gcc.target/arc/mtune-ARC700-xmac
b/gcc/testsuite/gcc.target/arc/mtune-ARC700-xmac
deleted file mode 100644
index 2f1e137be4d..000
--- a/gcc/testsuite/gcc.target/arc/mtune-ARC700-xmac
+++ /dev/null
@@ -1,4 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-mtune=ARC700-xmac" } */
-
-/* { dg-final { scan-assembler ".cpu ARC700" } } */
diff --git a/gcc/testsuite/gcc.target/arc/mtune-ARC700.c
b/gcc/testsuite/gcc.target/arc/mtune-ARC700.c
deleted file mode 100644
index 851ea7305e0..000
--- a/gcc/testsuite/gcc.target/arc/mtune-ARC700.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-mtune=ARC700" } */
-
-/* { dg-final { scan-assembler ".cpu ARC700" } } */
diff --git a/gcc/testsuite/gcc.target/arc/mtune-ARC725D.c
b/gcc/testsuite/gcc.target/arc/mtune-ARC725D.c
deleted file mode 100644
index e2aa4846291..000
--- a/gcc/testsuite/gcc.target/arc/mtune-ARC725D.c
+++ /dev/null
@@ -1,4 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-mtune=ARC725D" } */
-
-/* { dg-final { scan-assembler ".cpu ARC700"
[committed 1/5] arc: Remove unused/incomplete alignment assembly annotation.
Removes '&' print operant punct character, disable -mannotate-align
option and clean up the port.
gcc/
* config/arc/arc-protos.h (arc_clear_unalign): Remove.
(arc_toggle_unalign): Likewise.
* config/arc/arc.cc (machine_function) Remove unalign.
(arc_init): Remove `&` punct character.
(arc_print_operand): Remove `&` related functions.
(arc_verify_short): Update function's number of parameters.
(output_short_suffix): Update function.
(arc_short_long): Likewise.
(arc_clear_unalign): Remove.
(arc_toggle_unalign): Likewise.
* config/arc/arc.h (ASM_OUTPUT_CASE_END): Remove.
(ASM_OUTPUT_ALIGN): Update.
* config/arc/arc.md: Remove all `%&` references.
* config/arc/arc.opt (mannotate-align): Ignore option.
* doc/invoke.texi (mannotate-align): Update description.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc-protos.h | 2 -
gcc/config/arc/arc.cc | 33 ++
gcc/config/arc/arc.h| 16 -
gcc/config/arc/arc.md | 125 ++--
gcc/config/arc/arc.opt | 4 +-
gcc/doc/invoke.texi | 3 +-
6 files changed, 70 insertions(+), 113 deletions(-)
diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
index 5ce92ba261f..0e89ac7ae33 100644
--- a/gcc/config/arc/arc-protos.h
+++ b/gcc/config/arc/arc-protos.h
@@ -83,8 +83,6 @@ extern void arc_expand_prologue (void);
extern void arc_expand_epilogue (int);
extern void arc_init_expanders (void);
extern int arc_check_millicode (rtx op, int offset, int load_p);
-extern void arc_clear_unalign (void);
-extern void arc_toggle_unalign (void);
extern void split_subsi (rtx *);
extern void arc_split_move (rtx *);
extern const char *arc_short_long (rtx_insn *insn, const char *, const char *);
diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index 2a59618ab6a..5e597d1bfeb 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -423,8 +423,6 @@ typedef struct GTY (()) machine_function
{
unsigned int fn_type;
struct arc_frame_info frame_info;
- /* To keep track of unalignment caused by short insns. */
- int unalign;
struct arc_ccfsm ccfsm_current;
/* Map from uid to ccfsm state during branch shortening. */
rtx ccfsm_current_insn;
@@ -1133,7 +1131,6 @@ arc_init (void)
arc_punct_chars['?'] = 1;
arc_punct_chars['!'] = 1;
arc_punct_chars['^'] = 1;
- arc_punct_chars['&'] = 1;
arc_punct_chars['+'] = 1;
arc_punct_chars['_'] = 1;
}
@@ -5011,10 +5008,7 @@ arc_print_operand (FILE *file, rtx x, int code)
return;
}
break;
-case '&':
- if (TARGET_ANNOTATE_ALIGN)
- fprintf (file, "; unalign: %d", cfun->machine->unalign);
- return;
+
case '+':
if (TARGET_V2)
fputs ("m", file);
@@ -5682,7 +5676,7 @@ arc_ccfsm_cond_exec_p (void)
If CHECK_ATTR is greater than 0, check the iscompact attribute first. */
static int
-arc_verify_short (rtx_insn *insn, int, int check_attr)
+arc_verify_short (rtx_insn *insn, int check_attr)
{
enum attr_iscompact iscompact;
@@ -5697,8 +5691,7 @@ arc_verify_short (rtx_insn *insn, int, int check_attr)
}
/* When outputting an instruction (alternative) that can potentially be short,
- output the short suffix if the insn is in fact short, and update
- cfun->machine->unalign accordingly. */
+ output the short suffix if the insn is in fact short. */
static void
output_short_suffix (FILE *file)
@@ -5707,10 +5700,9 @@ output_short_suffix (FILE *file)
if (!insn)
return;
- if (arc_verify_short (insn, cfun->machine->unalign, 1))
+ if (arc_verify_short (insn, 1))
{
fprintf (file, "_s");
- cfun->machine->unalign ^= 2;
}
/* Restore recog_operand. */
extract_insn_cached (insn);
@@ -10056,21 +10048,6 @@ arc_check_millicode (rtx op, int offset, int load_p)
return 1;
}
-/* Accessor functions for cfun->machine->unalign. */
-
-void
-arc_clear_unalign (void)
-{
- if (cfun)
-cfun->machine->unalign = 0;
-}
-
-void
-arc_toggle_unalign (void)
-{
- cfun->machine->unalign ^= 2;
-}
-
/* Operands 0..2 are the operands of a subsi which uses a 12 bit
constant in operand 1, but which would require a LIMM because of
operand mismatch.
@@ -10309,7 +10286,7 @@ arc_split_move (rtx *operands)
const char *
arc_short_long (rtx_insn *insn, const char *s_tmpl, const char *l_tmpl)
{
- int is_short = arc_verify_short (insn, cfun->machine->unalign, -1);
+ int is_short = arc_verify_short (insn, -1);
extract_constrain_insn_cached (insn);
return is_short ? s_tmpl : l_tmpl;
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 8daae41ff5b..5877389a10d 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -1312,20 +1312,6 @@ do {
Re: [ARC PATCH] Split SImode shifts pre-reload on !TARGET_BARREL_SHIFTER.
Hi Roger,
The patch as it is passed the validation, and it is in general OK.
Although it doesn't address the elephant in the room, namely
output_shift function, it is a welcome cleanup.
I would like you to split the patch in two. One which deals with
improvements on shifts in absence of a barrel shifter, and one which
addresses the default instruction length, as they can be seen as
separate work. Please feel free to commit resulting patches to the
mainline.
Thank you for your contribution,
Claudiu
On Thu, Sep 28, 2023 at 2:27 PM Roger Sayle wrote:
>
>
> Hi Claudiu,
> It was great meeting up with you and the Synopsys ARC team at the
> GNU tools Cauldron in Cambridge.
>
> This patch is the first in a series to improve SImode and DImode
> shifts and rotates in the ARC backend. This first piece splits
> SImode shifts, for !TARGET_BARREL_SHIFTER targets, after combine
> and before reload, in the split1 pass, as suggested by the FIXME
> comment above output_shift in arc.cc. To do this I've copied the
> implementation of the x86_pre_reload_split function from i386
> backend, and renamed it arc_pre_reload_split.
>
> Although the actual implementations of shifts remain the same
> (as in output_shift), having them as explicit instructions in
> the RTL stream allows better scheduling and use of compact forms
> when available. The benefits can be seen in two short examples
> below.
>
> For the function:
> unsigned int foo(unsigned int x, unsigned int y) {
> return y << 2;
> }
>
> GCC with -O2 -mcpu=em would previously generate:
> foo:add r1,r1,r1
> add r1,r1,r1
> j_s.d [blink]
> mov_s r0,r1 ;4
> and with this patch now generates:
> foo:asl_s r0,r1
> j_s.d [blink]
> asl_s r0,r0
>
> Notice the original (from shift_si3's output_shift) requires the
> shift sequence to be monolithic with the same destination register
> as the source (requiring an extra mov_s). The new version can
> eliminate this move, and schedule the second asl in the branch
> delay slot of the return.
>
> For the function:
> int x,y,z;
>
> void bar()
> {
> x <<= 3;
> y <<= 3;
> z <<= 3;
> }
>
> GCC -O2 -mcpu=em currently generates:
> bar:push_s r13
> ld.as r12,[gp,@x@sda] ;23
> ld.as r3,[gp,@y@sda] ;23
> mov r2,0
> add3 r12,r2,r12
> mov r2,0
> add3 r3,r2,r3
> ld.as r2,[gp,@z@sda] ;23
> st.as r12,[gp,@x@sda] ;26
> mov r13,0
> add3 r2,r13,r2
> st.as r3,[gp,@y@sda] ;26
> st.as r2,[gp,@z@sda] ;26
> j_s.d [blink]
> pop_s r13
>
> where each shift by 3, uses ARC's add3 instruction, which is similar
> to x86's lea implementing x = (y<<3) + z, but requires the value zero
> to be placed in a temporary register "z". Splitting this before reload
> allows these pseudos to be shared/reused. With this patch, we get
>
> bar:ld.as r2,[gp,@x@sda] ;23
> mov_s r3,0;3
> add3r2,r3,r2
> ld.as r3,[gp,@y@sda] ;23
> st.as r2,[gp,@x@sda] ;26
> ld.as r2,[gp,@z@sda] ;23
> mov_s r12,0 ;3
> add3r3,r12,r3
> add3r2,r12,r2
> st.as r3,[gp,@y@sda] ;26
> st.as r2,[gp,@z@sda] ;26
> j_s [blink]
>
> Unfortunately, register allocation means that we only share two of the
> three "mov_s z,0", but this is sufficient to reduce register pressure
> enough to avoid spilling r13 in the prologue/epilogue.
>
> This patch also contains a (latent?) bug fix. The implementation of
> the default insn "length" attribute, assumes instructions of type
> "shift" have two input operands and accesses operands[2], hence
> specializations of shifts that don't have a operands[2], need to be
> categorized as type "unary" (which results in the correct length).
>
> This patch has been tested on a cross-compiler to arc-elf (hosted on
> x86_64-pc-linux-gnu), but because I've an incomplete tool chain many
> of the regression test fail, but there are no new failures with new
> test cases added below. If you can confirm that there are no issues
> from additional testing, is this OK for mainline?
>
> Finally a quick technical question. ARC's zero overhead loops require
> at least two instructions in the loop, so currently the backend's
> implementation of shr20 pads the loop body with a "nop".
>
> lshr20: mov.f lp_count, 20
> lpnz2f
> lsr r0,r0
> nop
> 2: # end single insn loop
> j_s [blink]
>
> could this be more efficiently implemented as:
>
> lshr20: mov lp_count, 10
> lp 2f
> lsr_s r0,r0
> lsr_s r0,r0
> 2: # end single insn loop
> j_s [blink]
>
> i.e. half the number of iterations, but doing twice as much useful
> work in each iteration? Or might the nop be free on advanced
> microarchitectures, and/or the consecutive dependent shifts cause
> a pipeline stall? It would be nice to fuse loops
Re: [ARC PATCH] Split SImode shifts pre-reload on !TARGET_BARREL_SHIFTER.
Hi Roger,
It is not necessary to do any mods on your patch. I've just answered
the questions which you asked me. The adds are faster for the ARC CPUs
which are still in production, and I suppose we can leverage the LP
instruction use with DBNZ instructions for implementing loops. I'll
come back to you asap, after I've got the nightly results :)
Thank you,
Claudiu
On Tue, Oct 3, 2023 at 6:34 PM Roger Sayle wrote:
>
>
> Hi Claudiu,
> Thanks for the answers to my technical questions.
> If you'd prefer to update arc.md's add3 pattern first,
> I'm happy to update/revise my patch based on this
> and your feedback, for example preferring add over
> asl_s (or controlling this choice with -Os).
>
> Thanks again.
> Roger
> --
>
> > -Original Message-
> > From: Claudiu Zissulescu
> > Sent: 03 October 2023 15:26
> > To: Roger Sayle ; gcc-patches@gcc.gnu.org
> > Subject: RE: [ARC PATCH] Split SImode shifts pre-reload on
> > !TARGET_BARREL_SHIFTER.
> >
> > Hi Roger,
> >
> > It was nice to meet you too.
> >
> > Thank you in looking into the ARC's non-Barrel Shifter configurations. I
> will dive
> > into your patch asap, but before starting here are a few of my comments:
> >
> > -Original Message-----
> > From: Roger Sayle
> > Sent: Thursday, September 28, 2023 2:27 PM
> > To: gcc-patches@gcc.gnu.org
> > Cc: Claudiu Zissulescu
> > Subject: [ARC PATCH] Split SImode shifts pre-reload on
> > !TARGET_BARREL_SHIFTER.
> >
> >
> > Hi Claudiu,
> > It was great meeting up with you and the Synopsys ARC team at the GNU
> tools
> > Cauldron in Cambridge.
> >
> > This patch is the first in a series to improve SImode and DImode shifts
> and rotates
> > in the ARC backend. This first piece splits SImode shifts, for
> > !TARGET_BARREL_SHIFTER targets, after combine and before reload, in the
> split1
> > pass, as suggested by the FIXME comment above output_shift in arc.cc. To
> do
> > this I've copied the implementation of the x86_pre_reload_split function
> from
> > i386 backend, and renamed it arc_pre_reload_split.
> >
> > Although the actual implementations of shifts remain the same (as in
> > output_shift), having them as explicit instructions in the RTL stream
> allows better
> > scheduling and use of compact forms when available. The benefits can be
> seen in
> > two short examples below.
> >
> > For the function:
> > unsigned int foo(unsigned int x, unsigned int y) {
> > return y << 2;
> > }
> >
> > GCC with -O2 -mcpu=em would previously generate:
> > foo:add r1,r1,r1
> > add r1,r1,r1
> > j_s.d [blink]
> > mov_s r0,r1 ;4
> >
> > [CZI] The move shouldn't be generated indeed. The use of ADDs are slightly
> > beneficial for older ARCv1 arches.
> >
> > and with this patch now generates:
> > foo:asl_s r0,r1
> > j_s.d [blink]
> > asl_s r0,r0
> >
> > [CZI] Nice. This new sequence is as fast as we can get for our ARCv2 cpus.
> >
> > Notice the original (from shift_si3's output_shift) requires the shift
> sequence to be
> > monolithic with the same destination register as the source (requiring an
> extra
> > mov_s). The new version can eliminate this move, and schedule the second
> asl in
> > the branch delay slot of the return.
> >
> > For the function:
> > int x,y,z;
> >
> > void bar()
> > {
> > x <<= 3;
> > y <<= 3;
> > z <<= 3;
> > }
> >
> > GCC -O2 -mcpu=em currently generates:
> > bar:push_s r13
> > ld.as r12,[gp,@x@sda] ;23
> > ld.as r3,[gp,@y@sda] ;23
> > mov r2,0
> > add3 r12,r2,r12
> > mov r2,0
> > add3 r3,r2,r3
> > ld.as r2,[gp,@z@sda] ;23
> > st.as r12,[gp,@x@sda] ;26
> > mov r13,0
> > add3 r2,r13,r2
> > st.as r3,[gp,@y@sda] ;26
> > st.as r2,[gp,@z@sda] ;26
> > j_s.d [blink]
> > pop_s r13
> >
> > where each shift by 3, uses ARC's add3 instruction, which is similar to
> x86's lea
> > implementing x = (y<<3) + z, but requires the value zero to be placed in a
> > temporary register "z". Splitting this before reload allows these pseudos
> to be
> > shared/reused. With this patch, we get
> >
> > bar:ld.as r2,[gp,@x@sda] ;23
> > mov_s r3,0;3
> > add3r2,r3,r2
> >
RE: [ARC PATCH] Split SImode shifts pre-reload on !TARGET_BARREL_SHIFTER.
Hi Roger,
It was nice to meet you too.
Thank you in looking into the ARC's non-Barrel Shifter configurations. I will
dive into your patch asap, but before starting here are a few of my comments:
-Original Message-
From: Roger Sayle
Sent: Thursday, September 28, 2023 2:27 PM
To: gcc-patches@gcc.gnu.org
Cc: Claudiu Zissulescu
Subject: [ARC PATCH] Split SImode shifts pre-reload on !TARGET_BARREL_SHIFTER.
Hi Claudiu,
It was great meeting up with you and the Synopsys ARC team at the GNU tools
Cauldron in Cambridge.
This patch is the first in a series to improve SImode and DImode shifts and
rotates in the ARC backend. This first piece splits SImode shifts, for
!TARGET_BARREL_SHIFTER targets, after combine and before reload, in the split1
pass, as suggested by the FIXME comment above output_shift in arc.cc. To do
this I've copied the implementation of the x86_pre_reload_split function from
i386 backend, and renamed it arc_pre_reload_split.
Although the actual implementations of shifts remain the same (as in
output_shift), having them as explicit instructions in the RTL stream allows
better scheduling and use of compact forms when available. The benefits can be
seen in two short examples below.
For the function:
unsigned int foo(unsigned int x, unsigned int y) {
return y << 2;
}
GCC with -O2 -mcpu=em would previously generate:
foo:add r1,r1,r1
add r1,r1,r1
j_s.d [blink]
mov_s r0,r1 ;4
[CZI] The move shouldn't be generated indeed. The use of ADDs are slightly
beneficial for older ARCv1 arches.
and with this patch now generates:
foo:asl_s r0,r1
j_s.d [blink]
asl_s r0,r0
[CZI] Nice. This new sequence is as fast as we can get for our ARCv2 cpus.
Notice the original (from shift_si3's output_shift) requires the shift sequence
to be monolithic with the same destination register as the source (requiring an
extra mov_s). The new version can eliminate this move, and schedule the second
asl in the branch delay slot of the return.
For the function:
int x,y,z;
void bar()
{
x <<= 3;
y <<= 3;
z <<= 3;
}
GCC -O2 -mcpu=em currently generates:
bar:push_s r13
ld.as r12,[gp,@x@sda] ;23
ld.as r3,[gp,@y@sda] ;23
mov r2,0
add3 r12,r2,r12
mov r2,0
add3 r3,r2,r3
ld.as r2,[gp,@z@sda] ;23
st.as r12,[gp,@x@sda] ;26
mov r13,0
add3 r2,r13,r2
st.as r3,[gp,@y@sda] ;26
st.as r2,[gp,@z@sda] ;26
j_s.d [blink]
pop_s r13
where each shift by 3, uses ARC's add3 instruction, which is similar to x86's
lea implementing x = (y<<3) + z, but requires the value zero to be placed in a
temporary register "z". Splitting this before reload allows these pseudos to
be shared/reused. With this patch, we get
bar:ld.as r2,[gp,@x@sda] ;23
mov_s r3,0;3
add3r2,r3,r2
ld.as r3,[gp,@y@sda] ;23
st.as r2,[gp,@x@sda] ;26
ld.as r2,[gp,@z@sda] ;23
mov_s r12,0 ;3
add3r3,r12,r3
add3r2,r12,r2
st.as r3,[gp,@y@sda] ;26
st.as r2,[gp,@z@sda] ;26
j_s [blink]
[CZI] Looks great, but it also shows that I've forgot to add to ADD3
instruction the Ra,LIMM,RC variant, which will lead to have instead of
mov_s r3,0;3
add3r2,r3,r2
Only this add3,0,r2, Indeed it is longer instruction but faster.
Unfortunately, register allocation means that we only share two of the three
"mov_s z,0", but this is sufficient to reduce register pressure enough to avoid
spilling r13 in the prologue/epilogue.
This patch also contains a (latent?) bug fix. The implementation of the
default insn "length" attribute, assumes instructions of type "shift" have two
input operands and accesses operands[2], hence specializations of shifts that
don't have a operands[2], need to be categorized as type "unary" (which results
in the correct length).
[CZI] The ARC types need an upgrade too.
This patch has been tested on a cross-compiler to arc-elf (hosted on
x86_64-pc-linux-gnu), but because I've an incomplete tool chain many of the
regression test fail, but there are no new failures with new test cases added
below. If you can confirm that there are no issues from additional testing, is
this OK for mainline?
Finally a quick technical question. ARC's zero overhead loops require at least
two instructions in the loop, so currently the backend's implementation of
shr20 pads the loop body with a "nop".
lshr20: mov.f lp_count, 20
lpnz2f
lsr r0,r0
nop
2: # end single insn loop
j_s [blink]
[CZI] The ZOLs (LP instructions) are not great when dealing with short loop
blocks. Hence, the NOP instruction. Personally, I don't fancy using the LP
instruction in this case,
RE: [ARC PATCH] Use rlc r0, 0 to implement scc_ltu (i.e. carry_flag ? 1 : 0)
Hi Roger, Everything is good. Ok for mainline. Thank you for your contribution, Claudiu -Original Message- From: Claudiu Zissulescu Sent: Sunday, October 1, 2023 5:33 PM To: Jeff Law ; Roger Sayle Cc: gcc-patches@gcc.gnu.org Subject: RE: [ARC PATCH] Use rlc r0, 0 to implement scc_ltu (i.e. carry_flag ? 1 : 0) I'll add it to our nightly. Just to be sure I’ll let you know asap it's status. Roger, you can always use Synopsys free nsim simulator which you can find it on Synopsys website. Thanks, Claudiu -Original Message- From: Jeff Law Sent: Saturday, September 30, 2023 1:02 AM To: Roger Sayle ; Claudiu Zissulescu Cc: gcc-patches@gcc.gnu.org Subject: Re: [ARC PATCH] Use rlc r0, 0 to implement scc_ltu (i.e. carry_flag ? 1 : 0) On 9/29/23 15:11, Roger Sayle wrote: > > Hi Claudiu, >> The patch looks sane. Have you run dejagnu test suite? > > I've not yet managed to set up an emulator or compile the entire > toolchain, so my dejagnu results are only useful for catching > (serious) problems in the compile only tests: > > === gcc Summary === > > # of expected passes91875 > # of unexpected failures23768 > # of unexpected successes 23 > # of expected failures 1038 > # of unresolved testcases 19490 > # of unsupported tests 3819 > /home/roger/GCC/arc-linux/gcc/xgcc version 14.0.0 20230828 > (experimental) > (GCC) > > If someone could double check there are no issues on real hardware > that would be great. I'm not sure if ARC is one of the targets > covered by Jeff Law's compile farm? It is :-) Runs daily, about 4:30 am UTC. So if the bits go in we'd have data within 24hrs. Jeff
RE: [ARC PATCH] Use rlc r0, 0 to implement scc_ltu (i.e. carry_flag ? 1 : 0)
I'll add it to our nightly. Just to be sure I’ll let you know asap it's status. Roger, you can always use Synopsys free nsim simulator which you can find it on Synopsys website. Thanks, Claudiu -Original Message- From: Jeff Law Sent: Saturday, September 30, 2023 1:02 AM To: Roger Sayle ; Claudiu Zissulescu Cc: gcc-patches@gcc.gnu.org Subject: Re: [ARC PATCH] Use rlc r0, 0 to implement scc_ltu (i.e. carry_flag ? 1 : 0) On 9/29/23 15:11, Roger Sayle wrote: > > Hi Claudiu, >> The patch looks sane. Have you run dejagnu test suite? > > I've not yet managed to set up an emulator or compile the entire > toolchain, so my dejagnu results are only useful for catching > (serious) problems in the compile only tests: > > === gcc Summary === > > # of expected passes91875 > # of unexpected failures23768 > # of unexpected successes 23 > # of expected failures 1038 > # of unresolved testcases 19490 > # of unsupported tests 3819 > /home/roger/GCC/arc-linux/gcc/xgcc version 14.0.0 20230828 > (experimental) > (GCC) > > If someone could double check there are no issues on real hardware > that would be great. I'm not sure if ARC is one of the targets > covered by Jeff Law's compile farm? It is :-) Runs daily, about 4:30 am UTC. So if the bits go in we'd have data within 24hrs. Jeff
RE: [ARC PATCH] Use rlc r0, 0 to implement scc_ltu (i.e. carry_flag ? 1 : 0)
Hi Roger,
The patch looks sane. Have you run dejagnu test suite?
Thanks,
Claudiu
-Original Message-
From: Roger Sayle
Sent: Friday, September 29, 2023 6:54 PM
To: gcc-patches@gcc.gnu.org
Cc: Claudiu Zissulescu
Subject: [ARC PATCH] Use rlc r0,0 to implement scc_ltu (i.e. carry_flag ? 1 : 0)
This patch teaches the ARC backend that the contents of the carry flag can be
placed in an integer register conveniently using the "rlc rX,0"
instruction, which is a rotate-left-through-carry using zero as a source.
This is a convenient special case for the LTU form of the scc pattern.
unsigned int foo(unsigned int x, unsigned int y) {
return (x+y) < x;
}
With -O2 -mcpu=em this is currently compiled to:
foo:add.f 0,r0,r1
mov_s r0,1;3
j_s.d [blink]
mov.hs r0,0
[which after an addition to set the carry flag, sets r0 to 1, followed by a
conditional assignment of r0 to zero if the carry flag is clear]. With the new
define_insn/optimization in this patch, this becomes:
foo:add.f 0,r0,r1
j_s.d [blink]
rlc r0,0
This define_insn is also a useful building block for implementing shifts and
rotates.
Tested on a cross-compiler to arc-linux (hosted on x86_64-pc-linux-gnu), and a
partial tool chain, where the new case passes and there are no new regressions.
Ok for mainline?
2023-09-29 Roger Sayle
gcc/ChangeLog
* config/arc/arc.md (CC_ltu): New mode iterator for CC and CC_C.
(scc_ltu_): New define_insn to handle LTU form of scc_insn.
(*scc_insn): Don't split to a conditional move sequence for LTU.
gcc/testsuite/ChangeLog
* gcc.target/arc/scc-ltu.c: New test case.
Thanks in advance,
Roger
--
Re: [PATCH 2/2] ARC: Use intrinsics for __builtin_sub_overflow*()
OK,
Thank you for your contribution,
Claudiu
On Wed, Sep 6, 2023 at 3:50 PM Shahab Vahedi wrote:
>
> This patch covers signed and unsigned subtractions. The generated code
> would be something along these lines:
>
> signed:
> sub.f r0, r1, r2
> b.v @label
>
> unsigned:
> sub.f r0, r1, r2
> b.c @label
>
> gcc/ChangeLog:
>
> * config/arc/arc.md (subsi3_v): New insn.
> (subvsi4): New expand.
> (subsi3_c): New insn.
> (usubvsi4): New expand.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arc/overflow-2.c: New.
>
> Signed-off-by: Shahab Vahedi
> ---
> gcc/config/arc/arc.md | 48 +++
> gcc/testsuite/gcc.target/arc/overflow-2.c | 97 +++
> 2 files changed, 145 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/arc/overflow-2.c
>
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index 9d011f6b4a9..34e9e1a7f1d 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -2973,6 +2973,54 @@ archs4x, archs4xd"
>(set_attr "cpu_facility" "*,cd,*,*,*,*,*,*,*,*")
>])
>
> +(define_insn "subsi3_v"
> + [(set (match_operand:SI 0 "register_operand" "=r,r,r, r")
> + (minus:SI (match_operand:SI 1 "register_operand" "r,r,0, r")
> + (match_operand:SI 2 "nonmemory_operand" "r,L,I,C32")))
> + (set (reg:CC_V CC_REG)
> + (compare:CC_V (sign_extend:DI (minus:SI (match_dup 1)
> + (match_dup 2)))
> + (minus:DI (sign_extend:DI (match_dup 1))
> + (sign_extend:DI (match_dup 2)]
> + ""
> + "sub.f\\t%0,%1,%2"
> + [(set_attr "cond" "set")
> +(set_attr "type" "compare")
> +(set_attr "length" "4,4,4,8")])
> +
> +(define_expand "subvsi4"
> + [(match_operand:SI 0 "register_operand")
> + (match_operand:SI 1 "register_operand")
> + (match_operand:SI 2 "nonmemory_operand")
> + (label_ref (match_operand 3 "" ""))]
> + ""
> + "emit_insn (gen_subsi3_v (operands[0], operands[1], operands[2]));
> + arc_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]);
> + DONE;")
> +
> +(define_insn "subsi3_c"
> + [(set (match_operand:SI 0 "register_operand" "=r,r,r, r")
> + (minus:SI (match_operand:SI 1 "register_operand" "r,r,0, r")
> + (match_operand:SI 2 "nonmemory_operand" "r,L,I,C32")))
> + (set (reg:CC_C CC_REG)
> + (compare:CC_C (match_dup 1)
> + (match_dup 2)))]
> + ""
> + "sub.f\\t%0,%1,%2"
> + [(set_attr "cond" "set")
> +(set_attr "type" "compare")
> +(set_attr "length" "4,4,4,8")])
> +
> +(define_expand "usubvsi4"
> + [(match_operand:SI 0 "register_operand")
> + (match_operand:SI 1 "register_operand")
> + (match_operand:SI 2 "nonmemory_operand")
> + (label_ref (match_operand 3 "" ""))]
> + ""
> + "emit_insn (gen_subsi3_c (operands[0], operands[1], operands[2]));
> +arc_gen_unlikely_cbranch (LTU, CC_Cmode, operands[3]);
> +DONE;")
> +
> (define_expand "subdi3"
>[(set (match_operand:DI 0 "register_operand" "")
> (minus:DI (match_operand:DI 1 "register_operand" "")
> diff --git a/gcc/testsuite/gcc.target/arc/overflow-2.c
> b/gcc/testsuite/gcc.target/arc/overflow-2.c
> new file mode 100644
> index 000..b4de8c03b22
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arc/overflow-2.c
> @@ -0,0 +1,97 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O1" } */
> +
> +#include
> +#include
> +
> +/*
> + * sub.f r0,r0,r1
> + * st_s r0,[r2]
> + * mov_s r0,1
> + * j_s.d [blink]
> + * mov.nv r0,0
> + */
> +bool sub_overflow (int32_t a, int32_t b, int32_t *res)
> +{
> + return __builtin_sub_overflow (a, b, res);
> +}
> +
> +/*
> + * sub.f r0,r0,-1234
> + * st_s r0,[r1]
> + * mov_s r0,1
> + * j_s.d [blink]
> + * mov.nv r0,0
> + */
> +bool subi_overflow (int32_t a, int32_t *res)
> +{
> + return __builtin_sub_overflow (a, -1234, res);
> +}
> +
> +/*
> + * sub.f r3,r0,r1
> + * st_s r3,[r2]
> + * j_s.d [blink]
> + * setlo r0,r0,r1
> + */
> +bool usub_overflow (uint32_t a, uint32_t b, uint32_t *res)
> +{
> + return __builtin_sub_overflow (a, b, res);
> +}
> +
> +/*
> + * sub.f r2,r0,4321
> + * seths r0,4320,r0
> + * j_s.d [blink]
> + * st_s r2,[r1]
> + */
> +bool usubi_overflow (uint32_t a, uint32_t *res)
> +{
> + return __builtin_sub_overflow (a, 4321, res);
> +}
> +
> +/*
> + * sub.f r0,r0,r1
> + * mov_s r0,1
> + * j_s.d [blink]
> + * mov.nv r0,0
> + */
> +bool sub_overflow_p (int32_t a, int32_t b, int32_t res)
> +{
> + return __builtin_sub_overflow_p (a, b, res);
> +}
> +
> +/*
> + * sub.f r0,r0,-1000
> + * mov_s r0,1
> + * j_s.d [blink]
> + * mov.nv r0,0
> + */
> +bool subi_overflow_p (int32_t a, int32_t res)
> +{
> + return __builtin_sub_overflow_p (a, -1000, res);
> +}
> +
> +/*
> + * j_s.d [blink]
> + * setlo r0,r0,r1
> + */
> +bool usub_overflow_p (uint32_t a, uint32_t b, uint32_t res)
> +{
> +
Re: [PATCH 1/2] ARC: Use intrinsics for __builtin_add_overflow*()
Ok.
Thank you for your contribution,
Claudiu
On Wed, Sep 6, 2023 at 3:50 PM Shahab Vahedi wrote:
>
> This patch covers signed and unsigned additions. The generated code
> would be something along these lines:
>
> signed:
> add.f r0, r1, r2
> b.v @label
>
> unsigned:
> add.f r0, r1, r2
> b.c @label
>
> gcc/ChangeLog:
>
> * config/arc/arc-modes.def: Add CC_V mode.
> * config/arc/predicates.md (proper_comparison_operator): Handle
> E_CC_Vmode.
> (equality_comparison_operator): Exclude CC_Vmode from eq/ne.
> (cc_set_register): Handle CC_Vmode.
> (cc_use_register): Likewise.
> * config/arc/arc.md (addsi3_v): New insn.
> (addvsi4): New expand.
> (addsi3_c): New insn.
> (uaddvsi4): New expand.
> * config/arc/arc-protos.h (arc_gen_unlikely_cbranch): New.
> * config/arc/arc.cc (arc_gen_unlikely_cbranch): New.
> (get_arc_condition_code): Handle E_CC_Vmode.
> (arc_init_reg_tables): Handle CC_Vmode.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/arc/overflow-1.c: New.
>
> Signed-off-by: Shahab Vahedi
> ---
> gcc/config/arc/arc-modes.def | 1 +
> gcc/config/arc/arc-protos.h | 1 +
> gcc/config/arc/arc.cc | 26 +-
> gcc/config/arc/arc.md | 49 +++
> gcc/config/arc/predicates.md | 14 ++-
> gcc/testsuite/gcc.target/arc/overflow-1.c | 100 ++
> 6 files changed, 187 insertions(+), 4 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/arc/overflow-1.c
>
> diff --git a/gcc/config/arc/arc-modes.def b/gcc/config/arc/arc-modes.def
> index 763e880317d..69eeec5935a 100644
> --- a/gcc/config/arc/arc-modes.def
> +++ b/gcc/config/arc/arc-modes.def
> @@ -24,6 +24,7 @@ along with GCC; see the file COPYING3. If not see
>
> CC_MODE (CC_ZN);
> CC_MODE (CC_Z);
> +CC_MODE (CC_V);
> CC_MODE (CC_C);
> CC_MODE (CC_FP_GT);
> CC_MODE (CC_FP_GE);
> diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
> index 4f2db7ffb59..bc78fb0b370 100644
> --- a/gcc/config/arc/arc-protos.h
> +++ b/gcc/config/arc/arc-protos.h
> @@ -50,6 +50,7 @@ extern bool arc_check_mov_const (HOST_WIDE_INT );
> extern bool arc_split_mov_const (rtx *);
> extern bool arc_can_use_return_insn (void);
> extern bool arc_split_move_p (rtx *);
> +extern void arc_gen_unlikely_cbranch (enum rtx_code, machine_mode, rtx);
> #endif /* RTX_CODE */
>
> extern bool arc_ccfsm_branch_deleted_p (void);
> diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
> index f8c9bf17e2c..ec93d40aeb9 100644
> --- a/gcc/config/arc/arc.cc
> +++ b/gcc/config/arc/arc.cc
> @@ -1538,6 +1538,13 @@ get_arc_condition_code (rtx comparison)
> case GEU : return ARC_CC_NC;
> default : gcc_unreachable ();
> }
> +case E_CC_Vmode:
> + switch (GET_CODE (comparison))
> + {
> + case EQ : return ARC_CC_NV;
> + case NE : return ARC_CC_V;
> + default : gcc_unreachable ();
> + }
> case E_CC_FP_GTmode:
>if (TARGET_ARGONAUT_SET && TARGET_SPFP)
> switch (GET_CODE (comparison))
> @@ -1868,7 +1875,7 @@ arc_init_reg_tables (void)
> /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
> we must explicitly check for them here. */
> if (i == (int) CCmode || i == (int) CC_ZNmode || i == (int) CC_Zmode
> - || i == (int) CC_Cmode
> + || i == (int) CC_Cmode || i == (int) CC_Vmode
> || i == CC_FP_GTmode || i == CC_FP_GEmode || i == CC_FP_ORDmode
> || i == CC_FPUmode || i == CC_FPUEmode || i == CC_FPU_UNEQmode)
> arc_mode_class[i] = 1 << (int) C_MODE;
> @@ -11852,6 +11859,23 @@ arc_libm_function_max_error (unsigned cfn,
> machine_mode mode,
>return default_libm_function_max_error (cfn, mode, boundary_p);
> }
>
> +/* Generate RTL for conditional branch with rtx comparison CODE in mode
> + CC_MODE. */
> +
> +void
> +arc_gen_unlikely_cbranch (enum rtx_code cmp, machine_mode cc_mode, rtx label)
> +{
> + rtx cc_reg, x;
> +
> + cc_reg = gen_rtx_REG (cc_mode, CC_REG);
> + label = gen_rtx_LABEL_REF (VOIDmode, label);
> +
> + x = gen_rtx_fmt_ee (cmp, VOIDmode, cc_reg, const0_rtx);
> + x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, label, pc_rtx);
> +
> + emit_unlikely_jump (gen_rtx_SET (pc_rtx, x));
> +}
> +
> #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
> #define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p
>
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index d37ecbf4292..9d011f6b4a9 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -2725,6 +2725,55 @@ archs4x, archs4xd"
> }
>")
>
> +(define_insn "addsi3_v"
> + [(set (match_operand:SI 0 "register_operand" "=r,r,r, r")
> + (plus:SI (match_operand:SI 1 "register_operand" "r,r,0, r")
> + (match_operand:SI 2
[committed 2/2] arc: Cleanup addsi3 instruction pattern
This patch repurposes the code letter 's' to 'x', and 'S' to 'J'.
Also it introduces new CODE letters 'x', 's', 'S', and 'N'.
gcc/ChangeLog:
* config/arc/arc-protos.h (arc_output_addsi): Remove declaration.
(split_addsi): Likewise.
* config/arc/arc.cc (arc_print_operand): Add/repurpose 's', 'S',
'N', 'x', and 'J' code letters.
(arc_output_addsi): Make it static.
(split_addsi): Remove it.
* config/arc/arc.h (UNSIGNED_INT*): New defines.
(SINNED_INT*): Likewise.
* config/arc/arc.md (type): Add add, sub, bxor types.
(tst_movb): Change code letter from 's' to 'x'.
(andsi3_i): Likewise.
(addsi3_mixed): Refurbish the pattern.
(call_i): Change code letter from 'S' to 'J'.
* config/arc/arc700.md: Add newly introduced types.
* config/arc/arcHS.md: Likewsie.
* config/arc/arcHS4x.md: Likewise.
* config/arc/constraints.md (Cca, CL2, Csp, C2a): Remove it.
(CM4): Update description.
(CP4, C6u, C6n, CIs, C4p): New constraint.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc-protos.h | 2 -
gcc/config/arc/arc.cc | 94 +++
gcc/config/arc/arc.h | 58 +++--
gcc/config/arc/arc.md | 81 +++---
gcc/config/arc/arc700.md | 2 +-
gcc/config/arc/arcHS.md | 2 +-
gcc/config/arc/arcHS4x.md | 2 +-
gcc/config/arc/constraints.md | 71 +-
8 files changed, 184 insertions(+), 128 deletions(-)
diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
index d47b4756ad4..4f2db7ffb59 100644
--- a/gcc/config/arc/arc-protos.h
+++ b/gcc/config/arc/arc-protos.h
@@ -32,7 +32,6 @@ extern void arc_print_operand (FILE *, rtx, int);
extern void arc_print_operand_address (FILE *, rtx);
extern void arc_final_prescan_insn (rtx_insn *, rtx *, int);
extern const char *arc_output_libcall (const char *);
-extern int arc_output_addsi (rtx *operands, bool, bool);
extern int arc_output_commutative_cond_exec (rtx *operands, bool);
extern bool arc_expand_cpymem (rtx *operands);
extern bool prepare_move_operands (rtx *operands, machine_mode mode);
@@ -86,7 +85,6 @@ extern void arc_init_expanders (void);
extern int arc_check_millicode (rtx op, int offset, int load_p);
extern void arc_clear_unalign (void);
extern void arc_toggle_unalign (void);
-extern void split_addsi (rtx *);
extern void split_subsi (rtx *);
extern void arc_split_move (rtx *);
extern const char *arc_short_long (rtx_insn *insn, const char *, const char *);
diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index 8ee7387286e..f8c9bf17e2c 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -4501,8 +4501,8 @@ static int output_sdata = 0;
/* Print operand X (an rtx) in assembler syntax to file FILE.
CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
- For `%' followed by punctuation, CODE is the punctuation and X is null. */
-/* In final.cc:output_asm_insn:
+ For `%' followed by punctuation, CODE is the punctuation and X is null.
+ In final.cc:output_asm_insn:
'l' : label
'a' : address
'c' : constant address if CONSTANT_ADDRESS_P
@@ -4512,7 +4512,10 @@ static int output_sdata = 0;
'z': log2
'M': log2(~x)
'p': bit Position of lsb
-'s': size of bit field
+'s': scalled immediate
+'S': Scalled immediate, to be used in pair with 's'.
+'N': Negative immediate, to be used in pair with 's'.
+'x': size of bit field
'#': condbranch delay slot suffix
'*': jump delay slot suffix
'?' : nonjump-insn suffix for conditional execution or short instruction
@@ -4521,7 +4524,7 @@ static int output_sdata = 0;
'd'
'D'
'R': Second word
-'S': JLI instruction
+'J': JLI instruction
'j': used by mov instruction to properly emit jli related labels.
'B': Branch comparison operand - suppress sda reference
'H': Most significant word
@@ -4538,6 +4541,10 @@ static int output_sdata = 0;
void
arc_print_operand (FILE *file, rtx x, int code)
{
+ HOST_WIDE_INT ival;
+ unsigned scalled = 0;
+ int sign = 1;
+
switch (code)
{
case 'Z':
@@ -4580,6 +4587,56 @@ arc_print_operand (FILE *file, rtx x, int code)
return;
case 's':
+ if (REG_P (x))
+ return;
+ if (!CONST_INT_P (x))
+ {
+ output_operand_lossage ("invalid operand for %%s code");
+ return;
+ }
+ ival = INTVAL (x);
+ if ((ival & 0x07) == 0)
+ scalled = 3;
+ else if ((ival & 0x03) == 0)
+ scalled = 2;
+ else if ((ival & 0x01) == 0)
+ scalled = 1;
+
+ if (scalled)
+ asm_fprintf (file, "%d", scalled);
+ return;
+
+case 'N':
+ if (REG_P (x))
+ {
+ output_operand_lossage ("invalid operand for %%N code");
+
[committed 1/2] arc: Remove obsolete mbbit-peephole option and unused patterns.
gcc/
* common/config/arc/arc-common.cc (arc_option_optimization_table):
Remove mbbit_peephole.
* config/arc/arc.md (UNSPEC_ARC_DIRECT): Remove.
(store_direct): Likewise.
(BBIT peephole2): Likewise.
* config/arc/arc.opt (mbbit-peephole): Ignore option.
* doc/invoke.texi (mbbit-peephole): Update document.
Signed-off-by: Claudiu Zissulescu
---
gcc/common/config/arc/arc-common.cc | 1 -
gcc/config/arc/arc.md | 31 -
gcc/config/arc/arc.opt | 4 ++--
gcc/doc/invoke.texi | 2 +-
4 files changed, 3 insertions(+), 35 deletions(-)
diff --git a/gcc/common/config/arc/arc-common.cc
b/gcc/common/config/arc/arc-common.cc
index 95f5dd61201..3fd66e1f6b5 100644
--- a/gcc/common/config/arc/arc-common.cc
+++ b/gcc/common/config/arc/arc-common.cc
@@ -46,7 +46,6 @@ static const struct default_options
arc_option_optimization_table[] =
{
{ OPT_LEVELS_ALL, OPT_msize_level_, NULL, 1 },
{ OPT_LEVELS_ALL, OPT_mearly_cbranchsi, NULL, 1 },
-{ OPT_LEVELS_ALL, OPT_mbbit_peephole, NULL, 1 },
{ OPT_LEVELS_SIZE, OPT_ftree_loop_optimize, NULL, 0},
{ OPT_LEVELS_SIZE, OPT_fmove_loop_invariants, NULL, 0},
{ OPT_LEVELS_SIZE, OPT_fbranch_count_reg, NULL, 0},
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index a4e77a207bf..d401e600f42 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -3589,37 +3589,6 @@ (define_insn "*btst"
(set_attr "type" "compare")
(set_attr "length" "*,4")])
-; combine suffers from 'simplifications' that replace a one-bit zero
-; extract with a shift if it can prove that the upper bits are zero.
-; arc_reorg sees the code after sched2, which can have caused our
-; inputs to be clobbered even if they were not clobbered before.
-; Therefore, add a third way to convert btst / b{eq,ne} to bbit{0,1}
-; OTOH, this is somewhat marginal, and can leat to out-of-range
-; bbit (i.e. bad scheduling) and missed conditional execution,
-; so make this an option.
-(define_peephole2
- [(set (reg:CC_ZN CC_REG)
- (compare:CC_ZN
- (zero_extract:SI (match_operand:SI 0 "register_operand" "")
- (const_int 1)
- (match_operand:SI 1 "nonmemory_operand" ""))
- (const_int 0)))
- (set (pc)
- (if_then_else (match_operator 3 "equality_comparison_operator"
- [(reg:CC_ZN CC_REG) (const_int 0)])
- (label_ref (match_operand 2 "" ""))
- (pc)))]
- "TARGET_BBIT_PEEPHOLE && peep2_regno_dead_p (2, CC_REG)"
- [(parallel [(set (pc)
- (if_then_else
-(match_op_dup 3
- [(zero_extract:SI (match_dup 0)
-(const_int 1) (match_dup 1))
- (const_int 0)])
-(label_ref (match_dup 2))
-(pc)))
- (clobber (reg:CC_ZN CC_REG))])])
-
(define_insn "*cmpsi_cc_z_insn"
[(set (reg:CC_Z CC_REG)
(compare:CC_Z (match_operand:SI 0 "register_operand" "q,c")
diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt
index 273667c9b58..4af901f2619 100644
--- a/gcc/config/arc/arc.opt
+++ b/gcc/config/arc/arc.opt
@@ -322,8 +322,8 @@ Target Var(TARGET_EARLY_CBRANCHSI)
Enable pre-reload use of cbranchsi pattern.
mbbit-peephole
-Target Var(TARGET_BBIT_PEEPHOLE)
-Enable bbit peephole2.
+Target Ignore
+Does nothing. Preserved for backward compatibility.
mcase-vector-pcrel
Target Var(TARGET_CASE_VECTOR_PC_RELATIVE)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 435fb2fba99..33befee7d6b 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -21603,7 +21603,7 @@ Enable the use of pre/post modify with register
displacement.
@opindex mbbit-peephole
@item -mbbit-peephole
-Enable bbit peephole2.
+Does nothing. Preserved for backward compatibility.
@opindex mno-brcc
@item -mno-brcc
--
2.30.2
[committed] arc: Honor SWAP option for lsl16 instruction
The LSL16 instruction is only available if SWAP (-mswap) option is
turned on.
gcc/ChangeLog:
* config/arc/arc.cc (arc_split_mov_const): Use LSL16 only when
SWAP option is enabled.
* config/arc/arc.md (ashlsi2_cnt16): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc | 2 +-
gcc/config/arc/arc.md | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index 266ba8b00bb..8ee7387286e 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -11647,7 +11647,7 @@ arc_split_mov_const (rtx *operands)
}
/* 3. Check if we can just shift by 16 to fit into the u6 of LSL16. */
- if (TARGET_BARREL_SHIFTER && TARGET_V2
+ if (TARGET_SWAP && TARGET_V2
&& ((ival & ~0x3f) == 0))
{
shimm = (ival >> 16) & 0x3f;
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 1f122d9507f..a4e77a207bf 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -5991,7 +5991,7 @@ (define_insn "*ashlsi2_cnt16"
[(set (match_operand:SI 0 "register_operand""=r")
(ashift:SI (match_operand:SI 1 "nonmemory_operand" "rL")
(const_int 16)))]
- "TARGET_BARREL_SHIFTER && TARGET_V2"
+ "TARGET_SWAP && TARGET_V2"
"lsl16\\t%0,%1"
[(set_attr "type" "shift")
(set_attr "iscompact" "false")
--
2.30.2
[committed] arc: Update builtin documentation
gcc/ChangeLog:
* doc/extend.texi (ARC Built-in Functions): Update documentation
with missing builtins.
---
gcc/doc/extend.texi | 55 +
1 file changed, 55 insertions(+)
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index d701b4d1d41..bfbc1d6cc9f 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -15260,6 +15260,23 @@ __builtin_arc_sr()
__builtin_arc_swi()
@end example
+The following built-in functions are available for the ARCv2 family of
+processors.
+
+@example
+int __builtin_arc_clri ();
+void __builtin_arc_kflag (unsigned);
+void __builtin_arc_seti (int);
+@end example
+
+The following built-in functions are available for the ARCv2 family
+and uses @option{-mnorm}.
+
+@example
+int __builtin_arc_ffs (int);
+int __builtin_arc_fls (int);
+@end example
+
@node ARC SIMD Built-in Functions
@subsection ARC SIMD Built-in Functions
@@ -15486,6 +15503,44 @@ void __builtin_arc_vst16_n (__v8hi, const int, const
int, const int);
void __builtin_arc_vst32_n (__v8hi, const int, const int, const int);
@end example
+The following built-in functions are available on systems that uses
+@option{-mmpy-option=6} or higher.
+
+@example
+__v2hi __builtin_arc_dmach (__v2hi, __v2hi);
+__v2hi __builtin_arc_dmachu (__v2hi, __v2hi);
+__v2hi __builtin_arc_dmpyh (__v2hi, __v2hi);
+__v2hi __builtin_arc_dmpyhu (__v2hi, __v2hi);
+__v2hi __builtin_arc_vaddsub2h (__v2hi, __v2hi);
+__v2hi __builtin_arc_vsubadd2h (__v2hi, __v2hi);
+@end example
+
+The following built-in functions are available on systems that uses
+@option{-mmpy-option=7} or higher.
+
+@example
+__v2si __builtin_arc_vmac2h (__v2hi, __v2hi);
+__v2si __builtin_arc_vmac2hu (__v2hi, __v2hi);
+__v2si __builtin_arc_vmpy2h (__v2hi, __v2hi);
+__v2si __builtin_arc_vmpy2hu (__v2hi, __v2hi);
+@end example
+
+The following built-in functions are available on systems that uses
+@option{-mmpy-option=8} or higher.
+
+@example
+long long __builtin_arc_qmach (__v4hi, __v4hi);
+long long __builtin_arc_qmachu (__v4hi, __v4hi);
+long long __builtin_arc_qmpyh (__v4hi, __v4hi);
+long long __builtin_arc_qmpyhu (__v4hi, __v4hi);
+long long __builtin_arc_dmacwh (__v2si, __v2hi);
+long long __builtin_arc_dmacwhu (__v2si, __v2hi);
+_v2si __builtin_arc_vaddsub (__v2si, __v2si);
+_v2si __builtin_arc_vsubadd (__v2si, __v2si);
+_v4hi __builtin_arc_vaddsub4h (__v4hi, __v4hi);
+_v4hi __builtin_arc_vsubadd4h (__v4hi, __v4hi);
+@end example
+
@node ARM iWMMXt Built-in Functions
@subsection ARM iWMMXt Built-in Functions
--
2.30.2
[committed] arc: Make TLS Local Dynamic work like Global Dynamic model
Current ARC's TLS Local Dynamic model is using two anchors to access
data, namely `.tdata` and `.tbss`. This implementation is unnecessary
complicated. However, the TLS Local Dynamic model has better results
using Global Dynamic model and anchors.
gcc/ChangeLog;
* config/arc/arc.cc (arc_call_tls_get_addr): Simplify access using
TLS Local Dynamic.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc | 24 +---
1 file changed, 1 insertion(+), 23 deletions(-)
diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index dd012ffa975..fef8a504f77 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -6257,8 +6257,6 @@ arc_call_tls_get_addr (rtx ti)
return ret;
}
-#define DTPOFF_ZERO_SYM ".tdata"
-
/* Return a legitimized address for ADDR,
which is a SYMBOL_REF with tls_model MODEL. */
@@ -6267,37 +6265,17 @@ arc_legitimize_tls_address (rtx addr, enum tls_model
model)
{
rtx tmp;
- if (!flag_pic && model == TLS_MODEL_LOCAL_DYNAMIC)
-model = TLS_MODEL_LOCAL_EXEC;
-
-
/* The TP pointer needs to be set. */
gcc_assert (arc_tp_regno != -1);
switch (model)
{
case TLS_MODEL_GLOBAL_DYNAMIC:
+case TLS_MODEL_LOCAL_DYNAMIC:
tmp = gen_reg_rtx (Pmode);
emit_move_insn (tmp, arc_unspec_offset (addr, UNSPEC_TLS_GD));
return arc_call_tls_get_addr (tmp);
-case TLS_MODEL_LOCAL_DYNAMIC:
- rtx base;
- tree decl;
- const char *base_name;
-
- decl = SYMBOL_REF_DECL (addr);
- base_name = DTPOFF_ZERO_SYM;
- if (decl && bss_initializer_p (decl))
- base_name = ".tbss";
-
- base = gen_rtx_SYMBOL_REF (Pmode, base_name);
- tmp = gen_reg_rtx (Pmode);
- emit_move_insn (tmp, arc_unspec_offset (base, UNSPEC_TLS_GD));
- base = arc_call_tls_get_addr (tmp);
- return gen_rtx_PLUS (Pmode, force_reg (Pmode, base),
- arc_unspec_offset (addr, UNSPEC_TLS_OFF));
-
case TLS_MODEL_INITIAL_EXEC:
addr = arc_unspec_offset (addr, UNSPEC_TLS_IE);
addr = copy_to_mode_reg (Pmode, gen_const_mem (Pmode, addr));
--
2.30.2
[committed] arc: Don't use millicode thunks unless asked for.
ARC has enter_s/leave_s instructions which can save/restore the entire
function context. It is not needed the millicode thunks anylonger when
compiling for size, thus, make their usage optional.
gcc/
* common/config/arc/arc-common.cc (arc_option_optimization_table):
Remove millicode from list.
gcc/testsuite/
* gcc.target/arc/milli-1.c: Update test.
---
gcc/common/config/arc/arc-common.cc| 1 -
gcc/testsuite/gcc.target/arc/milli-1.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/gcc/common/config/arc/arc-common.cc
b/gcc/common/config/arc/arc-common.cc
index 6423f6a9647..95f5dd61201 100644
--- a/gcc/common/config/arc/arc-common.cc
+++ b/gcc/common/config/arc/arc-common.cc
@@ -54,7 +54,6 @@ static const struct default_options
arc_option_optimization_table[] =
{ OPT_LEVELS_SIZE, OPT_fsection_anchors, NULL, 1 },
{ OPT_LEVELS_SIZE, OPT_mcase_vector_pcrel, NULL, 1 },
{ OPT_LEVELS_SIZE, OPT_msize_level_, NULL, 3 },
-{ OPT_LEVELS_SIZE, OPT_mmillicode, NULL, 1 },
{ OPT_LEVELS_SIZE, OPT_fif_conversion, NULL, 0 },
{ OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
{ OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_msize_level_, NULL, 0 },
diff --git a/gcc/testsuite/gcc.target/arc/milli-1.c
b/gcc/testsuite/gcc.target/arc/milli-1.c
index b501b39eb81..5fba064ca66 100644
--- a/gcc/testsuite/gcc.target/arc/milli-1.c
+++ b/gcc/testsuite/gcc.target/arc/milli-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-Os" } */
+/* { dg-options "-Os -mmillicode" } */
/* Test if we restore correctly blink when using millicode. */
extern void bar (void);
--
2.30.2
[committed 4/5] arc: Remove Rcq constraint.
gcc/
* config/arc/arc.cc (arc_check_short_reg_p): New function.
(arc_address_cost): Replace satisfies_constraint_Rcq with the
above new function.
(arc_output_addsi): Likewise.
(split_addsi): Likewise.
(split_subsi): Likewise.
* config/arc/arc.md (movqi_insn): Remove Rcq constraint.
(movhi_insn): Likewise.
(movsi_insn): Likewise.
(tst_movb): Likewise.
(tst): Likewise.
(tst_bitfield): Likewise.
(abssi2): Likewise.
(addsi3_mixed): Likewise.
(mulhisi3_reg): Likewise.
(umulhisi3_reg): Likewise.
(mulsi_600): Likewise.
(mul64): Likewise.
(subsi3_insn): Likewise.
(bicsi3_insn): Likewise.
(xorsi3): Likewise.
(negsi2): Likewise.
(one_cmplsi2): Likewise.
(lshrsi3_insn): Likewise.
(cmpsi_cc_insn_mixed): Likewise.
(cmpsi_cc_zn_insn): Likewise.
(btst): Likewise.
(cmpsi_cc_z_insn): Likewise.
(cmpsi_cc_c_insn): Likewise.
(indirect_jump): Likewise.
(casesi_jump): Likewise.
(call_i): Likewise.
(call_value_i): Likewise.
(bbit): Likewise.
(abssf2): Likewise.
(ashlsi2_cnt1): Likewise.
(lshrsi3_cnt1): Likewise.
(ashrsi3_cnt1): Likewise.
* config/arc/constraints.md (Rcq): Remove.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc | 48 +++
gcc/config/arc/arc.md | 152 --
gcc/config/arc/constraints.md | 20 -
3 files changed, 104 insertions(+), 116 deletions(-)
diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index 7be27e01035..e6f52d87714 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -2474,6 +2474,20 @@ arc_setup_incoming_varargs (cumulative_args_t
args_so_far,
}
}
+/* Return TRUE if reg is ok for short instrcutions. */
+
+static bool
+arc_check_short_reg_p (rtx op)
+{
+ if (!REG_P (op))
+return false;
+
+ if (IN_RANGE (REGNO (op) ^ 4, 4, 11))
+return true;
+
+ return false;
+}
+
/* Cost functions. */
/* Provide the costs of an addressing mode that contains ADDR.
@@ -2485,7 +2499,7 @@ arc_address_cost (rtx addr, machine_mode, addr_space_t,
bool speed)
switch (GET_CODE (addr))
{
case REG :
- return speed || satisfies_constraint_Rcq (addr) ? 0 : 1;
+ return speed || arc_check_short_reg_p (addr) ? 0 : 1;
case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC:
case PRE_MODIFY: case POST_MODIFY:
return !speed;
@@ -2517,14 +2531,14 @@ arc_address_cost (rtx addr, machine_mode, addr_space_t,
bool speed)
? COSTS_N_INSNS (1)
: speed
? 0
- : (satisfies_constraint_Rcq (plus0)
+ : (arc_check_short_reg_p (plus0)
&& satisfies_constraint_O (plus1))
? 0
: 1);
case REG:
return (speed < 1 ? 0
- : (satisfies_constraint_Rcq (plus0)
- && satisfies_constraint_Rcq (plus1))
+ : (arc_check_short_reg_p (plus0)
+ && arc_check_short_reg_p (plus1))
? 0 : 1);
case CONST :
case SYMBOL_REF :
@@ -9003,8 +9017,8 @@ arc_output_addsi (rtx *operands, bool cond_p, bool
output_p)
int intval = (REG_P (operands[2]) ? 1
: CONST_INT_P (operands[2]) ? INTVAL (operands[2]) : 0xbadc057);
int neg_intval = -intval;
- int short_0 = satisfies_constraint_Rcq (operands[0]);
- int short_p = (!cond_p && short_0 && satisfies_constraint_Rcq (operands[1]));
+ int short_0 = arc_check_short_reg_p (operands[0]);
+ int short_p = (!cond_p && short_0 && arc_check_short_reg_p (operands[1]));
int ret = 0;
#define REG_H_P(OP) (REG_P (OP) && ((TARGET_V2 && REGNO (OP) <= 31 \
@@ -9037,7 +9051,7 @@ arc_output_addsi (rtx *operands, bool cond_p, bool
output_p)
patterns. */
if (short_p
&& ((REG_H_P (operands[2])
- && (match || satisfies_constraint_Rcq (operands[2])))
+ && (match || arc_check_short_reg_p (operands[2])))
|| (CONST_INT_P (operands[2])
&& ((unsigned) intval <= (match ? 127 : 7)
ADDSI_OUTPUT1 ("add%? %0,%1,%2 ;1");
@@ -9064,7 +9078,7 @@ arc_output_addsi (rtx *operands, bool cond_p, bool
output_p)
/* Generate add_s r0,b,u6; add_s r1,b,u6 patterns. */
if (TARGET_CODE_DENSITY && REG_P (operands[0]) && REG_P (operands[1])
&& ((REGNO (operands[0]) == 0) || (REGNO (operands[0]) == 1))
- && satisfies_constraint_Rcq (operands[1])
+ && arc_check_short_reg_p (operands[1])
&&
[committed 3/5] arc: Remove Rcw constraint
gcc/Changelog:
* config/arc/arc.md (smaxsi3): Remove Rcw.
(sminsi3): Likewise.
(addsi3_mixed): Likewise.
(add_f_2): Likewise.
(subsi3_insn): Likewise.
(sub_f): Likewise.
(sub_n): Likewise.
(bset): Likewise.
(bxor): Likewise.
(bclr): Likewise.
(bset_insn): Likewise.
(bxor_insn): Likewise.
(bclr_insn): Likewise.
(bmsk_insn): Likewise.
(bicsi3_insn): Likewise.
(xorsi3): Likewise.
(negsi2): Likewise.
(lshrsi3_insn): Likewise.
(abssf2): Likewise.
(negsf2): Likewise.
* config/arc/constraints.md(Rcw): Remove it.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.md | 220 +-
gcc/config/arc/constraints.md | 14 ---
2 files changed, 110 insertions(+), 124 deletions(-)
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 90ce66d45ba..e6fa2a1fbf6 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -1991,22 +1991,22 @@ (define_insn "abssi2"
;; Maximum and minimum insns
(define_insn "smaxsi3"
- [(set (match_operand:SI 0 "dest_reg_operand" "=Rcw, w, w")
-(smax:SI (match_operand:SI 1 "register_operand" "%0, c, c")
- (match_operand:SI 2 "nonmemory_operand" "cL,cL,Cal")))]
+ [(set (match_operand:SI 0 "dest_reg_operand" "=r, r, r")
+(smax:SI (match_operand:SI 1 "register_operand" "%0, r, r")
+ (match_operand:SI 2 "nonmemory_operand" "rL,rL,Cal")))]
""
- "max%? %0,%1,%2"
+ "max%?\\t%0,%1,%2"
[(set_attr "type" "two_cycle_core")
(set_attr "length" "4,4,8")
(set_attr "predicable" "yes,no,no")]
)
(define_insn "sminsi3"
- [(set (match_operand:SI 0 "dest_reg_operand" "=Rcw, w, w")
-(smin:SI (match_operand:SI 1 "register_operand" "%0, c, c")
- (match_operand:SI 2 "nonmemory_operand" "cL,cL,Cal")))]
+ [(set (match_operand:SI 0 "dest_reg_operand" "=r, r, r")
+(smin:SI (match_operand:SI 1 "register_operand" "%0, r, r")
+ (match_operand:SI 2 "nonmemory_operand" "rL,rL,Cal")))]
""
- "min%? %0,%1,%2"
+ "min%?\\t%0,%1,%2"
[(set_attr "type" "two_cycle_core")
(set_attr "length" "4,4,8")
(set_attr "predicable" "yes,no,no")]
@@ -2028,10 +2028,10 @@ (define_insn "sminsi3"
; We avoid letting this pattern use LP_COUNT as a register by specifying
; register class 'W' instead of 'w'.
(define_insn_and_split "*addsi3_mixed"
- ;; 0 123
4 5 6 78 9 ab c d e f 10 11 12
- [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,Rcq,
h,!*Rsd,Rcq,Rcb,Rcq, Rcqq,Rcqq,Rcw,Rcw, Rcw,W, W,W, W,Rcqq,Rcw, W")
- (plus:SI (match_operand:SI 1 "register_operand" "%0, c, 0, Rcqq,
0, 0,Rcb, Rcqq, 0, 0, c, 0,c, c,0, 0, 0, 0, c")
-(match_operand:SI 2 "nonmemory_operand" "cL, 0, Cm1,
L,CL2,Csp,CM4,RcqqK, cO, cL, 0,cCca,cLCmL,Cca,I,C2a, Cal,Cal,Cal")))]
+ ;; 0 12 3
4 5 6 78 9 ab c d e f 10 11 12
+ [(set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,Rcq,
h,!*Rsd,Rcq,Rcb,Rcq, Rcqq,Rcqq, r,r, r,W, W,W, W,Rcqq, r, W")
+ (plus:SI (match_operand:SI 1 "register_operand" "%0, c, 0, Rcqq,
0, 0,Rcb, Rcqq, 0, 0,r, 0,c, c,0, 0, 0, 0, c")
+(match_operand:SI 2 "nonmemory_operand" "cL, 0, Cm1,
L,CL2,Csp,CM4,RcqqK, cO,rL,0,rCca,cLCmL,Cca,I,C2a, Cal,Cal,Cal")))]
""
{
arc_output_addsi (operands, arc_ccfsm_cond_exec_p (), true);
@@ -2792,13 +2792,13 @@ (define_insn "add_f"
(define_insn "*add_f_2"
[(set (reg:CC_C CC_REG)
(compare:CC_C
- (plus:SI (match_operand:SI 1 "register_operand" "c,0,c")
- (match_operand:SI 2 "nonmemory_operand" "cL,I,cCal"))
+ (plus:SI (match_operand:SI 1 "register_operand" "r ,0,r")
+ (match_operand:SI 2 "nonmemory_operand" "rL,I,rCal"))
(match_dup 2)))
- (set (match_operand:SI 0 "dest_reg_operand&qu
[committed 5/5] arc: Remove obsolete mRcq and mRcw options.
gcc/
* common/config/arc/arc-common.cc (arc_option_optimization_table):
Remove Rcq and Rcw options.
* config/arc/arc.opt (mRcq): Ignore option, preserve it for
backwards compatibility.
(mRcw): Likewise.
* doc/invoke.texi (mRcw, mRcq): Update document.
Signed-off-by: Claudiu Zissulescu
---
gcc/common/config/arc/arc-common.cc | 2 --
gcc/config/arc/arc.opt | 10 ++
gcc/doc/invoke.texi | 8 ++--
3 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/gcc/common/config/arc/arc-common.cc
b/gcc/common/config/arc/arc-common.cc
index e69c4a4fac7..62fe54234e0 100644
--- a/gcc/common/config/arc/arc-common.cc
+++ b/gcc/common/config/arc/arc-common.cc
@@ -44,8 +44,6 @@ arc_option_init_struct (struct gcc_options *opts
ATTRIBUTE_UNUSED)
#define OPT_LEVELS_3_PLUS_SPEED_ONLY OPT_LEVELS_3_PLUS
static const struct default_options arc_option_optimization_table[] =
{
-{ OPT_LEVELS_ALL, OPT_mRcq, NULL, 1 },
-{ OPT_LEVELS_ALL, OPT_mRcw, NULL, 1 },
{ OPT_LEVELS_ALL, OPT_msize_level_, NULL, 1 },
{ OPT_LEVELS_ALL, OPT_mearly_cbranchsi, NULL, 1 },
{ OPT_LEVELS_ALL, OPT_mbbit_peephole, NULL, 1 },
diff --git a/gcc/config/arc/arc.opt b/gcc/config/arc/arc.opt
index 0add5a2a21f..b58273255f7 100644
--- a/gcc/config/arc/arc.opt
+++ b/gcc/config/arc/arc.opt
@@ -308,12 +308,14 @@ Target Ignore
Does nothing. Preserved for backward compatibility.
mRcq
-Target Var(TARGET_Rcq)
-Enable Rcq constraint handling - most short code generation depends on this.
+Target Ignore
+Does nothing. Preserved for backward compatibility.
+
mRcw
-Target Var(TARGET_Rcw)
-Enable Rcw constraint handling - ccfsm condexec mostly depends on this.
+Target Ignore
+Does nothing. Preserved for backward compatibility.
+
mearly-cbranchsi
Target Var(TARGET_EARLY_CBRANCHSI)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 1eeaec18810..278c55d5a19 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -20896,15 +20896,11 @@ This is the default for @option{-Os}.
@item -mRcq
@opindex mRcq
-Enable @samp{Rcq} constraint handling.
-Most short code generation depends on this.
-This is the default.
+Does nothing. Preserved for backward compatibility.
@item -mRcw
@opindex mRcw
-Enable @samp{Rcw} constraint handling.
-Most ccfsm condexec mostly depends on this.
-This is the default.
+Does nothing. Preserved for backward compatibility.
@item -msize-level=@var{level}
@opindex msize-level
--
2.30.2
[committed 2/5] arc: Remove Rcr constraint
gcc/ChangeLog: * config/arc/arc.md(mulsi3_700): Remove Rcr. (mulsi3_highpart): Likewise. (umulsi3_highpart_i): Likewise. (umulsi3_highpart_int): Likewise. (macd): Likewise. (macdu): Likewise. * config/arc/constraints.md (Rcr): Remove it. gcc/testsuite/ChangeLog: * gcc.target/arc/tmac-2.c: Update test. Signed-off-by: Claudiu Zissulescu fix --- gcc/config/arc/arc.md | 36 +-- gcc/config/arc/constraints.md | 10 gcc/testsuite/gcc.target/arc/tmac-2.c | 2 +- 3 files changed, 19 insertions(+), 29 deletions(-) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 7170445309f..90ce66d45ba 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -2336,11 +2336,11 @@ (define_insn "mulu64" ; registers, since it cannot be the destination of a multi-cycle insn ; like MPY or MPYU. (define_insn "mulsi3_700" - [(set (match_operand:SI 0 "mpy_dest_reg_operand""=Rcr,r,r,Rcr,r") - (mult:SI (match_operand:SI 1 "register_operand" "%0,c,0,0,c") -(match_operand:SI 2 "nonmemory_operand" "cL,cL,I,Cal,Cal")))] + [(set (match_operand:SI 0 "mpy_dest_reg_operand""=r, r,r, r,r") + (mult:SI (match_operand:SI 1 "register_operand" "%0, r,0, 0,r") +(match_operand:SI 2 "nonmemory_operand" "rL,rL,I,Cal,Cal")))] "TARGET_ARC700_MPY" - "mpyu%? %0,%1,%2" + "mpyu%?\\t%0,%1,%2" [(set_attr "length" "4,4,4,8,8") (set_attr "type" "umulti") (set_attr "predicable" "yes,no,no,yes,no") @@ -2501,15 +2501,15 @@ (define_insn_and_split "mulsidi3_700" (set_attr "length" "8")]) (define_insn "mulsi3_highpart" - [(set (match_operand:SI 0 "register_operand" "=Rcr,r,Rcr,r") + [(set (match_operand:SI 0 "register_operand""=r,r,r,r") (truncate:SI (lshiftrt:DI (mult:DI - (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,c, 0,c")) - (sign_extend:DI (match_operand:SI 2 "extend_operand""c,c, i,i"))) + (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,r,0,r")) + (sign_extend:DI (match_operand:SI 2 "extend_operand""r,r,i,i"))) (const_int 32] "TARGET_MPY" - "mpy%+%? %0,%1,%2" + "mpy%+%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,8") (set_attr "type" "multi") (set_attr "predicable" "yes,no,yes,no") @@ -2518,15 +2518,15 @@ (define_insn "mulsi3_highpart" ; Note that mpyhu has the same latency as mpy / mpyh, ; thus we use the type multi. (define_insn "*umulsi3_highpart_i" - [(set (match_operand:SI 0 "register_operand" "=Rcr,r,Rcr,r") + [(set (match_operand:SI 0 "register_operand""=r,r,r,r") (truncate:SI (lshiftrt:DI (mult:DI - (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,c, 0,c")) - (zero_extend:DI (match_operand:SI 2 "extend_operand""c,c, i,i"))) + (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,r,0,r")) + (zero_extend:DI (match_operand:SI 2 "extend_operand""r,r,i,i"))) (const_int 32] "TARGET_MPY" - "mpy%+u%? %0,%1,%2" + "mpy%+u%?\\t%0,%1,%2" [(set_attr "length" "4,4,8,8") (set_attr "type" "multi") (set_attr "predicable" "yes,no,yes,no") @@ -2536,15 +2536,15 @@ (define_insn "*umulsi3_highpart_i" ;; need a separate pattern for immediates ;; ??? This is fine for combine, but not for reload. (define_insn "umulsi3_highpart_int" - [(set (match_operand:SI 0 "register_operand""=Rcr, r, r,Rcr, r") + [(set (match_operand:SI 0 "register_operand""=r, r, r,r, r") (truncate:SI (lshiftrt:DI (mult:DI - (zero_extend:DI (match_operand:SI 1 "register_operand" " 0, c, 0, 0, c")) - (match_operand:DI 2 "immediate_usidi_operand" "L, L, I, Cal, Cal")) + (zero_extend:DI (match_operand:SI 1 "register_operand" " 0, r, 0, 0, r")) + (match_operand:DI 2 "immediate_usidi_operand" "L, L, I,Cal,Cal"))
[committed 1/5] arc: Fix enter pattern instruction's offsets
The enter pattern instruction contains the necessary information for
the dwarf machinery to generate the appropriate dwarf code. This
patch is fixing the register offsets related to CFA, and adds a test.
gcc/
* config/arc/arc.cc (arc_save_callee_enter): Use negative offsets.
gcc/testsuite
* gcc.target/arc/enter-dw2-1.c: New file.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc | 6 ++---
gcc/testsuite/gcc.target/arc/enter-dw2-1.c | 28 ++
2 files changed, 31 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arc/enter-dw2-1.c
diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index db4b56b23ff..7be27e01035 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -3356,7 +3356,7 @@ arc_save_callee_enter (uint64_t gmask,
reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
mem = gen_frame_mem (Pmode, plus_constant (Pmode,
stack_pointer_rtx,
-off));
+-off));
XVECEXP (insn, 0, indx) = gen_rtx_SET (mem, reg);
RTX_FRAME_RELATED_P (XVECEXP (insn, 0, indx++)) = 1;
off -= UNITS_PER_WORD;
@@ -3370,7 +3370,7 @@ arc_save_callee_enter (uint64_t gmask,
reg = gen_rtx_REG (SImode, regno);
mem = gen_frame_mem (SImode, plus_constant (Pmode,
stack_pointer_rtx,
- off));
+ -off));
XVECEXP (insn, 0, indx) = gen_rtx_SET (mem, reg);
RTX_FRAME_RELATED_P (XVECEXP (insn, 0, indx)) = 1;
gmask = gmask & ~(1ULL << regno);
@@ -3380,7 +3380,7 @@ arc_save_callee_enter (uint64_t gmask,
{
mem = gen_frame_mem (Pmode, plus_constant (Pmode,
stack_pointer_rtx,
-off));
+-off));
XVECEXP (insn, 0, indx) = gen_rtx_SET (mem, hard_frame_pointer_rtx);
RTX_FRAME_RELATED_P (XVECEXP (insn, 0, indx++)) = 1;
off -= UNITS_PER_WORD;
diff --git a/gcc/testsuite/gcc.target/arc/enter-dw2-1.c
b/gcc/testsuite/gcc.target/arc/enter-dw2-1.c
new file mode 100644
index 000..25d03562198
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/enter-dw2-1.c
@@ -0,0 +1,28 @@
+/* Verify that we generate appropriate CFI offsets in the case of enter
+ instruction. */
+/* { dg-skip-if "Not having enter_s insn." { arc700 || arc6xx } } */
+/* { dg-do compile } */
+/* { dg-options "-g -Os" } */
+
+extern void bar (void);
+
+void foo (void)
+{
+ asm volatile (";my clobber list"
+ : : : "r13", "r14", "r15", "r16", "r17", "r18", "r19");
+ bar ();
+ asm volatile (";my clobber list"
+ : : : "r13", "r14", "r15", "r16", "r17", "r18", "r19");
+}
+
+
+/* { dg-final { scan-assembler-times "enter_s" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_def_cfa_offset 32" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 31, -32" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 13, -28" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 14, -24" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 15, -20" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 16, -16" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 17, -12" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 18, -8" 1 } } */
+/* { dg-final { scan-assembler-times "\.cfi_offset 19, -4" 1 } } */
--
2.30.2
[committed] arc: Remove max-page-size and common-page-size forced setting
Max page size is defined in the ARC's BFD file, and the common page
size is also set by the appropriate binutils macros. Remove them from
LINK_SPEC.
2022-10-06 Claudiu Zissulescu
* config/arc/linux.h (LINK_SPEC): Remove max-page-size and
common-pave-size.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/linux.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h
index 0f1ff055be7..6ebbb143895 100644
--- a/gcc/config/arc/linux.h
+++ b/gcc/config/arc/linux.h
@@ -45,7 +45,6 @@ along with GCC; see the file COPYING3. If not see
%{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}} \
-X \
%{mbig-endian:-EB} %{EB} %{EL} \
- %{!z:-z max-page-size=0x2000 -z common-page-size=0x2000} \
%{mcpu=nps400:-marclinux_nps; :-marclinux}"
#undef STARTFILE_SPEC
--
2.30.2
Re: [PATCH] Avoid depending on destructor order
Thanks, I haven't observed it. Waiting for it, Claudiu On Mon, Sep 26, 2022 at 2:49 PM Thomas Neumann wrote: > > Hi Claudiu, > > > This change prohibits compiling of ARC backend: > > > >> + gcc_assert (in_shutdown || ob); > > > > in_shutdown is only defined when ATOMIC_FDE_FAST_PATH is defined, > > while gcc_assert is outside of any ifdef. Please can you revisit this > > line and change it accordingly. > > I have a patch ready, I am waiting for someone to approve my patch: > > https://gcc.gnu.org/pipermail/gcc-patches/2022-September/602130.html > > Best > > Thomas
Re: [PATCH] Avoid depending on destructor order
Hi Thomas, This change prohibits compiling of ARC backend: > + gcc_assert (in_shutdown || ob); in_shutdown is only defined when ATOMIC_FDE_FAST_PATH is defined, while gcc_assert is outside of any ifdef. Please can you revisit this line and change it accordingly. Thanks, Claudiu
[committed] arc: Add ARCHS release 310a tune variant.
Add mtune and mcpu options for ARCHS release 310a type CPU. The
mtune=release31a is designed to be used as an alternative to the
mcpu=hs4x_rel31 option.
ARCHS4x release 31a uses DSP instructions which are implemented a bit
different than mpy9. Hence, use safer mpy2 option.
gcc/
* config/arc/arc-arch.h (arc_tune_attr): Add
ARC_TUNE_ARCHS4X_REL31A variant.
* config/arc/arc.cc (arc_override_options): Tune options for
release 310a.
(arc_sched_issue_rate): Use correct enum.
(arc600_corereg_hazard): Textual change.
(arc_hazard): Add release 310a tunning.
* config/arc/arc.md (tune): Update and take into consideration new
tune option.
(tune_dspmpy): Likewise.
(tune_store): New attribute.
* config/arc/arc.opt (mtune): New tune option.
* config/arc/arcHS4x.md (hs4x_brcc0, hs4x_brcc1): New cpu units.
(hs4x_brcc_op): New instruction rezervation.
(hs4x_data_store_1_op): Likewise.
* config/arc/arc-cpus.def (hs4x_rel31): New cpu variant.
* config/arc/arc-tables.opt: Regenerate.
* config/arc/t-multilib: Likewise.
* doc/invoke.texi (ARC): Update mcpu and tune sections.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc-arch.h | 3 +-
gcc/config/arc/arc-cpus.def | 1 +
gcc/config/arc/arc-tables.opt | 3 +
gcc/config/arc/arc.cc | 192 +-
gcc/config/arc/arc.md | 32 +++---
gcc/config/arc/arc.opt| 3 +
gcc/config/arc/arcHS4x.md | 17 ++-
gcc/config/arc/t-multilib | 4 +-
gcc/doc/invoke.texi | 16 +++
9 files changed, 181 insertions(+), 90 deletions(-)
diff --git a/gcc/config/arc/arc-arch.h b/gcc/config/arc/arc-arch.h
index 4c728a87453..83b156ee34a 100644
--- a/gcc/config/arc/arc-arch.h
+++ b/gcc/config/arc/arc-arch.h
@@ -77,7 +77,8 @@ enum arc_tune_attr
ARC_TUNE_CORE_3,
ARC_TUNE_ARCHS4X,
ARC_TUNE_ARCHS4XD,
-ARC_TUNE_ARCHS4XD_SLOW
+ARC_TUNE_ARCHS4XD_SLOW,
+ARC_TUNE_ARCHS4X_REL31A
};
/* Extra options for a processor template to hold any CPU specific
diff --git a/gcc/config/arc/arc-cpus.def b/gcc/config/arc/arc-cpus.def
index baf61db02ed..5668b0fbf19 100644
--- a/gcc/config/arc/arc-cpus.def
+++ b/gcc/config/arc/arc-cpus.def
@@ -64,6 +64,7 @@ ARC_CPU (hs38, hs, FL_MPYOPT_9|FL_DIVREM|FL_LL64,
NONE, NONE)
ARC_CPU (hs38_linux, hs, FL_MPYOPT_9|FL_DIVREM|FL_LL64|FL_FPU_FPUD_ALL, NONE,
NONE)
ARC_CPU (hs4x, hs, FL_MPYOPT_9|FL_DIVREM|FL_LL64, NONE, ARCHS4X)
ARC_CPU (hs4xd, hs, FL_MPYOPT_9|FL_DIVREM|FL_LL64, NONE, ARCHS4XD)
+ARC_CPU (hs4x_rel31, hs, FL_MPYOPT_2|FL_DIVREM|FL_LL64, NONE, ARCHS4X_REL31A)
ARC_CPU (arc600, 6xx, FL_BS, NONE, ARC600)
ARC_CPU (arc600_norm,6xx, FL_BS|FL_NORM, NONE, ARC600)
diff --git a/gcc/config/arc/arc-tables.opt b/gcc/config/arc/arc-tables.opt
index 8cc5135205d..0a0d354db60 100644
--- a/gcc/config/arc/arc-tables.opt
+++ b/gcc/config/arc/arc-tables.opt
@@ -69,6 +69,9 @@ Enum(processor_type) String(hs4x) Value(PROCESSOR_hs4x)
EnumValue
Enum(processor_type) String(hs4xd) Value(PROCESSOR_hs4xd)
+EnumValue
+Enum(processor_type) String(hs4x_rel31) Value(PROCESSOR_hs4x_rel31)
+
EnumValue
Enum(processor_type) String(arc600) Value(PROCESSOR_arc600)
diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index 77730c88e55..064790bf396 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -646,8 +646,8 @@ arc_sched_issue_rate (void)
{
switch (arc_tune)
{
-case TUNE_ARCHS4X:
-case TUNE_ARCHS4XD:
+case ARC_TUNE_ARCHS4X:
+case ARC_TUNE_ARCHS4XD:
return 3;
default:
break;
@@ -1458,6 +1458,12 @@ arc_override_options (void)
if (!OPTION_SET_P (unaligned_access) && TARGET_HS)
unaligned_access = 1;
+ if (TARGET_HS && (arc_tune == ARC_TUNE_ARCHS4X_REL31A))
+{
+ TARGET_CODE_DENSITY_FRAME = 0;
+ flag_delayed_branch = 0;
+}
+
/* These need to be done at start up. It's convenient to do them here. */
arc_init ();
}
@@ -7817,6 +7823,115 @@ arc_store_addr_hazard_p (rtx_insn* producer, rtx_insn*
consumer)
return arc_store_addr_hazard_internal_p (producer, consumer);
}
+/* Return length adjustment for INSN.
+ For ARC600:
+ A write to a core reg greater or equal to 32 must not be immediately
+ followed by a use. Anticipate the length requirement to insert a nop
+ between PRED and SUCC to prevent a hazard. */
+
+static int
+arc600_corereg_hazard (rtx_insn *pred, rtx_insn *succ)
+{
+ if (!TARGET_ARC600)
+return 0;
+ if (GET_CODE (PATTERN (pred)) == SEQUENCE)
+pred = as_a (PATTERN (pred))->insn (1);
+ if (GET_CODE (PATTERN (succ)) == SEQUENCE)
+succ = as_a (PATTERN (succ))->insn (0);
+ if (recog_memoized (pred) == CODE_FOR_mulsi_600
+ || recog_memoized (pred) == CODE_FOR_umul_600
+ || recog_memoized (pred) == CODE_FOR_mac_600
+ || recog_memoized (pred)
[committed 2/2] libgcc/arc: Update udivmodsi4 and make the lib safe for rf16
From: Claudiu Zissulescu
The ARC soft udivmodsi4 algorithm and as well as using umodsi3
for reduced register set configurations are wrong.
libgcc/
* config/arc/lib2funcs.c (udivmodsi4): Update AND mask.
* config/arc/lib1funcs.S (umodsi3): Don't use it for RF16
configurations.
---
libgcc/config/arc/lib1funcs.S | 2 ++
libgcc/config/arc/lib2funcs.c | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/libgcc/config/arc/lib1funcs.S b/libgcc/config/arc/lib1funcs.S
index 14fd1d2f303..b06361257d1 100644
--- a/libgcc/config/arc/lib1funcs.S
+++ b/libgcc/config/arc/lib1funcs.S
@@ -936,6 +936,7 @@ SYM(__divsi3):
#endif /* L_divsi3 */
+#ifndef __ARC_RF16__
#ifdef L_umodsi3
.section .text
.align 4
@@ -950,6 +951,7 @@ SYM(__umodsi3):
ENDFUNC(__umodsi3)
#endif /* L_umodsi3 */
+#endif /* !__ARC_RF16__ */
#ifdef L_modsi3
.section .text
diff --git a/libgcc/config/arc/lib2funcs.c b/libgcc/config/arc/lib2funcs.c
index 70727b55365..8cba45172b2 100644
--- a/libgcc/config/arc/lib2funcs.c
+++ b/libgcc/config/arc/lib2funcs.c
@@ -59,7 +59,7 @@ udivmodsi4 (nint32_t num, nint32_t den, word_t modwanted)
nint32_t bit = 1;
nint32_t res = 0;
- while (den < num && bit && !(den & (1LL << 63)))
+ while (den < num && bit && !(den & (1L << 31)))
{
den <<= 1;
bit <<= 1;
--
2.30.2
[committed 1/2] arc: Fix interrupt's epilogue.
The stack pointer adjustment in interrupt epilogue is happening after
restoring the ZOL registers which is wrong. Fixing this.
gcc/
* config/arc/arc.cc (arc_expand_epilogue): Adjust the frame
pointer first when in interrupts.
gcc/testsuite/
* gcc.target/arc/interrupt-13.c: New file.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc | 2 +-
gcc/testsuite/gcc.target/arc/interrupt-13.c | 15 +++
2 files changed, 16 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/arc/interrupt-13.c
diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index fbc17e684a0..77730c88e55 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -3965,7 +3965,7 @@ arc_expand_epilogue (int sibcall_p)
if (size)
emit_insn (gen_blockage ());
- if (ARC_INTERRUPT_P (fn_type) && restore_fp)
+ if (ARC_INTERRUPT_P (fn_type))
{
/* We need to restore FP before any SP operation in an
interrupt. */
diff --git a/gcc/testsuite/gcc.target/arc/interrupt-13.c
b/gcc/testsuite/gcc.target/arc/interrupt-13.c
new file mode 100644
index 000..0ed8451c512
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/interrupt-13.c
@@ -0,0 +1,15 @@
+/* { dg-options "-O2" } */
+
+extern int foo (int *);
+
+void __attribute__((interrupt("ilink")))
+irq (void)
+{
+ struct {
+int x0;
+int x1;
+ } a = {1 ,2};
+ foo ((int *));
+}
+
+/* { dg-final { scan-assembler "add_s\\s+sp,sp,8.*pop_s\\s+r0" } } */
--
2.30.2
[committed] arc: Fix interrupt's epilogue.
The stack pointer adjustment in interrupt epilogue is happening after
restoring the ZOL registers which is wrong. Fixing this.
gcc/
* config/arc/arc.cc (arc_expand_epilogue): Adjust the frame
pointer first when in interrupts.
gcc/testsuite/
* gcc.target/arc/interrupt-13.c: New file.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc | 2 +-
gcc/testsuite/gcc.target/arc/interrupt-13.c | 15 +++
2 files changed, 16 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/arc/interrupt-13.c
diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index fbc17e684a0..77730c88e55 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -3965,7 +3965,7 @@ arc_expand_epilogue (int sibcall_p)
if (size)
emit_insn (gen_blockage ());
- if (ARC_INTERRUPT_P (fn_type) && restore_fp)
+ if (ARC_INTERRUPT_P (fn_type))
{
/* We need to restore FP before any SP operation in an
interrupt. */
diff --git a/gcc/testsuite/gcc.target/arc/interrupt-13.c
b/gcc/testsuite/gcc.target/arc/interrupt-13.c
new file mode 100644
index 000..0ed8451c512
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/interrupt-13.c
@@ -0,0 +1,15 @@
+/* { dg-options "-O2" } */
+
+extern int foo (int *);
+
+void __attribute__((interrupt("ilink")))
+irq (void)
+{
+ struct {
+int x0;
+int x1;
+ } a = {1 ,2};
+ foo ((int *));
+}
+
+/* { dg-final { scan-assembler "add_s\\s+sp,sp,8.*pop_s\\s+r0" } } */
--
2.30.2
Re: [PATCH] arc: Fix for new ifcvt behavior [PR104154]
Hi Robin, The patch looks good. Please go ahead and merge it, please let me know if you cannot. Thank you, Claudiu On Mon, Feb 21, 2022 at 9:57 AM Robin Dapp via Gcc-patches < gcc-patches@gcc.gnu.org> wrote: > Hi, > > I figured I'd just go ahead and post this patch as well since it seems > to have fixed the arc build problems. > > It would be nice if someone could bootstrap/regtest if Jeff hasn't > already done so. I was able to verify that the two testcases attached > to the PR build cleanly but not much more. Thank you. > > Regards > Robin > > -- > > PR104154 > > gcc/ChangeLog: > > * config/arc/arc.cc (gen_compare_reg): Return the CC-mode > comparison ifcvt passed us. > > --- > > From fa98a40abd55e3a10653f6a8c5b2414a2025103b Mon Sep 17 00:00:00 2001 > From: Robin Dapp > Date: Mon, 7 Feb 2022 08:39:41 +0100 > Subject: [PATCH] arc: Fix for new ifcvt behavior [PR104154] > > ifcvt now passes a CC-mode "comparison" to backends. This patch > simply returns from gen_compare_reg () in that case since nothing > needs to be prepared anymore. > > PR104154 > > gcc/ChangeLog: > > * config/arc/arc.cc (gen_compare_reg): Return the CC-mode > comparison ifcvt passed us. > --- > gcc/config/arc/arc.cc | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc > index 8cc173519ab..5e40ec2c04d 100644 > --- a/gcc/config/arc/arc.cc > +++ b/gcc/config/arc/arc.cc > @@ -2254,6 +2254,12 @@ gen_compare_reg (rtx comparison, machine_mode omode) > > >cmode = GET_MODE (x); > + > + /* If ifcvt passed us a MODE_CC comparison we can > + just return it. It should be in the proper form already. */ > + if (GET_MODE_CLASS (cmode) == MODE_CC) > +return comparison; > + >if (cmode == VOIDmode) > cmode = GET_MODE (y); >gcc_assert (cmode == SImode || cmode == SFmode || cmode == DFmode); > -- > 2.31.1 > >
Re: [committed] arc: Fail conditional move expand patterns
Hi Robin, I don't know how I missed your arc related patch, I'll bootstrap and test your patch asap. Thanks, Claudiu On Fri, Feb 25, 2022 at 3:29 PM Robin Dapp wrote: > > If the movcc comparison is not valid it triggers an assert in the > > current implementation. This behavior is not needed as we can FAIL > > the movcc expand pattern. > > In case of a MODE_CC comparison you can also just return it as described > here https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104154 > > or here: > https://gcc.gnu.org/pipermail/gcc-patches/2022-February/590639.html > > If there already is a "CC comparison" the backend does not need to > create one and ifcvt can make use of this, creating better sequences. > > Regards > Robin >
[committed] arc: Fail conditional move expand patterns
If the movcc comparison is not valid it triggers an assert in the
current implementation. This behavior is not needed as we can FAIL
the movcc expand pattern.
gcc/
* config/arc/arc.cc (gen_compare_reg): Return NULL_RTX if the
comparison is not valid.
* config/arc/arc.md (movsicc): Fail if comparison is not valid.
(movdicc): Likewise.
(movsfcc): Likewise.
(movdfcc): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.cc | 3 ++-
gcc/config/arc/arc.md | 25 -
2 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc
index 8cc173519ab..c27ba99eb60 100644
--- a/gcc/config/arc/arc.cc
+++ b/gcc/config/arc/arc.cc
@@ -2256,7 +2256,8 @@ gen_compare_reg (rtx comparison, machine_mode omode)
cmode = GET_MODE (x);
if (cmode == VOIDmode)
cmode = GET_MODE (y);
- gcc_assert (cmode == SImode || cmode == SFmode || cmode == DFmode);
+ if (cmode != SImode && cmode != SFmode && cmode != DFmode)
+return NULL_RTX;
if (cmode == SImode)
{
if (!register_operand (x, SImode))
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index ace3cb70424..39b358052c1 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -1618,8 +1618,11 @@ (define_expand "movsicc"
(match_operand:SI 2 "nonmemory_operand" "")
(match_operand:SI 3 "register_operand" "")))]
""
- "operands[1] = gen_compare_reg (operands[1], VOIDmode);")
-
+ "
+ operands[1] = gen_compare_reg (operands[1], VOIDmode);
+ if (operands[1] == NULL_RTX)
+FAIL;
+ ")
(define_expand "movdicc"
[(set (match_operand:DI 0 "dest_reg_operand" "")
@@ -1627,7 +1630,11 @@ (define_expand "movdicc"
(match_operand:DI 2 "nonmemory_operand" "")
(match_operand:DI 3 "register_operand" "")))]
""
- "operands[1] = gen_compare_reg (operands[1], VOIDmode);")
+ "
+ operands[1] = gen_compare_reg (operands[1], VOIDmode);
+ if (operands[1] == NULL_RTX)
+FAIL;
+ ")
(define_expand "movsfcc"
@@ -1636,7 +1643,11 @@ (define_expand "movsfcc"
(match_operand:SF 2 "nonmemory_operand" "")
(match_operand:SF 3 "register_operand" "")))]
""
- "operands[1] = gen_compare_reg (operands[1], VOIDmode);")
+ "
+ operands[1] = gen_compare_reg (operands[1], VOIDmode);
+ if (operands[1] == NULL_RTX)
+FAIL;
+ ")
(define_expand "movdfcc"
[(set (match_operand:DF 0 "dest_reg_operand" "")
@@ -1644,7 +1655,11 @@ (define_expand "movdfcc"
(match_operand:DF 2 "nonmemory_operand" "")
(match_operand:DF 3 "register_operand" "")))]
""
- "operands[1] = gen_compare_reg (operands[1], VOIDmode);")
+ "
+ operands[1] = gen_compare_reg (operands[1], VOIDmode);
+ if (operands[1] == NULL_RTX)
+FAIL;
+ ")
(define_insn "*movsicc_insn"
[(set (match_operand:SI 0 "dest_reg_operand" "=w,w")
--
2.35.1
[committed] arc: Add DWARF2 alternate CFA column.
Add DWARF 2 CFA column which tracks the return address from a signal
handler context. This value must not correspond to a hard register
and must be out of the range of DWARF_FRAME_REGNUM().
gcc/
* config/arc/arc.h (DWARF_FRAME_REGNUM): Update definition.
(DWARF_FRAME_RETURN_COLUMN): Use RETURN_ADDR_REGNUM macro.
(INCOMING_RETURN_ADDR_RTX): Likewise.
(DWARF_ALT_FRAME_RETURN_COLUMN): Define.
gcc/testsuite/
* gcc.target/arc/cancel-1.c: New file.
libgcc/
* config/arc/linux-unwind.h (arc_fallback_frame_state): Use
DWARF_ALT_FRAME_RETURN_COLUMN macro.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.h| 11 ++---
gcc/testsuite/gcc.target/arc/cancel-1.c | 31 +
libgcc/config/arc/linux-unwind.h| 9 +++
3 files changed, 44 insertions(+), 7 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arc/cancel-1.c
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 78b5000eeb7..539a1662084 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -1356,7 +1356,7 @@ do { \
: (REGNO))
/* Use gcc hard register numbering for eh_frame. */
-#define DWARF_FRAME_REGNUM(REG) (REG)
+#define DWARF_FRAME_REGNUM(REG) ((REG) < 144 ? REG : INVALID_REGNUM)
/* Map register numbers held in the call frame info that gcc has
collected using DWARF_FRAME_REGNUM to those that should be output
@@ -1370,9 +1370,14 @@ do { \
: 57 + !!TARGET_MULMAC_32BY16_SET) /* MLO */ \
: (REGNO))
-#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (31)
+/* The DWARF 2 CFA column which tracks the return address. */
+#define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
+#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
-#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 31)
+/* The DWARF 2 CFA column which tracks the return address from a signal handler
+ context. This value must not correspond to a hard register and must be out
+ of the range of DWARF_FRAME_REGNUM(). */
+#define DWARF_ALT_FRAME_RETURN_COLUMN 144
/* Frame info. */
diff --git a/gcc/testsuite/gcc.target/arc/cancel-1.c
b/gcc/testsuite/gcc.target/arc/cancel-1.c
new file mode 100644
index 000..e050c538157
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/cancel-1.c
@@ -0,0 +1,31 @@
+/* Test for cleanups with pthread_cancel. Any issue with libgcc's unwinder
+ will cause this test to spin in pthread_join. */
+
+/* { dg-do run } */
+/* { dg-require-effective-target pthread } */
+/* { dg-options "-pthread" } */
+
+#include
+#include
+#include
+
+void *thread_loop (void *)
+{
+ while (1)
+{
+ printf("worker: loop\n");
+ sleep(1);
+}
+}
+
+int main ()
+{
+ pthread_t thread;
+
+ pthread_create (, 0, thread_loop, 0);
+ sleep(5);
+ pthread_cancel (thread);
+ pthread_join (thread, 0);
+
+ return 0;
+}
diff --git a/libgcc/config/arc/linux-unwind.h b/libgcc/config/arc/linux-unwind.h
index 1d8c0c55883..be42a3163b2 100644
--- a/libgcc/config/arc/linux-unwind.h
+++ b/libgcc/config/arc/linux-unwind.h
@@ -120,10 +120,11 @@ arc_fallback_frame_state (struct _Unwind_Context *context,
= ((_Unwind_Ptr) &(regs[i])) - new_cfa;
}
- fs->regs.reg[31].how = REG_SAVED_VAL_OFFSET;
- fs->regs.reg[31].loc.offset = ((_Unwind_Ptr) (regs[ret])) - new_cfa;
-
- fs->retaddr_column = 31;
+ fs->signal_frame = 1;
+ fs->retaddr_column = __LIBGCC_DWARF_ALT_FRAME_RETURN_COLUMN__;
+ fs->regs.reg[fs->retaddr_column].how = REG_SAVED_VAL_OFFSET;
+ fs->regs.reg[fs->retaddr_column].loc.offset =
+((_Unwind_Ptr) (regs[ret])) - new_cfa;
return _URC_NO_REASON;
}
--
2.31.1
[committed] arc: Update stack size computation when accumulator registers are available.
When accumulator registers are available in a processor, they need to
be save onto stack durring interrupts. We were already doing so, but
the stack size was wrongly computed in the case other than ARC600.
gcc/
* config/arc/arc.c (arc_compute_frame_size): Remove condition when
computin checking accumulator regs.
(arc_expand_prologue): Update comments.
(arc_expand_epilogue): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 6de364e9ce0..3096a9bef44 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -2897,9 +2897,8 @@ arc_compute_frame_size (void)
cfun, TARGET_DPFP))
reg_size += UNITS_PER_WORD * 2;
- /* Check for special MLO/MHI case used by ARC600' MUL64
- extension. */
- if (arc_must_save_register (R58_REG, cfun, TARGET_MUL64_SET))
+ /* Check if R58 is used. */
+ if (arc_must_save_register (R58_REG, cfun, true))
reg_size += UNITS_PER_WORD * 2;
/* 4) Calculate extra size made up of the blink + fp size. */
@@ -3878,7 +3877,7 @@ arc_expand_prologue (void)
}
}
- /* Save ARC600' MUL64 registers. */
+ /* Save accumulator registers. */
if (arc_must_save_register (R58_REG, cfun, true))
frame_size_to_allocate -= arc_save_callee_saves (3ULL << 58,
false, false, 0, false);
@@ -3971,7 +3970,7 @@ arc_expand_epilogue (int sibcall_p)
first_offset = 0;
}
- /* Restore ARC600' MUL64 registers. */
+ /* Restore accumulator registers. */
if (arc_must_save_register (R58_REG, cfun, true))
{
rtx insn;
--
2.31.1
[committed] arc: Update (u)maddhisi4 patterns
The (u)maddsihi4 patterns are using the ARC's VMAC2H(U)
instruction with null destination, however, VMAC2H(U) doesn't
rewrite the accumulator. This patch solves the destination issue
of VMAC2H by replacing it with DMACH(U) instruction.
gcc/
* config/arc/arc.md (maddhisi4): Use a single move to accumulator.
(umaddhisi4): Likewise.
(machi): Update pattern.
(umachi): Likewise.
gcc/testsuite/
* gcc.target/arc/tmac-4.c: New test.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.md | 34 +--
gcc/testsuite/gcc.target/arc/tmac-4.c | 29 +++
2 files changed, 46 insertions(+), 17 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arc/tmac-4.c
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 4919d275820..74ec38f1526 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -6023,26 +6023,26 @@ (define_insn "stack_irq_dwarf"
(define_expand "maddhisi4"
[(match_operand:SI 0 "register_operand" "")
(match_operand:HI 1 "register_operand" "")
- (match_operand:HI 2 "extend_operand" "")
+ (match_operand:HI 2 "register_operand" "")
(match_operand:SI 3 "register_operand" "")]
"TARGET_PLUS_MACD"
"{
- rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
+ rtx acc_reg = gen_rtx_REG (SImode, ACCL_REGNO);
emit_move_insn (acc_reg, operands[3]);
- emit_insn (gen_machi (operands[1], operands[2]));
- emit_move_insn (operands[0], acc_reg);
+ emit_insn (gen_machi (operands[0], operands[1], operands[2], acc_reg));
DONE;
}")
(define_insn "machi"
- [(set (reg:SI ARCV2_ACC)
+ [(set (match_operand:SI 0 "register_operand" "=Ral,r")
(plus:SI
-(mult:SI (sign_extend:SI (match_operand:HI 0 "register_operand" "%r"))
- (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))
-(reg:SI ARCV2_ACC)))]
+(mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand"
"%r,r"))
+ (sign_extend:SI (match_operand:HI 2 "register_operand"
"r,r")))
+(match_operand:SI 3 "accl_operand" "")))
+ (clobber (reg:DI ARCV2_ACC))]
"TARGET_PLUS_MACD"
- "vmac2h\\t0,%0,%1"
+ "dmach\\t%0,%1,%2"
[(set_attr "length" "4")
(set_attr "type" "multi")
(set_attr "predicable" "no")
@@ -6056,22 +6056,22 @@ (define_expand "umaddhisi4"
(match_operand:SI 3 "register_operand" "")]
"TARGET_PLUS_MACD"
"{
- rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
+ rtx acc_reg = gen_rtx_REG (SImode, ACCL_REGNO);
emit_move_insn (acc_reg, operands[3]);
- emit_insn (gen_umachi (operands[1], operands[2]));
- emit_move_insn (operands[0], acc_reg);
+ emit_insn (gen_umachi (operands[0], operands[1], operands[2], acc_reg));
DONE;
}")
(define_insn "umachi"
- [(set (reg:SI ARCV2_ACC)
+ [(set (match_operand:SI 0 "register_operand" "=Ral,r")
(plus:SI
-(mult:SI (zero_extend:SI (match_operand:HI 0 "register_operand" "%r"))
- (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
-(reg:SI ARCV2_ACC)))]
+(mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand"
"%r,r"))
+ (zero_extend:SI (match_operand:HI 2 "register_operand"
"r,r")))
+(match_operand:SI 3 "accl_operand" "")))
+ (clobber (reg:DI ARCV2_ACC))]
"TARGET_PLUS_MACD"
- "vmac2hu\\t0,%0,%1"
+ "dmachu\\t%0,%1,%2"
[(set_attr "length" "4")
(set_attr "type" "multi")
(set_attr "predicable" "no")
diff --git a/gcc/testsuite/gcc.target/arc/tmac-4.c
b/gcc/testsuite/gcc.target/arc/tmac-4.c
new file mode 100644
index 000..3c6b99327a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/tmac-4.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-skip-if "" { ! { clmcpu } } } */
+/* { dg-options "-O3 -mbig-endian -mcpu=hs38" } */
+
+struct a {};
+struct b {
+ int c;
+ int d;
+};
+
+struct {
+ struct a e;
+ struct b f[];
+} g;
+short h;
+
+extern void bar (int *);
+
+int foo(void)
+{
+ struct b *a;
+ for (;;)
+{
+ a = [h];
+ bar(>d);
+}
+}
+
+/* { dg-final { scan-assembler "dmach" } } */
--
2.31.1
[committed] arc: Update arc specific tests
Update assembly output test pattern. Take into consideration also for
which platform we do execute the test (baremetal or linux).
gcc/testsuite/ChangeLog:
* gcc.target/arc/add_n-combine.c: Update test patterns.
* gcc.target/arc/builtin_eh.c: Update test for linux platforms.
* gcc.target/arc/mul64-1.c: Disable this test while running on
linux.
* gcc.target/arc/tls-gd.c: Update matching patterns.
* gcc.target/arc/tls-ie.c: Likewise.
* gcc.target/arc/tls-ld.c: Likewise.
* gcc.target/arc/uncached-8.c: Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/testsuite/gcc.target/arc/add_n-combine.c | 4 ++--
gcc/testsuite/gcc.target/arc/builtin_eh.c| 3 ++-
gcc/testsuite/gcc.target/arc/mul64-1.c | 2 +-
gcc/testsuite/gcc.target/arc/tls-gd.c| 4 ++--
gcc/testsuite/gcc.target/arc/tls-ie.c| 4 ++--
gcc/testsuite/gcc.target/arc/tls-ld.c| 6 +++---
gcc/testsuite/gcc.target/arc/uncached-8.c| 5 +++--
7 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/gcc/testsuite/gcc.target/arc/add_n-combine.c
b/gcc/testsuite/gcc.target/arc/add_n-combine.c
index bc400df669e..84e261ece8f 100644
--- a/gcc/testsuite/gcc.target/arc/add_n-combine.c
+++ b/gcc/testsuite/gcc.target/arc/add_n-combine.c
@@ -45,6 +45,6 @@ void f() {
a(at3.bn[bu]);
}
-/* { dg-final { scan-assembler "add1" } } */
-/* { dg-final { scan-assembler "add2" } } */
+/* { dg-final { scan-assembler "@at1\\+1" } } */
+/* { dg-final { scan-assembler "@at2\\+2" } } */
/* { dg-final { scan-assembler "add3" } } */
diff --git a/gcc/testsuite/gcc.target/arc/builtin_eh.c
b/gcc/testsuite/gcc.target/arc/builtin_eh.c
index 717a54bb084..83f4f1d2ee0 100644
--- a/gcc/testsuite/gcc.target/arc/builtin_eh.c
+++ b/gcc/testsuite/gcc.target/arc/builtin_eh.c
@@ -19,4 +19,5 @@ foo (int x)
/* { dg-final { scan-assembler "r13" } } */
/* { dg-final { scan-assembler "r0" } } */
/* { dg-final { scan-assembler "fp" } } */
-/* { dg-final { scan-assembler "fp,64" } } */
+/* { dg-final { scan-assembler "fp,64" { target { *-elf32-* } } } } */
+/* { dg-final { scan-assembler "fp,60" { target { *-linux-* } } } } */
diff --git a/gcc/testsuite/gcc.target/arc/mul64-1.c
b/gcc/testsuite/gcc.target/arc/mul64-1.c
index 2543fc33d3f..1a351feee87 100644
--- a/gcc/testsuite/gcc.target/arc/mul64-1.c
+++ b/gcc/testsuite/gcc.target/arc/mul64-1.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-skip-if "MUL64 is ARC600 extension." { ! { clmcpu } } } */
+/* { dg-skip-if "MUL64 is ARC600 extension." { { ! { clmcpu } } || *-linux-* }
} */
/* { dg-options "-O2 -mmul64 -mbig-endian -mcpu=arc600" } */
/* Check if mlo/mhi registers are correctly layout when we compile for
diff --git a/gcc/testsuite/gcc.target/arc/tls-gd.c
b/gcc/testsuite/gcc.target/arc/tls-gd.c
index aa1b5429b08..d02af9537f8 100644
--- a/gcc/testsuite/gcc.target/arc/tls-gd.c
+++ b/gcc/testsuite/gcc.target/arc/tls-gd.c
@@ -13,5 +13,5 @@ int *ae2 (void)
return
}
-/* { dg-final { scan-assembler "add r0,pcl,@e2@tlsgd" } } */
-/* { dg-final { scan-assembler "bl @__tls_get_addr@plt" } } */
+/* { dg-final { scan-assembler "add\\s+r0,pcl,@e2@tlsgd" } } */
+/* { dg-final { scan-assembler "bl\\s+@__tls_get_addr@plt" } } */
diff --git a/gcc/testsuite/gcc.target/arc/tls-ie.c
b/gcc/testsuite/gcc.target/arc/tls-ie.c
index 0c981cfbf67..f4ad635c4d3 100644
--- a/gcc/testsuite/gcc.target/arc/tls-ie.c
+++ b/gcc/testsuite/gcc.target/arc/tls-ie.c
@@ -13,5 +13,5 @@ int *ae2 (void)
return
}
-/* { dg-final { scan-assembler "ld r0,\\\[pcl,@e2@tlsie\\\]" } } */
-/* { dg-final { scan-assembler "add_s r0,r0,r25" } } */
+/* { dg-final { scan-assembler "ld\\s+r0,\\\[pcl,@e2@tlsie\\\]" } } */
+/* { dg-final { scan-assembler "add_s\\s+r0,r0,r25" } } */
diff --git a/gcc/testsuite/gcc.target/arc/tls-ld.c
b/gcc/testsuite/gcc.target/arc/tls-ld.c
index 351c3f02abd..68ab9bf809c 100644
--- a/gcc/testsuite/gcc.target/arc/tls-ld.c
+++ b/gcc/testsuite/gcc.target/arc/tls-ld.c
@@ -13,6 +13,6 @@ int *ae2 (void)
return
}
-/* { dg-final { scan-assembler "add r0,pcl,@.tbss@tlsgd" } } */
-/* { dg-final { scan-assembler "bl @__tls_get_addr@plt" } } */
-/* { dg-final { scan-assembler "add_s r0,r0,@e2@dtpoff" } } */
+/* { dg-final { scan-assembler "add\\s+r0,pcl,@.tbss@tlsgd" } } */
+/* { dg-final { scan-assembler "bl\\s+@__tls_get_addr@plt" } } */
+/* { dg-final { scan-assembler "add_s\\s+r0,r0,@e2@dtpoff" } } */
diff --git a/gcc/testsuite/gcc.target/arc/uncached-8.c
b/gcc/testsuite/gcc.target/arc/uncached-8.c
index 060229b11df..b5ea2359a9a 100644
--- a/gcc/testsuite/gcc.target/arc/uncached-8.c
+++ b/gcc/testsuite/gcc.target/arc/uncached-8.c
@@ -29,5 +29,6 @@ void bar (vo
[committed] arc: Update ZOL pattern.
The ZOL pattern is missing modes which may lead to errors during
var_tracking. Add them.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.md (doloop_end): Add missing mode.
(loop_end): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.md | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 90ba85e274e..4919d275820 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -4966,8 +4966,8 @@ (define_expand "doloop_end"
(const_int 1))
(label_ref (match_operand 1 "" ""))
(pc)))
- (set (match_dup 0) (plus (match_dup 0) (const_int -1)))
- (unspec [(const_int 0)] UNSPEC_ARC_LP)
+ (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))
+ (unspec:SI [(const_int 0)] UNSPEC_ARC_LP)
(clobber (match_dup 2))])]
""
{
@@ -4996,8 +4996,8 @@ (define_insn_and_split "loop_end"
(const_int 1))
(label_ref (match_operand 1 "" ""))
(pc)))
- (set (match_dup 0) (plus (match_dup 0) (const_int -1)))
- (unspec [(const_int 0)] UNSPEC_ARC_LP)
+ (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))
+ (unspec:SI [(const_int 0)] UNSPEC_ARC_LP)
(clobber (match_scratch:SI 2 "=X,"))]
""
"@
--
2.31.1
[committed] arc: Small data doesn't need fcommon option
ARC backend is defaulting to -fcommon. This is not anylonger needed, remove it.
gcc/
2021-08-12 Claudiu Zissulescu
* common/config/arc/arc-common.c (arc_option_init_struct): Remove
fno-common reference.
* config/arc/arc.c (arc_override_options): Remove overriding of
flag_no_common.
Signed-off-by: Claudiu Zissulescu
---
gcc/common/config/arc/arc-common.c | 4 +---
gcc/config/arc/arc.c | 3 ---
2 files changed, 1 insertion(+), 6 deletions(-)
diff --git a/gcc/common/config/arc/arc-common.c
b/gcc/common/config/arc/arc-common.c
index 6a119029616..3b36d09997c 100644
--- a/gcc/common/config/arc/arc-common.c
+++ b/gcc/common/config/arc/arc-common.c
@@ -30,10 +30,8 @@ along with GCC; see the file COPYING3. If not see
#include "flags.h"
static void
-arc_option_init_struct (struct gcc_options *opts)
+arc_option_init_struct (struct gcc_options *opts ATTRIBUTE_UNUSED)
{
- opts->x_flag_no_common = 255; /* Mark as not user-initialized. */
-
/* Which cpu we're compiling for (ARC600, ARC601, ARC700, ARCv2). */
arc_cpu = PROCESSOR_NONE;
}
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 69f6ae464e1..92797db96b7 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -1440,9 +1440,6 @@ arc_override_options (void)
if (flag_pic)
target_flags |= MASK_NO_SDATA_SET;
- if (flag_no_common == 255)
-flag_no_common = !TARGET_NO_SDATA_SET;
-
/* Check for small data option */
if (!global_options_set.x_g_switch_value && !TARGET_NO_SDATA_SET)
g_switch_value = TARGET_LL64 ? 8 : 4;
--
2.31.1
Re: [PATCH] arc: Add --with-fpu support for ARCv2 cpus
Thanks a lot guys. Patch is pushed. //Claudiu On Mon, Jun 14, 2021 at 12:34 AM Jeff Law wrote: > > > > On 6/13/2021 4:06 AM, Bernhard Reutner-Fischer wrote: > > On Fri, 11 Jun 2021 14:25:24 +0300 > > Claudiu Zissulescu wrote: > > > >> Hi Bernhard, > >> > >> Please find attached my latest patch, it includes (hopefully) all your > >> feedback. > >> > >> Thank you for comments, > > concise and clean, i wouldn't know what to remove. LGTM. > > thanks for your patience! > THen let's consider it approved at this point. Thanks for chiming in > Bernhard and thanks for implementing the suggestions Claudiu! > > jeff
Re: [PATCH] arc: Add --with-fpu support for ARCv2 cpus
Hi Bernhard,
Please find attached my latest patch, it includes (hopefully) all your
feedback.
Thank you for comments,
Claudiu
>From 03075b3d9194120d7adb3cdc2aa0f58e3ea9dd1d Mon Sep 17 00:00:00 2001
From: Claudiu Zissulescu
Date: Wed, 21 Oct 2020 16:11:43 +0300
Subject: [PATCH] arc: Add --with-fpu support for ARCv2 cpus
Support for a compile-time default FPU. The --with-fpu configuration
option is ignored if -mfpu compiler option is specified. The FPU
options are only available for ARCv2 cpus.
gcc/
-mm-dd Claudiu Zissulescu
* config.gcc (arc): Add support for with_cpu option.
* config/arc/arc.h (OPTION_DEFAULT_SPECS): Add fpu.
Signed-off-by: Claudiu Zissulescu
---
gcc/config.gcc | 44 +++-
gcc/config/arc/arc.h | 4
2 files changed, 43 insertions(+), 5 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 13c2004e3c52..5581dae88b52 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4258,18 +4258,52 @@ case "${target}" in
;;
arc*-*-*)
- supported_defaults="cpu"
+ supported_defaults="cpu fpu"
+ new_cpu=hs38_linux
if [ x"$with_cpu" = x ] \
- || grep "^ARC_CPU ($with_cpu," \
- ${srcdir}/config/arc/arc-cpus.def \
- > /dev/null; then
+ || grep -q -E "^ARC_CPU[[:blank:]]*\($with_cpu," \
+ ${srcdir}/config/arc/arc-cpus.def
+ then
# Ok
- true
+ new_cpu=$with_cpu
else
echo "Unknown cpu used in --with-cpu=$with_cpu" 1>&2
exit 1
fi
+
+ # see if --with-fpu matches any of the supported FPUs
+ case "$with_fpu" in
+ "")
+ # OK
+ ;;
+ fpus | fpus_div | fpus_fma | fpus_all)
+ # OK if em or hs
+ flags_ok="[emhs]+"
+ ;;
+ fpuda | fpuda_div | fpuda_fma | fpuda_all)
+ # OK only em
+ flags_ok="em"
+ ;;
+ fpud | fpud_div | fpud_fma | fpud_all)
+ # OK only hs
+ flags_ok="hs"
+ ;;
+ *)
+ echo "Unknown floating point type used in "\
+ "--with-fpu=$with_fpu" 1>&2
+ exit 1
+ ;;
+ esac
+
+ if [ -n "$flags_ok" ] \
+ && ! grep -q -E "^ARC_CPU[[:blank:]]*\($new_cpu,[[:blank:]]*$flags_ok," \
+ ${srcdir}/config/arc/arc-cpus.def
+ then
+ echo "Unknown floating point type used in "\
+ "--with-fpu=$with_fpu for cpu $new_cpu" 1>&2
+ exit 1
+ fi
;;
csky-*-*)
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 2ccebfa7afe6..e78f6e8202b3 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -100,7 +100,11 @@ extern const char *arc_cpu_to_as (int argc, const char **argv);
"%:cpu_to_as(%{mcpu=*:%*}) %{mspfp*} %{mdpfp*} " \
"%{mfpu=fpuda*:-mfpuda} %{mcode-density}"
+/* Support for a compile-time default CPU and FPU. The rules are:
+ --with-cpu is ignored if -mcpu, mARC*, marc*, mA7, mA6 are specified.
+ --with-fpu is ignored if -mfpu is specified. */
#define OPTION_DEFAULT_SPECS \
+ {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
{"cpu", "%{!mcpu=*:%{!mARC*:%{!marc*:%{!mA7:%{!mA6:-mcpu=%(VALUE)}" }
#ifndef DRIVER_ENDIAN_SELF_SPECS
--
2.31.1
Re: [PATCH] arc: Add --with-fpu support for ARCv2 cpus
Hi,
I would have written [[:space:]]* instead of [[:space:]]+ to handle
potentially missing space, at least after the comma but also before the
comma to avoid surprises for new names in the future.
Furthermore | alone would be [[:blank:]]* but as you prefer.
grep ... > /dev/null would be grep -q which is mandated by POSIX since
at least SUSv2 so can be used safely since quite some time now.
Instead of the redundant 'true' calls, i'd usually write :
E.g.
if grep -q ... ; then :
else echo "nah"; exit 1
fi
Which could be shortened to
if ! grep -q ...
then
echo "nah"
exit 1
fi
to avoid any questions about an empty arm in the first place.
I've updated the patch using your feedback (attached). Indeed, it looks
much better now :)
ISTM you only set the expected flags in the switch so i would have
set only that variable and have grepped only once after the switch for
brevity.
ARC has various FPU extensions, some of them are common to EM and HS
architectures, others are specific for only one of them. Hence, the grep
commands are ensuring that we accept the right fpu extension for the
right ARC architecture.
Either way, thanks for not using grep -P :)
thanks,
I thank you!
Claudiu
>From 1f895d277752277fb51e8436903a94949bd5c7bd Mon Sep 17 00:00:00 2001
From: Claudiu Zissulescu
Date: Wed, 21 Oct 2020 16:11:43 +0300
Subject: [PATCH] arc: Add --with-fpu support for ARCv2 cpus
Support for a compile-time default FPU. The --with-fpu configuration
option is ignored if -mfpu compiler option is specified. The FPU
options are only available for ARCv2 cpus.
gcc/
-mm-dd Claudiu Zissulescu
* config.gcc (arc): Add support for with_cpu option.
* config/arc/arc.h (OPTION_DEFAULT_SPECS): Add fpu.
Signed-off-by: Claudiu Zissulescu
---
gcc/config.gcc | 49 +---
gcc/config/arc/arc.h | 4
2 files changed, 50 insertions(+), 3 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 13c2004e3c52..09886c8635e0 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4258,18 +4258,61 @@ case "${target}" in
;;
arc*-*-*)
- supported_defaults="cpu"
+ supported_defaults="cpu fpu"
+ new_cpu=hs38_linux
if [ x"$with_cpu" = x ] \
- || grep "^ARC_CPU ($with_cpu," \
+ || grep -E "^ARC_CPU \($with_cpu," \
${srcdir}/config/arc/arc-cpus.def \
> /dev/null; then
# Ok
- true
+ new_cpu=$with_cpu
else
echo "Unknown cpu used in --with-cpu=$with_cpu" 1>&2
exit 1
fi
+
+ # see if --with-fpu matches any of the supported FPUs
+ case "$with_fpu" in
+ "")
+ # OK
+ ;;
+ fpus | fpus_div | fpus_fma | fpus_all)
+ # OK if em or hs
+ if ! grep -q -E "^ARC_CPU[[:blank:]]*\($new_cpu,[[:space:]]*[emhs]+," \
+ ${srcdir}/config/arc/arc-cpus.def
+ then
+ echo "Unknown floating point type used in "\
+ "--with-fpu=$with_fpu for cpu $new_cpu" 1>&2
+ exit 1
+ fi
+ ;;
+ fpuda | fpuda_div | fpuda_fma | fpuda_all)
+ # OK only em
+ if ! grep -q -E "^ARC_CPU[[:blank:]]*\($new_cpu,[[:space:]]*em," \
+ ${srcdir}/config/arc/arc-cpus.def
+ then
+ echo "Unknown floating point type used in "\
+ "--with-fpu=$with_fpu for cpu $new_cpu" 1>&2
+ exit 1
+ fi
+ ;;
+ fpud | fpud_div | fpud_fma | fpud_all)
+ # OK only hs
+ if ! grep -q -E "^ARC_CPU[[:blank:]]*\($new_cpu,[[:space:]]*hs," \
+ ${srcdir}/config/arc/arc-cpus.def
+ then
+ echo "Unknown floating point type used in"\
+ "--with-fpu=$with_fpu for cpu $new_cpu" 1>&2
+ exit 1
+ fi
+ ;;
+ *)
+ echo "Unknown floating point type used in "\
+ "--with-fpu=$with_fpu" 1>&2
+ exit 1
+ ;;
+ esac
;;
csky-*-*)
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 722bb10b8813..b9c4ba0398e5 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -100,7 +100,11 @@ extern const char *arc_cpu_to_as (int argc, const char **argv);
"%:cpu_to_as(%{mcpu=*:%*}) %{mspfp*} %{mdpfp*} " \
"%{mfpu=fpuda*:-mfpuda} %{mcode-density}"
+/* Support for a compile-time default CPU and FPU. The rules are:
+ --with-cpu is ignored if -mcpu, mARC*, marc*, mA7, mA6 are specified.
+ --with-fpu is ignored if -mfpu is specified. */
#define OPTION_DEFAULT_SPECS \
+ {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
{"cpu", "%{!mcpu=*:%{!mARC*:%{!marc*:%{!mA7:%{!mA6:-mcpu=%(VALUE)}" }
#ifndef DRIVER_ENDIAN_SELF_SPECS
--
2.31.1
[committed] arc: Update doloop_end patterns
ARC processor can use LP instruction to implement zero overlay loops. The current inplementation doesn't handle the unlikely situation when the loop iterator is located in memory. Refurbish the loop_end insn pattern into a define_insn_and_split pattern. This patch is also backported to gcc11. gcc/ -dd-mm Claudiu Zissulescu * config/arc/arc.md (loop_end): Change it to define_insn_and_split. Signed-off-by: Claudiu Zissulescu --- gcc/config/arc/arc.md | 46 +++ 1 file changed, 20 insertions(+), 26 deletions(-) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index aed0b40728b..90ba85e274e 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -4962,7 +4962,7 @@ (define_insn "*bbit" (define_expand "doloop_end" [(parallel [(set (pc) (if_then_else - (ne (match_operand 0 "" "") + (ne (match_operand 0 "nonimmediate_operand") (const_int 1)) (label_ref (match_operand 1 "" "")) (pc))) @@ -4988,44 +4988,38 @@ (define_insn "arc_lp" ;; if by any chance the lp_count is not used, then use an 'r' ;; register, instead of going to memory. -(define_insn "loop_end" - [(set (pc) - (if_then_else (ne (match_operand:SI 2 "nonimmediate_operand" "0,m") - (const_int 1)) - (label_ref (match_operand 1 "" "")) - (pc))) - (set (match_operand:SI 0 "nonimmediate_operand" "=r,m") - (plus (match_dup 2) (const_int -1))) - (unspec [(const_int 0)] UNSPEC_ARC_LP) - (clobber (match_scratch:SI 3 "=X,"))] - "" - "; ZOL_END, begins @%l1" - [(set_attr "length" "0") - (set_attr "predicable" "no") - (set_attr "type" "loop_end")]) - ;; split pattern for the very slim chance when the loop register is ;; memory. -(define_split +(define_insn_and_split "loop_end" [(set (pc) - (if_then_else (ne (match_operand:SI 0 "memory_operand") + (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "+r,!m") (const_int 1)) - (label_ref (match_operand 1 "")) + (label_ref (match_operand 1 "" "")) (pc))) (set (match_dup 0) (plus (match_dup 0) (const_int -1))) (unspec [(const_int 0)] UNSPEC_ARC_LP) - (clobber (match_scratch:SI 2))] - "memory_operand (operands[0], SImode)" + (clobber (match_scratch:SI 2 "=X,"))] + "" + "@ + ; ZOL_END, begins @%l1 + #" + "reload_completed && memory_operand (operands[0], Pmode)" [(set (match_dup 2) (match_dup 0)) - (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) + (parallel +[(set (reg:CC_ZN CC_REG) + (compare:CC_ZN (plus:SI (match_dup 2) (const_int -1)) +(const_int 0))) + (set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))]) (set (match_dup 0) (match_dup 2)) - (set (reg:CC CC_REG) (compare:CC (match_dup 2) (const_int 0))) (set (pc) - (if_then_else (ne (reg:CC CC_REG) + (if_then_else (ne (reg:CC_ZN CC_REG) (const_int 0)) (label_ref (match_dup 1)) (pc)))] - "") + "" + [(set_attr "length" "0,24") + (set_attr "predicable" "no") + (set_attr "type" "loop_end")]) (define_insn "loop_fail" [(set (reg:SI LP_COUNT) -- 2.31.1
[committed] arc: Fix (u)maddhisi patterns
Rework the (u)maddhisi4 patterns and use VMAC2H(U) instruction instead
of the 64bit MAC(U) instruction.
This fixes the next execute.exp failures:
arith-rand-ll.c -O2 execution test
arith-rand-ll.c -O3 execution test
pr78726.c -O2 execution test
pr78726.c -O3 execution test
Backported to gcc11 too.
gcc/
2021-06-09 Claudiu Zissulescu
* config/arc/arc.md (maddhisi4): Use VMAC2H instruction.
(machi): New pattern.
(umaddhisi4): Use VMAC2HU instruction.
(umachi): New pattern.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.md | 66 +++
1 file changed, 41 insertions(+), 25 deletions(-)
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 6f13b3a01d8..aed0b40728b 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -6025,48 +6025,64 @@ (define_insn "stack_irq_dwarf"
;; MAC and DMPY instructions
-; Use MAC instruction to emulate 16bit mac.
+; Use VMAC2H(U) instruction to emulate scalar 16bit mac.
(define_expand "maddhisi4"
[(match_operand:SI 0 "register_operand" "")
(match_operand:HI 1 "register_operand" "")
(match_operand:HI 2 "extend_operand" "")
(match_operand:SI 3 "register_operand" "")]
- "TARGET_PLUS_DMPY"
+ "TARGET_PLUS_MACD"
"{
- rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
- rtx tmp1 = gen_reg_rtx (SImode);
- rtx tmp2 = gen_reg_rtx (SImode);
- rtx accl = gen_lowpart (SImode, acc_reg);
-
- emit_move_insn (accl, operands[3]);
- emit_insn (gen_rtx_SET (tmp1, gen_rtx_SIGN_EXTEND (SImode, operands[1])));
- emit_insn (gen_rtx_SET (tmp2, gen_rtx_SIGN_EXTEND (SImode, operands[2])));
- emit_insn (gen_mac (tmp1, tmp2));
- emit_move_insn (operands[0], accl);
+ rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
+
+ emit_move_insn (acc_reg, operands[3]);
+ emit_insn (gen_machi (operands[1], operands[2]));
+ emit_move_insn (operands[0], acc_reg);
DONE;
}")
-; The same for the unsigned variant, but using MACU instruction.
+(define_insn "machi"
+ [(set (reg:SI ARCV2_ACC)
+ (plus:SI
+(mult:SI (sign_extend:SI (match_operand:HI 0 "register_operand" "%r"))
+ (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))
+(reg:SI ARCV2_ACC)))]
+ "TARGET_PLUS_MACD"
+ "vmac2h\\t0,%0,%1"
+ [(set_attr "length" "4")
+ (set_attr "type" "multi")
+ (set_attr "predicable" "no")
+ (set_attr "cond" "nocond")])
+
+; The same for the unsigned variant, but using VMAC2HU instruction.
(define_expand "umaddhisi4"
[(match_operand:SI 0 "register_operand" "")
(match_operand:HI 1 "register_operand" "")
- (match_operand:HI 2 "extend_operand" "")
+ (match_operand:HI 2 "register_operand" "")
(match_operand:SI 3 "register_operand" "")]
- "TARGET_PLUS_DMPY"
+ "TARGET_PLUS_MACD"
"{
- rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
- rtx tmp1 = gen_reg_rtx (SImode);
- rtx tmp2 = gen_reg_rtx (SImode);
- rtx accl = gen_lowpart (SImode, acc_reg);
-
- emit_move_insn (accl, operands[3]);
- emit_insn (gen_rtx_SET (tmp1, gen_rtx_ZERO_EXTEND (SImode, operands[1])));
- emit_insn (gen_rtx_SET (tmp2, gen_rtx_ZERO_EXTEND (SImode, operands[2])));
- emit_insn (gen_macu (tmp1, tmp2));
- emit_move_insn (operands[0], accl);
+ rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
+
+ emit_move_insn (acc_reg, operands[3]);
+ emit_insn (gen_umachi (operands[1], operands[2]));
+ emit_move_insn (operands[0], acc_reg);
DONE;
}")
+(define_insn "umachi"
+ [(set (reg:SI ARCV2_ACC)
+ (plus:SI
+(mult:SI (zero_extend:SI (match_operand:HI 0 "register_operand" "%r"))
+ (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
+(reg:SI ARCV2_ACC)))]
+ "TARGET_PLUS_MACD"
+ "vmac2hu\\t0,%0,%1"
+ [(set_attr "length" "4")
+ (set_attr "type" "multi")
+ (set_attr "predicable" "no")
+ (set_attr "cond" "nocond")])
+
(define_expand "maddsidi4"
[(match_operand:DI 0 "register_operand" "")
(match_operand:SI 1 "register_operand" "")
--
2.31.1
[committed] arc: Update 64bit move split patterns.
ARCv2HS can use a limited number of instructions to implement 64bit
moves. The VADD2 is used as a 64bit move, the LDD/STD are 64 bit loads
and stores. All those instructions are not baseline, hence we need to
provide alternatives when they are not available or cannot be generate
due to instruction restriction.
This patch is cleaning up those move patterns, and updates splits
instruction lengths.
Backported to gcc11 too.
gcc/
2021-06-09 Claudiu Zissulescu
* config/arc/arc-protos.h (arc_split_move_p): New prototype.
* config/arc/arc.c (arc_split_move_p): New function.
(arc_split_move): Clean up.
* config/arc/arc.md (movdi_insn): Clean up, use arc_split_move_p.
(movdf_insn): Likewise.
* config/arc/simdext.md (mov_insn): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc-protos.h | 1 +
gcc/config/arc/arc.c| 44 ++
gcc/config/arc/arc.md | 91 -
gcc/config/arc/simdext.md | 38
4 files changed, 52 insertions(+), 122 deletions(-)
diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
index 1f56a0d82e4..62d7e45d29d 100644
--- a/gcc/config/arc/arc-protos.h
+++ b/gcc/config/arc/arc-protos.h
@@ -50,6 +50,7 @@ extern void arc_split_ior (rtx *);
extern bool arc_check_mov_const (HOST_WIDE_INT );
extern bool arc_split_mov_const (rtx *);
extern bool arc_can_use_return_insn (void);
+extern bool arc_split_move_p (rtx *);
#endif /* RTX_CODE */
extern bool arc_ccfsm_branch_deleted_p (void);
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 0d34c964963..69f6ae464e1 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -10108,6 +10108,31 @@ arc_process_double_reg_moves (rtx *operands)
return true;
}
+
+/* Check if we need to split a 64bit move. We do not need to split it if we
can
+ use vadd2 or ldd/std instructions. */
+
+bool
+arc_split_move_p (rtx *operands)
+{
+ machine_mode mode = GET_MODE (operands[0]);
+
+ if (TARGET_LL64
+ && ((memory_operand (operands[0], mode)
+ && (even_register_operand (operands[1], mode)
+ || satisfies_constraint_Cm3 (operands[1])))
+ || (memory_operand (operands[1], mode)
+ && even_register_operand (operands[0], mode
+return false;
+
+ if (TARGET_PLUS_QMACW
+ && even_register_operand (operands[0], mode)
+ && even_register_operand (operands[1], mode))
+return false;
+
+ return true;
+}
+
/* operands 0..1 are the operands of a 64 bit move instruction.
split it into two moves with operands 2/3 and 4/5. */
@@ -10125,25 +10150,6 @@ arc_split_move (rtx *operands)
return;
}
- if (TARGET_LL64
- && ((memory_operand (operands[0], mode)
- && (even_register_operand (operands[1], mode)
- || satisfies_constraint_Cm3 (operands[1])))
- || (memory_operand (operands[1], mode)
- && even_register_operand (operands[0], mode
-{
- emit_move_insn (operands[0], operands[1]);
- return;
-}
-
- if (TARGET_PLUS_QMACW
- && even_register_operand (operands[0], mode)
- && even_register_operand (operands[1], mode))
-{
- emit_move_insn (operands[0], operands[1]);
- return;
-}
-
if (TARGET_PLUS_QMACW
&& GET_CODE (operands[1]) == CONST_VECTOR)
{
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index de61b2b790f..6f13b3a01d8 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -1330,47 +1330,20 @@ (define_insn_and_split "*movdi_insn"
"register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode)
|| (satisfies_constraint_Cm3 (operands[1])
- && memory_operand (operands[0], DImode))"
- "*
-{
- switch (which_alternative)
-{
-default:
- return \"#\";
-
-case 0:
-if (TARGET_PLUS_QMACW
- && even_register_operand (operands[0], DImode)
- && even_register_operand (operands[1], DImode))
- return \"vadd2%?\\t%0,%1,0\";
-return \"#\";
-
-case 2:
-if (TARGET_LL64
-&& memory_operand (operands[1], DImode)
- && even_register_operand (operands[0], DImode))
- return \"ldd%U1%V1 %0,%1%&\";
-return \"#\";
-
-case 3:
-if (TARGET_LL64
- && memory_operand (operands[0], DImode)
- && (even_register_operand (operands[1], DImode)
- || satisfies_constraint_Cm3 (operands[1])))
- return \"std%U0%V0 %1,%0\";
-return \"#\";
-}
-}"
- "&& reload_completed"
+ && memory_operand (operands[0], DImode))"
+ "@
+ vadd2\\t%0,%1,0
+ #
+ ldd%U1%V1\\t%0,%1
+ std%U0%V0\\t%1,%0"
+
Re: [PATCH] arc: Add --with-fpu support for ARCv2 cpus
Thank you for your input.
I have made an update using grep's ERE. Please let me know if it is ok.
//Claudiu
>From 3f598e0fc9bc88c3f40f3e381c2955ab36e77ce0 Mon Sep 17 00:00:00 2001
From: Claudiu Zissulescu
Date: Wed, 21 Oct 2020 16:11:43 +0300
Subject: [PATCH] arc: Add --with-fpu support for ARCv2 cpus
Support for a compile-time default FPU. The --with-fpu configuration
option is ignored if -mfpu compiler option is specified. The FPU
options are only available for ARCv2 cpus.
gcc/
-mm-dd Claudiu Zissulescu
* config.gcc (arc): Add support for with_cpu option.
* config/arc/arc.h (OPTION_DEFAULT_SPECS): Add fpu.
Signed-off-by: Claudiu Zissulescu
---
gcc/config.gcc | 58 +---
gcc/config/arc/arc.h | 4 +++
2 files changed, 59 insertions(+), 3 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 610422fb29ee..d4445e98e0c9 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4258,18 +4258,70 @@ case "${target}" in
;;
arc*-*-*)
- supported_defaults="cpu"
+ supported_defaults="cpu fpu"
+ new_cpu=hs38_linux
if [ x"$with_cpu" = x ] \
- || grep "^ARC_CPU ($with_cpu," \
+ || grep -E "^ARC_CPU \($with_cpu," \
${srcdir}/config/arc/arc-cpus.def \
> /dev/null; then
# Ok
- true
+ new_cpu=$with_cpu
else
echo "Unknown cpu used in --with-cpu=$with_cpu" 1>&2
exit 1
fi
+
+ # see if --with-fpu matches any of the supported FPUs
+ case "$with_fpu" in
+ "")
+ # OK
+ ;;
+ fpus | fpus_div | fpus_fma | fpus_all)
+ # OK if em or hs
+ if grep -E "^ARC_CPU \($new_cpu,[[:space:]]+[emhs]+," \
+ ${srcdir}/config/arc/arc-cpus.def \
+ > /dev/null; then
+ # OK
+ true
+ else
+ echo "Unknown floating point type used in "\
+ "--with-fpu=$with_fpu for cpu $new_cpu" 1>&2
+ exit 1
+ fi
+ ;;
+ fpuda | fpuda_div | fpuda_fma | fpuda_all)
+ # OK only em
+ if grep -E "^ARC_CPU \($new_cpu,[[:space:]]+em," \
+ ${srcdir}/config/arc/arc-cpus.def \
+ > /dev/null; then
+ # OK
+ true
+ else
+ echo "Unknown floating point type used in "\
+ "--with-fpu=$with_fpu for cpu $new_cpu" 1>&2
+ exit 1
+ fi
+ ;;
+ fpud | fpud_div | fpud_fma | fpud_all)
+ # OK only hs
+ if grep -E "^ARC_CPU \($new_cpu,[[:space:]]+hs," \
+ ${srcdir}/config/arc/arc-cpus.def \
+ > /dev/null; then
+ # OK
+ true
+ else
+ echo "Unknown floating point type used in"\
+ "--with-fpu=$with_fpu for cpu $new_cpu" 1>&2
+ exit 1
+ fi
+ ;;
+ *)
+ echo "Unknown floating point type used in "\
+ "--with-fpu=$with_fpu" 1>&2
+ exit 1
+ ;;
+ esac
;;
csky-*-*)
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 722bb10b8813..b9c4ba0398e5 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -100,7 +100,11 @@ extern const char *arc_cpu_to_as (int argc, const char **argv);
"%:cpu_to_as(%{mcpu=*:%*}) %{mspfp*} %{mdpfp*} " \
"%{mfpu=fpuda*:-mfpuda} %{mcode-density}"
+/* Support for a compile-time default CPU and FPU. The rules are:
+ --with-cpu is ignored if -mcpu, mARC*, marc*, mA7, mA6 are specified.
+ --with-fpu is ignored if -mfpu is specified. */
#define OPTION_DEFAULT_SPECS \
+ {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \
{"cpu", "%{!mcpu=*:%{!mARC*:%{!marc*:%{!mA7:%{!mA6:-mcpu=%(VALUE)}" }
#ifndef DRIVER_ENDIAN_SELF_SPECS
--
2.31.1
[PATCH] arc: Add --with-fpu support for ARCv2 cpus
Hi Jeff,
I would like to add spport for selecting the ARCv2 FPU extension at
configuration-time.
The --with-fpu configuration option is ignored when -mfpu compiler
option is specified.
My concern is using `grep -P` when configuring. Is that ok?
Thanks,
Claudiu
gcc/
-mm-dd Claudiu Zissulescu
* config.gcc (arc): Add support for with_cpu option.
* config/arc/arc.h (OPTION_DEFAULT_SPECS): Add fpu.
Signed-off-by: Claudiu Zissulescu
---
gcc/config.gcc | 56 ++--
gcc/config/arc/arc.h | 4
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 610422fb29ee..f46b5e79af69 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -4258,18 +4258,70 @@ case "${target}" in
;;
arc*-*-*)
- supported_defaults="cpu"
+ supported_defaults="cpu fpu"
+ new_cpu=hs38_linux
if [ x"$with_cpu" = x ] \
|| grep "^ARC_CPU ($with_cpu," \
${srcdir}/config/arc/arc-cpus.def \
> /dev/null; then
# Ok
-true
+new_cpu=$with_cpu
else
echo "Unknown cpu used in --with-cpu=$with_cpu" 1>&2
exit 1
fi
+
+ # see if --with-fpu matches any of the supported FPUs
+ case "$with_fpu" in
+ "")
+ # OK
+ ;;
+ fpus | fpus_div | fpus_fma | fpus_all)
+ # OK if em or hs
+ if grep -P "^ARC_CPU \($new_cpu,\s+[emhs]+," \
+ ${srcdir}/config/arc/arc-cpus.def \
+ > /dev/null; then
+ # OK
+ true
+ else
+echo "Unknown floating point type used in "\
+"--with-fpu=$with_fpu for cpu $new_cpu" 1>&2
+exit 1
+ fi
+ ;;
+ fpuda | fpuda_div | fpuda_fma | fpuda_all)
+ # OK only em
+ if grep -P "^ARC_CPU \($new_cpu,\s+em," \
+ ${srcdir}/config/arc/arc-cpus.def \
+ > /dev/null; then
+ # OK
+ true
+ else
+echo "Unknown floating point type used in "\
+ "--with-fpu=$with_fpu for cpu $new_cpu" 1>&2
+exit 1
+ fi
+ ;;
+ fpud | fpud_div | fpud_fma | fpud_all)
+ # OK only hs
+ if grep -P "^ARC_CPU \($new_cpu,\s+hs," \
+ ${srcdir}/config/arc/arc-cpus.def \
+ > /dev/null; then
+ # OK
+ true
+ else
+echo "Unknown floating point type used in"\
+ "--with-fpu=$with_fpu for cpu $new_cpu" 1>&2
+exit 1
+ fi
+ ;;
+ *)
+ echo "Unknown floating point type used in "\
+"--with-fpu=$with_fpu" 1>&2
+ exit 1
+ ;;
+ esac
;;
csky-*-*)
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 722bb10b8813..b9c4ba0398e5 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -100,7 +100,11 @@ extern const char *arc_cpu_to_as (int argc, const char
**argv);
"%:cpu_to_as(%{mcpu=*:%*}) %{mspfp*} %{mdpfp*} " \
"%{mfpu=fpuda*:-mfpuda} %{mcode-density}"
+/* Support for a compile-time default CPU and FPU. The rules are:
+ --with-cpu is ignored if -mcpu, mARC*, marc*, mA7, mA6 are specified.
+ --with-fpu is ignored if -mfpu is specified. */
#define OPTION_DEFAULT_SPECS \
+ {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"},
\
{"cpu", "%{!mcpu=*:%{!mARC*:%{!marc*:%{!mA7:%{!mA6:-mcpu=%(VALUE)}" }
#ifndef DRIVER_ENDIAN_SELF_SPECS
--
2.31.1
[committed] arc: Don't allow millicode thunks with reduced register set CPUs.
The millicode thunks are not reduced register set safe. Disable them for CPUs having this option on. gcc/ 2021-06-04 Claudiu Zissulescu * config/arc/arc.c (arc_override_options): Disable millicode thunks when RF16 is on. Signed-off-by: Claudiu Zissulescu --- gcc/config/arc/arc.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index b77d0566386..0d34c964963 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -1451,8 +1451,10 @@ arc_override_options (void) if (TARGET_ARC700 && (arc_tune != ARC_TUNE_ARC7XX)) flag_delayed_branch = 0; - /* Millicode thunks doesn't work with long calls. */ - if (TARGET_LONG_CALLS_SET) + /* Millicode thunks doesn't work for long calls. */ + if (TARGET_LONG_CALLS_SET + /* neither for RF16. */ + || TARGET_RF16) target_flags &= ~MASK_MILLICODE_THUNK_SET; /* Set unaligned to all HS cpus. */ -- 2.31.1
[committed] arc: Remove obsolete options
This is a respin of an older series of three patches which I have
merged into one. The new (committed) patch is keeping the obsolete
options int .opt file marking them accrodingly for backwards
compatibility.
Remove the following obsolete options:
- munalign-prob-threshold
- malign-call
- mmixed-code
The ARC's options are marked as obsolete and ignored for backwards
compatibility.
gcc/
2021-06-03 Claudiu Zissulescu
* common/config/arc/arc-common.c (arc_option_optimization_table):
Remove malign-call.
* config/arc/arc.c (arc_unalign_branch_p): Remove unused function.
* config/arc/arc.h (TARGET_MIXED_CODE): Remove macro.
(INDEX_REG_CLASS): Only refer to GENERAL_REGS.
* config/arc/arc.md (abssi2_mixed): Remove pattern.
* config/arc/arc.opt (munalign-prob-threshold): Mark it obsolete.
(malign-call): Likewise.
(mmixed-code): Likewise.
* doc/invoke.texi (ARC): Update doc.
Signed-off-by: Claudiu Zissulescu
---
gcc/common/config/arc/arc-common.c | 1 -
gcc/config/arc/arc.c | 23 ---
gcc/config/arc/arc.h | 4 +---
gcc/config/arc/arc.md | 8
gcc/config/arc/arc.opt | 18 ++
gcc/doc/invoke.texi| 13 +++--
6 files changed, 10 insertions(+), 57 deletions(-)
diff --git a/gcc/common/config/arc/arc-common.c
b/gcc/common/config/arc/arc-common.c
index 86674dd3de7..6a119029616 100644
--- a/gcc/common/config/arc/arc-common.c
+++ b/gcc/common/config/arc/arc-common.c
@@ -62,7 +62,6 @@ static const struct default_options
arc_option_optimization_table[] =
{ OPT_LEVELS_SIZE, OPT_fif_conversion, NULL, 0 },
{ OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
{ OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_msize_level_, NULL, 0 },
-{ OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_malign_call, NULL, 1 },
{ OPT_LEVELS_NONE, 0, NULL, 0 }
};
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 9153f0529ab..b77d0566386 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -9868,29 +9868,6 @@ gen_acc2 (void)
return gen_rtx_REG (SImode, TARGET_BIG_ENDIAN ? 57: 56);
}
-/* FIXME: a parameter should be added, and code added to final.c,
- to reproduce this functionality in shorten_branches. */
-#if 0
-/* Return nonzero iff BRANCH should be unaligned if possible by upsizing
- a previous instruction. */
-int
-arc_unalign_branch_p (rtx branch)
-{
- rtx note;
-
- if (!TARGET_UNALIGN_BRANCH)
-return 0;
- /* Do not do this if we have a filled delay slot. */
- if (get_attr_delay_slot_filled (branch) == DELAY_SLOT_FILLED_YES
- && !NEXT_INSN (branch)->deleted ())
-return 0;
- note = find_reg_note (branch, REG_BR_PROB, 0);
- return (!note
- || (arc_unalign_prob_threshold && !br_prob_note_reliable_p (note))
- || INTVAL (XEXP (note, 0)) < arc_unalign_prob_threshold);
-}
-#endif
-
/* When estimating sizes during arc_reorg, when optimizing for speed, there
are three reasons why we need to consider branches to be length 6:
- annull-false delay slot insns are implemented using conditional execution,
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 252241a858c..0224ae65074 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -115,8 +115,6 @@ extern const char *arc_cpu_to_as (int argc, const char
**argv);
/* Run-time compilation parameters selecting different hardware subsets. */
-#define TARGET_MIXED_CODE (TARGET_MIXED_CODE_SET)
-
#define TARGET_SPFP (TARGET_SPFP_FAST_SET || TARGET_SPFP_COMPACT_SET)
#define TARGET_DPFP (TARGET_DPFP_FAST_SET || TARGET_DPFP_COMPACT_SET \
|| TARGET_FP_DP_AX)
@@ -571,7 +569,7 @@ extern enum reg_class arc_regno_reg_class[];
a scale factor or added to another register (as well as added to a
displacement). */
-#define INDEX_REG_CLASS (TARGET_MIXED_CODE ? ARCOMPACT16_REGS : GENERAL_REGS)
+#define INDEX_REG_CLASS GENERAL_REGS
/* The class value for valid base registers. A base register is one used in
an address which is the register value plus a displacement. */
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index a67bb581003..de61b2b790f 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -2011,14 +2011,6 @@ (define_expand "extendhisi2"
;; Absolute instructions
-(define_insn "*abssi2_mixed"
- [(set (match_operand:SI 0 "compact_register_operand" "=q")
- (abs:SI (match_operand:SI 1 "compact_register_operand" "q")))]
- "TARGET_MIXED_CODE"
- "abs%? %0,%1%&"
- [(set_attr "type" "two_cycle_core")
- (set_attr "iscompact" "true")])
-
(define_insn "abssi2"
[(set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,w,w")
(abs:SI (match_operand:SI 1
Re: [PATCH] ARC: gcc driver default to hs38_linux
Right, we can consider this cpu switch missing in gcc11. Best, Claudiu From: Vineet Gupta Sent: Wednesday, June 2, 2021 8:36 PM To: Claudiu Zissulescu ; gcc-patches@gcc.gnu.org Cc: linux-snps-...@lists.infradead.org Subject: Re: [PATCH] ARC: gcc driver default to hs38_linux On 6/2/21 1:38 AM, Claudiu Zissulescu wrote: > Approved. Thx for the super quick action on this Claudiu. Can this be slated for backports too as it causes issues when building toolchains for modern cores without explicit defaults. -Vineet > > //Claudiu > > *From:* Vineet Gupta > *Sent:* Tuesday, June 1, 2021 10:42 PM > *To:* gcc-patches@gcc.gnu.org > *Cc:* Claudiu Zissulescu ; > linux-snps-...@lists.infradead.org > ; Vineet Gupta > *Subject:* [PATCH] ARC: gcc driver default to hs38_linux > arc700 is legacy and there's no active development for it, so switch to > latest hs38_linux as default > > Signed-off-by: Vineet Gupta > --- > gcc/config/arc/arc.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h > index bd1fe0abd7af..252241a858c9 100644 > --- a/gcc/config/arc/arc.h > +++ b/gcc/config/arc/arc.h > @@ -34,7 +34,7 @@ along with GCC; see the file COPYING3. If not see > #define SYMBOL_FLAG_CMEM(SYMBOL_FLAG_MACH_DEP << 3) > > #ifndef TARGET_CPU_DEFAULT > -#define TARGET_CPU_DEFAULT PROCESSOR_arc700 > +#define TARGET_CPU_DEFAULT PROCESSOR_hs38_linux > #endif > > /* Check if this symbol has a long_call attribute in its declaration */ > -- > 2.25.1 >
Re: [PATCH] ARC: gcc driver default to hs38_linux
Approved. //Claudiu From: Vineet Gupta Sent: Tuesday, June 1, 2021 10:42 PM To: gcc-patches@gcc.gnu.org Cc: Claudiu Zissulescu ; linux-snps-...@lists.infradead.org ; Vineet Gupta Subject: [PATCH] ARC: gcc driver default to hs38_linux arc700 is legacy and there's no active development for it, so switch to latest hs38_linux as default Signed-off-by: Vineet Gupta --- gcc/config/arc/arc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index bd1fe0abd7af..252241a858c9 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -34,7 +34,7 @@ along with GCC; see the file COPYING3. If not see #define SYMBOL_FLAG_CMEM(SYMBOL_FLAG_MACH_DEP << 3) #ifndef TARGET_CPU_DEFAULT -#define TARGET_CPU_DEFAULT PROCESSOR_arc700 +#define TARGET_CPU_DEFAULT PROCESSOR_hs38_linux #endif /* Check if this symbol has a long_call attribute in its declaration */ -- 2.25.1
Re: [PATCH 02/11 v2] arc: Remove define_insn_and_split *bbit_di
Looks good :) You can go ahead and commit it. Thank you for your contribution, Claudiu From: Kewen.Lin Sent: Wednesday, June 2, 2021 10:43 AM To: Claudiu Zissulescu Cc: g...@amylaar.uk ; andrew.burg...@embecosm.com ; gcc-patches@gcc.gnu.org Subject: [PATCH 02/11 v2] arc: Remove define_insn_and_split *bbit_di Hi Claudiu, on 2021/6/2 下午3:12, Claudiu Zissulescu wrote: > Hi Kewen, > > Maybe it is best just to remove the pattern entirely, I couldn't exercise it > myself. I was secretly hopping someone could do it. > Please can you submit a patch which removes it if it is not too much trouble? > The patch v2 has been attached which removes define_insn_and_split "*bbit_di" as you suggested. Does it look good to you? BR, Kewen - gcc/ChangeLog: * config/arc/arc.md (*bbit_di): Remove.
Re: [PATCH 02/11] arc: Update unexpected empty split condition
Hi Kewen, Maybe it is best just to remove the pattern entirely, I couldn't exercise it myself. I was secretly hopping someone could do it. Please can you submit a patch which removes it if it is not too much trouble? Thanks, Claudiu From: Kewen.Lin Sent: Wednesday, June 2, 2021 10:05 AM To: Claudiu Zissulescu ; gcc-patches@gcc.gnu.org Cc: g...@amylaar.uk ; andrew.burg...@embecosm.com Subject: Re: [PATCH 02/11] arc: Update unexpected empty split condition Hi Claudiu, on 2021/6/2 下午2:52, Claudiu Zissulescu wrote: > Hi, > > Indeed, the split condition needs to be populated. However, I doubt that the > pattern in question is used by the compiler. Do you have an example where it > is exercised? > Thanks for the reply! Sorry that I don't have an example, the gensupport change will emit an error message for this pattern in build stage even without actual running. BR, Kewen > Thanks, > Claudiu > -- > *From:* Kewen Lin > *Sent:* Wednesday, June 2, 2021 8:04 AM > *To:* gcc-patches@gcc.gnu.org > *Cc:* Kewen Lin ; g...@amylaar.uk ; > Claudiu Zissulescu ; andrew.burg...@embecosm.com > > *Subject:* [PATCH 02/11] arc: Update unexpected empty split condition > > gcc/ChangeLog: > > * config/arc/arc.md (*bbit_di): Fix empty split condition. > --- > gcc/config/arc/arc.md | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index 7a52551eef5..a03840c4c36 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -5020,7 +5020,7 @@ (define_insn_and_split "*bbit_di" > (clobber (reg:CC_ZN CC_REG))] >"!CROSSING_JUMP_P (insn)" >"#" > - "" > + "&& 1" >[(parallel > [(set (pc) (if_then_else (match_dup 3) (label_ref (match_dup 0)) (pc))) >(clobber (reg:CC_ZN CC_REG))])] > -- > 2.17.1
Re: [PATCH 02/11] arc: Update unexpected empty split condition
Hi, Indeed, the split condition needs to be populated. However, I doubt that the pattern in question is used by the compiler. Do you have an example where it is exercised? Thanks, Claudiu From: Kewen Lin Sent: Wednesday, June 2, 2021 8:04 AM To: gcc-patches@gcc.gnu.org Cc: Kewen Lin ; g...@amylaar.uk ; Claudiu Zissulescu ; andrew.burg...@embecosm.com Subject: [PATCH 02/11] arc: Update unexpected empty split condition gcc/ChangeLog: * config/arc/arc.md (*bbit_di): Fix empty split condition. --- gcc/config/arc/arc.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 7a52551eef5..a03840c4c36 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -5020,7 +5020,7 @@ (define_insn_and_split "*bbit_di" (clobber (reg:CC_ZN CC_REG))] "!CROSSING_JUMP_P (insn)" "#" - "" + "&& 1" [(parallel [(set (pc) (if_then_else (match_dup 3) (label_ref (match_dup 0)) (pc))) (clobber (reg:CC_ZN CC_REG))])] -- 2.17.1
[COMMITTED] arc: Fix typo in negv2si2 pattern
gcc/ 2021-05-18 Claudiu Zissulescu * config/arc/simdext.md (negv2si2): Remove round bracket. Signed-off-by: Claudiu Zissulescu --- gcc/config/arc/simdext.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md index c7ca306a081..dd63f93b3fd 100644 --- a/gcc/config/arc/simdext.md +++ b/gcc/config/arc/simdext.md @@ -2056,7 +2056,7 @@ (define_insn "*neg2" [(set (match_operand:VCT 0 "register_operand" "=r") (neg:VCT (match_operand:VCT 1 "register_operand" "r")))] "TARGET_PLUS_DMPY" - "vsub\\t%0,0,%1" + "vsub\\t%0,0,%1" [(set_attr "length" "8") (set_attr "type" "multi")]) -- 2.31.1
[PATCH 2/3] [committed] arc: Cleanup simdext.md file
Textual cleanup of the simdext.md file. Format the output assembly instructions. gcc/ 2021-05-10 Claudiu Zissulescu * config/arc/simdext.md: Format and cleanup file. Signed-off-by: Claudiu Zissulescu --- gcc/config/arc/simdext.md | 730 +- 1 file changed, 400 insertions(+), 330 deletions(-) diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md index d142aacd7dc..41c42690633 100644 --- a/gcc/config/arc/simdext.md +++ b/gcc/config/arc/simdext.md @@ -174,7 +174,7 @@ (define_insn "vld128_insn" (parallel [(match_operand:SI 2 "immediate_operand" "L")]))) (match_operand:SI 3 "immediate_operand" "P"] "TARGET_SIMD_SET" - "vld128 %0, [i%2, %3]" + "vld128\\t%0,[i%2,%3]" [(set_attr "type" "simd_vload128") (set_attr "length" "4") (set_attr "cond" "nocond")] @@ -186,7 +186,7 @@ (define_insn "vst128_insn" (match_operand:SI 2 "immediate_operand" "P"))) (match_operand:V8HI 3 "vector_register_operand" "=v"))] "TARGET_SIMD_SET" - "vst128 %3, [i%1, %2]" + "vst128\\t%3,[i%1,%2]" [(set_attr "type" "simd_vstore") (set_attr "length" "4") (set_attr "cond" "nocond")] @@ -204,7 +204,7 @@ (define_insn "vst64_insn" (match_operand:V8HI 3 "vector_register_operand" "=v") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])))] "TARGET_SIMD_SET" - "vst64 %3, [i%1, %2]" + "vst64\\t%3,[i%1,%2]" [(set_attr "type" "simd_vstore") (set_attr "length" "4") (set_attr "cond" "nocond")] @@ -215,9 +215,9 @@ (define_insn "movv8hi_insn" (match_operand:V8HI 1 "vector_register_or_memory_operand" "m,v,v"))] "TARGET_SIMD_SET && !(GET_CODE (operands[0]) == MEM && GET_CODE(operands[1]) == MEM)" "@ -vld128r %0, %1 -vst128r %1, %0 -vmvzw %0,%1,0x" +vld128r\\t%0,%1 +vst128r\\t%1,%0 +vmvzw\\t%0,%1,0x" [(set_attr "type" "simd_vload128,simd_vstore,simd_vmove_else_zero") (set_attr "length" "8,8,4") (set_attr "cond" "nocond, nocond, nocond")]) @@ -227,55 +227,21 @@ (define_insn "movti_insn" (match_operand:TI 1 "vector_register_or_memory_operand" "m,v,v"))] "" "@ -vld128r %0, %1 -vst128r %1, %0 -vmvzw %0,%1,0x" +vld128r\\t%0,%1 +vst128r\\t%1,%0 +vmvzw\\t%0,%1,0x" [(set_attr "type" "simd_vload128,simd_vstore,simd_vmove_else_zero") (set_attr "length" "8,8,4") (set_attr "cond" "nocond, nocond, nocond")]) -;; (define_insn "*movv8hi_insn_rr" -;; [(set (match_operand:V8HI 0 "vector_register_operand" "=v") -;; (match_operand:V8HI 1 "vector_register_operand" "v"))] -;; "" -;; "mov reg,reg" -;; [(set_attr "length" "8") -;; (set_attr "type" "move")]) - -;; (define_insn "*movv8_out" -;; [(set (match_operand:V8HI 0 "memory_operand" "=m") -;; (match_operand:V8HI 1 "vector_register_operand" "v"))] -;; "" -;; "mov out" -;; [(set_attr "length" "8") -;; (set_attr "type" "move")]) - - -;; (define_insn "addv8hi3" -;; [(set (match_operand:V8HI 0 "vector_register_operand" "=v") -;; (plus:V8HI (match_operand:V8HI 1 "vector_register_operand" "v") -;;(match_operand:V8HI 2 "vector_register_operand" "v")))] -;; "TARGET_SIMD_SET" -;; "vaddw %0, %1, %2" -;; [(set_attr "length" "8") -;;(set_attr "cond" "nocond")]) - -;; (define_insn "vaddw_insn" -;; [(set (match_operand:V8HI 0 "vector_register_operand" "=v") -;; (unspec [(match_operand:V8HI 1 "vector_register_operand" "v") -;; (match_operand:V8HI 2 "vector_register_operand" "v")] UNSPEC_ARC_SIMD_VADDW))] -;; "TARGET_SIMD_SET" -;; "vaddw %0, %1, %2" -;; [(set_attr "length" "8") -;;(set_attr "cond" "nocond")]) - ;; V V V Insns (define_insn "vaddaw_insn&
[PATCH 3/3] [committed] arc: Improve vector support for ARCv2.
Add vector negate, reduc_plus_scal, vec_duplicate, vector
min/max/mult/div patterns. Besides vector negate and reduction
patterns, all the others are emulated using scalar instructions. The
reason is taking advantage of the double load/store instructions as
well as enabling the autovectorizer to further analize a loop.
gcc/
2021-05-10 Claudiu Zissulescu
* config/arc/arc.md (UNSPEC_ARC_DMPYWH): Define.
* config/arc/simdext.md (VCT): Add predicates for iterator
elements.
(EMUVEC): Define.
(voptab): Likewise.
(vec_widen_mult_hi_v4hi): Change pattern predicate.
(v2si3): New patterns.
(neg): Likewise.
(reduc_plus_scal_v4hi): Likewise.
(reduc_plus_scal_v2si): Likewise.
(vec_duplicatev2si): Likewise.
(vec_duplicatev4hi): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.md | 1 +
gcc/config/arc/simdext.md | 112 +-
2 files changed, 111 insertions(+), 2 deletions(-)
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index f3efe65ca2f..b6f2d8e28be 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -128,6 +128,7 @@ (define_c_enum "unspec" [
UNSPEC_ARC_DMACHU
UNSPEC_ARC_DMACWH
UNSPEC_ARC_DMACWHU
+ UNSPEC_ARC_DMPYWH
UNSPEC_ARC_QMACH
UNSPEC_ARC_QMACHU
UNSPEC_ARC_QMPYH
diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
index 41c42690633..c7ca306a081 100644
--- a/gcc/config/arc/simdext.md
+++ b/gcc/config/arc/simdext.md
@@ -1395,9 +1395,20 @@ (define_mode_attr V_addsub [(V2HI "HI") (V2SI "SI")])
(define_mode_attr V_addsub_suffix [(V2HI "2h") (V2SI "")])
;;all vectors
-(define_mode_iterator VCT [V2HI V4HI V2SI])
+(define_mode_iterator VCT [(V2HI "TARGET_PLUS_DMPY")
+ (V4HI "TARGET_PLUS_QMACW")
+ (V2SI "TARGET_PLUS_QMACW")])
(define_mode_attr V_suffix [(V2HI "2h") (V4HI "4h") (V2SI "2")])
+(define_code_iterator EMUVEC [(mult "TARGET_MPYW")
+ (div "TARGET_DIVREM")
+ smax smin])
+
+(define_code_attr voptab [(mult "mul")
+ (div "div")
+ (smin "smin")
+ (smax "smax")])
+
;; Widening operations.
(define_code_iterator SE [sign_extend zero_extend])
(define_code_attr V_US [(sign_extend "s") (zero_extend "u")])
@@ -1805,7 +1816,7 @@ (define_expand "vec_widen_mult_hi_v4hi"
(SE:V2SI (vec_select:V2HI
(match_operand:V4HI 2 "even_register_operand")
(parallel [(const_int 2) (const_int 3)])]
- "TARGET_PLUS_MACD"
+ "TARGET_PLUS_QMACW"
{
emit_insn (gen_arc_vec_mult_hi_v4hi (operands[0],
operands[1],
@@ -2011,3 +2022,100 @@ (define_insn "qmpyhu"
(set_attr "type" "multi")
(set_attr "predicable" "yes,no")
(set_attr "cond" "canuse,nocond")])
+
+;; Emulated vector instructions.
+(define_insn_and_split "v2si3"
+ [(set (match_operand:V2SI 0 "register_operand" "=r")
+ (EMUVEC:V2SI (match_operand:V2SI 1 "register_operand" "r")
+(match_operand:V2SI 2 "nonmemory_operand" "ri")))]
+ ""
+ "#"
+ "reload_completed"
+ [(const_int 0)]
+ {
+ rtx high_dest = gen_highpart (SImode, operands[0]);
+ rtx low_dest = gen_lowpart (SImode, operands[0]);
+ rtx high_op1 = gen_highpart (SImode, operands[1]);
+ rtx low_op1 = gen_lowpart (SImode, operands[1]);
+ rtx high_op2 = gen_highpart (SImode, operands[2]);
+ rtx low_op2 = gen_lowpart (SImode, operands[2]);
+ emit_insn (gen_si3 (low_dest, low_op1, low_op2));
+ emit_insn (gen_si3 (high_dest, high_op1, high_op2));
+ DONE;
+ }
+ [(set_attr "length" "12")
+ (set_attr "type" "multi")])
+
+(define_expand "neg2"
+ [(set (match_operand:VCT 0 "register_operand")
+ (neg:VCT (match_operand:VCT 1 "register_operand")))]
+ "TARGET_PLUS_DMPY"
+ "")
+
+(define_insn "*neg2"
+ [(set (match_operand:VCT 0 "register_operand" "=r")
+ (neg:VCT (match_operand:VCT 1 "register_operand" "r")))]
+ "TARGET_PLUS_DMPY"
+ "vsub\\t%0,0,%1"
+ [(set_attr "length" "8")
+ (set_attr "type" "multi")])
+
+(define_insn "reduc_plus_scal_v4hi"
+ [(set (match_operand:HI 0 "even_register_operand" "=r")
+ (
[PATCH 1/3] [committed] arc: Disable movmisalign patterns when aligned access is required
Disable movmisalign patterns when aligned access is required.
gcc/
2021-05-10 Claudiu Zissulescu
* config/arc/simdext.md (movmisalignv2hi): Allow misaligned access
only when munaligned-access option is on.
(movmisalign): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/simdext.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
index f0900757452..d142aacd7dc 100644
--- a/gcc/config/arc/simdext.md
+++ b/gcc/config/arc/simdext.md
@@ -1382,7 +1382,7 @@ (define_insn_and_split "*movv2hi_insn"
(define_expand "movmisalignv2hi"
[(set (match_operand:V2HI 0 "general_operand" "")
(match_operand:V2HI 1 "general_operand" ""))]
- ""
+ "unaligned_access"
"{
if (prepare_move_operands (operands, V2HImode))
DONE;
@@ -1441,7 +1441,7 @@ (define_insn_and_split "*mov_insn"
(define_expand "movmisalign"
[(set (match_operand:VWH 0 "general_operand" "")
(match_operand:VWH 1 "general_operand" ""))]
- ""
+ "unaligned_access"
"{
if (prepare_move_operands (operands, mode))
DONE;
--
2.30.2
[PATCH 4/4] [committed] arc: Fix compilation warnings.
gcc/
2021-05-10 Claudiu Zissulescu
* common/config/arc/arc-common.c (arc_handle_option): Remove dot
from string.
* config/arc/arc.c (arc_reorg): Remove underscore from string.
Signed-off-by: Claudiu Zissulescu
---
gcc/common/config/arc/arc-common.c | 2 +-
gcc/config/arc/arc.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/common/config/arc/arc-common.c
b/gcc/common/config/arc/arc-common.c
index d5229ae7146..86674dd3de7 100644
--- a/gcc/common/config/arc/arc-common.c
+++ b/gcc/common/config/arc/arc-common.c
@@ -84,7 +84,7 @@ arc_handle_option (struct gcc_options *opts,
our caller, so comparing arc_cpu with PROCESSOR_NONE is pointless. */
if (mcpu_seen != PROCESSOR_NONE && mcpu_seen != value)
- warning_at (loc, 0, "multiple %<-mcpu=%> options specified.");
+ warning_at (loc, 0, "multiple %<-mcpu=%> options specified");
mcpu_seen = value;
break;
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 3201c3fefd7..ec7328edb5a 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -8433,7 +8433,7 @@ arc_reorg (void)
if (!INSN_ADDRESSES_SET_P())
fatal_error (input_location,
- "insn addresses not set after shorten_branches");
+ "insn addresses not set after shorten branches");
for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
{
--
2.30.2
[PATCH 3/4] [committed] arc: Update ctz/clz patterns
ARCv2 ISA introduces special clz/ctz instructions. This patch is
adding support for them when available.
Corner case:
movr0,0x0 : (w0) r0 <= 0x *
ffsr1,r0 : (w0) r1 <= 0x001f *
flsr2,r0 : (w0) r2 <= 0x *
gcc/
2021-05-10 Claudiu Zissulescu
* gcc/config/arc/arc.h (CLZ_DEFINED_VALUE_AT_ZERO): Define.
(CTZ_DEFINED_VALUE_AT_ZERO): Likewise.
* gcc/config/arc/arc.md (clrsbsi2): Cleanup pattern.
(norm_f): Likewise.
(ffs): Likewise.
(ffs_f): Likewise.
(clzsi2): Use fls instruction when available.
(arc_clzsi2): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.h | 6 +
gcc/config/arc/arc.md | 53 ---
2 files changed, 36 insertions(+), 23 deletions(-)
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index b7b34734f24..bd1fe0abd7a 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -1445,6 +1445,12 @@ do { \
*/
#define SHIFT_COUNT_TRUNCATED 1
+/* Defines if the CLZ result is undefined or has a useful value. */
+#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 31, 2)
+
+/* Defines if the CTZ result is undefined or has a useful value. */
+#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 31, 2)
+
/* We assume that the store-condition-codes instructions store 0 for false
and some other value for true. This is the value stored for true. */
#define STORE_FLAG_VALUE 1
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 7a52551eef5..f3efe65ca2f 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -4396,24 +4396,20 @@ (define_peephole2
;; Instructions generated through builtins
(define_insn "clrsbsi2"
- [(set (match_operand:SI 0 "dest_reg_operand" "=w,w")
- (clrsb:SI (match_operand:SI 1 "general_operand" "cL,Cal")))]
+ [(set (match_operand:SI 0 "dest_reg_operand" "=r,r")
+ (clrsb:SI (match_operand:SI 1 "general_operand" "rL,Cal")))]
"TARGET_NORM"
- "@
- norm \t%0, %1
- norm \t%0, %1"
+ "norm\\t%0,%1"
[(set_attr "length" "4,8")
(set_attr "type" "two_cycle_core,two_cycle_core")])
(define_insn "norm_f"
- [(set (match_operand:SI 0 "dest_reg_operand" "=w,w")
- (clrsb:SI (match_operand:SI 1 "general_operand" "cL,Cal")))
+ [(set (match_operand:SI 0 "dest_reg_operand" "=r,r")
+ (clrsb:SI (match_operand:SI 1 "general_operand" "rL,Cal")))
(set (reg:CC_ZN CC_REG)
(compare:CC_ZN (match_dup 1) (const_int 0)))]
"TARGET_NORM"
- "@
- norm.f\t%0, %1
- norm.f\t%0, %1"
+ "norm.f\\t%0,%1"
[(set_attr "length" "4,8")
(set_attr "type" "two_cycle_core,two_cycle_core")])
@@ -4443,7 +4439,17 @@ (define_expand "clzsi2"
(clz:SI (match_operand:SI 1 "register_operand" "")))
(clobber (match_dup 2))])]
"TARGET_NORM"
- "operands[2] = gen_rtx_REG (CC_ZNmode, CC_REG);")
+ "
+ if (TARGET_V2)
+{
+ /* ARCv2's FLS is a bit more optimal than using norm. */
+ rtx tmp = gen_reg_rtx (SImode);
+ emit_insn (gen_fls (tmp, operands[1]));
+ emit_insn (gen_subsi3 (operands[0], GEN_INT (31), tmp));
+ DONE;
+}
+ operands[2] = gen_rtx_REG (CC_ZNmode, CC_REG);
+ ")
(define_insn_and_split "*arc_clzsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
@@ -4475,8 +4481,13 @@ (define_expand "ctzsi2"
(match_operand:SI 1 "register_operand" "")]
"TARGET_NORM"
"
- emit_insn (gen_arc_ctzsi2 (operands[0], operands[1]));
- DONE;
+ if (TARGET_V2)
+{
+ emit_insn (gen_ffs (operands[0], operands[1]));
+ DONE;
+}
+ emit_insn (gen_arc_ctzsi2 (operands[0], operands[1]));
+ DONE;
")
(define_insn_and_split "arc_ctzsi2"
@@ -5575,26 +5586,22 @@ (define_insn "clri"
(set_attr "type" "misc")])
(define_insn "ffs"
- [(set (match_operand:SI 0 "dest_reg_operand" "=w,w")
- (unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")]
+ [(set (match_operand:SI 0 "dest_reg_operand" "=r,r")
+ (unspec:SI [(match_operand:SI 1 "general_operand" "rL,Cal")]
UNSPEC_ARC_FFS))]
"TARGET_NORM && TARGET_V2"
- "@
- ffs \t%0, %1
- ffs \t%0, %1"
+ "ffs\\t%0,%1"
[(set_attr "length" "4,8")
(set_attr "type" "two_cycle_core,two_cycle_core")])
(define_insn "ffs_f"
- [(set (match_operand:SI 0 "dest_reg_operand" "=w,w")
- (unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")]
+ [(set (match_operand:SI 0 "dest_reg_operand" "=r,r")
+ (unspec:SI [(match_operand:SI 1 "general_operand" "rL,Cal")]
UNSPEC_ARC_FFS))
(set (reg:CC_ZN CC_REG)
(compare:CC_ZN (match_dup 1) (const_int 0)))]
"TARGET_NORM && TARGET_V2"
- "@
- ffs.f\t%0, %1
- ffs.f\t%0, %1"
+ "ffs.f\\t%0,%1"
[(set_attr "length" "4,8")
(set_attr "type" "two_cycle_core,two_cycle_core")])
--
2.30.2
[PATCH 2/4] [committed] arc: Add alternative names for gp and fp registers.
Add alternative register name r26 for gp register, and add
alternative register name r27 for fp register.
gcc/
2021-05-10 Claudiu Zissulescu
* config/arc/arc.h (ADDITIONAL_REGISTER_NAMES): Add r26 and r27.
---
gcc/config/arc/arc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index bbb362504cc..b7b34734f24 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -1193,6 +1193,8 @@ extern char rname56[], rname57[], rname58[], rname59[];
#define ADDITIONAL_REGISTER_NAMES \
{ \
+ {"r26",26}, \
+ {"r27",27}, \
{"ilink", 29}, \
{"r29",29}, \
{"r30",30}, \
--
2.30.2
[PATCH 1/4] [committed] arc: Fix documentation __builtin_arc_sr
The arguments of __builtin_arc_sr are swapped in documentation. Fix it.
gcc/
2021-05-10 Claudiu Zissulescu
* doc/extend.texi (__builtin_arc_sr): Swap arguments.
Signed-off-by: Claudiu Zissulescu
---
gcc/doc/extend.texi | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index fd9175d1b3b..826804e6149 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -14709,12 +14709,12 @@ sleep @var{a}
@end example
@end deftypefn
-@deftypefn {Built-in Function} void __builtin_arc_sr (unsigned int
@var{auxr}, unsigned int @var{val})
-The first argument, @var{auxv}, is the address of an auxiliary
-register, the second argument, @var{val}, is a compile time constant
-to be written to the register. Generates:
+@deftypefn {Built-in Function} void __builtin_arc_sr (unsigned int @var{val},
unsigned int @var{auxr})
+The first argument, @var{val}, is a compile time constant to be
+written to the register, the second argument, @var{auxr}, is the
+address of an auxiliary register. Generates:
@example
-sr @var{auxr}, [@var{val}]
+sr @var{val}, [@var{auxr}]
@end example
@end deftypefn
--
2.30.2
[PATCH] arc: Remove orphan function.
Remove unused function.
gcc/
2021-03-09 Claudiu Zissulescu
* config/arc/arc.c (arc_attr_type): Remove function.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.c | 17 -
1 file changed, 17 deletions(-)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 367e4c91c39..3201c3fefd7 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -10285,23 +10285,6 @@ arc_regno_use_in (unsigned int regno, rtx x)
return NULL_RTX;
}
-/* Return the integer value of the "type" attribute for INSN, or -1 if
- INSN can't have attributes. */
-
-static int
-arc_attr_type (rtx_insn *insn)
-{
- if (NONJUMP_INSN_P (insn)
- ? (GET_CODE (PATTERN (insn)) == USE
-|| GET_CODE (PATTERN (insn)) == CLOBBER)
- : JUMP_P (insn)
- ? (GET_CODE (PATTERN (insn)) == ADDR_VEC
-|| GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
- : !CALL_P (insn))
-return -1;
- return get_attr_type (insn);
-}
-
/* Code has a minimum p2 alignment of 1, which we must restore after
an ADDR_DIFF_VEC. */
--
2.26.2
[backport gcc10] arc: Use separate predicated patterns for mpyd(u)
From: Claudiu Zissulescu The compiler can match mpyd.eq r0,r1,r0 as a predicated instruction, which is incorrect. The mpyd(u) instruction takes as input two 32-bit registers, returning into a double 64-bit even-odd register pair. For the predicated case, the ARC instruction decoder expects the destination register to be the same as the first input register. In the big-endian case the result is swaped in the destination register pair, however, the instruction encoding remains the same. Refurbish the mpyd(u) patterns to take into account the above observation. gcc/ 2020-12-11 Claudiu Zissulescu * config/arc/arc.md (mpyd_arcv2hs): New template pattern. (*pmpyd_arcv2hs): Likewise. (*pmpyd_imm_arcv2hs): Likewise. (mpyd_arcv2hs): Moved into above template. (mpyd_imm_arcv2hs): Moved into above template. (mpydu_arcv2hs): Likewise. (mpydu_imm_arcv2hs): Likewise. (su_optab): New optab prefix for sign/zero-extending operations. gcc/testsuite/ 2020-12-11 Claudiu Zissulescu * gcc.target/arc/pmpyd.c: New test. * gcc.target/arc/tmac-1.c: Update. Signed-off-by: Claudiu Zissulescu (cherry picked from commit f7ad4446274831234e5acd3506fd2e01c7594c6a) --- gcc/config/arc/arc.md | 101 +- gcc/testsuite/gcc.target/arc/pmpyd.c | 15 gcc/testsuite/gcc.target/arc/tmac-1.c | 2 +- 3 files changed, 67 insertions(+), 51 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arc/pmpyd.c diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 398034d361e..a79db6da89e 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -871,6 +871,8 @@ (define_mode_attr SQH_postfix [(QI "b") (HI "%_")]) (define_code_iterator SEZ [sign_extend zero_extend]) (define_code_attr SEZ_prefix [(sign_extend "sex") (zero_extend "ext")]) +; Optab prefix for sign/zero-extending operations +(define_code_attr su_optab [(sign_extend "") (zero_extend "u")]) (define_insn "*xt_cmp0_noout" [(set (match_operand 0 "cc_set_register" "") @@ -6289,66 +6291,65 @@ (define_insn "macu_r" (set_attr "predicable" "no") (set_attr "cond" "nocond")]) -(define_insn "mpyd_arcv2hs" - [(set (match_operand:DI 0 "even_register_operand""=Rcr, r") - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " 0, c")) -(sign_extend:DI (match_operand:SI 2 "register_operand" " c, c" +(define_insn "mpyd_arcv2hs" + [(set (match_operand:DI 0 "even_register_operand" "=r") + (mult:DI (SEZ:DI (match_operand:SI 1 "register_operand" "r")) +(SEZ:DI (match_operand:SI 2 "register_operand" "r" (set (reg:DI ARCV2_ACC) (mult:DI - (sign_extend:DI (match_dup 1)) - (sign_extend:DI (match_dup 2] + (SEZ:DI (match_dup 1)) + (SEZ:DI (match_dup 2] "TARGET_PLUS_MACD" - "mpyd%? %0,%1,%2" - [(set_attr "length" "4,4") - (set_attr "iscompact" "false") - (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) - -(define_insn "mpyd_imm_arcv2hs" - [(set (match_operand:DI 0 "even_register_operand""=Rcr, r,r,Rcr, r") - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " 0, c,0, 0, c")) -(match_operand 2 "immediate_operand" " L, L,I,Cal,Cal"))) + "mpyd%?\\t%0,%1,%2" + [(set_attr "length" "4") + (set_attr "iscompact" "false") + (set_attr "type" "multi") + (set_attr "predicable" "no")]) + +(define_insn "*pmpyd_arcv2hs" + [(set (match_operand:DI 0 "even_register_operand" "=r") + (mult:DI +(SEZ:DI (match_operand:SI 1 "even_register_operand" "%0")) +(SEZ:DI (match_operand:SI 2 "register_operand" "r" (set (reg:DI ARCV2_ACC) - (mult:DI (sign_extend:DI (match_dup 1)) -(match_dup 2)))] + (mult:DI + (SEZ:DI (match_dup 1)) + (SEZ:DI (match_dup 2] "TARGET_PLUS_MACD" - "mpyd%? %0,%1,%2" - [(set_attr "length" "4,4,4,8,8") - (set_attr "iscompact" "false") - (set_attr "type" "multi") - (set_attr "predicable" "yes,no,no,yes,no&quo
[backport gcc10] arc: Refurbish adc/sbc patterns
Back port for gcc10
The adc/sbc patterns were unecessary spliting, remove that and
associated functions.
gcc/
2020-12-11 Claudiu Zissulescu
* config/arc/arc-protos.h (arc_scheduling_not_expected): Remove
it.
(arc_sets_cc_p): Likewise.
(arc_need_delay): Likewise.
* config/arc/arc.c (arc_sets_cc_p): Likewise.
(arc_need_delay): Likewise.
(arc_scheduling_not_expected): Likewise.
* config/arc/arc.md: Convert adc/sbc patterns to simple
instruction definitions.
Signed-off-by: Claudiu Zissulescu
(cherry picked from commit dfbe642c97f7f430926cb6b33cd5c20b42c85573)
---
gcc/config/arc/arc-protos.h | 3 --
gcc/config/arc/arc.c| 53 -
gcc/config/arc/arc.md | 95 +++--
3 files changed, 29 insertions(+), 122 deletions(-)
diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
index c72d78e3b9e..de4cf47c818 100644
--- a/gcc/config/arc/arc-protos.h
+++ b/gcc/config/arc/arc-protos.h
@@ -90,10 +90,7 @@ extern void split_subsi (rtx *);
extern void arc_split_move (rtx *);
extern const char *arc_short_long (rtx_insn *insn, const char *, const char *);
extern rtx arc_regno_use_in (unsigned int, rtx);
-extern bool arc_scheduling_not_expected (void);
-extern bool arc_sets_cc_p (rtx_insn *insn);
extern int arc_label_align (rtx_insn *label);
-extern bool arc_need_delay (rtx_insn *insn);
extern bool arc_text_label (rtx_insn *insn);
extern bool arc_short_comparison_p (rtx, int);
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 6b96c5e4bf5..7902940c16c 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -10291,59 +10291,6 @@ arc_attr_type (rtx_insn *insn)
return get_attr_type (insn);
}
-/* Return true if insn sets the condition codes. */
-
-bool
-arc_sets_cc_p (rtx_insn *insn)
-{
- if (NONJUMP_INSN_P (insn))
-if (rtx_sequence *seq = dyn_cast (PATTERN (insn)))
- insn = seq->insn (seq->len () - 1);
- return arc_attr_type (insn) == TYPE_COMPARE;
-}
-
-/* Return true if INSN is an instruction with a delay slot we may want
- to fill. */
-
-bool
-arc_need_delay (rtx_insn *insn)
-{
- rtx_insn *next;
-
- if (!flag_delayed_branch)
-return false;
- /* The return at the end of a function needs a delay slot. */
- if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
- && (!(next = next_active_insn (insn))
- || ((!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) != SEQUENCE)
- && arc_attr_type (next) == TYPE_RETURN))
- && (!TARGET_PAD_RETURN
- || (prev_active_insn (insn)
- && prev_active_insn (prev_active_insn (insn))
- && prev_active_insn (prev_active_insn (prev_active_insn
(insn))
-return true;
- if (NONJUMP_INSN_P (insn)
- ? (GET_CODE (PATTERN (insn)) == USE
-|| GET_CODE (PATTERN (insn)) == CLOBBER
-|| GET_CODE (PATTERN (insn)) == SEQUENCE)
- : JUMP_P (insn)
- ? (GET_CODE (PATTERN (insn)) == ADDR_VEC
-|| GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
- : !CALL_P (insn))
-return false;
- return num_delay_slots (insn) != 0;
-}
-
-/* Return true if the scheduling pass(es) has/have already run,
- i.e. where possible, we should try to mitigate high latencies
- by different instruction selection. */
-
-bool
-arc_scheduling_not_expected (void)
-{
- return cfun->machine->arc_reorg_started;
-}
-
/* Code has a minimum p2 alignment of 1, which we must restore after
an ADDR_DIFF_VEC. */
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index a7f4056c7af..398034d361e 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -2824,43 +2824,25 @@ (define_insn "*add_f_2"
(set_attr "type" "compare")
(set_attr "length" "4,4,8")])
-; w/c/c comes first (rather than w/0/C_0) to prevent the middle-end
-; needlessly prioritizing the matching constraint.
-; Rcw/0/C_0 comes before w/c/L so that the lower latency conditional
-; execution is used where possible.
-(define_insn_and_split "adc"
- [(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w,Rcw,w")
- (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REG) (const_int 0))
- (match_operand:SI 1 "nonmemory_operand"
-"%c,0,c,0,cCal"))
-(match_operand:SI 2 "nonmemory_operand" "c,C_0,L,I,cCal")))]
+(define_insn "adc"
+ [(set (match_operand:SI 0 "register_operand""=r, r,r,r, r,r")
+ (plus:SI
+(plus:SI
+ (ltu:SI (reg:CC_C CC_REG) (const_int 0))
+ (match_operand:SI 1 "nonmemory_operand" "%r, 0,r,0,Cal,r"))
+(match_operand:SI 2 "nonmemory_operand" "r,C
[PATCH,committed] arc: fix accumulator first register.
gcc/
2021-01-05 Claudiu Zissulescu
* config/arc/arc.md (maddsidi4_split): Use ACC_REG_FIRST.
(umaddsidi4_split): Likewise.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.md | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 3e544430167..7a52551eef5 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -6177,12 +6177,12 @@ (define_insn_and_split "maddsidi4_split"
rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
emit_move_insn (acc_reg, operands[3]);
if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode)
- && REGNO (operands[0]) != ACCL_REGNO)
+ && REGNO (operands[0]) != ACC_REG_FIRST)
emit_insn (gen_macd (operands[0], operands[1], operands[2]));
else
{
emit_insn (gen_mac (operands[1], operands[2]));
- if (REGNO (operands[0]) != ACCL_REGNO)
+ if (REGNO (operands[0]) != ACC_REG_FIRST)
emit_move_insn (operands[0], acc_reg);
}
DONE;
@@ -6279,12 +6279,12 @@ (define_insn_and_split "umaddsidi4_split"
rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
emit_move_insn (acc_reg, operands[3]);
if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode)
- && REGNO (operands[0]) != ACCL_REGNO)
+ && REGNO (operands[0]) != ACC_REG_FIRST)
emit_insn (gen_macdu (operands[0], operands[1], operands[2]));
else
{
emit_insn (gen_macu (operands[1], operands[2]));
- if (REGNO (operands[0]) != ACCL_REGNO)
+ if (REGNO (operands[0]) != ACC_REG_FIRST)
emit_move_insn (operands[0], acc_reg);
}
DONE;
--
2.26.2
[committed 6/6] arc: generate mac(u) insn instead of macd(u) when destination is accl
Generate MAC(U) instruction instead of MACD(U) when the destination
register is already choosen as ACCL register.
gcc/
2020-12-29 Claudiu Zissulescu
* config/arc/arc.md (maddsidi4_split): Skip macd gen, use mac insn
instead.
(macd): Update register letters.
(umaddsidi4_split): Skip macdu gen, use macu insn instead.
(macdu): Update register letters.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.md | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 75c32f6d3e9..b616c7fb82c 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -6176,12 +6176,14 @@ (define_insn_and_split "maddsidi4_split"
"{
rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
emit_move_insn (acc_reg, operands[3]);
- if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode))
- emit_insn (gen_macd (operands[0], operands[1], operands[2]));
+ if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode)
+ && REGNO (operands[0]) != ACCL_REGNO)
+ emit_insn (gen_macd (operands[0], operands[1], operands[2]));
else
{
emit_insn (gen_mac (operands[1], operands[2]));
- emit_move_insn (operands[0], acc_reg);
+ if (REGNO (operands[0]) != ACCL_REGNO)
+emit_move_insn (operands[0], acc_reg);
}
DONE;
}"
@@ -6192,8 +6194,8 @@ (define_insn "macd"
[(set (match_operand:DI 0 "even_register_operand" "=Rcr,r,r")
(plus:DI
(mult:DI
- (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,c,c"))
- (sign_extend:DI (match_operand:SI 2 "extend_operand" " c,cI,Cal")))
+ (sign_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r"))
+ (sign_extend:DI (match_operand:SI 2 "extend_operand""r,rI,Cal")))
(reg:DI ARCV2_ACC)))
(set (reg:DI ARCV2_ACC)
(plus:DI
@@ -6276,12 +6278,14 @@ (define_insn_and_split "umaddsidi4_split"
"{
rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
emit_move_insn (acc_reg, operands[3]);
- if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode))
- emit_insn (gen_macdu (operands[0], operands[1], operands[2]));
+ if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode)
+ && REGNO (operands[0]) != ACCL_REGNO)
+ emit_insn (gen_macdu (operands[0], operands[1], operands[2]));
else
{
emit_insn (gen_macu (operands[1], operands[2]));
- emit_move_insn (operands[0], acc_reg);
+ if (REGNO (operands[0]) != ACCL_REGNO)
+emit_move_insn (operands[0], acc_reg);
}
DONE;
}"
@@ -6292,8 +6296,8 @@ (define_insn "macdu"
[(set (match_operand:DI 0 "even_register_operand" "=Rcr,r,r")
(plus:DI
(mult:DI
- (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,c,c"))
- (zero_extend:DI (match_operand:SI 2 "extend_operand" " c,cI,i")))
+ (zero_extend:DI (match_operand:SI 1 "register_operand" "%0,r,r"))
+ (zero_extend:DI (match_operand:SI 2 "extend_operand""r,rI,i")))
(reg:DI ARCV2_ACC)))
(set (reg:DI ARCV2_ACC)
(plus:DI
--
2.26.2
[committed 5/6] arc: flip if-condition predicates in secondary reload hook
The ARC code contains code which should only work with the old reload
pass. Such code is found in arc_secondary_reload hook, however it was
not properly quarded. Reverse the if-condition predicate such that
req_equiv_mem is called when lra is not in progress.
gcc/
2020-12-29 Claudiu Zissulescu
* config/arc/arc.c (arc_secondary_reload): Flip if-condition
predicates.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index d0a52ee8b8d..fb672c75ff4 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -901,7 +901,7 @@ arc_secondary_reload (bool in_p,
/* It is a pseudo that ends in a stack location. This
procedure only works with the old reload step. */
- if (reg_equiv_mem (REGNO (x)) && !lra_in_progress)
+ if (!lra_in_progress && reg_equiv_mem (REGNO (x)))
{
/* Get the equivalent address and check the range of the
offset. */
--
2.26.2
[committed 4/6] arc: Make use reg_renumber safe.
The REGNO_OK_FOR_BASE_P is using reg_renumber array. However, it is not always defined. Use it only when it is defined. gcc/ 2020-12-29 Claudiu Zissulescu * config/arc/arc.h (REGNO_OK_FOR_BASE_P): Check if defined reg_renumber. Signed-off-by: Claudiu Zissulescu --- gcc/config/arc/arc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index fd6e21adfaa..c3886330f1b 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -588,7 +588,7 @@ extern enum reg_class arc_regno_reg_class[]; || ((REGNO) == ARG_POINTER_REGNUM) \ || ((REGNO) == FRAME_POINTER_REGNUM) \ || ((REGNO) == PCL_REG) \ - || ((unsigned) reg_renumber[REGNO] < 29)\ + || (reg_renumber && ((unsigned) reg_renumber[REGNO] < 29)) \ || ((unsigned) (REGNO) == (unsigned) arc_tp_regno) \ || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59)) \ || (fixed_regs[REGNO] == 0 && (REGNO) == R30_REG)) -- 2.26.2
[committed 3/6] arc: Update test pattern.
gcc/testsuite
2020-12-29 Claudiu Zissulescu
* gcc.target/arc/loop-3.c: Update test pattern.
Signed-off-by: Claudiu Zissulescu
---
gcc/testsuite/gcc.target/arc/loop-3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/arc/loop-3.c
b/gcc/testsuite/gcc.target/arc/loop-3.c
index bf7aec94842..7f55e2f43fa 100644
--- a/gcc/testsuite/gcc.target/arc/loop-3.c
+++ b/gcc/testsuite/gcc.target/arc/loop-3.c
@@ -23,5 +23,5 @@ void fn1(void)
}
}
-/* { dg-final { scan-assembler "bne_s @.L2" } } */
+/* { dg-final { scan-assembler "bne.*@.L2" } } */
/* { dg-final { scan-assembler-not "add.eq" } } */
--
2.26.2
[committed 2/6] arc: Fix cached to uncached moves.
We need an temporary register when moving data from a cached memory to
an uncached memory. Fix this issue and add a test for it.
gcc/
2020-12-29 Claudiu Zissulescu
* config/arc/arc.c (prepare_move_operands): Use a temporary
registers when we have cached mem-to-uncached mem moves.
gcc/testsuite/
2020-12-29 Claudiu Zissulescu
Vladimir Isaev
* cc.target/arc/uncached-9.c: New test.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.c | 12 +--
gcc/testsuite/gcc.target/arc/uncached-9.c | 39 +++
2 files changed, 49 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/arc/uncached-9.c
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 6a9e1fbf824..d0a52ee8b8d 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -9234,13 +9234,21 @@ prepare_move_operands (rtx *operands, machine_mode mode)
}
if (arc_is_uncached_mem_p (operands[1]))
{
+ rtx tmp = operands[0];
+
if (MEM_P (operands[0]))
- operands[0] = force_reg (mode, operands[0]);
+ tmp = gen_reg_rtx (mode);
+
emit_insn (gen_rtx_SET
-(operands[0],
+(tmp,
gen_rtx_UNSPEC_VOLATILE
(mode, gen_rtvec (1, operands[1]),
VUNSPEC_ARC_LDDI)));
+ if (MEM_P (operands[0]))
+ {
+ operands[1] = tmp;
+ return false;
+ }
return true;
}
}
diff --git a/gcc/testsuite/gcc.target/arc/uncached-9.c
b/gcc/testsuite/gcc.target/arc/uncached-9.c
new file mode 100644
index 000..4caba293bc5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/uncached-9.c
@@ -0,0 +1,39 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+#include
+
+struct uncached_st
+{
+ int value;
+} __attribute__((uncached));
+
+struct cached_st
+{
+ int value;
+};
+
+struct uncached_st g_uncached_st =
+ {
+.value = 17
+ };
+
+struct cached_st g_cached_st =
+ {
+.value = 4
+ };
+
+void __attribute__((noinline)) test_struct_copy (void)
+{
+ g_cached_st.value = g_uncached_st.value;
+}
+
+int main (void)
+{
+ test_struct_copy();
+
+ if (g_cached_st.value != g_uncached_st.value)
+abort ();
+
+ return 0;
+}
--
2.26.2
[committed 1/6] arc: Don't use predicated vadd2 instructions in mov patterns.
Update movdi, movdf and mov vectors not to use predicated vadd2 instructions. vadd2 is used as a "fast" move in these patterns. This fixes a number of failures in dejagnu. gcc/ 2020-12-29 Claudiu Zissulescu * config/arc/arc.md (movdi_insn): Update pattern, no predicated vadd2 usage. (movdf_insn): Likewise. * config/arc/simdext.md (movVEC_insn): Likewise. Signed-off-by: Claudiu Zissulescu --- gcc/config/arc/arc.md | 6 +++--- gcc/config/arc/simdext.md | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index ae08146bcaf..75c32f6d3e9 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -1341,7 +1341,7 @@ (define_insn_and_split "*movdi_insn" if (TARGET_PLUS_QMACW && even_register_operand (operands[0], DImode) && even_register_operand (operands[1], DImode)) - return \"vadd2\\t%0,%1,0\"; + return \"vadd2%?\\t%0,%1,0\"; return \"#\"; case 2: @@ -1421,7 +1421,7 @@ (define_insn_and_split "*movdf_insn" if (TARGET_PLUS_QMACW && even_register_operand (operands[0], DFmode) && even_register_operand (operands[1], DFmode)) - return \"vadd2\\t%0,%1,0\"; + return \"vadd2%?\\t%0,%1,0\"; return \"#\"; case 4: @@ -1450,7 +1450,7 @@ (define_insn_and_split "*movdf_insn" DONE; } [(set_attr "type" "move,move,move,move,load,store") - (set_attr "predicable" "no,no,yes,yes,no,no") + (set_attr "predicable" "no,no,no,yes,no,no") ;; ??? The ld/st values could be 16 if it's [reg,bignum]. (set_attr "length" "4,16,8,16,16,16")]) diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md index d2fc309ea87..58651b5fcac 100644 --- a/gcc/config/arc/simdext.md +++ b/gcc/config/arc/simdext.md @@ -1413,7 +1413,7 @@ (define_insn_and_split "*mov_insn" if (TARGET_PLUS_QMACW && even_register_operand (operands[0], mode) && even_register_operand (operands[1], mode)) - return \"vadd2\\t%0,%1,0\"; + return \"vadd2%?\\t%0,%1,0\"; return \"#\"; case 2: @@ -1434,7 +1434,7 @@ (define_insn_and_split "*mov_insn" DONE; } [(set_attr "type" "move,multi,load,store") - (set_attr "predicable" "yes,no,no,no") + (set_attr "predicable" "no,no,no,no") (set_attr "iscompact" "false,false,false,false") ]) -- 2.26.2
[committed] arc: Update ARC700 cache hazard detection.
From: Claudiu Zissulescu
Replace/update ARC700 cache hazard detection. The next situations are
handled:
- There are 2 stores back2back, then 3 loads in next 3 or 4 instructions.
if 3 loads in 3 instructions then we insert 2 nops after stores.
if 3 loads in 4 instructions then we insert 1 nop after stores
- 2 back to back stores, followed by at least 3 loads in next 4 instructions.
st st ld ld ld ##
st st ## ld ld ld
st st ld ## ld ld
st st ld ld ## ld
## - any instruction
- store between non-store instructions, followed by 3 loads
$$ st SS ld ld ld
$$ - non-store instruction, even load.
gcc/
2020-12-11 Claudiu Zissulescu
* config/arc/arc.c (arc_active_insn): Ignore all non essential
instructions when getting the next active instruction.
(check_store_cacheline_hazard): Update.
(workaround_arc_anomaly): Remove obsolete cache hazard code.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.c | 52
1 file changed, 23 insertions(+), 29 deletions(-)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 27bd458537b..6a9e1fbf824 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -7663,11 +7663,18 @@ arc_invalid_within_doloop (const rtx_insn *insn)
static rtx_insn *
arc_active_insn (rtx_insn *insn)
{
- rtx_insn *nxt = next_active_insn (insn);
-
- if (nxt && GET_CODE (PATTERN (nxt)) == ASM_INPUT)
-nxt = next_active_insn (nxt);
- return nxt;
+ while (insn)
+{
+ insn = NEXT_INSN (insn);
+ if (insn == 0
+ || (active_insn_p (insn)
+ && NONDEBUG_INSN_P (insn)
+ && !NOTE_P (insn)
+ && GET_CODE (PATTERN (insn)) != UNSPEC_VOLATILE
+ && GET_CODE (PATTERN (insn)) != PARALLEL))
+ break;
+}
+ return insn;
}
/* Search for a sequence made out of two stores and a given number of
@@ -7686,11 +7693,10 @@ check_store_cacheline_hazard (void)
if (!succ0)
return;
- if (!single_set (insn) || !single_set (succ0))
+ if (!single_set (insn))
continue;
- if ((get_attr_type (insn) != TYPE_STORE)
- || (get_attr_type (succ0) != TYPE_STORE))
+ if ((get_attr_type (insn) != TYPE_STORE))
continue;
/* Found at least two consecutive stores. Goto the end of the
@@ -7699,6 +7705,9 @@ check_store_cacheline_hazard (void)
if (!single_set (insn1) || get_attr_type (insn1) != TYPE_STORE)
break;
+ /* Save were we are. */
+ succ0 = insn1;
+
/* Now, check the next two instructions for the following cases:
1. next instruction is a LD => insert 2 nops between store
sequence and load.
@@ -7730,9 +7739,13 @@ check_store_cacheline_hazard (void)
}
}
- insn = insn1;
if (found)
- found = false;
+ {
+ insn = insn1;
+ found = false;
+ }
+ else
+ insn = succ0;
}
}
@@ -7807,7 +7820,6 @@ static void
workaround_arc_anomaly (void)
{
rtx_insn *insn, *succ0;
- rtx_insn *succ1;
/* For any architecture: call arc_hazard here. */
for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
@@ -7826,24 +7838,6 @@ workaround_arc_anomaly (void)
nops between any sequence of stores and a load. */
if (arc_tune != ARC_TUNE_ARC7XX)
check_store_cacheline_hazard ();
-
- for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
-{
- succ0 = next_real_insn (insn);
- if (arc_store_addr_hazard_internal_p (insn, succ0))
- {
- emit_insn_after (gen_nopv (), insn);
- emit_insn_after (gen_nopv (), insn);
- continue;
- }
-
- /* Avoid adding nops if the instruction between the ST and LD is
-a call or jump. */
- succ1 = next_real_insn (succ0);
- if (succ0 && !JUMP_P (succ0) && !CALL_P (succ0)
- && arc_store_addr_hazard_internal_p (insn, succ1))
- emit_insn_after (gen_nopv (), insn);
-}
}
/* A callback for the hw-doloop pass. Called when a loop we have discovered
--
2.26.2
[committed] arc: Avoid generating brcc instructions with limm
From: Claudiu Zissulescu BRcc instructions are generated quite late in the compilation process. These instructions combines a compare with a regular conditional branch if the result of the compare is not used anylonger. However, when compiling for size, it is better to avoid BRcc instructions which are introducing a 32-bit long immediate. gcc/ 2020-12-11 Claudiu Zissulescu * config/arc/arc.c (arc_reorg): Avoid limm in BRcc. --- gcc/config/arc/arc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c index b80bb9b63a5..27bd458537b 100644 --- a/gcc/config/arc/arc.c +++ b/gcc/config/arc/arc.c @@ -8589,6 +8589,7 @@ arc_reorg (void) if (!brcc_nolimm_operator (op, VOIDmode) && !long_immediate_operand (op1, VOIDmode) && (TARGET_ARC700 + || (TARGET_V2 && optimize_size) || next_active_insn (link_insn) != insn)) continue; -- 2.26.2
[committed] arc: Refurbish adc/sbc patterns
The adc/sbc patterns were unecessary spliting, remove that and
associated functions.
gcc/
2020-12-11 Claudiu Zissulescu
* config/arc/arc-protos.h (arc_scheduling_not_expected): Remove
it.
(arc_sets_cc_p): Likewise.
(arc_need_delay): Likewise.
* config/arc/arc.c (arc_sets_cc_p): Likewise.
(arc_need_delay): Likewise.
(arc_scheduling_not_expected): Likewise.
* config/arc/arc.md: Convert adc/sbc patterns to simple
instruction definitions.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc-protos.h | 3 --
gcc/config/arc/arc.c| 53 -
gcc/config/arc/arc.md | 95 +++--
3 files changed, 29 insertions(+), 122 deletions(-)
diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h
index c72d78e3b9e..de4cf47c818 100644
--- a/gcc/config/arc/arc-protos.h
+++ b/gcc/config/arc/arc-protos.h
@@ -90,10 +90,7 @@ extern void split_subsi (rtx *);
extern void arc_split_move (rtx *);
extern const char *arc_short_long (rtx_insn *insn, const char *, const char *);
extern rtx arc_regno_use_in (unsigned int, rtx);
-extern bool arc_scheduling_not_expected (void);
-extern bool arc_sets_cc_p (rtx_insn *insn);
extern int arc_label_align (rtx_insn *label);
-extern bool arc_need_delay (rtx_insn *insn);
extern bool arc_text_label (rtx_insn *insn);
extern bool arc_short_comparison_p (rtx, int);
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index eabc122d5f1..b80bb9b63a5 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -10299,59 +10299,6 @@ arc_attr_type (rtx_insn *insn)
return get_attr_type (insn);
}
-/* Return true if insn sets the condition codes. */
-
-bool
-arc_sets_cc_p (rtx_insn *insn)
-{
- if (NONJUMP_INSN_P (insn))
-if (rtx_sequence *seq = dyn_cast (PATTERN (insn)))
- insn = seq->insn (seq->len () - 1);
- return arc_attr_type (insn) == TYPE_COMPARE;
-}
-
-/* Return true if INSN is an instruction with a delay slot we may want
- to fill. */
-
-bool
-arc_need_delay (rtx_insn *insn)
-{
- rtx_insn *next;
-
- if (!flag_delayed_branch)
-return false;
- /* The return at the end of a function needs a delay slot. */
- if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
- && (!(next = next_active_insn (insn))
- || ((!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) != SEQUENCE)
- && arc_attr_type (next) == TYPE_RETURN))
- && (!TARGET_PAD_RETURN
- || (prev_active_insn (insn)
- && prev_active_insn (prev_active_insn (insn))
- && prev_active_insn (prev_active_insn (prev_active_insn
(insn))
-return true;
- if (NONJUMP_INSN_P (insn)
- ? (GET_CODE (PATTERN (insn)) == USE
-|| GET_CODE (PATTERN (insn)) == CLOBBER
-|| GET_CODE (PATTERN (insn)) == SEQUENCE)
- : JUMP_P (insn)
- ? (GET_CODE (PATTERN (insn)) == ADDR_VEC
-|| GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC)
- : !CALL_P (insn))
-return false;
- return num_delay_slots (insn) != 0;
-}
-
-/* Return true if the scheduling pass(es) has/have already run,
- i.e. where possible, we should try to mitigate high latencies
- by different instruction selection. */
-
-bool
-arc_scheduling_not_expected (void)
-{
- return cfun->machine->arc_reorg_started;
-}
-
/* Code has a minimum p2 alignment of 1, which we must restore after
an ADDR_DIFF_VEC. */
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 2b46e265538..ae08146bcaf 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -2842,43 +2842,25 @@ (define_insn "*add_f_2"
(set_attr "type" "compare")
(set_attr "length" "4,4,8")])
-; w/c/c comes first (rather than w/0/C_0) to prevent the middle-end
-; needlessly prioritizing the matching constraint.
-; Rcw/0/C_0 comes before w/c/L so that the lower latency conditional
-; execution is used where possible.
-(define_insn_and_split "adc"
- [(set (match_operand:SI 0 "dest_reg_operand" "=w,Rcw,w,Rcw,w")
- (plus:SI (plus:SI (ltu:SI (reg:CC_C CC_REG) (const_int 0))
- (match_operand:SI 1 "nonmemory_operand"
-"%c,0,c,0,cCal"))
-(match_operand:SI 2 "nonmemory_operand" "c,C_0,L,I,cCal")))]
+(define_insn "adc"
+ [(set (match_operand:SI 0 "register_operand""=r, r,r,r, r,r")
+ (plus:SI
+(plus:SI
+ (ltu:SI (reg:CC_C CC_REG) (const_int 0))
+ (match_operand:SI 1 "nonmemory_operand" "%r, 0,r,0,Cal,r"))
+(match_operand:SI 2 "nonmemory_operand" "r,C_0,L,I, r,Cal")))]
"register_operand (operands[1], SImode)
Re: [PATCH] arc: Use separate predicated patterns for mpyd(u)
Gentle PING. On Wed, Oct 7, 2020 at 12:39 PM Claudiu Zissulescu wrote: > > From: Claudiu Zissulescu > > The compiler can match mpyd.eq r0,r1,r0 as a predicated instruction, > which is incorrect. The mpyd(u) instruction takes as input two 32-bit > registers, returning into a double 64-bit even-odd register pair. For > the predicated case, the ARC instruction decoder expects the > destination register to be the same as the first input register. In > the big-endian case the result is swaped in the destination register > pair, however, the instruction encoding remains the same. Refurbish > the mpyd(u) patterns to take into account the above observation. > > Permission to apply this patch to master, gcc10 and gcc9 branches. > > Cheers, > Claudiu > > -xx-xx Claudiu Zissulescu > > * testsuite/gcc.target/arc/pmpyd.c: New test. > * testsuite/gcc.target/arc/tmac-1.c: Update. > * config/arc/arc.md (mpyd_arcv2hs): New template > pattern. > (*pmpyd_arcv2hs): Likewise. > (*pmpyd_imm_arcv2hs): Likewise. > (mpyd_arcv2hs): Moved into above template. > (mpyd_imm_arcv2hs): Moved into above template. > (mpydu_arcv2hs): Likewise. > (mpydu_imm_arcv2hs): Likewise. > (su_optab): New optab prefix for sign/zero-extending operations. > > Signed-off-by: Claudiu Zissulescu > --- > gcc/config/arc/arc.md | 101 +- > gcc/testsuite/gcc.target/arc/pmpyd.c | 15 > gcc/testsuite/gcc.target/arc/tmac-1.c | 2 +- > 3 files changed, 67 insertions(+), 51 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/arc/pmpyd.c > > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index 1720e8cd2f6f..d4d9f59a3eac 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -894,6 +894,8 @@ archs4x, archs4xd" > > (define_code_iterator SEZ [sign_extend zero_extend]) > (define_code_attr SEZ_prefix [(sign_extend "sex") (zero_extend "ext")]) > +; Optab prefix for sign/zero-extending operations > +(define_code_attr su_optab [(sign_extend "") (zero_extend "u")]) > > (define_insn "*xt_cmp0_noout" >[(set (match_operand 0 "cc_set_register" "") > @@ -6436,66 +6438,65 @@ archs4x, archs4xd" > (set_attr "predicable" "no") > (set_attr "cond" "nocond")]) > > -(define_insn "mpyd_arcv2hs" > - [(set (match_operand:DI 0 "even_register_operand" > "=Rcr, r") > - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " > 0, c")) > -(sign_extend:DI (match_operand:SI 2 "register_operand" " > c, c" > +(define_insn "mpyd_arcv2hs" > + [(set (match_operand:DI 0 "even_register_operand" "=r") > + (mult:DI (SEZ:DI (match_operand:SI 1 "register_operand" "r")) > +(SEZ:DI (match_operand:SI 2 "register_operand" "r" > (set (reg:DI ARCV2_ACC) > (mult:DI > - (sign_extend:DI (match_dup 1)) > - (sign_extend:DI (match_dup 2] > + (SEZ:DI (match_dup 1)) > + (SEZ:DI (match_dup 2] >"TARGET_PLUS_MACD" > - "mpyd%? %0,%1,%2" > - [(set_attr "length" "4,4") > - (set_attr "iscompact" "false") > - (set_attr "type" "multi") > - (set_attr "predicable" "yes,no") > - (set_attr "cond" "canuse,nocond")]) > - > -(define_insn "mpyd_imm_arcv2hs" > - [(set (match_operand:DI 0 "even_register_operand" > "=Rcr, r,r,Rcr, r") > - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " > 0, c,0, 0, c")) > -(match_operand 2 "immediate_operand" " > L, L,I,Cal,Cal"))) > + "mpyd%?\\t%0,%1,%2" > + [(set_attr "length" "4") > + (set_attr "iscompact" "false") > + (set_attr "type" "multi") > + (set_attr "predicable" "no")]) > + > +(define_insn "*pmpyd_arcv2hs" > + [(set (match_operand:DI 0 "even_register_operand" "=r") > + (mult:DI > +(SEZ:DI (match_operand:SI 1 "even_register_operand" "%0")) > +(SEZ:DI (match_operand:SI 2 "register_operand" "r" > (s
Re: [PATCH] arc: Improve/add instruction patterns to better use MAC instructions.
Gentle PING.
On Fri, Oct 9, 2020 at 5:24 PM Claudiu Zissulescu wrote:
>
> From: Claudiu Zissulescu
>
> ARC MYP7+ instructions add MAC instructions for vector and scalar data
> types. This patch adds a madd pattern for 16it datum that is using the
> 32bit MAC instruction, and dot_prod patterns for v4hi vector
> types. The 64bit moves are also upgraded by using vadd2 instuction.
>
> gcc/
> -xx-xx Claudiu Zissulescu
>
> * config/arc/arc.c (arc_split_move): Recognize vadd2 instructions.
> * config/arc/arc.md (movdi_insn): Update pattern to use vadd2
> instructions.
> (movdf_insn): Likewise.
> (maddhisi4): New pattern.
> (umaddhisi4): Likewise.
> * config/arc/simdext.md (mov_int): Update pattern to use
> vadd2.
> (sdot_prodv4hi): New pattern.
> (udot_prodv4hi): Likewise.
> (arc_vec_mac_hi_v4hi): Update/renamed to
> arc_vec_mac_v2hiv2si.
> (arc_vec_mac_v2hiv2si_zero): New pattern.
>
> Signed-off-by: Claudiu Zissulescu
> ---
> gcc/config/arc/arc.c | 8
> gcc/config/arc/arc.md | 71 ---
> gcc/config/arc/constraints.md | 5 ++
> gcc/config/arc/simdext.md | 90 +++
> 4 files changed, 147 insertions(+), 27 deletions(-)
>
> diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
> index ec55cfde87a9..d5b521e75e67 100644
> --- a/gcc/config/arc/arc.c
> +++ b/gcc/config/arc/arc.c
> @@ -10202,6 +10202,14 @@ arc_split_move (rtx *operands)
>return;
> }
>
> + if (TARGET_PLUS_QMACW
> + && even_register_operand (operands[0], mode)
> + && even_register_operand (operands[1], mode))
> +{
> + emit_move_insn (operands[0], operands[1]);
> + return;
> +}
> +
>if (TARGET_PLUS_QMACW
>&& GET_CODE (operands[1]) == CONST_VECTOR)
> {
> diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
> index f9fc11e51a85..1720e8cd2f6f 100644
> --- a/gcc/config/arc/arc.md
> +++ b/gcc/config/arc/arc.md
> @@ -1345,8 +1345,8 @@ archs4x, archs4xd"
>")
>
> (define_insn_and_split "*movdi_insn"
> - [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r, m")
> - (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,cCm3"))]
> + [(set (match_operand:DI 0 "move_dest_operand" "=r, r,r, m")
> + (match_operand:DI 1 "move_double_src_operand" "r,Hi,m,rCm3"))]
>"register_operand (operands[0], DImode)
> || register_operand (operands[1], DImode)
> || (satisfies_constraint_Cm3 (operands[1])
> @@ -1358,6 +1358,13 @@ archs4x, archs4xd"
> default:
>return \"#\";
>
> +case 0:
> +if (TARGET_PLUS_QMACW
> + && even_register_operand (operands[0], DImode)
> + && even_register_operand (operands[1], DImode))
> + return \"vadd2\\t%0,%1,0\";
> +return \"#\";
> +
> case 2:
> if (TARGET_LL64
> && memory_operand (operands[1], DImode)
> @@ -1374,7 +1381,7 @@ archs4x, archs4xd"
> return \"#\";
> }
> }"
> - "reload_completed"
> + "&& reload_completed"
>[(const_int 0)]
>{
> arc_split_move (operands);
> @@ -1420,15 +1427,24 @@ archs4x, archs4xd"
>"if (prepare_move_operands (operands, DFmode)) DONE;")
>
> (define_insn_and_split "*movdf_insn"
> - [(set (match_operand:DF 0 "move_dest_operand" "=D,r,c,c,r,m")
> - (match_operand:DF 1 "move_double_src_operand" "r,D,c,E,m,c"))]
> - "register_operand (operands[0], DFmode) || register_operand (operands[1],
> DFmode)"
> + [(set (match_operand:DF 0 "move_dest_operand" "=D,r,r,r,r,m")
> + (match_operand:DF 1 "move_double_src_operand" "r,D,r,E,m,r"))]
> + "register_operand (operands[0], DFmode)
> + || register_operand (operands[1], DFmode)"
>"*
> {
> switch (which_alternative)
> {
> default:
>return \"#\";
> +
> +case 2:
> +if (TARGET_PLUS_QMACW
> + && even_register_operand (operands[0], DFmode)
> + && even_register_operand (operands[1], DFmode))
> + return \"vadd2\\t%0,%1,0\";
> +return \"#\";
> +
> case 4:
> if (TARGET_LL64
> && ((even_register_operand (operands[0], DFmode)
> @@ -6177,6
[PATCH] arc: Improve/add instruction patterns to better use MAC instructions.
From: Claudiu Zissulescu
ARC MYP7+ instructions add MAC instructions for vector and scalar data
types. This patch adds a madd pattern for 16it datum that is using the
32bit MAC instruction, and dot_prod patterns for v4hi vector
types. The 64bit moves are also upgraded by using vadd2 instuction.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.c (arc_split_move): Recognize vadd2 instructions.
* config/arc/arc.md (movdi_insn): Update pattern to use vadd2
instructions.
(movdf_insn): Likewise.
(maddhisi4): New pattern.
(umaddhisi4): Likewise.
* config/arc/simdext.md (mov_int): Update pattern to use
vadd2.
(sdot_prodv4hi): New pattern.
(udot_prodv4hi): Likewise.
(arc_vec_mac_hi_v4hi): Update/renamed to
arc_vec_mac_v2hiv2si.
(arc_vec_mac_v2hiv2si_zero): New pattern.
Signed-off-by: Claudiu Zissulescu
---
gcc/config/arc/arc.c | 8
gcc/config/arc/arc.md | 71 ---
gcc/config/arc/constraints.md | 5 ++
gcc/config/arc/simdext.md | 90 +++
4 files changed, 147 insertions(+), 27 deletions(-)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index ec55cfde87a9..d5b521e75e67 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -10202,6 +10202,14 @@ arc_split_move (rtx *operands)
return;
}
+ if (TARGET_PLUS_QMACW
+ && even_register_operand (operands[0], mode)
+ && even_register_operand (operands[1], mode))
+{
+ emit_move_insn (operands[0], operands[1]);
+ return;
+}
+
if (TARGET_PLUS_QMACW
&& GET_CODE (operands[1]) == CONST_VECTOR)
{
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index f9fc11e51a85..1720e8cd2f6f 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -1345,8 +1345,8 @@ archs4x, archs4xd"
")
(define_insn_and_split "*movdi_insn"
- [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r, m")
- (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,cCm3"))]
+ [(set (match_operand:DI 0 "move_dest_operand" "=r, r,r, m")
+ (match_operand:DI 1 "move_double_src_operand" "r,Hi,m,rCm3"))]
"register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode)
|| (satisfies_constraint_Cm3 (operands[1])
@@ -1358,6 +1358,13 @@ archs4x, archs4xd"
default:
return \"#\";
+case 0:
+if (TARGET_PLUS_QMACW
+ && even_register_operand (operands[0], DImode)
+ && even_register_operand (operands[1], DImode))
+ return \"vadd2\\t%0,%1,0\";
+return \"#\";
+
case 2:
if (TARGET_LL64
&& memory_operand (operands[1], DImode)
@@ -1374,7 +1381,7 @@ archs4x, archs4xd"
return \"#\";
}
}"
- "reload_completed"
+ "&& reload_completed"
[(const_int 0)]
{
arc_split_move (operands);
@@ -1420,15 +1427,24 @@ archs4x, archs4xd"
"if (prepare_move_operands (operands, DFmode)) DONE;")
(define_insn_and_split "*movdf_insn"
- [(set (match_operand:DF 0 "move_dest_operand" "=D,r,c,c,r,m")
- (match_operand:DF 1 "move_double_src_operand" "r,D,c,E,m,c"))]
- "register_operand (operands[0], DFmode) || register_operand (operands[1],
DFmode)"
+ [(set (match_operand:DF 0 "move_dest_operand" "=D,r,r,r,r,m")
+ (match_operand:DF 1 "move_double_src_operand" "r,D,r,E,m,r"))]
+ "register_operand (operands[0], DFmode)
+ || register_operand (operands[1], DFmode)"
"*
{
switch (which_alternative)
{
default:
return \"#\";
+
+case 2:
+if (TARGET_PLUS_QMACW
+ && even_register_operand (operands[0], DFmode)
+ && even_register_operand (operands[1], DFmode))
+ return \"vadd2\\t%0,%1,0\";
+return \"#\";
+
case 4:
if (TARGET_LL64
&& ((even_register_operand (operands[0], DFmode)
@@ -6177,6 +6193,49 @@ archs4x, archs4xd"
[(set_attr "length" "0")])
;; MAC and DMPY instructions
+
+; Use MAC instruction to emulate 16bit mac.
+(define_expand "maddhisi4"
+ [(match_operand:SI 0 "register_operand" "")
+ (match_operand:HI 1 "register_operand" "")
+ (match_operand:HI 2 "extend_operand" "")
+ (match_operand:SI 3 "register_operand" "")]
+ "TARGET_PLUS_DMPY"
+ "{
+ rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST);
+ rtx tmp1 = gen_reg_rtx (SImode);
+ rtx tmp2 = gen_reg_rtx (SImode);
+ rtx accl = gen_lo
[PATCH] arc: Use separate predicated patterns for mpyd(u)
From: Claudiu Zissulescu The compiler can match mpyd.eq r0,r1,r0 as a predicated instruction, which is incorrect. The mpyd(u) instruction takes as input two 32-bit registers, returning into a double 64-bit even-odd register pair. For the predicated case, the ARC instruction decoder expects the destination register to be the same as the first input register. In the big-endian case the result is swaped in the destination register pair, however, the instruction encoding remains the same. Refurbish the mpyd(u) patterns to take into account the above observation. Permission to apply this patch to master, gcc10 and gcc9 branches. Cheers, Claudiu -xx-xx Claudiu Zissulescu * testsuite/gcc.target/arc/pmpyd.c: New test. * testsuite/gcc.target/arc/tmac-1.c: Update. * config/arc/arc.md (mpyd_arcv2hs): New template pattern. (*pmpyd_arcv2hs): Likewise. (*pmpyd_imm_arcv2hs): Likewise. (mpyd_arcv2hs): Moved into above template. (mpyd_imm_arcv2hs): Moved into above template. (mpydu_arcv2hs): Likewise. (mpydu_imm_arcv2hs): Likewise. (su_optab): New optab prefix for sign/zero-extending operations. Signed-off-by: Claudiu Zissulescu --- gcc/config/arc/arc.md | 101 +- gcc/testsuite/gcc.target/arc/pmpyd.c | 15 gcc/testsuite/gcc.target/arc/tmac-1.c | 2 +- 3 files changed, 67 insertions(+), 51 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arc/pmpyd.c diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 1720e8cd2f6f..d4d9f59a3eac 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -894,6 +894,8 @@ archs4x, archs4xd" (define_code_iterator SEZ [sign_extend zero_extend]) (define_code_attr SEZ_prefix [(sign_extend "sex") (zero_extend "ext")]) +; Optab prefix for sign/zero-extending operations +(define_code_attr su_optab [(sign_extend "") (zero_extend "u")]) (define_insn "*xt_cmp0_noout" [(set (match_operand 0 "cc_set_register" "") @@ -6436,66 +6438,65 @@ archs4x, archs4xd" (set_attr "predicable" "no") (set_attr "cond" "nocond")]) -(define_insn "mpyd_arcv2hs" - [(set (match_operand:DI 0 "even_register_operand""=Rcr, r") - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " 0, c")) -(sign_extend:DI (match_operand:SI 2 "register_operand" " c, c" +(define_insn "mpyd_arcv2hs" + [(set (match_operand:DI 0 "even_register_operand" "=r") + (mult:DI (SEZ:DI (match_operand:SI 1 "register_operand" "r")) +(SEZ:DI (match_operand:SI 2 "register_operand" "r" (set (reg:DI ARCV2_ACC) (mult:DI - (sign_extend:DI (match_dup 1)) - (sign_extend:DI (match_dup 2] + (SEZ:DI (match_dup 1)) + (SEZ:DI (match_dup 2] "TARGET_PLUS_MACD" - "mpyd%? %0,%1,%2" - [(set_attr "length" "4,4") - (set_attr "iscompact" "false") - (set_attr "type" "multi") - (set_attr "predicable" "yes,no") - (set_attr "cond" "canuse,nocond")]) - -(define_insn "mpyd_imm_arcv2hs" - [(set (match_operand:DI 0 "even_register_operand""=Rcr, r,r,Rcr, r") - (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " 0, c,0, 0, c")) -(match_operand 2 "immediate_operand" " L, L,I,Cal,Cal"))) + "mpyd%?\\t%0,%1,%2" + [(set_attr "length" "4") + (set_attr "iscompact" "false") + (set_attr "type" "multi") + (set_attr "predicable" "no")]) + +(define_insn "*pmpyd_arcv2hs" + [(set (match_operand:DI 0 "even_register_operand" "=r") + (mult:DI +(SEZ:DI (match_operand:SI 1 "even_register_operand" "%0")) +(SEZ:DI (match_operand:SI 2 "register_operand" "r" (set (reg:DI ARCV2_ACC) - (mult:DI (sign_extend:DI (match_dup 1)) -(match_dup 2)))] + (mult:DI + (SEZ:DI (match_dup 1)) + (SEZ:DI (match_dup 2] "TARGET_PLUS_MACD" - "mpyd%? %0,%1,%2" - [(set_attr "length" "4,4,4,8,8") - (set_attr "iscompact" "false") - (set_attr "type" "multi") - (set_attr "predicable" "yes,no,no,yes,no") - (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond")]) -
Re: [PATCH] [ARC] Allow more ABIs in GLIBC_DYNAMIC_LINKER
Done.
Thank you for your support,
Claudiu
On Thu, Apr 9, 2020 at 2:38 AM Vineet Gupta wrote:
>
> Hi Claudiu,
>
> For glibc needs can this be backported to gcc-9 please !
>
> Thx,
> -Vineet
>
> On 3/31/20 3:06 AM, Claudiu Zissulescu Ianculescu wrote:
> > Pushed.
> >
> > Thank you,
> > Claudiu
> >
> > On Sun, Mar 29, 2020 at 2:05 AM Vineet Gupta via Gcc-patches
> > wrote:
> >> Enable big-endian suffixed dynamic linker per glibc multi-abi support.
> >>
> >> And to avoid a future churn and version pairingi hassles, also allow
> >> arc700 although glibc for ARC currently doesn't support it.
> >>
> >> gcc/
> >> -xx-xx Vineet Gupta
> >> +
> >> + * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700
> >>
> >> Signed-off-by: Vineet Gupta
> >> ---
> >> gcc/ChangeLog | 4
> >> gcc/config/arc/linux.h | 2 +-
> >> 2 files changed, 5 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/gcc/ChangeLog b/gcc/ChangeLog
> >> index 86ad683a6cb0..c26a748fd51b 100644
> >> --- a/gcc/ChangeLog
> >> +++ b/gcc/ChangeLog
> >> @@ -1,3 +1,7 @@
> >> +2020-03-28 Vineet Gupta
> >> +
> >> + * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700
> >> +
> >> 2020-03-28 Jakub Jelinek
> >>
> >> PR c/93573
> >> diff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h
> >> index 0b99da3fcdaf..1bbeccee7115 100644
> >> --- a/gcc/config/arc/linux.h
> >> +++ b/gcc/config/arc/linux.h
> >> @@ -29,7 +29,7 @@ along with GCC; see the file COPYING3. If not see
> >> } \
> >>while (0)
> >>
> >> -#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-arc.so.2"
> >> +#define GLIBC_DYNAMIC_LINKER
> >> "/lib/ld-linux-arc%{mbig-endian:eb}%{mcpu=arc700:700}.so.2"
> >> #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
> >>
> >> /* Note that the default is to link against dynamic libraries, if they are
> >> --
> >> 2.20.1
> >>
> > ___
> > linux-snps-arc mailing list
> > linux-snps-...@lists.infradead.org
> > https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_mailman_listinfo_linux-2Dsnps-2Darc=DwICAg=DPL6_X_6JkXFx7AXWqB0tg=7FgpX6o3vAhwMrMhLh-4ZJey5kjdNUwOL2CWsFwR4T8=MrObyH2ki95_7m_xHpnWX-k9eIMOsxMuSa48qhxYOCY=3ggbGwaiJuSFnFECy0ItuwBBMDAcriwCdSc3GA0UFig=
>
[PATCH] arc:commited: Allow more ABIs in GLIBC_DYNAMIC_LINKER
Backport to gcc9:
Enable big-endian suffixed dynamic linker per glibc multi-abi support.
And to avoid a future churn and version pairingi hassles, also allow
arc700 although glibc for ARC currently doesn't support it.
gcc/
-xx-xx Vineet Gupta
* config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700
---
gcc/ChangeLog | 6 ++
gcc/config/arc/linux.h | 3 ++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 836a20f79d1..be4384eb0ef 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-04-10 Claudiu Zissulescu
+
+ Backport from trunk
+ 2020-0-31 Vineet Gupta
+ * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700.
+
2020-04-09 Michael Meissner
Back port from trunk
diff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h
index 270ca907d87..7d07adc4257 100644
--- a/gcc/config/arc/linux.h
+++ b/gcc/config/arc/linux.h
@@ -29,7 +29,8 @@ along with GCC; see the file COPYING3. If not see
} \
while (0)
-#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-arc.so.2"
+#define GLIBC_DYNAMIC_LINKER \
+ "/lib/ld-linux-arc%{mbig-endian:eb}%{mcpu=arc700:700}.so.2"
#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
/* Note that the default is to link against dynamic libraries, if they are
--
2.24.1
[PATCH][committed] arc: Update operand printing
Use HOST_WIDE_INT_PRINT_DEC macro instead of %ld for format printing.
Committed as obvious.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.c (arc_print_operand): Use
HOST_WIDE_INT_PRINT_DEC macro.
---
gcc/ChangeLog| 5 +
gcc/config/arc/arc.c | 6 +++---
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9da7a4a76b7..3d4e798a2f1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2020-03-31 Claudiu Zissulescu
+
+ * config/arc/arc.c (arc_print_operand): Use
+ HOST_WIDE_INT_PRINT_DEC macro.
+
2020-03-31 Claudiu Zissulescu
* config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 922ccc5c9f9..6b96c5e4bf5 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -4530,7 +4530,7 @@ arc_print_operand (FILE *file, rtx x, int code)
case 'c':
if (GET_CODE (x) == CONST_INT)
-fprintf (file, "%ld", INTVAL (x) );
+fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) );
else
output_operand_lossage ("invalid operands to %%c code");
@@ -4724,7 +4724,7 @@ arc_print_operand (FILE *file, rtx x, int code)
/* No special treatment for jli_fixed functions. */
if (code == 'j')
break;
- fprintf (file, "%ld\t; @",
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC "\t; @",
TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attrs;
assemble_name (file, XSTR (x, 0));
return;
@@ -4745,7 +4745,7 @@ arc_print_operand (FILE *file, rtx x, int code)
tree attrs = (TREE_TYPE (SYMBOL_REF_DECL (x)) != error_mark_node
? TYPE_ATTRIBUTES (TREE_TYPE (SYMBOL_REF_DECL (x)))
: NULL_TREE);
- fprintf (file, "%ld\t; @",
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC "\t; @",
TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attrs;
assemble_name (file, XSTR (x, 0));
return;
--
2.24.1
[PATCH][committed] arc: Cleanup compilation warning
Committed as obvious.
gcc/
-xx-xx Claudiu Zissulescu
* config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.
---
gcc/ChangeLog| 6 +-
gcc/config/arc/arc.h | 6 +++---
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 928c7939925..9da7a4a76b7 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,10 +1,14 @@
+2020-03-31 Claudiu Zissulescu
+
+ * config/arc/arc.h (ASM_FORMAT_PRIVATE_NAME): Fix it.
+
2020-03-31 Srinath Parvathaneni
* config/arm/arm_mve.h (vbicq): Define MVE intrinsic polymorphic
variant.
(__arm_vbicq): Likewise.
-2020-0-31 Vineet Gupta
+2020-03-31 Vineet Gupta
* config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700.
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index be1d5cb21e7..fd6e21adfaa 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -1136,9 +1136,9 @@ do {
\
/* Store in OUTPUT a string (made with alloca) containing
an assembler-name for a local static variable named NAME.
LABELNO is an integer which is different for each call. */
-#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
-( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
- sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
+#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
+ ((OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
+ sprintf ((OUTPUT), "%s.%u", (NAME), (unsigned int)(LABELNO)))
/* The following macro defines the format used to output the second
operand of the .type assembler directive. Different svr4 assemblers
--
2.24.1
Re: [PATCH] [ARC] Allow more ABIs in GLIBC_DYNAMIC_LINKER
Pushed.
Thank you,
Claudiu
On Sun, Mar 29, 2020 at 2:05 AM Vineet Gupta via Gcc-patches
wrote:
>
> Enable big-endian suffixed dynamic linker per glibc multi-abi support.
>
> And to avoid a future churn and version pairingi hassles, also allow
> arc700 although glibc for ARC currently doesn't support it.
>
> gcc/
> -xx-xx Vineet Gupta
> +
> + * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700
>
> Signed-off-by: Vineet Gupta
> ---
> gcc/ChangeLog | 4
> gcc/config/arc/linux.h | 2 +-
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/ChangeLog b/gcc/ChangeLog
> index 86ad683a6cb0..c26a748fd51b 100644
> --- a/gcc/ChangeLog
> +++ b/gcc/ChangeLog
> @@ -1,3 +1,7 @@
> +2020-03-28 Vineet Gupta
> +
> + * config/arc/linux.h: GLIBC_DYNAMIC_LINKER support BE/arc700
> +
> 2020-03-28 Jakub Jelinek
>
> PR c/93573
> diff --git a/gcc/config/arc/linux.h b/gcc/config/arc/linux.h
> index 0b99da3fcdaf..1bbeccee7115 100644
> --- a/gcc/config/arc/linux.h
> +++ b/gcc/config/arc/linux.h
> @@ -29,7 +29,7 @@ along with GCC; see the file COPYING3. If not see
> } \
>while (0)
>
> -#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-arc.so.2"
> +#define GLIBC_DYNAMIC_LINKER
> "/lib/ld-linux-arc%{mbig-endian:eb}%{mcpu=arc700:700}.so.2"
> #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
>
> /* Note that the default is to link against dynamic libraries, if they are
> --
> 2.20.1
>
Re: [PATCH] [COMMITTED] arc: Add ARC entry for gcc-10/changes.html
It looks great I'll keep in mind this tip next time. Thank you, Clauidu From: Gerald Pfeifer Sent: Saturday, March 7, 2020 11:05 PM To: Claudiu Zissulescu ; Martin Sebor Cc: gcc-patches@gcc.gnu.org ; Jeff Law ; Francois Bedard ; Claudiu Zissulescu ; andrew.burg...@embecosm.com Subject: Re: [PATCH] [COMMITTED] arc: Add ARC entry for gcc-10/changes.html On Tue, 3 Mar 2020, Claudiu Zissulescu wrote: > Add ARC entry for gcc-10/changes.html What do you think of the following refinement to mark up mov and ior as code? Gerald PS: And thanks for your other feedback, Martin! diff --git a/htdocs/gcc-10/changes.html b/htdocs/gcc-10/changes.html index 710e3863..5ba388cf 100644 --- a/htdocs/gcc-10/changes.html +++ b/htdocs/gcc-10/changes.html @@ -562,9 +562,9 @@ a work-in-progress. The interrupt service routine functions save all used registers, including extension registers and auxiliary registers used by Zero Overhead Loops. - Improve code size by using multiple short instructions instead - of a single long mov or ior instruction when its long immediate - constant is known. + Improve code size by using multiple short instructions instead of + a single long mov or ior instruction when its + long immediate constant is known. Fix usage of the accumulator register for ARC600. Fix issues with uncached attribute. Remove -mq-class option.
[PATCH][committed] arc: Update tumaddsidi4 test.
The test is using -O1 and, the macu instruction is generated by the
combiner and not in the expand step. My previous "arc: Improve code
gen for 64bit add/sub operations." is actually splitting the 64-bit
add in the expand, leading to the impossibility to match the multiply
and accumulate on 64 bit datum by the combiner, hence, the error. This
patch is stepping up the optimization level which will generate the
macu instruction at the expand time.
xxxx-xx-xx Claudiu Zissulescu
* gcc.target/arc/tumaddsidi4.c: Step-up optimization level.
Signed-off-by: Claudiu Zissulescu
---
gcc/testsuite/ChangeLog| 4
gcc/testsuite/gcc.target/arc/tumaddsidi4.c | 4 ++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 13da5a8581d..ea9bc42ff75 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2020-03-06 Claudiu Zissulescu
+
+ * gcc.target/arc/tumaddsidi4.c: Step-up optimization level.
+
2020-03-06 Delia Burduv
* gcc.target/arm/simd/bf16_vldn_1.c: New test.
diff --git a/gcc/testsuite/gcc.target/arc/tumaddsidi4.c
b/gcc/testsuite/gcc.target/arc/tumaddsidi4.c
index d5dc2944d9b..0298a2456f5 100644
--- a/gcc/testsuite/gcc.target/arc/tumaddsidi4.c
+++ b/gcc/testsuite/gcc.target/arc/tumaddsidi4.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-mcpu=archs -O1 -mmpy-option=plus_dmpy -w" } */
+/* { dg-options "-mcpu=archs -O2 -mmpy-option=plus_dmpy -w" } */
/* Check how we generate umaddsidi4 patterns. */
long a;
@@ -11,4 +11,4 @@ void fn1(void)
b = d * (long long)c + a;
}
-/* { dg-final { scan-assembler "macu 0,r" } } */
+/* { dg-final { scan-assembler "macu" } } */
--
2.24.1
