Re: [PATCH] or1k: Do not clear existing FPU exceptions before updating
Hello,
I pushed this upstream.
On Sat, Mar 18, 2023 at 05:04:05PM +0900, Stafford Horne wrote:
> We should always carry the exceptions forward. This bug was found when
> working on testing glibc math tests, many tests were failing with
> Overflow and Underflow flags not set. This was traced to here.
>
> libgcc/ChangeLog:
>
> * config/or1k/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Remove
> statement clearing existing exceptions.
> ---
> libgcc/config/or1k/sfp-machine.h | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/libgcc/config/or1k/sfp-machine.h
> b/libgcc/config/or1k/sfp-machine.h
> index 162c6bc5326..c804270fb3c 100644
> --- a/libgcc/config/or1k/sfp-machine.h
> +++ b/libgcc/config/or1k/sfp-machine.h
> @@ -73,7 +73,6 @@ do {
> \
> do { \
>if (__builtin_expect (_fex, 0))\
> {\
> - _fpcsr &= ~FP_EX_ALL; \
>_fpcsr |= _fex;\
>__asm__ volatile ("l.mtspr r0,%0,20" : : "r" (_fpcsr));\
> }\
> --
> 2.39.1
>
[PATCH] or1k: Do not clear existing FPU exceptions before updating
We should always carry the exceptions forward. This bug was found when
working on testing glibc math tests, many tests were failing with
Overflow and Underflow flags not set. This was traced to here.
libgcc/ChangeLog:
* config/or1k/sfp-machine.h (FP_HANDLE_EXCEPTIONS): Remove
statement clearing existing exceptions.
---
libgcc/config/or1k/sfp-machine.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/libgcc/config/or1k/sfp-machine.h b/libgcc/config/or1k/sfp-machine.h
index 162c6bc5326..c804270fb3c 100644
--- a/libgcc/config/or1k/sfp-machine.h
+++ b/libgcc/config/or1k/sfp-machine.h
@@ -73,7 +73,6 @@ do {
\
do { \
if (__builtin_expect (_fex, 0)) \
{ \
- _fpcsr &= ~FP_EX_ALL;\
_fpcsr |= _fex; \
__asm__ volatile ("l.mtspr r0,%0,20" : : "r" (_fpcsr)); \
} \
--
2.39.1
Re: [PATCH] or1k: Only define TARGET_HAVE_TLS when HAVE_AS_TLS
On Thu, Sep 29, 2022 at 03:57:40PM +0100, Stafford Horne wrote: > This was found when testing buildroot with linuxthreads enabled. In > this case, the build passes --disable-tls to the toolchain during > configuration. After building the OpenRISC toolchain it was still > generating TLS code sequences and causing linker failures such as: > > /or1k-buildroot-linux-uclibc-gcc -o gpsd-3.24/gpsctl -lusb-1.0 -lm > -lrt -lnsl > /ld: /sysroot/usr/lib/libusb-1.0.so: undefined reference to > `__tls_get_addr' > > This patch fixes this by disabling tls for the OpenRISC target when requested > via --disable-tls. > > Tested-by: Yann E. MORIN > > gcc/ChangeLog: > > * config/or1k/or1k.cc (TARGET_HAVE_TLS): Only define if > HAVE_AS_TLS is defined. I have pushed this upstream now. Adding buildroot patches should be easy to do now. -Stafford
[PATCH] or1k: Only define TARGET_HAVE_TLS when HAVE_AS_TLS
This was found when testing buildroot with linuxthreads enabled. In this case, the build passes --disable-tls to the toolchain during configuration. After building the OpenRISC toolchain it was still generating TLS code sequences and causing linker failures such as: /or1k-buildroot-linux-uclibc-gcc -o gpsd-3.24/gpsctl -lusb-1.0 -lm -lrt -lnsl /ld: /sysroot/usr/lib/libusb-1.0.so: undefined reference to `__tls_get_addr' This patch fixes this by disabling tls for the OpenRISC target when requested via --disable-tls. Tested-by: Yann E. MORIN gcc/ChangeLog: * config/or1k/or1k.cc (TARGET_HAVE_TLS): Only define if HAVE_AS_TLS is defined. --- gcc/config/or1k/or1k.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/config/or1k/or1k.cc b/gcc/config/or1k/or1k.cc index da2f59062ba..0ce7b234417 100644 --- a/gcc/config/or1k/or1k.cc +++ b/gcc/config/or1k/or1k.cc @@ -2206,8 +2206,10 @@ or1k_output_mi_thunk (FILE *file, tree thunk_fndecl, #undef TARGET_LEGITIMATE_ADDRESS_P #define TARGET_LEGITIMATE_ADDRESS_P or1k_legitimate_address_p +#ifdef HAVE_AS_TLS #undef TARGET_HAVE_TLS #define TARGET_HAVE_TLS true +#endif #undef TARGET_HAVE_SPECULATION_SAFE_VALUE #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed -- 2.37.2
Re: [PATCH] or1k: Add support for a little-endian target variant
> diff --git a/gcc/config.gcc b/gcc/config.gcc
> index c5064dd37666..0c3a09dfe810 100644
> --- a/gcc/config.gcc
> +++ b/gcc/config.gcc
> @@ -2866,6 +2866,11 @@ or1k*-*-*)
> done
> TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's/^,//'`
>
> + case ${target} in
> + or1k*le*-*)
Should this be just or1kle*-*?
> + tm_defines="${tm_defines} TARGET_LITTLE_ENDIAN_DEFAULT=1"
> + ;;
> + esac
> case ${target} in
> or1k*-*-linux*)
> tm_file="${tm_file} gnu-user.h linux.h glibc-stdint.h"
> diff --git a/gcc/config/or1k/or1k.opt b/gcc/config/or1k/or1k.opt
> index 8a66832a99b1..497f259faae9 100644
> --- a/gcc/config/or1k/or1k.opt
> +++ b/gcc/config/or1k/or1k.opt
> @@ -24,6 +24,14 @@
> HeaderInclude
> config/or1k/or1k-opts.h
>
> +mbig-endian
> +Target Report RejectNegative Mask(BIG_ENDIAN)
> +Use big-endian byte order.
> +
> +mlittle-endian
> +Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN)
> +Use little-endian byte order.
> +
We should explain what is the default int he doc's.
Can you also document in: gcc/doc/invoke.texi
This looks good, thank you.
-Stafford
[PATCH] gcc: define _REENTRANT for OpenRISC when -pthread is passed
From: Bernd Kuhls
The detection of pthread support fails on OpenRISC unless _REENTRANT
is defined. Added the CPP_SPEC definition to correct this.
gcc/ChangeLog:
PR target/94372
* config/or1k/linux.h (CPP_SPEC): Define.
Signed-off-by: Bernd Kuhls
---
This was brought up on the buildroot list and somehow I missed it. Sending it
now. I plan to commit soon.
gcc/config/or1k/linux.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/config/or1k/linux.h b/gcc/config/or1k/linux.h
index 52909af41a6..80f77c72232 100644
--- a/gcc/config/or1k/linux.h
+++ b/gcc/config/or1k/linux.h
@@ -32,6 +32,8 @@
#undef MUSL_DYNAMIC_LINKER
#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-or1k.so.1"
+#define CPP_SPEC "%{pthread:-D_REENTRANT}"
+
#undef LINK_SPEC
#define LINK_SPEC "%{h*} \
%{static:-Bstatic} \
--
2.31.1
Re: [RFC PATCH] or1k: Fix clobbering of _mcount argument if fPIC is enabled
I have committed this as is.
-Stafford
On Tue, Nov 09, 2021 at 09:13:08PM +0900, Stafford Horne wrote:
> Recently we changed the PROFILE_HOOK _mcount call to pass in the link
> register as an argument. This actually does not work when the _mcount
> call uses a PLT because the GOT register setup code ends up getting
> inserted before the PROFILE_HOOK and clobbers the link register
> argument.
>
> These glibc tests are failing:
> gmon/tst-gmon-pie-gprof
> gmon/tst-gmon-static-gprof
>
> This patch fixes this by saving the instruction that stores the Link
> Register to the _mcount argument and then inserts the GOT register setup
> instructions after that.
>
> For example:
>
> main.c:
>
> extern int e;
>
> int f2(int a) {
> return a + e;
> }
>
> int f1(int a) {
> return f2 (a + a);
> }
>
> int main(int argc, char ** argv) {
> return f1 (argc);
> }
>
> Compiled:
>
> or1k-smh-linux-gnu-gcc -Wall -c -O2 -fPIC -pg -S main.c
>
> Before Fix:
>
> main:
> l.addi r1, r1, -16
> l.sw8(r1), r2
> l.sw0(r1), r16
> l.addi r2, r1, 16 # Keeping FP, but not needed
> l.sw4(r1), r18
> l.sw12(r1), r9
> l.jal 8# GOT Setup clobbers r9 (Link Register)
> l.movhir16, gotpchi(_GLOBAL_OFFSET_TABLE_-4)
> l.ori r16, r16, gotpclo(_GLOBAL_OFFSET_TABLE_+0)
> l.add r16, r16, r9
> l.orr18, r3, r3
> l.orr3, r9, r9# This is not the original LR
> l.jal plt(_mcount)
> l.nop
>
> l.jal plt(f1)
> l.orr3, r18, r18
> l.lwz r9, 12(r1)
> l.lwz r16, 0(r1)
> l.lwz r18, 4(r1)
> l.lwz r2, 8(r1)
> l.jrr9
> l.addi r1, r1, 16
>
> After the fix:
>
> main:
> l.addi r1, r1, -12
> l.sw0(r1), r16
> l.sw4(r1), r18
> l.sw8(r1), r9
> l.orr18, r3, r3
> l.orr3, r9, r9# We now have r9 (LR) set early
> l.jal 8 # Clobbers r9 (Link Register)
> l.movhir16, gotpchi(_GLOBAL_OFFSET_TABLE_-4)
> l.ori r16, r16, gotpclo(_GLOBAL_OFFSET_TABLE_+0)
> l.add r16, r16, r9
> l.jal plt(_mcount)
> l.nop
>
> l.jal plt(f1)
> l.orr3, r18, r18
> l.lwz r9, 8(r1)
> l.lwz r16, 0(r1)
> l.lwz r18, 4(r1)
> l.jrr9
> l.addi r1, r1, 12
>
> Fixes: 308531d148a ("or1k: Add return address argument to _mcount call")
>
> gcc/ChangeLog:
> * config/or1k/or1k-protos.h (or1k_profile_hook): New function.
> * config/or1k/or1k.h (PROFILE_HOOK): Change macro to reference
> new function or1k_profile_hook.
> * config/or1k/or1k.c (struct machine_function): Add new field
> set_mcount_arg_insn.
> (or1k_profile_hook): New function.
> (or1k_init_pic_reg): Update to inject pic rtx after _mcount arg
> when profiling.
> (or1k_frame_pointer_required): Frame pointer no longer needed
> when profiling.
> ---
> I am sending this as RFC as I think there should be a better way to handle
> this but I am not sure how that would be.
>
> An earlier patch I tried was to store the link register to a temporary
> register
> then pass the temporary register as an argument to _mcount, however
> optimizations caused the link register to still get clobbered.
>
> Any thoughts will be helpful.
>
> -Stafford
>
> gcc/config/or1k/or1k-protos.h | 1 +
> gcc/config/or1k/or1k.c| 49 ---
> gcc/config/or1k/or1k.h| 8 +-
> 3 files changed, 42 insertions(+), 16 deletions(-)
>
> diff --git a/gcc/config/or1k/or1k-protos.h b/gcc/config/or1k/or1k-protos.h
> index bbb54c8f790..56554f2937f 100644
> --- a/gcc/config/or1k/or1k-protos.h
> +++ b/gcc/config/or1k/or1k-protos.h
> @@ -20,6 +20,7 @@ along with GCC; see the file COPYING3. If not see
> extern HOST_WIDE_INT or1k_initial_elimination_offset (int, int);
> extern void or1k_expand_prologue (void);
> extern void or1k_expand_epilogue (void);
> +extern void or1k_profile_hook (void);
> extern void or1k_expand_eh_return (rtx);
> extern rtx or1k_initial_frame_addr (void);
> extern rtx or1k_dynamic_chain_addr (rtx);
> diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c
> index e772a7addea..335c4c5decf 100644
> --- a/gcc/config/or1k/or1k.c
> +++ b/gcc/config/or1k/or1k.c
> @@ -73,6 +73,10 @@ struct GTY(()) mac
[RFC PATCH] or1k: Fix clobbering of _mcount argument if fPIC is enabled
Recently we changed the PROFILE_HOOK _mcount call to pass in the link
register as an argument. This actually does not work when the _mcount
call uses a PLT because the GOT register setup code ends up getting
inserted before the PROFILE_HOOK and clobbers the link register
argument.
These glibc tests are failing:
gmon/tst-gmon-pie-gprof
gmon/tst-gmon-static-gprof
This patch fixes this by saving the instruction that stores the Link
Register to the _mcount argument and then inserts the GOT register setup
instructions after that.
For example:
main.c:
extern int e;
int f2(int a) {
return a + e;
}
int f1(int a) {
return f2 (a + a);
}
int main(int argc, char ** argv) {
return f1 (argc);
}
Compiled:
or1k-smh-linux-gnu-gcc -Wall -c -O2 -fPIC -pg -S main.c
Before Fix:
main:
l.addi r1, r1, -16
l.sw8(r1), r2
l.sw0(r1), r16
l.addi r2, r1, 16 # Keeping FP, but not needed
l.sw4(r1), r18
l.sw12(r1), r9
l.jal 8# GOT Setup clobbers r9 (Link Register)
l.movhir16, gotpchi(_GLOBAL_OFFSET_TABLE_-4)
l.ori r16, r16, gotpclo(_GLOBAL_OFFSET_TABLE_+0)
l.add r16, r16, r9
l.orr18, r3, r3
l.orr3, r9, r9# This is not the original LR
l.jal plt(_mcount)
l.nop
l.jal plt(f1)
l.orr3, r18, r18
l.lwz r9, 12(r1)
l.lwz r16, 0(r1)
l.lwz r18, 4(r1)
l.lwz r2, 8(r1)
l.jrr9
l.addi r1, r1, 16
After the fix:
main:
l.addi r1, r1, -12
l.sw0(r1), r16
l.sw4(r1), r18
l.sw8(r1), r9
l.orr18, r3, r3
l.orr3, r9, r9# We now have r9 (LR) set early
l.jal 8 # Clobbers r9 (Link Register)
l.movhir16, gotpchi(_GLOBAL_OFFSET_TABLE_-4)
l.ori r16, r16, gotpclo(_GLOBAL_OFFSET_TABLE_+0)
l.add r16, r16, r9
l.jal plt(_mcount)
l.nop
l.jal plt(f1)
l.orr3, r18, r18
l.lwz r9, 8(r1)
l.lwz r16, 0(r1)
l.lwz r18, 4(r1)
l.jrr9
l.addi r1, r1, 12
Fixes: 308531d148a ("or1k: Add return address argument to _mcount call")
gcc/ChangeLog:
* config/or1k/or1k-protos.h (or1k_profile_hook): New function.
* config/or1k/or1k.h (PROFILE_HOOK): Change macro to reference
new function or1k_profile_hook.
* config/or1k/or1k.c (struct machine_function): Add new field
set_mcount_arg_insn.
(or1k_profile_hook): New function.
(or1k_init_pic_reg): Update to inject pic rtx after _mcount arg
when profiling.
(or1k_frame_pointer_required): Frame pointer no longer needed
when profiling.
---
I am sending this as RFC as I think there should be a better way to handle
this but I am not sure how that would be.
An earlier patch I tried was to store the link register to a temporary register
then pass the temporary register as an argument to _mcount, however
optimizations caused the link register to still get clobbered.
Any thoughts will be helpful.
-Stafford
gcc/config/or1k/or1k-protos.h | 1 +
gcc/config/or1k/or1k.c| 49 ---
gcc/config/or1k/or1k.h| 8 +-
3 files changed, 42 insertions(+), 16 deletions(-)
diff --git a/gcc/config/or1k/or1k-protos.h b/gcc/config/or1k/or1k-protos.h
index bbb54c8f790..56554f2937f 100644
--- a/gcc/config/or1k/or1k-protos.h
+++ b/gcc/config/or1k/or1k-protos.h
@@ -20,6 +20,7 @@ along with GCC; see the file COPYING3. If not see
extern HOST_WIDE_INT or1k_initial_elimination_offset (int, int);
extern void or1k_expand_prologue (void);
extern void or1k_expand_epilogue (void);
+extern void or1k_profile_hook (void);
extern void or1k_expand_eh_return (rtx);
extern rtx or1k_initial_frame_addr (void);
extern rtx or1k_dynamic_chain_addr (rtx);
diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c
index e772a7addea..335c4c5decf 100644
--- a/gcc/config/or1k/or1k.c
+++ b/gcc/config/or1k/or1k.c
@@ -73,6 +73,10 @@ struct GTY(()) machine_function
/* Remember where the set_got_placeholder is located. */
rtx_insn *set_got_insn;
+
+ /* Remember where mcount args are stored so we can insert set_got_insn
+ after. */
+ rtx_insn *set_mcount_arg_insn;
};
/* Zero initialization is OK for all current fields. */
@@ -415,6 +419,25 @@ or1k_expand_epilogue (void)
EH_RETURN_STACKADJ_RTX));
}
+/* Worker for PROFILE_HOOK.
+ The OpenRISC profile hook uses the link register which will get clobbered by
+ the GOT setup RTX. This sets up a placeholder to allow injecting of the GOT
+ setup RTX to avoid clobbering. */
+
+void
+or1k_profile_hook (void)
+{
+ rtx a1 = gen_rtx_REG (Pmode, 3);
+ rtx ra = get_hard_reg_initial_val (Pmode, LR_REGNUM);
+ rtx fun =
[PATCH] or1k: Add return address argument to _mcount call
This fixes an issue in the glibc port I am working on where the build
fails due to the warning:
error: calling ‘__builtin_return_address’ with a nonzero argument is unsafe
[-Werror=frame-address]
This is due to how the current implementation of _mcount in glibc uses
__builtin_return_address with a count argument of 1.
Fix that by passing the value of LR_REGNUM to the _mcount function,
effectivtly providing the value _mcount is after.
This is an ABI change, but I think it's OK because the glibc port for
or1k is not yet upstreamed. Also, I think just adding an argument
should not break anything anyway.
gcc/ChangeLog:
* config/or1k/or1k.h (PROFILE_HOOK): Add return address argument
to _mcount.
---
gcc/config/or1k/or1k.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
index fe01ab81ead..4603cb67160 100644
--- a/gcc/config/or1k/or1k.h
+++ b/gcc/config/or1k/or1k.h
@@ -387,9 +387,10 @@ do {\
profiling a function entry. */
#define PROFILE_HOOK(LABEL)\
{\
-rtx fun; \
+rtx fun, ra; \
+ra = get_hard_reg_initial_val (Pmode, LR_REGNUM); \
fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); \
-emit_library_call (fun, LCT_NORMAL, VOIDmode); \
+emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode); \
}
/* All the work is done in PROFILE_HOOK, but this is still required. */
--
2.31.1
[PATCH] or1k: Update FPU to specify detect tininess before rounding
This was not defined in the spec and not consistent in the
implementation causing incosistent behavior. After review we have
updated the CPU implementations and proposed the spec be updated to
specific that FPU tininess checks check for tininess before roudning.
Architecture change draft:
https://openrisc.io/proposals/p18-fpu-tininess
libgcc/ChangeLog:
* config/or1k/sfp-machine.h (_FP_TININESS_AFTER_ROUNDING):
Change to 0.
---
libgcc/config/or1k/sfp-machine.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/libgcc/config/or1k/sfp-machine.h b/libgcc/config/or1k/sfp-machine.h
index eebe5b0578e..162c6bc5326 100644
--- a/libgcc/config/or1k/sfp-machine.h
+++ b/libgcc/config/or1k/sfp-machine.h
@@ -85,7 +85,7 @@ do {
\
#define __BYTE_ORDER __BIG_ENDIAN
-#define _FP_TININESS_AFTER_ROUNDING 1
+#define _FP_TININESS_AFTER_ROUNDING 0
/* Define ALIASNAME as a strong alias for NAME. */
# define strong_alias(name, aliasname) _strong_alias(name, aliasname)
--
2.31.1
Re: [PATCH v2 0/2] OpenRISC support for cmodel=large
On Sun, Aug 15, 2021 at 12:05:37AM +0200, Giulio Benetti wrote: > On 8/15/21 12:03 AM, Stafford Horne wrote: > > On Sat, Aug 14, 2021 at 11:01:16PM +0200, Giulio Benetti wrote: > > > Hi All, > > > > > > On 5/1/21 11:11 PM, Stafford Horne wrote: > > > > Changes from v1: > > > >- Added patch to enabled cmodle=large on crtstuff > > > > > > > > This series fixes some bugs found when linking large binaries, both in > > > > buildroot > > > > and glibc testing. > > > > > > > > Stafford Horne (2): > > > > or1k: Add mcmodel option to handle large GOTs > > > > or1k: Use cmodel=large when building crtstuff > > > > > > > >gcc/config/or1k/or1k-opts.h | 30 ++ > > > >gcc/config/or1k/or1k.c| 11 +-- > > > >gcc/config/or1k/or1k.h| 7 +++ > > > >gcc/config/or1k/or1k.opt | 19 +++ > > > >gcc/doc/invoke.texi | 12 +++- > > > >libgcc/config.host| 4 ++-- > > > >libgcc/config/or1k/t-crtstuff | 2 ++ > > > >7 files changed, 80 insertions(+), 5 deletions(-) > > > >create mode 100644 gcc/config/or1k/or1k-opts.h > > > >create mode 100644 libgcc/config/or1k/t-crtstuff > > > > > > > > > > I've tested this patchset and works as expected. > > > It fixed libgeos build failure in conjunction with: > > > https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=3c3de29b048bca6b4aa4235c647b9328e71801b6 > > > > > > Hope this helps to commit it upstream since I still don't see it, or am I > > > wrong? > > > > You are not wrong, I did not push the changed to GCC yet. I will do soon. > > Ah ok, you're the maintainer :-) I thought there was someone else who needed > to push it :-) Yeah, I pushed it now.
Re: [PATCH v2 0/2] OpenRISC support for cmodel=large
On Sat, Aug 14, 2021 at 11:01:16PM +0200, Giulio Benetti wrote: > Hi All, > > On 5/1/21 11:11 PM, Stafford Horne wrote: > > Changes from v1: > > - Added patch to enabled cmodle=large on crtstuff > > > > This series fixes some bugs found when linking large binaries, both in > > buildroot > > and glibc testing. > > > > Stafford Horne (2): > >or1k: Add mcmodel option to handle large GOTs > >or1k: Use cmodel=large when building crtstuff > > > > gcc/config/or1k/or1k-opts.h | 30 ++ > > gcc/config/or1k/or1k.c| 11 +-- > > gcc/config/or1k/or1k.h| 7 +++ > > gcc/config/or1k/or1k.opt | 19 +++ > > gcc/doc/invoke.texi | 12 +++- > > libgcc/config.host| 4 ++-- > > libgcc/config/or1k/t-crtstuff | 2 ++ > > 7 files changed, 80 insertions(+), 5 deletions(-) > > create mode 100644 gcc/config/or1k/or1k-opts.h > > create mode 100644 libgcc/config/or1k/t-crtstuff > > > > I've tested this patchset and works as expected. > It fixed libgeos build failure in conjunction with: > https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=3c3de29b048bca6b4aa4235c647b9328e71801b6 > > Hope this helps to commit it upstream since I still don't see it, or am I > wrong? You are not wrong, I did not push the changed to GCC yet. I will do soon. -Stafford
Re: [PATCH v2 0/2] OpenRISC support for cmodel=large
On Mon, May 03, 2021 at 12:34:22PM +0200, Giulio Benetti wrote: > Hi Stafford, All, > > I've backported this patchset for Buildroot to versions: > - 9.3.0 > - 10.3.0 > > Does it make sense to send them? I don't know if those version will have > minor versions where these backported patches can be applied. Do you mean for me/you to send the backported GCC patches for GCC or buildroot? I don't need backported versions of the toolchains and usually work off the latest release/master. If someone wants them let me know. -Stafford > Best regards > -- > Giulio Benetti > Benetti Engineering sas > > On 5/1/21 11:11 PM, Stafford Horne wrote: > > Changes from v1: > > - Added patch to enabled cmodle=large on crtstuff > > > > This series fixes some bugs found when linking large binaries, both in > > buildroot > > and glibc testing. > > > > Stafford Horne (2): > >or1k: Add mcmodel option to handle large GOTs > >or1k: Use cmodel=large when building crtstuff > > > > gcc/config/or1k/or1k-opts.h | 30 ++ > > gcc/config/or1k/or1k.c| 11 +-- > > gcc/config/or1k/or1k.h| 7 +++ > > gcc/config/or1k/or1k.opt | 19 +++ > > gcc/doc/invoke.texi | 12 +++- > > libgcc/config.host| 4 ++-- > > libgcc/config/or1k/t-crtstuff | 2 ++ > > 7 files changed, 80 insertions(+), 5 deletions(-) > > create mode 100644 gcc/config/or1k/or1k-opts.h > > create mode 100644 libgcc/config/or1k/t-crtstuff > >
[PATCH v2 2/2] or1k: Use cmodel=large when building crtstuff
When linking gcc runtime objects into large binaries the link may fail with the below errors. This will happen even if we are building with -mcmodel=large. /home/shorne/work/openrisc/output/host/lib/gcc/or1k-buildroot-linux-uclibc/10.3.0/crtbeginS.o: in function `deregister_tm_clones': crtstuff.c:(.text+0x3c): relocation truncated to fit: R_OR1K_GOT16 against undefined symbol `_ITM_deregisterTMCloneTable' /home/shorne/work/openrisc/output/host/lib/gcc/or1k-buildroot-linux-uclibc/10.3.0/crtbeginS.o: in function `register_tm_clones': crtstuff.c:(.text+0xc0): relocation truncated to fit: R_OR1K_GOT16 against undefined symbol `_ITM_registerTMCloneTable' This patch builds the gcc crtstuff binaries always with the -mcmodel=large option to ensure they can be linked into large binaries. libgcc/ChangeLog: PR 99783 * config.host (or1k-*, tmake_file): Add or1k/t-crtstuff. * config/or1k/t-crtstuff: New file. --- libgcc/config.host| 4 ++-- libgcc/config/or1k/t-crtstuff | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-) create mode 100644 libgcc/config/or1k/t-crtstuff diff --git a/libgcc/config.host b/libgcc/config.host index f808b61be70..9e40d4560a3 100644 --- a/libgcc/config.host +++ b/libgcc/config.host @@ -1119,12 +1119,12 @@ nios2-*-*) extra_parts="$extra_parts crti.o crtn.o" ;; or1k-*-linux*) - tmake_file="$tmake_file or1k/t-or1k" + tmake_file="$tmake_file or1k/t-or1k or1k/t-crtstuff" tmake_file="$tmake_file t-softfp-sfdf t-softfp" md_unwind_header=or1k/linux-unwind.h ;; or1k-*-*) - tmake_file="$tmake_file or1k/t-or1k" + tmake_file="$tmake_file or1k/t-or1k or1k/t-crtstuff" tmake_file="$tmake_file t-softfp-sfdf t-softfp" ;; pdp11-*-*) diff --git a/libgcc/config/or1k/t-crtstuff b/libgcc/config/or1k/t-crtstuff new file mode 100644 index 000..dcae7f3498e --- /dev/null +++ b/libgcc/config/or1k/t-crtstuff @@ -0,0 +1,2 @@ +# Compile crtbeginS.o and crtendS.o with -mcmodel=large +CRTSTUFF_T_CFLAGS_S += -mcmodel=large -- 2.26.2
[PATCH v2 1/2] or1k: Add mcmodel option to handle large GOTs
When building libgeos we get an error with:
linux-uclibc/9.3.0/crtbeginS.o: in function `__do_global_dtors_aux':
crtstuff.c:(.text+0x118): relocation truncated to fit: R_OR1K_GOT16 against
symbol `__cxa_finalize' defined in .text section in
/home/shorne/work/openrisc/3eb9f9d0f6d8274b2d19753c006bd83f7d536e3c/output/host/or1k-buildroot-linux-uclibc/sysroot/lib/libc.so.
This is caused by GOT code having a limit of 64k. In OpenRISC this
looks to be the only relocation code pattern to be limited to 64k.
This patch allows specifying a new option -mcmodel=large which can be
used to generate 2 more instructions to construct 32-bit addresses for
up to 4G GOTs.
gcc/ChangeLog:
PR 99783
* config/or1k/or1k-opts.h: New file.
* config/or1k/or1k.c (or1k_legitimize_address_1, print_reloc):
Support generating gotha relocations if -mcmodel=large is
specified.
* config/or1k/or1k.h (TARGET_CMODEL_SMALL, TARGET_CMODEL_LARGE):
New macros.
* config/or1k/or1k.opt (mcmodel=): New option.
* doc/invoke.text (OpenRISC Options): Document mcmodel.
---
gcc/config/or1k/or1k-opts.h | 30 ++
gcc/config/or1k/or1k.c | 11 +--
gcc/config/or1k/or1k.h | 7 +++
gcc/config/or1k/or1k.opt| 19 +++
gcc/doc/invoke.texi | 12 +++-
5 files changed, 76 insertions(+), 3 deletions(-)
create mode 100644 gcc/config/or1k/or1k-opts.h
diff --git a/gcc/config/or1k/or1k-opts.h b/gcc/config/or1k/or1k-opts.h
new file mode 100644
index 000..f791b894fdd
--- /dev/null
+++ b/gcc/config/or1k/or1k-opts.h
@@ -0,0 +1,30 @@
+/* Definitions for option handling for OpenRISC.
+ Copyright (C) 2021 Free Software Foundation, Inc.
+ Contributed by Stafford Horne.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef GCC_OR1K_OPTS_H
+#define GCC_OR1K_OPTS_H
+
+/* The OpenRISC code generation models available. */
+enum or1k_cmodel_type {
+ CMODEL_SMALL,
+ CMODEL_LARGE
+};
+
+#endif /* GCC_OR1K_OPTS_H */
diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c
index e772a7addea..27d3fa17995 100644
--- a/gcc/config/or1k/or1k.c
+++ b/gcc/config/or1k/or1k.c
@@ -750,7 +750,14 @@ or1k_legitimize_address_1 (rtx x, rtx scratch)
{
base = gen_sym_unspec (base, UNSPEC_GOT);
crtl->uses_pic_offset_table = 1;
- t2 = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, base);
+ if (TARGET_CMODEL_LARGE)
+ {
+ emit_insn (gen_rtx_SET (t1, gen_rtx_HIGH (Pmode, base)));
+ emit_insn (gen_add3_insn (t1, t1, pic_offset_table_rtx));
+ t2 = gen_rtx_LO_SUM (Pmode, t1, base);
+ }
+ else
+ t2 = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, base);
t2 = gen_const_mem (Pmode, t2);
emit_insn (gen_rtx_SET (t1, t2));
base = t1;
@@ -1089,7 +1096,7 @@ print_reloc (FILE *stream, rtx x, HOST_WIDE_INT add,
reloc_kind kind)
no special markup. */
static const char * const relocs[RKIND_MAX][RTYPE_MAX] = {
{ "lo", "got", "gotofflo", "tpofflo", "gottpofflo", "tlsgdlo" },
-{ "ha", NULL, "gotoffha", "tpoffha", "gottpoffha", "tlsgdhi" },
+{ "ha", "gotha", "gotoffha", "tpoffha", "gottpoffha", "tlsgdhi" },
};
reloc_type type = RTYPE_DIRECT;
diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
index fe01ab81ead..669907e7e74 100644
--- a/gcc/config/or1k/or1k.h
+++ b/gcc/config/or1k/or1k.h
@@ -21,6 +21,8 @@
#ifndef GCC_OR1K_H
#define GCC_OR1K_H
+#include "config/or1k/or1k-opts.h"
+
/* Names to predefine in the preprocessor for this target machine. */
#define TARGET_CPU_CPP_BUILTINS() \
do \
@@ -37,6 +39,11 @@
} \
while (0)
+#define TARGET_CMODEL_SMALL \
+ (or1k_code_model == CMODEL_SMALL)
+#define TARGET_CMODEL_LARGE \
+ (or1k_code_model == CMODEL_LARGE)
+
/* Storage layout. */
#define DEFAULT_SIGNED_CHAR 1
diff --git a/gcc/config/or1k/or1k.opt b/gcc/config/or1k/or
[PATCH v2 0/2] OpenRISC support for cmodel=large
Changes from v1: - Added patch to enabled cmodle=large on crtstuff This series fixes some bugs found when linking large binaries, both in buildroot and glibc testing. Stafford Horne (2): or1k: Add mcmodel option to handle large GOTs or1k: Use cmodel=large when building crtstuff gcc/config/or1k/or1k-opts.h | 30 ++ gcc/config/or1k/or1k.c| 11 +-- gcc/config/or1k/or1k.h| 7 +++ gcc/config/or1k/or1k.opt | 19 +++ gcc/doc/invoke.texi | 12 +++- libgcc/config.host| 4 ++-- libgcc/config/or1k/t-crtstuff | 2 ++ 7 files changed, 80 insertions(+), 5 deletions(-) create mode 100644 gcc/config/or1k/or1k-opts.h create mode 100644 libgcc/config/or1k/t-crtstuff -- 2.26.2
Re: [PATCH] or1k: Add mcmodel option to handle large GOTs
On Tue, Apr 20, 2021 at 05:20:39PM -0600, Jeff Law wrote: > > On 4/18/2021 6:10 PM, Stafford Horne via Gcc-patches wrote: > > When building libgeos we get an error with: > > > > linux-uclibc/9.3.0/crtbeginS.o: in function `__do_global_dtors_aux': > > crtstuff.c:(.text+0x118): relocation truncated to fit: R_OR1K_GOT16 > > against symbol `__cxa_finalize' defined in .text section in > > > > /home/shorne/work/openrisc/3eb9f9d0f6d8274b2d19753c006bd83f7d536e3c/output/host/or1k-buildroot-linux-uclibc/sysroot/lib/libc.so. > > > > This is caused by GOT code having a limit of 64k. In OpenRISC this > > looks to be the only relocation code pattern to be limited to 64k. > > > > This patch allows specifying a new option -mcmodel=large which can be > > used to generate 2 more instructions to construct 32-bit addresses for > > up to 4G GOTs. > > > > gcc/ChangeLog: > > > > PR 99783 > > * config/or1k/or1k-opts.h: New file. > > * config/or1k/or1k.c (or1k_legitimize_address_1, print_reloc): > > Support generating gotha relocations if -mcmodel=large is > > specified. > > * config/or1k/or1k.h (TARGET_CMODEL_SMALL, TARGET_CMODEL_LARGE): > > New macros. > > * config/or1k/or1k.opt (mcmodel=): New option. > > * doc/invoke.text (OpenRISC Options): Document mcmodel. > > Note you're the port maintainer, so you don't need approval to commit this > to GCC. Thanks for confirming, I know that after Segher told me with some previous patches. :) For this series Giulio picked it up and tested it. We found some issues and I am going to fix with a V2. I should commit that version, after the binutils changes are in. -Stafford
[PATCH] or1k: Add mcmodel option to handle large GOTs
When building libgeos we get an error with:
linux-uclibc/9.3.0/crtbeginS.o: in function `__do_global_dtors_aux':
crtstuff.c:(.text+0x118): relocation truncated to fit: R_OR1K_GOT16 against
symbol `__cxa_finalize' defined in .text section in
/home/shorne/work/openrisc/3eb9f9d0f6d8274b2d19753c006bd83f7d536e3c/output/host/or1k-buildroot-linux-uclibc/sysroot/lib/libc.so.
This is caused by GOT code having a limit of 64k. In OpenRISC this
looks to be the only relocation code pattern to be limited to 64k.
This patch allows specifying a new option -mcmodel=large which can be
used to generate 2 more instructions to construct 32-bit addresses for
up to 4G GOTs.
gcc/ChangeLog:
PR 99783
* config/or1k/or1k-opts.h: New file.
* config/or1k/or1k.c (or1k_legitimize_address_1, print_reloc):
Support generating gotha relocations if -mcmodel=large is
specified.
* config/or1k/or1k.h (TARGET_CMODEL_SMALL, TARGET_CMODEL_LARGE):
New macros.
* config/or1k/or1k.opt (mcmodel=): New option.
* doc/invoke.text (OpenRISC Options): Document mcmodel.
---
This depends on the binutils-gdb patch sent here:
- https://sourceware.org/pipermail/binutils/2021-April/116155.html
gcc/config/or1k/or1k-opts.h | 30 ++
gcc/config/or1k/or1k.c | 11 +--
gcc/config/or1k/or1k.h | 7 +++
gcc/config/or1k/or1k.opt| 19 +++
gcc/doc/invoke.texi | 12 +++-
5 files changed, 76 insertions(+), 3 deletions(-)
create mode 100644 gcc/config/or1k/or1k-opts.h
diff --git a/gcc/config/or1k/or1k-opts.h b/gcc/config/or1k/or1k-opts.h
new file mode 100644
index 000..f791b894fdd
--- /dev/null
+++ b/gcc/config/or1k/or1k-opts.h
@@ -0,0 +1,30 @@
+/* Definitions for option handling for OpenRISC.
+ Copyright (C) 2021 Free Software Foundation, Inc.
+ Contributed by Stafford Horne.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef GCC_OR1K_OPTS_H
+#define GCC_OR1K_OPTS_H
+
+/* The OpenRISC code generation models available. */
+enum or1k_cmodel_type {
+ CMODEL_SMALL,
+ CMODEL_LARGE
+};
+
+#endif /* GCC_OR1K_OPTS_H */
diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c
index e772a7addea..27d3fa17995 100644
--- a/gcc/config/or1k/or1k.c
+++ b/gcc/config/or1k/or1k.c
@@ -750,7 +750,14 @@ or1k_legitimize_address_1 (rtx x, rtx scratch)
{
base = gen_sym_unspec (base, UNSPEC_GOT);
crtl->uses_pic_offset_table = 1;
- t2 = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, base);
+ if (TARGET_CMODEL_LARGE)
+ {
+ emit_insn (gen_rtx_SET (t1, gen_rtx_HIGH (Pmode, base)));
+ emit_insn (gen_add3_insn (t1, t1, pic_offset_table_rtx));
+ t2 = gen_rtx_LO_SUM (Pmode, t1, base);
+ }
+ else
+ t2 = gen_rtx_LO_SUM (Pmode, pic_offset_table_rtx, base);
t2 = gen_const_mem (Pmode, t2);
emit_insn (gen_rtx_SET (t1, t2));
base = t1;
@@ -1089,7 +1096,7 @@ print_reloc (FILE *stream, rtx x, HOST_WIDE_INT add,
reloc_kind kind)
no special markup. */
static const char * const relocs[RKIND_MAX][RTYPE_MAX] = {
{ "lo", "got", "gotofflo", "tpofflo", "gottpofflo", "tlsgdlo" },
-{ "ha", NULL, "gotoffha", "tpoffha", "gottpoffha", "tlsgdhi" },
+{ "ha", "gotha", "gotoffha", "tpoffha", "gottpoffha", "tlsgdhi" },
};
reloc_type type = RTYPE_DIRECT;
diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
index fe01ab81ead..669907e7e74 100644
--- a/gcc/config/or1k/or1k.h
+++ b/gcc/config/or1k/or1k.h
@@ -21,6 +21,8 @@
#ifndef GCC_OR1K_H
#define GCC_OR1K_H
+#include "config/or1k/or1k-opts.h"
+
/* Names to predefine in the preprocessor for this target machine. */
#define TARGET_CPU_CPP_BUILTINS() \
do \
@@ -37,6 +39,11 @@
} \
while (0)
+#define TARGET_CMODEL_SMALL \
+ (or1k_code_model == CMODEL_SMALL)
+#define TARGET_CMODEL_LARGE \
+ (or1k_code_model == CMODEL_LARGE)
+
[PATCH v2 5/5] or1k: Fixup exception header data encodings
While running glibc tests several *-textrel tests failed showing that
relocations remained against read only sections. It turned out this was
related to exception headers data encoding being wrong.
By default pointer encoding will always use the DW_EH_PE_absptr format.
This patch uses format DW_EH_PE_pcrel and DW_EH_PE_sdata4. Optionally
DW_EH_PE_indirect is included for global symbols. This eliminates the
relocations.
gcc/ChangeLog:
* config/or1k/or1k.h (ASM_PREFERRED_EH_DATA_FORMAT): New macro.
---
gcc/config/or1k/or1k.h | 4
1 file changed, 4 insertions(+)
diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
index b686f1bd159..fe01ab81ead 100644
--- a/gcc/config/or1k/or1k.h
+++ b/gcc/config/or1k/or1k.h
@@ -408,4 +408,8 @@ do {\
((N) < 4 ? HW_TO_GCC_REGNO (25) + (N) : INVALID_REGNUM)
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM)
+/* Select a format to encode pointers in exception handling data. */
+#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
+ (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
+
#endif /* GCC_OR1K_H */
--
2.26.2
[PATCH v2 4/5] or1k: Add note to indicate execstack
Define TARGET_ASM_FILE_END as file_end_indicate_exec_stack to allow
generation of the ".note.GNU-stack" section note. This allows binutils
to properly set PT_GNU_STACK in the program header.
This fixes a glibc execstack testsuite test failure found while working
on the OpenRISC glibc port.
gcc/ChangeLog:
* config/or1k/linux.h (TARGET_ASM_FILE_END): Define macro.
---
gcc/config/or1k/linux.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/config/or1k/linux.h b/gcc/config/or1k/linux.h
index 74fbe082103..196f3f3c8f0 100644
--- a/gcc/config/or1k/linux.h
+++ b/gcc/config/or1k/linux.h
@@ -42,4 +42,6 @@
%{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}} \
%{static-pie:-Bstatic -pie --no-dynamic-linker -z text}"
+#define TARGET_ASM_FILE_END file_end_indicate_exec_stack
+
#endif /* GCC_OR1K_LINUX_H */
--
2.26.2
[PATCH v2 3/5] or1k: Support for softfloat to emulate hw exceptions
This allows the openrisc softfloat implementation to set exceptions.
This also sets the correct tininess after rounding value to be
consistent with hardware and simulator implementations.
libgcc/ChangeLog:
* config/or1k/sfp-machine.h (FP_RND_NEAREST, FP_RND_ZERO,
FP_RND_PINF, FP_RND_MINF, FP_RND_MASK, FP_EX_OVERFLOW,
FP_EX_UNDERFLOW, FP_EX_INEXACT, FP_EX_INVALID, FP_EX_DIVZERO,
FP_EX_ALL): New constant macros.
(_FP_DECL_EX, FP_ROUNDMODE, FP_INIT_ROUNDMODE,
FP_HANDLE_EXCEPTIONS): New macros.
(_FP_TININESS_AFTER_ROUNDING): Change to 1.
---
libgcc/config/or1k/sfp-machine.h | 41 +++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/libgcc/config/or1k/sfp-machine.h b/libgcc/config/or1k/sfp-machine.h
index 5da9e84990d..eebe5b0578e 100644
--- a/libgcc/config/or1k/sfp-machine.h
+++ b/libgcc/config/or1k/sfp-machine.h
@@ -41,12 +41,51 @@
R##_c = FP_CLS_NAN;\
} while (0)
+/* Handle getting and setting rounding mode for soft fp operations. */
+
+#define FP_RND_NEAREST (0x0 << 1)
+#define FP_RND_ZERO(0x1 << 1)
+#define FP_RND_PINF(0x2 << 1)
+#define FP_RND_MINF(0x3 << 1)
+#define FP_RND_MASK(0x3 << 1)
+
+#define FP_EX_OVERFLOW 1 << 3
+#define FP_EX_UNDERFLOW1 << 4
+#define FP_EX_INEXACT 1 << 8
+#define FP_EX_INVALID 1 << 9
+#define FP_EX_DIVZERO 1 << 11
+#define FP_EX_ALL \
+ (FP_EX_INVALID | FP_EX_DIVZERO | FP_EX_OVERFLOW | FP_EX_UNDERFLOW \
+| FP_EX_INEXACT)
+
+#define _FP_DECL_EX \
+ unsigned int _fpcsr __attribute__ ((unused)) = FP_RND_NEAREST
+
+#define FP_ROUNDMODE (_fpcsr & FP_RND_MASK)
+
+#ifdef __or1k_hard_float__
+#define FP_INIT_ROUNDMODE \
+do { \
+ __asm__ volatile ("l.mfspr %0,r0,20" : "=r" (_fpcsr)); \
+} while (0)
+
+#define FP_HANDLE_EXCEPTIONS \
+do { \
+ if (__builtin_expect (_fex, 0)) \
+{ \
+ _fpcsr &= ~FP_EX_ALL;\
+ _fpcsr |= _fex; \
+ __asm__ volatile ("l.mtspr r0,%0,20" : : "r" (_fpcsr)); \
+} \
+} while (0)
+#endif
+
#define__LITTLE_ENDIAN 1234
#define__BIG_ENDIAN4321
#define __BYTE_ORDER __BIG_ENDIAN
-#define _FP_TININESS_AFTER_ROUNDING 0
+#define _FP_TININESS_AFTER_ROUNDING 1
/* Define ALIASNAME as a strong alias for NAME. */
# define strong_alias(name, aliasname) _strong_alias(name, aliasname)
--
2.26.2
[PATCH v2 2/5] or1k: Add builtin define to detect hard float
This is used in libgcc and now glibc to detect when hardware floating
point operations are supported by the target.
gcc/ChangeLog:
* config/or1k/or1k.h (TARGET_CPU_CPP_BUILTINS): Add builtin
define for __or1k_hard_float__.
---
gcc/config/or1k/or1k.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
index dc579e4a388..b686f1bd159 100644
--- a/gcc/config/or1k/or1k.h
+++ b/gcc/config/or1k/or1k.h
@@ -30,6 +30,8 @@
builtin_define ("__or1k__"); \
if (TARGET_CMOV) \
builtin_define ("__or1k_cmov__"); \
+ if (TARGET_HARD_FLOAT) \
+ builtin_define ("__or1k_hard_float__"); \
builtin_assert ("cpu=or1k"); \
builtin_assert ("machine=or1k"); \
} \
--
2.26.2
[PATCH v2 1/5] or1k: Implement profile hook calling _mcount
Defining this to not abort as found when working on running tests in
the glibc test suite.
We implement this with a call to _mcount with no arguments. The required
return address's will be pulled from the stack. Passing the LR (r9) as
an argument had problems as sometimes r9 is clobbered by the GOT logic
in the prologue before the call to _mcount.
gcc/ChangeLog:
* config/or1k/or1k.h (NO_PROFILE_COUNTERS): Define as 1.
(PROFILE_HOOK): Define to call _mcount.
(FUNCTION_PROFILER): Change from abort to no-op.
---
gcc/config/or1k/or1k.h | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
index ab1c4bbd2a7..dc579e4a388 100644
--- a/gcc/config/or1k/or1k.h
+++ b/gcc/config/or1k/or1k.h
@@ -379,8 +379,19 @@ do {\
/* Always pass the SYMBOL_REF for direct calls to the expanders. */
#define NO_FUNCTION_CSE 1
-/* Profiling */
-#define FUNCTION_PROFILER(FILE,LABELNO) (abort (), 0)
+#define NO_PROFILE_COUNTERS 1
+
+/* Emit rtl for profiling. Output assembler code to call "_mcount" for
+ profiling a function entry. */
+#define PROFILE_HOOK(LABEL)\
+ {\
+rtx fun; \
+fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); \
+emit_library_call (fun, LCT_NORMAL, VOIDmode); \
+ }
+
+/* All the work is done in PROFILE_HOOK, but this is still required. */
+#define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
/* Dwarf 2 Support */
#define DWARF2_DEBUGGING_INFO 1
--
2.26.2
[RESEND PATCH 0/5] OpenRISC GCC Fixes for Glibc Support
Hello, Changes since v1: - Rebase This just a resend of v1 with no changes from when I sent it last year. I hadn't committed it because I had not completed all testing in glibc. Now that I have done that and it all seems to work I will commit it. I am currently working on the glibc port for OpenRISC. This is a series of patches that fix issues and add features that were missing in GCC causing glibc testsuite failures. Pretty much all of these changes are just adding macros. These changes have been tested via the glibc test suite. -Stafford Stafford Horne (5): or1k: Implement profile hook calling _mcount or1k: Add builtin define to detect hard float or1k: Support for softfloat to emulate hw exceptions or1k: Add note to indicate execstack or1k: Fixup exception header data encodings gcc/config/or1k/linux.h | 2 ++ gcc/config/or1k/or1k.h | 21 ++-- libgcc/config/or1k/sfp-machine.h | 41 +++- 3 files changed, 61 insertions(+), 3 deletions(-) -- 2.26.2
Re: [PATCH 4/6] contrib: Add or1k-elf, or1k-linux-*, and or1k-rtems to config-list.mk
On Sun, May 31, 2020 at 12:19:16PM +0200, Iain Buclaw wrote: > Support for OpenRISC target was added in SVN r265963. > > The target configurations were taken from the list of supported > toolchains[1], so seems sensible to include them all. > > OK? > > Regards > Iain > > [1]: https://www.openrisc.io/software > > --- > contrib/ChangeLog: > > * config-list.mk (LIST): Add or1k-elf, or1k-linux-*, and or1k-rtems. This looks good to me. Can you apply it or do you want me to do it? -Stafford
[PATCH 5/5] or1k: Fixup exception header data encodings
While running glibc tests several *-textrel tests failed showing that
relocations remained against read only sections. It turned out this was
related to exception headers data encoding being wrong.
By default pointer encoding will always use the DW_EH_PE_absptr format.
This patch uses format DW_EH_PE_pcrel and DW_EH_PE_sdata4. Optionally
DW_EH_PE_indirect is included for global symbols. This eliminates the
relocations.
gcc/ChangeLog:
* config/or1k/or1k.h (ASM_PREFERRED_EH_DATA_FORMAT): New macro.
---
gcc/config/or1k/or1k.h | 4
1 file changed, 4 insertions(+)
diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
index 0d6fed5f4ca..2fe62f0b90c 100644
--- a/gcc/config/or1k/or1k.h
+++ b/gcc/config/or1k/or1k.h
@@ -408,4 +408,8 @@ do {\
((N) < 4 ? HW_TO_GCC_REGNO (25) + (N) : INVALID_REGNUM)
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM)
+/* Select a format to encode pointers in exception handling data. */
+#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
+ (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
+
#endif /* GCC_OR1K_H */
--
2.26.2
[PATCH 2/5] or1k: Add builtin define to detect hard float
This is used in libgcc and now glibc to detect when hardware floating
point operations are supported by the target.
gcc/ChangeLog:
* config/or1k/or1k.h (TARGET_CPU_CPP_BUILTINS): Add builtin
define for __or1k_hard_float__.
---
gcc/config/or1k/or1k.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
index be089900fd4..0d6fed5f4ca 100644
--- a/gcc/config/or1k/or1k.h
+++ b/gcc/config/or1k/or1k.h
@@ -30,6 +30,8 @@
builtin_define ("__or1k__"); \
if (TARGET_CMOV) \
builtin_define ("__or1k_cmov__"); \
+ if (TARGET_HARD_FLOAT) \
+ builtin_define ("__or1k_hard_float__"); \
builtin_assert ("cpu=or1k"); \
builtin_assert ("machine=or1k"); \
} \
--
2.26.2
[PATCH 3/5] or1k: Support for softfloat to emulate hw exceptions
This allows the openrisc softfloat implementation to set exceptions.
This also sets the correct tininess after rounding value to be
consistent with hardware and simulator implementations.
libgcc/ChangeLog:
* config/or1k/sfp-machine.h (FP_RND_NEAREST, FP_RND_ZERO,
FP_RND_PINF, FP_RND_MINF, FP_RND_MASK, FP_EX_OVERFLOW,
FP_EX_UNDERFLOW, FP_EX_INEXACT, FP_EX_INVALID, FP_EX_DIVZERO,
FP_EX_ALL): New constant macros.
(_FP_DECL_EX, FP_ROUNDMODE, FP_INIT_ROUNDMODE,
FP_HANDLE_EXCEPTIONS): New macros.
(_FP_TININESS_AFTER_ROUNDING): Change to 1.
---
libgcc/config/or1k/sfp-machine.h | 41 +++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/libgcc/config/or1k/sfp-machine.h b/libgcc/config/or1k/sfp-machine.h
index 5da9e84990d..eebe5b0578e 100644
--- a/libgcc/config/or1k/sfp-machine.h
+++ b/libgcc/config/or1k/sfp-machine.h
@@ -41,12 +41,51 @@
R##_c = FP_CLS_NAN;\
} while (0)
+/* Handle getting and setting rounding mode for soft fp operations. */
+
+#define FP_RND_NEAREST (0x0 << 1)
+#define FP_RND_ZERO(0x1 << 1)
+#define FP_RND_PINF(0x2 << 1)
+#define FP_RND_MINF(0x3 << 1)
+#define FP_RND_MASK(0x3 << 1)
+
+#define FP_EX_OVERFLOW 1 << 3
+#define FP_EX_UNDERFLOW1 << 4
+#define FP_EX_INEXACT 1 << 8
+#define FP_EX_INVALID 1 << 9
+#define FP_EX_DIVZERO 1 << 11
+#define FP_EX_ALL \
+ (FP_EX_INVALID | FP_EX_DIVZERO | FP_EX_OVERFLOW | FP_EX_UNDERFLOW \
+| FP_EX_INEXACT)
+
+#define _FP_DECL_EX \
+ unsigned int _fpcsr __attribute__ ((unused)) = FP_RND_NEAREST
+
+#define FP_ROUNDMODE (_fpcsr & FP_RND_MASK)
+
+#ifdef __or1k_hard_float__
+#define FP_INIT_ROUNDMODE \
+do { \
+ __asm__ volatile ("l.mfspr %0,r0,20" : "=r" (_fpcsr)); \
+} while (0)
+
+#define FP_HANDLE_EXCEPTIONS \
+do { \
+ if (__builtin_expect (_fex, 0)) \
+{ \
+ _fpcsr &= ~FP_EX_ALL;\
+ _fpcsr |= _fex; \
+ __asm__ volatile ("l.mtspr r0,%0,20" : : "r" (_fpcsr)); \
+} \
+} while (0)
+#endif
+
#define__LITTLE_ENDIAN 1234
#define__BIG_ENDIAN4321
#define __BYTE_ORDER __BIG_ENDIAN
-#define _FP_TININESS_AFTER_ROUNDING 0
+#define _FP_TININESS_AFTER_ROUNDING 1
/* Define ALIASNAME as a strong alias for NAME. */
# define strong_alias(name, aliasname) _strong_alias(name, aliasname)
--
2.26.2
[PATCH 1/5] or1k: Implement profile hook calling _mcount
Defining this to not abort as found when working on running tests in
the glibc test suite.
We implement this with a call to _mcount with no arguments. The required
return address's will be pulled from the stack. Passing the LR (r9) as
an argument had problems as sometimes r9 is clobbered by the GOT logic
in the prologue before the call to _mcount.
gcc/ChangeLog:
* config/or1k/or1k.h (NO_PROFILE_COUNTERS): Define as 1.
(PROFILE_HOOK): Define to call _mcount.
(FUNCTION_PROFILER): Change from abort to no-op.
---
gcc/config/or1k/or1k.h | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
index 23db771d8fb..be089900fd4 100644
--- a/gcc/config/or1k/or1k.h
+++ b/gcc/config/or1k/or1k.h
@@ -379,8 +379,19 @@ do {\
/* Always pass the SYMBOL_REF for direct calls to the expanders. */
#define NO_FUNCTION_CSE 1
-/* Profiling */
-#define FUNCTION_PROFILER(FILE,LABELNO) (abort (), 0)
+#define NO_PROFILE_COUNTERS 1
+
+/* Emit rtl for profiling. Output assembler code to call "_mcount" for
+ profiling a function entry. */
+#define PROFILE_HOOK(LABEL)\
+ {\
+rtx fun; \
+fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); \
+emit_library_call (fun, LCT_NORMAL, VOIDmode); \
+ }
+
+/* All the work is done in PROFILE_HOOK, but this is still required. */
+#define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
/* Dwarf 2 Support */
#define DWARF2_DEBUGGING_INFO 1
--
2.26.2
[PATCH 0/5] OpenRISC GCC Fixes for Glibc Support
Hello, I am currently working on the glibc port for OpenRISC. This is a series of patches that fix issues and add features that were missing in GCC causing glibc testsuite failures. Pretty much all of these changes are just adding macros. These changes have been tested via the glibc test suite. -Stafford Stafford Horne (5): or1k: Implement profile hook calling _mcount or1k: Add builtin define to detect hard float or1k: Support for softfloat to emulate hw exceptions or1k: Add note to indicate execstack or1k: Fixup exception header data encodings gcc/config/or1k/linux.h | 2 ++ gcc/config/or1k/or1k.h | 21 ++-- libgcc/config/or1k/sfp-machine.h | 41 +++- 3 files changed, 61 insertions(+), 3 deletions(-) -- 2.26.2
[PATCH 4/5] or1k: Add note to indicate execstack
Define TARGET_ASM_FILE_END as file_end_indicate_exec_stack to allow
generation of the ".note.GNU-stack" section note. This allows binutils
to properly set PT_GNU_STACK in the program header.
This fixes a glibc execstack testsuite test failure found while working
on the OpenRISC glibc port.
gcc/ChangeLog:
* config/or1k/linux.h (TARGET_ASM_FILE_END): Define macro.
---
gcc/config/or1k/linux.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/config/or1k/linux.h b/gcc/config/or1k/linux.h
index 21cef067dda..8693e884e2a 100644
--- a/gcc/config/or1k/linux.h
+++ b/gcc/config/or1k/linux.h
@@ -42,4 +42,6 @@
%{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}} \
%{static-pie:-Bstatic -pie --no-dynamic-linker -z text}"
+#define TARGET_ASM_FILE_END file_end_indicate_exec_stack
+
#endif /* GCC_OR1K_LINUX_H */
--
2.26.2
Re: [PATCH] or1k: Fix issue with set_got clobbering r9
On Fri, Aug 30, 2019 at 08:21:56AM -0700, Richard Henderson wrote:
> LGTM.
Thank you.
> On 8/30/19 2:31 AM, Stafford Horne wrote:
> > Hello, any comments on this?
> >
> > If nothing I will commit in a few days.
> >
> > On Thu, Aug 22, 2019 at 08:44:04PM +0900, Stafford Horne wrote:
> >> When compiling glibc we found that the GOT register was being allocated
> >> r9 when the instruction was still set_got_tmp. That caused set_got to
> >> clobber r9. We cannot simply say set_got_tmp clobbers r9 as this is the
> >> reason for having the temporary set_got_tmp.
> >>
> >> Fix by using a register class constraint that does not allow r9 during
> >> register allocation.
> >>
> >> gcc/ChangeLog:
> >>
> >>* config/or1k/constraints.md (t): New constraint.
> >>* config/or1k/or1k.h (GOT_REGS): New register class.
> >>* config/or1k/or1k.md (set_got_tmp, set_got): Use t contraint.
> >> ---
> >> gcc/config/or1k/constraints.md | 4
> >> gcc/config/or1k/or1k.h | 3 +++
> >> gcc/config/or1k/or1k.md| 4 ++--
> >> 3 files changed, 9 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/gcc/config/or1k/constraints.md
> >> b/gcc/config/or1k/constraints.md
> >> index 8cac7eb5329..ba330c6b8c2 100644
> >> --- a/gcc/config/or1k/constraints.md
> >> +++ b/gcc/config/or1k/constraints.md
> >> @@ -25,6 +25,7 @@
> >> ; We use:
> >> ; c - sibcall registers
> >> ; d - double pair base registers (excludes r0, r30 and r31 which
> >> overflow)
> >> +; t - got address registers (excludes r9 is clobbered by set_got)
> >
> > I will changee this to (... r9 which is clobbered ...)
> >
> >> ; I - constant signed 16-bit
> >> ; K - constant unsigned 16-bit
> >> ; M - constant signed 16-bit shifted left 16-bits (l.movhi)
> >> @@ -36,6 +37,9 @@
> >> (define_register_constraint "d" "DOUBLE_REGS"
> >>"Registers which can be used for double reg pairs.")
> >>
> >> +(define_register_constraint "t" "GOT_REGS"
> >> + "Registers which can be used to store the Global Offset Table (GOT)
> >> address.")
> >> +
> >> ;; Immediates
> >> (define_constraint "I"
> >>"A signed 16-bit immediate in the range -32768 to 32767."
> >> diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
> >> index 2b29e62fdd3..4c32607bac1 100644
> >> --- a/gcc/config/or1k/or1k.h
> >> +++ b/gcc/config/or1k/or1k.h
> >> @@ -190,6 +190,7 @@ enum reg_class
> >>NO_REGS,
> >>SIBCALL_REGS,
> >>DOUBLE_REGS,
> >> + GOT_REGS,
> >>GENERAL_REGS,
> >>FLAG_REGS,
> >>ALL_REGS,
> >> @@ -202,6 +203,7 @@ enum reg_class
> >>"NO_REGS", \
> >>"SIBCALL_REGS", \
> >>"DOUBLE_REGS", \
> >> + "GOT_REGS", \
> >>"GENERAL_REGS", \
> >>"FLAG_REGS",\
> >>"ALL_REGS" }
> >> @@ -215,6 +217,7 @@ enum reg_class
> >> { { 0x, 0x }, \
> >>{ SIBCALL_REGS_MASK, 0 }, \
> >>{ 0x7f7e, 0x }, \
> >> + { 0xfdff, 0x }, \
> >>{ 0x, 0x0003 }, \
> >>{ 0x, 0x0004 }, \
> >>{ 0x, 0x0007 } \
> >> diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md
> >> index cee11d078cc..36bcee336ab 100644
> >> --- a/gcc/config/or1k/or1k.md
> >> +++ b/gcc/config/or1k/or1k.md
> >> @@ -706,7 +706,7 @@
> >> ;; set_got pattern below. This works because the set_got_tmp insn is the
> >> ;; first insn in the stream and that it isn't moved during RA.
> >> (define_insn "set_got_tmp"
> >> - [(set (match_operand:SI 0 "register_operand" "=r")
> >> + [(set (match_operand:SI 0 "register_operand" "=t")
> >>(unspec_volatile:SI [(const_int 0)] UNSPECV_SET_GOT))]
> >>""
> >> {
> >> @@ -715,7 +715,7 @@
> >>
> >> ;; The insn to initialize the GOT.
> >> (define_insn "set_got"
> >> - [(set (match_operand:SI 0 "register_operand" "=r")
> >> + [(set (match_operand:SI 0 "register_operand" "=t")
> >>(unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
> >> (clobber (reg:SI LR_REGNUM))]
> >>""
> >> --
> >> 2.21.0
> >>
>
Re: [PATCH] or1k: Fix issue with set_got clobbering r9
Hello, any comments on this?
If nothing I will commit in a few days.
On Thu, Aug 22, 2019 at 08:44:04PM +0900, Stafford Horne wrote:
> When compiling glibc we found that the GOT register was being allocated
> r9 when the instruction was still set_got_tmp. That caused set_got to
> clobber r9. We cannot simply say set_got_tmp clobbers r9 as this is the
> reason for having the temporary set_got_tmp.
>
> Fix by using a register class constraint that does not allow r9 during
> register allocation.
>
> gcc/ChangeLog:
>
> * config/or1k/constraints.md (t): New constraint.
> * config/or1k/or1k.h (GOT_REGS): New register class.
> * config/or1k/or1k.md (set_got_tmp, set_got): Use t contraint.
> ---
> gcc/config/or1k/constraints.md | 4
> gcc/config/or1k/or1k.h | 3 +++
> gcc/config/or1k/or1k.md| 4 ++--
> 3 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/or1k/constraints.md b/gcc/config/or1k/constraints.md
> index 8cac7eb5329..ba330c6b8c2 100644
> --- a/gcc/config/or1k/constraints.md
> +++ b/gcc/config/or1k/constraints.md
> @@ -25,6 +25,7 @@
> ; We use:
> ; c - sibcall registers
> ; d - double pair base registers (excludes r0, r30 and r31 which overflow)
> +; t - got address registers (excludes r9 is clobbered by set_got)
I will changee this to (... r9 which is clobbered ...)
> ; I - constant signed 16-bit
> ; K - constant unsigned 16-bit
> ; M - constant signed 16-bit shifted left 16-bits (l.movhi)
> @@ -36,6 +37,9 @@
> (define_register_constraint "d" "DOUBLE_REGS"
>"Registers which can be used for double reg pairs.")
>
> +(define_register_constraint "t" "GOT_REGS"
> + "Registers which can be used to store the Global Offset Table (GOT)
> address.")
> +
> ;; Immediates
> (define_constraint "I"
>"A signed 16-bit immediate in the range -32768 to 32767."
> diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
> index 2b29e62fdd3..4c32607bac1 100644
> --- a/gcc/config/or1k/or1k.h
> +++ b/gcc/config/or1k/or1k.h
> @@ -190,6 +190,7 @@ enum reg_class
>NO_REGS,
>SIBCALL_REGS,
>DOUBLE_REGS,
> + GOT_REGS,
>GENERAL_REGS,
>FLAG_REGS,
>ALL_REGS,
> @@ -202,6 +203,7 @@ enum reg_class
>"NO_REGS", \
>"SIBCALL_REGS",\
>"DOUBLE_REGS", \
> + "GOT_REGS",\
>"GENERAL_REGS",\
>"FLAG_REGS", \
>"ALL_REGS" }
> @@ -215,6 +217,7 @@ enum reg_class
> { { 0x, 0x },\
>{ SIBCALL_REGS_MASK, 0 },\
>{ 0x7f7e, 0x },\
> + { 0xfdff, 0x },\
>{ 0x, 0x0003 },\
>{ 0x, 0x0004 },\
>{ 0x, 0x0007 } \
> diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md
> index cee11d078cc..36bcee336ab 100644
> --- a/gcc/config/or1k/or1k.md
> +++ b/gcc/config/or1k/or1k.md
> @@ -706,7 +706,7 @@
> ;; set_got pattern below. This works because the set_got_tmp insn is the
> ;; first insn in the stream and that it isn't moved during RA.
> (define_insn "set_got_tmp"
> - [(set (match_operand:SI 0 "register_operand" "=r")
> + [(set (match_operand:SI 0 "register_operand" "=t")
> (unspec_volatile:SI [(const_int 0)] UNSPECV_SET_GOT))]
>""
> {
> @@ -715,7 +715,7 @@
>
> ;; The insn to initialize the GOT.
> (define_insn "set_got"
> - [(set (match_operand:SI 0 "register_operand" "=r")
> + [(set (match_operand:SI 0 "register_operand" "=t")
> (unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
> (clobber (reg:SI LR_REGNUM))]
>""
> --
> 2.21.0
>
[PATCH] or1k: Fix issue with set_got clobbering r9
When compiling glibc we found that the GOT register was being allocated
r9 when the instruction was still set_got_tmp. That caused set_got to
clobber r9. We cannot simply say set_got_tmp clobbers r9 as this is the
reason for having the temporary set_got_tmp.
Fix by using a register class constraint that does not allow r9 during
register allocation.
gcc/ChangeLog:
* config/or1k/constraints.md (t): New constraint.
* config/or1k/or1k.h (GOT_REGS): New register class.
* config/or1k/or1k.md (set_got_tmp, set_got): Use t contraint.
---
gcc/config/or1k/constraints.md | 4
gcc/config/or1k/or1k.h | 3 +++
gcc/config/or1k/or1k.md| 4 ++--
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/gcc/config/or1k/constraints.md b/gcc/config/or1k/constraints.md
index 8cac7eb5329..ba330c6b8c2 100644
--- a/gcc/config/or1k/constraints.md
+++ b/gcc/config/or1k/constraints.md
@@ -25,6 +25,7 @@
; We use:
; c - sibcall registers
; d - double pair base registers (excludes r0, r30 and r31 which overflow)
+; t - got address registers (excludes r9 is clobbered by set_got)
; I - constant signed 16-bit
; K - constant unsigned 16-bit
; M - constant signed 16-bit shifted left 16-bits (l.movhi)
@@ -36,6 +37,9 @@
(define_register_constraint "d" "DOUBLE_REGS"
"Registers which can be used for double reg pairs.")
+(define_register_constraint "t" "GOT_REGS"
+ "Registers which can be used to store the Global Offset Table (GOT)
address.")
+
;; Immediates
(define_constraint "I"
"A signed 16-bit immediate in the range -32768 to 32767."
diff --git a/gcc/config/or1k/or1k.h b/gcc/config/or1k/or1k.h
index 2b29e62fdd3..4c32607bac1 100644
--- a/gcc/config/or1k/or1k.h
+++ b/gcc/config/or1k/or1k.h
@@ -190,6 +190,7 @@ enum reg_class
NO_REGS,
SIBCALL_REGS,
DOUBLE_REGS,
+ GOT_REGS,
GENERAL_REGS,
FLAG_REGS,
ALL_REGS,
@@ -202,6 +203,7 @@ enum reg_class
"NO_REGS", \
"SIBCALL_REGS", \
"DOUBLE_REGS", \
+ "GOT_REGS", \
"GENERAL_REGS", \
"FLAG_REGS", \
"ALL_REGS" }
@@ -215,6 +217,7 @@ enum reg_class
{ { 0x, 0x }, \
{ SIBCALL_REGS_MASK, 0 }, \
{ 0x7f7e, 0x }, \
+ { 0xfdff, 0x }, \
{ 0x, 0x0003 }, \
{ 0x, 0x0004 }, \
{ 0x, 0x0007 } \
diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md
index cee11d078cc..36bcee336ab 100644
--- a/gcc/config/or1k/or1k.md
+++ b/gcc/config/or1k/or1k.md
@@ -706,7 +706,7 @@
;; set_got pattern below. This works because the set_got_tmp insn is the
;; first insn in the stream and that it isn't moved during RA.
(define_insn "set_got_tmp"
- [(set (match_operand:SI 0 "register_operand" "=r")
+ [(set (match_operand:SI 0 "register_operand" "=t")
(unspec_volatile:SI [(const_int 0)] UNSPECV_SET_GOT))]
""
{
@@ -715,7 +715,7 @@
;; The insn to initialize the GOT.
(define_insn "set_got"
- [(set (match_operand:SI 0 "register_operand" "=r")
+ [(set (match_operand:SI 0 "register_operand" "=t")
(unspec:SI [(const_int 0)] UNSPEC_SET_GOT))
(clobber (reg:SI LR_REGNUM))]
""
--
2.21.0
Re: [PATCH v3 0/5] OpenRISC updates for 10 (fpu, fixes)
Hi All, This is all upstream now. Thank you for the reviews. On Tue, Jul 09, 2019 at 10:06:21PM +0900, Stafford Horne wrote: > Hello, > > New since v2: > - Fix comment formatting pointed out by Segher in valatile patch > - Fix issue and add test for rotrsi3 options pointed out by Segher > - Fix issue with reg mask for doubles being backwards Pointed out by Segher >and Richard. > > New since v1: > - Changed 64-bit FPU operations to use explicit register pairs as per spec >revision suggested by Richard Henderson. > - Added patch for new -mrori option > - Added patch for msoft-div fix from other series (no changes) > - Fixed volatile spelling pointed out by Bernhard >Reutner-Fischer > > This is a set of patches to bring FPU support to the OpenRISC backend. The > backend also add support for 64-bit floating point operations on 32-bit cores > using register pairs, see orfpx64a32 [0]. > > This binutils patches are already upstream. > > The toolchain has been tested using the gcc and binutils testsuites as well as > floating point test suites running on sim and an fpga soft core > or1k_marocchino. > [1] > > I have also included a few fixes to PRs: > > - 90362 or1k: Soft divide does not work correctly > - 90363 or1k: Extra mask insn after load from memory > > This whole patch series can be found on my github repo [2] as well. > > If all is OK, I plan to commit these to master (gcc 10). Then back port the > PR > fixes to the GCC 9 branch, I will ask for guidance when I start to do the > backporting. > > -Stafford > > [0] https://openrisc.io/proposals/orfpx64a32 > [1] https://github.com/openrisc/or1k_marocchino > [2] g...@github.com:stffrdhrn/gcc.git or1k-fpu-3 > > > *** BLURB HERE *** > > Stafford Horne (5): > or1k: Fix code quality for volatile memory loads > or1k: Fix issues with msoft-div > or1k: Add mrori option, fix option docs > or1k: Initial support for FPU > or1k: only force reg for immediates > > gcc/config.gcc| 2 + > gcc/config/or1k/constraints.md| 4 + > gcc/config/or1k/elf.opt | 6 +- > gcc/config/or1k/or1k.c| 50 +++-- > gcc/config/or1k/or1k.h| 3 + > gcc/config/or1k/or1k.md | 131 -- > gcc/config/or1k/or1k.opt | 78 + > gcc/config/or1k/predicates.md | 30 + > gcc/doc/invoke.texi | 77 - > gcc/testsuite/gcc.target/or1k/div-mul-3.c | 31 + > gcc/testsuite/gcc.target/or1k/ror-4.c | 8 ++ > gcc/testsuite/gcc.target/or1k/ror-5.c | 9 ++ > gcc/testsuite/gcc.target/or1k/shftimm-1.c | 8 +- > gcc/testsuite/gcc.target/or1k/swap-1.c| 70 > gcc/testsuite/gcc.target/or1k/swap-2.c| 47 > libgcc/config/or1k/lib1funcs.S| 6 +- > 16 files changed, 484 insertions(+), 76 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/or1k/div-mul-3.c > create mode 100644 gcc/testsuite/gcc.target/or1k/ror-4.c > create mode 100644 gcc/testsuite/gcc.target/or1k/ror-5.c > create mode 100644 gcc/testsuite/gcc.target/or1k/swap-1.c > create mode 100644 gcc/testsuite/gcc.target/or1k/swap-2.c > > -- > 2.21.0 >
Re: [PATCH v3 0/5] OpenRISC updates for 10 (fpu, fixes)
On Tue, Jul 09, 2019 at 10:06:21PM +0900, Stafford Horne wrote: > Hello, > > New since v2: > - Fix comment formatting pointed out by Segher in valatile patch > - Fix issue and add test for rotrsi3 options pointed out by Segher > - Fix issue with reg mask for doubles being backwards Pointed out by Segher >and Richard. > > New since v1: > - Changed 64-bit FPU operations to use explicit register pairs as per spec >revision suggested by Richard Henderson. > - Added patch for new -mrori option > - Added patch for msoft-div fix from other series (no changes) > - Fixed volatile spelling pointed out by Bernhard >Reutner-Fischer > > This is a set of patches to bring FPU support to the OpenRISC backend. The > backend also add support for 64-bit floating point operations on 32-bit cores > using register pairs, see orfpx64a32 [0]. > > This binutils patches are already upstream. > > The toolchain has been tested using the gcc and binutils testsuites as well as > floating point test suites running on sim and an fpga soft core > or1k_marocchino. > [1] > > I have also included a few fixes to PRs: > > - 90362 or1k: Soft divide does not work correctly > - 90363 or1k: Extra mask insn after load from memory > > This whole patch series can be found on my github repo [2] as well. > > If all is OK, I plan to commit these to master (gcc 10). Then back port the > PR > fixes to the GCC 9 branch, I will ask for guidance when I start to do the > backporting. Hello, Is there any concern if I commit these? -Stafford > -Stafford > > [0] https://openrisc.io/proposals/orfpx64a32 > [1] https://github.com/openrisc/or1k_marocchino > [2] g...@github.com:stffrdhrn/gcc.git or1k-fpu-3 > > > *** BLURB HERE *** > > Stafford Horne (5): > or1k: Fix code quality for volatile memory loads > or1k: Fix issues with msoft-div > or1k: Add mrori option, fix option docs > or1k: Initial support for FPU > or1k: only force reg for immediates > > gcc/config.gcc| 2 + > gcc/config/or1k/constraints.md| 4 + > gcc/config/or1k/elf.opt | 6 +- > gcc/config/or1k/or1k.c| 50 +++-- > gcc/config/or1k/or1k.h| 3 + > gcc/config/or1k/or1k.md | 131 -- > gcc/config/or1k/or1k.opt | 78 + > gcc/config/or1k/predicates.md | 30 + > gcc/doc/invoke.texi | 77 - > gcc/testsuite/gcc.target/or1k/div-mul-3.c | 31 + > gcc/testsuite/gcc.target/or1k/ror-4.c | 8 ++ > gcc/testsuite/gcc.target/or1k/ror-5.c | 9 ++ > gcc/testsuite/gcc.target/or1k/shftimm-1.c | 8 +- > gcc/testsuite/gcc.target/or1k/swap-1.c| 70 > gcc/testsuite/gcc.target/or1k/swap-2.c| 47 > libgcc/config/or1k/lib1funcs.S| 6 +- > 16 files changed, 484 insertions(+), 76 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/or1k/div-mul-3.c > create mode 100644 gcc/testsuite/gcc.target/or1k/ror-4.c > create mode 100644 gcc/testsuite/gcc.target/or1k/ror-5.c > create mode 100644 gcc/testsuite/gcc.target/or1k/swap-1.c > create mode 100644 gcc/testsuite/gcc.target/or1k/swap-2.c > > -- > 2.21.0 >
[PATCH v3 2/5] or1k: Fix issues with msoft-div
Fixes bad assembly logic with software divide as reported by Richard Selvaggi.
Also, add a basic test to verify the soft math works when enabled.
gcc/testsuite/ChangeLog:
PR target/90362
* gcc.target/or1k/div-mul-3.c: New test.
libgcc/ChangeLog:
PR target/90362
* config/or1k/lib1funcs.S (__udivsi3): Change l.sfeqi
to l.sfeq and l.sfltsi to l.sflts equivalents as the immediate
instructions are not available on every processor. Change a
l.bnf to l.bf to fix logic issue.
---
gcc/testsuite/gcc.target/or1k/div-mul-3.c | 31 +++
libgcc/config/or1k/lib1funcs.S| 6 ++---
2 files changed, 34 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/or1k/div-mul-3.c
diff --git a/gcc/testsuite/gcc.target/or1k/div-mul-3.c
b/gcc/testsuite/gcc.target/or1k/div-mul-3.c
new file mode 100644
index 000..2c4f91b7e98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/or1k/div-mul-3.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msoft-div -msoft-mul" } */
+
+struct testcase {
+ int a;
+ int b;
+ int c;
+ int expected;
+};
+
+struct testcase tests[] = {
+ {2, 200, 3, 133},
+ {3, 300, 3, 300},
+ {2, 500, 3, 333},
+ {4, 250, 3, 333},
+ {0, 0, 0, 0}
+};
+
+int calc (int a, int b, int c) {
+ return a * b / c;
+}
+
+int main () {
+ int fail = 0;
+ struct testcase *tc;
+
+ for (int i = 0; (tc = [i], tc->c); i++)
+fail |= (calc (tc->a, tc->b, tc->c) != tc->expected);
+
+ return fail;
+}
diff --git a/libgcc/config/or1k/lib1funcs.S b/libgcc/config/or1k/lib1funcs.S
index d2103923486..6d058977229 100644
--- a/libgcc/config/or1k/lib1funcs.S
+++ b/libgcc/config/or1k/lib1funcs.S
@@ -68,18 +68,18 @@ __udivmodsi3_internal:
is not clobbered by this routine, and use that as to
save a return address without creating a stack frame. */
- l.sfeqi r4, 0 /* division by zero; return 0. */
+ l.sfeq r4, r0 /* division by zero; return 0. */
l.ori r11, r0, 0 /* initial quotient */
l.bf9f
l.ori r12, r3, 0 /* initial remainder */
/* Given X/Y, shift Y left until Y >= X. */
l.ori r6, r0, 1 /* mask = 1 */
-1: l.sfltsir4, 0 /* y has msb set */
+1: l.sflts r4, r0 /* y has msb set */
l.bf2f
l.sfltur4, r12 /* y < x */
l.add r4, r4, r4 /* y <<= 1 */
- l.bnf 1b
+ l.bf1b
l.add r6, r6, r6 /* mask <<= 1 */
/* Shift Y back to the right again, subtracting from X. */
--
2.21.0
[PATCH v3 3/5] or1k: Add mrori option, fix option docs
gcc/ChangeLog:
* config.gcc (or1k*-*-*): Add mrori and mror to validation.
* doc/invoke.texi (OpenRISC Options): Add mrori option, rewrite all
documenation to be more clear.
* config/or1k/elf.opt (mboard=, mnewlib): Rewrite documentation to be
more clear.
* config/or1k/or1k.opt (mrori): New option.
(mhard-div, msoft-div, mhard-mul, msoft-mul, mcmov, mror, msext,
msfimm, mshftimm): Rewrite documentation to be more clear.
* config/or1k/predicates.md (ror_reg_or_u6_operand): New predicate.
* config/or1k/or1k.md (insn_support): Add ror and rori.
(enabled): Add conditions for ror and rori.
(rotrsi3): Replace condition for shftimm with ror and rori.
gcc/testsuite/ChangeLog:
* gcc.target/or1k/ror-4.c: New file.
* gcc.target/or1k/ror-5.c: New file.
* gcc.target/or1k/shftimm-1.c: Update test from rotate to shift
as the shftimm option no longer controls rotate.
---
Changes since v2:
- Fix issue with ror predicate pointed out by Segher.
- Added ror-5.c test to confirm/fix ICE.
gcc/config.gcc| 1 +
gcc/config/or1k/elf.opt | 6 +--
gcc/config/or1k/or1k.md | 14 --
gcc/config/or1k/or1k.opt | 56 +--
gcc/config/or1k/predicates.md | 7 +++
gcc/doc/invoke.texi | 56 +--
gcc/testsuite/gcc.target/or1k/ror-4.c | 8
gcc/testsuite/gcc.target/or1k/ror-5.c | 9
gcc/testsuite/gcc.target/or1k/shftimm-1.c | 8 ++--
9 files changed, 104 insertions(+), 61 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/or1k/ror-4.c
create mode 100644 gcc/testsuite/gcc.target/or1k/ror-5.c
diff --git a/gcc/config.gcc b/gcc/config.gcc
index c281c418b28..aeab8b4544e 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -2578,6 +2578,7 @@ or1k*-*-*)
for or1k_multilib in ${or1k_multilibs}; do
case ${or1k_multilib} in
mcmov | msext | msfimm | \
+ mror | mrori | \
mhard-div | mhard-mul | \
msoft-div | msoft-mul )
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG},${or1k_multilib}"
diff --git a/gcc/config/or1k/elf.opt b/gcc/config/or1k/elf.opt
index 641b6ddd4be..2d4d1875d02 100644
--- a/gcc/config/or1k/elf.opt
+++ b/gcc/config/or1k/elf.opt
@@ -25,9 +25,9 @@
mboard=
Target RejectNegative Joined
-Configure board specific runtime.
+Configure the newlib board specific runtime. The default is or1ksim.
mnewlib
Target RejectNegative
-For compatibility, it's always newlib for elf now.
-
+This option is ignored; it is provided for compatibility purposes only. This
+used to select linker and preprocessor options for use with newlib.
diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md
index 757d899c442..0faa0fa4c47 100644
--- a/gcc/config/or1k/or1k.md
+++ b/gcc/config/or1k/or1k.md
@@ -63,7 +63,7 @@
"alu,st,ld,control,multi"
(const_string "alu"))
-(define_attr "insn_support" "class1,sext,sfimm,shftimm" (const_string
"class1"))
+(define_attr "insn_support" "class1,sext,sfimm,shftimm,ror,rori" (const_string
"class1"))
(define_attr "enabled" ""
(cond [(eq_attr "insn_support" "class1") (const_int 1)
@@ -72,7 +72,11 @@
(and (eq_attr "insn_support" "sfimm")
(ne (symbol_ref "TARGET_SFIMM") (const_int 0))) (const_int 1)
(and (eq_attr "insn_support" "shftimm")
- (ne (symbol_ref "TARGET_SHFTIMM") (const_int 0))) (const_int 1)]
+ (ne (symbol_ref "TARGET_SHFTIMM") (const_int 0))) (const_int 1)
+(and (eq_attr "insn_support" "ror")
+ (ne (symbol_ref "TARGET_ROR") (const_int 0))) (const_int 1)
+(and (eq_attr "insn_support" "rori")
+ (ne (symbol_ref "TARGET_RORI") (const_int 0))) (const_int 1)]
(const_int 0)))
;; Describe a user's asm statement.
@@ -178,12 +182,12 @@
(define_insn "rotrsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
- (match_operand:SI 2 "reg_or_u6_operand" "r,n")))]
- "TARGET_ROR"
+(match_operand:SI 2 "ror_reg_or_u6_operand" "r,n")))]
+ "TARGET_ROR || TARGET_RORI"
"@
l.ror\t%0, %1, %2
l.rori\t%0, %1, %2"
- [(set_attr "insn_support" "*,shftimm")])
+ [(set_attr "insn_support" "ror,rori")])
(define_insn "andsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
diff --git a/gcc/config/or1k/or1k.opt b/gcc/config/or1k/or1k.opt
index 7bdbd842dd4..c2f64c5dd45 100644
--- a/gcc/config/or1k/or1k.opt
+++ b/gcc/config/or1k/or1k.opt
@@ -21,47 +21,55 @@
; See the GCC internals manual (options.texi) for a description of
; this file's format.
-; Please try to keep this file in ASCII collating order.
-
mhard-div
Target RejectNegative InverseMask(SOFT_DIV)
-Use hardware divide
[PATCH v3 5/5] or1k: only force reg for immediates
The force_reg in or1k_expand_compare is hard coded for SImode, which is fine as
this used to only be used on SI expands. However, with FP support this will
cause issues. In general we should only force the right hand operand to a
register if its an immediate. This patch adds an condition to check for that.
gcc/ChangeLog:
* config/or1k/or1k.c (or1k_expand_compare): Check for int before
force_reg.
---
gcc/config/or1k/or1k.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c
index 1eea84f47e0..f8eed4a7797 100644
--- a/gcc/config/or1k/or1k.c
+++ b/gcc/config/or1k/or1k.c
@@ -1448,13 +1448,15 @@ void
or1k_expand_compare (rtx *operands)
{
rtx sr_f = gen_rtx_REG (BImode, SR_F_REGNUM);
+ rtx righthand_op = XEXP (operands[0], 1);
rtx_code cmp_code = GET_CODE (operands[0]);
bool flag_check_ne = true;
- /* The RTL may receive an immediate in argument 1 of the compare, this is not
- supported unless we have l.sf*i instructions, force them into registers.
*/
- if (!TARGET_SFIMM)
-XEXP (operands[0], 1) = force_reg (SImode, XEXP (operands[0], 1));
+ /* Integer RTL may receive an immediate in argument 1 of the compare, this is
+ not supported unless we have l.sf*i instructions, force them into
+ registers. */
+ if (!TARGET_SFIMM && CONST_INT_P (righthand_op))
+XEXP (operands[0], 1) = force_reg (SImode, righthand_op);
/* Normalize comparison operators to ones OpenRISC support. */
switch (cmp_code)
--
2.21.0
[PATCH v3 4/5] or1k: Initial support for FPU
This adds support for OpenRISC hardware floating point instructions.
This is enabled with the -mhard-float option.
Double-prevision floating point operations work using register pairing as
specified in: https://openrisc.io/proposals/orfpx64a32. This has just been
added in the OpenRISC architecture specification 1.3.
This is enabled with the -mdouble-float option.
Not all architectures support unordered comparisons so an option,
-munordered-float is added.
Currently OpenRISC does not support sf/df or df/sf conversions, but this has
also just been added in architecture specification 1.3.
gcc/ChangeLog:
* config.gcc (or1k*-*-*): Add mhard-float, mdouble-float, msoft-float
and munordered-float validations.
* config/or1k/constraints.md (d): New register constraint.
* config/or1k/predicates.md (fp_comparison_operator): New.
* config/or1k/or1k.c (or1k_print_operand): Add support for printing 'd'
operands.
(or1k_expand_compare): Normalize unordered comparisons.
* config/or1k/or1k.h (reg_class): Define DOUBLE_REGS.
(REG_CLASS_NAMES): Add "DOUBLE_REGS".
(REG_CLASS_CONTENTS): Add contents for DOUBLE_REGS.
* config/or1k/or1k.md (type): Add fpu.
(fpu): New instruction reservation.
(F, f, fr, fi, FI, FOP, fop): New.
(3): New ALU instruction definition.
(float2): New conversion instruction definition.
(fix_trunc2): New conversion instruction definition.
(fpcmpcc): New code iterator.
(*sf_fp_insn): New instruction definition.
(cstore4): New expand definition.
(cbranch4): New expand definition.
* config/or1k/or1k.opt (msoft-float, mhard-float, mdouble-float,
munordered-float): New options.
* doc/invoke.texi: Document msoft-float, mhard-float, mdouble-float and
munordered-float.
---
Changes since v2:
- Fix wrong order in double reg mask.
gcc/config.gcc | 1 +
gcc/config/or1k/constraints.md | 4 ++
gcc/config/or1k/or1k.c | 38 ++-
gcc/config/or1k/or1k.h | 3 +
gcc/config/or1k/or1k.md| 111 -
gcc/config/or1k/or1k.opt | 22 +++
gcc/config/or1k/predicates.md | 5 ++
gcc/doc/invoke.texi| 21 +++
8 files changed, 201 insertions(+), 4 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index aeab8b4544e..1678109131f 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -2579,6 +2579,7 @@ or1k*-*-*)
case ${or1k_multilib} in
mcmov | msext | msfimm | \
mror | mrori | \
+ mhard-float | mdouble-float | munordered-float | msoft-float | \
mhard-div | mhard-mul | \
msoft-div | msoft-mul )
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG},${or1k_multilib}"
diff --git a/gcc/config/or1k/constraints.md b/gcc/config/or1k/constraints.md
index 93da8c058c6..8cac7eb5329 100644
--- a/gcc/config/or1k/constraints.md
+++ b/gcc/config/or1k/constraints.md
@@ -24,6 +24,7 @@
; We use:
; c - sibcall registers
+; d - double pair base registers (excludes r0, r30 and r31 which overflow)
; I - constant signed 16-bit
; K - constant unsigned 16-bit
; M - constant signed 16-bit shifted left 16-bits (l.movhi)
@@ -32,6 +33,9 @@
(define_register_constraint "c" "SIBCALL_REGS"
"Registers which can hold a sibling call address")
+(define_register_constraint "d" "DOUBLE_REGS"
+ "Registers which can be used for double reg pairs.")
+
;; Immediates
(define_constraint "I"
"A signed 16-bit immediate in the range -32768 to 32767."
diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c
index 54c9e804ea5..1eea84f47e0 100644
--- a/gcc/config/or1k/or1k.c
+++ b/gcc/config/or1k/or1k.c
@@ -1226,6 +1226,19 @@ or1k_print_operand (FILE *file, rtx x, int code)
output_operand_lossage ("invalid %%H value");
break;
+case 'd':
+ if (REG_P (x))
+ {
+ if (GET_MODE (x) == DFmode || GET_MODE (x) == DImode)
+ fprintf (file, "%s,%s", reg_names[REGNO (operand)],
+ reg_names[REGNO (operand) + 1]);
+ else
+ fprintf (file, "%s", reg_names[REGNO (operand)]);
+ }
+ else
+ output_operand_lossage ("invalid %%d value");
+ break;
+
case 'h':
print_reloc (file, x, 0, RKIND_HI);
break;
@@ -1435,21 +1448,42 @@ void
or1k_expand_compare (rtx *operands)
{
rtx sr_f = gen_rtx_REG (BImode, SR_F_REGNUM);
+ rtx_code cmp_code = GET_CODE (operands[0]);
+ bool flag_check_ne = true;
/* The RTL may receive an immediate in argument 1 of the compare, this is not
supported unless we have l.sf*i instructions, force them into registers.
*/
if (!TARGET_SFIMM)
XEXP (operands[0], 1) = force_reg (SImode, XEXP (operands[0], 1));
+ /* Normalize comparison operators to ones OpenRISC support. */
+ switch
[PATCH v3 1/5] or1k: Fix code quality for volatile memory loads
Volatile memory does not match the memory_operand predicate. This
causes extra extend/mask instructions instructions when reading
from volatile memory. On OpenRISC loading volatile memory can be
treated the same as regular memory loads which supports combined
sign/zero extends. Fixing this eliminates the need for extra
extend/mask instructions.
This also adds a test provided by Richard Selvaggi which uncovered the
issue while we were looking into another issue.
gcc/ChangeLog:
PR target/90363
* config/or1k/or1k.md (zero_extendsi2): Update predicate.
(extendsi2): Update predicate.
* gcc/config/or1k/predicates.md (volatile_mem_operand): New.
(reg_or_mem_operand): New.
gcc/testsuite/ChangeLog:
PR target/90363
* gcc.target/or1k/swap-1.c: New test.
* gcc.target/or1k/swap-2.c: New test.
---
Changes since v2:
- Fix comment format issue, pointed out by Segher
gcc/config/or1k/or1k.md| 6 +--
gcc/config/or1k/predicates.md | 18 +++
gcc/testsuite/gcc.target/or1k/swap-1.c | 70 ++
gcc/testsuite/gcc.target/or1k/swap-2.c | 47 +
4 files changed, 138 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/or1k/swap-1.c
create mode 100644 gcc/testsuite/gcc.target/or1k/swap-2.c
diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md
index 2dad51cd46b..757d899c442 100644
--- a/gcc/config/or1k/or1k.md
+++ b/gcc/config/or1k/or1k.md
@@ -328,11 +328,11 @@
;; Sign Extending
;; -
-;; Zero extension can always be done with AND and an extending load.
+;; Zero extension can always be done with AND or an extending load.
(define_insn "zero_extendsi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (zero_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))]
+ (zero_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))]
""
"@
l.andi\t%0, %1,
@@ -344,7 +344,7 @@
(define_insn "extendsi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (sign_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))]
+ (sign_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))]
"TARGET_SEXT"
"@
l.exts\t%0, %1
diff --git a/gcc/config/or1k/predicates.md b/gcc/config/or1k/predicates.md
index 879236bca49..dad1c5d4be3 100644
--- a/gcc/config/or1k/predicates.md
+++ b/gcc/config/or1k/predicates.md
@@ -82,3 +82,21 @@
(define_predicate "equality_comparison_operator"
(match_code "ne,eq"))
+
+;; Borrowed from rs6000
+;; Return true if the operand is in volatile memory. Note that during the
+;; RTL generation phase, memory_operand does not return TRUE for volatile
+;; memory references. So this function allows us to recognize volatile
+;; references where it's safe.
+(define_predicate "volatile_mem_operand"
+ (and (match_code "mem")
+ (match_test "MEM_VOLATILE_P (op)")
+ (if_then_else (match_test "reload_completed")
+(match_operand 0 "memory_operand")
+(match_test "memory_address_p (mode, XEXP (op, 0))"
+
+;; Return true if the operand is a register or memory; including volatile
+;; memory.
+(define_predicate "reg_or_mem_operand"
+ (ior (match_operand 0 "nonimmediate_operand")
+ (match_operand 0 "volatile_mem_operand")))
diff --git a/gcc/testsuite/gcc.target/or1k/swap-1.c
b/gcc/testsuite/gcc.target/or1k/swap-1.c
new file mode 100644
index 000..4c179d1e430
--- /dev/null
+++ b/gcc/testsuite/gcc.target/or1k/swap-1.c
@@ -0,0 +1,70 @@
+/* { dg-do run } */
+/* { dg-options "-Os -mhard-mul -msoft-div -msoft-float" } */
+
+/* Notes:
+
+ This test failed on or1k GCC 7.2.0, and passes on or1k GCC 5.3.0
+ as well as the or1k port released in GCC 9.1.
+
+ The main program is organized as a loop structure so gcc does not
+ optimize-away the calls to swap_1(). Compiling with -O2 is still smart
+ enough to optimize-away the calls, but using -Os does not.
+ The bad code is only generated when compiled with -Os.
+
+ When the bad code is generated all code is okay except for the very last
+ instruction (a 'l.addc' in the l.jr delay slot).
+ Up to that point in execution, r11 and r12 contain the correct (expected)
+ values, but the execution of the final "l.addc" corrupts r11.
+
+ This test is added to ensure this does not come back. */
+
+#include
+
+volatile static uint8_t g_doswap = 1;
+
+uint64_t swap_1 (uint64_t u64) {
+ uint32_t u64_lo, u64_hi, u64_tmp;
+
+ u64_lo = u64 & 0x;
+ u64_hi = u64 >> 32;
+
+ if (g_doswap)
+{
+ u64_tmp = u64_lo;
+ u64_lo = u64_hi;
+ u64_hi = u64_tmp;
+}
+
+ u64 = u64_lo;
+ u64 += ((uint64_t) u64_hi << 32);
+
+ return u64;
+}
+
+int main () {
+ int ret;
+ int iter;
+ uint64_t aa[2]; // inputs to swap function
+ uint64_t ee[2]; // expected
[PATCH v3 0/5] OpenRISC updates for 10 (fpu, fixes)
Hello, New since v2: - Fix comment formatting pointed out by Segher in valatile patch - Fix issue and add test for rotrsi3 options pointed out by Segher - Fix issue with reg mask for doubles being backwards Pointed out by Segher and Richard. New since v1: - Changed 64-bit FPU operations to use explicit register pairs as per spec revision suggested by Richard Henderson. - Added patch for new -mrori option - Added patch for msoft-div fix from other series (no changes) - Fixed volatile spelling pointed out by Bernhard Reutner-Fischer This is a set of patches to bring FPU support to the OpenRISC backend. The backend also add support for 64-bit floating point operations on 32-bit cores using register pairs, see orfpx64a32 [0]. This binutils patches are already upstream. The toolchain has been tested using the gcc and binutils testsuites as well as floating point test suites running on sim and an fpga soft core or1k_marocchino. [1] I have also included a few fixes to PRs: - 90362 or1k: Soft divide does not work correctly - 90363 or1k: Extra mask insn after load from memory This whole patch series can be found on my github repo [2] as well. If all is OK, I plan to commit these to master (gcc 10). Then back port the PR fixes to the GCC 9 branch, I will ask for guidance when I start to do the backporting. -Stafford [0] https://openrisc.io/proposals/orfpx64a32 [1] https://github.com/openrisc/or1k_marocchino [2] g...@github.com:stffrdhrn/gcc.git or1k-fpu-3 *** BLURB HERE *** Stafford Horne (5): or1k: Fix code quality for volatile memory loads or1k: Fix issues with msoft-div or1k: Add mrori option, fix option docs or1k: Initial support for FPU or1k: only force reg for immediates gcc/config.gcc| 2 + gcc/config/or1k/constraints.md| 4 + gcc/config/or1k/elf.opt | 6 +- gcc/config/or1k/or1k.c| 50 +++-- gcc/config/or1k/or1k.h| 3 + gcc/config/or1k/or1k.md | 131 -- gcc/config/or1k/or1k.opt | 78 + gcc/config/or1k/predicates.md | 30 + gcc/doc/invoke.texi | 77 - gcc/testsuite/gcc.target/or1k/div-mul-3.c | 31 + gcc/testsuite/gcc.target/or1k/ror-4.c | 8 ++ gcc/testsuite/gcc.target/or1k/ror-5.c | 9 ++ gcc/testsuite/gcc.target/or1k/shftimm-1.c | 8 +- gcc/testsuite/gcc.target/or1k/swap-1.c| 70 gcc/testsuite/gcc.target/or1k/swap-2.c| 47 libgcc/config/or1k/lib1funcs.S| 6 +- 16 files changed, 484 insertions(+), 76 deletions(-) create mode 100644 gcc/testsuite/gcc.target/or1k/div-mul-3.c create mode 100644 gcc/testsuite/gcc.target/or1k/ror-4.c create mode 100644 gcc/testsuite/gcc.target/or1k/ror-5.c create mode 100644 gcc/testsuite/gcc.target/or1k/swap-1.c create mode 100644 gcc/testsuite/gcc.target/or1k/swap-2.c -- 2.21.0
Re: [PATCH v2 3/5] or1k: Add mrori option, fix option docs
On Wed, Jul 03, 2019 at 05:26:58PM -0500, Segher Boessenkool wrote:
> On Thu, Jul 04, 2019 at 06:49:17AM +0900, Stafford Horne wrote:
> > On Wed, Jul 03, 2019 at 09:49:02AM -0500, Segher Boessenkool wrote:
> > > On Wed, Jul 03, 2019 at 12:33:49PM +0900, Stafford Horne wrote:
> > > > @@ -179,11 +183,11 @@
> > > >[(set (match_operand:SI 0 "register_operand" "=r,r")
> > > > (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
> > > > (match_operand:SI 2 "reg_or_u6_operand" "r,n")))]
> > > > - "TARGET_ROR"
> > > > + "TARGET_ROR || TARGET_RORI"
> > > >"@
> > > > l.ror\t%0, %1, %2
> > > > l.rori\t%0, %1, %2"
> > > > - [(set_attr "insn_support" "*,shftimm")])
> > > > + [(set_attr "insn_support" "ror,rori")])
> > >
> > > Does this work? If you use -mno-ror -mrori? It will then allow
> > > generating
> > > a reg for the second operand, and ICE later on, as far as I can see?
> >
> > It does seem to work. Why would it produce an internal compiler error?
> >
> > One thing I have is RegectNegative on mror and mrori, so -mno-ror will not
> > be
> > allowed and cause an error.
>
> But both options are off by default, and neither is enabled or disabled
> based on the setting of the other.
>
> > Example:
> >
> > $ cat ./gcc/testsuite/gcc.target/or1k/ror-4.c
> >
> > unsigned int rotate6 (unsigned int a) {
> > return ( a >> 6 ) | ( a << ( 32 - 6 ) );
> > }
>
> That's a fixed distance rotate. My question is will it work if the
> distance is a variable. The other direction should work fine, agreed.
>
> So, does ror-[12].c work with -mrori and no -mror? The predicates say
> this insn pattern is just fine in that case, but the constraints will
> disagree.
OK, yes I see it now. Sorry I mis-understood what you meant by second argument.
I will fix. It's probably going to be easiest to split this to 2 instructions.
-Stafford
Re: [OpenRISC] [PATCH v2 4/5] or1k: Initial support for FPU
On Wed, Jul 03, 2019 at 09:09:51PM +0200, Richard Henderson wrote:
> On 7/3/19 5:43 PM, Segher Boessenkool wrote:
> >> @@ -212,6 +214,7 @@ enum reg_class
> >> #define REG_CLASS_CONTENTS \
> >> { { 0x, 0x }, \
> >>{ SIBCALL_REGS_MASK, 0 }, \
> >> + { 0x7efe, 0x }, \
> >
> > Above you said r0, r30, r31 are excluded, but this is r0, r8, r30, or
> > in GCC register numbers, 0, 8, and 31? You probably should mention r8
> > somewhere (it's because it is the last arg, this avoid problems, I guess?),
> > and the 30/31 thing is confused some way. Maybe it is all just that one
> > documentation line :-)
>
> ... and if r8 is excluded because of arguments, I suspect that this is the
> wrong fix, as there's nothing inherently wrong with r7:r8 or r8:r9 as a pair,
> at least that I can see.
>
> Perhaps function_arg and/or function_arg_advance is the right place for a fix?
> The calling convention says that 64-bit arguments are not split across
> registers+stack, so you already shouldn't have seen (r8, [sp+0]) as a pair.
I will double check, the mask may be wrong. It should not matter about the
function args.
I didn't see any issue that caused me to add r8. So I may have just masked thw
rong bit thinking it's r31. Is there something worng with what I did?
The mask is 0x7efe, and names should corresbond to this name list?
#define REGISTER_NAMES {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", # 7e, excl r0
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", # ff, excl none
"r17", "r19", "r21", "r23", "r25", "r27", "r29", "r31", # fe, excl r31
"r16", "r18", "r20", "r22", "r24", "r26", "r28", "r30", # fe, excl r30
"?ap", "?fp", "?sr_f" }
Do I have it backwards? With an endian issue?
-Stafford
Re: [PATCH v2 4/5] or1k: Initial support for FPU
On Wed, Jul 03, 2019 at 10:43:01AM -0500, Segher Boessenkool wrote:
> Hi Stafford,
>
> On Wed, Jul 03, 2019 at 12:33:50PM +0900, Stafford Horne wrote:
> > +case 'd':
> > + if (REG_P (x))
> > + if (GET_MODE (x) == DFmode || GET_MODE (x) == DImode)
> > + fprintf (file, "%s,%s", reg_names[REGNO (operand)],
> > + reg_names[REGNO (operand) + 1]);
> > + else
> > + fprintf (file, "%s", reg_names[REGNO (operand)]);
> > + else
>
> The coding conventions says to use braces around nested conditionals.
Right I will fix that. Interestingly the indentation is correct just missing
the braces.
> > @@ -212,6 +214,7 @@ enum reg_class
> > #define REG_CLASS_CONTENTS \
> > { { 0x, 0x }, \
> >{ SIBCALL_REGS_MASK, 0 }, \
> > + { 0x7efe, 0x }, \
>
> Above you said r0, r30, r31 are excluded, but this is r0, r8, r30, or
> in GCC register numbers, 0, 8, and 31? You probably should mention r8
> somewhere (it's because it is the last arg, this avoid problems, I guess?),
> and the 30/31 thing is confused some way. Maybe it is all just that one
> documentation line :-)
>
> > +; d - double pair base registers (excludes r0, r30 and r31 which overflow)
Hmm, maybe I messed up the mask. It should be r0, r30 and r31. Register pairs
can be a base register (rX) with a +1 or +2 offset second register.
Registers not allowed
- r0, because its reserved for hardwired zero and doesn't work as a double
zero when paired with a general register.
- r31, because it cant pair with r32 or r33 (those are overflows)
- r30, because it cant work when paried with r32 (its an overflow), it would
work with r31, but GCC will not generate that pair anyway.
-Stafford
Re: [PATCH v2 3/5] or1k: Add mrori option, fix option docs
On Wed, Jul 03, 2019 at 09:49:02AM -0500, Segher Boessenkool wrote:
> On Wed, Jul 03, 2019 at 12:33:49PM +0900, Stafford Horne wrote:
> > @@ -179,11 +183,11 @@
> >[(set (match_operand:SI 0 "register_operand" "=r,r")
> > (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
> > (match_operand:SI 2 "reg_or_u6_operand" "r,n")))]
> > - "TARGET_ROR"
> > + "TARGET_ROR || TARGET_RORI"
> >"@
> > l.ror\t%0, %1, %2
> > l.rori\t%0, %1, %2"
> > - [(set_attr "insn_support" "*,shftimm")])
> > + [(set_attr "insn_support" "ror,rori")])
>
> Does this work? If you use -mno-ror -mrori? It will then allow generating
> a reg for the second operand, and ICE later on, as far as I can see?
It does seem to work. Why would it produce an internal compiler error?
One thing I have is RegectNegative on mror and mrori, so -mno-ror will not be
allowed and cause an error.
Example:
$ cat ./gcc/testsuite/gcc.target/or1k/ror-4.c
unsigned int rotate6 (unsigned int a) {
return ( a >> 6 ) | ( a << ( 32 - 6 ) );
}
# With rori, direct immediate.
$ or1k-elf-gcc -O2 -c -mrori ./gcc/testsuite/gcc.target/or1k/ror-4.c
$ or1k-elf-objdump -d ror-4.o
ror-4.o: file format elf32-or1k
Disassembly of section .text:
:
0: 44 00 48 00 l.jr r9
4: b9 63 00 c6 l.rori r11,r3,0x6
# With ror, loading immediate to temporary register first.
$ or1k-elf-gcc -O2 -c -mror ./gcc/testsuite/gcc.target/or1k/ror-4.c
$ or1k-elf-objdump -d ror-4.o
ror-4.o: file format elf32-or1k
Disassembly of section .text:
:
0: aa 20 00 06 l.ori r17,r0,0x6
4: 44 00 48 00 l.jr r9
8: e1 63 88 c8 l.ror r11,r3,r17
-Stafford
[PATCH v2 5/5] or1k: only force reg for immediates
The force_reg in or1k_expand_compare is hard coded for SImode, which is fine as
this used to only be used on SI expands. However, with FP support this will
cause issues. In general we should only force the right hand operand to a
register if its an immediate. This patch adds an condition to check for that.
gcc/ChangeLog:
* config/or1k/or1k.c (or1k_expand_compare): Check for int before
force_reg.
---
Changes since v1:
- none
gcc/config/or1k/or1k.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c
index d90826b75ca..e4aff83cec7 100644
--- a/gcc/config/or1k/or1k.c
+++ b/gcc/config/or1k/or1k.c
@@ -1446,13 +1446,15 @@ void
or1k_expand_compare (rtx *operands)
{
rtx sr_f = gen_rtx_REG (BImode, SR_F_REGNUM);
+ rtx righthand_op = XEXP (operands[0], 1);
rtx_code cmp_code = GET_CODE (operands[0]);
bool flag_check_ne = true;
- /* The RTL may receive an immediate in argument 1 of the compare, this is not
- supported unless we have l.sf*i instructions, force them into registers.
*/
- if (!TARGET_SFIMM)
-XEXP (operands[0], 1) = force_reg (SImode, XEXP (operands[0], 1));
+ /* Integer RTL may receive an immediate in argument 1 of the compare, this is
+ not supported unless we have l.sf*i instructions, force them into
+ registers. */
+ if (!TARGET_SFIMM && CONST_INT_P (righthand_op))
+XEXP (operands[0], 1) = force_reg (SImode, righthand_op);
/* Normalize comparison operators to ones OpenRISC support. */
switch (cmp_code)
--
2.21.0
[PATCH v2 4/5] or1k: Initial support for FPU
This adds support for OpenRISC hardware floating point instructions.
This is enabled with the -mhard-float option.
Double-prevision floating point operations work using register pairing as
specified in: https://openrisc.io/proposals/orfpx64a32. This has just been
added in the OpenRISC architecture specification 1.3.
This is enabled with the -mdouble-float option.
Not all architectures support unordered comparisons so an option,
-munordered-float is added.
Currently OpenRISC does not support sf/df or df/sf conversions, but this has
also just been added in architecture specification 1.3.
gcc/ChangeLog:
* config.gcc (or1k*-*-*): Add mhard-float, mdouble-float, msoft-float
and munordered-float validations.
* config/or1k/constraints.md (d): New register constraint.
* config/or1k/predicates.md (fp_comparison_operator): New.
* config/or1k/or1k.c (or1k_print_operand): Add support for printing 'd'
operands.
(or1k_expand_compare): Normalize unordered comparisons.
* config/or1k/or1k.h (reg_class): Define DOUBLE_REGS.
(REG_CLASS_NAMES): Add "DOUBLE_REGS".
(REG_CLASS_CONTENTS): Add contents for DOUBLE_REGS.
* config/or1k/or1k.md (type): Add fpu.
(fpu): New instruction reservation.
(F, f, fr, fi, FI, FOP, fop): New.
(3): New ALU instruction definition.
(float2): New conversion instruction definition.
(fix_trunc2): New conversion instruction definition.
(fpcmpcc): New code iterator.
(*sf_fp_insn): New instruction definition.
(cstore4): New expand definition.
(cbranch4): New expand definition.
* config/or1k/or1k.opt (msoft-float, mhard-float, mdouble-float,
munordered-float): New options.
* doc/invoke.texi: Document msoft-float, mhard-float, mdouble-float and
munordered-float.
---
Changes since v1:
- User register pairs for 64-bit ops. See or1k_print_operand
gcc/config.gcc | 1 +
gcc/config/or1k/constraints.md | 4 ++
gcc/config/or1k/or1k.c | 36 ++-
gcc/config/or1k/or1k.h | 3 +
gcc/config/or1k/or1k.md| 111 -
gcc/config/or1k/or1k.opt | 22 +++
gcc/config/or1k/predicates.md | 5 ++
gcc/doc/invoke.texi| 21 +++
8 files changed, 199 insertions(+), 4 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index aeab8b4544e..1678109131f 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -2579,6 +2579,7 @@ or1k*-*-*)
case ${or1k_multilib} in
mcmov | msext | msfimm | \
mror | mrori | \
+ mhard-float | mdouble-float | munordered-float | msoft-float | \
mhard-div | mhard-mul | \
msoft-div | msoft-mul )
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG},${or1k_multilib}"
diff --git a/gcc/config/or1k/constraints.md b/gcc/config/or1k/constraints.md
index 93da8c058c6..8cac7eb5329 100644
--- a/gcc/config/or1k/constraints.md
+++ b/gcc/config/or1k/constraints.md
@@ -24,6 +24,7 @@
; We use:
; c - sibcall registers
+; d - double pair base registers (excludes r0, r30 and r31 which overflow)
; I - constant signed 16-bit
; K - constant unsigned 16-bit
; M - constant signed 16-bit shifted left 16-bits (l.movhi)
@@ -32,6 +33,9 @@
(define_register_constraint "c" "SIBCALL_REGS"
"Registers which can hold a sibling call address")
+(define_register_constraint "d" "DOUBLE_REGS"
+ "Registers which can be used for double reg pairs.")
+
;; Immediates
(define_constraint "I"
"A signed 16-bit immediate in the range -32768 to 32767."
diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c
index 54c9e804ea5..d90826b75ca 100644
--- a/gcc/config/or1k/or1k.c
+++ b/gcc/config/or1k/or1k.c
@@ -1226,6 +1226,17 @@ or1k_print_operand (FILE *file, rtx x, int code)
output_operand_lossage ("invalid %%H value");
break;
+case 'd':
+ if (REG_P (x))
+ if (GET_MODE (x) == DFmode || GET_MODE (x) == DImode)
+ fprintf (file, "%s,%s", reg_names[REGNO (operand)],
+ reg_names[REGNO (operand) + 1]);
+ else
+ fprintf (file, "%s", reg_names[REGNO (operand)]);
+ else
+ output_operand_lossage ("invalid %%d value");
+ break;
+
case 'h':
print_reloc (file, x, 0, RKIND_HI);
break;
@@ -1435,21 +1446,42 @@ void
or1k_expand_compare (rtx *operands)
{
rtx sr_f = gen_rtx_REG (BImode, SR_F_REGNUM);
+ rtx_code cmp_code = GET_CODE (operands[0]);
+ bool flag_check_ne = true;
/* The RTL may receive an immediate in argument 1 of the compare, this is not
supported unless we have l.sf*i instructions, force them into registers.
*/
if (!TARGET_SFIMM)
XEXP (operands[0], 1) = force_reg (SImode, XEXP (operands[0], 1));
+ /* Normalize comparison operators to ones OpenRISC support. */
+
[PATCH v2 3/5] or1k: Add mrori option, fix option docs
gcc/ChangeLog:
* config.gcc (or1k*-*-*): Add mrori and mror to validation.
* doc/invoke.texi (OpenRISC Options): Add mrori option, rewrite all
documenation to be more clear.
* config/or1k/elf.opt (mboard=, mnewlib): Rewrite documentation to be
more clear.
* config/or1k/or1k.opt (mrori): New option.
(mhard-div, msoft-div, mhard-mul, msoft-mul, mcmov, mror, msext,
msfimm, mshftimm): Rewrite documentation to be more clear.
* config/or1k/or1k.md (insn_support): Add ror and rori.
(enabled): Add conditions for ror and rori.
(rotrsi3): Replace condition for shftimm with ror and rori.
gcc/testsuite/ChangeLog:
* gcc.target/or1k/ror-4.c: New file.
* gcc.target/or1k/shftimm-1.c: Update test from rotate to shift
as the shftimm option no longer controls rotate.
---
Changes since v1:
- new patch
gcc/config.gcc| 1 +
gcc/config/or1k/elf.opt | 6 +--
gcc/config/or1k/or1k.md | 12 +++--
gcc/config/or1k/or1k.opt | 56 +--
gcc/doc/invoke.texi | 56 +--
gcc/testsuite/gcc.target/or1k/ror-4.c | 8
gcc/testsuite/gcc.target/or1k/shftimm-1.c | 8 ++--
7 files changed, 87 insertions(+), 60 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/or1k/ror-4.c
diff --git a/gcc/config.gcc b/gcc/config.gcc
index c281c418b28..aeab8b4544e 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -2578,6 +2578,7 @@ or1k*-*-*)
for or1k_multilib in ${or1k_multilibs}; do
case ${or1k_multilib} in
mcmov | msext | msfimm | \
+ mror | mrori | \
mhard-div | mhard-mul | \
msoft-div | msoft-mul )
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG},${or1k_multilib}"
diff --git a/gcc/config/or1k/elf.opt b/gcc/config/or1k/elf.opt
index 641b6ddd4be..2d4d1875d02 100644
--- a/gcc/config/or1k/elf.opt
+++ b/gcc/config/or1k/elf.opt
@@ -25,9 +25,9 @@
mboard=
Target RejectNegative Joined
-Configure board specific runtime.
+Configure the newlib board specific runtime. The default is or1ksim.
mnewlib
Target RejectNegative
-For compatibility, it's always newlib for elf now.
-
+This option is ignored; it is provided for compatibility purposes only. This
+used to select linker and preprocessor options for use with newlib.
diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md
index 757d899c442..bbad593db40 100644
--- a/gcc/config/or1k/or1k.md
+++ b/gcc/config/or1k/or1k.md
@@ -63,7 +63,7 @@
"alu,st,ld,control,multi"
(const_string "alu"))
-(define_attr "insn_support" "class1,sext,sfimm,shftimm" (const_string
"class1"))
+(define_attr "insn_support" "class1,sext,sfimm,shftimm,ror,rori" (const_string
"class1"))
(define_attr "enabled" ""
(cond [(eq_attr "insn_support" "class1") (const_int 1)
@@ -72,7 +72,11 @@
(and (eq_attr "insn_support" "sfimm")
(ne (symbol_ref "TARGET_SFIMM") (const_int 0))) (const_int 1)
(and (eq_attr "insn_support" "shftimm")
- (ne (symbol_ref "TARGET_SHFTIMM") (const_int 0))) (const_int 1)]
+ (ne (symbol_ref "TARGET_SHFTIMM") (const_int 0))) (const_int 1)
+(and (eq_attr "insn_support" "ror")
+ (ne (symbol_ref "TARGET_ROR") (const_int 0))) (const_int 1)
+(and (eq_attr "insn_support" "rori")
+ (ne (symbol_ref "TARGET_RORI") (const_int 0))) (const_int 1)]
(const_int 0)))
;; Describe a user's asm statement.
@@ -179,11 +183,11 @@
[(set (match_operand:SI 0 "register_operand" "=r,r")
(rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
(match_operand:SI 2 "reg_or_u6_operand" "r,n")))]
- "TARGET_ROR"
+ "TARGET_ROR || TARGET_RORI"
"@
l.ror\t%0, %1, %2
l.rori\t%0, %1, %2"
- [(set_attr "insn_support" "*,shftimm")])
+ [(set_attr "insn_support" "ror,rori")])
(define_insn "andsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
diff --git a/gcc/config/or1k/or1k.opt b/gcc/config/or1k/or1k.opt
index 7bdbd842dd4..c2f64c5dd45 100644
--- a/gcc/config/or1k/or1k.opt
+++ b/gcc/config/or1k/or1k.opt
@@ -21,47 +21,55 @@
; See the GCC internals manual (options.texi) for a description of
; this file's format.
-; Please try to keep this file in ASCII collating order.
-
mhard-div
Target RejectNegative InverseMask(SOFT_DIV)
-Use hardware divide instructions, use -msoft-div for emulation.
+Enable generation of hardware divide (l.div, l.divu) instructions. This is the
+default; use -msoft-div to override.
+
+msoft-div
+Target RejectNegative Mask(SOFT_DIV)
+Enable generation of binaries which use functions from libgcc to perform divide
+operations. The default is -mhard-div.
mhard-mul
Target RejectNegative InverseMask(SOFT_MUL).
-Use hardware multiply instructions, use -msoft-mul for emulation.
+Enable
[PATCH v2 2/5] or1k: Fix issues with msoft-div
Fixes bad assembly logic with software divide as reported by Richard Selvaggi.
Also, add a basic test to verify the soft math works when enabled.
gcc/testsuite/ChangeLog:
PR target/90362
* gcc.target/or1k/div-mul-3.c: New test.
libgcc/ChangeLog:
PR target/90362
* config/or1k/lib1funcs.S (__udivsi3): Change l.sfeqi
to l.sfeq and l.sfltsi to l.sflts equivalents as the immediate
instructions are not available on every processor. Change a
l.bnf to l.bf to fix logic issue.
---
Changes since v1:
- none
gcc/testsuite/gcc.target/or1k/div-mul-3.c | 31 +++
libgcc/config/or1k/lib1funcs.S| 6 ++---
2 files changed, 34 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/or1k/div-mul-3.c
diff --git a/gcc/testsuite/gcc.target/or1k/div-mul-3.c
b/gcc/testsuite/gcc.target/or1k/div-mul-3.c
new file mode 100644
index 000..2c4f91b7e98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/or1k/div-mul-3.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msoft-div -msoft-mul" } */
+
+struct testcase {
+ int a;
+ int b;
+ int c;
+ int expected;
+};
+
+struct testcase tests[] = {
+ {2, 200, 3, 133},
+ {3, 300, 3, 300},
+ {2, 500, 3, 333},
+ {4, 250, 3, 333},
+ {0, 0, 0, 0}
+};
+
+int calc (int a, int b, int c) {
+ return a * b / c;
+}
+
+int main () {
+ int fail = 0;
+ struct testcase *tc;
+
+ for (int i = 0; (tc = [i], tc->c); i++)
+fail |= (calc (tc->a, tc->b, tc->c) != tc->expected);
+
+ return fail;
+}
diff --git a/libgcc/config/or1k/lib1funcs.S b/libgcc/config/or1k/lib1funcs.S
index d2103923486..6d058977229 100644
--- a/libgcc/config/or1k/lib1funcs.S
+++ b/libgcc/config/or1k/lib1funcs.S
@@ -68,18 +68,18 @@ __udivmodsi3_internal:
is not clobbered by this routine, and use that as to
save a return address without creating a stack frame. */
- l.sfeqi r4, 0 /* division by zero; return 0. */
+ l.sfeq r4, r0 /* division by zero; return 0. */
l.ori r11, r0, 0 /* initial quotient */
l.bf9f
l.ori r12, r3, 0 /* initial remainder */
/* Given X/Y, shift Y left until Y >= X. */
l.ori r6, r0, 1 /* mask = 1 */
-1: l.sfltsir4, 0 /* y has msb set */
+1: l.sflts r4, r0 /* y has msb set */
l.bf2f
l.sfltur4, r12 /* y < x */
l.add r4, r4, r4 /* y <<= 1 */
- l.bnf 1b
+ l.bf1b
l.add r6, r6, r6 /* mask <<= 1 */
/* Shift Y back to the right again, subtracting from X. */
--
2.21.0
[PATCH v2 1/5] or1k: Fix code quality for volatile memory loads
Volatile memory does not match the memory_operand predicate. This
causes extra extend/mask instructions instructions when reading
from volatile memory. On OpenRISC loading volatile memory can be
treated the same as regular memory loads which supports combined
sign/zero extends. Fixing this eliminates the need for extra
extend/mask instructions.
This also adds a test provided by Richard Selvaggi which uncovered the
issue while we were looking into another issue.
gcc/ChangeLog:
PR target/90363
* config/or1k/or1k.md (zero_extendsi2): Update predicate.
(extendsi2): Update predicate.
* gcc/config/or1k/predicates.md (volatile_mem_operand): New.
(reg_or_mem_operand): New.
gcc/testsuite/ChangeLog:
PR target/90363
* gcc.target/or1k/swap-1.c: New test.
* gcc.target/or1k/swap-2.c: New test.
---
Since v1:
- Fixed typos with volatile
gcc/config/or1k/or1k.md| 6 +--
gcc/config/or1k/predicates.md | 18 +++
gcc/testsuite/gcc.target/or1k/swap-1.c | 70 ++
gcc/testsuite/gcc.target/or1k/swap-2.c | 47 +
4 files changed, 138 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/or1k/swap-1.c
create mode 100644 gcc/testsuite/gcc.target/or1k/swap-2.c
diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md
index 2dad51cd46b..757d899c442 100644
--- a/gcc/config/or1k/or1k.md
+++ b/gcc/config/or1k/or1k.md
@@ -328,11 +328,11 @@
;; Sign Extending
;; -
-;; Zero extension can always be done with AND and an extending load.
+;; Zero extension can always be done with AND or an extending load.
(define_insn "zero_extendsi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (zero_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))]
+ (zero_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))]
""
"@
l.andi\t%0, %1,
@@ -344,7 +344,7 @@
(define_insn "extendsi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (sign_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))]
+ (sign_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))]
"TARGET_SEXT"
"@
l.exts\t%0, %1
diff --git a/gcc/config/or1k/predicates.md b/gcc/config/or1k/predicates.md
index 879236bca49..b895f1b4228 100644
--- a/gcc/config/or1k/predicates.md
+++ b/gcc/config/or1k/predicates.md
@@ -82,3 +82,21 @@
(define_predicate "equality_comparison_operator"
(match_code "ne,eq"))
+
+;; Borrowed from rs6000
+; Return true if the operand is in volatile memory. Note that during the
+;; RTL generation phase, memory_operand does not return TRUE for volatile
+;; memory references. So this function allows us to recognize volatile
+;; references where it's safe.
+(define_predicate "volatile_mem_operand"
+ (and (match_code "mem")
+ (match_test "MEM_VOLATILE_P (op)")
+ (if_then_else (match_test "reload_completed")
+(match_operand 0 "memory_operand")
+(match_test "memory_address_p (mode, XEXP (op, 0))"
+
+;; Return true if the operand is a register or memory; including volatile
+;; memory.
+(define_predicate "reg_or_mem_operand"
+ (ior (match_operand 0 "nonimmediate_operand")
+ (match_operand 0 "volatile_mem_operand")))
diff --git a/gcc/testsuite/gcc.target/or1k/swap-1.c
b/gcc/testsuite/gcc.target/or1k/swap-1.c
new file mode 100644
index 000..4c179d1e430
--- /dev/null
+++ b/gcc/testsuite/gcc.target/or1k/swap-1.c
@@ -0,0 +1,70 @@
+/* { dg-do run } */
+/* { dg-options "-Os -mhard-mul -msoft-div -msoft-float" } */
+
+/* Notes:
+
+ This test failed on or1k GCC 7.2.0, and passes on or1k GCC 5.3.0
+ as well as the or1k port released in GCC 9.1.
+
+ The main program is organized as a loop structure so gcc does not
+ optimize-away the calls to swap_1(). Compiling with -O2 is still smart
+ enough to optimize-away the calls, but using -Os does not.
+ The bad code is only generated when compiled with -Os.
+
+ When the bad code is generated all code is okay except for the very last
+ instruction (a 'l.addc' in the l.jr delay slot).
+ Up to that point in execution, r11 and r12 contain the correct (expected)
+ values, but the execution of the final "l.addc" corrupts r11.
+
+ This test is added to ensure this does not come back. */
+
+#include
+
+volatile static uint8_t g_doswap = 1;
+
+uint64_t swap_1 (uint64_t u64) {
+ uint32_t u64_lo, u64_hi, u64_tmp;
+
+ u64_lo = u64 & 0x;
+ u64_hi = u64 >> 32;
+
+ if (g_doswap)
+{
+ u64_tmp = u64_lo;
+ u64_lo = u64_hi;
+ u64_hi = u64_tmp;
+}
+
+ u64 = u64_lo;
+ u64 += ((uint64_t) u64_hi << 32);
+
+ return u64;
+}
+
+int main () {
+ int ret;
+ int iter;
+ uint64_t aa[2]; // inputs to swap function
+ uint64_t ee[2]; // expected outputs of swap function
+
[PATCH v2 0/5] OpenRISC updates for 10 (fpu, fixes)
Hello, It's been about 2 months since I last sent these patches. Sorry for the delay I ended up getting side tracked finishing the new OpenRISC architecture spec revision. New since v1: - Changed 64-bit FPU operations to use explicit register pairs as per spec revision suggested by Richard Henderson. - Added patch for new -mrori option - Added patch for msoft-div fix from other series (no changes) - Fixed volatile spelling pointed out by Bernhard Reutner-Fischer This is a set of patches to bring FPU support to the OpenRISC backend. The backend also add support for 64-bit floating point operations on 32-bit cores using register pairs, see orfpx64a32 [0]. This binutils patches are already upstream. The toolchain has been tested using the gcc and binutils testsuites as well as floating point test suites running on sim and an fpga soft core or1k_marocchino. [1] I have also included a few fixes to PRs: - 90362 or1k: Soft divide does not work correctly - 90363 or1k: Extra mask insn after load from memory This whole patch series can be found on my github repo [2] as well. If all is OK, I plan to commit these to master (gcc 10). Then back port the PR fixes to the GCC 9 branch, I will ask for guidance when I start to do the backporting. -Stafford [0] https://openrisc.io/proposals/orfpx64a32 [1] https://github.com/openrisc/or1k_marocchino [2] g...@github.com:stffrdhrn/gcc.git or1k-fpu-2 Stafford Horne (5): or1k: Fix code quality for volatile memory loads or1k: Fix issues with msoft-div or1k: Add mrori option, fix option docs or1k: Initial support for FPU or1k: only force reg for immediates gcc/config.gcc| 2 + gcc/config/or1k/constraints.md| 4 + gcc/config/or1k/elf.opt | 6 +- gcc/config/or1k/or1k.c| 48 ++-- gcc/config/or1k/or1k.h| 3 + gcc/config/or1k/or1k.md | 129 -- gcc/config/or1k/or1k.opt | 78 + gcc/config/or1k/predicates.md | 23 gcc/doc/invoke.texi | 77 - gcc/testsuite/gcc.target/or1k/div-mul-3.c | 31 ++ gcc/testsuite/gcc.target/or1k/ror-4.c | 8 ++ gcc/testsuite/gcc.target/or1k/shftimm-1.c | 8 +- gcc/testsuite/gcc.target/or1k/swap-1.c| 70 gcc/testsuite/gcc.target/or1k/swap-2.c| 47 libgcc/config/or1k/lib1funcs.S| 6 +- 15 files changed, 465 insertions(+), 75 deletions(-) create mode 100644 gcc/testsuite/gcc.target/or1k/div-mul-3.c create mode 100644 gcc/testsuite/gcc.target/or1k/ror-4.c create mode 100644 gcc/testsuite/gcc.target/or1k/swap-1.c create mode 100644 gcc/testsuite/gcc.target/or1k/swap-2.c -- 2.21.0
Re: [PATCH 1/2] or1k: Fix code quality for volatile memory loads
On Thu, May 09, 2019 at 07:44:15PM +0200, Bernhard Reutner-Fischer wrote: > On 6 May 2019 15:16:20 CEST, Stafford Horne wrote: > >Volatile memory does not match the memory_operand predicate. This > >causes extra extend/mask instructions instructions when reading > >from volatile memory. On OpenRISC loading volitile memory can be > > s/volitile/volatile/g > > also at least in the test. > Thanks, Thank you, I always mispell that one. -Stafford > > >diff --git a/gcc/testsuite/gcc.target/or1k/swap-2.c > >b/gcc/testsuite/gcc.target/or1k/swap-2.c > >new file mode 100644 > >index 000..8ddea4e659f > >--- /dev/null > >+++ b/gcc/testsuite/gcc.target/or1k/swap-2.c > > >+/* Check to ensure the volitile load does not get zero extended. */ >
[PATCH 2/2] or1k: Fix issues with msoft-div
As reported by Richard Selvaggi. Also, add a basic test to verify the
soft math works when enabled.
gcc/testsuite/ChangeLog:
PR target/90362
* gcc.target/or1k/div-mul-3.c: New test.
libgcc/ChangeLog:
PR target/90362
* config/or1k/lib1funcs.S (__udivsi3): Change l.sfeqi
to l.sfeq and l.sfltsi to l.sflts equivalents as the immediate
instructions are not available on every processor. Change a
l.bnf to l.bf to fix logic issue.
---
gcc/testsuite/gcc.target/or1k/div-mul-3.c | 31 +++
libgcc/config/or1k/lib1funcs.S| 6 ++---
2 files changed, 34 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/or1k/div-mul-3.c
diff --git a/gcc/testsuite/gcc.target/or1k/div-mul-3.c
b/gcc/testsuite/gcc.target/or1k/div-mul-3.c
new file mode 100644
index 000..2c4f91b7e98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/or1k/div-mul-3.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msoft-div -msoft-mul" } */
+
+struct testcase {
+ int a;
+ int b;
+ int c;
+ int expected;
+};
+
+struct testcase tests[] = {
+ {2, 200, 3, 133},
+ {3, 300, 3, 300},
+ {2, 500, 3, 333},
+ {4, 250, 3, 333},
+ {0, 0, 0, 0}
+};
+
+int calc (int a, int b, int c) {
+ return a * b / c;
+}
+
+int main () {
+ int fail = 0;
+ struct testcase *tc;
+
+ for (int i = 0; (tc = [i], tc->c); i++)
+fail |= (calc (tc->a, tc->b, tc->c) != tc->expected);
+
+ return fail;
+}
diff --git a/libgcc/config/or1k/lib1funcs.S b/libgcc/config/or1k/lib1funcs.S
index d2103923486..6d058977229 100644
--- a/libgcc/config/or1k/lib1funcs.S
+++ b/libgcc/config/or1k/lib1funcs.S
@@ -68,18 +68,18 @@ __udivmodsi3_internal:
is not clobbered by this routine, and use that as to
save a return address without creating a stack frame. */
- l.sfeqi r4, 0 /* division by zero; return 0. */
+ l.sfeq r4, r0 /* division by zero; return 0. */
l.ori r11, r0, 0 /* initial quotient */
l.bf9f
l.ori r12, r3, 0 /* initial remainder */
/* Given X/Y, shift Y left until Y >= X. */
l.ori r6, r0, 1 /* mask = 1 */
-1: l.sfltsir4, 0 /* y has msb set */
+1: l.sflts r4, r0 /* y has msb set */
l.bf2f
l.sfltur4, r12 /* y < x */
l.add r4, r4, r4 /* y <<= 1 */
- l.bnf 1b
+ l.bf1b
l.add r6, r6, r6 /* mask <<= 1 */
/* Shift Y back to the right again, subtracting from X. */
--
2.19.1
[PATCH 0/2] OpenRISC fixes
I sent the fix for 90363 previously with the FPU patches. Now, I have added tests and another issue came up, so I am sending as a new series. I planned to commit the code before the 9.x release but missed that. This is a series of fixes for the OpenRISC target found during recent testings. PRs: - 90362 or1k: Soft divide does not work correctly - 90363 or1k: Extra mask insn after load from memory Stafford Horne (2): or1k: Fix code quality for volatile memory loads or1k: Fix issues with msoft-div gcc/config/or1k/or1k.md | 6 +- gcc/config/or1k/predicates.md | 18 + gcc/testsuite/gcc.target/or1k/div-mul-3.c | 31 gcc/testsuite/gcc.target/or1k/swap-1.c| 86 +++ gcc/testsuite/gcc.target/or1k/swap-2.c| 63 + libgcc/config/or1k/lib1funcs.S| 6 +- 6 files changed, 204 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/or1k/div-mul-3.c create mode 100644 gcc/testsuite/gcc.target/or1k/swap-1.c create mode 100644 gcc/testsuite/gcc.target/or1k/swap-2.c -- 2.19.1
[PATCH 1/2] or1k: Fix code quality for volatile memory loads
Volatile memory does not match the memory_operand predicate. This
causes extra extend/mask instructions instructions when reading
from volatile memory. On OpenRISC loading volitile memory can be
treated the same as regular memory loads which supports combined
sign/zero extends. Fixing this eliminates the need for extra
extend/mask instructions.
This also adds a test provided by Richard Selvaggi which uncovered the
issue while we were looking into another issue.
gcc/ChangeLog:
PR target/90363
* config/or1k/or1k.md (zero_extendsi2): Update predicate.
(extendsi2): Update predicate.
* gcc/config/or1k/predicates.md (volatile_mem_operand): New.
(reg_or_mem_operand): New.
gcc/testsuite/ChangeLog:
PR target/90363
* gcc.target/or1k/swap-1.c: New test.
* gcc.target/or1k/swap-2.c: New test.
---
gcc/config/or1k/or1k.md| 6 +-
gcc/config/or1k/predicates.md | 18 ++
gcc/testsuite/gcc.target/or1k/swap-1.c | 86 ++
gcc/testsuite/gcc.target/or1k/swap-2.c | 63 +++
4 files changed, 170 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/or1k/swap-1.c
create mode 100644 gcc/testsuite/gcc.target/or1k/swap-2.c
diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md
index 2dad51cd46b..757d899c442 100644
--- a/gcc/config/or1k/or1k.md
+++ b/gcc/config/or1k/or1k.md
@@ -328,11 +328,11 @@
;; Sign Extending
;; -
-;; Zero extension can always be done with AND and an extending load.
+;; Zero extension can always be done with AND or an extending load.
(define_insn "zero_extendsi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (zero_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))]
+ (zero_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))]
""
"@
l.andi\t%0, %1,
@@ -344,7 +344,7 @@
(define_insn "extendsi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
- (sign_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))]
+ (sign_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))]
"TARGET_SEXT"
"@
l.exts\t%0, %1
diff --git a/gcc/config/or1k/predicates.md b/gcc/config/or1k/predicates.md
index 879236bca49..b895f1b4228 100644
--- a/gcc/config/or1k/predicates.md
+++ b/gcc/config/or1k/predicates.md
@@ -82,3 +82,21 @@
(define_predicate "equality_comparison_operator"
(match_code "ne,eq"))
+
+;; Borrowed from rs6000
+; Return true if the operand is in volatile memory. Note that during the
+;; RTL generation phase, memory_operand does not return TRUE for volatile
+;; memory references. So this function allows us to recognize volatile
+;; references where it's safe.
+(define_predicate "volatile_mem_operand"
+ (and (match_code "mem")
+ (match_test "MEM_VOLATILE_P (op)")
+ (if_then_else (match_test "reload_completed")
+(match_operand 0 "memory_operand")
+(match_test "memory_address_p (mode, XEXP (op, 0))"
+
+;; Return true if the operand is a register or memory; including volatile
+;; memory.
+(define_predicate "reg_or_mem_operand"
+ (ior (match_operand 0 "nonimmediate_operand")
+ (match_operand 0 "volatile_mem_operand")))
diff --git a/gcc/testsuite/gcc.target/or1k/swap-1.c
b/gcc/testsuite/gcc.target/or1k/swap-1.c
new file mode 100644
index 000..233c4b71627
--- /dev/null
+++ b/gcc/testsuite/gcc.target/or1k/swap-1.c
@@ -0,0 +1,86 @@
+/* { dg-do run } */
+/* { dg-options "-Os -mhard-mul -msoft-div -msoft-float" } */
+
+/* Copyright (C) 2018-2019 Free Software Foundation, Inc.
+ Copyright 2019 Broadcom. Richard Selvaggi, 2019-March-27
+ The term "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License, version 2, as
+ published by the Free Software Foundation (the "GPL").
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License version 2 (GPLv2) for more details.
+
+ You should have received a copy of the GNU General Public License
+ version 2 (GPLv2) along with this source code. */
+
+/* Notes:
+
+ This test failed on or1k GCC 7.2.0, and passes on or1k GCC 5.3.0
+ as well as the or1k port released in GCC 9.1.
+
+ The main program is organized as a loop structure so gcc does not
+ optimize-away the calls to swap_1(). Compiling with -O2 is still smart
+ enough to optimize-away the calls, but using -Os does not.
+ The bad code is only generated when compiled with -Os.
+
+ When the bad code is generated all code is okay except for the very last
+ instruction (a
Re: [PATCH 0/3] OpenRISC floating point support + fixes
On Fri, Apr 12, 2019 at 09:28:55AM -0600, Jeff Law wrote: > On 4/10/19 3:27 PM, Stafford Horne wrote: > > Hello, > > > > This is a set of patches to bring FPU support to the OpenRISC backend. The > > backend also add support for 64-bit floating point operations on 32-bit > > cores > > using register pairs, see orfpx64a32 [0]. > > > > This depends on binutils patches which have also been submitted per review. > > [1] > > > > The toolchain has been tested using the gcc and binutils testsuites as well > > as > > floating point test suites running on sim and an fpga soft core > > or1k_marocchino. > > [2] > > > > There is also an unrelated, but trivial patch to fix a code quality issue > > with > > volatile memory loads. > > > > This whole patch series can be found on my github repo [3] as well. > > > > -Stafford > > > > [0] https://openrisc.io/proposals/orfpx64a32 > > [1] g...@github.com:stffrdhrn/binutils-gdb.git orfpx64a32-2 > > [2] https://github.com/openrisc/or1k_marocchino > > [3] g...@github.com:stffrdhrn/gcc.git or1k-fpu-1a > > > > Stafford Horne (3): > > or1k: Initial support for FPU > > or1k: Allow volatile memory for sign/zero extend loads > > or1k: only force reg for immediates > > > > gcc/config.gcc| 1 + > > gcc/config/or1k/or1k.c| 10 ++-- > > gcc/config/or1k/or1k.md | 109 -- > > gcc/config/or1k/or1k.opt | 15 - > > gcc/config/or1k/predicates.md | 16 + > > gcc/doc/invoke.texi | 15 + > > 6 files changed, 156 insertions(+), 10 deletions(-) > > > So the only question is whether or not you're looking to drop this into > gcc-9 or gcc-10. > > gcc-9 is in regression bugfixing stage, so technically this patch should > wait to gcc-10. However, we usually give maintainers a degree of > freedom, particularly if a change doens't "bleed" into generic parts of > the compiler. > > So we'll leave it up to you to decide if you want to add this to gcc-9 > or wait for gcc-10. Hi Jeff, Thanks, I know I sent all the patches together for review. But, I am thinking for gcc-9 I will only be aiming at including 2/3. The others are only needed for FPU support and I can wait for gcc-10. We had a quick discussion about this on irc yesterday too. -Stafford
[PATCH 3/3] or1k: only force reg for immediates
The force_reg in or1k_expand_compare is hard coded for SImode, which is fine as
this used to only be used on SI expands. However, with FP support this will
cause issues. In general we should only force the right hand operand to a
register if its an immediate. This patch adds an condition to check for that.
gcc/ChangeLog:
* config/or1k/or1k.c (or1k_expand_compare): Check for int before
force_reg.
---
gcc/config/or1k/or1k.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c
index fc10fcfabde..35d984533be 100644
--- a/gcc/config/or1k/or1k.c
+++ b/gcc/config/or1k/or1k.c
@@ -1435,11 +1435,13 @@ void
or1k_expand_compare (rtx *operands)
{
rtx sr_f = gen_rtx_REG (BImode, SR_F_REGNUM);
+ rtx righthand_op = XEXP (operands[0], 1);
- /* The RTL may receive an immediate in argument 1 of the compare, this is not
- supported unless we have l.sf*i instructions, force them into registers.
*/
- if (!TARGET_SFIMM)
-XEXP (operands[0], 1) = force_reg (SImode, XEXP (operands[0], 1));
+ /* Integer RTL may receive an immediate in argument 1 of the compare, this is
+ not supported unless we have l.sf*i instructions, force them into
+ registers. */
+ if (!TARGET_SFIMM && CONST_INT_P (righthand_op))
+XEXP (operands[0], 1) = force_reg (SImode, righthand_op);
/* Emit the given comparison into the Flag bit. */
PUT_MODE (operands[0], BImode);
--
2.19.1
[PATCH 1/3] or1k: Initial support for FPU
Or1k only supports ordered compares so we fall back to lib functions
for unordered operations.
Doubles work on this 32-bit architecture by using register pairing as
specified in: https://openrisc.io/proposals/orfpx64a32
Or1k does not support sf/df or df/sf conversions.
gcc/ChangeLog:
* config.gcc (or1k*-*-*): Add mhard-float and mdouble-float validations.
* config/or1k/or1k.md (type): Add fpu.
(fpu): New instruction reservation.
(F, f, fi, FI, FOP, fop): New.
(3): New ALU instruction definition.
(float2): New conversion instruction definition.
(fix_trunc2): New conversion instruction definition.
(fpcmpcc): New code iterator.
(*sf_fp_insn): New instruction definition.
(cstore4): New expand definition.
(cbranch4): New expand definition.
* config/or1k/or1k.opt (msoft-float, mhard-float, mdouble-float): New
options.
* doc/invoke.texi: Document msoft-float, mhard-float and mdouble-float.
---
gcc/config.gcc | 1 +
gcc/config/or1k/or1k.md | 103 ++-
gcc/config/or1k/or1k.opt | 15 +-
gcc/doc/invoke.texi | 15 ++
4 files changed, 131 insertions(+), 3 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index ebbab5d8b6a..8017851922e 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -2541,6 +2541,7 @@ or1k*-*-*)
for or1k_multilib in ${or1k_multilibs}; do
case ${or1k_multilib} in
mcmov | msext | msfimm | \
+ mhard-float | mdouble-float | \
mhard-div | mhard-mul | \
msoft-div | msoft-mul )
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG},${or1k_multilib}"
diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md
index 2dad51cd46b..202493c5ab9 100644
--- a/gcc/config/or1k/or1k.md
+++ b/gcc/config/or1k/or1k.md
@@ -60,7 +60,7 @@
(define_attr "length" "" (const_int 4))
(define_attr "type"
- "alu,st,ld,control,multi"
+ "alu,st,ld,control,multi,fpu"
(const_string "alu"))
(define_attr "insn_support" "class1,sext,sfimm,shftimm" (const_string
"class1"))
@@ -93,6 +93,10 @@
(define_insn_reservation "control" 1
(eq_attr "type" "control")
"cpu")
+(define_insn_reservation "fpu" 2
+ (eq_attr "type" "fpu")
+ "cpu")
+
; Define delay slots for any branch
(define_delay (eq_attr "type" "control")
@@ -155,6 +159,46 @@
""
"l.sub\t%0, %r1, %2")
+;; -
+;; Floating Point Arithmetic instructions
+;; -
+
+;; Mode iterator for single/double float
+(define_mode_iterator F [(SF "TARGET_HARD_FLOAT")
+(DF "TARGET_DOUBLE_FLOAT")])
+(define_mode_attr f [(SF "s") (DF "d")])
+(define_mode_attr fi [(SF "si") (DF "di")])
+(define_mode_attr FI [(SF "SI") (DF "DI")])
+
+;; Basic arithmetic instructions
+(define_code_iterator FOP [plus minus mult div])
+(define_code_attr fop [(plus "add") (minus "sub") (mult "mul") (div "div")])
+
+(define_insn "3"
+ [(set (match_operand:F 0 "register_operand" "=r")
+ (FOP:F (match_operand:F 1 "register_operand" "r")
+ (match_operand:F 2 "register_operand" "r")))]
+ "TARGET_HARD_FLOAT"
+ "lf..\t%0, %1, %2"
+ [(set_attr "type" "fpu")])
+
+;; Basic float<->int conversion
+(define_insn "float2"
+ [(set (match_operand:F 0 "register_operand" "=r")
+ (float:F
+ (match_operand: 1 "register_operand" "r")))]
+ "TARGET_HARD_FLOAT"
+ "lf.itof.\t%0, %1"
+ [(set_attr "type" "fpu")])
+
+(define_insn "fix_trunc2"
+ [(set (match_operand: 0 "register_operand" "=r")
+ (fix:
+ (match_operand:F 1 "register_operand" "r")))]
+ "TARGET_HARD_FLOAT"
+ "lf.ftoi.\t%0, %1"
+ [(set_attr "type" "fpu")])
+
;; -
;; Logical operators
;; -
@@ -388,6 +432,31 @@
l.sfi\t%r0, %1"
[(set_attr "insn_support" "*,sfimm")])
+;; Support FP comparisons too
+
+;; The OpenRISC FPU supports these comparisons:
+;;
+;;lf.sfeq.{d,s} - equality, r r, double or single precision
+;;lf.sfge.{d,s} - greater than or equal, r r, double or single precision
+;;lf.sfgt.{d,s} - greater than, r r, double or single precision
+;;lf.sfle.{d,s} - less than or equal, r r, double or single precision
+;;lf.sflt.{d,s} - less than, r r, double or single precision
+;;lf.sfne.{d,s} - not equal, r r, double or single precision
+;;
+;; Double precision is only supported on some hardware. Only register/register
+;; comparisons are supported. All comparisons are signed.
+
+(define_code_iterator fpcmpcc [ne eq lt gt ge le])
+
+(define_insn "*sf_fp_insn"
+ [(set (reg:BI SR_F_REGNUM)
+ (fpcmpcc:BI (match_operand:F 0 "register_operand" "r")
+
[PATCH 2/3] or1k: Allow volatile memory for sign/zero extend loads
Volatile memory does not match the memory_operand predicate. This causes extra extend/mask instructions instructions when reading from volatile memory. On OpenRISC this can be treated the same as regular memory. gcc/ChangeLog: * config/or1k/or1k.md (zero_extendsi2): Update predicate. (extendsi2): Update predicate. * gcc/config/or1k/predicates.md (volatile_mem_operand): New. (reg_or_mem_operand): New. --- gcc/config/or1k/or1k.md | 6 +++--- gcc/config/or1k/predicates.md | 16 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/gcc/config/or1k/or1k.md b/gcc/config/or1k/or1k.md index 202493c5ab9..23ded94feb3 100644 --- a/gcc/config/or1k/or1k.md +++ b/gcc/config/or1k/or1k.md @@ -372,11 +372,11 @@ ;; Sign Extending ;; - -;; Zero extension can always be done with AND and an extending load. +;; Zero extension can always be done with AND or an extending load. (define_insn "zero_extendsi2" [(set (match_operand:SI 0 "register_operand" "=r,r") - (zero_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))] + (zero_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))] "" "@ l.andi\t%0, %1, @@ -388,7 +388,7 @@ (define_insn "extendsi2" [(set (match_operand:SI 0 "register_operand" "=r,r") - (sign_extend:SI (match_operand:I12 1 "nonimmediate_operand" "r,m")))] + (sign_extend:SI (match_operand:I12 1 "reg_or_mem_operand" "r,m")))] "TARGET_SEXT" "@ l.exts\t%0, %1 diff --git a/gcc/config/or1k/predicates.md b/gcc/config/or1k/predicates.md index 879236bca49..17599d0ee3b 100644 --- a/gcc/config/or1k/predicates.md +++ b/gcc/config/or1k/predicates.md @@ -82,3 +82,19 @@ (define_predicate "equality_comparison_operator" (match_code "ne,eq")) + +;; Borrowed from rs6000 +; Return 1 if the operand is in volatile memory. Note that during the +;; RTL generation phase, memory_operand does not return TRUE for volatile +;; memory references. So this function allows us to recognize volatile +;; references where it's safe. +(define_predicate "volatile_mem_operand" + (and (and (match_code "mem") + (match_test "MEM_VOLATILE_P (op)")) + (if_then_else (match_test "reload_completed") +(match_operand 0 "memory_operand") +(match_test "memory_address_p (mode, XEXP (op, 0))" + +(define_predicate "reg_or_mem_operand" + (ior (match_operand 0 "nonimmediate_operand") + (match_operand 0 "volatile_mem_operand"))) -- 2.19.1
[PATCH 0/3] OpenRISC floating point support + fixes
Hello, This is a set of patches to bring FPU support to the OpenRISC backend. The backend also add support for 64-bit floating point operations on 32-bit cores using register pairs, see orfpx64a32 [0]. This depends on binutils patches which have also been submitted per review. [1] The toolchain has been tested using the gcc and binutils testsuites as well as floating point test suites running on sim and an fpga soft core or1k_marocchino. [2] There is also an unrelated, but trivial patch to fix a code quality issue with volatile memory loads. This whole patch series can be found on my github repo [3] as well. -Stafford [0] https://openrisc.io/proposals/orfpx64a32 [1] g...@github.com:stffrdhrn/binutils-gdb.git orfpx64a32-2 [2] https://github.com/openrisc/or1k_marocchino [3] g...@github.com:stffrdhrn/gcc.git or1k-fpu-1a Stafford Horne (3): or1k: Initial support for FPU or1k: Allow volatile memory for sign/zero extend loads or1k: only force reg for immediates gcc/config.gcc| 1 + gcc/config/or1k/or1k.c| 10 ++-- gcc/config/or1k/or1k.md | 109 -- gcc/config/or1k/or1k.opt | 15 - gcc/config/or1k/predicates.md | 16 + gcc/doc/invoke.texi | 15 + 6 files changed, 156 insertions(+), 10 deletions(-) -- 2.19.1
Re: [wwwdocs] gcc-9/changes.html - Mention new OpenRISC backend
Committed. On Tue, Apr 02, 2019 at 01:03:35PM +0900, Stafford Horne wrote: > Hello, > > I was reading through some things and found this was missing. > > As before, I don't seem to have CVS access, if its OK and someone can commit > it > would be helpful. It turns out I do have CVS access, which is granted along with SVN access. > -Stafford > > Index: htdocs/gcc-9/changes.html > === > RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-9/changes.html,v > retrieving revision 1.56 > diff -u -r1.56 changes.html > --- htdocs/gcc-9/changes.html 1 Apr 2019 14:55:53 - 1.56 > +++ htdocs/gcc-9/changes.html 2 Apr 2019 03:59:42 - > @@ -827,6 +827,13 @@ > > > > +OpenRISC > + > + > +A new back end targeting OpenRISC processors has been contributed to GCC. > + > + > + > > >
[wwwdocs] gcc-9/changes.html - Mention new OpenRISC backend
Hello, I was reading through some things and found this was missing. As before, I don't seem to have CVS access, if its OK and someone can commit it would be helpful. -Stafford Index: htdocs/gcc-9/changes.html === RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-9/changes.html,v retrieving revision 1.56 diff -u -r1.56 changes.html --- htdocs/gcc-9/changes.html 1 Apr 2019 14:55:53 - 1.56 +++ htdocs/gcc-9/changes.html 2 Apr 2019 03:59:42 - @@ -827,6 +827,13 @@ +OpenRISC + + +A new back end targeting OpenRISC processors has been contributed to GCC. + + +
Re: [PATCH] MAINTAINERS: add myself as or1k maintainer
On Sat, Nov 10, 2018 at 06:09:56AM +0900, Stafford Horne wrote: > Hello, > > I will just commit the below, I dont expect it to cause any problem as I am > maintainer :). > > https://gcc.gnu.org/ml/gcc/2018-08/msg00216.html > > On Fri, Nov 09, 2018 at 09:44:07PM +0900, Stafford Horne wrote: > > ChangeLog: > > > > -mm-dd Stafford Horne > > > > * MAINTAINERS (CPU Port Maintainers): Add myself for or1k. > > --- > > MAINTAINERS | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index ba8c8040967..cc7d4bddee8 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -90,6 +90,7 @@ nds32 portShiva Chen > > > > nios2 port Chung-Lin Tang > > nios2 port Sandra Loosemore > > nvptx port Tom de Vries > > +or1k port Stafford Horne > > pdp11 port Paul Koning > > powerpcspe portAndrew Jenner > > > > riscv port Kito Cheng > > -- > > 2.17.2 FYI, the actual patch I comitted was the below. I was reminded offline that I also needed to remove myself from Write After Approval. * MAINTAINERS (CPU Port Maintainers): Add myself for or1k. (Write After Approval): Remove myself. --- ChangeLog | 5 + MAINTAINERS | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/ChangeLog b/ChangeLog index e0662790934..1d71ed6538e 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,8 @@ +2018-11-10 Stafford Horne + + * MAINTAINERS (CPU Port Maintainers): Add myself for or1k. + (Write After Approval): Remove myself. + 2018-11-06 Hafiz Abid Qadeer * config/iconv.m4 (AM_ICONV_LINK): Don't overwrite CPPFLAGS. diff --git a/MAINTAINERS b/MAINTAINERS index ba8c8040967..35a815bad97 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -90,6 +90,7 @@ nds32 portShiva Chen nios2 port Chung-Lin Tang nios2 port Sandra Loosemore nvptx port Tom de Vries +or1k port Stafford Horne pdp11 port Paul Koning powerpcspe portAndrew Jenner riscv port Kito Cheng @@ -415,7 +416,6 @@ Stuart Henderson Matthew Hiller Kazu Hirata Manfred Hollstein -Stafford Horne Cong Hou Falk Hueffner Andrew John Hughes -- 2.17.2
Re: [PATCH] MAINTAINERS: add myself as or1k maintainer
Hello, I will just commit the below, I dont expect it to cause any problem as I am maintainer :). https://gcc.gnu.org/ml/gcc/2018-08/msg00216.html On Fri, Nov 09, 2018 at 09:44:07PM +0900, Stafford Horne wrote: > ChangeLog: > > yyyy-mm-dd Stafford Horne > > * MAINTAINERS (CPU Port Maintainers): Add myself for or1k. > --- > MAINTAINERS | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index ba8c8040967..cc7d4bddee8 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -90,6 +90,7 @@ nds32 port Shiva Chen > > nios2 port Chung-Lin Tang > nios2 port Sandra Loosemore > nvptx port Tom de Vries > +or1k portStafford Horne > pdp11 port Paul Koning > powerpcspe port Andrew Jenner > > riscv port Kito Cheng > -- > 2.17.2 >
[PATCH] MAINTAINERS: add myself as or1k maintainer
ChangeLog: -mm-dd Stafford Horne * MAINTAINERS (CPU Port Maintainers): Add myself for or1k. --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index ba8c8040967..cc7d4bddee8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -90,6 +90,7 @@ nds32 portShiva Chen nios2 port Chung-Lin Tang nios2 port Sandra Loosemore nvptx port Tom de Vries +or1k port Stafford Horne pdp11 port Paul Koning powerpcspe portAndrew Jenner riscv port Kito Cheng -- 2.17.2
[PATCH v4 2/3] or1k: testsuite: initial support for openrisc
-mm-dd Stafford Horne Richard Henderson gcc/testsuite/ChangeLog: * gcc.c-torture/execute/20101011-1.c: Adjust for OpenRISC. * gcc.dg/20020312-2.c: Likewise. * gcc.dg/attr-alloc_size-11.c: Likewise. * gcc.dg/builtin-apply2.c: Likewise. * gcc.dg/nop.h: Likewise. * gcc.dg/torture/stackalign/builtin-apply-2.c: Likewise. * gcc.dg/tree-ssa/20040204-1.c: Likewise. * gcc.dg/tree-ssa/reassoc-33.c: Likewise. * gcc.dg/tree-ssa/reassoc-34.c: Likewise. * gcc.dg/tree-ssa/reassoc-35.c: Likewise. * gcc.dg/tree-ssa/reassoc-36.c: Likewise. * lib/target-supports.exp (check_effective_target_logical_op_short_circuit): Add or1k*-*-*. * gcc.target/or1k/*: New. --- .../gcc.c-torture/execute/20101011-1.c| 3 ++ gcc/testsuite/gcc.dg/20020312-2.c | 2 + gcc/testsuite/gcc.dg/attr-alloc_size-11.c | 4 +- gcc/testsuite/gcc.dg/builtin-apply2.c | 2 +- gcc/testsuite/gcc.dg/nop.h| 2 + .../torture/stackalign/builtin-apply-2.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c| 2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-33.c| 2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-34.c| 2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-35.c| 2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-36.c| 2 +- gcc/testsuite/gcc.target/or1k/args-1.c| 19 + gcc/testsuite/gcc.target/or1k/args-2.c| 15 +++ gcc/testsuite/gcc.target/or1k/cmov-1.c| 8 gcc/testsuite/gcc.target/or1k/cmov-2.c| 9 gcc/testsuite/gcc.target/or1k/div-mul-1.c | 9 gcc/testsuite/gcc.target/or1k/div-mul-2.c | 9 gcc/testsuite/gcc.target/or1k/or1k.exp| 41 +++ gcc/testsuite/gcc.target/or1k/return-1.c | 10 + gcc/testsuite/gcc.target/or1k/return-2.c | 19 + gcc/testsuite/gcc.target/or1k/return-3.c | 19 + gcc/testsuite/gcc.target/or1k/return-4.c | 19 + gcc/testsuite/gcc.target/or1k/ror-1.c | 8 gcc/testsuite/gcc.target/or1k/ror-2.c | 9 gcc/testsuite/gcc.target/or1k/ror-3.c | 8 gcc/testsuite/gcc.target/or1k/shftimm-1.c | 8 gcc/testsuite/gcc.target/or1k/shftimm-2.c | 8 gcc/testsuite/gcc.target/or1k/sibcall-1.c | 18 gcc/testsuite/lib/target-supports.exp | 1 + 29 files changed, 253 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/or1k/args-1.c create mode 100644 gcc/testsuite/gcc.target/or1k/args-2.c create mode 100644 gcc/testsuite/gcc.target/or1k/cmov-1.c create mode 100644 gcc/testsuite/gcc.target/or1k/cmov-2.c create mode 100644 gcc/testsuite/gcc.target/or1k/div-mul-1.c create mode 100644 gcc/testsuite/gcc.target/or1k/div-mul-2.c create mode 100644 gcc/testsuite/gcc.target/or1k/or1k.exp create mode 100644 gcc/testsuite/gcc.target/or1k/return-1.c create mode 100644 gcc/testsuite/gcc.target/or1k/return-2.c create mode 100644 gcc/testsuite/gcc.target/or1k/return-3.c create mode 100644 gcc/testsuite/gcc.target/or1k/return-4.c create mode 100644 gcc/testsuite/gcc.target/or1k/ror-1.c create mode 100644 gcc/testsuite/gcc.target/or1k/ror-2.c create mode 100644 gcc/testsuite/gcc.target/or1k/ror-3.c create mode 100644 gcc/testsuite/gcc.target/or1k/shftimm-1.c create mode 100644 gcc/testsuite/gcc.target/or1k/shftimm-2.c create mode 100644 gcc/testsuite/gcc.target/or1k/sibcall-1.c diff --git a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c index 8261b796a47..d2beeb52a0e 100644 --- a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c @@ -100,6 +100,9 @@ __aeabi_idiv0 (int return_value) #elif defined (__moxie__) /* Not all moxie configurations may raise exceptions. */ # define DO_TEST 0 +#elif defined (__or1k__) + /* On OpenRISC division by zero does not trap. */ +# define DO_TEST 0 #else # define DO_TEST 1 #endif diff --git a/gcc/testsuite/gcc.dg/20020312-2.c b/gcc/testsuite/gcc.dg/20020312-2.c index 1a8afd81506..e72a5b261ae 100644 --- a/gcc/testsuite/gcc.dg/20020312-2.c +++ b/gcc/testsuite/gcc.dg/20020312-2.c @@ -117,6 +117,8 @@ extern void abort (void); # if defined (__CK807__) || defined (__CK810__) # define PIC_REG "r28" # endif +#elif defined (__or1k__) +/* No pic register. */ #else # error "Modify the test for your target." #endif diff --git a/gcc/testsuite/gcc.dg/attr-alloc_size-11.c b/gcc/testsuite/gcc.dg/attr-alloc_size-11.c index 301a06fd464..e19f81a7624 100644 --- a/gcc/testsuite/gcc.dg/attr-alloc_size-11.c +++ b/gcc/testsuite/gcc.dg/attr-alloc_size-11.c @@ -47,8 +47,8 @@ typedef __SIZE_TYPE__size_t; /* The following tests fail because of missing range information. The xfail exclusions are PR79356. */ -TEST (signed char, SCHAR_MIN + 2, ALLOC_MAX
[PATCH v4 3/3] or1k: gcc: initial support for openrisc
-mm-dd Stafford Horne
Richard Henderson
Joel Sherrill
gcc/ChangeLog:
* common/config/or1k/or1k-common.c: New file.
* config/or1k/*: New.
* config.gcc (or1k*-*-*): New.
* configure.ac (or1k*-*-*): New test for openrisc tls.
* configure: Regenerated.
* doc/install.texi: Document OpenRISC triplets.
* doc/invoke.texi: Document OpenRISC arguments.
* doc/md.texi: Document OpenRISC.
---
gcc/common/config/or1k/or1k-common.c | 41 +
gcc/config.gcc | 45 +
gcc/config/or1k/constraints.md | 55 +
gcc/config/or1k/elf.h| 42 +
gcc/config/or1k/elf.opt | 33 +
gcc/config/or1k/linux.h | 45 +
gcc/config/or1k/or1k-protos.h| 38 +
gcc/config/or1k/or1k.c | 2183 ++
gcc/config/or1k/or1k.h | 392 +
gcc/config/or1k/or1k.md | 897 +++
gcc/config/or1k/or1k.opt | 67 +
gcc/config/or1k/predicates.md| 84 +
gcc/config/or1k/rtems.h | 30 +
gcc/config/or1k/t-or1k | 22 +
gcc/config/or1k/t-rtems |3 +
gcc/configure| 12 +
gcc/configure.ac | 12 +
gcc/doc/install.texi | 19 +
gcc/doc/invoke.texi | 68 +
gcc/doc/md.texi | 25 +
20 files changed, 4113 insertions(+)
create mode 100644 gcc/common/config/or1k/or1k-common.c
create mode 100644 gcc/config/or1k/constraints.md
create mode 100644 gcc/config/or1k/elf.h
create mode 100644 gcc/config/or1k/elf.opt
create mode 100644 gcc/config/or1k/linux.h
create mode 100644 gcc/config/or1k/or1k-protos.h
create mode 100644 gcc/config/or1k/or1k.c
create mode 100644 gcc/config/or1k/or1k.h
create mode 100644 gcc/config/or1k/or1k.md
create mode 100644 gcc/config/or1k/or1k.opt
create mode 100644 gcc/config/or1k/predicates.md
create mode 100644 gcc/config/or1k/rtems.h
create mode 100644 gcc/config/or1k/t-or1k
create mode 100644 gcc/config/or1k/t-rtems
diff --git a/gcc/common/config/or1k/or1k-common.c
b/gcc/common/config/or1k/or1k-common.c
new file mode 100644
index 000..044e843fd19
--- /dev/null
+++ b/gcc/common/config/or1k/or1k-common.c
@@ -0,0 +1,41 @@
+/* Common hooks for OpenRISC
+ Copyright (C) 2018 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "diagnostic-core.h"
+#include "tm.h"
+#include "common/common-target.h"
+#include "common/common-target-def.h"
+#include "opts.h"
+#include "flags.h"
+
+/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
+static const struct default_options or1k_option_optimization_table[] =
+ {
+/* Enable section anchors by default at -O1 or higher. */
+{ OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
+{ OPT_LEVELS_NONE, 0, NULL, 0 }
+ };
+
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#define TARGET_OPTION_OPTIMIZATION_TABLE or1k_option_optimization_table
+
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 284f7d178de..7ef8d27f091 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -484,6 +484,9 @@ nios2-*-*)
nvptx-*-*)
cpu_type=nvptx
;;
+or1k*-*-*)
+ cpu_type=or1k
+ ;;
powerpc*-*-*spe*)
cpu_type=powerpcspe
extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h
spu2vmx.h vec_types.h si2vmx.h htmintrin.h htmxlintrin.h"
@@ -2490,6 +2493,48 @@ nvptx-*)
tm_file="${tm_file} nvptx/offload.h"
fi
;;
+or1k*-*-*)
+ tm_file="elfos.h ${tm_file}"
+ tmake_file="${tmake_file} or1k/t-or1k"
+ # Force .init_array support. The configure script cannot always
+ # automatically detect that GAS supports it, yet we require it.
+ gcc_cv_initfini_array=yes
+
+ # Handle --with-multilib-list=...
+ or1k_multilibs="${with_multilib_list}"
+ if test "$or1k_multilibs" = "default"; then
+ or1k_multilibs="mcm
[PATCH v4 1/3] or1k: libgcc: initial support for openrisc
-mm-dd Stafford Horne Richard Henderson libgcc/ChangeLog: * config.host: Add OpenRISC support. * config/or1k/*: New. --- libgcc/config.host| 12 ++ libgcc/config/or1k/lib1funcs.S| 222 ++ libgcc/config/or1k/linux-unwind.h | 87 libgcc/config/or1k/sfp-machine.h | 54 libgcc/config/or1k/t-or1k | 22 +++ 5 files changed, 397 insertions(+) create mode 100644 libgcc/config/or1k/lib1funcs.S create mode 100644 libgcc/config/or1k/linux-unwind.h create mode 100644 libgcc/config/or1k/sfp-machine.h create mode 100644 libgcc/config/or1k/t-or1k diff --git a/libgcc/config.host b/libgcc/config.host index 029f6569caf..1cbc8aca1cb 100644 --- a/libgcc/config.host +++ b/libgcc/config.host @@ -165,6 +165,9 @@ nds32*-*) nios2*-*-*) cpu_type=nios2 ;; +or1k*-*-*) + cpu_type=or1k + ;; powerpc*-*-*) cpu_type=rs6000 ;; @@ -1039,6 +1042,15 @@ nios2-*-*) tmake_file="$tmake_file nios2/t-nios2 t-softfp-sfdf t-softfp-excl t-softfp" extra_parts="$extra_parts crti.o crtn.o" ;; +or1k-*-linux*) + tmake_file="$tmake_file or1k/t-or1k" + tmake_file="$tmake_file t-softfp-sfdf t-softfp" + md_unwind_header=or1k/linux-unwind.h + ;; +or1k-*-*) + tmake_file="$tmake_file or1k/t-or1k" + tmake_file="$tmake_file t-softfp-sfdf t-softfp" + ;; pdp11-*-*) tmake_file="pdp11/t-pdp11 t-fdpbit" ;; diff --git a/libgcc/config/or1k/lib1funcs.S b/libgcc/config/or1k/lib1funcs.S new file mode 100644 index 000..0ec41c3eba1 --- /dev/null +++ b/libgcc/config/or1k/lib1funcs.S @@ -0,0 +1,222 @@ +/* Copyright (C) 2018 Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 3, or (at your option) any +later version. + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + + +#ifdef L__mulsi3 + .balign 4 + .globl __mulsi3 + .type __mulsi3, @function +__mulsi3: + l.movhi r11, 0 /* initial r */ + + /* Given R = X * Y ... */ +1: l.sfeq r4, r0 /* while (y != 0) */ + l.bf2f +l.andi r5, r4, 1 /* if (y & 1) ... */ + l.add r12, r11, r3 + l.sfne r5, r0 +#if defined(__or1k_cmov__) + l.cmov r11, r12, r11 /* ... r += x. */ + l.srli r4, r4, 1 /* y >>= 1 */ +#else + l.bnf 3f +l.srli r4, r4, 1 /* y >>= 1 */ + l.ori r11, r12, 0 +3: +#endif + l.j 1b +l.add r3, r3, r3 /* x <<= 1 */ + +2: l.jrr9 +l.nop + + .size __mulsi3, . - __mulsi3 +#endif + +#if defined(L__udivsi3) || defined(L__umodsi3) \ +|| defined(L__divsi3) || defined(L__modsi3) + .global __udivmodsi3_internal + .hidden __udivmodsi3_internal + .type __udivmodsi3_internal, @function +#endif + +#ifdef L__udivsi3 + .balign 4 + .global __udivsi3 + .type __udivsi3, @function +__udivsi3: +__udivmodsi3_internal: + /* Note that the other division routines assume that r13 + is not clobbered by this routine, and use that as to + save a return address without creating a stack frame. */ + + l.sfeqi r4, 0 /* division by zero; return 0. */ + l.ori r11, r0, 0 /* initial quotient */ + l.bf9f +l.ori r12, r3, 0 /* initial remainder */ + + /* Given X/Y, shift Y left until Y >= X. */ + l.ori r6, r0, 1 /* mask = 1 */ +1: l.sfltsir4, 0 /* y has msb set */ + l.bf2f +l.sfltur4, r12 /* y < x */ + l.add r4, r4, r4 /* y <<= 1 */ + l.bnf 1b +l.add r6, r6, r6 /* mask <<= 1 */ + + /* Shift Y back to the right again, subtracting from X. */ +2: l.add
[PATCH v4 0/3] OpenRISC port
Hello, As you can see this is v4 of the OpenRISC port patch series, I just want to mention that there are a few things pointed out during the v3 review that I have not fixed, and do not plan before pushing upstream. These are either because I didn't feel they made the code easier to read or they were things that could wait unil after upstreaming. These include: (not changed) - libgcc !cmov 1cyc improvements suggested by Richard - gcc eliminations refactorings suggested by Segher - leaving out empty constraint strings suggested by Segher - implementing TARGET_ISNS_COST suggested by Segher Please let me know if you have concerns; now onto the patches: Changes Since v3: - Fix tabs formatting pointed out by Segher - Fix comment formatting and typos pointed out by Segher - Fix for sign/zero extention login in md file from Richard - Remove usages of ATTRIBUTE_UNUSED suggested by Segher - Remove need for init/fini, removing crti/n.S files - Add support for -static-pie in LINK_SPEC suggsted by Szabolcs Changes Since v2: - Add RTEMS patches from Joel Sherrill - Disable t-softfp-excl as suggsted by Joseph Myers - Add new architecture flags needed to run on real FPGA's found in testing * -mror - enable l.ror (rotate right) * -mshftimm - enable shift/rorate by immediate instructions - Binutils requirements are now in upstream git Changes Since v1: - Document options in invoke.texi suggested by Joseph Myers - Remove obsolete/incorrect macros suggested by Joseph Myers - Documented or1k.c functions as requested by Jeff Law - Add epilogue barriers suggested by Jeff Law - Define SPECULATION_SAFE_VALUE suggested by Jeff Law - Switch to init/fini array suggested by Richard Henderson - Define and document multilib flags to enable disable instructions only available on some CPU cores as requested on OpenRISC mailing list. Since February this year I have been working on an OpenRISC clean room rewrite. http://stffrdhrn.github.io/software/embedded/openrisc/2018/02/03/openrisc_gcc_rewrite.html As per the article, the old port had issues with some of the owners signing over FSF copyright. To get around this I discussed options with the group and in the end I opted for a clean room rewrite. The new code base has been written by me with lots of help from Richard Henderson. I trust that both of us have our FSF GCC copyright's in place. # Testing We have been running the GCC testsuite with newlib and musl libc. The results are good. See results published in a test build/release here: - https://github.com/stffrdhrn/gcc/releases/tag/or1k-9.0.0-20181106 # Building To build this requires the latest binutils upstream master i.e. 2.31.52. Also, due to removing need for `init` and `fini` it requires the latest changes on newlib master. -Stafford Stafford Horne (3): or1k: libgcc: initial support for openrisc or1k: testsuite: initial support for openrisc or1k: gcc: initial support for openrisc gcc/common/config/or1k/or1k-common.c | 41 + gcc/config.gcc| 45 + gcc/config/or1k/constraints.md| 55 + gcc/config/or1k/elf.h | 42 + gcc/config/or1k/elf.opt | 33 + gcc/config/or1k/linux.h | 45 + gcc/config/or1k/or1k-protos.h | 38 + gcc/config/or1k/or1k.c| 2183 + gcc/config/or1k/or1k.h| 392 +++ gcc/config/or1k/or1k.md | 897 +++ gcc/config/or1k/or1k.opt | 67 + gcc/config/or1k/predicates.md | 84 + gcc/config/or1k/rtems.h | 30 + gcc/config/or1k/t-or1k| 22 + gcc/config/or1k/t-rtems |3 + gcc/configure | 12 + gcc/configure.ac | 12 + gcc/doc/install.texi | 19 + gcc/doc/invoke.texi | 68 + gcc/doc/md.texi | 25 + .../gcc.c-torture/execute/20101011-1.c|3 + gcc/testsuite/gcc.dg/20020312-2.c |2 + gcc/testsuite/gcc.dg/attr-alloc_size-11.c |4 +- gcc/testsuite/gcc.dg/builtin-apply2.c |2 +- gcc/testsuite/gcc.dg/nop.h|2 + .../torture/stackalign/builtin-apply-2.c |2 +- gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c|2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-33.c|2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-34.c|2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-35.c|2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-36.c|2 +- gcc/testsuite/gcc.target/or1k/args-1.c| 19 + gcc/testsuite/gcc.target/or1k/args-2.c| 15 + gcc/testsuite/gcc.target/or1k/cmov-1.c|8 + gcc/testsuite/gcc.target/or1k/cmov-2.c|9 + gcc/testsuite/gcc.target/or1k
Re: [PATCH] newlib/configure.host: Set have_init_fini to no for OpenRISC
On Mon, Nov 05, 2018 at 10:03:29AM +0100, Corinna Vinschen wrote:
> On Nov 3 07:00, Stafford Horne wrote:
> > The new GCC port for OpenRISC will use the init_fini_array only and not
> > provide the init() and fini() functions. Disable the function usage by
> > default as its no longer needed.
> >
> > Signed-off-by: Stafford Horne
> > ---
> > newlib/configure.host | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/newlib/configure.host b/newlib/configure.host
> > index 27bce36a1..6c49cb750 100644
> > --- a/newlib/configure.host
> > +++ b/newlib/configure.host
> > @@ -279,6 +279,7 @@ case "${host_cpu}" in
> > ;;
> >or1k*|or1knd*)
> > machine_dir=or1k
> > + have_init_fini=no
> > ;;
> >powerpc*)
> > machine_dir=powerpc
> > --
> > 2.17.2
>
> Pushed.
Thank you,
-Stafford
Re: [PATCH v3 3/3] or1k: gcc: initial support for openrisc
On Mon, Nov 05, 2018 at 10:10:22AM -0500, Rich Felker wrote:
> On Mon, Nov 05, 2018 at 11:13:53AM +, Szabolcs Nagy wrote:
> > On 04/11/18 09:05, Stafford Horne wrote:
> > > On Mon, Oct 29, 2018 at 02:28:11PM +, Szabolcs Nagy wrote:
> > >> On 27/10/18 05:37, Stafford Horne wrote:
> > ...
> > >>> +#undef LINK_SPEC
> > >>> +#define LINK_SPEC "%{h*} \
> > >>> + %{static:-Bstatic} \
> > >>> + %{shared:-shared} \
> > >>> + %{symbolic:-Bsymbolic} \
> > >>> + %{!static: \
> > >>> + %{rdynamic:-export-dynamic} \
> > >>> + %{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}"
> > >>> +
> > >>> +#endif /* GCC_OR1K_LINUX_H */
> > >>
> > >> note that because of the -static-pie mess each
> > >> target needs a more complicated LINK_SPEC now.
> > >
> > > Hello,
> > >
> > > Does something like this look better?
> > >
> > > --- a/gcc/config/or1k/linux.h
> > > +++ b/gcc/config/or1k/linux.h
> > > @@ -37,8 +37,9 @@
> > > %{static:-Bstatic} \
> > > %{shared:-shared} \
> > > %{symbolic:-Bsymbolic} \
> > > - %{!static: \
> > > + %{!static:%{!static-pie:\
> > > %{rdynamic:-export-dynamic} \
> > > - %{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}"
> > > + %{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}} \
> > > + %{static-pie:-Bstatic -pie --no-dynamic-linker -z text}"
> > >
> > > #endif /* GCC_OR1K_LINUX_H */
> >
> > looks ok.
> >
> > > I have tested this out with or1k-linux-musl, but I get some LD complaints
> > > i.e.
> > >
> > > .../or1k-linux-musl/bin/ld: .../or1k-linux-musl/lib/libc.a(exit.o):
> > > non-pic relocation against symbol __fini_array_end
> > > .../or1k-linux-musl/bin/ld: .../or1k-linux-musl/lib/libc.a(exit.o):
> > > non-pic relocation against symbol __fini_array_start
> > >
> > > Those are some warnings we recently added to LD, perhaps I need to
> > > rebuild the
> > > libc.a with PIE as well. I will try it out, but if anyone has some
> > > suggestions
> > > that would be helpful.
> >
> > yes, musl does not build libc.a with pic by default,
> > either use a gcc configured with --enable-default-pie
> > or CC='gcc -fPIC' when building musl.
> >
> > after that -static-pie linking should work.
> >
> > (maybe musl should have an --enable-static-pie config
> > option to make this simpler)
>
> For practical purposes, if you want to use static pie, you need a
> default-pie toolchain. This is because _every_ static lib you might
> link needs to be built with -fPIE (or -fPIC), and ensuring that
> happens on a package-by-package basis is largely impractical; at least
> it's on the same order of magnitude of difficulty as other systems
> integration/packaging tasks.
Thanks, I kind of figured it out, but it was no so clear when I started.
> However from the musl side it might make sense to produce a libc_pic.a
> as part of the build process. This would make it easy to replace
> libc.a with libc_pic.a if desired, and could also be used as the basis
> for linking libc.so and to allow production of a stripped-down libc.so
> that only includes symbols a fixed set of binaries depend on. We could
> discuss something like this on the musl list.
That makes sense.
Thanks Rich for your input.
-Stafford
Re: [PATCH v3 3/3] or1k: gcc: initial support for openrisc
On Mon, Nov 05, 2018 at 11:13:53AM +, Szabolcs Nagy wrote:
> On 04/11/18 09:05, Stafford Horne wrote:
> > On Mon, Oct 29, 2018 at 02:28:11PM +, Szabolcs Nagy wrote:
> >> On 27/10/18 05:37, Stafford Horne wrote:
> ...
> >>> +#undef LINK_SPEC
> >>> +#define LINK_SPEC "%{h*} \
> >>> + %{static:-Bstatic}\
> >>> + %{shared:-shared} \
> >>> + %{symbolic:-Bsymbolic}\
> >>> + %{!static:\
> >>> + %{rdynamic:-export-dynamic} \
> >>> + %{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}"
> >>> +
> >>> +#endif /* GCC_OR1K_LINUX_H */
> >>
> >> note that because of the -static-pie mess each
> >> target needs a more complicated LINK_SPEC now.
> >
> > Hello,
> >
> > Does something like this look better?
> >
> > --- a/gcc/config/or1k/linux.h
> > +++ b/gcc/config/or1k/linux.h
> > @@ -37,8 +37,9 @@
> > %{static:-Bstatic} \
> > %{shared:-shared} \
> > %{symbolic:-Bsymbolic} \
> > - %{!static: \
> > + %{!static:%{!static-pie:\
> > %{rdynamic:-export-dynamic} \
> > - %{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}"
> > + %{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}} \
> > + %{static-pie:-Bstatic -pie --no-dynamic-linker -z text}"
> >
> > #endif /* GCC_OR1K_LINUX_H */
>
> looks ok.
>
> > I have tested this out with or1k-linux-musl, but I get some LD complaints
> > i.e.
> >
> > .../or1k-linux-musl/bin/ld: .../or1k-linux-musl/lib/libc.a(exit.o): non-pic
> > relocation against symbol __fini_array_end
> > .../or1k-linux-musl/bin/ld: .../or1k-linux-musl/lib/libc.a(exit.o): non-pic
> > relocation against symbol __fini_array_start
> >
> > Those are some warnings we recently added to LD, perhaps I need to rebuild
> > the
> > libc.a with PIE as well. I will try it out, but if anyone has some
> > suggestions
> > that would be helpful.
>
> yes, musl does not build libc.a with pic by default,
> either use a gcc configured with --enable-default-pie
> or CC='gcc -fPIC' when building musl.
>
> after that -static-pie linking should work.
>
> (maybe musl should have an --enable-static-pie config
> option to make this simpler)
Thank's for confirming. I tested this out with your tips and it works.
I use musl-cross-make [0] to build musl, all you really need to do is add
'GCC_CONFIG += --enable-default-pie' to your config.mak file.
-Stafford
[0] https://github.com/richfelker/musl-cross-make
Re: [PATCH v3 3/3] or1k: gcc: initial support for openrisc
On Mon, Oct 29, 2018 at 02:28:11PM +, Szabolcs Nagy wrote:
> On 27/10/18 05:37, Stafford Horne wrote:
> > +++ b/gcc/config/or1k/linux.h
> > @@ -0,0 +1,44 @@
> > +/* Linux Definitions for OpenRISC.
> > + Copyright (C) 2018 Free Software Foundation, Inc.
> > + Contributed by Stafford Horne.
> > +
> > + This file is part of GCC.
> > +
> > + GCC is free software; you can redistribute it and/or modify it
> > + under the terms of the GNU General Public License as published
> > + by the Free Software Foundation; either version 3, or (at your
> > + option) any later version.
> > +
> > + GCC is distributed in the hope that it will be useful, but WITHOUT
> > + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
> > + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
> > + License for more details.
> > +
> > + You should have received a copy of the GNU General Public License
> > + along with GCC; see the file COPYING3. If not see
> > + <http://www.gnu.org/licenses/>. */
> > +
> > +#ifndef GCC_OR1K_LINUX_H
> > +#define GCC_OR1K_LINUX_H
> > +
> > +/* elfos.h should have already been included. Now just override
> > + any conflicting definitions and add any extras. */
> > +
> > +#define TARGET_OS_CPP_BUILTINS() \
> > + GNU_USER_TARGET_OS_CPP_BUILTINS ()
> > +
> > +#define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-or1k.so.1"
> > +
> > +#undef MUSL_DYNAMIC_LINKER
> > +#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-or1k.so.1"
> > +
> > +#undef LINK_SPEC
> > +#define LINK_SPEC "%{h*} \
> > + %{static:-Bstatic} \
> > + %{shared:-shared} \
> > + %{symbolic:-Bsymbolic} \
> > + %{!static: \
> > + %{rdynamic:-export-dynamic} \
> > + %{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}"
> > +
> > +#endif /* GCC_OR1K_LINUX_H */
>
> note that because of the -static-pie mess each
> target needs a more complicated LINK_SPEC now.
Hello,
Does something like this look better?
--- a/gcc/config/or1k/linux.h
+++ b/gcc/config/or1k/linux.h
@@ -37,8 +37,9 @@
%{static:-Bstatic} \
%{shared:-shared} \
%{symbolic:-Bsymbolic} \
- %{!static: \
+ %{!static:%{!static-pie:\
%{rdynamic:-export-dynamic} \
- %{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}"
+ %{!shared:-dynamic-linker " GNU_USER_DYNAMIC_LINKER "}}} \
+ %{static-pie:-Bstatic -pie --no-dynamic-linker -z text}"
#endif /* GCC_OR1K_LINUX_H */
I have tested this out with or1k-linux-musl, but I get some LD complaints i.e.
.../or1k-linux-musl/bin/ld: .../or1k-linux-musl/lib/libc.a(exit.o): non-pic
relocation against symbol __fini_array_end
.../or1k-linux-musl/bin/ld: .../or1k-linux-musl/lib/libc.a(exit.o): non-pic
relocation against symbol __fini_array_start
Those are some warnings we recently added to LD, perhaps I need to rebuild the
libc.a with PIE as well. I will try it out, but if anyone has some suggestions
that would be helpful.
> i think there could be a generic LINK_SPEC in
> config/linux.h or config/gnu-user.h that works
> for simple targets (the start file spec is
> already there) so this complex logic is not
> repeated everywhere.
>
> or even do the -no-dynamic-linker logic in
> LINK_PIE_SPEC in gcc.c for all targets, not
> just linux, so backends don't need to do
> anything to get static-pie to work.
I see, yeah, it seems this could be made generic. I would defer myself working
on making this generic until after or1k port is in. Sorry, I dont have much
time to make sure it doesnt break everything/anything. Also, To tell you the
truth I haven't heard of anyone ever running OpenRISC with pie, it has always
been something on my todo list though. I have had some inqueries into helping
bootstrap some linux nommu machines.
-Stafford
Re: [PATCH] Add myself to MAINTAINERS (not-committed)
On Sat, Nov 03, 2018 at 10:34:40AM -0500, Peter Bergner wrote: > On 11/3/18 1:01 AM, Stafford Horne wrote: > > Nevermind, I don not have write access. I will request to: > > > > overse...@gcc.gnu.org > > > > Use the following form to request write access: > > https://sourceware.org/cgi-bin/pdw/ps_form.cgi Thank you, this is for requesting a new account. I already have an account. The page also mentions if you already have an account and just need write access to a new project then mail `overseers`; which I have just done. -Stafford
Re: [PATCH] Add myself to MAINTAINERS (not-committed)
Nevermind, I don not have write access. I will request to: overse...@gcc.gnu.org On Sat, Nov 03, 2018 at 02:55:17PM +0900, Stafford Horne wrote: > Committing this. > > 2018-11-02 Stafford Horne > > * MAINTAINERS (Write After Approval): Add myself. > > Index: MAINTAINERS > === > --- MAINTAINERS (revision 265762) > +++ MAINTAINERS (working copy) > @@ -415,6 +415,7 @@ Stuart Henderson > > Matthew Hiller > Kazu Hirata > Manfred Hollstein > +Stafford Horne > Cong Hou > Falk Hueffner > Andrew John Hughes
[PATCH] Add myself to MAINTAINERS
Committing this. 2018-11-02 Stafford Horne * MAINTAINERS (Write After Approval): Add myself. Index: MAINTAINERS === --- MAINTAINERS (revision 265762) +++ MAINTAINERS (working copy) @@ -415,6 +415,7 @@ Stuart Henderson Matthew Hiller Kazu Hirata Manfred Hollstein +Stafford Horne Cong Hou Falk Hueffner Andrew John Hughes
[PATCH] newlib/configure.host: Set have_init_fini to no for OpenRISC
The new GCC port for OpenRISC will use the init_fini_array only and not
provide the init() and fini() functions. Disable the function usage by
default as its no longer needed.
Signed-off-by: Stafford Horne
---
newlib/configure.host | 1 +
1 file changed, 1 insertion(+)
diff --git a/newlib/configure.host b/newlib/configure.host
index 27bce36a1..6c49cb750 100644
--- a/newlib/configure.host
+++ b/newlib/configure.host
@@ -279,6 +279,7 @@ case "${host_cpu}" in
;;
or1k*|or1knd*)
machine_dir=or1k
+ have_init_fini=no
;;
powerpc*)
machine_dir=powerpc
--
2.17.2
Re: [wwwdocs] readings.html - add OpenRISC links
On Thu, Nov 01, 2018 at 04:43:08PM -0500, Segher Boessenkool wrote: > On Fri, Nov 02, 2018 at 06:20:56AM +0900, Stafford Horne wrote: > > As we were getting ready for OpenRISC gcc port upstreaming Segher pointed > > out > > that we should be updating this. > > > > I don't think have CVS write access (only git binutils-gdb), can someone > > help to > > review and commit if OK? > > I committed this for you (as trivial and obvious). Thanks! Thank you!
[wwwdocs] readings.html - add OpenRISC links
Hello, As we were getting ready for OpenRISC gcc port upstreaming Segher pointed out that we should be updating this. I don't think have CVS write access (only git binutils-gdb), can someone help to review and commit if OK? -Stafford Index: readings.html === RCS file: /cvs/gcc/wwwdocs/htdocs/readings.html,v retrieving revision 1.305 diff -u -r1.305 readings.html --- readings.html 6 Oct 2018 17:36:29 - 1.305 +++ readings.html 1 Nov 2018 21:16:24 - @@ -233,7 +233,13 @@ Manufacturer: Intel (formerly Altera) https://www.intel.com/content/www/us/en/programmable/products/processors/support.html;>Nios II Processor Documentation - + + OpenRISC + Manufacturer: Many (community built architecture) + https://openrisc.io;>OpenRISC Project + https://openrisc.io/architecture;>Architecture Specification + + pa Manufacturer: HP PA-RISC is preferred over the older HPPA acronym
Re: [PATCH v3 3/3] or1k: gcc: initial support for openrisc
On Tue, Oct 30, 2018 at 03:57:03PM +, Richard Henderson wrote: > On 10/30/18 12:18 PM, Stafford Horne wrote: > > OK, I was just being lazy allowing the spill. Do you think the split/expand > > would be an RTL using left shift / right shift? Can you think of something > > more clever? Since "real" hardware does not usually support shifts with an > > immediate we will need 1 instruction to load shift amount. i.e. > > > > l.ori %0, r0, 24 > > l.sll %1, %1, %0 > > l.sra %0, %1, %0 > > This clobbers %1. Right, it was just a rough idea to create another r/r pattern. > So, ouch. I think we will want to avoid creating this particular pattern in > the first place unless l.exts exists then. We would use another pattern like > > (define_insn "*sign_extend_mem" > [(set (match_operand:SI 0 "register_operand" "=r") > (sign_extend:SI > (match_operand:HI 1 "memory_operand" "m")))] > "" > "l.lhs\t%0, %1") > > following the TARGET_SEXT pattern. In this way combine can use this pattern > without getting us into trouble with the register allocator later. OK, thats simple enough then. I had thought you were asking for creating another r/r pattern using define_split. That might be better than requiring a memory load/store to do sign extension, but I guess we can optimize that later if needed. (Thats what my original thought was.) -Stafford
Re: [PATCH v3 3/3] or1k: gcc: initial support for openrisc
On Tue, Oct 30, 2018 at 10:49:53AM -0500, Segher Boessenkool wrote:
> On Tue, Oct 30, 2018 at 09:49:18PM +0900, Stafford Horne wrote:
> > Hello,
> >
> > On Sun, Oct 28, 2018 at 05:54:47PM -0500, Segher Boessenkool wrote:
> > > Yes, like that. It also easily can handle the other combos (those with
> > > STACK_POINTER), and it is easier if you have to switch
> > > FRAME_GROWS_DOWNWARD
> > > ("false" is better on some args, but "true" is required for ssp).
> > >
> > > Your code is fine as-is of course.
> >
> > Just to be clear, when you say 'as-is' did you mean the original v3 patch?
> > Or
> > are you referring to followup patch I posted with the some_offset (from) -
> > some_offset (to) logic.
>
> Either. Both. I meant the orig big patch, v3 if that's what it was.
Alright, thanks, I just didnt want to misunderstand.
-Stafford
Re: [PATCH v3 3/3] or1k: gcc: initial support for openrisc
Hello,
On Sun, Oct 28, 2018 at 05:54:47PM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Mon, Oct 29, 2018 at 06:47:23AM +0900, Stafford Horne wrote:
> > On Sat, Oct 27, 2018 at 09:57:30PM -0500, Segher Boessenkool wrote:
> > > > +/* Helper for defining INITIAL_ELIMINATION_OFFSET.
> > > > + We allow the following eliminiations:
> > > > + FP -> HARD_FP or SP
> > > > + AP -> HARD_FP or SP
> > > > +
> > > > + HFP and AP are the same which is handled below. */
> > > > +
> > > > +HOST_WIDE_INT
> > > > +or1k_initial_elimination_offset (int from, int to)
> > >
> > > You could calculate this as some_offset (from) - some_offset (to) with
> > > some_offset a simple helper function. That gives you all possible
> > > eliminations :-)
> > >
> > > (Each offset is very cheap to compute in your case, so that's not a
> > > problem).
> >
> > Right, Do you mean something like the following? I think it would work,
> > but I
> > am not sure it make the code easier to read. Do you think there would be
> > much
> > benefits supporting all possible eliminations?
>
> Yes, like that. It also easily can handle the other combos (those with
> STACK_POINTER), and it is easier if you have to switch FRAME_GROWS_DOWNWARD
> ("false" is better on some args, but "true" is required for ssp).
>
> Your code is fine as-is of course.
Just to be clear, when you say 'as-is' did you mean the original v3 patch? Or
are you referring to followup patch I posted with the some_offset (from) -
some_offset (to) logic.
-Stafford
Re: [PATCH v3 3/3] or1k: gcc: initial support for openrisc
On Sun, Oct 28, 2018 at 01:56:29AM +, Richard Henderson wrote: > On 10/27/18 5:37 AM, Stafford Horne wrote: > > +(define_insn "zero_extendhisi2" > > + [(set (match_operand:SI 0 "register_operand""=r,r") > > + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] > > + "" > > + "@ > > + l.exthz\t%0, %1 > > + l.lhz\t%0, %1" > > + [(set_attr "insn_support" "sext,*")]) > > + > > +(define_insn "zero_extendqisi2" > > + [(set (match_operand:SI 0 "register_operand""=r,r") > > + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] > > + "" > > + "@ > > + l.extbz\t%0, %1 > > + l.lbz\t%0, %1" > > + [(set_attr "insn_support" "sext,*")]) > > The !sext r/r case is just l.andi. OK. > > +;; Sign extension patterns > > + > > +;; We can do memory extensions with a single load > > +(define_insn "extendhisi2" > > + [(set (match_operand:SI 0 "register_operand" "=r,r") > > + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] > > + "" > > + "@ > > + l.exths\t%0, %1 > > + l.lhs\t%0, %1" > > + [(set_attr "insn_support" "sext,*")]) > > + > > +(define_insn "extendqisi2" > > + [(set (match_operand:SI 0 "register_operand" "=r,r") > > + (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] > > + "" > > + "@ > > + l.extbs\t%0, %1 > > + l.lbs\t%0, %1" > > + [(set_attr "insn_support" "sext,*")]) > > You don't really want to give the register allocator no choice but to spill to > memory in the !sext case. Another r/r case with a splitter that is > conditional > on !sext would work. OK, I was just being lazy allowing the spill. Do you think the split/expand would be an RTL using left shift / right shift? Can you think of something more clever? Since "real" hardware does not usually support shifts with an immediate we will need 1 instruction to load shift amount. i.e. l.ori %0, r0, 24 l.sll %1, %1, %0 l.sra %0, %1, %0 If we support shift with immediate it would just be: l.slli %1, %1, 24 l.srai %0, %1, 24 But, I cant think of anything better. > Otherwise, OK. Thanks, I am submitting patches on my git branch or1k-port-4. Just in case you want to track progress. - Stafford
Re: [PATCH v3 3/3] or1k: gcc: initial support for openrisc
On Mon, Oct 29, 2018 at 04:42:43PM +, Richard Henderson wrote: > On 10/29/18 4:34 PM, Segher Boessenkool wrote: > > Is there some better documentation available? This is what google found > > for me. I would have like better docs (more compact, etc.) Links to > > such would be great to have in readings.html :-) > > https://openrisc.io/architecture > > and especially the v1.2 pdf linked from there > > https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.2-rev0.pdf Thanks, I meant to point this out during my previous reply. Also, I will send a patch for adding this to wwwdocs. https://www.gnu.org/software/gcc/readings.html -Stafford
Re: [PATCH v3 1/3] or1k: libgcc: initial support for openrisc
On Sun, Oct 28, 2018 at 01:25:54AM +, Richard Henderson wrote: > On 10/27/18 5:37 AM, Stafford Horne wrote: > > +/* Here _init and _fini are empty because .init_array/.fini_array are used > > + exclusively. However, the functions are still needed as required when > > + linking. */ > > + .align 4 > > + .global _init > > + .type _init,@function > > +_init: > > + .global _fini > > + .type _fini,@function > > +_fini: > > + l.jrr9 > > +l.nop > > Where are they referenced from? Perhaps just a binutils bug, in that the > linker script needs adjustment? I was getting the issue with newlib. Here: https://sourceware.org/git/gitweb.cgi?p=newlib-cygwin.git;a=blob;f=newlib/libc/misc/init.c https://sourceware.org/git/gitweb.cgi?p=newlib-cygwin.git;a=blob;f=newlib/libc/misc/fini.c The HAVE_INIT_FINI was not there when I last checked. Now, thanks to risc-v, we can turn off the need for _init/_fini see: https://sourceware.org/git/gitweb.cgi?p=newlib-cygwin.git;a=commit;f=newlib/libc/misc/fini.c;h=6158b30e3e9b1b582ae60b15d64e775fa1705483 I guess thats what you were referring to before though, I just missed it. > > + /* Given R = X * Y ... */ > > +1: l.sfeq r4, r0 /* while (y != 0) */ > > + l.bf2f > > +l.andi r5, r4, 1 /* if (y & 1) ... */ > > + l.add r12, r11, r3 > > + l.sfne r5, r0 > > +#if defined(__or1k_cmov__) > > + l.cmov r11, r12, r11 /* ... r += x. */ > > + l.srli r4, r4, 1 /* y >>= 1 */ > > +#else > > + l.bnf 3f > > +l.srli r4, r4, 1 /* y >>= 1 */ > > + l.ori r11, r12, 0 > > This move could be the add to save 1 cycle in the !cmov case. > > > + /* Shift Y back to the right again, subtracting from X. */ > > +2: l.add r7, r11, r6 /* tmp1 = quot + mask */ > > +3: l.srli r6, r6, 1 /* mask >>= 1 */ > > + l.sub r8, r12, r4 /* tmp2 = x - y */ > > + l.sfleu r4, r12 /* y <= x */ > > + l.srli r4, r4, 1 /* y >>= 1 */ > > +#if defined(__or1k_cmov__) > > + l.cmov r11, r7, r11/* if (y <= x) quot = tmp1 */ > > + l.cmov r12, r8, r12/* if (y <= x) x = tmp2 */ > > +#else > > + l.bnf 4f > > +l.nop > > + l.ori r11, r7, 0 > > + l.ori r12, r8, 0 > > Simiarly. > > Although both mul nor div are correct as-is, and need not be fixed > immediately. > I'm only concerned about _init and _fini. Sure, let me look into them. -Stafford
Re: [PATCH v3 3/3] or1k: gcc: initial support for openrisc
On Sun, Oct 28, 2018 at 11:16:13PM +, Richard Henderson wrote: > On 10/28/18 2:57 AM, Segher Boessenkool wrote: > >> +(define_insn "xorsi3" > >> + [(set (match_operand:SI 0 "register_operand" "=r,r") > >> +(xor:SI > >> + (match_operand:SI 1 "register_operand" "%r,r") > >> + (match_operand:SI 2 "reg_or_s16_operand" " r,I")))] > >> + "" > >> + "@ > >> + l.xor\t%0, %1, %2 > >> + l.xori\t%0, %1, %2") > > > > Is this correct? Should this be unsigned (u16 and K)? > > No, l.xori is signed. Right, sorry, I didn't have enough time to look at this at all this morning. It is correct. It looks like the documentation for this page [1] is generated from the cgen cpu descriptions that were removed from binutils-gdb back in 2014. Ccing cgen who seem to maintain this web page. How can we go about getting it regenerated? cpu/or1korbis.cpu (alu-insn-uimm and) (alu-insn-uimm or) (alu-insn-simm xor) (define-pmacro (alu-carry-insn-simm mnemonic) (begin (dni (.sym l- mnemonic "i") (.str "l." mnemonic "i reg/reg/simm16") ((MACH ORBIS-MACHS)) (.str "l." mnemonic "i $rD,$rA,$simm16") (+ (.sym OPC_ (.upcase mnemonic) "I") rD rA simm16) [1] https://sourceware.org/cgen/gen-doc/openrisc-insn.html#insns -Stafford
Re: [PATCH v3 3/3] or1k: gcc: initial support for openrisc
Hi Segher,
Thank you for the review and thank you for all the help up until now.
On Sat, Oct 27, 2018 at 09:57:30PM -0500, Segher Boessenkool wrote:
> Hi Stafford,
>
> Some minor comments. I didn't read the atomics much, but I did look at
> everything else, and it looks fine :-)
>
> On Sat, Oct 27, 2018 at 01:37:02PM +0900, Stafford Horne wrote:
> > +case ${target} in
> > +or1k*-*-linux*)
> > +tm_file="${tm_file} gnu-user.h linux.h glibc-stdint.h"
> > +tm_file="${tm_file} or1k/linux.h"
> > +;;
>
> Spaces instead of tabs.
OK, I will fix.
> > + /* Number of bytes saved on the stack for outgoing/sub-fucntion args. */
>
> Typo ("function").
OK.
> > + /* The sum of sizes: locals vars, called saved regs, stack pointer
> > + * and an optional frame pointer.
> > + * Used in expand_prologue () and expand_epilogue(). */
>
> We don't use leading stars in comments (just spaces), normally.
OK.
> > + /* Set address to volitile to ensure the store doesn't get optimized
> > out. */
>
> "volatile"
OK.
> > +/* Helper for defining INITIAL_ELIMINATION_OFFSET.
> > + We allow the following eliminiations:
> > + FP -> HARD_FP or SP
> > + AP -> HARD_FP or SP
> > +
> > + HFP and AP are the same which is handled below. */
> > +
> > +HOST_WIDE_INT
> > +or1k_initial_elimination_offset (int from, int to)
>
> You could calculate this as some_offset (from) - some_offset (to) with
> some_offset a simple helper function. That gives you all possible
> eliminations :-)
>
> (Each offset is very cheap to compute in your case, so that's not a problem).
Right, Do you mean something like the following? I think it would work, but I
am not sure it make the code easier to read. Do you think there would be much
benefits supporting all possible eliminations?
/* Helper function for use with INITIAL_ELIMINATION_OFFSET. */
static HOST_WIDE_INT
or1k_stack_pointer_offset (int from)
{
HOST_WIDE_INT offset;
/* Set OFFSET to the offset from the stack pointer. */
switch (from)
{
/* Incoming args are all the way up at the previous frame. */
case HARD_FRAME_POINTER_REGNUM:
case ARG_POINTER_REGNUM:
offset = cfun->machine->total_size;
break;
/* Local args grow downward from the saved registers. */
case FRAME_POINTER_REGNUM:
offset = cfun->machine->args_size + cfun->machine->local_vars_size;
break;
default:
gcc_unreachable ();
}
return offset;
}
/* Helper for defining INITIAL_ELIMINATION_OFFSET.
We allow the following eliminiations:
FP -> HARD_FP or SP
AP -> HARD_FP or SP
HARD_FP and AP are actually the same. */
HOST_WIDE_INT
or1k_initial_elimination_offset (int from, int to)
{
return or1k_stack_pointer_offset (from) - or1k_stack_pointer_offset (to);
}
> > +static rtx
> > +or1k_function_value (const_tree valtype,
> > +const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
> > +bool outgoing ATTRIBUTE_UNUSED)
>
> Since we use C++ now you can write this as
>bool /*outgoing*/)
> or such, for enhanced readability.
Sure, I will remove all ATTRIBUTE_UNUSED instances.
> > + split. Symbols are lagitimized using split relocations. */
>
> "legitimized"
OK.
> > +void
> > +or1k_expand_move (machine_mode mode, rtx op0, rtx op1)
> > +{
> > + if (MEM_P (op0))
> > +{
> > + if (!const0_operand(op1, mode))
>
> Space before (.
OK. I found a few ore too, thanks.
> > +#undef TARGET_RTX_COSTS
> > +#define TARGET_RTX_COSTS or1k_rtx_costs
>
> You may want TARGET_INSN_COST as well (it is easier to get (more) correct).
OK, I was not considering that for the first port. Perhaps after getting this
in? I think in general the OpenRISC insruction costs are fairly flat for the
ones are using.
> > + if (hi != 0)
> > + {
> > + rtx scratch2 = gen_rtx_REG (Pmode, RV_REGNUM);
> > + emit_move_insn (scratch2, GEN_INT (hi));
> > + emit_insn (gen_add2_insn (scratch, scratch2));
> > +}
>
> Tab instead of spaces.
OK.
> > + /* Generate a tail call to the target function. */
> > + if (! TREE_USED (function))
>
> No space after !.
Ok.
> > +#define TARGET_RETURN_IN_MEMORYor1k_return_in_memory
>
> > +#defineTARGET_PASS_BY_REFERENCE or1k_pass_by_reference
>
> These two have a tab instead of a space (as the rest do).
OK, also some TARGET_* are aligned and some not. Will fix.
> > +#define WCHAR_TYPE_SIZE32
>
> An
Re: [PATCH v3 1/3] or1k: libgcc: initial support for openrisc
Hi, Thanks for the review. On Sat, Oct 27, 2018 at 06:25:04PM -0500, Segher Boessenkool wrote: > Hi! > > On Sat, Oct 27, 2018 at 01:37:00PM +0900, Stafford Horne wrote: > > + /* Given R = X * Y ... */ > > +1: l.sfeq r4, r0 /* while (y != 0) */ > > + l.bf2f > > +l.andi r5, r4, 1 /* if (y & 1) ... */ > > Do the extra leading spaces mean something? Yes, we put those to indicate a branch delay slot instruction. > > +l.sfeqir4, 0 /* division by zero; return 0. > > */ > > In some places (like here) you ident with 8 spaces instead of a tab. Thanks, I will fix those, it should be tab. > > +/* For signed division we do: > > + * > > + * -x / y = x / -y = -(x / y) > > + * -x % y = -(x % y) > > + * x % -y = x % b > > + * > > + * which has the property that (x/y)*y + (x%y) = x. > > + */ > > You mean "y" instead of "b" I think. I believe so, I will read through it. This part was done by Richard I should have reviewed it better. -Stafford
[PATCH v3 3/3] or1k: gcc: initial support for openrisc
-mm-dd Stafford Horne
Richard Henderson
Joel Sherrill
gcc/ChangeLog:
* common/config/or1k/or1k-common.c: New file.
* config/or1k/*: New.
* config.gcc (or1k*-*-*): New.
* configure.ac (or1k*-*-*): New test for openrisc tls.
* configure: Regenerated.
* doc/install.texi: Document OpenRISC triplets.
* doc/invoke.texi: Document OpenRISC arguments.
* doc/md.texi: Document OpenRISC.
---
gcc/common/config/or1k/or1k-common.c | 41 +
gcc/config.gcc | 45 +
gcc/config/or1k/constraints.md | 55 +
gcc/config/or1k/elf.h| 42 +
gcc/config/or1k/elf.opt | 33 +
gcc/config/or1k/linux.h | 44 +
gcc/config/or1k/or1k-protos.h| 38 +
gcc/config/or1k/or1k.c | 2186 ++
gcc/config/or1k/or1k.h | 392 +
gcc/config/or1k/or1k.md | 907 +++
gcc/config/or1k/or1k.opt | 67 +
gcc/config/or1k/predicates.md| 84 +
gcc/config/or1k/rtems.h | 30 +
gcc/config/or1k/t-or1k | 22 +
gcc/config/or1k/t-rtems |3 +
gcc/configure| 12 +
gcc/configure.ac | 12 +
gcc/doc/install.texi | 19 +
gcc/doc/invoke.texi | 68 +
gcc/doc/md.texi | 25 +
20 files changed, 4125 insertions(+)
create mode 100644 gcc/common/config/or1k/or1k-common.c
create mode 100644 gcc/config/or1k/constraints.md
create mode 100644 gcc/config/or1k/elf.h
create mode 100644 gcc/config/or1k/elf.opt
create mode 100644 gcc/config/or1k/linux.h
create mode 100644 gcc/config/or1k/or1k-protos.h
create mode 100644 gcc/config/or1k/or1k.c
create mode 100644 gcc/config/or1k/or1k.h
create mode 100644 gcc/config/or1k/or1k.md
create mode 100644 gcc/config/or1k/or1k.opt
create mode 100644 gcc/config/or1k/predicates.md
create mode 100644 gcc/config/or1k/rtems.h
create mode 100644 gcc/config/or1k/t-or1k
create mode 100644 gcc/config/or1k/t-rtems
diff --git a/gcc/common/config/or1k/or1k-common.c
b/gcc/common/config/or1k/or1k-common.c
new file mode 100644
index 000..044e843fd19
--- /dev/null
+++ b/gcc/common/config/or1k/or1k-common.c
@@ -0,0 +1,41 @@
+/* Common hooks for OpenRISC
+ Copyright (C) 2018 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "diagnostic-core.h"
+#include "tm.h"
+#include "common/common-target.h"
+#include "common/common-target-def.h"
+#include "opts.h"
+#include "flags.h"
+
+/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
+static const struct default_options or1k_option_optimization_table[] =
+ {
+/* Enable section anchors by default at -O1 or higher. */
+{ OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
+{ OPT_LEVELS_NONE, 0, NULL, 0 }
+ };
+
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#define TARGET_OPTION_OPTIMIZATION_TABLE or1k_option_optimization_table
+
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 71f62a2aba2..0dc2ac4b879 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -468,6 +468,9 @@ nios2-*-*)
nvptx-*-*)
cpu_type=nvptx
;;
+or1k*-*-*)
+ cpu_type=or1k
+ ;;
powerpc*-*-*spe*)
cpu_type=powerpcspe
extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h
spu2vmx.h vec_types.h si2vmx.h htmintrin.h htmxlintrin.h"
@@ -2464,6 +2467,48 @@ nvptx-*)
tm_file="${tm_file} nvptx/offload.h"
fi
;;
+or1k*-*-*)
+ tm_file="elfos.h ${tm_file}"
+ tmake_file="${tmake_file} or1k/t-or1k"
+ # Force .init_array support. The configure script cannot always
+ # automatically detect that GAS supports it, yet we require it.
+ gcc_cv_initfini_array=yes
+
+ # Handle --with-multilib-list=...
+ or1k_multilibs="${with_multilib_list}"
+ if test "$or1k_multilibs" = "default"; then
+ or1k_multilibs="mcm
[PATCH v3 2/3] or1k: testsuite: initial support for openrisc
-mm-dd Stafford Horne Richard Henderson gcc/testsuite/ChangeLog: * gcc.c-torture/execute/20101011-1.c: Adjust for OpenRISC. * gcc.dg/20020312-2.c: Likewise. * gcc.dg/attr-alloc_size-11.c: Likewise. * gcc.dg/builtin-apply2.c: Likewise. * gcc.dg/nop.h: Likewise. * gcc.dg/torture/stackalign/builtin-apply-2.c: Likewise. * gcc.dg/tree-ssa/20040204-1.c: Likewise. * gcc.dg/tree-ssa/reassoc-33.c: Likewise. * gcc.dg/tree-ssa/reassoc-34.c: Likewise. * gcc.dg/tree-ssa/reassoc-35.c: Likewise. * gcc.dg/tree-ssa/reassoc-36.c: Likewise. * lib/target-supports.exp (check_effective_target_logical_op_short_circuit): Add or1k*-*-*. * gcc.target/or1k/*: New. --- .../gcc.c-torture/execute/20101011-1.c| 3 ++ gcc/testsuite/gcc.dg/20020312-2.c | 2 + gcc/testsuite/gcc.dg/attr-alloc_size-11.c | 4 +- gcc/testsuite/gcc.dg/builtin-apply2.c | 2 +- gcc/testsuite/gcc.dg/nop.h| 2 + .../torture/stackalign/builtin-apply-2.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c| 2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-33.c| 2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-34.c| 2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-35.c| 2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-36.c| 2 +- gcc/testsuite/gcc.target/or1k/args-1.c| 19 + gcc/testsuite/gcc.target/or1k/args-2.c| 15 +++ gcc/testsuite/gcc.target/or1k/cmov-1.c| 8 gcc/testsuite/gcc.target/or1k/cmov-2.c| 9 gcc/testsuite/gcc.target/or1k/div-mul-1.c | 9 gcc/testsuite/gcc.target/or1k/div-mul-2.c | 9 gcc/testsuite/gcc.target/or1k/or1k.exp| 41 +++ gcc/testsuite/gcc.target/or1k/return-1.c | 10 + gcc/testsuite/gcc.target/or1k/return-2.c | 19 + gcc/testsuite/gcc.target/or1k/return-3.c | 19 + gcc/testsuite/gcc.target/or1k/return-4.c | 19 + gcc/testsuite/gcc.target/or1k/ror-1.c | 8 gcc/testsuite/gcc.target/or1k/ror-2.c | 9 gcc/testsuite/gcc.target/or1k/ror-3.c | 8 gcc/testsuite/gcc.target/or1k/shftimm-1.c | 8 gcc/testsuite/gcc.target/or1k/shftimm-2.c | 8 gcc/testsuite/gcc.target/or1k/sibcall-1.c | 18 gcc/testsuite/lib/target-supports.exp | 1 + 29 files changed, 253 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/or1k/args-1.c create mode 100644 gcc/testsuite/gcc.target/or1k/args-2.c create mode 100644 gcc/testsuite/gcc.target/or1k/cmov-1.c create mode 100644 gcc/testsuite/gcc.target/or1k/cmov-2.c create mode 100644 gcc/testsuite/gcc.target/or1k/div-mul-1.c create mode 100644 gcc/testsuite/gcc.target/or1k/div-mul-2.c create mode 100644 gcc/testsuite/gcc.target/or1k/or1k.exp create mode 100644 gcc/testsuite/gcc.target/or1k/return-1.c create mode 100644 gcc/testsuite/gcc.target/or1k/return-2.c create mode 100644 gcc/testsuite/gcc.target/or1k/return-3.c create mode 100644 gcc/testsuite/gcc.target/or1k/return-4.c create mode 100644 gcc/testsuite/gcc.target/or1k/ror-1.c create mode 100644 gcc/testsuite/gcc.target/or1k/ror-2.c create mode 100644 gcc/testsuite/gcc.target/or1k/ror-3.c create mode 100644 gcc/testsuite/gcc.target/or1k/shftimm-1.c create mode 100644 gcc/testsuite/gcc.target/or1k/shftimm-2.c create mode 100644 gcc/testsuite/gcc.target/or1k/sibcall-1.c diff --git a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c index 8261b796a47..d2beeb52a0e 100644 --- a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c +++ b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c @@ -100,6 +100,9 @@ __aeabi_idiv0 (int return_value) #elif defined (__moxie__) /* Not all moxie configurations may raise exceptions. */ # define DO_TEST 0 +#elif defined (__or1k__) + /* On OpenRISC division by zero does not trap. */ +# define DO_TEST 0 #else # define DO_TEST 1 #endif diff --git a/gcc/testsuite/gcc.dg/20020312-2.c b/gcc/testsuite/gcc.dg/20020312-2.c index 1a8afd81506..e72a5b261ae 100644 --- a/gcc/testsuite/gcc.dg/20020312-2.c +++ b/gcc/testsuite/gcc.dg/20020312-2.c @@ -117,6 +117,8 @@ extern void abort (void); # if defined (__CK807__) || defined (__CK810__) # define PIC_REG "r28" # endif +#elif defined (__or1k__) +/* No pic register. */ #else # error "Modify the test for your target." #endif diff --git a/gcc/testsuite/gcc.dg/attr-alloc_size-11.c b/gcc/testsuite/gcc.dg/attr-alloc_size-11.c index 3ec44dc1463..6bb904f4794 100644 --- a/gcc/testsuite/gcc.dg/attr-alloc_size-11.c +++ b/gcc/testsuite/gcc.dg/attr-alloc_size-11.c @@ -47,8 +47,8 @@ typedef __SIZE_TYPE__size_t; /* The following tests fail because of missing range information. The xfail exclusions are PR79356. */ -TEST (signed char, SCHAR_MIN + 2, ALLOC_MAX
[PATCH v3 0/3] OpenRISC port
Hello, Changes Since v2: - Add RTEMS patches from Joel Sherrill - Disable t-softfp-excl as suggsted by Joseph Myers - Add new architecture flags needed to run on real FPGA's found in testing * -mror - enable l.ror (rotate right) * -mshftimm - enable shift/rorate by immediate instructions - Binutils requirements are now in upstream git Changes Since v1: - Document options in invoke.texi suggested by Joseph Myers - Remove obsolete/incorrect macros suggested by Joseph Myers - Documented or1k.c functions as requested by Jeff Law - Add epilogue barriers suggested by Jeff Law - Define SPECULATION_SAFE_VALUE suggested by Jeff Law - Switch to init/fini array suggested by Richard Henderson - Define and document multilib flags to enable disable instructions only available on some CPU cores as requested on OpenRISC mailing list. Since February this year I have been working on an OpenRISC clean room rewrite. http://stffrdhrn.github.io/software/embedded/openrisc/2018/02/03/openrisc_gcc_rewrite.html As per the article, the old port had issues with some of the owners signing over FSF copyright. To get around this I discussed options with the group and in the end I opted for a clean room rewrite. The new code base has been written by me with lots of help from Richard Henderson. I trust that both of us have our FSF GCC copyright's in place. # Testing We have been running the GCC testsuite with newlib and musl libc. The results are good. See results published in a test build/release here: - https://github.com/stffrdhrn/gcc/releases/tag/or1k-9.0.0-20181027 # Building To build this requires the latest binutils upstream master i.e. 2.31.52. -Stafford Stafford Horne (3): or1k: libgcc: initial support for openrisc or1k: testsuite: initial support for openrisc or1k: gcc: initial support for openrisc gcc/common/config/or1k/or1k-common.c | 41 + gcc/config.gcc| 45 + gcc/config/or1k/constraints.md| 55 + gcc/config/or1k/elf.h | 42 + gcc/config/or1k/elf.opt | 33 + gcc/config/or1k/linux.h | 44 + gcc/config/or1k/or1k-protos.h | 38 + gcc/config/or1k/or1k.c| 2186 + gcc/config/or1k/or1k.h| 392 +++ gcc/config/or1k/or1k.md | 907 +++ gcc/config/or1k/or1k.opt | 67 + gcc/config/or1k/predicates.md | 84 + gcc/config/or1k/rtems.h | 30 + gcc/config/or1k/t-or1k| 22 + gcc/config/or1k/t-rtems |3 + gcc/configure | 12 + gcc/configure.ac | 12 + gcc/doc/install.texi | 19 + gcc/doc/invoke.texi | 68 + gcc/doc/md.texi | 25 + .../gcc.c-torture/execute/20101011-1.c|3 + gcc/testsuite/gcc.dg/20020312-2.c |2 + gcc/testsuite/gcc.dg/attr-alloc_size-11.c |4 +- gcc/testsuite/gcc.dg/builtin-apply2.c |2 +- gcc/testsuite/gcc.dg/nop.h|2 + .../torture/stackalign/builtin-apply-2.c |2 +- gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c|2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-33.c|2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-34.c|2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-35.c|2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-36.c|2 +- gcc/testsuite/gcc.target/or1k/args-1.c| 19 + gcc/testsuite/gcc.target/or1k/args-2.c| 15 + gcc/testsuite/gcc.target/or1k/cmov-1.c|8 + gcc/testsuite/gcc.target/or1k/cmov-2.c|9 + gcc/testsuite/gcc.target/or1k/div-mul-1.c |9 + gcc/testsuite/gcc.target/or1k/div-mul-2.c |9 + gcc/testsuite/gcc.target/or1k/or1k.exp| 41 + gcc/testsuite/gcc.target/or1k/return-1.c | 10 + gcc/testsuite/gcc.target/or1k/return-2.c | 19 + gcc/testsuite/gcc.target/or1k/return-3.c | 19 + gcc/testsuite/gcc.target/or1k/return-4.c | 19 + gcc/testsuite/gcc.target/or1k/ror-1.c |8 + gcc/testsuite/gcc.target/or1k/ror-2.c |9 + gcc/testsuite/gcc.target/or1k/ror-3.c |8 + gcc/testsuite/gcc.target/or1k/shftimm-1.c |8 + gcc/testsuite/gcc.target/or1k/shftimm-2.c |8 + gcc/testsuite/gcc.target/or1k/sibcall-1.c | 18 + gcc/testsuite/lib/target-supports.exp |1 + libgcc/config.host| 13 + libgcc/config/or1k/crti.S | 33 + libgcc/config/or1k/crtn.S |1 + libgcc/config/or1k/lib1funcs.S| 223 ++ libgcc/config/or1k/linux-unwind.h | 87 + libgcc/config/or1k/sfp-machine.h | 54 + libgcc/config/or1k/t-or1k
[PATCH v3 1/3] or1k: libgcc: initial support for openrisc
-mm-dd Stafford Horne Richard Henderson libgcc/ChangeLog: * config.host: Add OpenRISC support. * config/or1k/*: New. --- libgcc/config.host| 13 ++ libgcc/config/or1k/crti.S | 33 + libgcc/config/or1k/crtn.S | 1 + libgcc/config/or1k/lib1funcs.S| 223 ++ libgcc/config/or1k/linux-unwind.h | 87 libgcc/config/or1k/sfp-machine.h | 54 libgcc/config/or1k/t-or1k | 22 +++ 7 files changed, 433 insertions(+) create mode 100644 libgcc/config/or1k/crti.S create mode 100644 libgcc/config/or1k/crtn.S create mode 100644 libgcc/config/or1k/lib1funcs.S create mode 100644 libgcc/config/or1k/linux-unwind.h create mode 100644 libgcc/config/or1k/sfp-machine.h create mode 100644 libgcc/config/or1k/t-or1k diff --git a/libgcc/config.host b/libgcc/config.host index 029f6569caf..e32b2541ea1 100644 --- a/libgcc/config.host +++ b/libgcc/config.host @@ -165,6 +165,9 @@ nds32*-*) nios2*-*-*) cpu_type=nios2 ;; +or1k*-*-*) + cpu_type=or1k + ;; powerpc*-*-*) cpu_type=rs6000 ;; @@ -1039,6 +1042,16 @@ nios2-*-*) tmake_file="$tmake_file nios2/t-nios2 t-softfp-sfdf t-softfp-excl t-softfp" extra_parts="$extra_parts crti.o crtn.o" ;; +or1k-*-linux*) + tmake_file="$tmake_file or1k/t-or1k" + tmake_file="$tmake_file t-softfp-sfdf t-softfp" + md_unwind_header=or1k/linux-unwind.h + ;; +or1k-*-*) + tmake_file="$tmake_file or1k/t-or1k" + tmake_file="$tmake_file t-softfp-sfdf t-softfp" + extra_parts="$extra_parts crti.o crtn.o" + ;; pdp11-*-*) tmake_file="pdp11/t-pdp11 t-fdpbit" ;; diff --git a/libgcc/config/or1k/crti.S b/libgcc/config/or1k/crti.S new file mode 100644 index 000..9fcf6ae5995 --- /dev/null +++ b/libgcc/config/or1k/crti.S @@ -0,0 +1,33 @@ +/* Copyright (C) 2012-2018 Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 3, or (at your option) any +later version. + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* Here _init and _fini are empty because .init_array/.fini_array are used + exclusively. However, the functions are still needed as required when + linking. */ + .align 4 + .global _init + .type _init,@function +_init: + .global _fini + .type _fini,@function +_fini: + l.jrr9 +l.nop diff --git a/libgcc/config/or1k/crtn.S b/libgcc/config/or1k/crtn.S new file mode 100644 index 000..ca6ee7b6fba --- /dev/null +++ b/libgcc/config/or1k/crtn.S @@ -0,0 +1 @@ +/* crtn.S is empty because .init_array/.fini_array are used exclusively. */ diff --git a/libgcc/config/or1k/lib1funcs.S b/libgcc/config/or1k/lib1funcs.S new file mode 100644 index 000..354aadae8c4 --- /dev/null +++ b/libgcc/config/or1k/lib1funcs.S @@ -0,0 +1,223 @@ +/* Copyright (C) 2018 Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 3, or (at your option) any +later version. + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + + +#ifdef L__mulsi3 + .balign 4 + .globl __mulsi3 + .type __mulsi3, @function +__mulsi3: + l.movhi r11, 0 /* initial r */ + + /* Given R = X * Y ... */ +1: l.sfeq r4, r0
Re: [PATCH v2 1/3] or1k: libgcc: initial support for openrisc
On Thu, Oct 18, 2018 at 05:55:35PM -0600, Jeff Law wrote: > On 10/18/18 2:06 PM, Stafford Horne wrote: > > On Thu, Oct 18, 2018 at 03:22:56PM +0200, Sebastian Huber wrote: > >> Hello, > >> > >> is there a chance to get the or1k support integrated before the GCC 9 stage > >> 3? > > > > Hello, > > > > I would definitly like that and that is my goal. It seems the limiting > > factor > > is getting technical review and signoff on this set of patches. > > > > I will send out a PATCH v3 with a few minor enhancements gathered since v2 > > today > > or tomorrow. Then I will try to ping a few people if I dont get reviews by > > next > > week. > Also note that for a port with minimal bleed out (and I think the or1k > qualifies) we can still integrate it during stage3. BUt obviously it'd > better to get it in during stage1. Thanks for the info. Its good to know the hard deadline is not this month for me. Did you get any chance to look at the second patch series for the OpenRISC gcc patches? I added the function comments you were asking for. Also Richard fixed up a few other things you were mentioning. I understand you must be busy with the upcoming lockdown. -Stafford
Re: [PATCH v2 1/3] or1k: libgcc: initial support for openrisc
On Thu, Oct 18, 2018 at 03:22:56PM +0200, Sebastian Huber wrote: > Hello, > > is there a chance to get the or1k support integrated before the GCC 9 stage > 3? Hello, I would definitly like that and that is my goal. It seems the limiting factor is getting technical review and signoff on this set of patches. I will send out a PATCH v3 with a few minor enhancements gathered since v2 today or tomorrow. Then I will try to ping a few people if I dont get reviews by next week. -Stafford > -- > Sebastian Huber, embedded brains GmbH > > Address : Dornierstr. 4, D-82178 Puchheim, Germany > Phone : +49 89 189 47 41-16 > Fax : +49 89 189 47 41-09 > E-Mail : sebastian.hu...@embedded-brains.de > PGP : Public key available on request. > > Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG. >
Re: [PATCH v2 1/3] or1k: libgcc: initial support for openrisc
On Thu, Oct 04, 2018 at 05:36:58PM +, Joseph Myers wrote: > On Thu, 4 Oct 2018, Stafford Horne wrote: > > > +or1k-*-linux*) > > + tmake_file="$tmake_file or1k/t-or1k" > > + tmake_file="$tmake_file t-softfp-sfdf t-softfp-excl t-softfp" > > + md_unwind_header=or1k/linux-unwind.h > > + ;; > > +or1k-*-*) > > + tmake_file="$tmake_file or1k/t-or1k" > > + tmake_file="$tmake_file t-softfp-sfdf t-softfp-excl t-softfp" > > + extra_parts="$extra_parts crti.o crtn.o" > > + ;; > > Could you clarify why you are using t-softfp-excl? > > In general, for soft-float configurations it's best not to use > t-softfp-excl - meaning the floating-point operations from libgcc2.c get > implemented directly in soft-fp, rather than through libgcc2.c wrapping > other soft-fp operations. While for hard-float configurations it's best > not to use soft-fp at all. > > If you have hard-float configurations using a soft-float ABI, that thus > need to provide all the functions in question so soft-float objects / > programs can be linked with hard-float libgcc, t-hardfp should be used > instead when building a hard-float multilib. (It's possible to have more > complicated mixtures in cases where some operations or types come from > hardfp and others from softfp; some mips and powerpcspe configurations > do.) Hello, I don't know of a reason for using t-softfp-excl, I think Richard or I was just copying from what we saw similar targets do. I just removed it and reran some of the tests and don't see any regressions. We will be patching in hardfp post upstreaming, so the notes above are very helpful. -Stafford
[PATCH v2 1/3] or1k: libgcc: initial support for openrisc
-mm-dd Stafford Horne Richard Henderson libgcc/ChangeLog: * config.host: Add OpenRISC support. * config/or1k/*: New. --- Changes since v1: - Use __or1k_cmov__ in *.S to conditionally use l.cmov insn - Use init/fini array making the crti/crtn basically blank libgcc/config.host| 13 ++ libgcc/config/or1k/crti.S | 33 + libgcc/config/or1k/crtn.S | 1 + libgcc/config/or1k/lib1funcs.S| 223 ++ libgcc/config/or1k/linux-unwind.h | 87 libgcc/config/or1k/sfp-machine.h | 54 libgcc/config/or1k/t-or1k | 22 +++ 7 files changed, 433 insertions(+) create mode 100644 libgcc/config/or1k/crti.S create mode 100644 libgcc/config/or1k/crtn.S create mode 100644 libgcc/config/or1k/lib1funcs.S create mode 100644 libgcc/config/or1k/linux-unwind.h create mode 100644 libgcc/config/or1k/sfp-machine.h create mode 100644 libgcc/config/or1k/t-or1k diff --git a/libgcc/config.host b/libgcc/config.host index 029f6569caf..8f4cff743ad 100644 --- a/libgcc/config.host +++ b/libgcc/config.host @@ -165,6 +165,9 @@ nds32*-*) nios2*-*-*) cpu_type=nios2 ;; +or1k*-*-*) + cpu_type=or1k + ;; powerpc*-*-*) cpu_type=rs6000 ;; @@ -1039,6 +1042,16 @@ nios2-*-*) tmake_file="$tmake_file nios2/t-nios2 t-softfp-sfdf t-softfp-excl t-softfp" extra_parts="$extra_parts crti.o crtn.o" ;; +or1k-*-linux*) + tmake_file="$tmake_file or1k/t-or1k" + tmake_file="$tmake_file t-softfp-sfdf t-softfp-excl t-softfp" + md_unwind_header=or1k/linux-unwind.h + ;; +or1k-*-*) + tmake_file="$tmake_file or1k/t-or1k" + tmake_file="$tmake_file t-softfp-sfdf t-softfp-excl t-softfp" + extra_parts="$extra_parts crti.o crtn.o" + ;; pdp11-*-*) tmake_file="pdp11/t-pdp11 t-fdpbit" ;; diff --git a/libgcc/config/or1k/crti.S b/libgcc/config/or1k/crti.S new file mode 100644 index 000..9fcf6ae5995 --- /dev/null +++ b/libgcc/config/or1k/crti.S @@ -0,0 +1,33 @@ +/* Copyright (C) 2012-2018 Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 3, or (at your option) any +later version. + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + +/* Here _init and _fini are empty because .init_array/.fini_array are used + exclusively. However, the functions are still needed as required when + linking. */ + .align 4 + .global _init + .type _init,@function +_init: + .global _fini + .type _fini,@function +_fini: + l.jrr9 +l.nop diff --git a/libgcc/config/or1k/crtn.S b/libgcc/config/or1k/crtn.S new file mode 100644 index 000..ca6ee7b6fba --- /dev/null +++ b/libgcc/config/or1k/crtn.S @@ -0,0 +1 @@ +/* crtn.S is empty because .init_array/.fini_array are used exclusively. */ diff --git a/libgcc/config/or1k/lib1funcs.S b/libgcc/config/or1k/lib1funcs.S new file mode 100644 index 000..354aadae8c4 --- /dev/null +++ b/libgcc/config/or1k/lib1funcs.S @@ -0,0 +1,223 @@ +/* Copyright (C) 2018 Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 3, or (at your option) any +later version. + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +Under Section 7 of GPL version 3, you are granted additional +permissions described in the GCC Runtime Library Exception, version +3.1, as published by the Free Software Foundation. + +You should have received a copy of the GNU General Public License and +a copy of the GCC Runtime Library Exception along with this program; +see the files COPYING3 and COPYING.RUNTIME respectively. If not, see +<http://www.gnu.org/licenses/>. */ + + +#ifdef L__mulsi3 + .balign 4 + .globl __mulsi3 + .type
[PATCH v2 3/3] or1k: gcc: initial support for openrisc
-mm-dd Stafford Horne
Richard Henderson
gcc/ChangeLog:
* common/config/or1k/or1k-common.c: New file.
* config/or1k/*: New.
* config.gcc (or1k*-*-*): New.
* configure.ac (or1k*-*-*): New test for openrisc tls.
* configure: Regenerated.
* doc/install.texi: Document OpenRISC triplets.
* doc/invoke.texi: Document OpenRISC arguments.
* doc/md.texi: Document OpenRISC.
---
Changes Since v1:
- Document options in invoke.texi suggested by Joseph Myers
- Remove obsolete/incorrect macros suggested by Joseph Myers
- Documented or1k.c functions as requested by Jeff Law
- Add epilogue barriers suggested by Jeff Law
- Define SPECULATION_SAFE_VALUE suggested by Jeff Law
- Switch to init/fini array suggested by Richard Henderson
- Define and document multilib flags to enable disable instructions only
available on some CPU cores as requested on OpenRISC mailing list.
gcc/common/config/or1k/or1k-common.c | 41 +
gcc/config.gcc | 45 +
gcc/config/or1k/constraints.md | 55 +
gcc/config/or1k/elf.h| 42 +
gcc/config/or1k/elf.opt | 33 +
gcc/config/or1k/linux.h | 44 +
gcc/config/or1k/or1k-protos.h| 38 +
gcc/config/or1k/or1k.c | 2186 ++
gcc/config/or1k/or1k.h | 392 +
gcc/config/or1k/or1k.md | 894 +++
gcc/config/or1k/or1k.opt | 62 +
gcc/config/or1k/predicates.md| 84 +
gcc/config/or1k/t-or1k | 22 +
gcc/configure| 12 +
gcc/configure.ac | 12 +
gcc/doc/install.texi | 19 +
gcc/doc/invoke.texi | 62 +
gcc/doc/md.texi | 25 +
18 files changed, 4068 insertions(+)
create mode 100644 gcc/common/config/or1k/or1k-common.c
create mode 100644 gcc/config/or1k/constraints.md
create mode 100644 gcc/config/or1k/elf.h
create mode 100644 gcc/config/or1k/elf.opt
create mode 100644 gcc/config/or1k/linux.h
create mode 100644 gcc/config/or1k/or1k-protos.h
create mode 100644 gcc/config/or1k/or1k.c
create mode 100644 gcc/config/or1k/or1k.h
create mode 100644 gcc/config/or1k/or1k.md
create mode 100644 gcc/config/or1k/or1k.opt
create mode 100644 gcc/config/or1k/predicates.md
create mode 100644 gcc/config/or1k/t-or1k
diff --git a/gcc/common/config/or1k/or1k-common.c
b/gcc/common/config/or1k/or1k-common.c
new file mode 100644
index 000..044e843fd19
--- /dev/null
+++ b/gcc/common/config/or1k/or1k-common.c
@@ -0,0 +1,41 @@
+/* Common hooks for OpenRISC
+ Copyright (C) 2018 Free Software Foundation, Inc.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "diagnostic-core.h"
+#include "tm.h"
+#include "common/common-target.h"
+#include "common/common-target-def.h"
+#include "opts.h"
+#include "flags.h"
+
+/* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
+static const struct default_options or1k_option_optimization_table[] =
+ {
+/* Enable section anchors by default at -O1 or higher. */
+{ OPT_LEVELS_1_PLUS, OPT_fsection_anchors, NULL, 1 },
+{ OPT_LEVELS_NONE, 0, NULL, 0 }
+ };
+
+#undef TARGET_OPTION_OPTIMIZATION_TABLE
+#define TARGET_OPTION_OPTIMIZATION_TABLE or1k_option_optimization_table
+
+struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 0c579d1f5ea..0f7f8651b07 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -467,6 +467,9 @@ nios2-*-*)
nvptx-*-*)
cpu_type=nvptx
;;
+or1k*-*-*)
+ cpu_type=or1k
+ ;;
powerpc*-*-*spe*)
cpu_type=powerpcspe
extra_headers="ppc-asm.h altivec.h spe.h ppu_intrinsics.h paired.h
spu2vmx.h vec_types.h si2vmx.h htmintrin.h htmxlintrin.h"
@@ -2462,6 +2465,48 @@ nvptx-*)
tm_file="${tm_file} nvptx/offload.h"
fi
;;
+or1k*-*-*)
+ tm_file="elfos.h ${tm_file}"
+ tmake_file="${tmake_file} or1k/t-or1k"
+ # Force .init_array support. The configure script cannot always
+ #
[PATCH v2 0/3] OpenRISC port
Hello, Changes Since v1: - Document options in invoke.texi suggested by Joseph Myers - Remove obsolete/incorrect macros suggested by Joseph Myers - Documented or1k.c functions as requested by Jeff Law - Add epilogue barriers suggested by Jeff Law - Define SPECULATION_SAFE_VALUE suggested by Jeff Law - Define and document multilib flags to enable disable instructions only available on some CPU cores as requested on OpenRISC mailing list. Since February this year I have been working on an OpenRISC clean room rewrite. http://stffrdhrn.github.io/software/embedded/openrisc/2018/02/03/openrisc_gcc_rewrite.html As per the article, the old port had issues with some of the owners signing over FSF copyright. To get around this I discussed options with the group and in the end I opted for a clean room rewrite. The new code base has been written by me with lots of help from Richard Henderson. I trust that both of us have our FSF GCC copyright's in place. # Testing We have been running the GCC testsuite with newlib and musl libc. The results are good. See results published in a test build/release here: - https://github.com/stffrdhrn/gcc/releases/tag/or1k-9.0.0-20180730 # Building To build this requires some of the latest binutils patches submitted here: - https://gcc.gnu.org/ml/gcc-patches/2018-08/msg01506.html - git tree: https://github.com/stffrdhrn/binutils-gdb/tree/or1k-6 -Stafford Stafford Horne (3): or1k: libgcc: initial support for openrisc or1k: testsuite: initial support for openrisc or1k: gcc: initial support for openrisc gcc/common/config/or1k/or1k-common.c | 41 + gcc/config.gcc| 45 + gcc/config/or1k/constraints.md| 55 + gcc/config/or1k/elf.h | 42 + gcc/config/or1k/elf.opt | 33 + gcc/config/or1k/linux.h | 44 + gcc/config/or1k/or1k-protos.h | 38 + gcc/config/or1k/or1k.c| 2186 + gcc/config/or1k/or1k.h| 392 +++ gcc/config/or1k/or1k.md | 894 +++ gcc/config/or1k/or1k.opt | 62 + gcc/config/or1k/predicates.md | 84 + gcc/config/or1k/t-or1k| 22 + gcc/configure | 12 + gcc/configure.ac | 12 + gcc/doc/install.texi | 19 + gcc/doc/invoke.texi | 62 + gcc/doc/md.texi | 25 + .../gcc.c-torture/execute/20101011-1.c|3 + gcc/testsuite/gcc.dg/20020312-2.c |2 + gcc/testsuite/gcc.dg/attr-alloc_size-11.c |4 +- gcc/testsuite/gcc.dg/builtin-apply2.c |2 +- gcc/testsuite/gcc.dg/nop.h|2 + .../torture/stackalign/builtin-apply-2.c |2 +- gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c|2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-33.c|2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-34.c|2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-35.c|2 +- gcc/testsuite/gcc.dg/tree-ssa/reassoc-36.c|2 +- gcc/testsuite/gcc.target/or1k/args-1.c| 19 + gcc/testsuite/gcc.target/or1k/args-2.c| 15 + gcc/testsuite/gcc.target/or1k/cmov-1.c|8 + gcc/testsuite/gcc.target/or1k/cmov-2.c|9 + gcc/testsuite/gcc.target/or1k/div-mul-1.c |9 + gcc/testsuite/gcc.target/or1k/div-mul-2.c |9 + gcc/testsuite/gcc.target/or1k/or1k.exp| 41 + gcc/testsuite/gcc.target/or1k/return-1.c | 10 + gcc/testsuite/gcc.target/or1k/return-2.c | 19 + gcc/testsuite/gcc.target/or1k/return-3.c | 19 + gcc/testsuite/gcc.target/or1k/return-4.c | 19 + gcc/testsuite/gcc.target/or1k/sibcall-1.c | 18 + gcc/testsuite/lib/target-supports.exp |1 + libgcc/config.host| 13 + libgcc/config/or1k/crti.S | 33 + libgcc/config/or1k/crtn.S |1 + libgcc/config/or1k/lib1funcs.S| 223 ++ libgcc/config/or1k/linux-unwind.h | 87 + libgcc/config/or1k/sfp-machine.h | 54 + libgcc/config/or1k/t-or1k | 22 + 49 files changed, 4713 insertions(+), 9 deletions(-) create mode 100644 gcc/common/config/or1k/or1k-common.c create mode 100644 gcc/config/or1k/constraints.md create mode 100644 gcc/config/or1k/elf.h create mode 100644 gcc/config/or1k/elf.opt create mode 100644 gcc/config/or1k/linux.h create mode 100644 gcc/config/or1k/or1k-protos.h create mode 100644 gcc/config/or1k/or1k.c create mode 100644 gcc/config/or1k/or1k.h create mode 100644 gcc/config/or1k/or1k.md create mode 100644 gcc/config/or1k/or1k.opt create mode 100644 gcc/config/or1k/predicates.md create mode 100644 gcc/config/or1k/t-or1k create mode 100644 gcc
[PATCH v2 2/3] or1k: testsuite: initial support for openrisc
-mm-dd Stafford Horne
Richard Henderson
gcc/testsuite/ChangeLog:
* gcc.c-torture/execute/20101011-1.c: Adjust for OpenRISC.
* gcc.dg/20020312-2.c: Likewise.
* gcc.dg/attr-alloc_size-11.c: Likewise.
* gcc.dg/builtin-apply2.c: Likewise.
* gcc.dg/nop.h: Likewise.
* gcc.dg/torture/stackalign/builtin-apply-2.c: Likewise.
* gcc.dg/tree-ssa/20040204-1.c: Likewise.
* gcc.dg/tree-ssa/reassoc-33.c: Likewise.
* gcc.dg/tree-ssa/reassoc-34.c: Likewise.
* gcc.dg/tree-ssa/reassoc-35.c: Likewise.
* gcc.dg/tree-ssa/reassoc-36.c: Likewise.
* lib/target-supports.exp
(check_effective_target_logical_op_short_circuit): Add or1k*-*-*.
* gcc.target/or1k/*: New.
---
Changes since v1:
- Add cmov-* test which uses multilib -mcmov flag
.../gcc.c-torture/execute/20101011-1.c| 3 ++
gcc/testsuite/gcc.dg/20020312-2.c | 2 +
gcc/testsuite/gcc.dg/attr-alloc_size-11.c | 4 +-
gcc/testsuite/gcc.dg/builtin-apply2.c | 2 +-
gcc/testsuite/gcc.dg/nop.h| 2 +
.../torture/stackalign/builtin-apply-2.c | 2 +-
gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c| 2 +-
gcc/testsuite/gcc.dg/tree-ssa/reassoc-33.c| 2 +-
gcc/testsuite/gcc.dg/tree-ssa/reassoc-34.c| 2 +-
gcc/testsuite/gcc.dg/tree-ssa/reassoc-35.c| 2 +-
gcc/testsuite/gcc.dg/tree-ssa/reassoc-36.c| 2 +-
gcc/testsuite/gcc.target/or1k/args-1.c| 19 +
gcc/testsuite/gcc.target/or1k/args-2.c| 15 +++
gcc/testsuite/gcc.target/or1k/cmov-1.c| 8
gcc/testsuite/gcc.target/or1k/cmov-2.c| 9
gcc/testsuite/gcc.target/or1k/div-mul-1.c | 9
gcc/testsuite/gcc.target/or1k/div-mul-2.c | 9
gcc/testsuite/gcc.target/or1k/or1k.exp| 41 +++
gcc/testsuite/gcc.target/or1k/return-1.c | 10 +
gcc/testsuite/gcc.target/or1k/return-2.c | 19 +
gcc/testsuite/gcc.target/or1k/return-3.c | 19 +
gcc/testsuite/gcc.target/or1k/return-4.c | 19 +
gcc/testsuite/gcc.target/or1k/sibcall-1.c | 18
gcc/testsuite/lib/target-supports.exp | 1 +
24 files changed, 212 insertions(+), 9 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/or1k/args-1.c
create mode 100644 gcc/testsuite/gcc.target/or1k/args-2.c
create mode 100644 gcc/testsuite/gcc.target/or1k/cmov-1.c
create mode 100644 gcc/testsuite/gcc.target/or1k/cmov-2.c
create mode 100644 gcc/testsuite/gcc.target/or1k/div-mul-1.c
create mode 100644 gcc/testsuite/gcc.target/or1k/div-mul-2.c
create mode 100644 gcc/testsuite/gcc.target/or1k/or1k.exp
create mode 100644 gcc/testsuite/gcc.target/or1k/return-1.c
create mode 100644 gcc/testsuite/gcc.target/or1k/return-2.c
create mode 100644 gcc/testsuite/gcc.target/or1k/return-3.c
create mode 100644 gcc/testsuite/gcc.target/or1k/return-4.c
create mode 100644 gcc/testsuite/gcc.target/or1k/sibcall-1.c
diff --git a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
index f95d900deaf..8c9b75933ec 100644
--- a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
+++ b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
@@ -97,6 +97,9 @@ __aeabi_idiv0 (int return_value)
/* This presently doesn't raise SIGFPE even on csky-linux-gnu, much
less bare metal. See the implementation of __divsi3 in libgcc. */
# define DO_TEST 0
+#elif defined (__or1k__)
+ /* On OpenRISC division by zero does not trap. */
+# define DO_TEST 0
#else
# define DO_TEST 1
#endif
diff --git a/gcc/testsuite/gcc.dg/20020312-2.c
b/gcc/testsuite/gcc.dg/20020312-2.c
index 1a8afd81506..e72a5b261ae 100644
--- a/gcc/testsuite/gcc.dg/20020312-2.c
+++ b/gcc/testsuite/gcc.dg/20020312-2.c
@@ -117,6 +117,8 @@ extern void abort (void);
# if defined (__CK807__) || defined (__CK810__)
# define PIC_REG "r28"
# endif
+#elif defined (__or1k__)
+/* No pic register. */
#else
# error "Modify the test for your target."
#endif
diff --git a/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
b/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
index 3ec44dc1463..6bb904f4794 100644
--- a/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
+++ b/gcc/testsuite/gcc.dg/attr-alloc_size-11.c
@@ -47,8 +47,8 @@ typedef __SIZE_TYPE__size_t;
/* The following tests fail because of missing range information. The xfail
exclusions are PR79356. */
-TEST (signed char, SCHAR_MIN + 2, ALLOC_MAX); /* { dg-warning "argument 1
range \\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info
for signed char" { xfail { ! { aarch64*-*-* arm*-*-* avr-*-* alpha*-*-*
ia64-*-* mips*-*-* powerpc*-*-* sparc*-*-* s390*-*-* visium-*-* } } } } */
-TEST (short, SHRT_MIN + 2, ALLOC_MAX); /* { dg-warning "argument 1 range
\\\[13, \[0-9\]+\\\] exceeds maximum object size 12" "missing range info for
short"
