Re: [PATCH v2] Add error message for target_clones and AVX512 ISAs (PR target/89929).
On Thu, Apr 25, 2019 at 1:03 AM Uros Bizjak wrote:
>
>
>
> On Thu, Apr 25, 2019 at 9:51 AM Martin Liška wrote:
>>
>> On 4/23/19 10:29 AM, Martin Liška wrote:
>> > On 4/18/19 7:44 PM, H.J. Lu wrote:
>> >> On Thu, Apr 18, 2019 at 4:07 AM Martin Liška wrote:
>> >>>
>> >>> Hi.
>> >>>
>> >>> I'm sending updated version of that patch. The patch rejects usage of
>> >>> AVX512 ISAs (except AVX512F)
>> >>> for target attribute for C++ multiversioning and for target_clone
>> >>> attribute.
>> >>>
>> >>> Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
>> >>>
>> >>> Ready to be installed?
>> >>> Thanks,
>> >>> Martin
>> >>
>> >> Your patch doesn't handle cmov nor gfni properly, which aren't AVX512.
>> >> I prefer this patch.
>> >>
>> >
>> > I like the patch. Thanks for working on that.
>> >
>> > Martin
>> >
>> >
>>
>> Btw. can we get that patch into GCC 9.1?
>>
>> Adding port maintainers to CC.
>
>
> HJ knows ISA interdependencies, and the benefit of the patch outweights the
> (small) risk, so from the maintaner PoV, OK for the mainline unless RM vetoes
> the decision soon. HJ, please double check the patch for eventual
> inconsistencies or possible regressions before committing.
>
> Thanks,
> Uros.
Tested on x86-64. I am checking in this updated patch with:
diff --git a/gcc/testsuite/g++.target/i386/pr57362.C b/gcc/testsuite/g++.target/
i386/pr57362.C
index 5e612130357..ced5e518cfe 100644
--- a/gcc/testsuite/g++.target/i386/pr57362.C
+++ b/gcc/testsuite/g++.target/i386/pr57362.C
@@ -199,4 +199,4 @@ int foo(void) { return 1; }
/* { dg-prune-output "attribute.* is unknown" } */
/* { dg-prune-output "missing 'target' attribute*" } */
/* { dg-prune-output "redefinition of 'int foo" } */
-/* { dg-prune-output "no dispatcher found for" } */
+/* { dg-prune-output "ISA '.*' is not supported in 'target' attribute" } */
--
H.J.
From 79013fe56d7ca7588dc9dbebdeb64f869e15e278 Mon Sep 17 00:00:00 2001
From: "H.J. Lu"
Date: Thu, 18 Apr 2019 09:49:58 -0700
Subject: [PATCH] x86: Update message for target_clones and unsupported ISAs
Before AVX512F, processors with the newer ISAs also support the older
ISAs, i.e., AVX2 processors also support AVX and SSE4, SSE4 processors
also support SSSE3, ... After AVX512F, an AVX512XX processor may not
support AVX512YY. It means AVX512XX features, except for AVX512F, can't
be used to decide priority in target_clones.
This patch updates error message for ISAs with P_ZERO priority. It also
merges _feature_list into _isa_names_table and marks ISAs, which have
unknown priority, with P_ZERO so that we only need to update one place
to add a new ISA feature.
gcc/
2019-04-25 H.J. Lu
PR target/89929
* config/i386/i386.c (feature_priority): Moved to file scope.
(processor_features): Likewise.
(processor_model): Likewise.
(_arch_names_table): Likewise.
(arch_names_table): Likewise.
(_feature_list): Removed.
(feature_list): Likewise.
(_isa_names_table): Moved to file scope. Add priority.
(isa_names_table): Likewise.
(get_builtin_code_for_version): Replace feature_list with
isa_names_table. Update error message for P_ZERO priority.
gcc/testsuite/
2019-04-25 Martin Liska
H.J. Lu
PR target/89929
* g++.target/i386/mv28.C: New test.
* gcc.target/i386/mvc14.c: Likewise.
* g++.target/i386/pr57362.C: Updated.
---
gcc/config/i386/i386.c | 490 +++-
gcc/testsuite/g++.target/i386/mv28.C| 26 ++
gcc/testsuite/g++.target/i386/pr57362.C | 2 +-
gcc/testsuite/gcc.target/i386/mvc14.c | 16 +
4 files changed, 275 insertions(+), 259 deletions(-)
create mode 100644 gcc/testsuite/g++.target/i386/mv28.C
create mode 100644 gcc/testsuite/gcc.target/i386/mvc14.c
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 191f570455b..8a1ffd3769f 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -31834,6 +31834,229 @@ add_condition_to_bb (tree function_decl, tree version_decl,
return bb3;
}
+/* Priority of i386 features, greater value is higher priority. This is
+ used to decide the order in which function dispatch must happen. For
+ instance, a version specialized for SSE4.2 should be checked for dispatch
+ before a version for SSE3, as SSE4.2 implies SSE3. */
+enum feature_priority
+{
+ P_ZERO = 0,
+ P_MMX,
+ P_SSE,
+ P_SSE2,
+ P_SSE3,
+ P_SSSE3,
+ P_PROC_SSSE3,
+ P_SSE4_A,
+ P_PROC_SSE4_A,
+ P_SSE4_1,
+ P_SSE4_2,
+ P_PROC_SSE4_2,
+ P_POPCNT,
+ P_AES,
+ P_PCLMUL,
+ P_AVX,
+ P_PROC_AVX,
+ P_BMI,
+ P_PROC_BMI,
+ P_FMA4,
+ P_XOP,
+ P_PROC_XOP,
+ P_FMA,
+ P_PROC_FMA,
+ P_BMI2,
+ P_AVX2,
+ P_PROC_AVX2,
+ P_AVX512F,
+ P_PROC_AVX512F
+};
+
+/* This is the order of bit-fields in __processor_features in cpuinfo.c */
+enum processor_features
+{
+ F_CMOV = 0,
+ F_MMX,
+ F_POPCNT,
+ F_SSE,
+ F_SSE2,
+ F_SSE3,
+ F_SSSE3,
+ F_SSE4_1,
+ F_SSE4_2,
+ F_AVX,
+ F_AVX2,
+ F_SSE4_A,
+ F_FMA4,
+ F_XOP,
+ F_FMA,
+ F_AVX512F,
+ F_BMI,
+
Re: [PATCH v2] Add error message for target_clones and AVX512 ISAs (PR target/89929).
On Thu, Apr 25, 2019 at 9:51 AM Martin Liška wrote: > On 4/23/19 10:29 AM, Martin Liška wrote: > > On 4/18/19 7:44 PM, H.J. Lu wrote: > >> On Thu, Apr 18, 2019 at 4:07 AM Martin Liška wrote: > >>> > >>> Hi. > >>> > >>> I'm sending updated version of that patch. The patch rejects usage of > AVX512 ISAs (except AVX512F) > >>> for target attribute for C++ multiversioning and for target_clone > attribute. > >>> > >>> Patch can bootstrap on x86_64-linux-gnu and survives regression tests. > >>> > >>> Ready to be installed? > >>> Thanks, > >>> Martin > >> > >> Your patch doesn't handle cmov nor gfni properly, which aren't AVX512. > >> I prefer this patch. > >> > > > > I like the patch. Thanks for working on that. > > > > Martin > > > > > > Btw. can we get that patch into GCC 9.1? > > Adding port maintainers to CC. > HJ knows ISA interdependencies, and the benefit of the patch outweights the (small) risk, so from the maintaner PoV, OK for the mainline unless RM vetoes the decision soon. HJ, please double check the patch for eventual inconsistencies or possible regressions before committing. Thanks, Uros.
Re: [PATCH v2] Add error message for target_clones and AVX512 ISAs (PR target/89929).
On 4/23/19 10:29 AM, Martin Liška wrote: > On 4/18/19 7:44 PM, H.J. Lu wrote: >> On Thu, Apr 18, 2019 at 4:07 AM Martin Liška wrote: >>> >>> Hi. >>> >>> I'm sending updated version of that patch. The patch rejects usage of >>> AVX512 ISAs (except AVX512F) >>> for target attribute for C++ multiversioning and for target_clone attribute. >>> >>> Patch can bootstrap on x86_64-linux-gnu and survives regression tests. >>> >>> Ready to be installed? >>> Thanks, >>> Martin >> >> Your patch doesn't handle cmov nor gfni properly, which aren't AVX512. >> I prefer this patch. >> > > I like the patch. Thanks for working on that. > > Martin > > Btw. can we get that patch into GCC 9.1? Adding port maintainers to CC. Martin
Re: [PATCH v2] Add error message for target_clones and AVX512 ISAs (PR target/89929).
On 4/18/19 7:44 PM, H.J. Lu wrote: > On Thu, Apr 18, 2019 at 4:07 AM Martin Liška wrote: >> >> Hi. >> >> I'm sending updated version of that patch. The patch rejects usage of AVX512 >> ISAs (except AVX512F) >> for target attribute for C++ multiversioning and for target_clone attribute. >> >> Patch can bootstrap on x86_64-linux-gnu and survives regression tests. >> >> Ready to be installed? >> Thanks, >> Martin > > Your patch doesn't handle cmov nor gfni properly, which aren't AVX512. > I prefer this patch. > I like the patch. Thanks for working on that. Martin
Re: [PATCH v2] Add error message for target_clones and AVX512 ISAs (PR target/89929).
On Thu, Apr 18, 2019 at 4:07 AM Martin Liška wrote:
>
> Hi.
>
> I'm sending updated version of that patch. The patch rejects usage of AVX512
> ISAs (except AVX512F)
> for target attribute for C++ multiversioning and for target_clone attribute.
>
> Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
>
> Ready to be installed?
> Thanks,
> Martin
Your patch doesn't handle cmov nor gfni properly, which aren't AVX512.
I prefer this patch.
--
H.J.
From 6089577be432bdd22fc89bf40e363c4af6876987 Mon Sep 17 00:00:00 2001
From: "H.J. Lu"
Date: Thu, 18 Apr 2019 09:49:58 -0700
Subject: [PATCH] x86: Update message for target_clones and unsupported ISAs
Before AVX512F, processors with the newer ISAs also support the older
ISAs, i.e., AVX2 processors also support AVX and SSE4, SSE4 processors
also support SSSE3, ... After AVX512F, an AVX512XX processor may not
support AVX512YY. It means AVX512XX features, except for AVX512F, can't
be used to decide priority in target_clones.
This patch updates error message for ISAs with P_ZERO priority. It also
merges _feature_list into _isa_names_table and marks ISAs, which have
unknown priority, with P_ZERO so that we only need to update one place
to add a new ISA feature.
gcc/
2019-04-18 H.J. Lu
PR target/89929
* config/i386/i386.c (feature_priority): Moved to file scope.
(processor_features): Likewise.
(processor_model): Likewise.
(_arch_names_table): Likewise.
(arch_names_table): Likewise.
(_feature_list): Removed.
(feature_list): Likewise.
(_isa_names_table): Moved to file scope. Add priority.
(isa_names_table): Likewise.
(get_builtin_code_for_version): Replace feature_list with
isa_names_table. Update error message for P_ZERO priority.
gcc/testsuite/
2019-04-18 Martin Liska
PR target/89929
* g++.target/i386/mv28.C: New test.
* gcc.target/i386/mvc14.c: New test.
---
gcc/config/i386/i386.c| 490 --
gcc/testsuite/g++.target/i386/mv28.C | 26 ++
gcc/testsuite/gcc.target/i386/mvc14.c | 16 +
3 files changed, 274 insertions(+), 258 deletions(-)
create mode 100644 gcc/testsuite/g++.target/i386/mv28.C
create mode 100644 gcc/testsuite/gcc.target/i386/mvc14.c
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 498a35d8aea..198af816f74 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -31832,6 +31832,229 @@ add_condition_to_bb (tree function_decl, tree version_decl,
return bb3;
}
+/* Priority of i386 features, greater value is higher priority. This is
+ used to decide the order in which function dispatch must happen. For
+ instance, a version specialized for SSE4.2 should be checked for dispatch
+ before a version for SSE3, as SSE4.2 implies SSE3. */
+enum feature_priority
+{
+ P_ZERO = 0,
+ P_MMX,
+ P_SSE,
+ P_SSE2,
+ P_SSE3,
+ P_SSSE3,
+ P_PROC_SSSE3,
+ P_SSE4_A,
+ P_PROC_SSE4_A,
+ P_SSE4_1,
+ P_SSE4_2,
+ P_PROC_SSE4_2,
+ P_POPCNT,
+ P_AES,
+ P_PCLMUL,
+ P_AVX,
+ P_PROC_AVX,
+ P_BMI,
+ P_PROC_BMI,
+ P_FMA4,
+ P_XOP,
+ P_PROC_XOP,
+ P_FMA,
+ P_PROC_FMA,
+ P_BMI2,
+ P_AVX2,
+ P_PROC_AVX2,
+ P_AVX512F,
+ P_PROC_AVX512F
+};
+
+/* This is the order of bit-fields in __processor_features in cpuinfo.c */
+enum processor_features
+{
+ F_CMOV = 0,
+ F_MMX,
+ F_POPCNT,
+ F_SSE,
+ F_SSE2,
+ F_SSE3,
+ F_SSSE3,
+ F_SSE4_1,
+ F_SSE4_2,
+ F_AVX,
+ F_AVX2,
+ F_SSE4_A,
+ F_FMA4,
+ F_XOP,
+ F_FMA,
+ F_AVX512F,
+ F_BMI,
+ F_BMI2,
+ F_AES,
+ F_PCLMUL,
+ F_AVX512VL,
+ F_AVX512BW,
+ F_AVX512DQ,
+ F_AVX512CD,
+ F_AVX512ER,
+ F_AVX512PF,
+ F_AVX512VBMI,
+ F_AVX512IFMA,
+ F_AVX5124VNNIW,
+ F_AVX5124FMAPS,
+ F_AVX512VPOPCNTDQ,
+ F_AVX512VBMI2,
+ F_GFNI,
+ F_VPCLMULQDQ,
+ F_AVX512VNNI,
+ F_AVX512BITALG,
+ F_MAX
+};
+
+/* These are the values for vendor types and cpu types and subtypes
+ in cpuinfo.c. Cpu types and subtypes should be subtracted by
+ the corresponding start value. */
+enum processor_model
+{
+ M_INTEL = 1,
+ M_AMD,
+ M_CPU_TYPE_START,
+ M_INTEL_BONNELL,
+ M_INTEL_CORE2,
+ M_INTEL_COREI7,
+ M_AMDFAM10H,
+ M_AMDFAM15H,
+ M_INTEL_SILVERMONT,
+ M_INTEL_KNL,
+ M_AMD_BTVER1,
+ M_AMD_BTVER2,
+ M_AMDFAM17H,
+ M_INTEL_KNM,
+ M_INTEL_GOLDMONT,
+ M_INTEL_GOLDMONT_PLUS,
+ M_INTEL_TREMONT,
+ M_CPU_SUBTYPE_START,
+ M_INTEL_COREI7_NEHALEM,
+ M_INTEL_COREI7_WESTMERE,
+ M_INTEL_COREI7_SANDYBRIDGE,
+ M_AMDFAM10H_BARCELONA,
+ M_AMDFAM10H_SHANGHAI,
+ M_AMDFAM10H_ISTANBUL,
+ M_AMDFAM15H_BDVER1,
+ M_AMDFAM15H_BDVER2,
+ M_AMDFAM15H_BDVER3,
+ M_AMDFAM15H_BDVER4,
+ M_AMDFAM17H_ZNVER1,
+ M_INTEL_COREI7_IVYBRIDGE,
+ M_INTEL_COREI7_HASWELL,
+ M_INTEL_COREI7_BROADWELL,
+ M_INTEL_COREI7_SKYLAKE,
+ M_INTEL_COREI7_SKYLAKE_AVX512,
+ M_INTEL_COREI7_CANNONLAKE,
+ M_INTEL_COREI7_ICELAKE_CLIENT,
+ M_INTEL_COREI7_ICELAKE_SERVER,
+ M_AMDFAM17H_ZNVER2,
+ M_INTEL_COREI7_CASCADELAKE
+};
+
+struct _arch_names_table
+{
+ const char *const name;
+ const enum processor_model model;
[PATCH v2] Add error message for target_clones and AVX512 ISAs (PR target/89929).
Hi.
I'm sending updated version of that patch. The patch rejects usage of AVX512
ISAs (except AVX512F)
for target attribute for C++ multiversioning and for target_clone attribute.
Patch can bootstrap on x86_64-linux-gnu and survives regression tests.
Ready to be installed?
Thanks,
Martin
>From 6a7119cbdb908a2a7bd8017c64e084b5f20b3052 Mon Sep 17 00:00:00 2001
From: marxin
Date: Wed, 17 Apr 2019 14:01:21 +0200
Subject: [PATCH] Add error message for target_clones and AVX512 ISAs (PR
target/89929).
gcc/ChangeLog:
2019-04-18 Martin Liska
PR target/89929
* config/i386/i386.c (get_builtin_code_for_version): Provide new
error for AVX512 ISAs.
gcc/testsuite/ChangeLog:
2019-04-18 Martin Liska
PR target/89929
* g++.target/i386/mv28.C: New test.
* gcc.target/i386/mvc14.c: New test.
---
gcc/config/i386/i386.c| 27 +++
gcc/testsuite/g++.target/i386/mv28.C | 26 ++
gcc/testsuite/gcc.target/i386/mvc14.c | 16
3 files changed, 69 insertions(+)
create mode 100644 gcc/testsuite/g++.target/i386/mv28.C
create mode 100644 gcc/testsuite/gcc.target/i386/mvc14.c
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 498a35d8aea..ed9a9c2e3f7 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -31920,6 +31920,24 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
{"avx512f", P_AVX512F}
};
+ static const char * avx512_warning_isas[] = {
+ "avx5124fmaps",
+ "avx5124vnniw",
+ "avx512vpopcntdq",
+ "avx512vbmi2",
+ "avx512vnni",
+ "avx512bitalg",
+ "avx512vbmi",
+ "avx512ifma",
+ "avx512vl",
+ "avx512bw",
+ "avx512dq",
+ "avx512er",
+ "avx512pf",
+ "avx512cd",
+ "gfni",
+ "vpclmulqdq",
+ };
static unsigned int NUM_FEATURES
= sizeof (feature_list) / sizeof (struct _feature_list);
@@ -32140,6 +32158,15 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
}
if (predicate_list && i == NUM_FEATURES)
{
+ for (unsigned i = 0; i < ARRAY_SIZE (avx512_warning_isas); i++)
+ if (strcmp (token, avx512_warning_isas[i]) == 0)
+ {
+ error_at (DECL_SOURCE_LOCATION (decl),
+ "AVX512 ISA %qs is not supported in "
+ "% attribute, use % syntax", token);
+ return 0;
+ }
+
error_at (DECL_SOURCE_LOCATION (decl),
"no dispatcher found for %s", token);
return 0;
diff --git a/gcc/testsuite/g++.target/i386/mv28.C b/gcc/testsuite/g++.target/i386/mv28.C
new file mode 100644
index 000..a33efd9cf21
--- /dev/null
+++ b/gcc/testsuite/g++.target/i386/mv28.C
@@ -0,0 +1,26 @@
+/* { dg-do compile} */
+/* { dg-require-ifunc "" } */
+
+void __attribute__ ((target("avx512vl"))) foo () {} /* { dg-error "AVX512 ISA '\[^\n\r\]*' is not supported in 'target' attribute, use 'arch=' syntax" } */
+void __attribute__ ((target("avx512bw"))) foo () {} /* { dg-error "AVX512 ISA '\[^\n\r\]*' is not supported in 'target' attribute, use 'arch=' syntax" } */
+void __attribute__ ((target("avx512dq"))) foo () {} /* { dg-error "AVX512 ISA '\[^\n\r\]*' is not supported in 'target' attribute, use 'arch=' syntax" } */
+void __attribute__ ((target("avx512cd"))) foo () {} /* { dg-error "AVX512 ISA '\[^\n\r\]*' is not supported in 'target' attribute, use 'arch=' syntax" } */
+void __attribute__ ((target("avx512er"))) foo () {} /* { dg-error "AVX512 ISA '\[^\n\r\]*' is not supported in 'target' attribute, use 'arch=' syntax" } */
+void __attribute__ ((target("avx512pf"))) foo () {} /* { dg-error "AVX512 ISA '\[^\n\r\]*' is not supported in 'target' attribute, use 'arch=' syntax" } */
+void __attribute__ ((target("avx512vbmi"))) foo () {} /* { dg-error "AVX512 ISA '\[^\n\r\]*' is not supported in 'target' attribute, use 'arch=' syntax" } */
+void __attribute__ ((target("avx512ifma"))) foo () {} /* { dg-error "AVX512 ISA '\[^\n\r\]*' is not supported in 'target' attribute, use 'arch=' syntax" } */
+void __attribute__ ((target("avx5124vnniw"))) foo () {} /* { dg-error "AVX512 ISA '\[^\n\r\]*' is not supported in 'target' attribute, use 'arch=' syntax" } */
+void __attribute__ ((target("avx5124fmaps"))) foo () {} /* { dg-error "AVX512 ISA '\[^\n\r\]*' is not supported in 'target' attribute, use 'arch=' syntax" } */
+void __attribute__ ((target("avx512vpopcntdq"))) foo () {} /* { dg-error "AVX512 ISA '\[^\n\r\]*' is not supported in 'target' attribute, use 'arch=' syntax" } */
+void __attribute__ ((target("avx512vbmi2"))) foo () {} /* { dg-error "AVX512 ISA '\[^\n\r\]*' is not supported in 'target' attribute, use 'arch=' syntax" } */
+void __attribute__ ((target("gfni"))) foo () {} /* { dg-error "AVX512 ISA '\[^\n\r\]*' is not supported in 'target' attribute, use 'arch=' syntax" } */
+void __attribute__ ((target("vpclmulqdq"))) foo () {} /* { dg-error "AVX512 ISA '\[^\n\r\]*' is not supported in 'target' attribute, use 'arch=' syntax" } */
+void __attribute__
