Re: [PATCH v2] aarch64: Add TX3 machine model
On Wed, Apr 22, 2020 at 8:25 PM Joel Jones wrote: > > Yes, Bellsoft's contribution is to be covered under the Marvell copyright > > assignment, as this is a work for hire. Thanks ! Ramana > > > > Joel > > > > >Yes, Bellsoft's contribution is to be covered under the Marvell copyright > > >assignment, as this is a work for hire. > > > > > >Joel > > > > > >>>Hi Anton, > > >>> > > >>>> -Original Message- > > >>>> From: Gcc-patches On Behalf Of Anton > > >>>> Youdkevitch > > >>>> Sent: 20 April 2020 19:29 > > >>>> To: gcc-patches@gcc.gnu.org > > >>>> Cc: jo...@marvell.com > > >>>> Subject: [PATCH v2] aarch64: Add TX3 machine model > > >>>> > > >>>> Here is the patch introducing thunderxt311 maching model > > >>>> for the scheduler. A name for the new chip was added to the > > >>>> list of the names to be recognized as a valid parameter for mcpu > > >>>> and mtune flags. The TX2 cost model was reused for TX3. > > >>>> > > >>>> The previously used "cryptic" name for the command line > > >>>> parameter is replaced with the same "thunderxt311" name. > > >>>> > > >>>> Bootstrapped on AArch64. > > >>> > > >>>Thanks for the patch. I had meant to ask, do you have a copyright > >>>assignment in place? > > >>>We'd need one to accept a contribution of this size. > > >>>Thanks, > > >>>Kyrill > > >>> > > >>>> > > >>>> 2020-04-20 Anton Youdkevitch > > >>>> > > >>>> * config/aarch64/aarch64-cores.def: Add the chip name. > > >>>> * config/aarch64/aarch64-tune.md: Regenerated. > > >>>> * gcc/config/aarch64/aarch64.c: Add the cost tables for the chip. > > >>>> * gcc/config/aarch64/thunderx3t11.md: New file: add the new > > >>>> machine model for the scheduler > > >>>> * gcc/config/aarch64/aarch64.md: Include the new model. > > >>>> > > >>>> --- > > >>>> gcc/config/aarch64/aarch64-cores.def | 3 + > > >>>> gcc/config/aarch64/aarch64-tune.md | 2 +- > > >>>> gcc/config/aarch64/aarch64.c | 27 + > > >>>> gcc/config/aarch64/aarch64.md| 1 + > > >>>> gcc/config/aarch64/thunderx3t11.md | 686 +++ > > >>>> 5 files changed, 718 insertions(+), 1 deletion(-) > > >>> > > >>> > > >>> > > >>> > > >
Re: [PATCH v2] aarch64: Add TX3 machine model
Hi Kyrylo,
On 23.4.2020 11:29 , Kyrylo Tkachov wrote:
Hi Anton,
Thanks to you and Joel for clarifying the copyright assignment...
-Original Message-
From: Gcc-patches On Behalf Of Anton
Youdkevitch
Sent: 20 April 2020 19:29
To: gcc-patches@gcc.gnu.org
Cc: jo...@marvell.com
Subject: [PATCH v2] aarch64: Add TX3 machine model
Here is the patch introducing thunderxt311 maching model
for the scheduler. A name for the new chip was added to the
list of the names to be recognized as a valid parameter for mcpu
and mtune flags. The TX2 cost model was reused for TX3.
The previously used "cryptic" name for the command line
parameter is replaced with the same "thunderxt311" name.
Bootstrapped on AArch64.
2020-04-20 Anton Youdkevitch
* config/aarch64/aarch64-cores.def: Add the chip name.
* config/aarch64/aarch64-tune.md: Regenerated.
* gcc/config/aarch64/aarch64.c: Add the cost tables for the chip.
* gcc/config/aarch64/thunderx3t11.md: New file: add the new
machine model for the scheduler
* gcc/config/aarch64/aarch64.md: Include the new model.
No "gcc/" in the path here.
Also, please add an entry in the documentation in doc/invoke.texi for the new
option.
Yes, sure, I missed that.
Will correct.
---
gcc/config/aarch64/aarch64-cores.def | 3 +
gcc/config/aarch64/aarch64-tune.md | 2 +-
gcc/config/aarch64/aarch64.c | 27 +
gcc/config/aarch64/aarch64.md| 1 +
gcc/config/aarch64/thunderx3t11.md | 686 +++
5 files changed, 718 insertions(+), 1 deletion(-)
diff --git a/gcc/config/aarch64/aarch64-cores.def
b/gcc/config/aarch64/aarch64-cores.def
index ea9b98b..ece6c34 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -95,6 +95,9 @@ AARCH64_CORE("vulcan", vulcan, thunderx2t99, 8_1A,
AARCH64_FL_FOR_ARCH8_1 | AA
/* Cavium ('C') cores. */
AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A,
AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx2t99, 0x43, 0x0af, -1)
+/* Cavium ('??') cores (TX3). */
+AARCH64_CORE("thunderx3t11", thunderx3t11, thunderx3t11, 8_1A,
AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx3t11, 0x43, 0x0b8, 0x0a)
+
I appreciate this is early CPU enablement and documentation is not always ready, but
would it be better to use a "Marvell cores" comment above that entry? Up to you.
The more important thing is the architecture features enabled. The entry here
means it's an Armv8.1-a CPU (with crypto).
From what I can find on the Internet [1] this CPU has Armv8.3-a features. Can
you please double-check that and update the flags here, if necessary?
It would be a shame to miss out on architecture enablement for
-mcpu=thunderx3t11 due to a flag mismatch.
No, I was using the wrong version. It has to be corrected.
Thanks a lot for you comments.
--
Anton
RE: [PATCH v2] aarch64: Add TX3 machine model
Hi Anton,
Thanks to you and Joel for clarifying the copyright assignment...
> -Original Message-
> From: Gcc-patches On Behalf Of Anton
> Youdkevitch
> Sent: 20 April 2020 19:29
> To: gcc-patches@gcc.gnu.org
> Cc: jo...@marvell.com
> Subject: [PATCH v2] aarch64: Add TX3 machine model
>
> Here is the patch introducing thunderxt311 maching model
> for the scheduler. A name for the new chip was added to the
> list of the names to be recognized as a valid parameter for mcpu
> and mtune flags. The TX2 cost model was reused for TX3.
>
> The previously used "cryptic" name for the command line
> parameter is replaced with the same "thunderxt311" name.
>
> Bootstrapped on AArch64.
>
> 2020-04-20 Anton Youdkevitch
>
> * config/aarch64/aarch64-cores.def: Add the chip name.
> * config/aarch64/aarch64-tune.md: Regenerated.
> * gcc/config/aarch64/aarch64.c: Add the cost tables for the chip.
> * gcc/config/aarch64/thunderx3t11.md: New file: add the new
> machine model for the scheduler
> * gcc/config/aarch64/aarch64.md: Include the new model.
No "gcc/" in the path here.
Also, please add an entry in the documentation in doc/invoke.texi for the new
option.
>
> ---
> gcc/config/aarch64/aarch64-cores.def | 3 +
> gcc/config/aarch64/aarch64-tune.md | 2 +-
> gcc/config/aarch64/aarch64.c | 27 +
> gcc/config/aarch64/aarch64.md| 1 +
> gcc/config/aarch64/thunderx3t11.md | 686 +++
> 5 files changed, 718 insertions(+), 1 deletion(-)
diff --git a/gcc/config/aarch64/aarch64-cores.def
b/gcc/config/aarch64/aarch64-cores.def
index ea9b98b..ece6c34 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -95,6 +95,9 @@ AARCH64_CORE("vulcan", vulcan, thunderx2t99, 8_1A,
AARCH64_FL_FOR_ARCH8_1 | AA
/* Cavium ('C') cores. */
AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A,
AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx2t99, 0x43, 0x0af, -1)
+/* Cavium ('??') cores (TX3). */
+AARCH64_CORE("thunderx3t11", thunderx3t11, thunderx3t11, 8_1A,
AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx3t11, 0x43, 0x0b8, 0x0a)
+
I appreciate this is early CPU enablement and documentation is not always
ready, but would it be better to use a "Marvell cores" comment above that
entry? Up to you.
The more important thing is the architecture features enabled. The entry here
means it's an Armv8.1-a CPU (with crypto).
>From what I can find on the Internet [1] this CPU has Armv8.3-a features. Can
>you please double-check that and update the flags here, if necessary?
It would be a shame to miss out on architecture enablement for
-mcpu=thunderx3t11 due to a flag mismatch.
Thanks,
Kyrill
[1]
https://www.anandtech.com/show/15621/marvell-announces-thunderx3-96-cores-384-thread-3rd-gen-arm-server-processor
[PATCH v2] aarch64: Add TX3 machine model
Yes, Bellsoft's contribution is to be covered under the Marvell copyright assignment, as this is a work for hire. Joel >Yes, Bellsoft's contribution is to be covered under the Marvell copyright >assignment, as this is a work for hire. > >Joel > >>>Hi Anton, >>> >>>> -Original Message- >>>> From: Gcc-patches On Behalf Of Anton >>>> Youdkevitch >>>> Sent: 20 April 2020 19:29 >>>> To: gcc-patches@gcc.gnu.org >>>> Cc: jo...@marvell.com >>>> Subject: [PATCH v2] aarch64: Add TX3 machine model >>>> >>>> Here is the patch introducing thunderxt311 maching model >>>> for the scheduler. A name for the new chip was added to the >>>> list of the names to be recognized as a valid parameter for mcpu >>>> and mtune flags. The TX2 cost model was reused for TX3. >>>> >>>> The previously used "cryptic" name for the command line >>>> parameter is replaced with the same "thunderxt311" name. >>>> >>>> Bootstrapped on AArch64. >>> >>>Thanks for the patch. I had meant to ask, do you have a copyright assignment >>>in place? >>>We'd need one to accept a contribution of this size. >>>Thanks, >>>Kyrill >>> >>>> >>>> 2020-04-20 Anton Youdkevitch >>>> >>>> * config/aarch64/aarch64-cores.def: Add the chip name. >>>> * config/aarch64/aarch64-tune.md: Regenerated. >>>> * gcc/config/aarch64/aarch64.c: Add the cost tables for the chip. >>>> * gcc/config/aarch64/thunderx3t11.md: New file: add the new >>>> machine model for the scheduler >>>> * gcc/config/aarch64/aarch64.md: Include the new model. >>>> >>>> --- >>>> gcc/config/aarch64/aarch64-cores.def | 3 + >>>> gcc/config/aarch64/aarch64-tune.md | 2 +- >>>> gcc/config/aarch64/aarch64.c | 27 + >>>> gcc/config/aarch64/aarch64.md| 1 + >>>> gcc/config/aarch64/thunderx3t11.md | 686 +++ >>>> 5 files changed, 718 insertions(+), 1 deletion(-) >>> >>> >>> >>> >
Re: [PATCH v2] aarch64: Add TX3 machine model
On Wed, Apr 22, 2020 at 5:38 AM Joel Jones via Gcc-patches wrote: > > I just joined the gcc-patches list, so I hope the mail software can parse > this out with an "In-Reply-To" header. > > I work for Marvell, and Anton's work is approved for submittal. I wrote the > first version of the .md file. I'm certain we have a copyright assignment.in > place, as we've had employees in the past six months submit changes, for > example Steve Ellcey. > I can certainly see Marvell hold a copyright assignment from 2010 in the copyright.list file. For being clear, is that stating that Anton's work is also covered by that copyright assignment ? Ramana > Joel Jones > > >Hi Anton, > > > >> -Original Message- > >> From: Gcc-patches On Behalf Of Anton > >> Youdkevitch > >> Sent: 20 April 2020 19:29 > >> To: gcc-patches@gcc.gnu.org > >> Cc: jo...@marvell.com > >> Subject: [PATCH v2] aarch64: Add TX3 machine model > >> > >> Here is the patch introducing thunderxt311 maching model > >> for the scheduler. A name for the new chip was added to the > >> list of the names to be recognized as a valid parameter for mcpu > >> and mtune flags. The TX2 cost model was reused for TX3. > >> > >> The previously used "cryptic" name for the command line > >> parameter is replaced with the same "thunderxt311" name. > >> > >> Bootstrapped on AArch64. > > > >Thanks for the patch. I had meant to ask, do you have a copyright assignment > >in place? > >We'd need one to accept a contribution of this size. > >Thanks, > >Kyrill > > > >> > >> 2020-04-20 Anton Youdkevitch > >> > >> * config/aarch64/aarch64-cores.def: Add the chip name. > >> * config/aarch64/aarch64-tune.md: Regenerated. > >> * gcc/config/aarch64/aarch64.c: Add the cost tables for the chip. > >> * gcc/config/aarch64/thunderx3t11.md: New file: add the new > >> machine model for the scheduler > >> * gcc/config/aarch64/aarch64.md: Include the new model. > >> > >> --- > >> gcc/config/aarch64/aarch64-cores.def | 3 + > >> gcc/config/aarch64/aarch64-tune.md | 2 +- > >> gcc/config/aarch64/aarch64.c | 27 + > >> gcc/config/aarch64/aarch64.md| 1 + > >> gcc/config/aarch64/thunderx3t11.md | 686 +++ > >> 5 files changed, 718 insertions(+), 1 deletion(-) >
[PATCH v2] aarch64: Add TX3 machine model
I just joined the gcc-patches list, so I hope the mail software can parse this out with an "In-Reply-To" header. I work for Marvell, and Anton's work is approved for submittal. I wrote the first version of the .md file. I'm certain we have a copyright assignment.in place, as we've had employees in the past six months submit changes, for example Steve Ellcey. Joel Jones >Hi Anton, > >> -Original Message- >> From: Gcc-patches On Behalf Of Anton >> Youdkevitch >> Sent: 20 April 2020 19:29 >> To: gcc-patches@gcc.gnu.org >> Cc: jo...@marvell.com >> Subject: [PATCH v2] aarch64: Add TX3 machine model >> >> Here is the patch introducing thunderxt311 maching model >> for the scheduler. A name for the new chip was added to the >> list of the names to be recognized as a valid parameter for mcpu >> and mtune flags. The TX2 cost model was reused for TX3. >> >> The previously used "cryptic" name for the command line >> parameter is replaced with the same "thunderxt311" name. >> >> Bootstrapped on AArch64. > >Thanks for the patch. I had meant to ask, do you have a copyright assignment >in place? >We'd need one to accept a contribution of this size. >Thanks, >Kyrill > >> >> 2020-04-20 Anton Youdkevitch >> >> * config/aarch64/aarch64-cores.def: Add the chip name. >> * config/aarch64/aarch64-tune.md: Regenerated. >> * gcc/config/aarch64/aarch64.c: Add the cost tables for the chip. >> * gcc/config/aarch64/thunderx3t11.md: New file: add the new >> machine model for the scheduler >> * gcc/config/aarch64/aarch64.md: Include the new model. >> >> --- >> gcc/config/aarch64/aarch64-cores.def | 3 + >> gcc/config/aarch64/aarch64-tune.md | 2 +- >> gcc/config/aarch64/aarch64.c | 27 + >> gcc/config/aarch64/aarch64.md| 1 + >> gcc/config/aarch64/thunderx3t11.md | 686 +++ >> 5 files changed, 718 insertions(+), 1 deletion(-)
RE: [PATCH v2] aarch64: Add TX3 machine model
Hi Anton, > -Original Message- > From: Gcc-patches On Behalf Of Anton > Youdkevitch > Sent: 20 April 2020 19:29 > To: gcc-patches@gcc.gnu.org > Cc: jo...@marvell.com > Subject: [PATCH v2] aarch64: Add TX3 machine model > > Here is the patch introducing thunderxt311 maching model > for the scheduler. A name for the new chip was added to the > list of the names to be recognized as a valid parameter for mcpu > and mtune flags. The TX2 cost model was reused for TX3. > > The previously used "cryptic" name for the command line > parameter is replaced with the same "thunderxt311" name. > > Bootstrapped on AArch64. Thanks for the patch. I had meant to ask, do you have a copyright assignment in place? We'd need one to accept a contribution of this size. Thanks, Kyrill > > 2020-04-20 Anton Youdkevitch > > * config/aarch64/aarch64-cores.def: Add the chip name. > * config/aarch64/aarch64-tune.md: Regenerated. > * gcc/config/aarch64/aarch64.c: Add the cost tables for the chip. > * gcc/config/aarch64/thunderx3t11.md: New file: add the new > machine model for the scheduler > * gcc/config/aarch64/aarch64.md: Include the new model. > > --- > gcc/config/aarch64/aarch64-cores.def | 3 + > gcc/config/aarch64/aarch64-tune.md | 2 +- > gcc/config/aarch64/aarch64.c | 27 + > gcc/config/aarch64/aarch64.md| 1 + > gcc/config/aarch64/thunderx3t11.md | 686 +++ > 5 files changed, 718 insertions(+), 1 deletion(-)
[PATCH v2] aarch64: Add TX3 machine model
Here is the patch introducing thunderxt311 maching model
for the scheduler. A name for the new chip was added to the
list of the names to be recognized as a valid parameter for mcpu
and mtune flags. The TX2 cost model was reused for TX3.
The previously used "cryptic" name for the command line
parameter is replaced with the same "thunderxt311" name.
Bootstrapped on AArch64.
2020-04-20 Anton Youdkevitch
* config/aarch64/aarch64-cores.def: Add the chip name.
* config/aarch64/aarch64-tune.md: Regenerated.
* gcc/config/aarch64/aarch64.c: Add the cost tables for the chip.
* gcc/config/aarch64/thunderx3t11.md: New file: add the new
machine model for the scheduler
* gcc/config/aarch64/aarch64.md: Include the new model.
---
gcc/config/aarch64/aarch64-cores.def | 3 +
gcc/config/aarch64/aarch64-tune.md | 2 +-
gcc/config/aarch64/aarch64.c | 27 +
gcc/config/aarch64/aarch64.md| 1 +
gcc/config/aarch64/thunderx3t11.md | 686 +++
5 files changed, 718 insertions(+), 1 deletion(-)
diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index ea9b98b..ece6c34 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -95,6 +95,9 @@ AARCH64_CORE("vulcan", vulcan, thunderx2t99, 8_1A, AARCH64_FL_FOR_ARCH8_1 | AA
/* Cavium ('C') cores. */
AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A, AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx2t99, 0x43, 0x0af, -1)
+/* Cavium ('??') cores (TX3). */
+AARCH64_CORE("thunderx3t11", thunderx3t11, thunderx3t11, 8_1A, AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx3t11, 0x43, 0x0b8, 0x0a)
+
/* ARMv8.2-A Architecture Processors. */
/* ARM ('A') cores. */
diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md
index 3cc1c4d..573a4a9 100644
--- a/gcc/config/aarch64/aarch64-tune.md
+++ b/gcc/config/aarch64/aarch64-tune.md
@@ -1,5 +1,5 @@
;; -*- buffer-read-only: t -*-
;; Generated automatically by gentune.sh from aarch64-cores.def
(define_attr "tune"
- "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa65,cortexa65ae,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,tsv110,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55"
+ "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,thunderx3t11,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa65,cortexa65ae,ares,neoversen1,neoversee1,octeontx2,octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95mm,tsv110,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55"
(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 24c055d..7abce6a 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1216,6 +1216,33 @@ static const struct tune_params thunderx2t99_tunings =
_prefetch_tune
};
+static const struct tune_params thunderx3t11_tunings =
+{
+ _extra_costs,
+ _addrcost_table,
+ _regmove_cost,
+ _vector_cost,
+ _branch_cost,
+ _approx_modes,
+ SVE_NOT_IMPLEMENTED, /* sve_width */
+ 4, /* memmov_cost. */
+ 4, /* issue_rate. */
+ (AARCH64_FUSE_ALU_BRANCH | AARCH64_FUSE_AES_AESMC
+ | AARCH64_FUSE_ALU_CBZ), /* fusible_ops */
+ "16", /* function_align. */
+ "8", /* jump_align. */
+ "16", /* loop_align. */
+ 3, /* int_reassoc_width. */
+ 2, /* fp_reassoc_width. */
+ 2, /* vec_reassoc_width. */
+ 2, /* min_div_recip_mul_sf. */
+ 2, /* min_div_recip_mul_df. */
+ 0, /* max_case_values. */
+ tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */
+ (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */
+ _prefetch_tune
+};
+
static const struct tune_params neoversen1_tunings =
{
_extra_costs,
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index c7c4d1d..d2123f8 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -438,6 +438,7 @@
(include "../arm/xgene1.md")
(include "thunderx2t99.md")
(include "tsv110.md")
+(include "thunderx3t11.md")
;; ---
;; Jumps and other miscellaneous insns
diff --git a/gcc/config/aarch64/thunderx3t11.md b/gcc/config/aarch64/thunderx3t11.md
new file mode 100644
index 000..8a4b824
---
Re: [PATCH v2] aarch64: Add TX3 machine model
Hi Kyrylo, On 20.4.2020 20:13 , Kyrylo Tkachov wrote: Hi Anton, -Original Message- From: Gcc-patches On Behalf Of Anton Youdkevitch Sent: 20 April 2020 18:05 To: gcc-patches@gcc.gnu.org Cc: jo...@marvell.com Subject: [PATCH v2] aarch64: Add TX3 machine model Here is the patch introducing thunderxt311 maching model for the scheduler. A name for the new chip was added to the list of the names to be recognized as a valid parameter for mcpu and mtune flags. The TX2 cost model was reused for TX3. The previously used "cryptic" name for the command line parameter is replaced with the same "thunderxt311" name. Bootstrapped on AArch64. Please post the full patch you want applied to trunk. I think the one you've sent is just a diff from the previous version you've posted. Oh, geez. You are right. Will resend in a minute. Thanks a lot!
RE: [PATCH v2] aarch64: Add TX3 machine model
Hi Anton, > -Original Message- > From: Gcc-patches On Behalf Of Anton > Youdkevitch > Sent: 20 April 2020 18:05 > To: gcc-patches@gcc.gnu.org > Cc: jo...@marvell.com > Subject: [PATCH v2] aarch64: Add TX3 machine model > > Here is the patch introducing thunderxt311 maching model > for the scheduler. A name for the new chip was added to the > list of the names to be recognized as a valid parameter for mcpu > and mtune flags. The TX2 cost model was reused for TX3. > > The previously used "cryptic" name for the command line > parameter is replaced with the same "thunderxt311" name. > > Bootstrapped on AArch64. Please post the full patch you want applied to trunk. I think the one you've sent is just a diff from the previous version you've posted. Thanks, Kyrill > > 2020-04-20 Anton Youdkevitch > > * config/aarch64/aarch64-cores.def: Add the chip name. > * config/aarch64/aarch64-tune.md: Regenerated. > * gcc/config/aarch64/aarch64.c: Add the cost tables for the chip. > * gcc/config/aarch64/thunderx3t11.md: New file: add the new > machine model for the scheduler > * gcc/config/aarch64/aarch64.md: Include the new model. > > --- > gcc/config/aarch64/aarch64-cores.def | 3 + > gcc/config/aarch64/aarch64-tune.md | 2 +- > gcc/config/aarch64/aarch64.c | 27 + > gcc/config/aarch64/aarch64.md| 1 + > gcc/config/aarch64/thunderx3t11.md | 686 +++ > 5 files changed, 718 insertions(+), 1 deletion(-)
[PATCH v2] aarch64: Add TX3 machine model
Here is the patch introducing thunderxt311 maching model
for the scheduler. A name for the new chip was added to the
list of the names to be recognized as a valid parameter for mcpu
and mtune flags. The TX2 cost model was reused for TX3.
The previously used "cryptic" name for the command line
parameter is replaced with the same "thunderxt311" name.
Bootstrapped on AArch64.
2020-04-20 Anton Youdkevitch
* config/aarch64/aarch64-cores.def: Add the chip name.
* config/aarch64/aarch64-tune.md: Regenerated.
* gcc/config/aarch64/aarch64.c: Add the cost tables for the chip.
* gcc/config/aarch64/thunderx3t11.md: New file: add the new
machine model for the scheduler
* gcc/config/aarch64/aarch64.md: Include the new model.
---
gcc/config/aarch64/aarch64-cores.def | 3 +
gcc/config/aarch64/aarch64-tune.md | 2 +-
gcc/config/aarch64/aarch64.c | 27 +
gcc/config/aarch64/aarch64.md| 1 +
gcc/config/aarch64/thunderx3t11.md | 686 +++
5 files changed, 718 insertions(+), 1 deletion(-)
diff --git a/gcc/config/aarch64/thunderx3t11.md b/gcc/config/aarch64/thunderx3t11.md
index 2c46f89..8a4b824 100644
--- a/gcc/config/aarch64/thunderx3t11.md
+++ b/gcc/config/aarch64/thunderx3t11.md
@@ -32,7 +32,7 @@
(define_cpu_unit "thunderx3t11_sd" "thunderx3t11_ldst")
; Pseudo-units for multiply pipeline.
-; XXX unchanged from TX2, occupies I1 for four (1 + 3 additional) slots
+; unchanged from TX2, occupies I1 for four (1 + 3 additional) slots
(define_cpu_unit "thunderx3t11_i1m1" "thunderx3t11_mult")
(define_cpu_unit "thunderx3t11_i1m2" "thunderx3t11_mult")
@@ -55,6 +55,8 @@
(define_cpu_unit "thunderx3t11_f3" "thunderx3t11_advsimd")
(define_reservation "thunderx3t11_i23" "thunderx3t11_i2|thunderx3t11_i3")
+(define_reservation "thunderx3t11_i01"
+"thunderx3t11_i0|thunderx3t11_i1")
(define_reservation "thunderx3t11_i012"
"thunderx3t11_i0|thunderx3t11_i1|thunderx3t11_i2")
(define_reservation "thunderx3t11_i0123"
@@ -62,13 +64,11 @@
(define_reservation "thunderx3t11_ls01" "thunderx3t11_ls0|thunderx3t11_ls1")
(define_reservation "thunderx3t11_f01" "thunderx3t11_f0|thunderx3t11_f1")
(define_reservation "thunderx3t11_f23" "thunderx3t11_f2|thunderx3t11_f3")
-;(define_reservation "thunderx3t11_f012"
-;"thunderx3t11_f2|thunderx3t11_f1|thunderx3t11_f0")
(define_reservation "thunderx3t11_f0123"
"thunderx3t11_f0|thunderx3t11_f1|thunderx3t11_f2|thunderx3t11_f3")
; A load with delay in the ls0/ls1 pipes.
-; XXX this is always a delay of four
+; this is always a delay of four
(define_reservation "thunderx3t11_l0delay"
"thunderx3t11_ls0,thunderx3t11_ls0d1,thunderx3t11_ls0d2,\
thunderx3t11_ls0d3")
@@ -79,7 +79,6 @@
"thunderx3t11_l0delay|thunderx3t11_l1delay")
;; Branch and call instructions.
-; trap?
(define_insn_reservation "thunderx3t11_branch" 1
(and (eq_attr "tune" "thunderx3t11")
(eq_attr "type" "call,branch,trap"))
@@ -93,26 +92,22 @@
(eq_attr "type" "block"))
"nothing")
-; XXX - mrs latency/throughput? Which units?
(define_insn_reservation "thunderx3t11_mrs" 0
(and (eq_attr "tune" "thunderx3t11")
(eq_attr "type" "mrs"))
"thunderx3t11_i2")
-; XXX - remove untyped, only appears in SVE .md file
-; multiple: 16 byte moves, other 16 byte ops?
(define_insn_reservation "thunderx3t11_multiple" 1
(and (eq_attr "tune" "thunderx3t11")
- (eq_attr "type" "multiple,untyped"))
+ (eq_attr "type" "multiple"))
"thunderx3t11_i0+thunderx3t11_i1+thunderx3t11_i3+thunderx3t11_ls0+\
thunderx3t11_ls1+thunderx3t11_sd+thunderx3t11_i1m1+thunderx3t11_i1m2+\
thunderx3t11_i1m3+thunderx3t11_f0+thunderx3t11_f1")
;; Integer arithmetic/logic instructions.
-; Plain register moves are handled by renaming, and don't create any uops.
-
-; XXX - distinguish asimd UMOV from GPR mov;
+; Plain register moves are handled by renaming,
+; and don't create any uops.
(define_insn_reservation "thunderx3t11_regmove" 0
(and (eq_attr "tune" "thunderx3t11")
(eq_attr "type" "mov_reg"))
@@ -127,15 +122,24 @@
bfx,rbit,rev,extend,rotate_imm"))
"thunderx3t11_i0123")
-; XXX distinguish between latency 1|2 and throughput 1/4|2/4?
-(define_insn_reservation "thunderx3t11_alu_shift" 1
+; distinguish between latency 1|2 and throughput 1/4|2/4?
+; is it actually 1,1/2,{i0,i1} vs 2,1/4,{i0,i1,i2,i3}
+(define_insn_reservation "thunderx3t11_alu_shift" 2
+ (and (eq_attr "tune" "thunderx3t11")
+ (eq_attr "type" "alu_shift_imm,alu_ext,\
+ alus_shift_imm,alus_ext,\
+ logic_shift_imm,logics_shift_imm"))
+ "thunderx3t11_i0123")
+
+(define_insn_reservation "thunderx3t11_alu_shift1" 1
(and (eq_attr "tune" "thunderx3t11")
(eq_attr "type" "alu_shift_imm,alu_ext,\
alus_shift_imm,alus_ext,\
logic_shift_imm,logics_shift_imm"))
- "thunderx3t11_i0123,thunderx3t11_i0123")
+ "thunderx3t11_i01")
-; XXX - is the optimistic answer (13) preferable than the
