[gem5-users] RISC-V ISA

[Alec Roelke]

Hello,

I'm implementing the RISC-V ISA for GEM5, and I have a few questions:

- How complete should it be before I try to submit it?  What features
should be supported?
- Is there some kind of submission process?  I know about the gem5-dev list
and patch review board, but how do I submit there?

Thanks,
Alec Roelke
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Re: [gem5-users] SPARC_SE -> Unimplemented Instruction

[Jason Lowe-Power]

Hi Monir,

No, I don't have any good suggestions for you. Too bad you're not inside
ARM. I bet they have something internally ;) (note: I have no knowledge of
what ARM may or may not be doing internally).

Another (semi-)sarcastic response: It may be less effort to add the RISC-V
ISA to gem5 than to get SPARC working. That is definitely something the
gem5 community would get excited about! Plus, it seems that the RTL models
for RISC-V cores are only going to get better, especially compared to SPARC
cores.

Sorry I can't be more help.

Jason

On Wed, Sep 7, 2016 at 9:47 AM Zaman, Monir 
wrote:

> Thanks Jason. You are right, too many times the struggle is with the ISA
> of choice in my case.
>
>
>
> But, I need something which I can model in GEM5 and also have
> synthesizable RTL available to play with. Any idea?
>
>
>
> /Monir
>
>
>
>
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Re: [gem5-users] SPARC_SE -> Unimplemented Instruction

[Zaman, Monir]

Thanks Jason. You are right, too many times the struggle is with the ISA of 
choice in my case.

But, I need something which I can model in GEM5 and also have synthesizable RTL 
available to play with. Any idea?

/Monir


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Re: [gem5-users] Minor Cpu x86

[Jason Lowe-Power]

Hi Ayaz,

This sounds like a bug to me. You should post your fix on reviewboard (
http://reviews.gem5.org/) so we can incorporate it into the mainline gem5.

Thanks!
Jason

On Tue, Sep 6, 2016 at 2:00 PM Ayaz Akram  wrote:

> I'll appreciate if someone who has used x86 minor cpu can look into output
> stats files of their experimental results and share if they observe the
> similar problem as mentioned in the following post:
>
> https://www.mail-archive.com/gem5-users@gem5.org/msg13196.html
>
> Actually based on this observation I added some code hacks in fetch2 stage
> of minor cpu to properly label x86 control instructions and it seems that
> the fetch stage calls branch predictor now. I want to know what others have
> experienced ?
>
> Thanks for your time.
>
> -Ayaz
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Re: [gem5-users] SPARC_SE -> Unimplemented Instruction

[Jason Lowe-Power]

Hi Monir,

I won't belabor the point about using a better supported ISA this time :).
For your other options, I definitely wouldn't change the instruction to a
warning. That may be appropriate for a few instructions, like prefetch, but
it's inappropriate for most. I don't know the SPARC ISA off the top of my
head, but I bet "for" is a floating point instruction, which can't be
skipped if you want the program to execute correctly.

Second, I don't think you can just "call that syscall from another ISA".
Instructions are not implemented with syscalls. They have to execute in the
core pipeline.

If you really need SPARC support, the best option is to implement the
unimplemented functions. Unfortunately, this isn't something I am
personally familiar with. Hopefully someone else can speak up to help out
here.

Cheers,
Jason

On Tue, Sep 6, 2016 at 11:04 PM Zaman, Monir 
wrote:

> Hello All,
>
> I was running the “456.hmmer” from the SPEC benchmark Suite, which was
> compiled by the “linux-gcc-sparc” compiler available from the Gem5 website.
> I did successfully run the “bzip” and “mcf” benchmarks, but while running
> “hmmer” I ran into error below (I used the script described in Mark
> Grottscho’s blog to easily run SPEC in GEM5):
>
>
>
> Selected SPEC_CPU2006 benchmark
>
> -->hmmer
>
> Process stdout file: /home/gem5/gem5-stable/Performance
> /SPARC_default/hmmer/hmmer.out
>
> Process stderr file: /home/gem5/gem5-stable/Performance
> /SPARC_default/hmmer/hmmer.err
>
> ['hmmer_base.gcc43-64bit', '--fixed', '0', '--mean', '325', '--num',
> '45000', '--sd', '200', '--seed', '0', 'bombesin.hmm']
>
> Global frequency set at 1 ticks per second
>
> 8192 Mbytes) does not match the address range assigned (512 Mbytes)
>
> 0: system.remote_gdb.listener: listening for remote gdb on port 7000
>
>  REAL SIMULATION 
>
> info: Entering event queue @ 0.  Starting simulation...
>
> panic: attempt to execute unimplemented instruction 'for' (inst
> 0x7c99b30f88)
>
> @ tick 979633823
>
> [execute:build/SPARC/arch/sparc/generated/exec-ns.cc.inc, line 31]
>
> Memory Usage: 800844 KBytes
>
> Program aborted at cycle 979633823
>
>
>
> real0m5.048s
>
> user0m3.420s
>
> sys 0m0.051s
>
>
>
>
>
> I have found some similar posts with different ISA’s, but haven’t found a
> concrete solution. Based on the discussion in previous posts with similar
> issue, following are the possible solutions:
>
> · Change the ISA to more robustly supported ISA by GEM5 community
>
> · Add the “for” instruction as a Warning instead of Error for
> Unimplemented Instruction
>
> · Find this instruction which is implemented in another ISA in
> GEM5 and call that Syscall from the ISA in use (SPARC in this case)
>
> · Actually implement the instruction in the ISA.
>
>
>
> Have anyone added instructions to ISA and have some guidance as to what
> and where to look at? The other option for calling the Syscall implemented
> in another ISA, does that maintain the correct functionality if implemented?
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Re: [gem5-users] Stuck at "initiateAcc not defined!"

[Oscar Rosell]

As Jason suggested I tried with the latest version of the script 
(./configs/learning_gem5/part1/simple.py) and it worked OK.



gem5 compiled Sep  7 2016 10:51:54

gem5 started Sep  7 2016 11:16:01

gem5 executing on orosell-Inspiron-3847, pid 27899

command line: ./build/X86/gem5.opt ./configs/learning_gem5/part1/simple.py



Global frequency set at 1 ticks per second

warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (512 Mbytes)

0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000

warn: ClockedObject: More than one power state change request encountered 
within the same simulation tick

Beginning simulation!

info: Entering event queue @ 0.  Starting simulation...

Hello world!

Exiting @ tick 454507000 because target called exit()



Oscar Rosell - Metempsy





 On Wed, 07 Sep 2016 09:38:57 +0100 Oscar Rosell 
oscar.ros...@metempsy.comwrote  




Hi,



Did you try Jason's solution? Did it work?



Thanks,



Oscar Rosell - Metempsy





 On Wed, 07 Sep 2016 09:23:02 +0100 Uma S umasuji...@gmail.comwrote 
 










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Dear all,

I had posted a question on 2016/08/30 with the subject, 

Stuck at "initiateAcc not defined!"

I am thankful that two persons replied to that. As per 

Oscar Rosell 's reply I am attaching the "simple.py" file for further
look. Kindly let me know how I can solve this.
_S.Uma

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Re: [gem5-users] Stuck at "initiateAcc not defined!"

[Oscar Rosell]

Hi,



Did you try Jason's solution? Did it work?



Thanks,



Oscar Rosell - Metempsy





 On Wed, 07 Sep 2016 09:23:02 +0100 Uma S umasuji...@gmail.comwrote 
 




Dear all,

I had posted a question on 2016/08/30 with the subject, 

Stuck at "initiateAcc not defined!"


I am thankful that two persons replied to that. As per 

Oscar Rosell 's reply I am attaching the "simple.py" file for further
look. Kindly let me know how I can solve this.
_S.Uma

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[gem5-users] Stuck at "initiateAcc not defined!"

[Uma S]

Dear all,
I had posted a question on 2016/08/30 with the subject,

Stuck at "initiateAcc not defined!"

I am thankful that two persons replied to that. As per

Oscar Rosell 's reply I am attaching the "simple.py" file for further

look. Kindly let me know how I can solve this.

_S.Uma
# -*- coding: utf-8 -*-
# Copyright (c) 2015 Jason Power
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Jason Power

""" This file creates a barebones system and executes 'hello', a simple Hello
World application.

This config file assumes that the x86 ISA was built.
See gem5/configs/learning_gem5/part1/simple.py for a general script.

"""

# import the m5 (gem5) library created when gem5 is built
import m5
# import all of the SimObjects
from m5.objects import *

# create the system we are going to simulate
system = System()

# Set the clock fequency of the system (and all of its children)
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()

# Set up the system
system.mem_mode = 'timing'   # Use timing accesses
system.mem_ranges = [AddrRange('512MB')] # Create an address range

# Create a simple CPU
system.cpu = TimingSimpleCPU()

# Create a memory bus, a coherent crossbar, in this case
system.membus = SystemXBar()

# Hook the CPU ports up to the membus
system.cpu.icache_port = system.membus.slave
system.cpu.dcache_port = system.membus.slave

# create the interrupt controller for the CPU and connect to the membus
system.cpu.createInterruptController()
system.cpu.interrupts.pio = system.membus.master
system.cpu.interrupts.int_master = system.membus.slave
system.cpu.interrupts.int_slave = system.membus.master

# Create a DDR3 memory controller and connect it to the membus
system.mem_ctrl = DDR3_1600_x64()
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master

# Connect the system up to the membus
system.system_port = system.membus.slave

# Create a process for a simple "Hello World" application
process = LiveProcess()
# Set the command
# cmd is a list which begins with the executable (like argv)
process.cmd = ['tests/test-progs/hello/bin/x86/linux/hello']
# Set the cpu to use the process as its workload and create thread contexts
system.cpu.workload = process
system.cpu.createThreads()

# set up the root SimObject and start the simulation
root = Root(full_system = False, system = system)
# instantiate all of the objects we've created above
m5.instantiate()

print "Beginning simulation!"
exit_event = m5.simulate()
print 'Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())
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