Re: [gem5-users] RISC-V ISA

[Jason Lowe-Power]

Hi Alex,

This is very exciting. I think I was just telling somebody a day or two ago
that RISC-V would be great to have in gem5!

For the submission process see http://gem5.org/Submitting_Contributions.
Also, you should be sure to follow the coding style:
http://gem5.org/Coding_Style.

In the same vein as what Andreas was saying, a good way to do this is to
post patches for some minimum working version on reviewboard. Once you get
those approved/submitted, then move onto more complicated things (e.g.,
privileged instructions, floating point, etc.). It helps that RISC-V is
defined with a minimum set of instructions and then further optional
extensions.

Looking forward to your patches!

Cheers,
Jason


On Thu, Sep 8, 2016 at 8:20 AM Andreas Hansson 
wrote:

> Hi Alec,
>
> I think a good starting point would be to aim for enough functionality to
> have a few regressions working, using some simple test programs, and the
> atomic and timing CPU model. From there you can extend it to eventually
> include basic linux regressions and in-order/out-of-order regressions,
> multi-processor, etc.
>
> Andreas
>
> From: gem5-users  on behalf of Alec Roelke <
> ar...@virginia.edu>
> Reply-To: gem5 users mailing list 
> Date: Thursday, 8 September 2016 at 03:56
>
> To: gem5 users mailing list 
> Subject: [gem5-users] RISC-V ISA
>
> Hello,
>
> I'm implementing the RISC-V ISA for GEM5, and I have a few questions:
>
> - How complete should it be before I try to submit it?  What features
> should be supported?
> - Is there some kind of submission process?  I know about the gem5-dev
> list and patch review board, but how do I submit there?
>
> Thanks,
> Alec Roelke
> IMPORTANT NOTICE: The contents of this email and any attachments are
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Re: [gem5-users] Stuck at "initiateAcc not defined!"

[Oscar Rosell]

The problem is not that scons is not installed. The problem is that it cannot 
find the SConstruct file. You have to be at the root of the repo to build the 
model. Just go there and do "scons build/X86/gem5.opt -j3"



Thanks,



Oscar Rosell - Metempsy





 On Fri, 09 Sep 2016 13:20:29 +0100 Uma S umasuji...@gmail.comwrote 
 




Hello all,


As per Mr.Jason Lowe-Power's suggesion,

I am trying to run the configs/learning_gem5/simple.py from current gem5.

so I have cloned and  gem5(current) in another directory.


but the following command returns error inside gem5(current) directory. I t was 
working alright in the gem5-stable directory.



scons CPU_MODELS="AtomicSimpleCPU,MinorCPU,O3CPU,TimingSimpleCPU" 
build/X86/gem5.opt -j3




output is 



suma@suma-G31T-M:~/g52$ scons 
CPU_MODELS="AtomicSimpleCPU,MinorCPU,O3CPU,TimingSimpleCPU" build/X86/gem5.opt 
-j3



scons: *** No SConstruct file found.

File "/usr/lib/scons/SCons/Script/Main.py", line 905, in _main




so I gave 

suma@suma-G31T-M:~/g52$ whereis scons



answer is



scons: /usr/bin/scons /usr/lib/scons /usr/bin/X11/scons 
/usr/share/man/man1/scons.1.gz



I dont know why I am not able to build the gem5 current. Please help me


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[gem5-users] Stuck at "initiateAcc not defined!"

[Uma S]

Hello all,

As per Mr.Jason Lowe-Power's suggesion,
I am trying to run the configs/learning_gem5/simple.py from current gem5.
so I have cloned and  gem5(current) in another directory.
but the following command returns error inside gem5(current) directory. I t
was working alright in the gem5-stable directory.

scons CPU_MODELS="AtomicSimpleCPU,MinorCPU,O3CPU,TimingSimpleCPU"
build/X86/gem5.opt -j3

output is

suma@suma-G31T-M:~/g52$ scons
CPU_MODELS="AtomicSimpleCPU,MinorCPU,O3CPU,TimingSimpleCPU"
build/X86/gem5.opt -j3

scons: *** No SConstruct file found.
File "/usr/lib/scons/SCons/Script/Main.py", line 905, in _main

so I gave
suma@suma-G31T-M:~/g52$ whereis scons

answer is

scons: /usr/bin/scons /usr/lib/scons /usr/bin/X11/scons
/usr/share/man/man1/scons.1.gz

I dont know why I am not able to build the gem5 current. Please help me
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Re: [gem5-users] Stuck at "initiateAcc not defined!"

[Oscar Rosell]

Hi,



The file is in latest gem5 repository:



http://repo.gem5.org/gem5/file/8bc53d5565ba/configs/learning_gem5/part1/simple.py



There's a gem5 repository and an stable repository.



http://www.gem5.org/Repository



The file we're talking about is in gem5 repo. Not sure what's your current-gem5 
repo.



Thanks,



Oscar Rosell - Metempsy





 On Fri, 09 Sep 2016 12:41:27 +0100 Uma S umasuji...@gmail.comwrote 
 




Hi,

 I had posted a question on 2016/08/30 with the subject, Stuck at "initiateAcc 
not defined!"

As per Mr.Jason Lowe-Power's advice, I now tried with current-gem5 instead of 
stable version.
But I could not find (./configs/learning_gem5/part1/simple.py) link in the 
internet?
What am I missing here?
Actually, I had downloaded the "simple.[y" file from 

http://pages.cs.wisc.edu/~david/courses/cs752/Fall2015/gem5-tutorial/_downloads/simple.py

link provided in the tutorial.

I did hg clone to latest gem5 version and did update and merge steps. I used 
the 
above said simple.py file as found in the attachment . But still getting that 
error.

Kindly help.
The screen said,.

suma@suma-G31T-M:~/g51/gem5-stable$ build/X86/gem5.opt -d /home/suma/g51out/2 
configs/tutorial/simple.py

gem5 Simulator System. http://gem5.org

gem5 is copyrighted software; use the --copyright option for details.



gem5 compiled Aug 30 2016 18:29:26

gem5 started Sep 9 2016 16:48:27

gem5 executing on suma-G31T-M

command line: build/X86/gem5.opt -d /home/suma/g51out/2 
configs/tutorial/simple.py



Global frequency set at 1 ticks per second

warn: DRAM device capacity (8192 Mbytes) does not match the address range 
assigned (512 Mbytes)

0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000

Beginning simulation!

info: Entering event queue @ 0. Starting simulation...

panic: initiateAcc not defined!

 @ tick 74000

[initiateAcc:build/X86/cpu/static_inst.hh, line 272]

Memory Usage: 586312 KBytes

Program aborted at cycle 74000

Aborted (core dumped)


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[gem5-users] Stuck at "initiateAcc not defined!"

[Uma S]

Hi,
 I had posted a question on 2016/08/30 with the subject,

Stuck at "initiateAcc not defined!"

As per Mr.Jason Lowe-Power's advice, I now tried with current-gem5
instead of stable version.

But I could not find (./configs/learning_gem5/part1/simple.py) link in
the internet?

What am I missing here?

Actually, I had downloaded the "simple.[y" file from
http://pages.cs.wisc.edu/~david/courses/cs752/Fall2015/gem5-tutorial/_downloads/simple.py

link provided in the tutorial.

I did hg clone to latest gem5 version and did update and merge steps.
I used the

above said simple.py file as found in the attachment . But still
getting that error.

Kindly help.

The screen said,.
suma@suma-G31T-M:~/g51/gem5-stable$ build/X86/gem5.opt -d
/home/suma/g51out/2 configs/tutorial/simple.py
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Aug 30 2016 18:29:26
gem5 started Sep  9 2016 16:48:27
gem5 executing on suma-G31T-M
command line: build/X86/gem5.opt -d /home/suma/g51out/2
configs/tutorial/simple.py

Global frequency set at 1 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address
range assigned (512 Mbytes)
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
Beginning simulation!
info: Entering event queue @ 0.  Starting simulation...
panic: initiateAcc not defined!
 @ tick 74000
[initiateAcc:build/X86/cpu/static_inst.hh, line 272]
Memory Usage: 586312 KBytes
Program aborted at cycle 74000
Aborted (core dumped)
# -*- coding: utf-8 -*-
# Copyright (c) 2015 Jason Power
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Jason Power

""" This file creates a barebones system and executes 'hello', a simple Hello
World application.

This config file assumes that the x86 ISA was built.
See gem5/configs/learning_gem5/part1/simple.py for a general script.

"""

# import the m5 (gem5) library created when gem5 is built
import m5
# import all of the SimObjects
from m5.objects import *

# create the system we are going to simulate
system = System()

# Set the clock fequency of the system (and all of its children)
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()

# Set up the system
system.mem_mode = 'timing'   # Use timing accesses
system.mem_ranges = [AddrRange('512MB')] # Create an address range

# Create a simple CPU
system.cpu = TimingSimpleCPU()

# Create a memory bus, a coherent crossbar, in this case
system.membus = SystemXBar()

# Hook the CPU ports up to the membus
system.cpu.icache_port = system.membus.slave
system.cpu.dcache_port = system.membus.slave

# create the interrupt controller for the CPU and connect to the membus
system.cpu.createInterruptController()
system.cpu.interrupts.pio = system.membus.master
system.cpu.interrupts.int_master = system.membus.slave
system.cpu.interrupts.int_slave = system.membus.master

# Create a DDR3 memory controller and connect it to the membus
system.mem_ctrl = DDR3_1600_x64()
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master

# Connect the system up to the membus
system.system_port = system.membus.slave

# Create a process for a simple "Hello World" application
process = LiveProcess()
# Set the command
# cmd is a list which begins with the executable (like argv)
process.cmd = ['tests/test-progs/hello/bin/x86/linux/hello']
# Set the cpu to use the process as its workload and create thread contexts

[gem5-users] Implementing UMON

[Yash Karundia]

Hi All,
   I am trying to implement utility monitoring using auxiliary tag
directory as suggested in Utility based cache partitioning by
Qureshi[2006]. However, I am unable to understand as to how I should
proceed with the same.Can someone help me ?

Regards,
Yash
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