Re: [gem5-users] undefined reference to `vtable for Port

[Oscar Rosell]

Hi,

This looks just like a C++ error. Check solution for: 
https://stackoverflow.com/questions/3065154/undefined-reference-to-vtable 


Regards,

   Oscar

> On 15 Jul 2017, at 17:47, Neu, Markus  wrote:
> 
> Hallo,
> 
> at the moment i try to add a additional port to the cache.cc/.hh 
> . The idea is to send a copy of the packets to a new 
> module.
> I use a example from: learning.gem5.org/book/part2/memoryobject.html 
>  as template for the 
> port implementation. Now i have reached a point were the syntax generates no 
> more problems. But the compiler stops with errors:
> 
> 
> build/X86/mem/cache/lib.o.partial: In function 
> `Cache::DapuSidePort::DapuSidePort(std::__cxx11::basic_string std::char_traits, std::allocator > const&, Cache*)':
> /home/osboxes/gem5_raw/build/X86/mem/cache/cache.hh:204: undefined reference 
> to `vtable for Cache::DapuSidePort'
> build/X86/mem/cache/lib.o.partial: In function 
> `Cache::DapuSidePort::~DapuSidePort()':
> /home/osboxes/gem5_raw/build/X86/mem/cache/cache.hh:190: undefined reference 
> to `vtable for Cache::DapuSidePort'
> /home/osboxes/gem5_raw/build/X86/mem/cache/cache.hh:190: undefined reference 
> to `vtable for Cache::DapuSidePort'
> build/X86/exposed_obj/lib.o.partial: In function 
> `Dapu::CPUSidePort::CPUSidePort(std::__cxx11::basic_string std::char_traits, std::allocator > const&, Dapu*)':
> /home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:43: undefined reference 
> to `vtable for Dapu::CPUSidePort'
> /home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:43: undefined reference 
> to `vtable for Dapu::CPUSidePort'
> build/X86/exposed_obj/lib.o.partial: In function 
> `Dapu::CPUSidePort::~CPUSidePort()':
> /home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:25: undefined reference 
> to `vtable for Dapu::CPUSidePort'
> /home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:25: undefined reference 
> to `vtable for Dapu::CPUSidePort'
> /home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:25: undefined reference 
> to `vtable for Dapu::CPUSidePort'
> build/X86/exposed_obj/lib.o.partial:/home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:25:
>  more undefined references to `vtable for Dapu::CPUSidePort' follow
> collect2: error: ld returned 1 exit status
> scons: *** [build/X86/gem5.opt] Error 1
> 
> 
> The gem5 version which i use is from today but the template seems to be much 
> older. The error massages point to the constructor and class definitions:
> 
> 
> Dapu.hh:25 --> class CPUSidePort : public SlavePort
> 
> Dapu.hh:43 -->CPUSidePort(const std::string& name, Dapu *owner) :
> SlavePort(name, owner), owner(owner), 
> needRetry(false),
> blockedPacket(nullptr)
> { }
> 
> 
> Unfortunately i don't understand what the compiler indicates but would assume 
> a missing library. I would appreciate some hints.
> 
> Regards,
> Markus Neu
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[gem5-users] undefined reference to `vtable for Port

[Neu, Markus]

Hallo,


at the moment i try to add a additional port to the cache.cc/.hh. The idea is 
to send a copy of the packets to a new module.

I use a example from: 
learning.gem5.org/book/part2/memoryobject.html
 as template for the port implementation. Now i have reached a point were the 
syntax generates no more problems. But the compiler stops with errors:



build/X86/mem/cache/lib.o.partial: In function 
`Cache::DapuSidePort::DapuSidePort(std::__cxx11::basic_string const&, Cache*)':
/home/osboxes/gem5_raw/build/X86/mem/cache/cache.hh:204: undefined reference to 
`vtable for Cache::DapuSidePort'
build/X86/mem/cache/lib.o.partial: In function 
`Cache::DapuSidePort::~DapuSidePort()':
/home/osboxes/gem5_raw/build/X86/mem/cache/cache.hh:190: undefined reference to 
`vtable for Cache::DapuSidePort'
/home/osboxes/gem5_raw/build/X86/mem/cache/cache.hh:190: undefined reference to 
`vtable for Cache::DapuSidePort'
build/X86/exposed_obj/lib.o.partial: In function 
`Dapu::CPUSidePort::CPUSidePort(std::__cxx11::basic_string const&, Dapu*)':
/home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:43: undefined reference to 
`vtable for Dapu::CPUSidePort'
/home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:43: undefined reference to 
`vtable for Dapu::CPUSidePort'
build/X86/exposed_obj/lib.o.partial: In function 
`Dapu::CPUSidePort::~CPUSidePort()':
/home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:25: undefined reference to 
`vtable for Dapu::CPUSidePort'
/home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:25: undefined reference to 
`vtable for Dapu::CPUSidePort'
/home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:25: undefined reference to 
`vtable for Dapu::CPUSidePort'
build/X86/exposed_obj/lib.o.partial:/home/osboxes/gem5_raw/build/X86/exposed_obj/Dapu.hh:25:
 more undefined references to `vtable for Dapu::CPUSidePort' follow
collect2: error: ld returned 1 exit status
scons: *** [build/X86/gem5.opt] Error 1



The gem5 version which i use is from today but the template seems to be much 
older. The error massages point to the constructor and class definitions:



Dapu.hh:25 --> class CPUSidePort : public SlavePort


Dapu.hh:43 -->CPUSidePort(const std::string& name, Dapu *owner) :
SlavePort(name, owner), owner(owner), 
needRetry(false),
blockedPacket(nullptr)
{ }



Unfortunately i don't understand what the compiler indicates but would assume a 
missing library. I would appreciate some hints.


Regards,

Markus Neu
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[gem5-users] Floating Point exception when changing the address mapping scheme

[Sneha Ved]

Hi,

When I change the address mapping scheme for gem5+ARM from RoRaBaChCo
to RoRaBaCoCh, the simulation aborts with a floating point exception. Why
should this be the case when the simulation runs to completion
in RoRaBaChCo?

Thank you.

Best Regards,
Sneha N Ved
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Re: [gem5-users] Non exclusive cache in gem5

[Muhammad Avais]

Hi
 Thanks for your response,
 In 'gem5', i have declared cache 'mostly
exclusive'  as recommended by you. I have also set "writeback_clean"
parameter to true of cache which is closer to CPU.
 Now, i want that this 'mostly exclusive cache,
should act as 'Non exclusive' cache.
 Non exclusive cache is cache which does not fill
on a miss from cache closer to CPU. Also, when some block is accessed from
Non exclusive cache, it does not invalidate the block.
 I think in gem5, accessed block from Non exclusive
cache is invalidated in 'maintainClusivity()' function.
 I think that by removing the 'maintainClusivity()'
function, i can make the 'mostly exclusive' cache as 'non exclusive' cache.
 Is my thinking correct?
 Also, maintainClusivity() function is used at two
places in cache.cc file. In 'access()' function and 'recvTimingResp()'
function.
I do not understand both functions completely. Can
anyone suggest, do i need to remove 'maintainClusivity()' function from
both places or not?

Many Thanks
Avais


On Fri, Jul 14, 2017 at 11:37 PM, Jason Lowe-Power 
wrote:

> Hello,
>
> The classic cache in gem5 (src/mem/cache and Cache()) is always
> non-inclusive (i.e., it is neither inclusive nor exclusive). You can set
> whether it is "mostly-inclusive" or "mostly-exclusive" as a parameter to
> the Cache SimObject. If the cache is "mostly-exclusive" it will not fill on
> a miss from a cache closer to the CPU (and the opposite for a
> mostly-inclusive). Thus, if you want a mostly-exclusive cache, the caches
> closer to the CPU should set the "writeback_clean" parameter to true (and
> to false if the further cache is mostly-inclusive).
>
> Jason
>
> On Fri, Jul 14, 2017 at 3:16 AM Muhammad Avais 
> wrote:
>
>> Dear all,
>>
>>  Gem5 supports 'Mostly exclusive' cache. How can i
>> modify code to make it non exclusive cache.
>>
>> I think i can do it by removing maintainClusivity() function from
>> cache.cc file
>>
>> Can someone comment, how to do it
>>
>>
>>
>> Many Thanks
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>
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