Re: [gem5-users] Re：sim_seconds is a huge different between x86-se mode and x86- fs mode ,under the same program condition

2017-09-05 Thread 李莉 
Hi Oscar,

Thank you very much for your reply, it helps me a lot!

Regards,
  lily


在2017-09-05 15:55:06,李莉写道：
> Hi,
> 
>  > Then, I change my rcS file followed you said ， I get a new stats,txt 
> ,the sim_seconds  is the actual simulation time for this program ,Am I 
> right?
> 
> After you first changed your rcS file, the sim_seconds show the time 
> from m5 resetstats until m5 exit. So yeah, should pretty approximately 
> correspond with the time for arraywritenew.
> 
>  > Next I changed rcS file again,it has two Simulation Statistics ,Is 
> sim_seconds(  0.004455   ) the actual simulation time for this 
> program? why different the sim_seconds   ( 0.004447 )
> 
> That's the simulation time for the program, right. Why is it different? 
> Note first that the difference is pretty small. The difference is 
> probably just due to the differences in the rcS file. Note that the 
> calls to m5 are actual instructions that the simulator will execute so 
> that will make some difference here and there. I wouldn't worry much 
> about it. Just as a sanity check you can make arraywritenew to perform 
> more/less work and see if the difference in sim_seconds between the two 
> rcS is constant (which I'd expect) or linear.
> 
> Regards,
> 
>  Oscar
> 
> On 02/09/17 08:25, 李莉 wrote:
> >
> > Hi Oscar.
> >
> > Thanks your rapid reply
> >
> > First of all ,you are right ,the fs mode commend line edit 
> > error, because of my careless
> >
> > Second , as you except ,the number of instructions executed is different.
> >
> > Then, I change my rcS file followed you said ， I get a new stats,txt 
> > ,the sim_seconds  is the actual simulation time for this program ,Am I 
> > right?
> >
> > this  is my rcs file
> >
> > #!/bin/sh
> > m5 resetstats
> > /arraywritenew
> > m5 exit
> >
> > common line：build/X86/gem5.opt configs/example/fs.py 
> > --cpu-type=TimingSimpleCPU --caches --script=configs/boot/arraywrite.rcS
> >
> > this is a part of my stats.txt
> >
> > sim_seconds 0.004447   # Number of seconds simulated
> > sim_ticks 4447491000   # Number of ticks simulated
> > final_tick 5311293823000   # Number of ticks from 
> > beginning of simulation (restored from checkpoints and never reset)
> > sim_freq 1   # Frequency of simulated 
> > ticks
> >
> > system.cpu.dtb.rdAccesses 305360   # TLB accesses 
> > on read requests
> > system.cpu.dtb.wrAccesses 227953   # TLB accesses 
> > on write requests
> > system.cpu.dtb.rdMisses 556   # TLB misses on read 
> > requests
> > system.cpu.dtb.wrMisses 175   # TLB misses on 
> > write requests
> >
> > - End Simulation Statistics   --
> >
> > Next I changed rcS file again,it has two Simulation Statistics ,Is 
> > sim_seconds(  0.004455   ) the actual simulation time for this 
> > program? why different the sim_seconds   ( 0.004447 )
> >
> > this  is   my rcs file
> >
> > m5 resetstats
> > /arraywritenew
> > m5 dumpstats
> > m5 exit
> >
> > common line：build/X86/gem5.opt configs/example/fs.py 
> > --cpu-type=TimingSimpleCPU --caches --script=configs/boot/arraywrite.rcS
> >
> > this is a part of  my stats.txt
> >
> > -- Begin Simulation Statistics --
> > sim_seconds 0.004455   # Number of seconds simulated
> > sim_ticks 445488   # Number of ticks simulated
> > final_tick 531130128   # Number of ticks from 
> > beginning of simulation (restored from checkpoints and never reset)
> > sim_freq 1   # Frequency of simulated 
> > ticks
> >
> > system.cpu.dtb.rdAccesses 306413   # TLB accesses 
> > on read requests
> > system.cpu.dtb.wrAccesses 228544   # TLB accesses 
> > on write requests
> > system.cpu.dtb.rdMisses 556   # TLB misses on read 
> > requests
> > system.cpu.dtb.wrMisses 175   # TLB misses on 
> > write requests
> >
> > - End Simulation Statistics   --
> >
> > -- Begin Simulation Statistics --
> > sim_seconds 0.006399   # Number of seconds simulated
> > sim_ticks 6399292000   # Number of ticks simulated
> > final_tick 5313245692000   # Number of ticks from 
> > beginning of simulation (restored from checkpoints and never reset)
> > sim_freq 1   # Frequency of simulated 
> > tickssystem.cpu.dtb.rdAccesses 430950   # TLB 
> > accesses on read requests
> > system.cpu.dtb.wrAccesses 323985   # TLB accesses 
> > on write requests
> > system.cpu.dtb.rdMisses 825   # TLB misses on read 
> > requests
> > system.cpu.dtb.wrMisses 249   # TLB misses on 
> > write requests
>

Re: [gem5-users] Re：sim_seconds is a huge different between x86-se mode and x86- fs mode ,under the same program condition

2017-09-05 Thread Oscar Rosell 

Hi,

> Then, I change my rcS file followed you said ， I get a new stats,txt 
,the sim_seconds  is the actual simulation time for this program ,Am I 
right?


After you first changed your rcS file, the sim_seconds show the time 
from m5 resetstats until m5 exit. So yeah, should pretty approximately 
correspond with the time for arraywritenew.


> Next I changed rcS file again,it has two Simulation Statistics ,Is 
sim_seconds(  0.004455   ) the actual simulation time for this 
program? why different the sim_seconds   ( 0.004447 )


That's the simulation time for the program, right. Why is it different? 
Note first that the difference is pretty small. The difference is 
probably just due to the differences in the rcS file. Note that the 
calls to m5 are actual instructions that the simulator will execute so 
that will make some difference here and there. I wouldn't worry much 
about it. Just as a sanity check you can make arraywritenew to perform 
more/less work and see if the difference in sim_seconds between the two 
rcS is constant (which I'd expect) or linear.


Regards,

Oscar

On 02/09/17 08:25, 李莉 wrote:


Hi Oscar.

Thanks your rapid reply

First of all ,you are right ,the fs mode commend line edit 
error, because of my careless


Second , as you except ,the number of instructions executed is different.

Then, I change my rcS file followed you said ， I get a new stats,txt 
,the sim_seconds  is the actual simulation time for this program ,Am I 
right?


this  is my rcs file

#!/bin/sh
m5 resetstats
/arraywritenew
m5 exit

common line：build/X86/gem5.opt configs/example/fs.py 
--cpu-type=TimingSimpleCPU --caches --script=configs/boot/arraywrite.rcS


this is a part of my stats.txt

sim_seconds 0.004447   # Number of seconds simulated
sim_ticks 4447491000   # Number of ticks simulated
final_tick 5311293823000   # Number of ticks from 
beginning of simulation (restored from checkpoints and never reset)
sim_freq 1   # Frequency of simulated 
ticks


system.cpu.dtb.rdAccesses 305360   # TLB accesses 
on read requests
system.cpu.dtb.wrAccesses 227953   # TLB accesses 
on write requests
system.cpu.dtb.rdMisses 556   # TLB misses on read 
requests
system.cpu.dtb.wrMisses 175   # TLB misses on 
write requests


- End Simulation Statistics   --

Next I changed rcS file again,it has two Simulation Statistics ,Is 
sim_seconds(  0.004455   ) the actual simulation time for this 
program? why different the sim_seconds   ( 0.004447 )


this  is   my rcs file

m5 resetstats
/arraywritenew
m5 dumpstats
m5 exit

common line：build/X86/gem5.opt configs/example/fs.py 
--cpu-type=TimingSimpleCPU --caches --script=configs/boot/arraywrite.rcS


this is a part of  my stats.txt

-- Begin Simulation Statistics --
sim_seconds 0.004455   # Number of seconds simulated
sim_ticks 445488   # Number of ticks simulated
final_tick 531130128   # Number of ticks from 
beginning of simulation (restored from checkpoints and never reset)
sim_freq 1   # Frequency of simulated 
ticks


system.cpu.dtb.rdAccesses 306413   # TLB accesses 
on read requests
system.cpu.dtb.wrAccesses 228544   # TLB accesses 
on write requests
system.cpu.dtb.rdMisses 556   # TLB misses on read 
requests
system.cpu.dtb.wrMisses 175   # TLB misses on 
write requests


- End Simulation Statistics   --

-- Begin Simulation Statistics --
sim_seconds 0.006399   # Number of seconds simulated
sim_ticks 6399292000   # Number of ticks simulated
final_tick 5313245692000   # Number of ticks from 
beginning of simulation (restored from checkpoints and never reset)
sim_freq 1   # Frequency of simulated 
tickssystem.cpu.dtb.rdAccesses 430950   # TLB 
accesses on read requests
system.cpu.dtb.wrAccesses 323985   # TLB accesses 
on write requests
system.cpu.dtb.rdMisses 825   # TLB misses on read 
requests
system.cpu.dtb.wrMisses 249   # TLB misses on 
write requests


- End Simulation Statistics   --




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[gem5-users] Re：sim_seconds is a huge different between x86-se mode and x86- fs mode ,under the same program condition

2017-09-02 Thread 李莉 
Hi Oscar.

Thanks your rapid reply

First of all ,you are right ,the fs mode commend line edit error, because of my 
careless

Second , as you except ,the number of instructions executed is different.

Then, I change my rcS file followed you said ， I get a new stats,txt ,the 
sim_seconds  is the actual simulation time for this program ,Am I right?

this  is my rcs file

#!/bin/sh
m5 resetstats
/arraywritenew
m5 exit

common line：build/X86/gem5.opt configs/example/fs.py --cpu-type=TimingSimpleCPU 
--caches  --script=configs/boot/arraywrite.rcS

this is a part of my stats.txt

sim_seconds  0.004447   # 
Number of seconds simulated
sim_ticks  4447491000   # 
Number of ticks simulated
final_tick   5311293823000   # 
Number of ticks from beginning of simulation (restored from checkpoints and 
never reset)
sim_freq 1   # 
Frequency of simulated ticks

system.cpu.dtb.rdAccesses  305360   # 
TLB accesses on read requests
system.cpu.dtb.wrAccesses  227953   # 
TLB accesses on write requests
system.cpu.dtb.rdMisses   556   # 
TLB misses on read requests
system.cpu.dtb.wrMisses   175   # 
TLB misses on write requests

- End Simulation Statistics   --

Next I changed rcS file again,it has two Simulation Statistics ,Is sim_seconds  
  (  0.004455   ) the actual simulation time for this program? why different 
the sim_seconds   ( 0.004447 )

 

this  is   my rcs file

m5 resetstats
/arraywritenew
m5 dumpstats
m5 exit

common line：build/X86/gem5.opt configs/example/fs.py --cpu-type=TimingSimpleCPU 
--caches  --script=configs/boot/arraywrite.rcS

this is a part of  my stats.txt  

-- Begin Simulation Statistics --
sim_seconds  0.004455   # 
Number of seconds simulated
sim_ticks  445488   # 
Number of ticks simulated
final_tick   531130128   # 
Number of ticks from beginning of simulation (restored from checkpoints and 
never reset)
sim_freq 1   # 
Frequency of simulated ticks

system.cpu.dtb.rdAccesses  306413   # 
TLB accesses on read requests
system.cpu.dtb.wrAccesses  228544   # 
TLB accesses on write requests
system.cpu.dtb.rdMisses   556   # 
TLB misses on read requests
system.cpu.dtb.wrMisses   175   # 
TLB misses on write requests

- End Simulation Statistics   --

-- Begin Simulation Statistics --
sim_seconds  0.006399   # 
Number of seconds simulated
sim_ticks  6399292000   # 
Number of ticks simulated
final_tick   5313245692000   # 
Number of ticks from beginning of simulation (restored from checkpoints and 
never reset)
sim_freq 1   # 
Frequency of simulated tickssystem.cpu.dtb.rdAccesses  
430950   # TLB accesses on read requests
system.cpu.dtb.wrAccesses  323985   # 
TLB accesses on write requests
system.cpu.dtb.rdMisses   825   # 
TLB misses on read requests
system.cpu.dtb.wrMisses   249   # 
TLB misses on write requests

 

- End Simulation Statistics   --___
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