Re: [Intel-gfx] [PATCH 0/4] [CFT] interlaced support
On Sat, Jan 28, 2012 at 02:52:21AM +0100, Alfonso Fiore wrote: On Fri, Jan 27, 2012 at 10:41 PM, Daniel Vetter dan...@ffwll.ch wrote: Paulo and me have crawled around in interlaced-land some more I just came home ready to test my compiled kernel but when I read this message I thought I should download your latest source files and recompile. It was not so simple but I think I managed (by the way, what's the simple command to update my local copy?). $ git fetch remote-name should sync up your local git repo with that remote, then update your working copy with $ git checkout remote-name/branch-name like when checking out for the first time. while my new kernel compiles: is there a simple way to check I'm testing your latest changes and not the previous version? CONFIG_LOCALVERSION_AUTO appends the git sha1 to your uname -r string. -Daniel -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365 57 48 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/8] drm/i915: clean up interlaced pipeconf bit definitions
- Clarify which bits are for which chips. - Note that gen2 can't do interlaced directly (only via dvo tv chips). - Move the mask to the top to make it clearer how wide this field is. - Add defintions for all possible values. This patch doesn't change any code. v2: Paulo Zanoni pointed out that the pixel doubling modes do no longer exist on ivb. Cc: Peter Ross pr...@xvid.org Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/i915/i915_reg.h | 17 ++--- 1 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c3afb78..58f0cec 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2319,10 +2319,21 @@ #define PIPECONF_PALETTE 0 #define PIPECONF_GAMMA (124) #define PIPECONF_FORCE_BORDER(125) -#define PIPECONF_PROGRESSIVE (0 21) -#define PIPECONF_INTERLACE_W_FIELD_INDICATION(6 21) -#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 21) #define PIPECONF_INTERLACE_MASK (7 21) +/* Note that pre-gen3 does not support interlaced display directly. Panel + * fitting must be disabled on pre-ilk for interlaced. */ +#define PIPECONF_PROGRESSIVE (0 21) +#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL(4 21) /* gen4 only */ +#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 21) /* gen4 only */ +#define PIPECONF_INTERLACE_W_FIELD_INDICATION(6 21) +#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 21) /* gen3 only */ +/* Ironlake and later have a complete new set of values for interlaced. PFIT + * means panel fitter required, PF means progressive fetch, DBL means power + * saving pixel doubling. */ +#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 21) +#define PIPECONF_INTERLACED_ILK (3 21) +#define PIPECONF_INTERLACED_DBL_ILK (4 21) /* ilk/snb only */ +#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 21) /* ilk/snb only */ #define PIPECONF_CXSR_DOWNCLOCK (116) #define PIPECONF_BPP_MASK(0x00e0) #define PIPECONF_BPP_8 (05) -- 1.7.7.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 4/8] drm/i915: fixup interlaced support on ilk+
According to Paulo Zanoni, this is what windows does.
Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_display.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d108146..e7c9154 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5953,7 +5953,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
pipeconf = ~PIPECONF_INTERLACE_MASK;
if (adjusted_mode-flags DRM_MODE_FLAG_INTERLACE) {
- pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
+ pipeconf |= PIPECONF_INTERLACED_ILK;
/* the chip adds 2 halflines automatically */
adjusted_mode-crtc_vtotal -= 1;
adjusted_mode-crtc_vblank_end -= 1;
--
1.7.7.5
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[Intel-gfx] [PATCH 5/8] drm/i915: don't allow interlaced pipeconf on gen2
gen2 doesn't support it, so be a bit more paranoid and add a check to
ensure that we never ever set an unsupported interlaced bit.
Ensure that userspace can't set an interlaced mode by resetting
interlace_allowed for the crt on gen2. dvo and lvds are the only other
encoders that gen2 supports and these already disallow interlaced
modes.
Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_crt.c |5 -
drivers/gpu/drm/i915/intel_display.c |3 ++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index dd729d4..4d3d736 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -594,7 +594,10 @@ void intel_crt_init(struct drm_device *dev)
1 INTEL_ANALOG_CLONE_BIT |
1 INTEL_SDVO_LVDS_CLONE_BIT);
crt-base.crtc_mask = (1 0) | (1 1);
- connector-interlace_allowed = 1;
+ if (IS_GEN2(dev))
+ connector-interlace_allowed = 0;
+ else
+ connector-interlace_allowed = 1;
connector-doublescan_allowed = 0;
drm_encoder_helper_add(crt-base.base, intel_crt_helper_funcs);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e7c9154..dc80842 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5363,7 +5363,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
}
pipeconf = ~PIPECONF_INTERLACE_MASK;
- if (adjusted_mode-flags DRM_MODE_FLAG_INTERLACE) {
+ if (!IS_GEN2(dev)
+ adjusted_mode-flags DRM_MODE_FLAG_INTERLACE) {
pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
/* the chip adds 2 halflines automatically */
adjusted_mode-crtc_vtotal -= 1;
--
1.7.7.5
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[Intel-gfx] [PATCH 6/8] drm/i915: correctly program the VSYNCSHIFT register
The hw seems to use this to correctly insert the required delay
before/after an even/odd interlaced field. This might also explain
why we need to substract 1 half-line from vtotal - if the hw just
adds the delay programmend in VSYNCSHIFT the total frame time would be
about that too long.
These registers seems to only exist on gen4 and later. For paranoia
also program it to 0 for progressive modes, but according to
documentation the hw should just ignore it in this case.
Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/i915_reg.h |8
drivers/gpu/drm/i915/intel_display.c | 19 ---
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 58f0cec..bcd5cce 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1316,6 +1316,7 @@
#define _VSYNC_A 0x60014
#define _PIPEASRC 0x6001c
#define _BCLRPAT_A 0x60020
+#define _VSYNCSHIFT_A 0x60028
/* Pipe B timing regs */
#define _HTOTAL_B 0x61000
@@ -1326,6 +1327,8 @@
#define _VSYNC_B 0x61014
#define _PIPEBSRC 0x6101c
#define _BCLRPAT_B 0x61020
+#define _VSYNCSHIFT_B 0x61028
+
#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
@@ -1334,6 +1337,7 @@
#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
+#define VSYNCSHIFT(pipe) _PIPE(pipe, _VSYNCSHIFT_A, _VSYNCSHIFT_B)
/* VGA port control */
#define ADPA 0x61100
@@ -3216,6 +3220,7 @@
#define _TRANS_VSYNC_A 0xe0014
#define TRANS_VSYNC_END_SHIFT 16
#define TRANS_VSYNC_START_SHIFT 0
+#define _TRANS_VSYNCSHIFT_A0xe0028
#define _TRANSA_DATA_M1 0xe0030
#define _TRANSA_DATA_N1 0xe0034
@@ -3246,6 +3251,7 @@
#define _TRANS_VTOTAL_B 0xe100c
#define _TRANS_VBLANK_B 0xe1010
#define _TRANS_VSYNC_B 0xe1014
+#define _TRANS_VSYNCSHIFT_B 0xe1028
#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
@@ -3253,6 +3259,8 @@
#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
+#define TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _TRANS_VSYNCSHIFT_A, \
+_TRANS_VSYNCSHIFT_B)
#define _TRANSB_DATA_M1 0xe1030
#define _TRANSB_DATA_N1 0xe1034
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index dc80842..e842961 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2961,6 +2961,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
+ I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
intel_fdi_normal_train(crtc);
@@ -5081,7 +5082,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
int plane = intel_crtc-plane;
int refclk, num_connectors = 0;
intel_clock_t clock, reduced_clock;
- u32 dpll, dspcntr, pipeconf;
+ u32 dpll, dspcntr, pipeconf, vsyncshift;
bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
struct drm_mode_config *mode_config = dev-mode_config;
@@ -5369,8 +5370,15 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
/* the chip adds 2 halflines automatically */
adjusted_mode-crtc_vtotal -= 1;
adjusted_mode-crtc_vblank_end -= 1;
- } else
+ vsyncshift = adjusted_mode-crtc_hsync_start
+- adjusted_mode-crtc_htotal/2;
+ } else {
pipeconf |= PIPECONF_PROGRESSIVE;
+ vsyncshift = 0;
+ }
+
+ if (!IS_GEN3(dev))
+ I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
I915_WRITE(HTOTAL(pipe),
(adjusted_mode-crtc_hdisplay - 1) |
@@ -5958,8 +5966,13 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
/* the chip adds 2 halflines automatically */
adjusted_mode-crtc_vtotal -= 1;
adjusted_mode-crtc_vblank_end -= 1;
- } else
+ I915_WRITE(VSYNCSHIFT(pipe),
+ adjusted_mode-crtc_hsync_start
+ - adjusted_mode-crtc_htotal/2);
+ } else {
pipeconf |= PIPECONF_PROGRESSIVE;
+
[Intel-gfx] [PATCH 7/8] drm/i915: allow interlaced mode output on the SDVO connector
From: Peter Ross pr...@xvid.org Signed-off-by: Peter Ross pr...@xvid.org Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/i915/intel_sdvo.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 5b480bb..80fb5da 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1984,7 +1984,7 @@ intel_sdvo_connector_init(struct intel_sdvo_connector *connector, drm_connector_helper_add(connector-base.base, intel_sdvo_connector_helper_funcs); - connector-base.base.interlace_allowed = 0; + connector-base.base.interlace_allowed = 1; connector-base.base.doublescan_allowed = 0; connector-base.base.display_info.subpixel_order = SubPixelHorizontalRGB; -- 1.7.7.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 8/8] drm/i915: allow interlaced mode output on the HDMI connector
From: Peter Ross pr...@xvid.org Signed-off-by: Peter Ross pr...@xvid.org Signed-off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/i915/intel_hdmi.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 64541f7..086288e 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -514,7 +514,7 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) intel_encoder-type = INTEL_OUTPUT_HDMI; connector-polled = DRM_CONNECTOR_POLL_HPD; - connector-interlace_allowed = 0; + connector-interlace_allowed = 1; connector-doublescan_allowed = 0; intel_encoder-crtc_mask = (1 0) | (1 1) | (1 2); -- 1.7.7.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/4] [CFT] interlaced support
On Sat, Jan 28, 2012 at 11:46:10AM +0100, Alfonso Fiore wrote: On Sat, Jan 28, 2012 at 11:21 AM, Peter Ross pr...@xvid.org wrote: Great job guys. I can only quote. :) Thank you SO MUCH Daniel, Peter, Paulo and Angela. Well, thanks for getting the ball rolling and for all the testing. I've just sent out my latest patches and updated my interlaced branch. Please retest and reply to interlaced patches v2 with your tested-by. Thanks, Daniel -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365 57 48 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: fixup interlaced bits clearing in PIPECONF on PCH_SPLIT
2012/1/26 Daniel Vetter daniel.vet...@ffwll.ch: An identical patch has been merged for i9xx_crtc_mode_set: ommit 59df7b1771c150163e522f33c638096ab0efbf42 Author: Christian Schmidt schm...@digadd.de Date: Mon Dec 19 20:03:33 2011 +0100 drm/intel: Fix initialization if startup happens in interlaced mode [v2] But that one neglected to fix up the ironlake+ path. This should fix the issue reported by Alfonso Fiore where booting with only a HDMI cable connected to his TV failed to display anything. The issue is that the bios set up things for 1080i and used the pannel fitter to scale up the lower progressive resolutions. We failed to clear the interlace bit in the PIPEACONF register, resulting in havoc. v2: Be more paranoid and just unconditionally clear the field before setting new values. Cc: Peter Ross pr...@xvid.org Cc: Alfonso Fiore alfonso.fi...@gmail.com Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch Reviewed-by: Paulo Zanoni paulo.r.zan...@intel.com I didn't experience Alfonso's problem, but tested this patch with the interlaced series. Tested-by: Paulo Zanoni paulo.r.zan...@intel.com -- Paulo Zanoni ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/8] interlaced support v2
On Sat, Jan 28, 2012 at 02:49:18PM +0100, Daniel Vetter wrote: Hi all, These are the patches I'd like to queue to -next for interlaced support. Needs the patch fixup interlaced bits clearing in PIPECONF on PCH_SPLIT and also the drm core fix drm/modes: do not enforce an odd vtotal for interlaced modes if you want to use interlaced modelines with an even vtotal. The entire series is available in my interlaced branch at http://cgit.freedesktop.org/~danvet/drm/log/?h=interlaced Review, comments and testing highly welcome. From irc: Tested-by: Christopher Egert cme3...@gmail.com On an i915gm eeepc over the VGA connector: 1080i@50Hz on a TV and 1600x1200@100Hz on a CRT. For him interlaced over VGA is broken on at least the 3.1 kernel his ubuntu install shipped with. -Daniel -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365 57 48 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 0/8] interlaced support v2
On Sat, Jan 28, 2012 at 2:49 PM, Daniel Vetter daniel.vet...@ffwll.ch wrote: Hi all, These are the patches I'd like to queue to -next for interlaced support. Needs the patch fixup interlaced bits clearing in PIPECONF on PCH_SPLIT and also the drm core fix drm/modes: do not enforce an odd vtotal for interlaced modes if you want to use interlaced modelines with an even vtotal. The entire series is available in my interlaced branch at http://cgit.freedesktop.org/~danvet/drm/log/?h=interlaced Review, comments and testing highly welcome. Tested-by: Alfonso Fiore alfonso.fi...@gmail.com i3 2130 connected to a Philips 32pf9731d over HDMI: - 1920x1080i@30Hz - 1280x720p@60Hz - 1024x768p@60Hz thanks again, alfonso ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: fixup overlay checks for interlaced modes
The drm core _really_ likes to frob around with the crtc timings and
put halfed vertical timings (in fields) in there. Which confuses the
overlay code, resulting in it's refusal to display anything at the
lower half of an interlaced pipe.
Tested-by: Christopher Egert cme3...@gmail.com
Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch
---
drivers/gpu/drm/i915/intel_overlay.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_overlay.c
b/drivers/gpu/drm/i915/intel_overlay.c
index cdf17d4..2cb67bf 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -935,10 +935,10 @@ static int check_overlay_dst(struct intel_overlay
*overlay,
{
struct drm_display_mode *mode = overlay-crtc-base.mode;
- if (rec-dst_x mode-crtc_hdisplay
- rec-dst_x + rec-dst_width = mode-crtc_hdisplay
- rec-dst_y mode-crtc_vdisplay
- rec-dst_y + rec-dst_height = mode-crtc_vdisplay)
+ if (rec-dst_x mode-hdisplay
+ rec-dst_x + rec-dst_width = mode-hdisplay
+ rec-dst_y mode-vdisplay
+ rec-dst_y + rec-dst_height = mode-vdisplay)
return 0;
else
return -EINVAL;
--
1.7.8.3
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Re: [Intel-gfx] [PATCH] drm/i915: fixup interlaced bits clearing in PIPECONF on PCH_SPLIT
On Sat, 28 Jan 2012 12:07:55 +0100, Daniel Vetter dan...@ffwll.ch wrote: Alfonso reported back that this does indeed fix up his black screen on boot issues when the bios sets up the hdmi connector with an interlaced mode. Can you pick this patch up for -fixes if it musters your review? Looks good. I've checked this with the docs; the (6 21) value used before seems completely random, the new value (7 21) looks correct. Merged to drm-intel-fixes. -- keith.pack...@intel.com pgpwUSgA5IivX.pgp Description: PGP signature ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH][rebased] drm/i915: set AUD_CONFIG N_value_index for DisplayPort
It should be programmed to 0 for HDMI or 1 for DisplayPort.
This enables DisplayPort audio for
- HP EliteBook 8460p
(whose BIOS does not set the N_value_index bit for us)
- DisplayPort monitor hot plugged after boot
(otherwise most BIOS will fill the N_value_index bit for us)
Tested-by: Robert Lemaire rlema...@suse.com
Signed-off-by: Wu Fengguang fengguang...@intel.com
---
drivers/gpu/drm/i915/i915_reg.h | 12
drivers/gpu/drm/i915/intel_display.c |8 +++-
2 files changed, 19 insertions(+), 1 deletion(-)
I've tried to apply this patch but it has a conflict in i915_reg.h (with
the SOL reset stuff). Care to rebase and resend? Also, git patches as
produced by git format-patch highly preferred.
Daniel, this is now based on linux-next. I use quilt, hope it also
works for you :)
--- linux-next.orig/drivers/gpu/drm/i915/i915_reg.h 2012-01-07
20:47:34.0 +0800
+++ linux-next/drivers/gpu/drm/i915/i915_reg.h 2012-01-29 12:37:31.0
+0800
@@ -3742,4 +3742,16 @@
*/
#define GEN7_SO_WRITE_OFFSET(n)(0x5280 + (n) * 4)
+#define IBX_AUD_CONFIG_A 0xe2000
+#define CPT_AUD_CONFIG_A 0xe5000
+#define AUD_CONFIG_N_VALUE_INDEX (1 29)
+#define AUD_CONFIG_N_PROG_ENABLE (1 28)
+#define AUD_CONFIG_UPPER_N_SHIFT 20
+#define AUD_CONFIG_UPPER_N_VALUE (0xff 20)
+#define AUD_CONFIG_LOWER_N_SHIFT 4
+#define AUD_CONFIG_LOWER_N_VALUE (0xfff 4)
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT16
+#define AUD_CONFIG_PIXEL_CLOCK_HDMI (0xf 16)
+#define AUD_CONFIG_DISABLE_NCTS (1 3)
+
#endif /* _I915_REG_H_ */
--- linux-next.orig/drivers/gpu/drm/i915/intel_display.c2012-01-29
12:23:17.0 +0800
+++ linux-next/drivers/gpu/drm/i915/intel_display.c 2012-01-29
12:37:31.0 +0800
@@ -6072,15 +6072,18 @@ static void ironlake_write_eld(struct dr
uint32_t i;
int len;
int hdmiw_hdmiedid;
+ int aud_config;
int aud_cntl_st;
int aud_cntrl_st2;
if (HAS_PCH_IBX(connector-dev)) {
hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
+ aud_config = IBX_AUD_CONFIG_A;
aud_cntl_st = IBX_AUD_CNTL_ST_A;
aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
} else {
hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
+ aud_config = CPT_AUD_CONFIG_A;
aud_cntl_st = CPT_AUD_CNTL_ST_A;
aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
}
@@ -6088,6 +6091,7 @@ static void ironlake_write_eld(struct dr
i = to_intel_crtc(crtc)-pipe;
hdmiw_hdmiedid += i * 0x100;
aud_cntl_st += i * 0x100;
+ aud_config += i * 0x100;
DRM_DEBUG_DRIVER(ELD on pipe %c\n, pipe_name(i));
@@ -6107,7 +6111,9 @@ static void ironlake_write_eld(struct dr
if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
DRM_DEBUG_DRIVER(ELD: DisplayPort detected\n);
eld[5] |= (1 2); /* Conn_Type, 0x1 = DisplayPort */
- }
+ I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
+ } else
+ I915_WRITE(aud_config, 0);
if (intel_eld_uptodate(connector,
aud_cntrl_st2, eldv,
___
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