[Intel-gfx] [ANNOUNCE] xf86-video-intel 2.20.5
Another silly bug found, another small bugfix release. The goal was for the driver to bind to all Intel devices supported by the kernel. Unfortunately we were too successful and started claiming Pouslbo, Medfield and Cedarview devices which are still encumbered by propietary IP and not supported by this driver. Bugs fixed since 2.20.4: * Only bind to Intel devices using the i915 kernel module * Regression in the bitmap-to-region code, e.g. icewm window buttons https://bugs.freedesktop.org/show_bug.cgi?id=53699 -Chris Chris Wilson (58): sna: Add damage for the whole unaligned trapezoid not per component sna/damage: Add some more sanity checks for creating empty regions sna: Reduce damage after a large composite operation sna: Reduce subtracted damage earlier sna: Avoid forcing an upload for an unblittable bo unless on a fallback path sna/damage: Replace the damage with a larger box if subsumed sna: Consider sample wraparound in each direction independently sna: Enable BLT composite functions to target CPU buffers sna: compare the correct trailing dword when skipping identical bitmap lines sna: Only submit the batch if flushing a DRI client bo sna: Update maybe_inplace to recognise more types of handled pixel formats sna/trapezoids: Accept more operators for maybe-inplace sna: Discard GPU (and damage) after applying clear on migration to CPU sna: Tweak is_cpu/is_gpu heuristics sna/gen3: Tidy vbo discard sna: Don't promote a ShmPixmap to GPU for a CopyArea sna: Experiment with flushing the batch prior to rendering to a ShmPixmap sna: Do not use the GPU to migrate to the CPU whilst wedged! sna: Flush the batch before preparing for a FlushCallback sna: Remove unneeded source bo unref after __sna_render_pixmap_bo() sna: Avoid migrating the BLT composite src to the GPU if the dst is not Sanity check that the driver is an i915.ko GEM device before claiming it sna: Add a modicum of DBG for PolyFillRect Missing includes for b5b76ad849b sna: Correct ordering of calls to memcpy for BLT cpu composite paths sna: Refine decision making for maybe-inplace trapezoids sna: Remove confusing is_cpu() sna: Add a couple of buffer cache management assertions Only open the matching BusID and not the first named Check that the module that indeed i915 before using custom ioctls sna: A few more buffer cache management assertions sna: Keep a stash of the most recently allocated requests sna: Trim a parameter from kgem_bo_mark_dirty() and add some assertions sna/gen3: Convert to sna_drawable_use_bo() sna: Assign a unique id to snoopable CPU bo sna: Allow target bo promotion to GPU even on old architectures sna/gen3: Fix assertion to check the freshly allocated vertex bo sna/gen6+: Only mark the dst as dirty again if it already is in the batch sna: Mark all levels of a proxy as dirty sna: Fix the assertion for tracking proxies in the batch sna: Add a DBG to log pixmap destruction sna: Display still resident memory in inactive/snoop caches under DEBUG_MEMORY sna: Balance CPU bo accounting for SHM pixmaps sna: Discard a no-longer-used GPU bo after moving to the CPU domain sna: Make sure the opposite damage is destroyed after reducing to all sna: Assert that the CPU bo is not used if the GPU is clear sna: Convert to using IGNORE_CPU flag rather than complicating the CPU damage sna: If we cannot use the CPU bo along a render pathway, promote to GPU sna: Only use the GPU for an active CPU bo unless forced sna: Flush before adding any SHM pixmap into the batch sna: Mark the CPU damage as needing flushing for DRI buffers sna: Flush the batch if it contains any DRI pixmaps sna: Use a temporary userptr mapping for a large upload into a busy target sna: Tidy up users of __kgem_bo_is_busy() sna: Correct a pair of DBG messages sna: Allow the batch to be flushed if the GPU is idle upon a context switch sna: Submit the partial batch before throttling 2.20.5 release Eric S. Raymond (1): Fix seriously malformed list syntax on intel(4). git tag: 2.20.5 http://xorg.freedesktop.org/archive/individual/driver/xf86-video-intel-2.20.5.tar.bz2 MD5: f6105268d7a63783460526ffe327e6c0 xf86-video-intel-2.20.5.tar.bz2 SHA1: 7ca9706fd3bd8b40e6f3288aa6e02b9ed44c6503 xf86-video-intel-2.20.5.tar.bz2 SHA256: 143d1cd808694ca7202b642fbb2b03a43a7474d7b527216c517fc41319410bec xf86-video-intel-2.20.5.tar.bz2 http://xorg.freedesktop.org/archive/individual/driver/xf86-video-intel-2.20.5.tar.gz MD5: 4816fe78992aef3bbfccdc67969c77f0 xf86-video-intel-2.20.5.tar.gz SHA1: f6217a986775fe2ab569c82014907f9ea5545443 xf86-video-intel-2.20.5.tar.gz SHA256:
[Intel-gfx] Please add last edited date to http://intellinuxgraphics.org/
Dear Intel folks, it would be nice if you could add a “last edited” field to the Web site so information like on the teams page [1] can be judged better. (It seems recent though, which is great and which should be made obvious.) Thanks, Paul [1] http://intellinuxgraphics.org/team.html signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ironlake rc6 + iommu = hangage
On Sun, Aug 26, 2012 at 02:53:50PM +1000, Dave Airlie wrote: It appears that running with iommu=on and ILK rc6 enabled on drm-next my machine hangs somewhere randomly between gdm starting, logging in, and gnome-shell starting. Setting iommu=igfx_off or off works around it. Since the same rc6+iommu combination is known to not work on snb, too, I'll just disable rc6 if the iommu is on. Since we've never figured out what's broken with rc6 on ilk (and all the old reporters disappeared) thanks a lot for hitting this ;-) btw I don't know if I'm seeing any power saving with ILK rc6 enabled, will do a bit more checking. Little afaik. Since the gpu is on a separate die in the package there's much less to switch off - all the inter-die coordination happens manually on ilk and hence all that stuff needs to be kept on. Thanks, Daniel -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365 57 48 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] Updated -testing
Hi All, Another two weeks, another round of -testing. Highlights: - prep patches for the modeset rework. Note that one of those patches touches the fb helper in the common drm code. - hasw hdmi audio support (Wang Xingchao) - improved instdone dumping for gen7 (Ben) - unbound tracking and a few follow-up patches from Chris - dma_buf-begin/end_cpu_access plus fix for drm/udl (Dave) - improve mmio error reporting for hsw - prep patch for WQ_NON_REENTRANT removal (Tejun Heo) Go forth and test! Cheers, Daniel -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365 57 48 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 2/2] mmio: Limit the uc- mapping to only map the registers
In the future, we may like to enable wc mapping of at least the GATT,
and so causing a conflict if we attempt to map the entire bar as uc-
here. Obviously we need a better fallback plan, but for the moment only
attempt to map the portion of the pci space that we use for register
access.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
lib/intel_mmio.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/lib/intel_mmio.c b/lib/intel_mmio.c
index b266847..ecb049b 100644
--- a/lib/intel_mmio.c
+++ b/lib/intel_mmio.c
@@ -80,8 +80,8 @@ intel_map_file(char *file)
void
intel_get_mmio(struct pci_device *pci_dev)
{
- uint32_t devid;
- int mmio_bar;
+ uint32_t devid, gen;
+ int mmio_bar, mmio_size;
int error;
devid = pci_dev-device_id;
@@ -90,11 +90,19 @@ intel_get_mmio(struct pci_device *pci_dev)
else
mmio_bar = 0;
+ gen = intel_gen(devid);
+ if (gen 3)
+ mmio_size = 64*1024;
+ else if (gen 5)
+ mmio_size = 512*1024;
+ else
+ mmio_size = 2*1024*1024;
+
error = pci_device_map_range (pci_dev,
- pci_dev-regions[mmio_bar].base_addr,
- pci_dev-regions[mmio_bar].size,
- PCI_DEV_MAP_FLAG_WRITABLE,
- mmio);
+ pci_dev-regions[mmio_bar].base_addr,
+ mmio_size,
+ PCI_DEV_MAP_FLAG_WRITABLE,
+ mmio);
if (error != 0) {
fprintf(stderr, Couldn't map MMIO region: %s\n,
--
1.7.10.4
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[Intel-gfx] [PATCH 1/2] intel_gtt: Harden against changes to kernel mappings of the GTT
Rather than use the common mmio segment which will be in future
restricted to just the registers and so exclude the GTT portion on all
architectures, explicitly mmap the GTT ourselves. Repeat this mmapping
with a couple of flags until we matching the existing kernel mapping.
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
tools/intel_gtt.c | 46 ++
1 file changed, 30 insertions(+), 16 deletions(-)
diff --git a/tools/intel_gtt.c b/tools/intel_gtt.c
index c246fda..05d36d7 100644
--- a/tools/intel_gtt.c
+++ b/tools/intel_gtt.c
@@ -45,33 +45,47 @@ int main(int argc, char **argv)
int start, aper_size;
unsigned char *gtt;
uint32_t devid;
+ int flag[] = {
+ PCI_DEV_MAP_FLAG_WRITE_COMBINE,
+ PCI_DEV_MAP_FLAG_WRITABLE,
+ 0
+ }, f;
pci_dev = intel_get_pci_device();
devid = pci_dev-device_id;
- intel_get_mmio(pci_dev);
if (IS_GEN2(devid)) {
printf(Unsupported chipset for gtt dumper\n);
exit(1);
}
- if (IS_G4X(devid) || IS_GEN5(devid))
- gtt = ((unsigned char *)mmio + MB(2));
- else if (IS_965(devid))
- gtt = ((unsigned char *)mmio + KB(512));
- else {
- /* 915/945 chips has GTT range in bar 3 */
- int err;
- err = pci_device_map_range(pci_dev,
- pci_dev-regions[3].base_addr,
- pci_dev-regions[3].size,
- PCI_DEV_MAP_FLAG_WRITABLE,
- (void **)gtt);
- if (err != 0) {
- fprintf(stderr, mapping GTT bar failed\n);
- exit(1);
+ for (f = 0; flag[f] != 0; f++) {
+ if (IS_GEN3(devid)) {
+ /* 915/945 chips has GTT range in bar 3 */
+ if (pci_device_map_range(pci_dev,
+pci_dev-regions[3].base_addr,
+pci_dev-regions[3].size,
+flag[f],
+(void **)gtt) == 0)
+ break;
+ } else {
+ int offset;
+ if (IS_G4X(devid) || IS_GEN5(devid))
+ offset = MB(2);
+ else
+ offset = KB(512);
+ if (pci_device_map_range(pci_dev,
+pci_dev-regions[0].base_addr
+ offset,
+offset,
+flag[f],
+(void **)gtt) == 0)
+ break;
}
}
+ if (flag[f] == 0) {
+ printf(Failed to map gtt\n);
+ exit(1);
+ }
aper_size = pci_dev-regions[2].size;
--
1.7.10.4
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