[Intel-gfx] [PATCH 1/5 v5] drm/i915: Stop using AGP layer for GEN6+
As a quick hack we make the old intel_gtt structure mutable so we can
fool a bunch of the existing code which depends on elements in that data
structure. We can/should try to remove this in a subsequent patch.
This should preserve the old gtt init behavior which upon writing these
patches seems incorrect. The next patch will fix these things.
The one exception is VLV which doesn't have the preserved flush control
write behavior. Since we want to do that for all GEN6+ stuff, we'll
handle that in a later patch. Mainstream VLV support doesn't actually
exist yet anyway.
v2: Update the comment to remove the voodoo
Check that the last pte written matches what we readback
v3: actually kill cache_level_to_agp_type since most of the flags will
disappear in an upcoming patch
v4: v3 was actually not what we wanted (Daniel)
Make the ggtt bind assertions better and stricter (Chris)
Fix some uncaught errors at gtt init (Chris)
Some other random stuff that Chris wanted
v5: check for i==0 in gen6_ggtt_bind_object to shut up gcc (Ben)
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Reviewed-by [v4]: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/char/agp/intel-gtt.c | 2 +-
drivers/gpu/drm/i915/i915_dma.c| 16 +-
drivers/gpu/drm/i915/i915_drv.h| 10 +-
drivers/gpu/drm/i915/i915_gem.c| 12 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c| 257 +
drivers/gpu/drm/i915/i915_reg.h| 6 +
include/drm/intel-gtt.h| 3 +-
8 files changed, 257 insertions(+), 51 deletions(-)
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 38390f7..4dfbb80 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1686,7 +1686,7 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct
pci_dev *gpu_pdev,
}
EXPORT_SYMBOL(intel_gmch_probe);
-const struct intel_gtt *intel_gtt_get(void)
+struct intel_gtt *intel_gtt_get(void)
{
return intel_private.base;
}
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index d04facb..d9b4a49 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1494,19 +1494,9 @@ int i915_driver_load(struct drm_device *dev, unsigned
long flags)
goto free_priv;
}
- ret = intel_gmch_probe(dev_priv-bridge_dev, dev-pdev, NULL);
- if (!ret) {
- DRM_ERROR(failed to set up gmch\n);
- ret = -EIO;
+ ret = i915_gem_gtt_init(dev);
+ if (ret)
goto put_bridge;
- }
-
- dev_priv-mm.gtt = intel_gtt_get();
- if (!dev_priv-mm.gtt) {
- DRM_ERROR(Failed to initialize GTT\n);
- ret = -ENODEV;
- goto put_gmch;
- }
i915_kick_out_firmware_fb(dev_priv);
@@ -1680,7 +1670,7 @@ out_mtrrfree:
out_rmmap:
pci_iounmap(dev-pdev, dev_priv-regs);
put_gmch:
- intel_gmch_remove();
+ i915_gem_gtt_fini(dev);
put_bridge:
pci_dev_put(dev_priv-bridge_dev);
free_priv:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a2c5e89..7274360 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -686,7 +686,7 @@ typedef struct drm_i915_private {
struct {
/** Bridge to intel-gtt-ko */
- const struct intel_gtt *gtt;
+ struct intel_gtt *gtt;
/** Memory allocator for GTT stolen memory */
struct drm_mm stolen;
/** Memory allocator for GTT */
@@ -1505,6 +1505,14 @@ void i915_gem_init_global_gtt(struct drm_device *dev,
unsigned long start,
unsigned long mappable_end,
unsigned long end);
+int i915_gem_gtt_init(struct drm_device *dev);
+void i915_gem_gtt_fini(struct drm_device *dev);
+extern inline void i915_gem_chipset_flush(struct drm_device *dev)
+{
+ if (INTEL_INFO(dev)-gen 6)
+ intel_gtt_chipset_flush();
+}
+
/* i915_gem_evict.c */
int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7dd1034..859ac4f 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -845,12 +845,12 @@ out:
* domain anymore. */
if (obj-base.write_domain != I915_GEM_DOMAIN_CPU) {
i915_gem_clflush_object(obj);
- intel_gtt_chipset_flush();
+ i915_gem_chipset_flush(dev);
}
}
if (needs_clflush_after)
- intel_gtt_chipset_flush();
+ i915_gem_chipset_flush(dev);
return ret;
}
@@ -3058,7 +3058,7 @@
[Intel-gfx] [PATCH 2/5] drm/i915: Calculate correct stolen size for GEN7+
This bug existed in the old code, but was easier to fix here in the
rework. Unfortunately gen7 doesn't have a nice way to figure out the
size and we must use a lookup table.
As Jesse pointed out, there is some confusion in the docs about these
definitions. We're picking the one which seems more accurate, but we
really aren't certain.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 14 +-
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b7eabdb..4abde31 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -512,6 +512,15 @@ static inline unsigned int gen6_get_stolen_size(u16
snb_gmch_ctl)
return snb_gmch_ctl 25; /* 32 MB units */
}
+static inline unsigned int gen7_get_stolen_size(u16 snb_gmch_ctl)
+{
+ static const int stolen_decoder[] = {
+ 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352};
+ snb_gmch_ctl = IVB_GMCH_GMS_SHIFT;
+ snb_gmch_ctl = IVB_GMCH_GMS_MASK;
+ return stolen_decoder[snb_gmch_ctl] 20;
+}
+
int i915_gem_gtt_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev-dev_private;
@@ -557,7 +566,10 @@ int i915_gem_gtt_init(struct drm_device *dev)
pci_read_config_word(dev-pdev, SNB_GMCH_CTRL, snb_gmch_ctl);
dev_priv-mm.gtt-gtt_total_entries =
gen6_get_total_gtt_size(snb_gmch_ctl) / sizeof(gtt_pte_t);
- dev_priv-mm.gtt-stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
+ if (INTEL_INFO(dev)-gen 7)
+ dev_priv-mm.gtt-stolen_size =
gen6_get_stolen_size(snb_gmch_ctl);
+ else
+ dev_priv-mm.gtt-stolen_size =
gen7_get_stolen_size(snb_gmch_ctl);
dev_priv-mm.gtt-gtt_mappable_entries = pci_resource_len(dev-pdev, 2)
PAGE_SHIFT;
/* 64/512MB is the current min/max we actually know of, but this is
just a
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a49ddd1..9de463f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -46,6 +46,8 @@
#defineSNB_GMCH_GGMS_MASK 0x3
#defineSNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */
#defineSNB_GMCH_GMS_MASK0x1f
+#defineIVB_GMCH_GMS_SHIFT 4
+#defineIVB_GMCH_GMS_MASK0xf
/* PCI config space */
--
1.8.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 3/5 v2] drm/i915: Kill off now unused gen6+ AGP code
v2: Accidently removed an ILK case in i9xx_setup (Nicely found by Chris) CC: Chris Wilson ch...@chris-wilson.co.uk Reviewed-by [v1] : Jesse Barnes jbar...@virtuousgeek.org Signed-off-by: Ben Widawsky b...@bwidawsk.net --- drivers/char/agp/intel-agp.h | 91 - drivers/char/agp/intel-gtt.c | 318 ++- include/drm/intel-gtt.h | 4 - 3 files changed, 11 insertions(+), 402 deletions(-) diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h index 6ec0fff..1042c1b 100644 --- a/drivers/char/agp/intel-agp.h +++ b/drivers/char/agp/intel-agp.h @@ -62,12 +62,6 @@ #define I810_PTE_LOCAL 0x0002 #define I810_PTE_VALID 0x0001 #define I830_PTE_SYSTEM_CACHED 0x0006 -/* GT PTE cache control fields */ -#define GEN6_PTE_UNCACHED 0x0002 -#define HSW_PTE_UNCACHED 0x -#define GEN6_PTE_LLC 0x0004 -#define GEN6_PTE_LLC_MLC 0x0006 -#define GEN6_PTE_GFDT 0x0008 #define I810_SMRAM_MISCC 0x70 #define I810_GFX_MEM_WIN_SIZE 0x0001 @@ -97,7 +91,6 @@ #define G4x_GMCH_SIZE_VT_2M(G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN) #define GFX_FLSH_CNTL 0x2170 /* 915+ */ -#define GFX_FLSH_CNTL_VLV 0x101008 #define I810_DRAM_CTL 0x3000 #define I810_DRAM_ROW_00x0001 @@ -148,29 +141,6 @@ #define INTEL_I7505_AGPCTRL0x70 #define INTEL_I7505_MCHCFG 0x50 -#define SNB_GMCH_CTRL 0x50 -#define SNB_GMCH_GMS_STOLEN_MASK 0xF8 -#define SNB_GMCH_GMS_STOLEN_32M(1 3) -#define SNB_GMCH_GMS_STOLEN_64M(2 3) -#define SNB_GMCH_GMS_STOLEN_96M(3 3) -#define SNB_GMCH_GMS_STOLEN_128M (4 3) -#define SNB_GMCH_GMS_STOLEN_160M (5 3) -#define SNB_GMCH_GMS_STOLEN_192M (6 3) -#define SNB_GMCH_GMS_STOLEN_224M (7 3) -#define SNB_GMCH_GMS_STOLEN_256M (8 3) -#define SNB_GMCH_GMS_STOLEN_288M (9 3) -#define SNB_GMCH_GMS_STOLEN_320M (0xa 3) -#define SNB_GMCH_GMS_STOLEN_352M (0xb 3) -#define SNB_GMCH_GMS_STOLEN_384M (0xc 3) -#define SNB_GMCH_GMS_STOLEN_416M (0xd 3) -#define SNB_GMCH_GMS_STOLEN_448M (0xe 3) -#define SNB_GMCH_GMS_STOLEN_480M (0xf 3) -#define SNB_GMCH_GMS_STOLEN_512M (0x10 3) -#define SNB_GTT_SIZE_0M(0 8) -#define SNB_GTT_SIZE_1M(1 8) -#define SNB_GTT_SIZE_2M(2 8) -#define SNB_GTT_SIZE_MASK (3 8) - /* pci devices ids */ #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588 #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a @@ -219,66 +189,5 @@ #define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062 #define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB0x006a #define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046 -#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100 /* Desktop */ -#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG 0x0102 -#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG 0x0112 -#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG0x0122 -#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104 /* Mobile */ -#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG 0x0106 -#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG 0x0116 -#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG 0x0126 -#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */ -#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A -#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB 0x0150 /* Desktop */ -#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG 0x0152 -#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG 0x0162 -#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB 0x0154 /* Mobile */ -#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG 0x0156 -#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG 0x0166 -#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB 0x0158 /* Server */ -#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG 0x015A -#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT2_IG 0x016A -#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_HB 0x0F00 /* VLV1 */ -#define PCI_DEVICE_ID_INTEL_VALLEYVIEW_IG 0x0F30 -#define PCI_DEVICE_ID_INTEL_HASWELL_HB 0x0400 /* Desktop */ -#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT1_IG 0x0402 -#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_IG 0x0412 -#define PCI_DEVICE_ID_INTEL_HASWELL_D_GT2_PLUS_IG 0x0422 -#define PCI_DEVICE_ID_INTEL_HASWELL_M_HB 0x0404 /* Mobile */ -#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT1_IG 0x0406 -#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_IG 0x0416 -#define PCI_DEVICE_ID_INTEL_HASWELL_M_GT2_PLUS_IG 0x0426 -#define PCI_DEVICE_ID_INTEL_HASWELL_S_HB 0x0408 /* Server */ -#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT1_IG 0x040a -#define PCI_DEVICE_ID_INTEL_HASWELL_S_GT2_IG
[Intel-gfx] [PATCH 4/5 v2] drm/i915: flush system agent TLBs on SNB
This allows us to map the PTEs WC. I've not done thorough testing or
performance measurements with this patch, but it should be decent.
This is based on a patch from Jesse with the original commit message
I've only lightly tested this so far, but the corruption seems to be
gone if I write the GFX_FLSH_CNTL reg after binding an object. This
register should control the TLB for the system agent, which is what CPU
mapped objects will go through.
It has been updated for the new AGP-less code by me, and included with
it is feedback from the original patch.
v2: Updated to reflect paranoia on pte updates/register posting reads.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Reviewed-by [v1]: Jesse Barnes jbar...@virtuousgeek.org
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 11 +--
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 4abde31..9a5b035 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -379,6 +379,13 @@ static void gen6_ggtt_bind_object(struct
drm_i915_gem_object *obj,
*/
if (i != 0)
WARN_ON(readl(gtt_entries[i-1]) != pte_encode(dev, addr,
level));
+
+ /* This next bit makes the above posting read even more important. We
+* want to flush the TLBs only after we're certain all the PTE updates
+* have finished.
+*/
+ I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
+ POSTING_READ(GFX_FLSH_CNTL_GEN6);
}
void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
@@ -589,8 +596,8 @@ int i915_gem_gtt_init(struct drm_device *dev)
goto err_out;
}
- dev_priv-mm.gtt-gtt = ioremap(gtt_bus_addr,
- dev_priv-mm.gtt-gtt_total_entries *
sizeof(gtt_pte_t));
+ dev_priv-mm.gtt-gtt = ioremap_wc(gtt_bus_addr,
+ dev_priv-mm.gtt-gtt_total_entries
* sizeof(gtt_pte_t));
if (!dev_priv-mm.gtt-gtt) {
DRM_ERROR(Failed to map the gtt page table\n);
teardown_scratch_page(dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9de463f..7942838 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -688,6 +688,8 @@
#define CM0_RC_OP_FLUSH_DISABLE (10)
#define BB_ADDR0x02140 /* 8 bytes */
#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
+#define GFX_FLSH_CNTL_GEN6 0x101008
+#define GFX_FLSH_CNTL_EN (10)
#define ECOSKPD0x021d0
#define ECO_GATING_CX_ONLY (13)
#define ECO_FLIP_DONE(10)
--
1.8.0
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 5/5] drm/i915: Move the remaining gtt code
It's pretty much all consolidated now that we've killed AGP. We can move
the one outlier, and defines too.
(Kill some unused defines in the process)
Signed-off-by: Ben Widawsky b...@bwidawsk.net
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
---
drivers/gpu/drm/i915/i915_gem.c | 62 --
drivers/gpu/drm/i915/i915_gem_gtt.c | 76 +
drivers/gpu/drm/i915/i915_reg.h | 17 -
3 files changed, 76 insertions(+), 79 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 859ac4f..b6a0c74 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3875,68 +3875,6 @@ void i915_gem_init_swizzling(struct drm_device *dev)
I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
}
-void i915_gem_init_ppgtt(struct drm_device *dev)
-{
- drm_i915_private_t *dev_priv = dev-dev_private;
- uint32_t pd_offset;
- struct intel_ring_buffer *ring;
- struct i915_hw_ppgtt *ppgtt = dev_priv-mm.aliasing_ppgtt;
- uint32_t __iomem *pd_addr;
- uint32_t pd_entry;
- int i;
-
- if (!dev_priv-mm.aliasing_ppgtt)
- return;
-
-
- pd_addr = dev_priv-mm.gtt-gtt + ppgtt-pd_offset/sizeof(uint32_t);
- for (i = 0; i ppgtt-num_pd_entries; i++) {
- dma_addr_t pt_addr;
-
- if (dev_priv-mm.gtt-needs_dmar)
- pt_addr = ppgtt-pt_dma_addr[i];
- else
- pt_addr = page_to_phys(ppgtt-pt_pages[i]);
-
- pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
- pd_entry |= GEN6_PDE_VALID;
-
- writel(pd_entry, pd_addr + i);
- }
- readl(pd_addr);
-
- pd_offset = ppgtt-pd_offset;
- pd_offset /= 64; /* in cachelines, */
- pd_offset = 16;
-
- if (INTEL_INFO(dev)-gen == 6) {
- uint32_t ecochk, gab_ctl, ecobits;
-
- ecobits = I915_READ(GAC_ECO_BITS);
- I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
-
- gab_ctl = I915_READ(GAB_CTL);
- I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
-
- ecochk = I915_READ(GAM_ECOCHK);
- I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
- ECOCHK_PPGTT_CACHE64B);
- I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
- } else if (INTEL_INFO(dev)-gen = 7) {
- I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
- /* GFX_MODE is per-ring on gen7+ */
- }
-
- for_each_ring(ring, dev_priv, i) {
- if (INTEL_INFO(dev)-gen = 7)
- I915_WRITE(RING_MODE_GEN7(ring),
- _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
-
- I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
- I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
- }
-}
-
static bool
intel_enable_blt(struct drm_device *dev)
{
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 9a5b035..4d62f32 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -30,6 +30,20 @@
typedef uint32_t gtt_pte_t;
+/* PPGTT stuff */
+#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) 28) 0xff0))
+
+#define GEN6_PDE_VALID (1 0)
+/* gen6+ has bit 11-4 for physical addr bit 39-32 */
+#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
+
+#define GEN6_PTE_VALID (1 0)
+#define GEN6_PTE_UNCACHED (1 1)
+#define HSW_PTE_UNCACHED (0)
+#define GEN6_PTE_CACHE_LLC (2 1)
+#define GEN6_PTE_CACHE_LLC_MLC (3 1)
+#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
+
static inline gtt_pte_t pte_encode(struct drm_device *dev,
dma_addr_t addr,
enum i915_cache_level level)
@@ -262,6 +276,68 @@ void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
obj-base.size PAGE_SHIFT);
}
+void i915_gem_init_ppgtt(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = dev-dev_private;
+ uint32_t pd_offset;
+ struct intel_ring_buffer *ring;
+ struct i915_hw_ppgtt *ppgtt = dev_priv-mm.aliasing_ppgtt;
+ uint32_t __iomem *pd_addr;
+ uint32_t pd_entry;
+ int i;
+
+ if (!dev_priv-mm.aliasing_ppgtt)
+ return;
+
+
+ pd_addr = dev_priv-mm.gtt-gtt + ppgtt-pd_offset/sizeof(uint32_t);
+ for (i = 0; i ppgtt-num_pd_entries; i++) {
+ dma_addr_t pt_addr;
+
+ if (dev_priv-mm.gtt-needs_dmar)
+ pt_addr = ppgtt-pt_dma_addr[i];
+ else
+ pt_addr = page_to_phys(ppgtt-pt_pages[i]);
+
+
Re: [Intel-gfx] [PATCH 00/10] shrink dev_priv by 300 lines
On Fri, 2 Nov 2012 19:55:01 +0100 Daniel Vetter daniel.vet...@ffwll.ch wrote: Hi all, Inspired by some recent patches I've figured I need to clean up and put some organization behind our driver_private struct. It shrunk from almost 500 lines to about 160. Things still there which could be gathered: - vbt and vbt-derived values - shared/global modeset state - random smaller bits and pieces Comments highly welcome. Cheers, Daniel This is in reference to all your extraction of substructs ie. the l3 parity... This really seems like moving around code mostly for the sake of moving around code (note that I said mostly). What I would have liked to see as a motivation/result of this is instead of passing dev_priv around all over the place, pass around the new extracted structures. If you still need dev_priv (for something other than reg reads or writes), then I don't think you've done anything useful. Changing the function prototypes to the new substructs would be a provably useful thing to do. Daniel Vetter (10): drm/i915: move the suspend/resume register file out of dev_priv drm/i915: move dev_priv-(rps|ips) out of line drm/i915: move pwrctx/renderctx to the other ilk power state drm/i915: move dri1 dungeon out of dev_priv drm/i915: extract dev_priv fbc state into separate substruct drm/i915: extract l3_parity substruct from dev_priv drm/i915: move dev_priv-mm out of line drm/i915: extract hangcheck/reset/error_state state into substruct drm/i915: kill dev_priv-modeset_on_lid drm/i915: move fence_regs to the fence lru drivers/gpu/drm/i915/i915_debugfs.c | 32 +- drivers/gpu/drm/i915/i915_dma.c | 43 +- drivers/gpu/drm/i915/i915_drv.c | 15 +- drivers/gpu/drm/i915/i915_drv.h | 608 ++-- drivers/gpu/drm/i915/i915_gem.c | 42 +- drivers/gpu/drm/i915/i915_gem_stolen.c | 14 +- drivers/gpu/drm/i915/i915_irq.c | 62 +-- drivers/gpu/drm/i915/i915_suspend.c | 692 drivers/gpu/drm/i915/i915_sysfs.c | 6 +- drivers/gpu/drm/i915/intel_display.c| 6 +- drivers/gpu/drm/i915/intel_lvds.c | 40 -- drivers/gpu/drm/i915/intel_panel.c | 20 +- drivers/gpu/drm/i915/intel_pm.c | 80 ++-- drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +- 14 files changed, 823 insertions(+), 839 deletions(-) -- Ben Widawsky, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 00/10] shrink dev_priv by 300 lines
On Sun, Nov 4, 2012 at 6:30 PM, Ben Widawsky b...@bwidawsk.net wrote: Inspired by some recent patches I've figured I need to clean up and put some organization behind our driver_private struct. It shrunk from almost 500 lines to about 160. Things still there which could be gathered: - vbt and vbt-derived values - shared/global modeset state - random smaller bits and pieces Comments highly welcome. This is in reference to all your extraction of substructs ie. the l3 parity... This really seems like moving around code mostly for the sake of moving around code (note that I said mostly). What I would have liked to see as a motivation/result of this is instead of passing dev_priv around all over the place, pass around the new extracted structures. If you still need dev_priv (for something other than reg reads or writes), then I don't think you've done anything useful. Changing the function prototypes to the new substructs would be a provably useful thing to do. I've played around with passing the substructs to functions that handle individual parts and notice that pretty much everywhere we need dev_priv to handle reg I/O. So I've decided to keep things as-is to avoid inconsistency (we already have that mess in the modeset code with drm_* vs. intel_* ...). Otoh if that move register blocks around thing becomes more prevalent on vlv, we might want to switch to passing substructs around, and also adding per-block reg I/O variants which implicitly take the substruct and add the required mmio_base offset. But even without that I very much like the new order in i915_dev_private. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915: don't block resume on fb console resume
Dear Jesse, unfortunately due to mail problems with SourceForge I did not get the latest series. Do you have a public repository with these patches in it? Am Mittwoch, den 31.10.2012, 15:41 -0700 schrieb Jesse Barnes: The console lock can be contended, so rather than prevent other drivers after us from being held up, queue the console suspend into the global work queue that can happen anytime. I've measured this to take around 200ms on my T420. Combined with the ring freq/turbo change, we should save almost 1/2 a second on resume. In #intel-gfx on irc.freenode.net, Daniel told me that this is mostly true for Sandybridge. Could you clarify that in the commit message please. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org […] Thanks, Paul signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 5/5] drm/i915: Move the remaining gtt code
On Sun, Nov 04, 2012 at 09:21:31AM -0800, Ben Widawsky wrote: It's pretty much all consolidated now that we've killed AGP. We can move the one outlier, and defines too. (Kill some unused defines in the process) Signed-off-by: Ben Widawsky b...@bwidawsk.net Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk Entire series merged, with Chris' irc r-b added for patch 3. Thanks, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/4] drm/i915: don't block resume on fb console resume
On Sun, 04 Nov 2012 22:16:39 +0100 Paul Menzel paulepan...@users.sourceforge.net wrote: Dear Jesse, unfortunately due to mail problems with SourceForge I did not get the latest series. No I haven't pushed an updated version anywhere, but I think Daniel has them queued now? Do you have a public repository with these patches in it? Am Mittwoch, den 31.10.2012, 15:41 -0700 schrieb Jesse Barnes: The console lock can be contended, so rather than prevent other drivers after us from being held up, queue the console suspend into the global work queue that can happen anytime. I've measured this to take around 200ms on my T420. Combined with the ring freq/turbo change, we should save almost 1/2 a second on resume. In #intel-gfx on irc.freenode.net, Daniel told me that this is mostly true for Sandybridge. Could you clarify that in the commit message please. The fb resume and GTT rewrite patches will benefit every Intel gfx platform. The work queue for ring freq updates will benefit SNB+. Jesse ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
