Re: [Intel-gfx] [PATCH] drm/i915: Clarify HW context size logic
On Thu, Feb 07, 2013 at 01:34:19PM -0800, Ben Widawsky wrote: This was a rebase error from when the patches originally landed. Since the context size is unsigned, there is also no use in checking if it's less than 0. The existing code is not really wrong, but it's not simple as it should be. Signed-off-by: Ben Widawsky b...@bwidawsk.net Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ERROR: pm_vt_switch_unregister [drivers/video/fb.ko] undefined!
On Fri, Feb 8, 2013 at 10:30 AM, kbuild test robot fengguang...@intel.com wrote: tree: git://people.freedesktop.org/~danvet/drm-intel.git drm-intel-nightly head: 69f0d09dfd2d0579241389aee18ba50aa39d0de2 commit: d6bc5b0603e5bea1b5a214d21c0aba8518f1a01f fb: add support for drivers not needing VT switch at suspend/resume time date: 2 days ago config: i386-randconfig-b031 (attached as .config) All error/warnings: ERROR: pm_vt_switch_unregister [drivers/video/fb.ko] undefined! ERROR: pm_vt_switch_required [drivers/video/fb.ko] undefined! I guess there's a select CONFIG_VT_CONSOLE_SLEEP missing somewhere ... Or at least a few stubs in headers if that's not selected. The offending config option itself was created itself to fix compile fail: commit 37cce26b32142f09a8967f6d238178af654b20de Author: H Hartley Sweeten hartl...@visionengravers.com Date: Wed Sep 21 22:47:55 2011 +0200 PM / VT: Cleanup #if defined uglyness and fix compile error Jesse, Rafael? -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [RFC] [PATCH 0/7] arb robustness enablers
On Mon, Feb 04, 2013 at 04:04:36PM +0200, Mika Kuoppala wrote: Hi, This patchset adds ioctl and related changes to allow userspace to query about the context loss status of the specified context. The aim is to provide enabler for the ARB_Robustness GL extension. I post this as RFC to get ack/nack on the interface. The interface is in 0004-drm-i915-add-i915_get_reset_status_ioctl.patch Also any feedback on the other parts of the patchset is most welcomed. The i-g-t testcase can be found here: https://github.com/mkuoppal/intel-gpu-tools/commits/arb-robustness Ok, I've only quickly scrolled through this but it looks rather sane, and the interface seems to be a fit for arb robustness. So tentative ack on the ioctl ;-) A few comments: The first patch imo makes sense conceptually, even though it's not required to implement the ioctl (only the test). This needs critical review from Chris though since he's really picky about the hangcheck misfiring or not detecting hangs. Might be that we also have some races left which have been papered over by the acthd checks ... Best to split this out for maximum scrunity. For the remaining stuff, I see three pieces: - refcounts for hw contexts: Imo this is rather independent and should go in early. If it doesn't apply without the other I think we should move it ahead in a rebase. - Infrastructure to figure out whom to blame for a hang. One thing I'd really love to see on top of your patches is adjusting the hanging too fast detection to only disable command execution for the offending fd and not kill the entire gpu unnecessarily. This should help a lot already today, without any userspace support. I think it'd be also good to have an i-g-t test for this which tries to hang the gpu with the hangman on e.g. the blit constantly until the gpu dies. And then open a new fd to check whether things still work. - Putting that blame to the right hw contexts and exposing it through the ioctl. Usual interface rules applies: We need to have userspace support more or less ready before merging, i.e. a rough cut at the robustness extension patches for mesa. Probably best if you can do this in collaboration with one of the gl guys in Helsinki. Cheers, Daniel Thanks, --Mika Mika Kuoppala (7): drm/i915: detect infinite loops in hang check drm/i915: add struct i915_reset_stats drm/i915: add reset_status for hw_contexts drm/i915: add i915_get_reset_status_ioctl drm/i915: add batch object and context to i915_add_request() drm/i915: reference count for i915_hw_contexts drm/i915: find guilty batch buffer on ring resets drivers/gpu/drm/i915/i915_dma.c|3 +- drivers/gpu/drm/i915/i915_drv.c| 42 + drivers/gpu/drm/i915/i915_drv.h| 41 +++-- drivers/gpu/drm/i915/i915_gem.c| 119 -- drivers/gpu/drm/i915/i915_gem_context.c| 66 +-- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 11 ++- drivers/gpu/drm/i915/i915_irq.c| 127 ++-- drivers/gpu/drm/i915/intel_overlay.c |5 +- drivers/gpu/drm/i915/intel_ringbuffer.c|2 +- drivers/gpu/drm/i915/intel_ringbuffer.h|4 + include/uapi/drm/i915_drm.h| 19 + 11 files changed, 351 insertions(+), 88 deletions(-) -- 1.7.9.5 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] Build: Add --disable-tests configure flag to avoid tests build.
Apparently Cairo wasn't the main reason, beucase something at /libs depends on Cairo as well. So cairo dependencie wasn't removed from checks. But now on, when including any dependencies used only for tests please add pkg_check_modules only if tests build enalbed. On Thu, Feb 7, 2013 at 8:40 PM, Ben Widawsky b...@bwidawsk.net wrote: On Thu, Feb 07, 2013 at 09:52:32PM +, Damien Lespiau wrote: On Mon, Feb 04, 2013 at 07:52:27PM -0200, Rodrigo Vivi wrote: Tests are still being built by default. However this request came from OSVs in order to allow them to include i-g-t in their distributions by default avoiding adding more and more dependencies since we are improving and adding more and more tests. Sorry to be the party crasher here, but the patch doesn't seem to really remove dependencies because the default action-if-not-found of PKG_CHECK_MODULES will end the configure script. For instance PKG_CHECK_MODULES(CAIRO, [cairo]) will end the configure script if cairo is not found. What are the goals here? remove dependencies? which ones? Hopefully not too wrong with that stupid FOSDEM flu :) -- Damien Takashi asked for it, and reviewed it, so http://en.wikipedia.org/wiki/Ostrich_algorithm? -- Ben Widawsky, Intel Open Source Technology Center -- Rodrigo Vivi Blog: http://blog.vivi.eng.br ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/2] drm/i915: disable shared panel fitter for pipe
If encoder is switched off by BIOS, but the panel fitter is left on,
we never try to turn off the panel fitter and leave it still attached
to the pipe - which can cause blurry output elsewhere.
Based on work by Chris Wilson ch...@chris-wilson.co.uk
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58867
Cc: sta...@vger.kernel.org
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d75c6a0..9b5f0fb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3656,6 +3656,15 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
intel_disable_plane(dev_priv, plane, pipe);
intel_disable_pipe(dev_priv, pipe);
+
+ if (!HAS_PCH_SPLIT(dev)) {
+ const u32 pctl = I915_READ(PFIT_CONTROL);
+
+ if ((pctl PFIT_ENABLE)
+ ((pctl PFIT_PIPE_MASK) PFIT_PIPE_SHIFT) == pipe)
+ I915_WRITE(PFIT_CONTROL, 0);
+ }
+
intel_disable_pll(dev_priv, pipe);
intel_crtc-active = false;
--
1.7.9.5
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[Intel-gfx] [PATCH 2/2] drm/i915: clean up panel fitter handling in lvds
commit c1d1f5aeda2033d96e872f416388653f05d4c16d
Author: Mika Kuoppala mika.kuopp...@intel.com
Date: Tue Feb 5 17:26:52 2013 +0200
drm/i915: disable shared panel fitter for pipe
moved panel fit disabling to be crtc property. Thus
the need to explicitly turn pfit off in encoder side
became obsolete. Take advantage of that and get rid of
pfit_dirty state handling in lvds.
Signed-off-by: Mika Kuoppala mika.kuopp...@intel.com
---
drivers/gpu/drm/i915/intel_display.c |5
drivers/gpu/drm/i915/intel_lvds.c| 47 +-
2 files changed, 29 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 9b5f0fb..175538d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3615,6 +3615,11 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
intel_update_watermarks(dev);
intel_enable_pll(dev_priv, pipe);
+
+ for_each_encoder_on_crtc(dev, crtc, encoder)
+ if (encoder-pre_enable)
+ encoder-pre_enable(encoder);
+
intel_enable_pipe(dev_priv, pipe, false);
intel_enable_plane(dev_priv, plane, pipe);
diff --git a/drivers/gpu/drm/i915/intel_lvds.c
b/drivers/gpu/drm/i915/intel_lvds.c
index 7e4ec63..f93058a 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -51,7 +51,6 @@ struct intel_lvds_encoder {
u32 pfit_control;
u32 pfit_pgm_ratios;
- bool pfit_dirty;
bool is_dual_link;
u32 reg;
@@ -151,6 +150,29 @@ static void intel_pre_pll_enable_lvds(struct intel_encoder
*encoder)
I915_WRITE(lvds_encoder-reg, temp);
}
+static void intel_pre_enable_lvds(struct intel_encoder *encoder)
+{
+ struct drm_device *dev = encoder-base.dev;
+ struct intel_lvds_encoder *enc = to_lvds_encoder(encoder-base);
+ struct drm_i915_private *dev_priv = dev-dev_private;
+
+ if (HAS_PCH_SPLIT(dev) || !enc-pfit_control)
+ return;
+
+ /*
+* Enable automatic panel scaling so that non-native modes
+* fill the screen. The panel fitter should only be
+* adjusted whilst the pipe is disabled, according to
+* register description and PRM.
+*/
+ DRM_DEBUG_KMS(applying panel-fitter: %x, %x\n,
+ enc-pfit_control,
+ enc-pfit_pgm_ratios);
+
+ I915_WRITE(PFIT_PGM_RATIOS, enc-pfit_pgm_ratios);
+ I915_WRITE(PFIT_CONTROL, enc-pfit_control);
+}
+
/**
* Sets the power state for the panel.
*/
@@ -172,22 +194,6 @@ static void intel_enable_lvds(struct intel_encoder
*encoder)
I915_WRITE(lvds_encoder-reg, I915_READ(lvds_encoder-reg) |
LVDS_PORT_EN);
- if (lvds_encoder-pfit_dirty) {
- /*
-* Enable automatic panel scaling so that non-native modes
-* fill the screen. The panel fitter should only be
-* adjusted whilst the pipe is disabled, according to
-* register description and PRM.
-*/
- DRM_DEBUG_KMS(applying panel-fitter: %x, %x\n,
- lvds_encoder-pfit_control,
- lvds_encoder-pfit_pgm_ratios);
-
- I915_WRITE(PFIT_PGM_RATIOS, lvds_encoder-pfit_pgm_ratios);
- I915_WRITE(PFIT_CONTROL, lvds_encoder-pfit_control);
- lvds_encoder-pfit_dirty = false;
- }
-
I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
POSTING_READ(lvds_encoder-reg);
if (wait_for((I915_READ(stat_reg) PP_ON) != 0, 1000))
@@ -217,11 +223,6 @@ static void intel_disable_lvds(struct intel_encoder
*encoder)
if (wait_for((I915_READ(stat_reg) PP_ON) == 0, 1000))
DRM_ERROR(timed out waiting for panel to power off\n);
- if (lvds_encoder-pfit_control) {
- I915_WRITE(PFIT_CONTROL, 0);
- lvds_encoder-pfit_dirty = true;
- }
-
I915_WRITE(lvds_encoder-reg, I915_READ(lvds_encoder-reg)
~LVDS_PORT_EN);
POSTING_READ(lvds_encoder-reg);
}
@@ -461,7 +462,6 @@ out:
pfit_pgm_ratios != lvds_encoder-pfit_pgm_ratios) {
lvds_encoder-pfit_control = pfit_control;
lvds_encoder-pfit_pgm_ratios = pfit_pgm_ratios;
- lvds_encoder-pfit_dirty = true;
}
dev_priv-lvds_border_bits = border;
@@ -1109,6 +1109,7 @@ bool intel_lvds_init(struct drm_device *dev)
DRM_MODE_ENCODER_LVDS);
intel_encoder-enable = intel_enable_lvds;
+ intel_encoder-pre_enable = intel_pre_enable_lvds;
intel_encoder-pre_pll_enable = intel_pre_pll_enable_lvds;
intel_encoder-disable = intel_disable_lvds;
intel_encoder-get_hw_state = intel_lvds_get_hw_state;
--
1.7.9.5
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Re: [Intel-gfx] [PATCH 01/12] configure.ac: slightly more standard --disable-tests
Dear Ben, Am Donnerstag, den 07.02.2013, 10:39 -0800 schrieb Ben Widawsky: This partially reverts missing empty line for better legibility. commit 7c170724003f42cd4ceea9f6c805292bbe2e81b2 Author: Rodrigo Vivi rodrigo.v...@gmail.com Date: Tue Feb 5 16:17:54 2013 -0200 Build: Add --disable-tests configure flag to avoid tests build I was still in the middle of arguing this when Daniel merged it. Could you please explain your change? Why is it »sligthly more standard«? Cc: Rodrigo Vivi rodrigo.v...@gmail.com Cc: Daniel Vetter daniel.vet...@ffwll.ch Cc: Julien Cristau jcris...@debian.org Signed-off-by: Ben Widawsky b...@bwidawsk.net Thanks, Paul signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] ERROR: pm_vt_switch_unregister [drivers/video/fb.ko] undefined!
On Fri, 8 Feb 2013 10:51:48 +0100 Daniel Vetter daniel.vet...@ffwll.ch wrote: On Fri, Feb 8, 2013 at 10:30 AM, kbuild test robot fengguang...@intel.com wrote: tree: git://people.freedesktop.org/~danvet/drm-intel.git drm-intel-nightly head: 69f0d09dfd2d0579241389aee18ba50aa39d0de2 commit: d6bc5b0603e5bea1b5a214d21c0aba8518f1a01f fb: add support for drivers not needing VT switch at suspend/resume time date: 2 days ago config: i386-randconfig-b031 (attached as .config) All error/warnings: ERROR: pm_vt_switch_unregister [drivers/video/fb.ko] undefined! ERROR: pm_vt_switch_required [drivers/video/fb.ko] undefined! I guess there's a select CONFIG_VT_CONSOLE_SLEEP missing somewhere ... Or at least a few stubs in headers if that's not selected. The offending config option itself was created itself to fix compile fail: commit 37cce26b32142f09a8967f6d238178af654b20de Author: H Hartley Sweeten hartl...@visionengravers.com Date: Wed Sep 21 22:47:55 2011 +0200 PM / VT: Cleanup #if defined uglyness and fix compile error Jesse, Rafael? Not sure... are there configs where power/console.c might be omitted or the whole file #ifdef'd out? -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 02/12] configure.ac: Move prime stuff to where it belongs
Am Donnerstag, den 07.02.2013, 10:39 -0800 schrieb Ben Widawsky: So where does it belong? Signed-off-by: Ben Widawsky b...@bwidawsk.net […] Thanks, Paul signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Extract ring init from hw_init
The ring initialization will differ a bit in upcoming generations, and
this split will prepare the code for what's needed.
This patch also fixes a bug introduced in:
commit 99433931950f33039d9e1a52b4ed9af3f1b58e84
Author: Mika Kuoppala mika.kuopp...@linux.intel.com
Date: Tue Jan 22 14:12:17 2013 +0200
drm/i915: use gem_set_seqno() on hardware init
After doing the extraction, the bad error handling became obvious. I
acknowledge that this should be two patches, but it's a pretty
small/trivial patch. If requested, I can certainly do the fix as a
distinct patch.
Cc: Mika Kuoppala mika.kuopp...@linux.intel.com
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem.c | 53 ++---
1 file changed, 34 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d746177..82cc23e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3922,22 +3922,11 @@ intel_enable_blt(struct drm_device *dev)
return true;
}
-int
-i915_gem_init_hw(struct drm_device *dev)
+static int i915_gem_init_rings(struct drm_device *dev)
{
- drm_i915_private_t *dev_priv = dev-dev_private;
+ struct drm_i915_private *dev_priv = dev-dev_private;
int ret;
- if (INTEL_INFO(dev)-gen 6 !intel_enable_gtt())
- return -EIO;
-
- if (IS_HASWELL(dev) (I915_READ(0x120010) == 1))
- I915_WRITE(0x9008, I915_READ(0x9008) | 0xf);
-
- i915_gem_l3_remap(dev);
-
- i915_gem_init_swizzling(dev);
-
ret = intel_init_render_ring_buffer(dev);
if (ret)
return ret;
@@ -3956,6 +3945,38 @@ i915_gem_init_hw(struct drm_device *dev)
ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
if (ret)
+ goto cleanup_blt_ring;
+
+ return 0;
+
+cleanup_blt_ring:
+ intel_init_blt_ring_buffer(dev_priv-ring[BCS]);
+cleanup_bsd_ring:
+ intel_cleanup_ring_buffer(dev_priv-ring[VCS]);
+cleanup_render_ring:
+ intel_cleanup_ring_buffer(dev_priv-ring[RCS]);
+
+ return ret;
+}
+
+int
+i915_gem_init_hw(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = dev-dev_private;
+ int ret;
+
+ if (INTEL_INFO(dev)-gen 6 !intel_enable_gtt())
+ return -EIO;
+
+ if (IS_HASWELL(dev) (I915_READ(0x120010) == 1))
+ I915_WRITE(0x9008, I915_READ(0x9008) | 0xf);
+
+ i915_gem_l3_remap(dev);
+
+ i915_gem_init_swizzling(dev);
+
+ ret = i915_gem_init_rings(dev);
+ if (ret)
return ret;
/*
@@ -3966,12 +3987,6 @@ i915_gem_init_hw(struct drm_device *dev)
i915_gem_init_ppgtt(dev);
return 0;
-
-cleanup_bsd_ring:
- intel_cleanup_ring_buffer(dev_priv-ring[VCS]);
-cleanup_render_ring:
- intel_cleanup_ring_buffer(dev_priv-ring[RCS]);
- return ret;
}
int i915_gem_init(struct drm_device *dev)
--
1.8.1.2
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Re: [Intel-gfx] [PATCH 7/7] drm/i915: print Gen 7 error interrupts
Hi
2013/1/25 Ben Widawsky b...@bwidawsk.net:
On Fri, 25 Jan 2013 18:57:42 -0200
Paulo Zanoni przan...@gmail.com wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
If we get one of these messages it means we did something wrong, and
the first step to fix wrong things is to detect them and recognize
they exist.
For now, leave most messages as DRM_DEBUG_KMS. After we conclude that
a certain message should not be print since our code is correct, then
we can promote that specific message to DRM_ERROR.
Also notice that on Haswell the only interrupt I ever get is for
unclaimed registers, so it looks like at least on Haswell we're in a
good shape.
Please take some of my cynicism, you are way too optimistic :p
The new patch won't just print everything.
I have a lot of concerns with this patch touch FPGA_DEBUG and races.
Please explain.
Third, I think to be super paranoid you might want to disable the ERR_INT
while
handling interrupts.
Yes, we need to mask ERR_INT inside ivybridge_irq_handler, otherwise
we may get an infinite loop in case we write to an unclaimed register
inside the irq handler. This will be fixed in the next version. The
good thing is that even if ERR_INT is masked, we can still detect
unclaimed registers inside the irq handler because we still check
FPGA_DBG (which doesn't give us interrputs) :)
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 28 +++-
drivers/gpu/drm/i915/i915_reg.h |2 +-
2 files changed, 28 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c
b/drivers/gpu/drm/i915/i915_irq.c
index 943db10..c2136cd 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -697,6 +697,17 @@ static void cpt_irq_handler(struct drm_device *dev, u32
pch_iir)
I915_READ(FDI_RX_IIR(pipe)));
}
+static void ivb_err_int_handler(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
+ u32 err_int = I915_READ(GEN7_ERR_INT);
+
+ if (err_int)
+ DRM_DEBUG_KMS(Error interrupt: 0x%08x\n, err_int);
+
+ I915_WRITE(GEN7_ERR_INT, err_int);
+}
+
static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
{
struct drm_device *dev = (struct drm_device *) arg;
@@ -707,6 +718,14 @@ static irqreturn_t ivybridge_irq_handler(int irq, void
*arg)
atomic_inc(dev_priv-irq_received);
+ /* We get interrupts on unclaimed registers, so check this before we do
+ * any I915_{READ,WRITE}. */
+ if (drm_debug IS_HASWELL(dev)
+ (I915_READ_NOTRACE(FPGA_DBG) FPGA_DBG_RM_NOCLAIM)) {
+ DRM_ERROR(Unclaimed register before interrupt\n);
+ I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+ }
+
/* disable master interrupt before clearing iir */
de_ier = I915_READ(DEIER);
I915_WRITE(DEIER, de_ier ~DE_MASTER_IRQ_CONTROL);
I don't really understand what you're trying to do with this, and I
think this is quite racy since you're usually protecting FPGA_DBG with
struct_mutex, but not here. Since it's mostly for debug, maybe you can
convince me why it should be here, and I'll drop my complaint.
On i915_write##x we do:
1 - writel(reg_that_doesnt_exist)
2 - read FPGA_DBG
3 - print error message
4 - clear FPGA_DBG
The problem is that sometimes we get the interrupt between steps 1 and
2, or 2 and 3, or 3 and 4. And since the interrupt handler also does
I915_WRITE, we may do the FPGA_DBG check inside the IRQ handler
before the original i915_WRITE check because the interrupt arrived
too fast.
@@ -720,6 +739,9 @@ static irqreturn_t ivybridge_irq_handler(int irq, void
*arg)
de_iir = I915_READ(DEIIR);
if (de_iir) {
+ if (de_iir DE_ERR_INT_IVB)
+ ivb_err_int_handler(dev);
+
if (de_iir DE_AUX_CHANNEL_A_IVB)
dp_aux_irq_handler(dev);
@@ -2006,7 +2028,8 @@ static int ivybridge_irq_postinstall(struct drm_device
*dev)
DE_PLANEC_FLIP_DONE_IVB |
DE_PLANEB_FLIP_DONE_IVB |
DE_PLANEA_FLIP_DONE_IVB |
- DE_AUX_CHANNEL_A_IVB;
+ DE_AUX_CHANNEL_A_IVB |
+ DE_ERR_INT_IVB;
u32 render_irqs;
u32 hotplug_mask;
u32 pch_irq_mask;
@@ -2014,6 +2037,7 @@ static int ivybridge_irq_postinstall(struct drm_device
*dev)
dev_priv-irq_mask = ~display_mask;
/* should always can generate irq */
+ I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
I915_WRITE(DEIIR, I915_READ(DEIIR));
I915_WRITE(DEIMR, dev_priv-irq_mask);
I915_WRITE(DEIER,
@@ -2177,6 +2201,8 @@ static void ironlake_irq_uninstall(struct drm_device
*dev)
I915_WRITE(DEIMR, 0x);
I915_WRITE(DEIER, 0x0);
I915_WRITE(DEIIR, I915_READ(DEIIR));
+ if
[Intel-gfx] [PATCH] drm/i915: Fix gen2 mappable calculations
When I refactored the code initially, I forgot that gen2 uses a
different bar for the CPU mappable aperture. The agp-less code knows
nothing of generations less than 5, so we have to expand the gtt_probe
function to include the mappable base and end.
It was originally broken by me:
commit baa09f5fd8a6d033ec075355dda99a65b7f6a0f3
Author: Ben Widawsky b...@bwidawsk.net
Date: Thu Jan 24 13:49:57 2013 -0800
drm/i915: Add probe and remove to the gtt ops
Reported-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/char/agp/intel-gtt.c| 5 -
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/i915_gem_gtt.c | 23 ++-
include/drm/intel-gtt.h | 3 ++-
4 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index d8e7e6c..207e5c3 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1371,10 +1371,13 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev,
struct pci_dev *gpu_pdev,
}
EXPORT_SYMBOL(intel_gmch_probe);
-void intel_gtt_get(size_t *gtt_total, size_t *stolen_size)
+void intel_gtt_get(size_t *gtt_total, size_t *stolen_size,
+ phys_addr_t *mappable_base, unsigned long *mappable_end)
{
*gtt_total = intel_private.gtt_total_entries PAGE_SHIFT;
*stolen_size = intel_private.stolen_size;
+ *mappable_base = intel_private.gma_bus_addr;
+ *mappable_end = intel_private.gtt_mappable_entries PAGE_SHIFT;
}
EXPORT_SYMBOL(intel_gtt_get);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 984523d..254ad66 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -396,7 +396,8 @@ struct i915_gtt {
/* global gtt ops */
int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
- size_t *stolen);
+ size_t *stolen, phys_addr_t *mappable_base,
+ unsigned long *mappable_end);
void (*gtt_remove)(struct drm_device *dev);
void (*gtt_clear_range)(struct drm_device *dev,
unsigned int first_entry,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index bdaca3f..926a1e2 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -725,7 +725,9 @@ static inline size_t gen7_get_stolen_size(u16 snb_gmch_ctl)
static int gen6_gmch_probe(struct drm_device *dev,
size_t *gtt_total,
- size_t *stolen)
+ size_t *stolen,
+ phys_addr_t *mappable_base,
+ unsigned long *mappable_end)
{
struct drm_i915_private *dev_priv = dev-dev_private;
phys_addr_t gtt_bus_addr;
@@ -733,11 +735,13 @@ static int gen6_gmch_probe(struct drm_device *dev,
u16 snb_gmch_ctl;
int ret;
+ *mappable_base = pci_resource_start(dev-pdev, 2);
+ *mappable_end = pci_resource_len(dev-pdev, 2);
+
/* 64/512MB is the current min/max we actually know of, but this is just
* a coarse sanity check.
*/
- if ((dev_priv-gtt.mappable_end (6420) ||
-(dev_priv-gtt.mappable_end (51220 {
+ if ((*mappable_end (6420) || (*mappable_end (51220 {
DRM_ERROR(Unknown GMADR size (%lx)\n,
dev_priv-gtt.mappable_end);
return -ENXIO;
@@ -782,7 +786,9 @@ static void gen6_gmch_remove(struct drm_device *dev)
static int i915_gmch_probe(struct drm_device *dev,
size_t *gtt_total,
- size_t *stolen)
+ size_t *stolen,
+ phys_addr_t *mappable_base,
+ unsigned long *mappable_end)
{
struct drm_i915_private *dev_priv = dev-dev_private;
int ret;
@@ -793,7 +799,7 @@ static int i915_gmch_probe(struct drm_device *dev,
return -EIO;
}
- intel_gtt_get(gtt_total, stolen);
+ intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
dev_priv-gtt.do_idle_maps = needs_idle_maps(dev_priv-dev);
dev_priv-gtt.gtt_clear_range = i915_ggtt_clear_range;
@@ -814,9 +820,6 @@ int i915_gem_gtt_init(struct drm_device *dev)
unsigned long gtt_size;
int ret;
- gtt-mappable_base = pci_resource_start(dev-pdev, 2);
- gtt-mappable_end = pci_resource_len(dev-pdev, 2);
-
if (INTEL_INFO(dev)-gen = 5) {
dev_priv-gtt.gtt_probe = i915_gmch_probe;
dev_priv-gtt.gtt_remove = i915_gmch_remove;
@@ -826,7 +829,9 @@ int i915_gem_gtt_init(struct drm_device *dev)
}
ret = dev_priv-gtt.gtt_probe(dev, dev_priv-gtt.total,
-
[Intel-gfx] [PATCH intel-gpu-tools 1/2] Put -I m4 in ACLOCAL_AMFLAGS so ./autogen.sh just works
---
Makefile.am |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/Makefile.am b/Makefile.am
index 0dd615b..20bca79 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -19,7 +19,7 @@
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-ACLOCAL_AMFLAGS = ${ACLOCAL_FLAGS}
+ACLOCAL_AMFLAGS = ${ACLOCAL_FLAGS} -I m4
SUBDIRS = lib man tools scripts benchmarks demos
--
1.7.8.6
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[Intel-gfx] [PATCH intel-gpu-tools 2/2] quick_dump: Makefile.am best practices and fix distcheck
A few changes - Put CPPFLAGS in AM_CPPFLAGS instead of a per-target CFLAGS var; - Use _LIBS/_CFLAGS from pkg-config instead of hard-coded values; - List non-generated scripts in dist_bin_SCRIPTS; - Add chipset.py to the run that implicitly generates it, which fixes distcheck. --- tools/quick_dump/Makefile.am | 10 ++ 1 files changed, 6 insertions(+), 4 deletions(-) diff --git a/tools/quick_dump/Makefile.am b/tools/quick_dump/Makefile.am index e89a115..42ab140 100644 --- a/tools/quick_dump/Makefile.am +++ b/tools/quick_dump/Makefile.am @@ -1,17 +1,19 @@ +AM_CPPFLAGS = -I$(top_srcdir)/lib $(PYTHON_CPPFLAGS) $(DRM_CFLAGS) + BUILT_SOURCES = chipset_wrap_python.c -bin_SCRIPTS = quick_dump.py chipset.py reg_access.py +dist_bin_SCRIPTS = quick_dump.py reg_access.py +bin_SCRIPTS = chipset.py lib_LTLIBRARIES = I915ChipsetPython.la -I915ChipsetPython_la_CFLAGS = -I$(top_srcdir)/lib $(PYTHON_CPPFLAGS) $(CFLAGS) -I/usr/include/libdrm/ -I915ChipsetPython_la_LDFLAGS = -module -avoid-version $(PYTHON_LDFLAGS) -lpciaccess +I915ChipsetPython_la_LDFLAGS = -module -avoid-version $(PYTHON_LDFLAGS) $(PCIACCESS_LIBS) I915ChipsetPython_la_SOURCES = chipset_wrap_python.c intel_chipset.c \ $(top_srcdir)/lib/intel_drm.c \ $(top_srcdir)/lib/intel_pci.c \ $(top_srcdir)/lib/intel_reg_map.c \ $(top_srcdir)/lib/intel_mmio.c -chipset_wrap_python.c: chipset.i +chipset_wrap_python.c chipset.py: chipset.i $(SWIG) $(AX_SWIG_PYTHON_OPT) -I/usr/include -I$(top_srcdir)/lib -o $@ $ all-local: I915ChipsetPython.la -- 1.7.8.6 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 00/10] Display error reporting
From: Paulo Zanoni paulo.r.zan...@intel.com Hi This series is the first step to improve error reporting on our driver. The first 3 patches were already sent to the list and they're a requirement for the series (because of the relationship between our unclaimed register checks and the display error interrupts). Patch 4 just removes some code duplication and could be merged before everything else. Patches 5-7 are the complicated bits. They use the I want to report Poison interrupts excuse, but the main goal of these 3 patches is: make sure our code is prepared for a possible interrupt tsunami, enable SERR_INT and enable GEN7_ERR_INT. The big problem with GEN7_ERR_INT and SERR_INT is that you can't enable/disable the specific sub-cases of this interrupt: either you enable all of the error interrupts or you disable all of them. Patches 8 and 9 are mainly about printing error messages. They try to make sure dmesg won't be flooded in case the interrupt tsunami happens, but they still leave GEN7_ERR_INT and SERR_INT enabled even if we decide to ignore some of the interrupts, because this way we may detect one problem even if the other is being ignored. Patch 10 is just for my OCD. After this series, enabling and printing more error interrupts will be easier. So far, I tested this series on ILK, SNB and HSW and I haven't seen the Poison interrupt message, but I have seen the PCH transcoder FIFO underrun message on SNB and ILK, and this seems to be caused by wrong watermark values when using multiple pipes. Future patches will fix the problems reported by the error messages. I hope these error messages will help us identify, reproduce and fix bugs in our driver. Thanks, Paulo Paulo Zanoni (10): drm/i915: drm/i915: create macros for the unclaimed register checks drm/i915: use FPGA_DBG for the unclaimed register checks drm/i915: clear the FPGA_DBG_RM_NOCLAIM bit at driver init drm/i915: add ibx_irq_postinstall drm/i915: also disable south interrupts when handling them drm/i915: print PCH poison interrupts drm/i915: print Gen5+ CPU poison interrupts drm/i915: print PCH FIFO underrun interrupts drm/i915: print CPU FIFO underruns drm/i915: also POSTING_READ(DEIER) on ivybridge_irq_handler drivers/gpu/drm/i915/i915_dma.c |4 + drivers/gpu/drm/i915/i915_drv.c | 24 ++-- drivers/gpu/drm/i915/i915_drv.h |5 + drivers/gpu/drm/i915/i915_irq.c | 217 ++ drivers/gpu/drm/i915/i915_reg.h | 18 ++- drivers/gpu/drm/i915/intel_display.c | 16 ++- 6 files changed, 223 insertions(+), 61 deletions(-) -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 01/10] drm/i915: drm/i915: create macros for the unclaimed register checks
From: Paulo Zanoni paulo.r.zan...@intel.com
This avoids polluting i915_write##x and also allows us to reuse code
on i915_read##x.
v2: Rebase
Reviewed-by: Ben Widawsky b...@bwidawsk.net (v1)
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index c5b8c81..e24c337 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1131,6 +1131,20 @@ ilk_dummy_write(struct drm_i915_private *dev_priv)
I915_WRITE_NOTRACE(MI_MODE, 0);
}
+#define UNCLAIMED_REG_CLEAR(dev_priv, reg) \
+ if (IS_HASWELL(dev_priv-dev) \
+ (I915_READ_NOTRACE(GEN7_ERR_INT) ERR_INT_MMIO_UNCLAIMED)) { \
+ DRM_ERROR(Unknown unclaimed register before writing to %x\n,
reg); \
+ I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
+ }
+
+#define UNCLAIMED_REG_CHECK(dev_priv, reg) \
+ if (IS_HASWELL(dev_priv-dev) \
+ (I915_READ_NOTRACE(GEN7_ERR_INT) ERR_INT_MMIO_UNCLAIMED)) { \
+ DRM_ERROR(Unclaimed write to %x\n, reg); \
+ writel(ERR_INT_MMIO_UNCLAIMED, dev_priv-regs + GEN7_ERR_INT); \
+ }
+
#define __i915_read(x, y) \
u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
u##x val = 0; \
@@ -1167,18 +1181,12 @@ void i915_write##x(struct drm_i915_private *dev_priv,
u32 reg, u##x val) { \
} \
if (IS_GEN5(dev_priv-dev)) \
ilk_dummy_write(dev_priv); \
- if (IS_HASWELL(dev_priv-dev) (I915_READ_NOTRACE(GEN7_ERR_INT)
ERR_INT_MMIO_UNCLAIMED)) { \
- DRM_ERROR(Unknown unclaimed register before writing to %x\n,
reg); \
- I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
- } \
+ UNCLAIMED_REG_CLEAR(dev_priv, reg); \
write##y(val, dev_priv-regs + reg); \
if (unlikely(__fifo_ret)) { \
gen6_gt_check_fifodbg(dev_priv); \
} \
- if (IS_HASWELL(dev_priv-dev) (I915_READ_NOTRACE(GEN7_ERR_INT)
ERR_INT_MMIO_UNCLAIMED)) { \
- DRM_ERROR(Unclaimed write to %x\n, reg); \
- writel(ERR_INT_MMIO_UNCLAIMED, dev_priv-regs + GEN7_ERR_INT);
\
- } \
+ UNCLAIMED_REG_CHECK(dev_priv, reg); \
}
__i915_write(8, b)
__i915_write(16, w)
--
1.7.10.4
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[Intel-gfx] [PATCH 02/10] drm/i915: use FPGA_DBG for the unclaimed register checks
From: Paulo Zanoni paulo.r.zan...@intel.com
We plan to treat GEN7_ERR_INT as an interrupt, so use this register
for the checks inside I915_WRITE. This way we can have the best of
both worlds: the error message with a register address and the
interrupt.
V2: Split in 2 patches: one for the macro, one for changing the
register, as requested by Ben.
Reviewed-by: Ben Widawsky b...@bwidawsk.net
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.c |8
drivers/gpu/drm/i915/i915_reg.h |3 +++
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e24c337..24b4e5c 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1133,16 +1133,16 @@ ilk_dummy_write(struct drm_i915_private *dev_priv)
#define UNCLAIMED_REG_CLEAR(dev_priv, reg) \
if (IS_HASWELL(dev_priv-dev) \
- (I915_READ_NOTRACE(GEN7_ERR_INT) ERR_INT_MMIO_UNCLAIMED)) { \
+ (I915_READ_NOTRACE(FPGA_DBG) FPGA_DBG_RM_NOCLAIM)) { \
DRM_ERROR(Unknown unclaimed register before writing to %x\n,
reg); \
- I915_WRITE_NOTRACE(GEN7_ERR_INT, ERR_INT_MMIO_UNCLAIMED); \
+ I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); \
}
#define UNCLAIMED_REG_CHECK(dev_priv, reg) \
if (IS_HASWELL(dev_priv-dev) \
- (I915_READ_NOTRACE(GEN7_ERR_INT) ERR_INT_MMIO_UNCLAIMED)) { \
+ (I915_READ_NOTRACE(FPGA_DBG) FPGA_DBG_RM_NOCLAIM)) { \
DRM_ERROR(Unclaimed write to %x\n, reg); \
- writel(ERR_INT_MMIO_UNCLAIMED, dev_priv-regs + GEN7_ERR_INT); \
+ I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); \
}
#define __i915_read(x, y) \
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eaed90f..663b5c1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -521,6 +521,9 @@
#define GEN7_ERR_INT 0x44040
#define ERR_INT_MMIO_UNCLAIMED (113)
+#define FPGA_DBG 0x42300
+#define FPGA_DBG_RM_NOCLAIM(131)
+
/* GM45+ chicken bits -- debug workaround bits that may be required
* for various sorts of correct behavior. The top 16 bits of each are
* the enables for writing to the corresponding low bit.
--
1.7.10.4
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[Intel-gfx] [PATCH 03/10] drm/i915: clear the FPGA_DBG_RM_NOCLAIM bit at driver init
From: Paulo Zanoni paulo.r.zan...@intel.com
Otherwise, if the BIOS did anything wrong, our first I915_{WRITE,READ}
will give us unclaimed register messages.
V2: Even earlier.
Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=58897
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_dma.c |4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 4fa6beb..6d8672e 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1542,6 +1542,10 @@ int i915_driver_load(struct drm_device *dev, unsigned
long flags)
goto put_gmch;
}
+ /* This must happen before any I915_{READ,WRITE}: */
+ if (IS_HASWELL(dev))
+ I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+
aperture_size = dev_priv-gtt.mappable_end;
dev_priv-gtt.mappable =
--
1.7.10.4
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[Intel-gfx] [PATCH 04/10] drm/i915: add ibx_irq_postinstall
From: Paulo Zanoni paulo.r.zan...@intel.com
So we can remove duplicated code. Note that this function is used not
only on IBX, but also CPT and LPT.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 66 ++-
1 file changed, 24 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index be5289b..f096ad9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1926,6 +1926,28 @@ static void ironlake_enable_pch_hotplug(struct
drm_device *dev)
I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
}
+static void ibx_irq_postinstall(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
+ u32 mask;
+
+ if (HAS_PCH_IBX(dev))
+ mask = SDE_HOTPLUG_MASK |
+ SDE_GMBUS |
+ SDE_AUX_MASK;
+ else
+ mask = SDE_HOTPLUG_MASK_CPT |
+ SDE_GMBUS_CPT |
+ SDE_AUX_MASK_CPT;
+
+ I915_WRITE(SDEIIR, I915_READ(SDEIIR));
+ I915_WRITE(SDEIMR, ~mask);
+ I915_WRITE(SDEIER, mask);
+ POSTING_READ(SDEIER);
+
+ ironlake_enable_pch_hotplug(dev);
+}
+
static int ironlake_irq_postinstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
@@ -1934,8 +1956,6 @@ static int ironlake_irq_postinstall(struct drm_device
*dev)
DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
DE_AUX_CHANNEL_A;
u32 render_irqs;
- u32 hotplug_mask;
- u32 pch_irq_mask;
dev_priv-irq_mask = ~display_mask;
@@ -1963,30 +1983,7 @@ static int ironlake_irq_postinstall(struct drm_device
*dev)
I915_WRITE(GTIER, render_irqs);
POSTING_READ(GTIER);
- if (HAS_PCH_CPT(dev)) {
- hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
- SDE_PORTB_HOTPLUG_CPT |
- SDE_PORTC_HOTPLUG_CPT |
- SDE_PORTD_HOTPLUG_CPT |
- SDE_GMBUS_CPT |
- SDE_AUX_MASK_CPT);
- } else {
- hotplug_mask = (SDE_CRT_HOTPLUG |
- SDE_PORTB_HOTPLUG |
- SDE_PORTC_HOTPLUG |
- SDE_PORTD_HOTPLUG |
- SDE_GMBUS |
- SDE_AUX_MASK);
- }
-
- pch_irq_mask = ~hotplug_mask;
-
- I915_WRITE(SDEIIR, I915_READ(SDEIIR));
- I915_WRITE(SDEIMR, pch_irq_mask);
- I915_WRITE(SDEIER, hotplug_mask);
- POSTING_READ(SDEIER);
-
- ironlake_enable_pch_hotplug(dev);
+ ibx_irq_postinstall(dev);
if (IS_IRONLAKE_M(dev)) {
/* Clear enable PCU event interrupts */
@@ -2009,8 +2006,6 @@ static int ivybridge_irq_postinstall(struct drm_device
*dev)
DE_PLANEA_FLIP_DONE_IVB |
DE_AUX_CHANNEL_A_IVB;
u32 render_irqs;
- u32 hotplug_mask;
- u32 pch_irq_mask;
dev_priv-irq_mask = ~display_mask;
@@ -2034,20 +2029,7 @@ static int ivybridge_irq_postinstall(struct drm_device
*dev)
I915_WRITE(GTIER, render_irqs);
POSTING_READ(GTIER);
- hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
- SDE_PORTB_HOTPLUG_CPT |
- SDE_PORTC_HOTPLUG_CPT |
- SDE_PORTD_HOTPLUG_CPT |
- SDE_GMBUS_CPT |
- SDE_AUX_MASK_CPT);
- pch_irq_mask = ~hotplug_mask;
-
- I915_WRITE(SDEIIR, I915_READ(SDEIIR));
- I915_WRITE(SDEIMR, pch_irq_mask);
- I915_WRITE(SDEIER, hotplug_mask);
- POSTING_READ(SDEIER);
-
- ironlake_enable_pch_hotplug(dev);
+ ibx_irq_postinstall(dev);
return 0;
}
--
1.7.10.4
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[Intel-gfx] [PATCH 05/10] drm/i915: also disable south interrupts when handling them
From: Paulo Zanoni paulo.r.zan...@intel.com
From the docs:
Only the rising edge of the PCH Display interrupt will cause the
North Display IIR (DEIIR) PCH Display Interrupt even bit to be set,
so all PCH Display Interrupts, including back to back interrupts,
must be cleared before a new PCH Display interrupt can cause DEIIR
to be set.
The current code works fine because we don't get many interrupts, but
if we enable the PCH FIFO underrun interrupts we'll start getting so
many interrupts that at some point new PCH interrupts won't cause
DEIIR to be set.
The initial implementation I tried was to turn the code that checks
SDEIIR into a loop, but we can still get interrupts even after the
loop is done (and before the irq handler finishes), so we have to
either disable the interrupts or mask them. In the end I concluded
that just disabling the PCH interrupts is enough, you don't even need
the loop, so this is what this patch implements. I've tested it and it
passes the 2 PCH FIFO underrun interrupt storms I can reproduce:
the ironlake_crtc_disable case and the wrong watermarks case.
In other words, here's how to reproduce the problem fixed by this
patch:
1 - Enable PCH FIFO underrun interrupts (SERR_INT on SNB+)
2 - Boot the machine
3 - While booting we'll get tons of PCH FIFO underrun interrupts
4 - Plug a new monitor
5 - Run xrandr, notice it won't detect the new monitor
6 - Read SDEIIR and notice it's not 0 while DEIIR is 0
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f096ad9..500fd65 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -701,7 +701,7 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
{
struct drm_device *dev = (struct drm_device *) arg;
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
- u32 de_iir, gt_iir, de_ier, pm_iir;
+ u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
irqreturn_t ret = IRQ_NONE;
int i;
@@ -711,6 +711,10 @@ static irqreturn_t ivybridge_irq_handler(int irq, void
*arg)
de_ier = I915_READ(DEIER);
I915_WRITE(DEIER, de_ier ~DE_MASTER_IRQ_CONTROL);
+ sde_ier = I915_READ(SDEIER);
+ I915_WRITE(SDEIER, 0);
+ POSTING_READ(SDEIER);
+
gt_iir = I915_READ(GTIIR);
if (gt_iir) {
snb_gt_irq_handler(dev, dev_priv, gt_iir);
@@ -759,6 +763,8 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
I915_WRITE(DEIER, de_ier);
POSTING_READ(DEIER);
+ I915_WRITE(SDEIER, sde_ier);
+ POSTING_READ(SDEIER);
return ret;
}
@@ -778,7 +784,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
struct drm_device *dev = (struct drm_device *) arg;
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
int ret = IRQ_NONE;
- u32 de_iir, gt_iir, de_ier, pm_iir;
+ u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
atomic_inc(dev_priv-irq_received);
@@ -787,6 +793,10 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
I915_WRITE(DEIER, de_ier ~DE_MASTER_IRQ_CONTROL);
POSTING_READ(DEIER);
+ sde_ier = I915_READ(SDEIER);
+ I915_WRITE(SDEIER, 0);
+ POSTING_READ(SDEIER);
+
de_iir = I915_READ(DEIIR);
gt_iir = I915_READ(GTIIR);
pm_iir = I915_READ(GEN6_PMIIR);
@@ -849,6 +859,8 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
done:
I915_WRITE(DEIER, de_ier);
POSTING_READ(DEIER);
+ I915_WRITE(SDEIER, sde_ier);
+ POSTING_READ(SDEIER);
return ret;
}
--
1.7.10.4
___
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[Intel-gfx] [PATCH 06/10] drm/i915: print PCH poison interrupts
From: Paulo Zanoni paulo.r.zan...@intel.com
This is bad news and shouldn't be happening.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 29 +
drivers/gpu/drm/i915/i915_reg.h |4
2 files changed, 29 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 500fd65..10aec0e 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -665,6 +665,17 @@ static void ibx_irq_handler(struct drm_device *dev, u32
pch_iir)
DRM_DEBUG_DRIVER(PCH transcoder A underrun interrupt\n);
}
+static void serr_int_handler(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
+ u32 serr_int = I915_READ(SERR_INT);
+
+ if (serr_int SERR_INT_POISON)
+ DRM_ERROR(PCH poison interrupt\n);
+
+ I915_WRITE(SERR_INT, serr_int);
+}
+
static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
@@ -695,6 +706,9 @@ static void cpt_irq_handler(struct drm_device *dev, u32
pch_iir)
DRM_DEBUG_DRIVER( pipe %c FDI IIR: 0x%08x\n,
pipe_name(pipe),
I915_READ(FDI_RX_IIR(pipe)));
+
+ if (pch_iir SDE_ERROR_CPT)
+ serr_int_handler(dev);
}
static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
@@ -1943,14 +1957,19 @@ static void ibx_irq_postinstall(struct drm_device *dev)
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
u32 mask;
- if (HAS_PCH_IBX(dev))
+ if (HAS_PCH_IBX(dev)) {
mask = SDE_HOTPLUG_MASK |
SDE_GMBUS |
- SDE_AUX_MASK;
- else
+ SDE_AUX_MASK |
+ SDE_POISON;
+ } else {
mask = SDE_HOTPLUG_MASK_CPT |
SDE_GMBUS_CPT |
- SDE_AUX_MASK_CPT;
+ SDE_AUX_MASK_CPT |
+ SDE_ERROR_CPT;
+
+ I915_WRITE(SERR_INT, I915_READ(SERR_INT));
+ }
I915_WRITE(SDEIIR, I915_READ(SDEIIR));
I915_WRITE(SDEIMR, ~mask);
@@ -2180,6 +2199,8 @@ static void ironlake_irq_uninstall(struct drm_device *dev)
I915_WRITE(SDEIMR, 0x);
I915_WRITE(SDEIER, 0x0);
I915_WRITE(SDEIIR, I915_READ(SDEIIR));
+ if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
+ I915_WRITE(SERR_INT, I915_READ(SERR_INT));
}
static void i8xx_irq_preinstall(struct drm_device * dev)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 663b5c1..9cd59f7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3528,6 +3528,7 @@
SDE_PORTC_HOTPLUG_CPT |\
SDE_PORTB_HOTPLUG_CPT)
#define SDE_GMBUS_CPT (1 17)
+#define SDE_ERROR_CPT (1 16)
#define SDE_AUDIO_CP_REQ_C_CPT (1 10)
#define SDE_AUDIO_CP_CHG_C_CPT (1 9)
#define SDE_FDI_RXC_CPT(1 8)
@@ -3552,6 +3553,9 @@
#define SDEIIR 0xc4008
#define SDEIER 0xc400c
+#define SERR_INT 0xc4040
+#define SERR_INT_POISON (1 31)
+
/* digital port hotplug */
#define PCH_PORT_HOTPLUG0xc4030/* SHOTPLUG_CTL */
#define PORTD_HOTPLUG_ENABLE(1 20)
--
1.7.10.4
___
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[Intel-gfx] [PATCH 07/10] drm/i915: print Gen5+ CPU poison interrupts
From: Paulo Zanoni paulo.r.zan...@intel.com
On ILK/SNB all we need to do is to enable the poison bit, but on
IVB/HSW we need to enable the CPU error interrupt register, which is
responsible not only for poison interrupts, but also other things.
This includes the unclaimed register interrupt, so on the IVB irq
handler we now need to: (i) check whether the interrupt was triggered by an
unclaimed register and (ii) mask the error interrupt bit so we don't
risk generating unclaimed register interrupts form inside the
interrupt handler.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_irq.c | 49 ---
drivers/gpu/drm/i915/i915_reg.h |5 ++--
2 files changed, 49 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 10aec0e..703a08a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -665,6 +665,17 @@ static void ibx_irq_handler(struct drm_device *dev, u32
pch_iir)
DRM_DEBUG_DRIVER(PCH transcoder A underrun interrupt\n);
}
+static void err_int_handler(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
+ u32 err_int = I915_READ(GEN7_ERR_INT);
+
+ if (err_int ERR_INT_POISON)
+ DRM_ERROR(Poison interrupt\n);
+
+ I915_WRITE(GEN7_ERR_INT, err_int);
+}
+
static void serr_int_handler(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
@@ -715,16 +726,33 @@ static irqreturn_t ivybridge_irq_handler(int irq, void
*arg)
{
struct drm_device *dev = (struct drm_device *) arg;
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev-dev_private;
- u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
+ u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier, de_imr;
irqreturn_t ret = IRQ_NONE;
int i;
atomic_inc(dev_priv-irq_received);
+ /* We get interrupts on unclaimed registers, so check for this before we
+* do any I915_{READ,WRITE}. */
+ if (IS_HASWELL(dev)
+ (I915_READ_NOTRACE(FPGA_DBG) FPGA_DBG_RM_NOCLAIM)) {
+ DRM_ERROR(Unclaimed register before interrupt\n);
+ I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+ }
+
/* disable master interrupt before clearing iir */
de_ier = I915_READ(DEIER);
I915_WRITE(DEIER, de_ier ~DE_MASTER_IRQ_CONTROL);
+ /* On Haswell, also mask ERR_INT because we don't want to risk
+* generating unclaimed register interrupts from inside the interrupt
+* handler. */
+ de_imr = I915_READ(DEIMR);
+ if (IS_HASWELL(dev)) {
+ I915_WRITE(DEIMR, de_imr | DE_ERR_INT_IVB);
+ POSTING_READ(DEIMR);
+ }
+
sde_ier = I915_READ(SDEIER);
I915_WRITE(SDEIER, 0);
POSTING_READ(SDEIER);
@@ -738,6 +766,9 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
de_iir = I915_READ(DEIIR);
if (de_iir) {
+ if (de_iir DE_ERR_INT_IVB)
+ err_int_handler(dev);
+
if (de_iir DE_AUX_CHANNEL_A_IVB)
dp_aux_irq_handler(dev);
@@ -775,6 +806,11 @@ static irqreturn_t ivybridge_irq_handler(int irq, void
*arg)
ret = IRQ_HANDLED;
}
+ if (IS_HASWELL(dev)) {
+ I915_WRITE(DEIMR, de_imr);
+ POSTING_READ(DEIMR);
+ }
+
I915_WRITE(DEIER, de_ier);
POSTING_READ(DEIER);
I915_WRITE(SDEIER, sde_ier);
@@ -837,6 +873,9 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
if (de_iir DE_PIPEB_VBLANK)
drm_handle_vblank(dev, 1);
+ if (de_iir DE_POISON)
+ DRM_ERROR(Poison interrupt\n);
+
if (de_iir DE_PLANEA_FLIP_DONE) {
intel_prepare_page_flip(dev, 0);
intel_finish_page_flip_plane(dev, 0);
@@ -1985,7 +2024,7 @@ static int ironlake_irq_postinstall(struct drm_device
*dev)
/* enable kind of interrupts always enabled */
u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
- DE_AUX_CHANNEL_A;
+ DE_AUX_CHANNEL_A | DE_POISON;
u32 render_irqs;
dev_priv-irq_mask = ~display_mask;
@@ -2035,12 +2074,14 @@ static int ivybridge_irq_postinstall(struct drm_device
*dev)
DE_PLANEC_FLIP_DONE_IVB |
DE_PLANEB_FLIP_DONE_IVB |
DE_PLANEA_FLIP_DONE_IVB |
- DE_AUX_CHANNEL_A_IVB;
+ DE_AUX_CHANNEL_A_IVB |
+ DE_ERR_INT_IVB;
u32 render_irqs;
dev_priv-irq_mask = ~display_mask;
/* should always can generate irq */
+ I915_WRITE(GEN7_ERR_INT,
[Intel-gfx] [PATCH 08/10] drm/i915: print PCH FIFO underrun interrupts
From: Paulo Zanoni paulo.r.zan...@intel.com
Also add an ignore bit that avoids printing the message in two
cases:
- When the message is in fact expected.
- After we get the first message. In tihs case, we expect to get
hundreds of consecutive messages, so we just ignore all the
subsequent messages until the next crtc_enable.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |3 +++
drivers/gpu/drm/i915/i915_irq.c | 37 +-
drivers/gpu/drm/i915/i915_reg.h |7 +--
drivers/gpu/drm/i915/intel_display.c | 14 -
4 files changed, 53 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 08c5def..e96d75e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -909,6 +909,9 @@ typedef struct drm_i915_private {
struct work_struct hotplug_work;
bool enable_hotplug_processing;
+ /* Bit 0: PCH transcoder A and so on. */
+ u8 ignore_pch_fifo_underrun;
+
int num_pipe;
int num_pch_pll;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 703a08a..7497589 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -659,10 +659,17 @@ static void ibx_irq_handler(struct drm_device *dev, u32
pch_iir)
if (pch_iir (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
DRM_DEBUG_DRIVER(PCH transcoder CRC error interrupt\n);
- if (pch_iir SDE_TRANSB_FIFO_UNDER)
- DRM_DEBUG_DRIVER(PCH transcoder B underrun interrupt\n);
- if (pch_iir SDE_TRANSA_FIFO_UNDER)
- DRM_DEBUG_DRIVER(PCH transcoder A underrun interrupt\n);
+ if ((pch_iir SDE_TRANSB_FIFO_UNDER)
+ !(dev_priv-ignore_pch_fifo_underrun (1 TRANSCODER_B))) {
+ DRM_DEBUG_DRIVER(PCH transcoder B underrun\n);
+ dev_priv-ignore_pch_fifo_underrun |= (1 TRANSCODER_B);
+ }
+
+ if ((pch_iir SDE_TRANSA_FIFO_UNDER)
+ !(dev_priv-ignore_pch_fifo_underrun (1 TRANSCODER_A))) {
+ DRM_DEBUG_DRIVER(PCH transcoder A underrun\n);
+ dev_priv-ignore_pch_fifo_underrun |= (1 TRANSCODER_A);
+ }
}
static void err_int_handler(struct drm_device *dev)
@@ -684,6 +691,24 @@ static void serr_int_handler(struct drm_device *dev)
if (serr_int SERR_INT_POISON)
DRM_ERROR(PCH poison interrupt\n);
+ if ((serr_int SERR_INT_TRANS_A_FIFO_UNDERRUN)
+ !(dev_priv-ignore_pch_fifo_underrun (1 TRANSCODER_A))) {
+ DRM_ERROR(PCH transcoder A FIFO underrun\n);
+ dev_priv-ignore_pch_fifo_underrun |= (1 TRANSCODER_A);
+ }
+
+ if ((serr_int SERR_INT_TRANS_B_FIFO_UNDERRUN)
+ !(dev_priv-ignore_pch_fifo_underrun (1 TRANSCODER_B))) {
+ DRM_ERROR(PCH transcoder B FIFO underrun\n);
+ dev_priv-ignore_pch_fifo_underrun |= (1 TRANSCODER_B);
+ }
+
+ if ((serr_int SERR_INT_TRANS_C_FIFO_UNDERRUN)
+ !(dev_priv-ignore_pch_fifo_underrun (1 TRANSCODER_C))) {
+ DRM_ERROR(PCH transcoder C FIFO underrun\n);
+ dev_priv-ignore_pch_fifo_underrun |= (1 TRANSCODER_C);
+ }
+
I915_WRITE(SERR_INT, serr_int);
}
@@ -2000,7 +2025,9 @@ static void ibx_irq_postinstall(struct drm_device *dev)
mask = SDE_HOTPLUG_MASK |
SDE_GMBUS |
SDE_AUX_MASK |
- SDE_POISON;
+ SDE_POISON |
+ SDE_TRANSB_FIFO_UNDER |
+ SDE_TRANSA_FIFO_UNDER;
} else {
mask = SDE_HOTPLUG_MASK_CPT |
SDE_GMBUS_CPT |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f22e27d..d565bd7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3554,8 +3554,11 @@
#define SDEIIR 0xc4008
#define SDEIER 0xc400c
-#define SERR_INT 0xc4040
-#define SERR_INT_POISON (1 31)
+#define SERR_INT 0xc4040
+#define SERR_INT_POISON (1 31)
+#define SERR_INT_TRANS_C_FIFO_UNDERRUN(1 6)
+#define SERR_INT_TRANS_B_FIFO_UNDERRUN(1 3)
+#define SERR_INT_TRANS_A_FIFO_UNDERRUN(1 0)
/* digital port hotplug */
#define PCH_PORT_HOTPLUG0xc4030/* SHOTPLUG_CTL */
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index d75c6a0..67bfb58 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3274,6 +3274,9 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
return;
intel_crtc-active = true;
+
+ dev_priv-ignore_pch_fifo_underrun = ~(1 pipe);
+
[Intel-gfx] [PATCH 09/10] drm/i915: print CPU FIFO underruns
From: Paulo Zanoni paulo.r.zan...@intel.com
Just like the PCH FIFO underruns, except that there's no place
where we expect it to happen.
Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com
---
drivers/gpu/drm/i915/i915_drv.h |2 ++
drivers/gpu/drm/i915/i915_irq.c | 33 -
drivers/gpu/drm/i915/i915_reg.h |3 +++
drivers/gpu/drm/i915/intel_display.c |2 ++
4 files changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e96d75e..f614ea8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -909,6 +909,8 @@ typedef struct drm_i915_private {
struct work_struct hotplug_work;
bool enable_hotplug_processing;
+ /* Bit 0: pipe A and son on. */
+ u8 ignore_cpu_fifo_underrun;
/* Bit 0: PCH transcoder A and so on. */
u8 ignore_pch_fifo_underrun;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 7497589..09bd8d4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -680,6 +680,24 @@ static void err_int_handler(struct drm_device *dev)
if (err_int ERR_INT_POISON)
DRM_ERROR(Poison interrupt\n);
+ if ((err_int ERR_INT_FIFO_UNDERRUN_A)
+ !(dev_priv-ignore_cpu_fifo_underrun (1 PIPE_A))) {
+ DRM_ERROR(Pipe A FIFO underrun\n);
+ dev_priv-ignore_cpu_fifo_underrun |= (1 PIPE_A);
+ }
+
+ if ((err_int ERR_INT_FIFO_UNDERRUN_B)
+ !(dev_priv-ignore_cpu_fifo_underrun (1 PIPE_B))) {
+ DRM_ERROR(Pipe B FIFO underrun\n);
+ dev_priv-ignore_cpu_fifo_underrun |= (1 PIPE_B);
+ }
+
+ if ((err_int ERR_INT_FIFO_UNDERRUN_C)
+ !(dev_priv-ignore_cpu_fifo_underrun (1 PIPE_C))) {
+ DRM_ERROR(Pipe C FIFO underrun\n);
+ dev_priv-ignore_cpu_fifo_underrun |= (1 PIPE_C);
+ }
+
I915_WRITE(GEN7_ERR_INT, err_int);
}
@@ -901,6 +919,18 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
if (de_iir DE_POISON)
DRM_ERROR(Poison interrupt\n);
+ if ((de_iir DE_PIPEA_FIFO_UNDERRUN)
+ !(dev_priv-ignore_cpu_fifo_underrun (1 PIPE_A))) {
+ DRM_ERROR(Pipe A FIFO underrun\n);
+ dev_priv-ignore_cpu_fifo_underrun |= (1 PIPE_A);
+ }
+
+ if ((de_iir DE_PIPEB_FIFO_UNDERRUN)
+ !(dev_priv-ignore_cpu_fifo_underrun (1 PIPE_B))) {
+ DRM_ERROR(Pipe B FIFO underrun\n);
+ dev_priv-ignore_cpu_fifo_underrun |= (1 PIPE_B);
+ }
+
if (de_iir DE_PLANEA_FLIP_DONE) {
intel_prepare_page_flip(dev, 0);
intel_finish_page_flip_plane(dev, 0);
@@ -2051,7 +2081,8 @@ static int ironlake_irq_postinstall(struct drm_device
*dev)
/* enable kind of interrupts always enabled */
u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
- DE_AUX_CHANNEL_A | DE_POISON;
+ DE_AUX_CHANNEL_A | DE_POISON |
+ DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
u32 render_irqs;
dev_priv-irq_mask = ~display_mask;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d565bd7..c0db8b4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -521,6 +521,9 @@
#define GEN7_ERR_INT 0x44040
#define ERR_INT_POISON (131)
#define ERR_INT_MMIO_UNCLAIMED (113)
+#define ERR_INT_FIFO_UNDERRUN_C (16)
+#define ERR_INT_FIFO_UNDERRUN_B (13)
+#define ERR_INT_FIFO_UNDERRUN_A (10)
#define FPGA_DBG 0x42300
#define FPGA_DBG_RM_NOCLAIM(131)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 67bfb58..030a8d3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3275,6 +3275,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
intel_crtc-active = true;
+ dev_priv-ignore_cpu_fifo_underrun = ~(1 pipe);
dev_priv-ignore_pch_fifo_underrun = ~(1 pipe);
intel_update_watermarks(dev);
@@ -3372,6 +3373,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
is_pch_port = haswell_crtc_driving_pch(crtc);
+ dev_priv-ignore_cpu_fifo_underrun = ~(1 pipe);
if (is_pch_port)
dev_priv-ignore_pch_fifo_underrun = ~(1 TRANSCODER_A);
--
1.7.10.4
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[Intel-gfx] [PATCH 10/10] drm/i915: also POSTING_READ(DEIER) on ivybridge_irq_handler
From: Paulo Zanoni paulo.r.zan...@intel.com This is already done on ironlake_irq_handler. We want to make sure the interrupts are disabled before we check any of the other interrupt registers. Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- drivers/gpu/drm/i915/i915_irq.c |1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 09bd8d4..e9a6ade 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -786,6 +786,7 @@ static irqreturn_t ivybridge_irq_handler(int irq, void *arg) /* disable master interrupt before clearing iir */ de_ier = I915_READ(DEIER); I915_WRITE(DEIER, de_ier ~DE_MASTER_IRQ_CONTROL); + POSTING_READ(DEIER); /* On Haswell, also mask ERR_INT because we don't want to risk * generating unclaimed register interrupts from inside the interrupt -- 1.7.10.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v2] drm/i915: Extract ring init from hw_init
The ring initialization will differ a bit in upcoming generations, and
this split will prepare the code for what's needed.
This patch also fixes a bug introduced in:
commit 99433931950f33039d9e1a52b4ed9af3f1b58e84
Author: Mika Kuoppala mika.kuopp...@linux.intel.com
Date: Tue Jan 22 14:12:17 2013 +0200
drm/i915: use gem_set_seqno() on hardware init
After doing the extraction, the bad error handling became obvious. I
acknowledge that this should be two patches, but it's a pretty
small/trivial patch. If requested, I can certainly do the fix as a
distinct patch.
v2: Should be cleanup blt, not init blt on failure (Chris)
Cc: Mika Kuoppala mika.kuopp...@linux.intel.com
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem.c | 53 ++---
1 file changed, 34 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d746177..82cc23e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3922,22 +3922,11 @@ intel_enable_blt(struct drm_device *dev)
return true;
}
-int
-i915_gem_init_hw(struct drm_device *dev)
+static int i915_gem_init_rings(struct drm_device *dev)
{
- drm_i915_private_t *dev_priv = dev-dev_private;
+ struct drm_i915_private *dev_priv = dev-dev_private;
int ret;
- if (INTEL_INFO(dev)-gen 6 !intel_enable_gtt())
- return -EIO;
-
- if (IS_HASWELL(dev) (I915_READ(0x120010) == 1))
- I915_WRITE(0x9008, I915_READ(0x9008) | 0xf);
-
- i915_gem_l3_remap(dev);
-
- i915_gem_init_swizzling(dev);
-
ret = intel_init_render_ring_buffer(dev);
if (ret)
return ret;
@@ -3956,6 +3945,38 @@ i915_gem_init_hw(struct drm_device *dev)
ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
if (ret)
+ goto cleanup_blt_ring;
+
+ return 0;
+
+cleanup_blt_ring:
+ intel_init_blt_ring_buffer(dev_priv-ring[BCS]);
+cleanup_bsd_ring:
+ intel_cleanup_ring_buffer(dev_priv-ring[VCS]);
+cleanup_render_ring:
+ intel_cleanup_ring_buffer(dev_priv-ring[RCS]);
+
+ return ret;
+}
+
+int
+i915_gem_init_hw(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = dev-dev_private;
+ int ret;
+
+ if (INTEL_INFO(dev)-gen 6 !intel_enable_gtt())
+ return -EIO;
+
+ if (IS_HASWELL(dev) (I915_READ(0x120010) == 1))
+ I915_WRITE(0x9008, I915_READ(0x9008) | 0xf);
+
+ i915_gem_l3_remap(dev);
+
+ i915_gem_init_swizzling(dev);
+
+ ret = i915_gem_init_rings(dev);
+ if (ret)
return ret;
/*
@@ -3966,12 +3987,6 @@ i915_gem_init_hw(struct drm_device *dev)
i915_gem_init_ppgtt(dev);
return 0;
-
-cleanup_bsd_ring:
- intel_cleanup_ring_buffer(dev_priv-ring[VCS]);
-cleanup_render_ring:
- intel_cleanup_ring_buffer(dev_priv-ring[RCS]);
- return ret;
}
int i915_gem_init(struct drm_device *dev)
--
1.8.1.2
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Re: [Intel-gfx] [PATCH 07/10] drm/i915: print Gen5+ CPU poison interrupts
On Fri, 8 Feb 2013 17:35:18 -0200 Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com On ILK/SNB all we need to do is to enable the poison bit, but on IVB/HSW we need to enable the CPU error interrupt register, which is responsible not only for poison interrupts, but also other things. This includes the unclaimed register interrupt, so on the IVB irq handler we now need to: (i) check whether the interrupt was triggered by an unclaimed register and (ii) mask the error interrupt bit so we don't risk generating unclaimed register interrupts form inside the interrupt handler. Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- OTOH there's nothing the user can do about it... so we might do a WARN_ONCE or something here instead. But even then, I'm not sure there's much *we* can do about these, as they indicate a corruption in the communication between the CPU and PCH. -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH v3] drm/i915: Extract ring init from hw_init
The ring initialization will differ a bit in upcoming generations, and
this split will prepare the code for what's needed.
This patch also fixes a bug introduced in:
commit 99433931950f33039d9e1a52b4ed9af3f1b58e84
Author: Mika Kuoppala mika.kuopp...@linux.intel.com
Date: Tue Jan 22 14:12:17 2013 +0200
drm/i915: use gem_set_seqno() on hardware init
After doing the extraction, the bad error handling became obvious. I
acknowledge that this should be two patches, but it's a pretty
small/trivial patch. If requested, I can certainly do the fix as a
distinct patch.
v2: Should be cleanup blt, not init blt on failure (Chris)
v3: Forgot to git add on v2
Cc: Mika Kuoppala mika.kuopp...@linux.intel.com
Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
drivers/gpu/drm/i915/i915_gem.c | 53 ++---
1 file changed, 34 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d746177..73b1e9e 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3922,22 +3922,11 @@ intel_enable_blt(struct drm_device *dev)
return true;
}
-int
-i915_gem_init_hw(struct drm_device *dev)
+static int i915_gem_init_rings(struct drm_device *dev)
{
- drm_i915_private_t *dev_priv = dev-dev_private;
+ struct drm_i915_private *dev_priv = dev-dev_private;
int ret;
- if (INTEL_INFO(dev)-gen 6 !intel_enable_gtt())
- return -EIO;
-
- if (IS_HASWELL(dev) (I915_READ(0x120010) == 1))
- I915_WRITE(0x9008, I915_READ(0x9008) | 0xf);
-
- i915_gem_l3_remap(dev);
-
- i915_gem_init_swizzling(dev);
-
ret = intel_init_render_ring_buffer(dev);
if (ret)
return ret;
@@ -3956,6 +3945,38 @@ i915_gem_init_hw(struct drm_device *dev)
ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
if (ret)
+ goto cleanup_blt_ring;
+
+ return 0;
+
+cleanup_blt_ring:
+ intel_cleanup_ring_buffer(dev_priv-ring[BCS]);
+cleanup_bsd_ring:
+ intel_cleanup_ring_buffer(dev_priv-ring[VCS]);
+cleanup_render_ring:
+ intel_cleanup_ring_buffer(dev_priv-ring[RCS]);
+
+ return ret;
+}
+
+int
+i915_gem_init_hw(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = dev-dev_private;
+ int ret;
+
+ if (INTEL_INFO(dev)-gen 6 !intel_enable_gtt())
+ return -EIO;
+
+ if (IS_HASWELL(dev) (I915_READ(0x120010) == 1))
+ I915_WRITE(0x9008, I915_READ(0x9008) | 0xf);
+
+ i915_gem_l3_remap(dev);
+
+ i915_gem_init_swizzling(dev);
+
+ ret = i915_gem_init_rings(dev);
+ if (ret)
return ret;
/*
@@ -3966,12 +3987,6 @@ i915_gem_init_hw(struct drm_device *dev)
i915_gem_init_ppgtt(dev);
return 0;
-
-cleanup_bsd_ring:
- intel_cleanup_ring_buffer(dev_priv-ring[VCS]);
-cleanup_render_ring:
- intel_cleanup_ring_buffer(dev_priv-ring[RCS]);
- return ret;
}
int i915_gem_init(struct drm_device *dev)
--
1.8.1.2
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Re: [Intel-gfx] [PATCH 07/10] drm/i915: print Gen5+ CPU poison interrupts
Hi 2013/2/8 Jesse Barnes jbar...@virtuousgeek.org: On Fri, 8 Feb 2013 17:35:18 -0200 Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com On ILK/SNB all we need to do is to enable the poison bit, but on IVB/HSW we need to enable the CPU error interrupt register, which is responsible not only for poison interrupts, but also other things. This includes the unclaimed register interrupt, so on the IVB irq handler we now need to: (i) check whether the interrupt was triggered by an unclaimed register and (ii) mask the error interrupt bit so we don't risk generating unclaimed register interrupts form inside the interrupt handler. Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- OTOH there's nothing the user can do about it... so we might do a WARN_ONCE or something here instead. Well, so far I haven't seen the message. If we conclude it happens *too much*, then we can use WARN_ONCE. But even then, I'm not sure there's much *we* can do about these, as they indicate a corruption in the communication between the CPU and PCH. At least if we get the message we may be able to understand and/or reproduce the problems. So far we don't even know whether the problem is happening or not... And when there's a display bug, we don't know if it's caused by poison. -- Jesse Barnes, Intel Open Source Technology Center -- Paulo Zanoni ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] i915 PCH backlight vs. Dell XPS13
You might want to try the latest drm-intel-nightly git branch from
http://cgit.freedesktop.org/~danvet/drm-intel This has a few more
tricks which helped on some similar platforsm to yours (and similar
resume issues).
And please always include a mailing list when reporting issues, since
your dear maintainer might be on vacation (or simply swamped with
other stuff).
Cheers, Daniel
On Fri, Feb 8, 2013 at 8:36 PM, Kamal Mostafa ka...@canonical.com wrote:
Hi Paulo and Daniel-
I've been tracking Daniel's work on i915 backlight for quite some time
now, in particular to support the Dell XPS13 (Sandybridge-mobile,
CougarPoint PCH) in the Ubuntu kernels.
Daniel's backlight fixes which landed in 3.6 did enable working
backlight controls on the XPS13, but it appears that this commit from
Paolo broke it again:
a4f32fc drm/i915: don't forget the PCH backlight registers
More specifically, the behavior on the XPS13 is this:
With the current 3.8-rc6 i915 stack (including a4f32fc), this machine
gets both of: /sys/class/backlight/{acpi_video0,intel_backlight}.
Changes to acpi_video0/brightness don't have any effect on the
backlight, unless I first echo 0 intel_backlight/brightness, then
acpi_video0 works properly. If I stuff a low non-zero number into
intel_backlight/brightness, then the backlight pulsates and flickers
continuously.
If I revert a4f32fc (or just omit the setting of BLM_PCH_PWM_ENABLE in
intel_panel_enable_backlight) then my backlight controls work fine:
acpi_video0/brightness works at boot, and intel_backlight/brightness no
longer induces the pulsate/flicker effect (or any effect at all).
So... before I go shooting my mouth off on intel-gfx, I wonder if either
of you can shed any (back)light on the situation (sorry ;-).
I don't really have any reason to think that this issue is specific to
CougarPoint PCH, but since the XPS13 is PCH_CPT this patch fixes it for
me, for instance:
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -347,7 +347,9 @@ void intel_panel_enable_backlight(struct drm_device *dev,
POSTING_READ(reg);
I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
- if (HAS_PCH_SPLIT(dev)) {
+ /* Note setting BLM_PCH_PWM_ENABLE breaks backlight on
+* Dell XPS13 (sandybridge_m, CougarPoint PCH). */
+ if (HAS_PCH_SPLIT(dev) !HAS_PCH_CPT(dev)) {
tmp = I915_READ(BLC_PWM_PCH_CTL1);
tmp |= BLM_PCH_PWM_ENABLE;
tmp = ~BLM_PCH_OVERRIDE_ENABLE;
I don't know if switching this based on HAS_PCH_CPT() is really relevant
-- it just works for the Dell XPS. (And please forgive my obvious
cluelessness about what PCH_CPT even means!)
Any advice?
-Kamal
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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Re: [Intel-gfx] [PATCH 07/10] drm/i915: print Gen5+ CPU poison interrupts
On Fri, 8 Feb 2013 17:54:23 -0200 Paulo Zanoni przan...@gmail.com wrote: Hi 2013/2/8 Jesse Barnes jbar...@virtuousgeek.org: On Fri, 8 Feb 2013 17:35:18 -0200 Paulo Zanoni przan...@gmail.com wrote: From: Paulo Zanoni paulo.r.zan...@intel.com On ILK/SNB all we need to do is to enable the poison bit, but on IVB/HSW we need to enable the CPU error interrupt register, which is responsible not only for poison interrupts, but also other things. This includes the unclaimed register interrupt, so on the IVB irq handler we now need to: (i) check whether the interrupt was triggered by an unclaimed register and (ii) mask the error interrupt bit so we don't risk generating unclaimed register interrupts form inside the interrupt handler. Signed-off-by: Paulo Zanoni paulo.r.zan...@intel.com --- OTOH there's nothing the user can do about it... so we might do a WARN_ONCE or something here instead. Well, so far I haven't seen the message. If we conclude it happens *too much*, then we can use WARN_ONCE. But even then, I'm not sure there's much *we* can do about these, as they indicate a corruption in the communication between the CPU and PCH. At least if we get the message we may be able to understand and/or reproduce the problems. So far we don't even know whether the problem is happening or not... And when there's a display bug, we don't know if it's caused by poison. Ok I guess the DRM_ERROR won't hurt if/until we see reports. Then we can dig in and see if keeping the message makes sense or not. -- Jesse Barnes, Intel Open Source Technology Center ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Implement pipe CSC based limited range RGB output
On Fri, Jan 18, 2013 at 07:11:38PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com HSW no longer has the PIPECONF bit for limited range RGB output. Instead the pipe CSC unit must be used to perform that task. The CSC pre offset are set to 0, since the incoming data is full [0:255] range RGB, the coefficients are programmed to compress the data into [0:219] range, and then we use either the CSC_MODE black screen offset bit, or the CSC post offsets to shift the data to the correct [16:235] range. Also have to change the confiuration of all planes so that the data is sent through the pipe CSC unit. For simplicity send the plane data through the pipe CSC unit always, and in case full range output is requested, the pipe CSC unit is set up with an identity transform to pass the plane data through unchanged. I've been told by some hardware people that the use of the pipe CSC unit shouldn't result in any measurable increase in power consumption numbers. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- Note that I haven't actually tested this on HSW. I did test the earlier prototype version on ILK and IVB. The pipe CSC unit on ILK isn't programmed in quite the same as on HSW, but the IVB unit _should_ be identical to HSW. The main risk involves the coefficient registers. If the channel mapping changed for some reason, we could get swapped channels. For some reason reality and documenation didn't seem to agree how the channels are mapped even on ILK and IVB. So I'd like someone to try this out on HSW to make sure the output still looks correct. FYI I just tested this on a HSW box, and all the colors look correct. I also verified that the pipeconf color range bit is well and truly gone (hw won't allow you to even set it). So Daniel, I think this can go in as is. -- Ville Syrjälä Intel OTC ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Fix sprite_scaling_enabled for multiple sprites
From: Ville Syrjälä ville.syrj...@linux.intel.com
We have more than one sprite, so a boolean simply won't cut it.
Turn sprite_scaling_enabled into a bitmask and track the state
of sprite scaler for each sprite independently.
Also don't re-enable LP watermarks until the sprite registers
have actually been written, and thus sprite scaling has really
been disabled.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_sprite.c | 27 ---
2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4e5a377..a7860ea 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -925,7 +925,7 @@ typedef struct drm_i915_private {
/* overlay */
struct intel_overlay *overlay;
- bool sprite_scaling_enabled;
+ unsigned int sprite_scaling_enabled;
/* LVDS info */
int backlight_level; /* restore backlight to this value */
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index f829306..03cfd62 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -50,6 +50,7 @@ ivb_update_plane(struct drm_plane *plane, struct
drm_framebuffer *fb,
u32 sprctl, sprscale = 0;
unsigned long sprsurf_offset, linear_offset;
int pixel_size = drm_format_plane_cpp(fb-pixel_format, 0);
+ bool scaling_was_enabled = dev_priv-sprite_scaling_enabled;
sprctl = I915_READ(SPRCTL(pipe));
@@ -103,19 +104,15 @@ ivb_update_plane(struct drm_plane *plane, struct
drm_framebuffer *fb,
* when scaling is disabled.
*/
if (crtc_w != src_w || crtc_h != src_h) {
- if (!dev_priv-sprite_scaling_enabled) {
- dev_priv-sprite_scaling_enabled = true;
+ dev_priv-sprite_scaling_enabled |= 1 pipe;
+
+ if (!scaling_was_enabled) {
intel_update_watermarks(dev);
intel_wait_for_vblank(dev, pipe);
}
sprscale = SPRITE_SCALE_ENABLE | (src_w 16) | src_h;
- } else {
- if (dev_priv-sprite_scaling_enabled) {
- dev_priv-sprite_scaling_enabled = false;
- /* potentially re-enable LP watermarks */
- intel_update_watermarks(dev);
- }
- }
+ } else
+ dev_priv-sprite_scaling_enabled = ~(1 pipe);
I915_WRITE(SPRSTRIDE(pipe), fb-pitches[0]);
I915_WRITE(SPRPOS(pipe), (crtc_y 16) | crtc_x);
@@ -141,6 +138,10 @@ ivb_update_plane(struct drm_plane *plane, struct
drm_framebuffer *fb,
I915_WRITE(SPRCTL(pipe), sprctl);
I915_MODIFY_DISPBASE(SPRSURF(pipe), obj-gtt_offset + sprsurf_offset);
POSTING_READ(SPRSURF(pipe));
+
+ /* potentially re-enable LP watermarks */
+ if (scaling_was_enabled !dev_priv-sprite_scaling_enabled)
+ intel_update_watermarks(dev);
}
static void
@@ -150,6 +151,7 @@ ivb_disable_plane(struct drm_plane *plane)
struct drm_i915_private *dev_priv = dev-dev_private;
struct intel_plane *intel_plane = to_intel_plane(plane);
int pipe = intel_plane-pipe;
+ bool scaling_was_enabled = dev_priv-sprite_scaling_enabled;
I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) ~SPRITE_ENABLE);
/* Can't leave the scaler enabled... */
@@ -159,8 +161,11 @@ ivb_disable_plane(struct drm_plane *plane)
I915_MODIFY_DISPBASE(SPRSURF(pipe), 0);
POSTING_READ(SPRSURF(pipe));
- dev_priv-sprite_scaling_enabled = false;
- intel_update_watermarks(dev);
+ dev_priv-sprite_scaling_enabled = ~(1 pipe);
+
+ /* potentially re-enable LP watermarks */
+ if (scaling_was_enabled !dev_priv-sprite_scaling_enabled)
+ intel_update_watermarks(dev);
}
static int
--
1.7.12.4
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Re: [Intel-gfx] [PATCH] drm/i915: Fix sprite_scaling_enabled for multiple sprites
On Fri, Feb 08, 2013 at 11:13:35PM +0200, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com We have more than one sprite, so a boolean simply won't cut it. Turn sprite_scaling_enabled into a bitmask and track the state of sprite scaler for each sprite independently. Also don't re-enable LP watermarks until the sprite registers have actually been written, and thus sprite scaling has really been disabled. I would emphasize this, since this fix is worthy of Cc: stable@ Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com Reviewed-by: Chris Wilson ch...@chris-wilson.co.uk -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH intel-gpu-tools 1/2] Put -I m4 in ACLOCAL_AMFLAGS so ./autogen.sh just works
On Fri, Feb 08, 2013 at 11:36:53AM -0800, Matt Turner wrote:
---
Makefile.am |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/Makefile.am b/Makefile.am
index 0dd615b..20bca79 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -19,7 +19,7 @@
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-ACLOCAL_AMFLAGS = ${ACLOCAL_FLAGS}
+ACLOCAL_AMFLAGS = ${ACLOCAL_FLAGS} -I m4
SUBDIRS = lib man tools scripts benchmarks demos
I've pushed both patches. Thanks.
--
Ben Widawsky, Intel Open Source Technology Center
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