Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: avoid concurrent writes to aux_inv (rev5)

[Yang, Fei]

Confirmed this is a regression caused by the patch. Will debug further.

From: Summers, Stuart 
Sent: Tuesday, March 15, 2022 8:23 PM
To: intel-gfx@lists.freedesktop.org; Yang, Fei 
Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: avoid concurrent 
writes to aux_inv (rev5)

On Sat, 2022-03-05 at 09:36 +, Patchwork wrote:
Patch Details
Series:
drm/i915: avoid concurrent writes to aux_inv (rev5)
URL:
https://patchwork.freedesktop.org/series/100772/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22492/index.html
CI Bug Log - changes from CI_DRM_11330_full -> Patchwork_22492_full
Summary

FAILURE

Serious unknown changes coming with Patchwork_22492_full absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22492_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Participating hosts (13 -> 13)

No changes in participating hosts

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_22492_full:

IGT changes
Possible regressions

  *   igt@gem_exec_balancer@fairslice:

 *   shard-tglb: 
PASS
 -> 
FAIL

I don't think the one below is related, but can you check on the above failure 
to make sure that isn't a result of your patch?

Thanks,
Stuart


  *
  *   igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt:

 *   shard-tglb: 
PASS
 -> 
INCOMPLETE

Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  *   igt@api_intel_allocator@fork-simple-stress-signal:

 *   {shard-dg1}: 
PASS
 -> 
TIMEOUT

  *   igt@drm_import_export@import-close-race-prime:

 *   {shard-rkl}: 
PASS
 -> 
INCOMPLETE
 +1 similar issue

  *   
{igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale}:

 *   {shard-rkl}: NOTRUN -> 
SKIP
 +2 similar issues

  *   igt@prime_mmap_coherency@ioctl-errors:

 *   {shard-dg1}: NOTRUN -> 
SKIP

Known issues

Here are the changes found in Patchwork_22492_full that come from known issues:

CI changes
Possible fixes

  *   boot:

 *   shard-glk: 
(PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 

Re: [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

[Yang, Fei]

>> @@ -157,6 +163,9 @@ int gen11_emit_flush_rcs(struct i915_request *rq,
>> u32 mode)
>>  intel_ring_advance(rq, cs);
>>  }
>>  
>> +/* hsdes: 1809175790. No fixup needed for gen11 rcs */
>> +rq->aux_inv_fixup = NULL;
>
> This is a little ugly to me. Can we just set this to 0 or 0xdeadbeef by 
> default maybe and check that value below instead of retroactively adding all 
> of these assignments?

The problem is there are many code paths that a i915_request could be 
allocated, I'm not aware of a unified routine where I could initialize the 
pointer for all i915_requests.

>> +
>>  return 0;
>>  }
>>  
>> +/*
>> + * We don't know which engine will eventually carry out
>> + * this request, so the mmio aux_inv register address
>> is
>> + * unknown at this moment. We save the cs pointer
>> supposed
>> + * to hold the aux_inv address in rq->aux_inv_fixup and
>> set
>> + * it in execlists_dequeue() when the engine instance
>> + * carrying out this request becomes certain
>> + */
>> +*cs++ = MI_LOAD_REGISTER_IMM(1);
>> +rq->aux_inv_fixup = cs; /* save the pointer to aux_inv
>> */
>> +*cs++ = 0; /* mmio addr to be set at submission to HW
>> */
>
>Maybe MI_NOOP instead?

This is supposed to be the mmio address field for the MI_LOAD_REGISTER_IMM 
instruction, setting it to 0 makes more sense?

>> +*cs++ = AUX_INV;
>>  *cs++ = MI_NOOP;
>> -}
>> +} else
>
> Can you add the brackets here on the else:
> } else {
>aux_inv_fixup = NULL
> }
>
>Also good to run checkpatch. I see this showing up as a warning in the 
>checkpatch results.

I noticed the warning, will update.

>> +rq->aux_inv_fixup = NULL;
>>  
>>  if (mode & EMIT_INVALIDATE)
>>  *cs++ = preparser_disable(false);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> index e1470bb60f34..7e8552414275 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> @@ -1258,6 +1258,34 @@ static bool completed(const struct i915_request 
>> *rq)
>>  return __i915_request_is_complete(rq);  }
>>  
>> +static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine) {
>> +static const i915_reg_t vd[] = {
>> +GEN12_VD0_AUX_NV,
>> +GEN12_VD1_AUX_NV,
>> +GEN12_VD2_AUX_NV,
>> +GEN12_VD3_AUX_NV,
>> +};
>> +
>> +static const i915_reg_t ve[] = {
>> +GEN12_VE0_AUX_NV,
>> +GEN12_VE1_AUX_NV,
>> +};
>> +
>> +if (engine->class == VIDEO_DECODE_CLASS) {
>> +GEM_BUG_ON(engine->instance >= ARRAY_SIZE(vd));
>> +return vd[engine->instance];
>> +}
>> +
>> +if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
>> +GEM_BUG_ON(engine->instance >= ARRAY_SIZE(ve));
>> +return ve[engine->instance];
>> +}
>> +
>> +GEM_BUG_ON("unknown aux_inv reg\n");
>> +return INVALID_MMIO_REG;
>> +}
>> +
>>  static void execlists_dequeue(struct intel_engine_cs *engine)
> 
> So in the previous implementation, this "worked" for both execlists and guc 
> submission. But how will this work now for GuC based submission?
> This flow and the address of the engine is owned by the GuC.
>
> If we are going to say this is an execlist only requirement (e.g.
> platforms using GuC submission don't need this workaround), you should add an 
> if (!using guc submission) in the sequence you added to the various 
> emit_flush() routines above.

Good point.
I didn't consider GuC submission because Chrome doesn't enable GuC for TGL. But 
it is true that the implementation will have problem with GuC submission.
I'm not sure if it's possible for i915 to know which engine will eventually 
carry out the request because it might be scheduled by GuC. I will need to 
investigate.

> Thanks,
> Stuart

Re: [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

[Summers, Stuart]

On Fri, 2022-03-04 at 14:14 -0800, fei.y...@intel.com wrote:
> From: Fei Yang 
> 
> GPU hangs have been observed when multiple engines write to the
> same aux_inv register at the same time. To avoid this each engine
> should only invalidate its own auxiliary table. The function
> gen12_emit_flush_xcs() currently invalidate the auxiliary table for
> all engines because the rq->engine is not necessarily the engine
> eventually carrying out the request, and potentially the engine
> could even be a virtual one (with engine->instance being -1).
> With this patch, auxiliary table invalidation is done only for the
> engine executing the request. And the mmio address for the aux_inv
> register is set after the engine instance becomes certain.
> 
> Signed-off-by: Chris Wilson 
> Signed-off-by: Fei Yang 
> ---
>  drivers/gpu/drm/i915/gt/gen2_engine_cs.c  |  9 +++
>  drivers/gpu/drm/i915/gt/gen6_engine_cs.c  |  9 +++
>  drivers/gpu/drm/i915/gt/gen8_engine_cs.c  | 61 -
> --
>  .../drm/i915/gt/intel_execlists_submission.c  | 35 +++
>  drivers/gpu/drm/i915/i915_request.h   |  2 +
>  5 files changed, 82 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> index 1c82caf525c3..0ec4986e4805 100644
> --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> @@ -37,6 +37,9 @@ int gen2_emit_flush(struct i915_request *rq, u32
> mode)
>  
>   intel_ring_advance(rq, cs);
>  
> + /* hsdes: 1809175790. No fixup needed for gen2 */
> + rq->aux_inv_fixup = NULL;
> +
>   return 0;
>  }
>  
> @@ -123,6 +126,9 @@ int gen4_emit_flush_rcs(struct i915_request *rq,
> u32 mode)
>  
>   intel_ring_advance(rq, cs);
>  
> + /* hsdes: 1809175790. No fixup needed for gen4 rcs */
> + rq->aux_inv_fixup = NULL;
> +
>   return 0;
>  }
>  
> @@ -138,6 +144,9 @@ int gen4_emit_flush_vcs(struct i915_request *rq,
> u32 mode)
>   *cs++ = MI_NOOP;
>   intel_ring_advance(rq, cs);
>  
> + /* hsdes: 1809175790. No fixup needed for gen4 vcs */
> + rq->aux_inv_fixup = NULL;
> +
>   return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
> b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
> index 5e65550b4dfb..efe51c4662fe 100644
> --- a/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen6_engine_cs.c
> @@ -137,6 +137,9 @@ int gen6_emit_flush_rcs(struct i915_request *rq,
> u32 mode)
>   *cs++ = 0;
>   intel_ring_advance(rq, cs);
>  
> + /* hsdes: 1809175790. No fixup needed for gen6 */
> + rq->aux_inv_fixup = NULL;
> +
>   return 0;
>  }
>  
> @@ -208,6 +211,9 @@ static int mi_flush_dw(struct i915_request *rq,
> u32 flags)
>  
>   intel_ring_advance(rq, cs);
>  
> + /* hsdes: 1809175790. No fixup needed for gen6 */
> + rq->aux_inv_fixup = NULL;
> +
>   return 0;
>  }
>  
> @@ -347,6 +353,9 @@ int gen7_emit_flush_rcs(struct i915_request *rq,
> u32 mode)
>   *cs++ = 0;
>   intel_ring_advance(rq, cs);
>  
> + /* hsdes: 1809175790. No fixup needed for gen7 rcs */
> + rq->aux_inv_fixup = NULL;
> +
>   return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index b1b9c3fd7bf9..b6374cf53314 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -73,6 +73,9 @@ int gen8_emit_flush_rcs(struct i915_request *rq,
> u32 mode)
>  
>   intel_ring_advance(rq, cs);
>  
> + /* hsdes: 1809175790. No fixup needed for gen8 rcs */
> + rq->aux_inv_fixup = NULL;
> +
>   return 0;
>  }
>  
> @@ -106,6 +109,9 @@ int gen8_emit_flush_xcs(struct i915_request *rq,
> u32 mode)
>   *cs++ = 0; /* value */
>   intel_ring_advance(rq, cs);
>  
> + /* hsdes: 1809175790. No fixup needed for gen8 xcs */
> + rq->aux_inv_fixup = NULL;
> +
>   return 0;
>  }
>  
> @@ -157,6 +163,9 @@ int gen11_emit_flush_rcs(struct i915_request *rq,
> u32 mode)
>   intel_ring_advance(rq, cs);
>   }
>  
> + /* hsdes: 1809175790. No fixup needed for gen11 rcs */
> + rq->aux_inv_fixup = NULL;

This is a little ugly to me. Can we just set this to 0 or 0xdeadbeef by
default maybe and check that value below instead of retroactively
adding all of these assignments?

> +
>   return 0;
>  }
>  
> @@ -165,30 +174,6 @@ static u32 preparser_disable(bool state)
>   return MI_ARB_CHECK | 1 << 8 | state;
>  }
>  
> -static i915_reg_t aux_inv_reg(const struct intel_engine_cs *engine)
> -{
> - static const i915_reg_t vd[] = {
> - GEN12_VD0_AUX_NV,
> - GEN12_VD1_AUX_NV,
> - GEN12_VD2_AUX_NV,
> - GEN12_VD3_AUX_NV,
> - };
> -
> - static const i915_reg_t ve[] = {
> - GEN12_VE0_AUX_NV,
> - GEN12_VE1_AUX_NV,
> - };
> -
> - if (engine->class == 

[Intel-gfx] ✗ Fi.CI.IGT: failure for Add GuC Error Capture Support

[Patchwork]

== Series Details ==

Series: Add GuC Error Capture Support
URL   : https://patchwork.freedesktop.org/series/101410/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11365_full -> Patchwork_22581_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22581_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22581_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 12)
--

  Missing(1): shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22581_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-render:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-tglb5/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-shrfb-draw-render.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/shard-tglb8/igt@kms_frontbuffer_track...@fbcpsr-1p-offscren-pri-shrfb-draw-render.html

  * igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-edp-1-pipe-a:
- shard-skl:  NOTRUN -> [INCOMPLETE][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/shard-skl4/igt@kms_hdr@bpc-switch-susp...@bpc-switch-suspend-edp-1-pipe-a.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_bad_reloc@negative-reloc-bltcopy:
- {shard-rkl}:[PASS][4] -> [DMESG-WARN][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-rkl-2/igt@gem_bad_re...@negative-reloc-bltcopy.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/shard-rkl-5/igt@gem_bad_re...@negative-reloc-bltcopy.html

  
Known issues


  Here are the changes found in Patchwork_22581_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@chamelium:
- shard-iclb: NOTRUN -> [SKIP][6] ([fdo#111827])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/shard-iclb3/igt@feature_discov...@chamelium.html

  * igt@gem_exec_capture@pi@bcs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][7] ([i915#4547])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/shard-skl9/igt@gem_exec_capture@p...@bcs0.html

  * igt@gem_exec_fair@basic-deadline:
- shard-apl:  NOTRUN -> [FAIL][8] ([i915#2846])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/shard-apl3/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl:  [PASS][9] -> [FAIL][10] ([i915#2842]) +1 similar issue
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-apl7/igt@gem_exec_fair@basic-none-s...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/shard-apl4/igt@gem_exec_fair@basic-none-s...@rcs0.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-tglb6/igt@gem_exec_fair@basic-none-...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/shard-tglb2/igt@gem_exec_fair@basic-none-...@rcs0.html

  * igt@gem_exec_fair@basic-none@rcs0:
- shard-kbl:  [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar 
issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-kbl6/igt@gem_exec_fair@basic-n...@rcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/shard-kbl4/igt@gem_exec_fair@basic-n...@rcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk:  [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk5/igt@gem_exec_fair@basic-pace-sh...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/shard-glk6/igt@gem_exec_fair@basic-pace-sh...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#2842])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/shard-iclb8/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#112283])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/shard-iclb3/igt@gem_exec_par...@secure-non-root.html

  * igt@gem_exec_whisper@basic-queues-forked:
- shard-glk:  [PASS][20] -> 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: avoid concurrent writes to aux_inv (rev5)

[Summers, Stuart]

On Sat, 2022-03-05 at 09:36 +, Patchwork wrote:
Patch Details
Series: drm/i915: avoid concurrent writes to aux_inv (rev5)
URL:https://patchwork.freedesktop.org/series/100772/
State:  failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22492/index.html
CI Bug Log - changes from CI_DRM_11330_full -> Patchwork_22492_full
Summary

FAILURE

Serious unknown changes coming with Patchwork_22492_full absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22492_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

Participating hosts (13 -> 13)

No changes in participating hosts

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_22492_full:

IGT changes
Possible regressions

  *   igt@gem_exec_balancer@fairslice:

 *   shard-tglb: 
PASS
 -> 
FAIL

I don't think the one below is related, but can you check on the above failure 
to make sure that isn't a result of your patch?

Thanks,
Stuart


  *
  *   igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-blt:

 *   shard-tglb: 
PASS
 -> 
INCOMPLETE

Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  *   igt@api_intel_allocator@fork-simple-stress-signal:

 *   {shard-dg1}: 
PASS
 -> 
TIMEOUT
  *   igt@drm_import_export@import-close-race-prime:

 *   {shard-rkl}: 
PASS
 -> 
INCOMPLETE
 +1 similar issue
  *   
{igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale}:

 *   {shard-rkl}: NOTRUN -> 
SKIP
 +2 similar issues
  *   igt@prime_mmap_coherency@ioctl-errors:

 *   {shard-dg1}: NOTRUN -> 
SKIP

Known issues

Here are the changes found in Patchwork_22492_full that come from known issues:

CI changes
Possible fixes

  *   boot:
 *   shard-glk: 
(PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
PASS,
 
FAIL,
 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display/: Refactor hsw_crtc_enable for bigjoiner cleanup

[Patchwork]

== Series Details ==

Series: drm/i915/display/: Refactor hsw_crtc_enable for bigjoiner cleanup
URL   : https://patchwork.freedesktop.org/series/101409/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11365_full -> Patchwork_22580_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22580_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22580_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 12)
--

  Missing(1): shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22580_full:

### IGT changes ###

 Possible regressions 

  * 
igt@kms_plane_scaling@scaler-with-pixel-format-unity-scaling@pipe-b-edp-1-scaler-with-pixel-format:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-iclb1/igt@kms_plane_scaling@scaler-with-pixel-format-unity-scal...@pipe-b-edp-1-scaler-with-pixel-format.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22580/shard-iclb2/igt@kms_plane_scaling@scaler-with-pixel-format-unity-scal...@pipe-b-edp-1-scaler-with-pixel-format.html

  
Known issues


  Here are the changes found in Patchwork_22580_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-glk:  ([PASS][3], [PASS][4], [PASS][5], [PASS][6], 
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], 
[PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], 
[PASS][31], [FAIL][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], 
[PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], 
[PASS][49], [PASS][50], [PASS][51], [PASS][52]) ([i915#4392])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk1/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk1/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk1/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk2/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk2/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk2/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk3/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk3/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk4/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk4/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk4/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk5/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk5/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk6/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk6/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk6/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk7/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk7/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk7/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk8/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk8/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk8/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk9/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk9/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk9/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22580/shard-glk9/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22580/shard-glk9/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22580/shard-glk8/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22580/shard-glk8/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22580/shard-glk8/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22580/shard-glk8/boot.html
   [34]: 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: General multicast steering updates (rev2)

[Matt Roper]

On Tue, Mar 15, 2022 at 05:10:28PM -0700, Matt Roper wrote:
> On Tue, Mar 15, 2022 at 11:39:41PM +, Patchwork wrote:
> > == Series Details ==
> > 
> > Series: i915: General multicast steering updates (rev2)
> > URL   : https://patchwork.freedesktop.org/series/101367/
> > State : failure
> > 
> > == Summary ==
> > 
> > CI Bug Log - changes from CI_DRM_11365_full -> Patchwork_22574_full
> > 
> > 
> > Summary
> > ---
> > 
> >   **FAILURE**
> > 
> >   Serious unknown changes coming with Patchwork_22574_full absolutely need 
> > to be
> >   verified manually.
> >   
> >   If you think the reported changes have nothing to do with the changes
> >   introduced in Patchwork_22574_full, please notify your bug team to allow 
> > them
> >   to document this new failure mode, which will reduce false positives in 
> > CI.
> > 
> >   
> > 
> > Participating hosts (13 -> 13)
> > --
> > 
> >   No changes in participating hosts
> > 
> > Possible new issues
> > ---
> > 
> >   Here are the unknown changes that may have been introduced in 
> > Patchwork_22574_full:
> > 
> > ### IGT changes ###
> > 
> >  Possible regressions 
> > 
> >   * igt@gem_exec_whisper@basic-fds-forked-all:
> > - shard-kbl:  [PASS][1] -> [INCOMPLETE][2]
> >[1]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-kbl6/igt@gem_exec_whis...@basic-fds-forked-all.html
> >[2]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-kbl4/igt@gem_exec_whis...@basic-fds-forked-all.html
> 
> <4> [222.484874] general protection fault, probably for non-canonical address 
> 0x6b6b6b6b6b6b7c23:  [#1] PREEMPT SMP PTI
> <4> [222.484889] CPU: 3 PID: 1279 Comm: gem_exec_whispe Not tainted 
> 5.17.0-rc8-CI-Patchwork_22574+ #1
> <4> [222.484899] Hardware name:  /NUC7i5BNB, BIOS 
> BNKBL357.86A.0054.2017.1025.1822 10/25/2017
> <4> [222.484906] RIP: 0010:__lock_acquire+0x612/0x2940
> 
> This implies a use-after-free mistake somewhere; it wouldn't be caused
> by the steering changes in this series.
> 
> I see a similar stack trace and error on a different test/platform here:
> https://gitlab.freedesktop.org/drm/intel/-/issues/5268 which might be
> caused by the same underlying bug.

Since this failure seems unrelated to this series, patches applied to
drm-intel-gt-next (with the one extra 'const' suggested by sparse
added).  Thanks Jose and Lucas for the reviews.


Matt

> 
> 
> Matt
> 
> > 
> >   
> >  Suppressed 
> > 
> >   The following results come from untrusted machines, tests, or statuses.
> >   They do not affect the overall result.
> > 
> >   * igt@gem_bad_reloc@negative-reloc-bltcopy:
> > - {shard-rkl}:[PASS][3] -> [DMESG-WARN][4]
> >[3]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-rkl-2/igt@gem_bad_re...@negative-reloc-bltcopy.html
> >[4]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-rkl-5/igt@gem_bad_re...@negative-reloc-bltcopy.html
> > 
> >   * igt@gem_ccs@block-copy-inplace:
> > - {shard-dg1}:NOTRUN -> [SKIP][5]
> >[5]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-dg1-12/igt@gem_...@block-copy-inplace.html
> > 
> >   * igt@gem_exec_schedule@submit-early-slice@vecs0:
> > - {shard-dg1}:NOTRUN -> [INCOMPLETE][6]
> >[6]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-dg1-15/igt@gem_exec_schedule@submit-early-sl...@vecs0.html
> > 
> >   
> > Known issues
> > 
> > 
> >   Here are the changes found in Patchwork_22574_full that come from known 
> > issues:
> > 
> > ### IGT changes ###
> > 
> >  Issues hit 
> > 
> >   * igt@feature_discovery@chamelium:
> > - shard-iclb: NOTRUN -> [SKIP][7] ([fdo#111827])
> >[7]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-iclb2/igt@feature_discov...@chamelium.html
> > 
> >   * igt@gem_eio@unwedge-stress:
> > - shard-tglb: [PASS][8] -> [TIMEOUT][9] ([i915#3063] / 
> > [i915#3648])
> >[8]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-tglb7/igt@gem_...@unwedge-stress.html
> >[9]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-tglb7/igt@gem_...@unwedge-stress.html
> > 
> >   * igt@gem_exec_fair@basic-deadline:
> > - shard-skl:  NOTRUN -> [FAIL][10] ([i915#2846])
> >[10]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-skl6/igt@gem_exec_f...@basic-deadline.html
> > 
> >   * igt@gem_exec_fair@basic-none-vip@rcs0:
> > - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842])
> >[11]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-tglb6/igt@gem_exec_fair@basic-none-...@rcs0.html
> >[12]: 
> > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-tglb5/igt@gem_exec_fair@basic-none-...@rcs0.html
> > 
> >   * igt@gem_exec_fair@basic-none@vcs0:
> >   

[Intel-gfx] ✓ Fi.CI.BAT: success for Add GuC Error Capture Support

[Patchwork]

== Series Details ==

Series: Add GuC Error Capture Support
URL   : https://patchwork.freedesktop.org/series/101410/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11365 -> Patchwork_22581


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/index.html

Participating hosts (48 -> 38)
--

  Additional (1): fi-kbl-soraka 
  Missing(11): fi-rkl-guc shard-tglu bat-dg1-6 fi-hsw-4200u bat-dg2-9 
fi-bsw-cyan fi-ctg-p8600 bat-rpls-1 shard-rkl shard-dg1 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_22581 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271]) +9 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][4] ([i915#1886])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@dp-edid-read:
- fi-kbl-soraka:  NOTRUN -> [SKIP][5] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#533])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}:   [FAIL][7] ([i915#5323]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-rpls-2/igt@i915_pm_...@module-reload.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/bat-rpls-2/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@gtt:
- fi-bdw-5557u:   [DMESG-FAIL][9] ([i915#3674]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html

  * igt@i915_selftest@live@migrate:
- {bat-rpls-2}:   [DMESG-WARN][11] ([i915#4391]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-rpls-2/igt@i915_selftest@l...@migrate.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/bat-rpls-2/igt@i915_selftest@l...@migrate.html

  * igt@i915_selftest@live@workarounds:
- {bat-adlp-6}:   [DMESG-WARN][13] ([i915#5068]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/bat-adlp-6/igt@i915_selftest@l...@workarounds.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}:   [DMESG-WARN][15] ([i915#3576]) -> [PASS][16] +1 
similar issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22581/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3674]: https://gitlab.freedesktop.org/drm/intel/issues/3674
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068
  [i915#5323]: https://gitlab.freedesktop.org/drm/intel/issues/5323
  [i915#533]: 

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: More DRRS work (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: More DRRS work (rev2)
URL   : https://patchwork.freedesktop.org/series/101390/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11365_full -> Patchwork_22579_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22579_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22579_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 12)
--

  Missing(1): shard-dg1 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22579_full:

### IGT changes ###

 Possible regressions 

  * igt@i915_suspend@sysfs-reader:
- shard-kbl:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-kbl4/igt@i915_susp...@sysfs-reader.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/shard-kbl3/igt@i915_susp...@sysfs-reader.html

  
Known issues


  Here are the changes found in Patchwork_22579_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@chamelium:
- shard-iclb: NOTRUN -> [SKIP][3] ([fdo#111827])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/shard-iclb7/igt@feature_discov...@chamelium.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][4] -> [TIMEOUT][5] ([i915#3063] / [i915#3648])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-tglb7/igt@gem_...@unwedge-stress.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/shard-tglb6/igt@gem_...@unwedge-stress.html
- shard-skl:  [PASS][6] -> [TIMEOUT][7] ([i915#3063])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-skl4/igt@gem_...@unwedge-stress.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/shard-skl4/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
- shard-skl:  NOTRUN -> [FAIL][8] ([i915#2846])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/shard-skl10/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-tglb6/igt@gem_exec_fair@basic-none-...@rcs0.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/shard-tglb5/igt@gem_exec_fair@basic-none-...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842]) +1 similar 
issue
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/shard-iclb6/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][13] ([fdo#112283])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/shard-iclb7/igt@gem_exec_par...@secure-non-root.html

  * igt@gem_lmem_swapping@heavy-multi:
- shard-apl:  NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/shard-apl1/igt@gem_lmem_swapp...@heavy-multi.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-iclb: NOTRUN -> [SKIP][15] ([i915#4613])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/shard-iclb7/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) +4 
similar issues
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/shard-skl6/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_userptr_blits@access-control:
- shard-iclb: NOTRUN -> [SKIP][17] ([i915#3297])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/shard-iclb5/igt@gem_userptr_bl...@access-control.html

  * igt@gem_userptr_blits@vma-merge:
- shard-skl:  NOTRUN -> [FAIL][18] ([i915#3318])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/shard-skl10/igt@gem_userptr_bl...@vma-merge.html

  * igt@gen3_render_mixed_blits:
- shard-iclb: NOTRUN -> [SKIP][19] ([fdo#109289])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/shard-iclb7/igt@gen3_render_mixed_blits.html

  * igt@gen9_exec_parse@allowed-all:
- shard-glk:  [PASS][20] -> [DMESG-WARN][21] ([i915#1436] / 
[i915#716])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk1/igt@gen9_exec_pa...@allowed-all.html
   [21]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add GuC Error Capture Support

[Patchwork]

== Series Details ==

Series: Add GuC Error Capture Support
URL   : https://patchwork.freedesktop.org/series/101410/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add GuC Error Capture Support

[Patchwork]

== Series Details ==

Series: Add GuC Error Capture Support
URL   : https://patchwork.freedesktop.org/series/101410/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
287e39ce2771 drm/i915/guc: Update GuC ADS size for error capture lists
-:40: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#40: 
new file mode 100644

-:471: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'regslist' - possible 
side-effects?
#471: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:63:
+#define MAKE_REGLIST(regslist, regsowner, regstype, class) \
+   { \
+   regslist, \
+   ARRAY_SIZE(regslist), \
+   TO_GCAP_DEF_OWNER(regsowner), \
+   TO_GCAP_DEF_TYPE(regstype), \
+   class, \
+   }

-:691: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#691: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:283:
+   if (!caplist) {
+   drm_dbg(>drm, "GuC-capture: failed to alloc cached 
caplist");

-:733: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#733: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:325:
+   if (!null_header) {
+   drm_dbg(>drm, "GuC-capture: failed to alloc cached 
nulllist");

total: 0 errors, 3 warnings, 1 checks, 751 lines checked
7f37017607c0 drm/i915/guc: Add XE_LP static registers for GuC error capture.
-:26: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#26: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:25:
+#define COMMON_GEN12BASE_GLOBAL() \
+   {GEN12_FAULT_TLB_DATA0,0,  0, "GEN12_FAULT_TLB_DATA0"}, \
+   {GEN12_FAULT_TLB_DATA1,0,  0, "GEN12_FAULT_TLB_DATA1"}, \
+   {FORCEWAKE_MT, 0,  0, "FORCEWAKE"}, \
+   {GEN12_AUX_ERR_DBG,0,  0, "AUX_ERR_DBG"}, \
+   {GEN12_GAM_DONE,   0,  0, "GAM_DONE"}, \
+   {GEN12_RING_FAULT_REG, 0,  0, "FAULT_REG"}

-:34: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#34: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:33:
+#define COMMON_GEN12BASE_ENGINE_INSTANCE() \
+   {RING_PSMI_CTL(0), 0,  0, "RC PSMI"}, \
+   {RING_ESR(0),  0,  0, "ESR"}, \
+   {RING_DMA_FADD(0), 0,  0, "RING_DMA_FADD_LDW"}, \
+   {RING_DMA_FADD_UDW(0), 0,  0, "RING_DMA_FADD_UDW"}, \
+   {RING_IPEIR(0),0,  0, "IPEIR"}, \
+   {RING_IPEHR(0),0,  0, "IPEHR"}, \
+   {RING_INSTPS(0),   0,  0, "INSTPS"}, \
+   {RING_BBADDR(0),   0,  0, "RING_BBADDR_LOW32"}, \
+   {RING_BBADDR_UDW(0),   0,  0, "RING_BBADDR_UP32"}, \
+   {RING_BBSTATE(0),  0,  0, "BB_STATE"}, \
+   {CCID(0),  0,  0, "CCID"}, \
+   {RING_ACTHD(0),0,  0, "ACTHD_LDW"}, \
+   {RING_ACTHD_UDW(0),0,  0, "ACTHD_UDW"}, \
+   {RING_INSTPM(0),   0,  0, "INSTPM"}, \
+   {RING_INSTDONE(0), 0,  0, "INSTDONE"}, \
+   {RING_NOPID(0),0,  0, "RING_NOPID"}, \
+   {RING_START(0),0,  0, "START"}, \
+   {RING_HEAD(0), 0,  0, "HEAD"}, \
+   {RING_TAIL(0), 0,  0, "TAIL"}, \
+   {RING_CTL(0),  0,  0, "CTL"}, \
+   {RING_MI_MODE(0),  0,  0, "MODE"}, \
+   {RING_CONTEXT_CONTROL(0),  0,  0, "RING_CONTEXT_CONTROL"}, \
+   {RING_HWS_PGA(0),  0,  0, "HWS"}, \
+   {RING_MODE_GEN7(0),0,  0, "GFX_MODE"}, \
+   {GEN8_RING_PDP_LDW(0, 0),  0,  0, "PDP0_LDW"}, \
+   {GEN8_RING_PDP_UDW(0, 0),  0,  0, "PDP0_UDW"}, \
+   {GEN8_RING_PDP_LDW(0, 1),  0,  0, "PDP1_LDW"}, \
+   {GEN8_RING_PDP_UDW(0, 1),  0,  0, "PDP1_UDW"}, \
+   {GEN8_RING_PDP_LDW(0, 2),  0,  0, "PDP2_LDW"}, \
+   {GEN8_RING_PDP_UDW(0, 2),  0,  0, "PDP2_UDW"}, \
+   {GEN8_RING_PDP_LDW(0, 3),  0,  0, "PDP3_LDW"}, \
+   {GEN8_RING_PDP_UDW(0, 3),  0,  0, "PDP3_UDW"}

-:71: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#71: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:70:
+#define COMMON_GEN12BASE_RENDER() \
+   {GEN7_SC_INSTDONE, 0,  0, "GEN7_SC_INSTDONE"}, \
+   {GEN12_SC_INSTDONE_EXTRA,  0,  0, "GEN12_SC_INSTDONE_EXTRA"}, \
+   {GEN12_SC_INSTDONE_EXTRA2, 0,  0, "GEN12_SC_INSTDONE_EXTRA2"}

-:76: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#76: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:75:
+#define COMMON_GEN12BASE_VEC() \
+   {GEN12_SFC_DONE(0),0,  0, "SFC_DONE[0]"}, \
+   {GEN12_SFC_DONE(1),0,  0, "SFC_DONE[1]"}, \
+   {GEN12_SFC_DONE(2),0,  0, "SFC_DONE[2]"}, \
+   {GEN12_SFC_DONE(3),0,  0, 

[Intel-gfx] [PATCH v10 07/13] drm/i915/guc: Update GuC-log relay function names

[Alan Previn]

For the sake of better code readibility, change previous
relay logging function names with "capture_logs" to
"copy_debug_logs" to differentiate from error capture
functions that will use a different region of the same buffer.

Signed-off-by: Alan Previn 
Reviewed-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 35 --
 1 file changed, 19 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index a24dc6441872..0d63c411080f 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -12,7 +12,7 @@
 #include "i915_memcpy.h"
 #include "intel_guc_log.h"
 
-static void guc_log_capture_logs(struct intel_guc_log *log);
+static void guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log);
 
 /**
  * DOC: GuC firmware log
@@ -198,7 +198,7 @@ static unsigned int guc_get_log_buffer_size(enum 
guc_log_buffer_type type)
return 0;
 }
 
-static void guc_read_update_log_buffer(struct intel_guc_log *log)
+static void _guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
 {
unsigned int buffer_size, read_offset, write_offset, bytes_to_copy, 
full_cnt;
struct guc_log_buffer_state *log_buf_state, *log_buf_snapshot_state;
@@ -223,7 +223,7 @@ static void guc_read_update_log_buffer(struct intel_guc_log 
*log)
 * Used rate limited to avoid deluge of messages, logs might be
 * getting consumed by User at a slow rate.
 */
-   DRM_ERROR_RATELIMITED("no sub-buffer to capture logs\n");
+   DRM_ERROR_RATELIMITED("no sub-buffer to copy general logs\n");
log->relay.full_count++;
 
goto out_unlock;
@@ -301,15 +301,15 @@ static void guc_read_update_log_buffer(struct 
intel_guc_log *log)
mutex_unlock(>relay.lock);
 }
 
-static void capture_logs_work(struct work_struct *work)
+static void copy_debug_logs_work(struct work_struct *work)
 {
struct intel_guc_log *log =
container_of(work, struct intel_guc_log, relay.flush_work);
 
-   guc_log_capture_logs(log);
+   guc_log_copy_debuglogs_for_relay(log);
 }
 
-static int guc_log_map(struct intel_guc_log *log)
+static int guc_log_relay_map(struct intel_guc_log *log)
 {
void *vaddr;
 
@@ -332,7 +332,7 @@ static int guc_log_map(struct intel_guc_log *log)
return 0;
 }
 
-static void guc_log_unmap(struct intel_guc_log *log)
+static void guc_log_relay_unmap(struct intel_guc_log *log)
 {
lockdep_assert_held(>relay.lock);
 
@@ -343,7 +343,7 @@ static void guc_log_unmap(struct intel_guc_log *log)
 void intel_guc_log_init_early(struct intel_guc_log *log)
 {
mutex_init(>relay.lock);
-   INIT_WORK(>relay.flush_work, capture_logs_work);
+   INIT_WORK(>relay.flush_work, copy_debug_logs_work);
log->relay.started = false;
 }
 
@@ -358,8 +358,11 @@ static int guc_log_relay_create(struct intel_guc_log *log)
lockdep_assert_held(>relay.lock);
GEM_BUG_ON(!log->vma);
 
-/* Keep the size of sub buffers same as shared log buffer */
-   subbuf_size = log->vma->size;
+/*
+ * Keep the size of sub buffers same as shared log buffer
+ * but GuC log-events excludes the error-state-capture logs
+ */
+   subbuf_size = log->vma->size - CAPTURE_BUFFER_SIZE;
 
/*
 * Store up to 8 snapshots, which is large enough to buffer sufficient
@@ -394,13 +397,13 @@ static void guc_log_relay_destroy(struct intel_guc_log 
*log)
log->relay.channel = NULL;
 }
 
-static void guc_log_capture_logs(struct intel_guc_log *log)
+static void guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log)
 {
struct intel_guc *guc = log_to_guc(log);
struct drm_i915_private *dev_priv = guc_to_gt(guc)->i915;
intel_wakeref_t wakeref;
 
-   guc_read_update_log_buffer(log);
+   _guc_log_copy_debuglogs_for_relay(log);
 
/*
 * Generally device is expected to be active only at this
@@ -566,7 +569,7 @@ int intel_guc_log_relay_open(struct intel_guc_log *log)
if (ret)
goto out_unlock;
 
-   ret = guc_log_map(log);
+   ret = guc_log_relay_map(log);
if (ret)
goto out_relay;
 
@@ -616,8 +619,8 @@ void intel_guc_log_relay_flush(struct intel_guc_log *log)
with_intel_runtime_pm(guc_to_gt(guc)->uncore->rpm, wakeref)
guc_action_flush_log(guc);
 
-   /* GuC would have updated log buffer by now, so capture it */
-   guc_log_capture_logs(log);
+   /* GuC would have updated log buffer by now, so copy it */
+   guc_log_copy_debuglogs_for_relay(log);
 }
 
 /*
@@ -646,7 +649,7 @@ void intel_guc_log_relay_close(struct intel_guc_log *log)
 
mutex_lock(>relay.lock);
GEM_BUG_ON(!intel_guc_log_relay_created(log));
-   guc_log_unmap(log);
+   

[Intel-gfx] [PATCH v10 03/13] drm/i915/guc: Add XE_LP steered register lists support

[Alan Previn]

Add the ability for runtime allocation and freeing of
steered register list extentions that depend on the
detected HW config fuses.

Signed-off-by: Alan Previn 
Reviewed-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h |   9 +
 .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 176 --
 2 files changed, 174 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
index 919ed985f09a..6c199433945d 100644
--- a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
@@ -52,6 +52,7 @@ struct __guc_mmio_reg_descr_group {
u32 owner; /* see enum guc_capture_owner */
u32 type; /* see enum guc_capture_type */
u32 engine; /* as per MAX_ENGINE_CLASS */
+   struct __guc_mmio_reg_descr *extlist; /* only used for steered 
registers */
 };
 
 /**
@@ -79,6 +80,14 @@ struct intel_guc_state_capture {
 */
const struct __guc_mmio_reg_descr_group *reglists;
 
+   /**
+* @extlists: allocated table of steered register lists used for 
error-capture state.
+*
+* NOTE: steered registers have multiple instances depending on the HW 
configuration
+* (slices or dual-sub-slices) and thus depends on HW fuses discovered 
at startup
+*/
+   struct __guc_mmio_reg_descr_group *extlists;
+
/**
 * @ads_cache: cached register lists that is ADS format ready
 */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 6152a23289e3..0f2b47139140 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -133,6 +133,7 @@ static const struct __guc_mmio_reg_descr empty_regs_list[] 
= {
TO_GCAP_DEF_OWNER(regsowner), \
TO_GCAP_DEF_TYPE(regstype), \
class, \
+   NULL, \
}
 
 /* List of lists */
@@ -150,28 +151,33 @@ static const struct __guc_mmio_reg_descr_group 
xe_lpd_lists[] = {
 };
 
 static const struct __guc_mmio_reg_descr_group *
-guc_capture_get_device_reglist(struct intel_guc *guc)
+guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists,
+u32 owner, u32 type, u32 id)
 {
-   struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
+   int i;
 
-   if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915) ||
-   IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) {
-   return xe_lpd_lists;
+   if (!reglists)
+   return NULL;
+
+   for (i = 0; reglists[i].list; ++i) {
+   if (reglists[i].owner == owner && reglists[i].type == type &&
+   (reglists[i].engine == id || reglists[i].type == 
GUC_CAPTURE_LIST_TYPE_GLOBAL))
+   return [i];
}
 
return NULL;
 }
 
-static const struct __guc_mmio_reg_descr_group *
-guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists,
-u32 owner, u32 type, u32 id)
+static struct __guc_mmio_reg_descr_group *
+guc_capture_get_one_ext_list(struct __guc_mmio_reg_descr_group *reglists,
+u32 owner, u32 type, u32 id)
 {
int i;
 
if (!reglists)
return NULL;
 
-   for (i = 0; reglists[i].list; ++i) {
+   for (i = 0; reglists[i].extlist; ++i) {
if (reglists[i].owner == owner && reglists[i].type == type &&
(reglists[i].engine == id || reglists[i].type == 
GUC_CAPTURE_LIST_TYPE_GLOBAL))
return [i];
@@ -180,6 +186,127 @@ guc_capture_get_one_list(const struct 
__guc_mmio_reg_descr_group *reglists,
return NULL;
 }
 
+static void guc_capture_free_extlists(struct __guc_mmio_reg_descr_group 
*reglists)
+{
+   int i = 0;
+
+   if (!reglists)
+   return;
+
+   while (reglists[i].extlist)
+   kfree(reglists[i++].extlist);
+}
+
+struct __ext_steer_reg {
+   const char *name;
+   i915_reg_t reg;
+};
+
+static const struct __ext_steer_reg xe_extregs[] = {
+   {"GEN7_SAMPLER_INSTDONE", GEN7_SAMPLER_INSTDONE},
+   {"GEN7_ROW_INSTDONE", GEN7_ROW_INSTDONE}
+};
+
+static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext,
+  const struct __ext_steer_reg *extlist,
+  int slice_id, int subslice_id)
+{
+   ext->reg = extlist->reg;
+   ext->flags = FIELD_PREP(GUC_REGSET_STEERING_GROUP, slice_id);
+   ext->flags |= FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, subslice_id);
+   ext->regname = extlist->name;
+}
+
+static int
+__alloc_ext_regs(struct __guc_mmio_reg_descr_group *newlist,
+const struct __guc_mmio_reg_descr_group *rootlist, int 
num_regs)
+{
+   struct __guc_mmio_reg_descr *list;
+
+   list = kcalloc(num_regs, sizeof(struct 

[Intel-gfx] [PATCH v10 09/13] drm/i915/guc: Check sizing of guc_capture output

[Alan Previn]

Add intel_guc_capture_output_min_size_est function to
provide a reasonable minimum size for error-capture
region before allocating the shared buffer.

Signed-off-by: Alan Previn 
Reviewed-by: Matthew Brost 
---
 .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 48 +++
 .../gpu/drm/i915/gt/uc/intel_guc_capture.h|  1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c|  7 ++-
 3 files changed, 55 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index f9612e45def6..413d1c2e84d1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -663,6 +663,54 @@ intel_guc_capture_getnullheader(struct intel_guc *guc,
return 0;
 }
 
+#define GUC_CAPTURE_OVERBUFFER_MULTIPLIER 3
+int
+intel_guc_capture_output_min_size_est(struct intel_guc *guc)
+{
+   struct intel_gt *gt = guc_to_gt(guc);
+   struct intel_engine_cs *engine;
+   enum intel_engine_id id;
+   int worst_min_size = 0, num_regs = 0;
+   size_t tmp = 0;
+
+   /*
+* If every single engine-instance suffered a failure in quick 
succession but
+* were all unrelated, then a burst of multiple error-capture events 
would dump
+* registers for every one engine instance, one at a time. In this 
case, GuC
+* would even dump the global-registers repeatedly.
+*
+* For each engine instance, there would be 1 x 
guc_state_capture_group_t output
+* followed by 3 x guc_state_capture_t lists. The latter is how the 
register
+* dumps are split across different register types (where the '3' are 
global vs class
+* vs instance). Finally, let's multiply the whole thing by 3x (just so 
we are
+* not limited to just 1 round of data in a worst case full register 
dump log)
+*
+* NOTE: intel_guc_log that allocates the log buffer would round this 
size up to
+* a power of two.
+*/
+
+   for_each_engine(engine, gt, id) {
+   worst_min_size += sizeof(struct 
guc_state_capture_group_header_t) +
+ (3 * sizeof(struct 
guc_state_capture_header_t));
+
+   if (!intel_guc_capture_getlistsize(guc, 0, 
GUC_CAPTURE_LIST_TYPE_GLOBAL, 0, ))
+   num_regs += tmp;
+
+   if (!intel_guc_capture_getlistsize(guc, 0, 
GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS,
+  engine->class, )) {
+   num_regs += tmp;
+   }
+   if (!intel_guc_capture_getlistsize(guc, 0, 
GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE,
+  engine->class, )) {
+   num_regs += tmp;
+   }
+   }
+
+   worst_min_size += (num_regs * sizeof(struct guc_mmio_reg));
+
+   return (worst_min_size * GUC_CAPTURE_OVERBUFFER_MULTIPLIER);
+}
+
 static void
 guc_capture_free_ads_cache(struct intel_guc_state_capture *gc)
 {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
index 8de7704e12eb..540d72079462 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
@@ -11,6 +11,7 @@
 struct guc_gt_system_info;
 struct intel_guc;
 
+int intel_guc_capture_output_min_size_est(struct intel_guc *guc);
 int intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 
classid,
  void **outptr);
 int intel_guc_capture_getlistsize(struct intel_guc *guc, u32 owner, u32 type, 
u32 classid,
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index fe4b2d3f305d..ed05b1a04f9c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -7,10 +7,11 @@
 #include 
 
 #include "gt/intel_gt.h"
+#include "intel_guc_capture.h"
+#include "intel_guc_log.h"
 #include "i915_drv.h"
 #include "i915_irq.h"
 #include "i915_memcpy.h"
-#include "intel_guc_log.h"
 
 static void guc_log_copy_debuglogs_for_relay(struct intel_guc_log *log);
 
@@ -466,6 +467,10 @@ int intel_guc_log_create(struct intel_guc_log *log)
 *  | Capture logs  |
 *  +===+ + CAPTURE_SIZE
 */
+   if (intel_guc_capture_output_min_size_est(guc) > CAPTURE_BUFFER_SIZE)
+   DRM_WARN("GuC log buffer for state_capture maybe too small. %d 
< %d\n",
+CAPTURE_BUFFER_SIZE, 
intel_guc_capture_output_min_size_est(guc));
+
guc_log_size = PAGE_SIZE + CRASH_BUFFER_SIZE + DEBUG_BUFFER_SIZE +
   CAPTURE_BUFFER_SIZE;
 
-- 
2.25.1

[Intel-gfx] [PATCH v10 11/13] drm/i915/guc: Pre-allocate output nodes for extraction

[Alan Previn]

In the rare but possible scenario where we are in the midst of
multiple GuC error-capture (and engine reset) events and the
user also triggers a forced full GT reset or the internal watchdog
triggers the same, intel_guc_submission_reset_prepare's call
to flush_work(>ct.requests.worker) can cause the G2H message
handler to trigger intel_guc_capture_store_snapshot upon
receiving new G2H error-capture notifications. This can happen
despite the prior call to disable_submission(guc);. However,
there's no race-free way for intel_guc_capture_store_snapshot to
know that we are in the midst of a reset. That said, we can never
dynamically allocate the output nodes in this handler. Thus, we
shall pre-allocate a fixed number of empty nodes up front (at the
time of ADS registration) that we can consume from or return to
an internal cached list of nodes.

Signed-off-by: Alan Previn 
Reviewed-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h |  19 +-
 .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 177 ++
 2 files changed, 161 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
index 5d959e62d146..3624abfd22d1 100644
--- a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
@@ -31,7 +31,7 @@ struct __guc_capture_bufstate {
  *
  * A single unit of extracted error-capture output data grouped together
  * at an engine-instance level. We keep these nodes in a linked list.
- * See outlist below.
+ * See cachelist and outlist below.
  */
 struct __guc_capture_parsed_output {
/*
@@ -190,7 +190,22 @@ struct intel_guc_state_capture {
void *ads_null_cache;
 
/**
-* @outlist: allocated nodes with parsed engine-instance error capture 
data
+* @cachelist: Pool of pre-allocated nodes for error capture output
+*
+* We need this pool of pre-allocated nodes because we cannot
+* dynamically allocate new nodes when receiving the G2H notification
+* because the event handlers for all G2H event-processing is called
+* by the ct processing worker queue and when that queue is being
+* processed, there is no absoluate guarantee that we are not in the
+* midst of a GT reset operation (which doesn't allow allocations).
+*/
+   struct list_head cachelist;
+#define PREALLOC_NODES_MAX_COUNT (3 * GUC_MAX_ENGINE_CLASSES * 
GUC_MAX_INSTANCES_PER_CLASS)
+#define PREALLOC_NODES_DEFAULT_NUMREGS 64
+   int max_mmio_per_node;
+
+   /**
+* @outlist: Pool of pre-allocated nodes for error capture output
 *
 * A linked list of parsed GuC error-capture output data before
 * reporting with formatting via i915_gpu_coredump. Each node in this 
linked list shall
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 776221d525fd..0f3852591096 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -581,6 +581,8 @@ intel_guc_capture_getlistsize(struct intel_guc *guc, u32 
owner, u32 type, u32 cl
return 0;
 }
 
+static void guc_capture_create_prealloc_nodes(struct intel_guc *guc);
+
 int
 intel_guc_capture_getlist(struct intel_guc *guc, u32 owner, u32 type, u32 
classid,
  void **outptr)
@@ -601,6 +603,12 @@ intel_guc_capture_getlist(struct intel_guc *guc, u32 
owner, u32 type, u32 classi
return cache->status;
}
 
+   /*
+* ADS population of input registers is a good
+* time to pre-allocate cachelist output nodes
+*/
+   guc_capture_create_prealloc_nodes(guc);
+
ret = intel_guc_capture_getlistsize(guc, owner, type, classid, );
if (ret) {
cache->is_valid = true;
@@ -741,7 +749,8 @@ intel_guc_capture_output_min_size_est(struct intel_guc *guc)
  *err-state-captured register-list we find, we 
alloc 'C':
  *  --> alloc C: A capture-output-node structure that includes misc 
capture info along
  *   with 3 register list dumps (global, engine-class and 
engine-instance)
- *   This node is dynamically allocated and populated with the 
error-capture
+ *   This node is created from a pre-allocated list of blank 
nodes in
+ *   guc->capture->cachelist and populated with the 
error-capture
  *   data from GuC and then it's added into 
guc->capture->outlist linked
  *   list. This list is used for matchup and printout by 
i915_gpu_coredump
  *   and err_print_gt, (when user invokes the error capture 
sysfs).
@@ -901,19 +910,20 @@ guc_capture_delete_one_node(struct intel_guc *guc, struct 
__guc_capture_parsed_o
 }
 
 static void
-guc_capture_delete_nodes(struct intel_guc *guc)

[Intel-gfx] [PATCH v10 06/13] drm/i915/guc: Add GuC's error state capture output structures.

[Alan Previn]

Add GuC's error capture output structures and definitions as how
they would appear in GuC log buffer's error capture subregion after
an error state capture G2H event notification.

Signed-off-by: Alan Previn 
Reviewed-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 47 +++
 1 file changed, 47 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
index 6c199433945d..8824c5eba355 100644
--- a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
@@ -55,6 +55,53 @@ struct __guc_mmio_reg_descr_group {
struct __guc_mmio_reg_descr *extlist; /* only used for steered 
registers */
 };
 
+/**
+ * struct guc_state_capture_header_t / struct guc_state_capture_t /
+ * guc_state_capture_group_header_t / guc_state_capture_group_t
+ *
+ * Prior to resetting engines that have hung or faulted, GuC microkernel
+ * reports the engine error-state (register values that was read) by
+ * logging them into the shared GuC log buffer using these hierarchy
+ * of structures.
+ */
+struct guc_state_capture_header_t {
+   u32 owner;
+#define CAP_HDR_CAPTURE_VFID GENMASK(7, 0)
+   u32 info;
+#define CAP_HDR_CAPTURE_TYPE GENMASK(3, 0) /* see enum guc_capture_type */
+#define CAP_HDR_ENGINE_CLASS GENMASK(7, 4) /* see GUC_MAX_ENGINE_CLASSES */
+#define CAP_HDR_ENGINE_INSTANCE GENMASK(11, 8)
+   u32 lrca; /* if type-instance, LRCA (address) that hung, else set to ~0 
*/
+   u32 guc_id; /* if type-instance, context index of hung context, else 
set to ~0 */
+   u32 num_mmios;
+#define CAP_HDR_NUM_MMIOS GENMASK(9, 0)
+} __packed;
+
+struct guc_state_capture_t {
+   struct guc_state_capture_header_t header;
+   struct guc_mmio_reg mmio_entries[0];
+} __packed;
+
+enum guc_capture_group_types {
+   GUC_STATE_CAPTURE_GROUP_TYPE_FULL,
+   GUC_STATE_CAPTURE_GROUP_TYPE_PARTIAL,
+   GUC_STATE_CAPTURE_GROUP_TYPE_MAX,
+};
+
+struct guc_state_capture_group_header_t {
+   u32 owner;
+#define CAP_GRP_HDR_CAPTURE_VFID GENMASK(7, 0)
+   u32 info;
+#define CAP_GRP_HDR_NUM_CAPTURES GENMASK(7, 0)
+#define CAP_GRP_HDR_CAPTURE_TYPE GENMASK(15, 8) /* guc_capture_group_types */
+} __packed;
+
+/* this is the top level structure where an error-capture dump starts */
+struct guc_state_capture_group_t {
+   struct guc_state_capture_group_header_t grp_header;
+   struct guc_state_capture_t capture_entries[0];
+} __packed;
+
 /**
  * struct __guc_capture_ads_cache
  *
-- 
2.25.1

[Intel-gfx] [PATCH v10 05/13] drm/i915/guc: Add Gen9 registers for GuC error state capture.

[Alan Previn]

Abstract out a Gen9 register list as the default for all other
platforms we don't yet formally support GuC submission on.

Signed-off-by: Alan Previn 
Reviewed-by: Umesh Nerlige Ramappa 
---
 .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 82 +--
 1 file changed, 59 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 15fc36203463..f9612e45def6 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -22,15 +22,24 @@
  * NOTE1: For engine-registers, GuC only needs the register offsets
  *from the engine-mmio-base
  */
+#define COMMON_BASE_GLOBAL() \
+   {FORCEWAKE_MT, 0,  0, "FORCEWAKE"}
+
+#define COMMON_GEN9BASE_GLOBAL() \
+   {GEN8_FAULT_TLB_DATA0, 0,  0, "GEN8_FAULT_TLB_DATA0"}, \
+   {GEN8_FAULT_TLB_DATA1, 0,  0, "GEN8_FAULT_TLB_DATA1"}, \
+   {ERROR_GEN6,   0,  0, "ERROR_GEN6"}, \
+   {DONE_REG, 0,  0, "DONE_REG"}, \
+   {HSW_GTT_CACHE_EN, 0,  0, "HSW_GTT_CACHE_EN"}
+
 #define COMMON_GEN12BASE_GLOBAL() \
{GEN12_FAULT_TLB_DATA0,0,  0, "GEN12_FAULT_TLB_DATA0"}, \
{GEN12_FAULT_TLB_DATA1,0,  0, "GEN12_FAULT_TLB_DATA1"}, \
-   {FORCEWAKE_MT, 0,  0, "FORCEWAKE"}, \
{GEN12_AUX_ERR_DBG,0,  0, "AUX_ERR_DBG"}, \
{GEN12_GAM_DONE,   0,  0, "GAM_DONE"}, \
{GEN12_RING_FAULT_REG, 0,  0, "FAULT_REG"}
 
-#define COMMON_GEN12BASE_ENGINE_INSTANCE() \
+#define COMMON_BASE_ENGINE_INSTANCE() \
{RING_PSMI_CTL(0), 0,  0, "RC PSMI"}, \
{RING_ESR(0),  0,  0, "ESR"}, \
{RING_DMA_FADD(0), 0,  0, "RING_DMA_FADD_LDW"}, \
@@ -64,11 +73,13 @@
{GEN8_RING_PDP_LDW(0, 3),  0,  0, "PDP3_LDW"}, \
{GEN8_RING_PDP_UDW(0, 3),  0,  0, "PDP3_UDW"}
 
-#define COMMON_GEN12BASE_HAS_EU() \
+#define COMMON_BASE_HAS_EU() \
{EIR,  0,  0, "EIR"}
 
+#define COMMON_BASE_RENDER() \
+   {GEN7_SC_INSTDONE, 0,  0, "GEN7_SC_INSTDONE"}
+
 #define COMMON_GEN12BASE_RENDER() \
-   {GEN7_SC_INSTDONE, 0,  0, "GEN7_SC_INSTDONE"}, \
{GEN12_SC_INSTDONE_EXTRA,  0,  0, "GEN12_SC_INSTDONE_EXTRA"}, \
{GEN12_SC_INSTDONE_EXTRA2, 0,  0, "GEN12_SC_INSTDONE_EXTRA2"}
 
@@ -80,28 +91,26 @@
 
 /* XE_LPD - Global */
 static const struct __guc_mmio_reg_descr xe_lpd_global_regs[] = {
+   COMMON_BASE_GLOBAL(),
+   COMMON_GEN9BASE_GLOBAL(),
COMMON_GEN12BASE_GLOBAL(),
 };
 
 /* XE_LPD - Render / Compute Per-Class */
 static const struct __guc_mmio_reg_descr xe_lpd_rc_class_regs[] = {
-   COMMON_GEN12BASE_HAS_EU(),
+   COMMON_BASE_HAS_EU(),
+   COMMON_BASE_RENDER(),
COMMON_GEN12BASE_RENDER(),
 };
 
-/* XE_LPD - Render / Compute Per-Engine-Instance */
+/* GEN9/XE_LPD - Render / Compute Per-Engine-Instance */
 static const struct __guc_mmio_reg_descr xe_lpd_rc_inst_regs[] = {
-   COMMON_GEN12BASE_ENGINE_INSTANCE(),
+   COMMON_BASE_ENGINE_INSTANCE(),
 };
 
-/* XE_LPD - Media Decode/Encode Per-Class */
-static const struct __guc_mmio_reg_descr xe_lpd_vd_class_regs[] = {
-   COMMON_GEN12BASE_ENGINE_INSTANCE(),
-};
-
-/* XE_LPD - Media Decode/Encode Per-Engine-Instance */
+/* GEN9/XE_LPD - Media Decode/Encode Per-Engine-Instance */
 static const struct __guc_mmio_reg_descr xe_lpd_vd_inst_regs[] = {
-   COMMON_GEN12BASE_ENGINE_INSTANCE(),
+   COMMON_BASE_ENGINE_INSTANCE(),
 };
 
 /* XE_LPD - Video Enhancement Per-Class */
@@ -109,18 +118,33 @@ static const struct __guc_mmio_reg_descr 
xe_lpd_vec_class_regs[] = {
COMMON_GEN12BASE_VEC(),
 };
 
-/* XE_LPD - Video Enhancement Per-Engine-Instance */
+/* GEN9/XE_LPD - Video Enhancement Per-Engine-Instance */
 static const struct __guc_mmio_reg_descr xe_lpd_vec_inst_regs[] = {
-   COMMON_GEN12BASE_ENGINE_INSTANCE(),
+   COMMON_BASE_ENGINE_INSTANCE(),
 };
 
-/* XE_LPD - Blitter Per-Engine-Instance */
+/* GEN9/XE_LPD - Blitter Per-Engine-Instance */
 static const struct __guc_mmio_reg_descr xe_lpd_blt_inst_regs[] = {
-   COMMON_GEN12BASE_ENGINE_INSTANCE(),
+   COMMON_BASE_ENGINE_INSTANCE(),
 };
 
-/* XE_LPD - Blitter Per-Class */
-/* XE_LPD - Media Decode/Encode Per-Class */
+/* GEN9 - Global */
+static const struct __guc_mmio_reg_descr default_global_regs[] = {
+   COMMON_BASE_GLOBAL(),
+   COMMON_GEN9BASE_GLOBAL(),
+};
+
+static const struct __guc_mmio_reg_descr default_rc_class_regs[] = {
+   COMMON_BASE_HAS_EU(),
+   COMMON_BASE_RENDER(),
+};
+
+/*
+ * Empty lists:
+ * GEN9/XE_LPD - Blitter Per-Class
+ * GEN9/XE_LPD - Media Decode/Encode Per-Class
+ * GEN9 - VEC Class
+ */
 static const struct __guc_mmio_reg_descr empty_regs_list[] = {
 };
 
@@ -137,6 +161,19 @@ static const struct 

[Intel-gfx] [PATCH v10 12/13] drm/i915/guc: Plumb GuC-capture into gpu_coredump

[Alan Previn]

Add a flags parameter through all of the coredump creation
functions. Add a bitmask flag to indicate if the top
level gpu_coredump event is triggered in response to
a GuC context reset notification.

Using that flag, ensure all coredump functions that
read or print mmio-register values related to work submission
or command-streamer engines are skipped and replaced with
a calls guc-capture module equivalent functions to retrieve
or print the register dump.

While here, split out display related register reading
and printing into its own function that is called agnostic
to whether GuC had triggered the reset.

For now, introduce an empty printing function that can
filled in on a subsequent patch just to handle formatting.

Signed-off-by: Alan Previn 
Reviewed-by: Umesh Nerlige Ramappa 
---
 .../drm/i915/gt/intel_execlists_submission.c  |   4 +-
 drivers/gpu/drm/i915/gt/intel_reset.c |   2 +-
 .../gpu/drm/i915/gt/uc/intel_guc_capture.c|  70 +
 .../gpu/drm/i915/gt/uc/intel_guc_capture.h|   9 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |   2 +-
 drivers/gpu/drm/i915/i915_debugfs.c   |   2 +-
 drivers/gpu/drm/i915/i915_gpu_error.c | 266 --
 drivers/gpu/drm/i915/i915_gpu_error.h |  30 +-
 8 files changed, 288 insertions(+), 97 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c 
b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index e1470bb60f34..738c120490fc 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2236,11 +2236,11 @@ static struct execlists_capture *capture_regs(struct 
intel_engine_cs *engine)
if (!cap->error)
goto err_cap;
 
-   cap->error->gt = intel_gt_coredump_alloc(engine->gt, gfp);
+   cap->error->gt = intel_gt_coredump_alloc(engine->gt, gfp, 
CORE_DUMP_FLAG_NONE);
if (!cap->error->gt)
goto err_gpu;
 
-   cap->error->gt->engine = intel_engine_coredump_alloc(engine, gfp);
+   cap->error->gt->engine = intel_engine_coredump_alloc(engine, gfp, 
CORE_DUMP_FLAG_NONE);
if (!cap->error->gt->engine)
goto err_gt;
 
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
b/drivers/gpu/drm/i915/gt/intel_reset.c
index a6ae213c7d89..f52015e79fdf 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1319,7 +1319,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
engine_mask &= gt->info.engine_mask;
 
if (flags & I915_ERROR_CAPTURE) {
-   i915_capture_error_state(gt, engine_mask);
+   i915_capture_error_state(gt, engine_mask, CORE_DUMP_FLAG_NONE);
intel_gt_clear_error_registers(gt, engine_mask);
}
 
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 0f3852591096..8f6031782d20 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -10,6 +10,7 @@
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_regs.h"
+#include "gt/intel_lrc.h"
 #include "guc_capture_fwif.h"
 #include "intel_guc_capture.h"
 #include "intel_guc_fwif.h"
@@ -754,6 +755,18 @@ intel_guc_capture_output_min_size_est(struct intel_guc 
*guc)
  *   data from GuC and then it's added into 
guc->capture->outlist linked
  *   list. This list is used for matchup and printout by 
i915_gpu_coredump
  *   and err_print_gt, (when user invokes the error capture 
sysfs).
+ *
+ * GUC --> notify context reset:
+ * -
+ * --> G2H CONTEXT RESET
+ *   L--> guc_handle_context_reset --> i915_capture_error_state
+ *  L--> i915_gpu_coredump(..IS_GUC_CAPTURE) --> 
gt_record_engines
+ *   --> capture_engine(..IS_GUC_CAPTURE)
+ *   L--> intel_guc_capture_get_matching_node is 
where
+ *detach C from internal linked list and 
add it into
+ *intel_engine_coredump struct (if the 
context and
+ *engine of the event notification matches 
a node
+ *in the link list).
  */
 
 static int guc_capture_buf_cnt(struct __guc_capture_bufstate *buf)
@@ -1369,6 +1382,63 @@ static void __guc_capture_process_output(struct 
intel_guc *guc)
__guc_capture_flushlog_complete(guc);
 }
 
+#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
+
+int intel_guc_capture_print_engine_node(struct drm_i915_error_state_buf *ebuf,
+   const struct intel_engine_coredump *ee)
+{
+   return 0;
+}
+
+#endif //CONFIG_DRM_I915_CAPTURE_ERROR
+
+void intel_guc_capture_free_node(struct intel_engine_coredump *ee)
+{
+   if (!ee || 

[Intel-gfx] [PATCH v10 02/13] drm/i915/guc: Add XE_LP static registers for GuC error capture.

[Alan Previn]

Add device specific tables and register lists to cover different engines
class types for GuC error state capture for XE_LP products.

Signed-off-by: Alan Previn 
Reviewed-by: Umesh Nerlige Ramappa 
---
 .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 116 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   4 +-
 2 files changed, 97 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index ebae0943f0a0..6152a23289e3 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -19,43 +19,109 @@
 
 /*
  * Define all device tables of GuC error capture register lists
- * NOTE: For engine-registers, GuC only needs the register offsets
- *   from the engine-mmio-base
+ * NOTE1: For engine-registers, GuC only needs the register offsets
+ *from the engine-mmio-base
  */
+#define COMMON_GEN12BASE_GLOBAL() \
+   {GEN12_FAULT_TLB_DATA0,0,  0, "GEN12_FAULT_TLB_DATA0"}, \
+   {GEN12_FAULT_TLB_DATA1,0,  0, "GEN12_FAULT_TLB_DATA1"}, \
+   {FORCEWAKE_MT, 0,  0, "FORCEWAKE"}, \
+   {GEN12_AUX_ERR_DBG,0,  0, "AUX_ERR_DBG"}, \
+   {GEN12_GAM_DONE,   0,  0, "GAM_DONE"}, \
+   {GEN12_RING_FAULT_REG, 0,  0, "FAULT_REG"}
+
+#define COMMON_GEN12BASE_ENGINE_INSTANCE() \
+   {RING_PSMI_CTL(0), 0,  0, "RC PSMI"}, \
+   {RING_ESR(0),  0,  0, "ESR"}, \
+   {RING_DMA_FADD(0), 0,  0, "RING_DMA_FADD_LDW"}, \
+   {RING_DMA_FADD_UDW(0), 0,  0, "RING_DMA_FADD_UDW"}, \
+   {RING_IPEIR(0),0,  0, "IPEIR"}, \
+   {RING_IPEHR(0),0,  0, "IPEHR"}, \
+   {RING_INSTPS(0),   0,  0, "INSTPS"}, \
+   {RING_BBADDR(0),   0,  0, "RING_BBADDR_LOW32"}, \
+   {RING_BBADDR_UDW(0),   0,  0, "RING_BBADDR_UP32"}, \
+   {RING_BBSTATE(0),  0,  0, "BB_STATE"}, \
+   {CCID(0),  0,  0, "CCID"}, \
+   {RING_ACTHD(0),0,  0, "ACTHD_LDW"}, \
+   {RING_ACTHD_UDW(0),0,  0, "ACTHD_UDW"}, \
+   {RING_INSTPM(0),   0,  0, "INSTPM"}, \
+   {RING_INSTDONE(0), 0,  0, "INSTDONE"}, \
+   {RING_NOPID(0),0,  0, "RING_NOPID"}, \
+   {RING_START(0),0,  0, "START"}, \
+   {RING_HEAD(0), 0,  0, "HEAD"}, \
+   {RING_TAIL(0), 0,  0, "TAIL"}, \
+   {RING_CTL(0),  0,  0, "CTL"}, \
+   {RING_MI_MODE(0),  0,  0, "MODE"}, \
+   {RING_CONTEXT_CONTROL(0),  0,  0, "RING_CONTEXT_CONTROL"}, \
+   {RING_HWS_PGA(0),  0,  0, "HWS"}, \
+   {RING_MODE_GEN7(0),0,  0, "GFX_MODE"}, \
+   {GEN8_RING_PDP_LDW(0, 0),  0,  0, "PDP0_LDW"}, \
+   {GEN8_RING_PDP_UDW(0, 0),  0,  0, "PDP0_UDW"}, \
+   {GEN8_RING_PDP_LDW(0, 1),  0,  0, "PDP1_LDW"}, \
+   {GEN8_RING_PDP_UDW(0, 1),  0,  0, "PDP1_UDW"}, \
+   {GEN8_RING_PDP_LDW(0, 2),  0,  0, "PDP2_LDW"}, \
+   {GEN8_RING_PDP_UDW(0, 2),  0,  0, "PDP2_UDW"}, \
+   {GEN8_RING_PDP_LDW(0, 3),  0,  0, "PDP3_LDW"}, \
+   {GEN8_RING_PDP_UDW(0, 3),  0,  0, "PDP3_UDW"}
+
+#define COMMON_GEN12BASE_HAS_EU() \
+   {EIR,  0,  0, "EIR"}
+
+#define COMMON_GEN12BASE_RENDER() \
+   {GEN7_SC_INSTDONE, 0,  0, "GEN7_SC_INSTDONE"}, \
+   {GEN12_SC_INSTDONE_EXTRA,  0,  0, "GEN12_SC_INSTDONE_EXTRA"}, \
+   {GEN12_SC_INSTDONE_EXTRA2, 0,  0, "GEN12_SC_INSTDONE_EXTRA2"}
+
+#define COMMON_GEN12BASE_VEC() \
+   {GEN12_SFC_DONE(0),0,  0, "SFC_DONE[0]"}, \
+   {GEN12_SFC_DONE(1),0,  0, "SFC_DONE[1]"}, \
+   {GEN12_SFC_DONE(2),0,  0, "SFC_DONE[2]"}, \
+   {GEN12_SFC_DONE(3),0,  0, "SFC_DONE[3]"}
+
 /* XE_LPD - Global */
 static const struct __guc_mmio_reg_descr xe_lpd_global_regs[] = {
-   {GEN12_RING_FAULT_REG, 0,  0, "GEN12_RING_FAULT_REG"}
+   COMMON_GEN12BASE_GLOBAL(),
 };
 
 /* XE_LPD - Render / Compute Per-Class */
 static const struct __guc_mmio_reg_descr xe_lpd_rc_class_regs[] = {
-   {EIR,  0,  0, "EIR"}
+   COMMON_GEN12BASE_HAS_EU(),
+   COMMON_GEN12BASE_RENDER(),
 };
 
 /* XE_LPD - Render / Compute Per-Engine-Instance */
 static const struct __guc_mmio_reg_descr xe_lpd_rc_inst_regs[] = {
-   {RING_HEAD(0), 0,  0, "RING_HEAD"},
-   {RING_TAIL(0), 0,  0, "RING_TAIL"},
+   COMMON_GEN12BASE_ENGINE_INSTANCE(),
 };
 
 /* XE_LPD - Media Decode/Encode Per-Class */
 static const struct __guc_mmio_reg_descr xe_lpd_vd_class_regs[] = {
+   COMMON_GEN12BASE_ENGINE_INSTANCE(),
 };
 
 /* XE_LPD - Media Decode/Encode Per-Engine-Instance */
 static const struct 

[Intel-gfx] [PATCH v10 08/13] drm/i915/guc: Add capture region into intel_guc_log

[Alan Previn]

GuC log buffer regions for debug-log-events, crash-dumps and
error-state-capture are all part of a single bo allocation that
also includes the guc_log_buffer_state structures. Now that we
support it, increase the size allocation for error-capture.

Since the error-capture region is accessed at non-deterministic
times (as part of GuC triggered context reset) while debug-log-
events region is accessed as part of relay logging or during
debugfs triggered dumps, move the mapping and unmapping of the
shared buffer into intel_guc_log_create and intel_guc_log_destroy
so that it's always mapped throughout life of GuC operation.

Additionally, while here, update the guc log region layout
diagram to follow the order according to the enum definition
as per the GuC interface.

NOTE: A future effort to visit (part of baseline code) is that
buf_addr should be updated to be a io_sys_map and use the
io_sys_map wrapper functions to access the various GuC log
buffer regions.

Signed-off-by: Alan Previn 
Reviewed-by: Matthew Brost 
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 59 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.h |  3 +-
 2 files changed, 37 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index 0d63c411080f..fe4b2d3f305d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -26,7 +26,8 @@ static void guc_log_copy_debuglogs_for_relay(struct 
intel_guc_log *log);
 static int guc_action_flush_log_complete(struct intel_guc *guc)
 {
u32 action[] = {
-   INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE
+   INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE,
+   GUC_DEBUG_LOG_BUFFER
};
 
return intel_guc_send(guc, action, ARRAY_SIZE(action));
@@ -137,7 +138,7 @@ static void guc_move_to_next_buf(struct intel_guc_log *log)
smp_wmb();
 
/* All data has been written, so now move the offset of sub buffer. */
-   relay_reserve(log->relay.channel, log->vma->obj->base.size);
+   relay_reserve(log->relay.channel, log->vma->obj->base.size - 
CAPTURE_BUFFER_SIZE);
 
/* Switch to the next sub buffer */
relay_flush(log->relay.channel);
@@ -213,7 +214,8 @@ static void _guc_log_copy_debuglogs_for_relay(struct 
intel_guc_log *log)
goto out_unlock;
 
/* Get the pointer to shared GuC log buffer */
-   log_buf_state = src_data = log->relay.buf_addr;
+   src_data = log->buf_addr;
+   log_buf_state = src_data;
 
/* Get the pointer to local buffer to store the logs */
log_buf_snapshot_state = dst_data = guc_get_write_buffer(log);
@@ -233,7 +235,8 @@ static void _guc_log_copy_debuglogs_for_relay(struct 
intel_guc_log *log)
src_data += PAGE_SIZE;
dst_data += PAGE_SIZE;
 
-   for (type = GUC_DEBUG_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
+   /* For relay logging, we exclude error state capture */
+   for (type = GUC_DEBUG_LOG_BUFFER; type <= GUC_CRASH_DUMP_LOG_BUFFER; 
type++) {
/*
 * Make a copy of the state structure, inside GuC log buffer
 * (which is uncached mapped), on the stack to avoid reading
@@ -311,23 +314,17 @@ static void copy_debug_logs_work(struct work_struct *work)
 
 static int guc_log_relay_map(struct intel_guc_log *log)
 {
-   void *vaddr;
-
lockdep_assert_held(>relay.lock);
 
-   if (!log->vma)
+   if (!log->vma || !log->buf_addr)
return -ENODEV;
 
/*
-* Create a WC (Uncached for read) vmalloc mapping of log
-* buffer pages, so that we can directly get the data
-* (up-to-date) from memory.
+* WC vmalloc mapping of log buffer pages was done at
+* GuC Log Init time, but lets keep a ref for book-keeping
 */
-   vaddr = i915_gem_object_pin_map_unlocked(log->vma->obj, I915_MAP_WC);
-   if (IS_ERR(vaddr))
-   return PTR_ERR(vaddr);
-
-   log->relay.buf_addr = vaddr;
+   i915_gem_object_get(log->vma->obj);
+   log->relay.buf_in_use = true;
 
return 0;
 }
@@ -336,8 +333,8 @@ static void guc_log_relay_unmap(struct intel_guc_log *log)
 {
lockdep_assert_held(>relay.lock);
 
-   i915_gem_object_unpin_map(log->vma->obj);
-   log->relay.buf_addr = NULL;
+   i915_gem_object_put(log->vma->obj);
+   log->relay.buf_in_use = false;
 }
 
 void intel_guc_log_init_early(struct intel_guc_log *log)
@@ -443,6 +440,7 @@ int intel_guc_log_create(struct intel_guc_log *log)
 {
struct intel_guc *guc = log_to_guc(log);
struct i915_vma *vma;
+   void *vaddr;
u32 guc_log_size;
int ret;
 
@@ -450,20 +448,21 @@ int intel_guc_log_create(struct intel_guc_log *log)
 
/*
 *  GuC Log buffer Layout
+* (this ordering must follow "enum guc_log_buffer_type" 

[Intel-gfx] [PATCH v10 13/13] drm/i915/guc: Print the GuC error capture output register list.

[Alan Previn]

Print the GuC captured error state register list (string names
and values) when gpu_coredump_state printout is invoked via
the i915 debugfs for flushing the gpu error-state that was
captured prior.

Since GuC could have reported multiple engine register dumps
in a single notification event, parse the captured data
(appearing as a stream of structures) to identify each dump as
a different 'engine-capture-group-output'.

Finally, for each 'engine-capture-group-output' that is found,
verify if the engine register dump corresponds to the
engine_coredump content that was previously populated by the
i915_gpu_coredump function. That function would have copied
the context's vma's including the bacth buffer during the
G2H-context-reset notification that occurred earlier. Perform
this verification check by comparing guc_id, lrca and engine-
instance obtained from the 'engine-capture-group-output' vs a
copy of that same info taken during i915_gpu_coredump. If
they match, then print those vma's as well (such as the batch
buffers).

NOTE: the output format was verified using the gem_exec_capture
IGT test.

Signed-off-by: Alan Previn 
Reviewed-by: Umesh Nerlige Ramappa 
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c |   4 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|   3 +
 .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 161 ++
 .../gpu/drm/i915/gt/uc/intel_guc_capture.h|   2 +-
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |   6 +-
 drivers/gpu/drm/i915/i915_debugfs.c   |   1 +
 drivers/gpu/drm/i915/i915_gpu_error.c |  16 +-
 drivers/gpu/drm/i915/i915_gpu_error.h |   5 +
 8 files changed, 183 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c 
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 8080479f27aa..151861afc4d2 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1702,9 +1702,7 @@ static void intel_engine_print_registers(struct 
intel_engine_cs *engine,
drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
}
 
-   if (intel_engine_uses_guc(engine)) {
-   /* nothing to print yet */
-   } else if (HAS_EXECLISTS(dev_priv)) {
+   if (HAS_EXECLISTS(dev_priv) && !intel_engine_uses_guc(engine)) {
struct i915_request * const *port, *rq;
const u32 *hws =
>status_page.addr[I915_HWS_CSB_BUF0_INDEX];
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h 
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index de32367831c6..4e431c14b118 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -438,6 +438,9 @@ int intel_guc_engine_failure_process_msg(struct intel_guc 
*guc,
 int intel_guc_error_capture_process_msg(struct intel_guc *guc,
const u32 *msg, u32 len);
 
+struct intel_engine_cs *
+intel_guc_lookup_engine(struct intel_guc *guc, u8 guc_class, u8 instance);
+
 void intel_guc_find_hung_context(struct intel_engine_cs *engine);
 
 int intel_guc_global_policies_update(struct intel_guc *guc);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 8f6031782d20..0a55871dad82 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -767,6 +767,21 @@ intel_guc_capture_output_min_size_est(struct intel_guc 
*guc)
  *intel_engine_coredump struct (if the 
context and
  *engine of the event notification matches 
a node
  *in the link list).
+ *
+ * User Sysfs / Debugfs
+ * 
+ *  --> i915_gpu_coredump_copy_to_buffer->
+ *   L--> err_print_to_sgl --> err_print_gt
+ *L--> error_print_guc_captures
+ * L--> intel_guc_capture_print_node prints the
+ *  register lists values of the attached node
+ *  on the error-engine-dump being reported.
+ *   L--> i915_reset_error_state ... 
-->__i915_gpu_coredump_free
+ *L--> ... cleanup_gt -->
+ * L--> intel_guc_capture_free_node returns the
+ *  capture-output-node back to the internal
+ *  cachelist for reuse.
+ *
  */
 
 static int guc_capture_buf_cnt(struct __guc_capture_bufstate *buf)
@@ -1384,9 +1399,155 @@ static void __guc_capture_process_output(struct 
intel_guc *guc)
 
 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 
+static const char *
+guc_capture_reg_to_str(const struct intel_guc *guc, u32 owner, u32 type,
+  u32 class, u32 id, u32 offset, u32 *is_ext)
+{
+   const struct __guc_mmio_reg_descr_group *reglists = 

[Intel-gfx] [PATCH v10 10/13] drm/i915/guc: Extract GuC error capture lists on G2H notification.

[Alan Previn]

- Upon the G2H Notify-Err-Capture event, parse through the
  GuC Log Buffer (error-capture-subregion) and generate one or
  more capture-nodes. A single node represents a single "engine-
  instance-capture-dump" and contains at least 3 register lists:
  global, engine-class and engine-instance. An internal link
  list is maintained to store one or more nodes.
- Because the link-list node generation happen before the call
  to i915_gpu_codedump, duplicate global and engine-class register
  lists for each engine-instance register dump if we find
  dependent-engine resets in a engine-capture-group.
- When i915_gpu_coredump calls into capture_engine, (in a
  subsequent patch) we detach the matching node (guc-id,
  LRCA, etc) from the link list above and attach it to
  i915_gpu_coredump's intel_engine_coredump structure when have
  matching LRCA/guc-id/engine-instance.

Additional notes to be aware of:
- GuC generates the error capture dump into the GuC log buffer but
  this buffer is one big log buffer with 3 independent subregions
  within it. Each subregion is populated with different content
  and used in different ways and timings but all regions operate
  behave as independent ring buffers. Each guc-log subregion
  (general-logs, crash-dump and error- capture) has it's own
  guc_log_buffer_state that contain independent read and write
  pointers.

Signed-off-by: Alan Previn 
Reviewed-by: Umesh Nerlige Ramappa 
---
 .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h  |   7 +
 drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h |  56 ++
 .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 561 +-
 .../gpu/drm/i915/gt/uc/intel_guc_capture.h|   1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.c|  26 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_log.h|   4 +
 .../gpu/drm/i915/gt/uc/intel_guc_submission.c |  10 +-
 7 files changed, 652 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 
b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index e77f955435ce..77936912c278 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -171,4 +171,11 @@ enum intel_guc_sleep_state_status {
 #define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
 #define GUC_LOG_CONTROL_DEFAULT_LOGGING(1 << 8)
 
+enum intel_guc_state_capture_event_status {
+   INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_SUCCESS = 0x0,
+   INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE = 0x1,
+};
+
+#define INTEL_GUC_STATE_CAPTURE_EVENT_STATUS_MASK  0x00FF
+
 #endif /* _ABI_GUC_ACTIONS_ABI_H */
diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
index 8824c5eba355..5d959e62d146 100644
--- a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
@@ -12,6 +12,52 @@
 struct intel_guc;
 struct file;
 
+/**
+ * struct __guc_capture_bufstate
+ *
+ * Book-keeping structure used to track read and write pointers
+ * as we extract error capture data from the GuC-log-buffer's
+ * error-capture region as a stream of dwords.
+ */
+struct __guc_capture_bufstate {
+   u32 size;
+   void *data;
+   u32 rd;
+   u32 wr;
+};
+
+/**
+ * struct __guc_capture_parsed_output - extracted error capture node
+ *
+ * A single unit of extracted error-capture output data grouped together
+ * at an engine-instance level. We keep these nodes in a linked list.
+ * See outlist below.
+ */
+struct __guc_capture_parsed_output {
+   /*
+* A single set of 3 capture lists: a global-list
+* an engine-class-list and an engine-instance list.
+* outlist in __guc_capture_parsed_output will keep
+* a linked list of these nodes that will eventually
+* be detached from outlist and attached into to
+* i915_gpu_codedump in response to a context reset
+*/
+   struct list_head link;
+   bool is_partial;
+   u32 eng_class;
+   u32 eng_inst;
+   u32 guc_id;
+   u32 lrca;
+   struct gcap_reg_list_info {
+   u32 vfid;
+   u32 num_regs;
+   struct guc_mmio_reg *regs;
+   } reginfo[GUC_CAPTURE_LIST_TYPE_MAX];
+#define GCAP_PARSED_REGLIST_INDEX_GLOBAL   BIT(GUC_CAPTURE_LIST_TYPE_GLOBAL)
+#define GCAP_PARSED_REGLIST_INDEX_ENGCLASS 
BIT(GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS)
+#define GCAP_PARSED_REGLIST_INDEX_ENGINST  
BIT(GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE)
+};
+
 /**
  * struct guc_debug_capture_list_header / struct guc_debug_capture_list
  *
@@ -142,6 +188,16 @@ struct intel_guc_state_capture {
[GUC_CAPTURE_LIST_TYPE_MAX]
[GUC_MAX_ENGINE_CLASSES];
void *ads_null_cache;
+
+   /**
+* @outlist: allocated nodes with parsed engine-instance error capture 
data
+*
+* A linked list of parsed GuC 

[Intel-gfx] [PATCH v10 04/13] drm/i915/guc: Add DG2 registers for GuC error state capture.

[Alan Previn]

Add additional DG2 registers for GuC error state capture.

Signed-off-by: Alan Previn 
Reviewed-by: Umesh Nerlige Ramappa 
---
 .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 80 ++-
 1 file changed, 77 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c 
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 0f2b47139140..15fc36203463 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -285,20 +285,94 @@ guc_capture_alloc_steered_lists_xe_lpd(struct intel_guc 
*guc,
guc->capture->extlists = extlists;
 }
 
+static const struct __ext_steer_reg xehpg_extregs[] = {
+   {"XEHPG_INSTDONE_GEOM_SVG", XEHPG_INSTDONE_GEOM_SVG}
+};
+
+static bool __has_xehpg_extregs(u32 ipver)
+{
+   return (ipver >= IP_VER(12, 55));
+}
+
+static void
+guc_capture_alloc_steered_lists_xe_hpg(struct intel_guc *guc,
+  const struct __guc_mmio_reg_descr_group 
*lists,
+  u32 ipver)
+{
+   struct intel_gt *gt = guc_to_gt(guc);
+   struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
+   struct sseu_dev_info *sseu;
+   int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0;
+   const struct __guc_mmio_reg_descr_group *list;
+   struct __guc_mmio_reg_descr_group *extlists;
+   struct __guc_mmio_reg_descr *extarray;
+
+   /* In XE_LP / HPG we only have render-class steering registers during 
error-capture */
+   list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF,
+   GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, 
GUC_RENDER_CLASS);
+   /* skip if extlists was previously allocated */
+   if (!list || guc->capture->extlists)
+   return;
+
+   num_steer_regs = ARRAY_SIZE(xe_extregs);
+   if (__has_xehpg_extregs(ipver))
+   num_steer_regs += ARRAY_SIZE(xehpg_extregs);
+
+   sseu = >info.sseu;
+   for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) {
+   num_tot_regs += num_steer_regs;
+   }
+
+   if (!num_tot_regs)
+   return;
+
+   /* allocate an extra for an end marker */
+   extlists = kcalloc(2, sizeof(struct __guc_mmio_reg_descr_group), 
GFP_KERNEL);
+   if (!extlists)
+   return;
+
+   if (__alloc_ext_regs([0], list, num_tot_regs)) {
+   kfree(extlists);
+   return;
+   }
+
+   extarray = extlists[0].extlist;
+   for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice, subslice) {
+   for (i = 0; i < ARRAY_SIZE(xe_extregs); ++i) {
+   __fill_ext_reg(extarray, _extregs[i], slice, 
subslice);
+   ++extarray;
+   }
+   if (__has_xehpg_extregs(ipver)) {
+   for (i = 0; i < ARRAY_SIZE(xehpg_extregs); ++i) {
+   __fill_ext_reg(extarray, _extregs[i], 
slice, subslice);
+   ++extarray;
+   }
+   }
+   }
+
+   drm_dbg(>drm, "GuC-capture found %d-ext-regs.\n", num_tot_regs);
+   guc->capture->extlists = extlists;
+}
+
 static const struct __guc_mmio_reg_descr_group *
 guc_capture_get_device_reglist(struct intel_guc *guc)
 {
struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
 
-   if (IS_TIGERLAKE(i915) || IS_ROCKETLAKE(i915) ||
-   IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) {
+   if (GRAPHICS_VER(i915) > 11) {
/*
 * For certain engine classes, there are slice and subslice
 * level registers requiring steering. We allocate and populate
 * these at init time based on hw config add it as an extension
 * list at the end of the pre-populated render list.
 */
-   guc_capture_alloc_steered_lists_xe_lpd(guc, xe_lpd_lists);
+   if (IS_DG2(i915))
+   guc_capture_alloc_steered_lists_xe_hpg(guc, 
xe_lpd_lists, IP_VER(12, 55));
+   else if (IS_XEHPSDV(i915))
+   guc_capture_alloc_steered_lists_xe_hpg(guc, 
xe_lpd_lists, IP_VER(12, 50));
+   else
+   guc_capture_alloc_steered_lists_xe_lpd(guc, 
xe_lpd_lists);
+
return xe_lpd_lists;
}
 
-- 
2.25.1

[Intel-gfx] [PATCH v10 00/13] Add GuC Error Capture Support

[Alan Previn]

This series:
  1. Enables support of GuC to report error-state-capture
 using a list of MMIO registers the driver registers
 and GuC will dump, log and notify right before a GuC
 triggered engine-reset event.
  2. Updates the ADS blob creation to register said lists
 of global, engine class and engine instance registers
 with GuC.
  3. Defines tables of register lists that are global or
 engine class or engine instance in scope.
  4. Updates usage and buffer-state data for the regions
 of the shared GuC log-buffer to accomdate both
 the existing relay logging of general debug logs
 along with the new error state capture usage.
  5. Using a pool of preallocated memory, provide ability
 to extract and format the GuC reported register-capture
 data into chunks consistent with existing i915 error-
 state collection flows and structures.
  6. Connects the i915_gpu_coredump reporting function
 to the GuC error capture module to print all GuC
 error state capture dumps that is reported.

This is the 8th rev of this series with the first 3 revs
labelled as RFC.

Prior receipts of rvb's:
  - Patch #2, #3, #4, #5, #10, #11, #12, #13 have received
R-v-b's from Umesh Nerlige Ramappa 
  - Patch #6, #7, #8, #9 has received an R-v-b from Matthew Brost
. NOTE: some of these came in on the
trybot series. https://patchwork.freedesktop.org/series/100831/

Changes from prior revs:
  v10:- Rebase on latest drm-tip again. Fix a number of checkpatch
warnings and an error Reported-by: kernel test robot .
  v9: - Rebase on latest drm-tip to solve CI merge-build error.
  v8: - Fix a bug found by CI in rev7: Create a cached ADS
capture list for null-header like the other lists.
  - Fixed a bug on the ggtt offset calculation in the
ADS population loop. Thanks to Matt Brost.
  - Change the storage uses for initial allocation and
caching of the ADS register lists so we only store
a regular pointer instead of file handle.
  - Multiple improvements on code styling, variable names,
comments and code reduction from Umesh suggestions
across multiple patches.

  v7: - Rebased on lastest drm_tip that has the ADS now using
shmem based ads_blob_write utilities. Stress test
was performed with this patch included to fix a
legacy bug:
https://patchwork.freedesktop.org/series/100768/

  v6: - In patch #1, ADS reg-list population, we now alloc
regular memory to create the lists and cache them for
simpler and faster use by GuC ADS module at init, 
suspend-resume and reset cycles. This was in response
to review comments from Lucas De Marchi that also
wanted to ensure the GuC ADS module owns the final
copying into the ADS phyical memory.
  - Thanks to Jani Nikula for pointing out that patch #2
and #3 should ensure static tables as constant and
dynamic lists should be allocated and cached but
attached to the GT level for the case of multiple
cards with different fusings for steered registers.
These are addressed now along with multiple code
style fixups (thanks to review comment from Umesh)
and splitting the steered register list generation
as a seperate patch.
  - The extraction functionality, Patch #10 and #11 (was
patch #7), has fixed all of Umesh's review comments
related to the code styling. Additionally, it was
discovered during stress tests that the extraction
function could be called by the ct processing thread
at the same time as the start of a GT reset event.
Thus, a redesign was done whereby the linked list of
processed capture-output-nodes are allocated up
front and reused throughout the driver's life to
ensure no memory locks are taken during extraction.
  - For patch #6 (now 7, 8 and 9), updates to
intel_guc_log was split into smaller chunks and the
log_state structure was returned back to inside of
the intel_guc_log struct as opposed to the
intel_guc struct in prior rev. This is in response
to review comments by Matt Brost.
  - #Patch 13 (previously #10) is mostly identical but
addresses all of the code styling comments reviews
from Umesh.

  v5: - Added Gen9->Gen11 register list for CI coverage that
included Gen9 with GuC submission.
  - Redesigned the extraction of the GuC error-capture
dumps by grouping them into complete per-engine-reset
nodes. Complete here means each node includes the
global, engine-class and engine-instance register
lists in a single structure.
  - Extraction is decoupled from the print-out. We now
do the extraction immediately when receiving the
G2H for error-capture notification. A link list of
nodes is maintained 

[Intel-gfx] [PATCH v10 01/13] drm/i915/guc: Update GuC ADS size for error capture lists

[Alan Previn]

Update GuC ADS size allocation to include space for
the lists of error state capture register descriptors.

Then, populate GuC ADS with the lists of registers we want
GuC to report back to host on engine reset events. This list
should include global, engine-class and engine-instance
registers for every engine-class type on the current hardware.

Ensure we allocate a persistent store for the register lists
that are populated into ADS so that we don't need to allocate
memory during GT resets when GuC is reloaded and ADS population
happens again.

NOTE: Start with a sample static table of register lists to
layout the framework before adding real registers in subsequent
patch. This static register tables are a different format from
the ADS populated list.

Signed-off-by: Alan Previn 
Reviewed-by: Matthew Brost 
---
 drivers/gpu/drm/i915/Makefile |   1 +
 drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h |  91 +
 drivers/gpu/drm/i915/gt/uc/intel_guc.c|  13 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc.h|   9 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 127 +-
 .../gpu/drm/i915/gt/uc/intel_guc_capture.c| 374 ++
 .../gpu/drm/i915/gt/uc/intel_guc_capture.h|  22 ++
 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h   |   8 +
 8 files changed, 628 insertions(+), 17 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
 create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1a771ee5b1d0..69ada3b90a2c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -184,6 +184,7 @@ i915-y += gt/uc/intel_uc.o \
  gt/uc/intel_uc_fw.o \
  gt/uc/intel_guc.o \
  gt/uc/intel_guc_ads.o \
+ gt/uc/intel_guc_capture.o \
  gt/uc/intel_guc_ct.o \
  gt/uc/intel_guc_debugfs.o \
  gt/uc/intel_guc_fw.o \
diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h 
b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
new file mode 100644
index ..919ed985f09a
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021-2022 Intel Corporation
+ */
+
+#ifndef _INTEL_GUC_CAPTURE_FWIF_H
+#define _INTEL_GUC_CAPTURE_FWIF_H
+
+#include 
+#include "intel_guc_fwif.h"
+
+struct intel_guc;
+struct file;
+
+/**
+ * struct guc_debug_capture_list_header / struct guc_debug_capture_list
+ *
+ * As part of ADS registration, these header structures (followed by
+ * an array of 'struct guc_mmio_reg' entries) are used to register with
+ * GuC microkernel the list of registers we want it to dump out prior
+ * to a engine reset.
+ */
+struct guc_debug_capture_list_header {
+   u32 info;
+#define GUC_CAPTURELISTHDR_NUMDESCR GENMASK(15, 0)
+} __packed;
+
+struct guc_debug_capture_list {
+   struct guc_debug_capture_list_header header;
+   struct guc_mmio_reg regs[0];
+} __packed;
+
+/**
+ * struct __guc_mmio_reg_descr / struct __guc_mmio_reg_descr_group
+ *
+ * intel_guc_capture module uses these structures to maintain static
+ * tables (per unique platform) that consists of lists of registers
+ * (offsets, names, flags,...) that are used at the ADS regisration
+ * time as well as during runtime processing and reporting of error-
+ * capture states generated by GuC just prior to engine reset events.
+ */
+struct __guc_mmio_reg_descr {
+   i915_reg_t reg;
+   u32 flags;
+   u32 mask;
+   const char *regname;
+};
+
+struct __guc_mmio_reg_descr_group {
+   const struct __guc_mmio_reg_descr *list;
+   u32 num_regs;
+   u32 owner; /* see enum guc_capture_owner */
+   u32 type; /* see enum guc_capture_type */
+   u32 engine; /* as per MAX_ENGINE_CLASS */
+};
+
+/**
+ * struct __guc_capture_ads_cache
+ *
+ * A structure to cache register lists that were populated and registered
+ * with GuC at startup during ADS registration. This allows much quicker
+ * GuC resets without re-parsing all the tables for the given gt.
+ */
+struct __guc_capture_ads_cache {
+   bool is_valid;
+   void *ptr;
+   size_t size;
+   int status;
+};
+
+/**
+ * struct intel_guc_state_capture
+ *
+ * Internal context of the intel_guc_capture module.
+ */
+struct intel_guc_state_capture {
+   /**
+* @reglists: static table of register lists used for error-capture 
state.
+*/
+   const struct __guc_mmio_reg_descr_group *reglists;
+
+   /**
+* @ads_cache: cached register lists that is ADS format ready
+*/
+   struct __guc_capture_ads_cache ads_cache[GUC_CAPTURE_LIST_INDEX_MAX]
+   [GUC_CAPTURE_LIST_TYPE_MAX]
+   [GUC_MAX_ENGINE_CLASSES];
+   void *ads_null_cache;
+};
+
+#endif /* 

Re: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add GuC Error Capture Support (rev2)

[Teres Alexis, Alan Previn]

I shall fix the length line warnings.

However i shall not fix the " WARNING:OOM_MESSAGE: Possible unnecessary 
'out of memory' message" warnings for reasons as stated because the 
caller function is not reporting the OOM error and because if such an 
error occurs, the ADS function that populates the offsets for the 
error-capture register list will default to the null list. And even if 
the null list had failed to allocate, the ADS routine would have been 
able to use the initial empty error-capture region that would have been 
interpreted as a null list. The reason why i still DO want the drm_dbg 
(as opposed to a drm_warn) is because I am assuming the the definition 
of "i915s normal operation" does not include guaranteeing a valid 
error-capture dump since this would be a driver error-handling-condition..


...alan


On 3/15/2022 11:24 AM, Patchwork wrote:

== Series Details ==

Series: Add GuC Error Capture Support (rev2)
URL   : https://patchwork.freedesktop.org/series/101348/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
41d2f067e825 drm/i915/guc: Update GuC ADS size for error capture lists
-:40: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#40:
new file mode 100644

-:324: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#324: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:653:
+   ads_blob_write(guc, ads.capture_class[i][j], 
ads_ggtt + capture_offset);

-:345: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#345: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:674:
+   ads_blob_write(guc, ads.capture_instance[i][j], 
ads_ggtt + capture_offset);

-:469: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'regslist' - possible 
side-effects?
#469: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:63:
+#define MAKE_REGLIST(regslist, regsowner, regstype, class) \
+   { \
+   regslist, \
+   ARRAY_SIZE(regslist), \
+   TO_GCAP_DEF_OWNER(regsowner), \
+   TO_GCAP_DEF_TYPE(regstype), \
+   class, \
+   }

-:513: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional 
statements (16, 16)
#513: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:107:
+   if (reglists[i].owner == owner && reglists[i].type == type &&
[...]
+   return [i];

-:689: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#689: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:283:
+   if (!caplist) {
+   drm_dbg(>drm, "GuC-capture: failed to alloc cached 
caplist");

-:731: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#731: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:325:
+   if (!null_header) {
+   drm_dbg(>drm, "GuC-capture: failed to alloc cached 
nulllist");

total: 0 errors, 6 warnings, 1 checks, 749 lines checked
7b2eb12974e1 drm/i915/guc: Add XE_LP static registers for GuC error capture.
-:26: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#26: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:25:
+#define COMMON_GEN12BASE_GLOBAL() \
+   {GEN12_FAULT_TLB_DATA0,0,  0, "GEN12_FAULT_TLB_DATA0"}, \
+   {GEN12_FAULT_TLB_DATA1,0,  0, "GEN12_FAULT_TLB_DATA1"}, \
+   {FORCEWAKE_MT, 0,  0, "FORCEWAKE"}, \
+   {GEN12_AUX_ERR_DBG,0,  0, "AUX_ERR_DBG"}, \
+   {GEN12_GAM_DONE,   0,  0, "GAM_DONE"}, \
+   {GEN12_RING_FAULT_REG, 0,  0, "FAULT_REG"}

-:34: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#34: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:33:
+#define COMMON_GEN12BASE_ENGINE_INSTANCE() \
+   {RING_PSMI_CTL(0), 0,  0, "RC PSMI"}, \
+   {RING_ESR(0),  0,  0, "ESR"}, \
+   {RING_DMA_FADD(0), 0,  0, "RING_DMA_FADD_LDW"}, \
+   {RING_DMA_FADD_UDW(0), 0,  0, "RING_DMA_FADD_UDW"}, \
+   {RING_IPEIR(0),0,  0, "IPEIR"}, \
+   {RING_IPEHR(0),0,  0, "IPEHR"}, \
+   {RING_INSTPS(0),   0,  0, "INSTPS"}, \
+   {RING_BBADDR(0),   0,  0, "RING_BBADDR_LOW32"}, \
+   {RING_BBADDR_UDW(0),   0,  0, "RING_BBADDR_UP32"}, \
+   {RING_BBSTATE(0),  0,  0, "BB_STATE"}, \
+   {CCID(0),  0,  0, "CCID"}, \
+   {RING_ACTHD(0),0,  0, "ACTHD_LDW"}, \
+   {RING_ACTHD_UDW(0),0,  0, "ACTHD_UDW"}, \
+   {RING_INSTPM(0),   0,  0, "INSTPM"}, \
+   {RING_INSTDONE(0), 0,  0, "INSTDONE"}, \
+   {RING_NOPID(0),0,  0, "RING_NOPID"}, \
+   {RING_START(0),0,  0, "START"}, \
+   {RING_HEAD(0), 0,  0, "HEAD"}, \
+   {RING_TAIL(0), 0,  0, "TAIL"}, \
+   

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/adlp: More voltage swing table updates

[Patchwork]

== Series Details ==

Series: drm/i915/display/adlp: More voltage swing table updates
URL   : https://patchwork.freedesktop.org/series/101404/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11365_full -> Patchwork_22578_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 12)
--

  Missing(1): shard-dg1 

Known issues


  Here are the changes found in Patchwork_22578_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-snb:  ([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], 
[PASS][24], [PASS][25]) -> ([PASS][26], [PASS][27], [PASS][28], [PASS][29], 
[PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [FAIL][35], 
[PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], 
[PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], 
[PASS][48], [PASS][49], [PASS][50]) ([i915#4338])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb7/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb7/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb7/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb7/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb7/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb7/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb7/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb7/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb5/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb5/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb5/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb5/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb5/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb4/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb4/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb4/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb4/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb4/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb4/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb2/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb2/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb2/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb2/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb2/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-snb2/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb7/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb7/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb7/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb7/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb7/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb7/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb5/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb5/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb5/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb5/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb5/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb5/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb4/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb4/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb4/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb4/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb4/boot.html
   [43]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/shard-snb4/boot.html
   [44]: 

Re: [Intel-gfx] [PATCH v9 13/13] drm/i915/guc: Print the GuC error capture output register list.

[Teres Alexis, Alan Previn]

This is an actual bug I missed - will fix this - would cause a 
compilation error when enabling "CONFIG_DRM_I915_DEBUG_GUC"


On 3/14/2022 7:26 PM, kernel test robot wrote:

Hi Alan,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next 
drm/drm-next tegra-drm/drm/tegra/for-next v5.17-rc8 next-20220310]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:
https://github.com/0day-ci/linux/commits/Alan-Previn/Add-GuC-Error-Capture-Support/20220315-010958
base:   git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-allyesconfig 
(https://download.01.org/0day-ci/archive/20220315/202203151007.myugtwwo-...@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 
3e4950d7fa78ac83f33bbf1658e2f49a73719236)
reproduce (this is a W=1 build):
 wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
 chmod +x ~/bin/make.cross
 # 
https://github.com/0day-ci/linux/commit/90c08c10562cba1ebf8b31788e7a9550c7637838
 git remote add linux-review https://github.com/0day-ci/linux
 git fetch --no-tags linux-review 
Alan-Previn/Add-GuC-Error-Capture-Support/20220315-010958
 git checkout 90c08c10562cba1ebf8b31788e7a9550c7637838
 # save the config file to linux build tree
 mkdir build_dir
 COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 
O=build_dir ARCH=i386 SHELL=/bin/bash

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot 

All errors (new ones prefixed by >>):


drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:1497:2: error: no member named 
'drm' in 'struct drm_i915_error_state_buf'

__out(ebuf, "global --- GuC Error Capture on %s command stream:\n",
^~~
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:1442:19: note: expanded from 
macro '__out'
drm_warn((&(a)->drm), __VA_ARGS__); \
^~
include/drm/drm_print.h:435:16: note: expanded from macro 'drm_warn'
__drm_printk((drm), warn,, fmt, ##__VA_ARGS__)
~~^~~~
include/drm/drm_print.h:425:21: note: expanded from macro '__drm_printk'
dev_##level##type((drm)->dev, "[drm] " fmt, ##__VA_ARGS__)
~~~^~~
include/linux/dev_printk.h:146:49: note: expanded from macro 'dev_warn'
dev_printk_index_wrap(_dev_warn, KERN_WARNING, dev, dev_fmt(fmt), 
##__VA_ARGS__)

~~~^
include/linux/dev_printk.h:110:11: note: expanded from macro 
'dev_printk_index_wrap'
_p_func(dev, fmt, ##__VA_ARGS__);   \
^~~
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:1502:3: error: no member 
named 'drm' in 'struct drm_i915_error_state_buf'
__out(ebuf, "  No matching ee-node\n");
^~
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:1442:19: note: expanded from 
macro '__out'
drm_warn((&(a)->drm), __VA_ARGS__); \
^~
include/drm/drm_print.h:435:16: note: expanded from macro 'drm_warn'
__drm_printk((drm), warn,, fmt, ##__VA_ARGS__)
~~^~~~
include/drm/drm_print.h:425:21: note: expanded from macro '__drm_printk'
dev_##level##type((drm)->dev, "[drm] " fmt, ##__VA_ARGS__)
~~~^~~
include/linux/dev_printk.h:146:49: note: expanded from macro 'dev_warn'
dev_printk_index_wrap(_dev_warn, KERN_WARNING, dev, dev_fmt(fmt), 
##__VA_ARGS__)

~~~^
include/linux/dev_printk.h:110:11: note: expanded from macro 
'dev_printk_index_wrap'
_p_func(dev, fmt, ##__VA_ARGS__);   \
^~~
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:1506:2: error: no member 
named 'drm' in 'struct drm_i915_error_state_buf'
__out(ebuf, "Coverage:  %s\n", grptype[node->is_partial]);
^
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:1442:19:

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/: Refactor hsw_crtc_enable for bigjoiner cleanup

[Patchwork]

== Series Details ==

Series: drm/i915/display/: Refactor hsw_crtc_enable for bigjoiner cleanup
URL   : https://patchwork.freedesktop.org/series/101409/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11365 -> Patchwork_22580


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22580/index.html

Participating hosts (48 -> 39)
--

  Additional (1): bat-dg2-8 
  Missing(10): shard-tglu bat-dg1-6 fi-hsw-4200u bat-dg2-9 fi-bsw-cyan 
fi-ctg-p8600 bat-rpls-1 shard-rkl shard-dg1 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22580:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@gt_lrc:
- {bat-dg2-8}:NOTRUN -> [INCOMPLETE][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22580/bat-dg2-8/igt@i915_selftest@live@gt_lrc.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
- {bat-dg2-8}:NOTRUN -> [SKIP][2] +22 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22580/bat-dg2-8/igt@kms_flip@basic-flip-vs-wf_vblank.html

  
Known issues


  Here are the changes found in Patchwork_22580 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@requests:
- fi-blb-e6850:   [PASS][3] -> [DMESG-FAIL][4] ([i915#4528])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-blb-e6850/igt@i915_selftest@l...@requests.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22580/fi-blb-e6850/igt@i915_selftest@l...@requests.html

  * igt@runner@aborted:
- fi-blb-e6850:   NOTRUN -> [FAIL][5] ([fdo#109271] / [i915#2403] / 
[i915#4312])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22580/fi-blb-e6850/igt@run...@aborted.html
- fi-bdw-5557u:   NOTRUN -> [FAIL][6] ([i915#2426] / [i915#4312])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22580/fi-bdw-5557u/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@migrate:
- {bat-rpls-2}:   [DMESG-WARN][7] ([i915#4391]) -> [PASS][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-rpls-2/igt@i915_selftest@l...@migrate.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22580/bat-rpls-2/igt@i915_selftest@l...@migrate.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
- {bat-adlp-6}:   [DMESG-WARN][9] ([i915#3576]) -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-adlp-6/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22580/bat-adlp-6/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
  [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
  [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
  [i915#5192]: https://gitlab.freedesktop.org/drm/intel/issues/5192
  [i915#5193]: https://gitlab.freedesktop.org/drm/intel/issues/5193
  [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
  [i915#5275]: 

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,1/7] drm/i915/lmem: don't treat small BAR as an error

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/7] drm/i915/lmem: don't treat small BAR as 
an error
URL   : https://patchwork.freedesktop.org/series/101398/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11365_full -> Patchwork_22576_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22576_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22576_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22576_full:

### IGT changes ###

 Possible regressions 

  * igt@kms_sequence@queue-busy:
- shard-skl:  [PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-skl1/igt@kms_seque...@queue-busy.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/shard-skl3/igt@kms_seque...@queue-busy.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_ccs@block-copy-inplace:
- {shard-dg1}:NOTRUN -> [SKIP][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/shard-dg1-12/igt@gem_...@block-copy-inplace.html

  * igt@gem_eio@in-flight-suspend:
- {shard-rkl}:[PASS][4] -> [FAIL][5]
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-rkl-1/igt@gem_...@in-flight-suspend.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/shard-rkl-4/igt@gem_...@in-flight-suspend.html

  
Known issues


  Here are the changes found in Patchwork_22576_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@chamelium:
- shard-iclb: NOTRUN -> [SKIP][6] ([fdo#111827])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/shard-iclb2/igt@feature_discov...@chamelium.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][7] -> [FAIL][8] ([i915#232])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-tglb7/igt@gem_...@unwedge-stress.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/shard-tglb8/igt@gem_...@unwedge-stress.html
- shard-skl:  [PASS][9] -> [TIMEOUT][10] ([i915#3063])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-skl4/igt@gem_...@unwedge-stress.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/shard-skl7/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
- shard-skl:  NOTRUN -> [FAIL][11] ([i915#2846])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/shard-skl3/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-tglb: [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-tglb6/igt@gem_exec_fair@basic-none-...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/shard-tglb3/igt@gem_exec_fair@basic-none-...@rcs0.html

  * igt@gem_exec_fair@basic-none@vecs0:
- shard-apl:  [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-apl4/igt@gem_exec_fair@basic-n...@vecs0.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/shard-apl1/igt@gem_exec_fair@basic-n...@vecs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2842]) +1 similar 
issue
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/shard-iclb8/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl:  [PASS][18] -> [FAIL][19] ([i915#2842]) +2 similar 
issues
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-kbl4/igt@gem_exec_fair@basic-p...@rcs0.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/shard-kbl7/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][20] ([fdo#112283])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/shard-iclb2/igt@gem_exec_par...@secure-non-root.html

  * igt@gem_exec_whisper@basic-fds-forked-all:
- shard-glk:  [PASS][21] -> [DMESG-WARN][22] ([i915#118])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk9/igt@gem_exec_whis...@basic-fds-forked-all.html
   [22]: 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for i915: General multicast steering updates (rev2)

[Matt Roper]

On Tue, Mar 15, 2022 at 11:39:41PM +, Patchwork wrote:
> == Series Details ==
> 
> Series: i915: General multicast steering updates (rev2)
> URL   : https://patchwork.freedesktop.org/series/101367/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_11365_full -> Patchwork_22574_full
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_22574_full absolutely need to 
> be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_22574_full, please notify your bug team to allow 
> them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   
> 
> Participating hosts (13 -> 13)
> --
> 
>   No changes in participating hosts
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_22574_full:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@gem_exec_whisper@basic-fds-forked-all:
> - shard-kbl:  [PASS][1] -> [INCOMPLETE][2]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-kbl6/igt@gem_exec_whis...@basic-fds-forked-all.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-kbl4/igt@gem_exec_whis...@basic-fds-forked-all.html

<4> [222.484874] general protection fault, probably for non-canonical address 
0x6b6b6b6b6b6b7c23:  [#1] PREEMPT SMP PTI
<4> [222.484889] CPU: 3 PID: 1279 Comm: gem_exec_whispe Not tainted 
5.17.0-rc8-CI-Patchwork_22574+ #1
<4> [222.484899] Hardware name:  /NUC7i5BNB, BIOS 
BNKBL357.86A.0054.2017.1025.1822 10/25/2017
<4> [222.484906] RIP: 0010:__lock_acquire+0x612/0x2940

This implies a use-after-free mistake somewhere; it wouldn't be caused
by the steering changes in this series.

I see a similar stack trace and error on a different test/platform here:
https://gitlab.freedesktop.org/drm/intel/-/issues/5268 which might be
caused by the same underlying bug.


Matt

> 
>   
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * igt@gem_bad_reloc@negative-reloc-bltcopy:
> - {shard-rkl}:[PASS][3] -> [DMESG-WARN][4]
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-rkl-2/igt@gem_bad_re...@negative-reloc-bltcopy.html
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-rkl-5/igt@gem_bad_re...@negative-reloc-bltcopy.html
> 
>   * igt@gem_ccs@block-copy-inplace:
> - {shard-dg1}:NOTRUN -> [SKIP][5]
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-dg1-12/igt@gem_...@block-copy-inplace.html
> 
>   * igt@gem_exec_schedule@submit-early-slice@vecs0:
> - {shard-dg1}:NOTRUN -> [INCOMPLETE][6]
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-dg1-15/igt@gem_exec_schedule@submit-early-sl...@vecs0.html
> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_22574_full that come from known 
> issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@feature_discovery@chamelium:
> - shard-iclb: NOTRUN -> [SKIP][7] ([fdo#111827])
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-iclb2/igt@feature_discov...@chamelium.html
> 
>   * igt@gem_eio@unwedge-stress:
> - shard-tglb: [PASS][8] -> [TIMEOUT][9] ([i915#3063] / 
> [i915#3648])
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-tglb7/igt@gem_...@unwedge-stress.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-tglb7/igt@gem_...@unwedge-stress.html
> 
>   * igt@gem_exec_fair@basic-deadline:
> - shard-skl:  NOTRUN -> [FAIL][10] ([i915#2846])
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-skl6/igt@gem_exec_f...@basic-deadline.html
> 
>   * igt@gem_exec_fair@basic-none-vip@rcs0:
> - shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842])
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-tglb6/igt@gem_exec_fair@basic-none-...@rcs0.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-tglb5/igt@gem_exec_fair@basic-none-...@rcs0.html
> 
>   * igt@gem_exec_fair@basic-none@vcs0:
> - shard-apl:  [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar 
> issue
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-apl4/igt@gem_exec_fair@basic-n...@vcs0.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-apl3/igt@gem_exec_fair@basic-n...@vcs0.html
> 
>   * igt@gem_exec_fair@basic-pace-solo@rcs0:
> - shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar 
> issue
>[15]: 
> 

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Add support for steered register writes

[Lucas De Marchi]

On Mon, Mar 14, 2022 at 04:42:03PM -0700, Matt Roper wrote:

Upcoming patches will need to steer writes to multicast registers as
well as reading them.

Although the setting of the 'multicast' bit should only really matter
for write operations (reads always operate in a unicast manner and give
us the result from one specific instance), Wa_22013088509 suggests that
we leave the multicast bit enabled when performing read operations, so
we follow suit here.

Cc: Harish Chegondi 
Signed-off-by: Matt Roper 



Reviewed-by: Lucas De Marchi 

Lucas De Marchi

Re: [Intel-gfx] [PATCH 2/3] drm/i915/guc: add steering info to GuC register save/restore list

[Lucas De Marchi]

On Mon, Mar 14, 2022 at 04:42:02PM -0700, Matt Roper wrote:

From: Daniele Ceraolo Spurio 

GuC has its own steering mechanism and can't use the default set by i915,
so we need to provide the steering information that the FW will need to
save/restore registers while processing an engine reset. The GUC
interface allows us to do so as part of the register save/restore list
and it requires us to specify the steering for all multicast register, even
those that would be covered by the default setting for cpu access. Given
that we do not distinguish between registers that do not need steering and
registers that are guaranteed to work the default steering, we set the
steering for all entries in the guc list that do not require a special
steering (e.g. mslice) to the default settings; this will cost us a few
extra writes during engine reset but allows us to keep the steering
logic simple.

Cc: John Harrison 
Cc: Matt Roper 
Signed-off-by: Daniele Ceraolo Spurio 
Signed-off-by: Matt Roper 



Reviewed-by: Lucas De Marchi 

Lucas De Marchi

[Intel-gfx] ✗ Fi.CI.IGT: failure for i915: General multicast steering updates (rev2)

[Patchwork]

== Series Details ==

Series: i915: General multicast steering updates (rev2)
URL   : https://patchwork.freedesktop.org/series/101367/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11365_full -> Patchwork_22574_full


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22574_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22574_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22574_full:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_whisper@basic-fds-forked-all:
- shard-kbl:  [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-kbl6/igt@gem_exec_whis...@basic-fds-forked-all.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-kbl4/igt@gem_exec_whis...@basic-fds-forked-all.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_bad_reloc@negative-reloc-bltcopy:
- {shard-rkl}:[PASS][3] -> [DMESG-WARN][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-rkl-2/igt@gem_bad_re...@negative-reloc-bltcopy.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-rkl-5/igt@gem_bad_re...@negative-reloc-bltcopy.html

  * igt@gem_ccs@block-copy-inplace:
- {shard-dg1}:NOTRUN -> [SKIP][5]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-dg1-12/igt@gem_...@block-copy-inplace.html

  * igt@gem_exec_schedule@submit-early-slice@vecs0:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][6]
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-dg1-15/igt@gem_exec_schedule@submit-early-sl...@vecs0.html

  
Known issues


  Here are the changes found in Patchwork_22574_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@chamelium:
- shard-iclb: NOTRUN -> [SKIP][7] ([fdo#111827])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-iclb2/igt@feature_discov...@chamelium.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][8] -> [TIMEOUT][9] ([i915#3063] / [i915#3648])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-tglb7/igt@gem_...@unwedge-stress.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-tglb7/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
- shard-skl:  NOTRUN -> [FAIL][10] ([i915#2846])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-skl6/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-tglb: [PASS][11] -> [FAIL][12] ([i915#2842])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-tglb6/igt@gem_exec_fair@basic-none-...@rcs0.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-tglb5/igt@gem_exec_fair@basic-none-...@rcs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
- shard-apl:  [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar 
issue
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-apl4/igt@gem_exec_fair@basic-n...@vcs0.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-apl3/igt@gem_exec_fair@basic-n...@vcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][15] -> [FAIL][16] ([i915#2842]) +1 similar 
issue
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-iclb5/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl:  [PASS][17] -> [FAIL][18] ([i915#2842])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-kbl4/igt@gem_exec_fair@basic-p...@rcs0.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-kbl6/igt@gem_exec_fair@basic-p...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl:  [PASS][19] -> [FAIL][20] ([i915#2851])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs1.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][21] ([fdo#112283])
   [21]: 

[Intel-gfx] [PATCH] drm/i915/display/: Refactor hsw_crtc_enable for bigjoiner cleanup

[Manasi Navare]

This patch abstracts pieces of hsw_crtc_enable corresponding to different
Bspec enable sequence steps into separate functions.
This helps to call them in a specific order for bigjoiner master/slave
in a cleaner fashion.

Cc: Ville Syrjälä 
Cc: Animesh Manna 
Signed-off-by: Manasi Navare 
---
 drivers/gpu/drm/i915/display/intel_display.c | 125 ++-
 1 file changed, 66 insertions(+), 59 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index eb49973621f0..d8e6466c9fa0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1865,24 +1865,6 @@ static void hsw_set_frame_start_delay(const struct 
intel_crtc_state *crtc_state)
intel_de_write(dev_priv, reg, val);
 }
 
-static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
-const struct intel_crtc_state 
*crtc_state)
-{
-   struct intel_crtc *master_crtc = intel_master_crtc(crtc_state);
-
-   /*
-* Enable sequence steps 1-7 on bigjoiner master
-*/
-   if (intel_crtc_is_bigjoiner_slave(crtc_state))
-   intel_encoders_pre_pll_enable(state, master_crtc);
-
-   if (crtc_state->shared_dpll)
-   intel_enable_shared_dpll(crtc_state);
-
-   if (intel_crtc_is_bigjoiner_slave(crtc_state))
-   intel_encoders_pre_enable(state, master_crtc);
-}
-
 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state 
*crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -1910,70 +1892,73 @@ static void hsw_configure_cpu_transcoder(const struct 
intel_crtc_state *crtc_sta
hsw_set_transconf(crtc_state);
 }
 
-static void hsw_crtc_enable(struct intel_atomic_state *state,
-   struct intel_crtc *crtc)
+static void hsw_crtc_pre_pll_enable(struct intel_atomic_state *state,
+   const struct intel_crtc_state *crtc_state)
 {
-   const struct intel_crtc_state *new_crtc_state =
-   intel_atomic_get_new_crtc_state(state, crtc);
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
-   enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
-   bool psl_clkgate_wa;
-
-   if (drm_WARN_ON(_priv->drm, crtc->active))
-   return;
+   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
-   if (!new_crtc_state->bigjoiner_pipes) {
-   intel_encoders_pre_pll_enable(state, crtc);
+   /*
+* Enable sequence steps 1 - 7 on all pipes
+*/
+   intel_encoders_pre_pll_enable(state, crtc);
+   if (crtc_state->shared_dpll)
+   intel_enable_shared_dpll(crtc_state);
 
-   if (new_crtc_state->shared_dpll)
-   intel_enable_shared_dpll(new_crtc_state);
+   intel_encoders_pre_enable(state, crtc);
+}
 
-   intel_encoders_pre_enable(state, crtc);
-   } else {
-   icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
-   }
+static void hsw_crtc_post_pll_enable(struct intel_atomic_state *state,
+const struct intel_crtc_state *crtc_state)
+{
+   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+   enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
+   enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+   bool psl_clkgate_wa;
 
-   intel_dsc_enable(new_crtc_state);
+   /*
+* Enable sequence step 8
+*/
+   intel_dsc_enable(crtc_state);
 
if (DISPLAY_VER(dev_priv) >= 13)
-   intel_uncompressed_joiner_enable(new_crtc_state);
+   intel_uncompressed_joiner_enable(crtc_state);
 
-   intel_set_pipe_src_size(new_crtc_state);
+   intel_set_pipe_src_size(crtc_state);
if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
-   bdw_set_pipemisc(new_crtc_state);
+   bdw_set_pipemisc(crtc_state);
 
-   if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
+   if (!intel_crtc_is_bigjoiner_slave(crtc_state) &&
!transcoder_is_dsi(cpu_transcoder))
-   hsw_configure_cpu_transcoder(new_crtc_state);
+   hsw_configure_cpu_transcoder(crtc_state);
 
crtc->active = true;
 
/* Display WA #1180: WaDisableScalarClockGating: glk */
psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
-   new_crtc_state->pch_pfit.enabled;
+   crtc_state->pch_pfit.enabled;
if (psl_clkgate_wa)
glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
 
if (DISPLAY_VER(dev_priv) >= 9)
-   skl_pfit_enable(new_crtc_state);
+   skl_pfit_enable(crtc_state);
  

[Intel-gfx] ✓ Fi.CI.IGT: success for Add GuC Error Capture Support (rev2)

[Patchwork]

== Series Details ==

Series: Add GuC Error Capture Support (rev2)
URL   : https://patchwork.freedesktop.org/series/101348/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11365_full -> Patchwork_22573_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22573_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_eio@in-flight-suspend:
- {shard-rkl}:[PASS][1] -> [FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-rkl-1/igt@gem_...@in-flight-suspend.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/shard-rkl-4/igt@gem_...@in-flight-suspend.html

  * igt@gem_exec_schedule@submit-early-slice@vecs0:
- {shard-dg1}:NOTRUN -> [INCOMPLETE][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/shard-dg1-17/igt@gem_exec_schedule@submit-early-sl...@vecs0.html

  
Known issues


  Here are the changes found in Patchwork_22573_full that come from known 
issues:

### IGT changes ###

 Issues hit 

  * igt@feature_discovery@chamelium:
- shard-iclb: NOTRUN -> [SKIP][4] ([fdo#111827])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/shard-iclb7/igt@feature_discov...@chamelium.html

  * igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][5] -> [FAIL][6] ([i915#232])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-tglb7/igt@gem_...@unwedge-stress.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/shard-tglb2/igt@gem_...@unwedge-stress.html

  * igt@gem_exec_capture@pi@vecs0:
- shard-skl:  NOTRUN -> [INCOMPLETE][7] ([i915#4547])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/shard-skl3/igt@gem_exec_capture@p...@vecs0.html

  * igt@gem_exec_fair@basic-deadline:
- shard-skl:  NOTRUN -> [FAIL][8] ([i915#2846])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/shard-skl8/igt@gem_exec_f...@basic-deadline.html
- shard-apl:  NOTRUN -> [FAIL][9] ([i915#2846])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/shard-apl1/igt@gem_exec_f...@basic-deadline.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-tglb: [PASS][10] -> [FAIL][11] ([i915#2842])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-tglb6/igt@gem_exec_fair@basic-none-...@rcs0.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/shard-tglb3/igt@gem_exec_fair@basic-none-...@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar 
issue
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-iclb3/igt@gem_exec_fair@basic-pace-s...@rcs0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/shard-iclb6/igt@gem_exec_fair@basic-pace-s...@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl:  [PASS][14] -> [FAIL][15] ([i915#2842])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-kbl4/igt@gem_exec_fair@basic-p...@vcs1.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/shard-kbl1/igt@gem_exec_fair@basic-p...@vcs1.html

  * igt@gem_exec_params@secure-non-root:
- shard-iclb: NOTRUN -> [SKIP][16] ([fdo#112283])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/shard-iclb7/igt@gem_exec_par...@secure-non-root.html

  * igt@gem_exec_whisper@basic-fds-forked-all:
- shard-glk:  [PASS][17] -> [DMESG-WARN][18] ([i915#118])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/shard-glk9/igt@gem_exec_whis...@basic-fds-forked-all.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/shard-glk2/igt@gem_exec_whis...@basic-fds-forked-all.html

  * igt@gem_lmem_swapping@heavy-multi:
- shard-apl:  NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +2 
similar issues
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/shard-apl2/igt@gem_lmem_swapp...@heavy-multi.html

  * igt@gem_lmem_swapping@heavy-random:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#4613])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/shard-iclb7/igt@gem_lmem_swapp...@heavy-random.html

  * igt@gem_lmem_swapping@parallel-random:
- shard-skl:  NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/shard-skl1/igt@gem_lmem_swapp...@parallel-random.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: 

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: More DRRS work (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: More DRRS work (rev2)
URL   : https://patchwork.freedesktop.org/series/101390/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11365 -> Patchwork_22579


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/index.html

Participating hosts (48 -> 40)
--

  Additional (2): fi-kbl-soraka bat-dg2-8 
  Missing(10): shard-tglu bat-dg1-6 fi-hsw-4200u bat-dg2-9 fi-bsw-cyan 
fi-ctg-p8600 bat-rpls-1 shard-rkl shard-dg1 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22579:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_flip@basic-flip-vs-wf_vblank:
- {bat-dg2-8}:NOTRUN -> [SKIP][1] +22 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/bat-dg2-8/igt@kms_flip@basic-flip-vs-wf_vblank.html

  
Known issues


  Here are the changes found in Patchwork_22579 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271]) +9 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][5] ([i915#1886])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@dp-edid-read:
- fi-kbl-soraka:  NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#533])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  
 Possible fixes 

  * igt@i915_selftest@live@gtt:
- fi-bdw-5557u:   [DMESG-FAIL][8] ([i915#3674]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/fi-bdw-5557u/igt@i915_selftest@l...@gtt.html

  * igt@i915_selftest@live@perf:
- {bat-rpls-2}:   [DMESG-WARN][10] ([i915#4391]) -> [PASS][11] +1 
similar issue
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-rpls-2/igt@i915_selftest@l...@perf.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/bat-rpls-2/igt@i915_selftest@l...@perf.html

  * igt@i915_selftest@live@workarounds:
- {bat-adlp-6}:   [DMESG-WARN][12] ([i915#5068]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/bat-adlp-6/igt@i915_selftest@l...@workarounds.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}:   [DMESG-WARN][14] ([i915#3576]) -> [PASS][15] +1 
similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22579/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3555]: 

[Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: More DRRS work (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: More DRRS work (rev2)
URL   : https://patchwork.freedesktop.org/series/101390/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:230: warning: Excess function 
parameter 'crtc_state' description in 'intel_drrs_deactivate'
./drivers/gpu/drm/i915/display/intel_drrs.c:230: warning: Excess function 
parameter 'crtc_state' description in 'intel_drrs_deactivate'
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not 
found
./drivers/gpu/drm/i915/display/intel_drrs.c:230: warning: Excess function 
parameter 'crtc_state' description in 'intel_drrs_deactivate'
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' 
not found
./drivers/gpu/drm/i915/display/intel_drrs.c:230: warning: Excess function 
parameter 'crtc_state' description in 'intel_drrs_deactivate'
./drivers/gpu/drm/i915/display/intel_drrs.c:230: warning: Excess function 
parameter 'crtc_state' description in 'intel_drrs_deactivate'
./drivers/gpu/drm/i915/display/intel_drrs.c:230: warning: Excess function 
parameter 'crtc_state' description in 'intel_drrs_deactivate'

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/adlp: More voltage swing table updates

[Patchwork]

== Series Details ==

Series: drm/i915/display/adlp: More voltage swing table updates
URL   : https://patchwork.freedesktop.org/series/101404/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11365 -> Patchwork_22578


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/index.html

Participating hosts (48 -> 38)
--

  Additional (2): fi-kbl-soraka fi-pnv-d510 
  Missing(12): shard-tglu bat-dg1-6 fi-hsw-4200u bat-dg2-9 fi-bsw-cyan 
fi-kbl-7500u fi-ctg-p8600 bat-rpls-1 shard-rkl shard-dg1 bat-jsl-2 fi-bdw-samus 

Known issues


  Here are the changes found in Patchwork_22578 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][1] ([fdo#109271]) +9 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][2] ([fdo#109271]) +57 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][5] ([i915#1886])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@dp-edid-read:
- fi-kbl-soraka:  NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-pnv-d510:NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#5341])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/fi-pnv-d510/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
- fi-cfl-8109u:   [PASS][8] -> [DMESG-WARN][9] ([i915#295] / 
[i915#5341])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/fi-cfl-8109u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#533])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-cfl-8109u:   [PASS][11] -> [DMESG-WARN][12] ([i915#295]) +11 
similar issues
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/fi-cfl-8109u/igt@kms_pipe_crc_ba...@read-crc-pipe-b.html

  * igt@runner@aborted:
- fi-bdw-5557u:   NOTRUN -> [FAIL][13] ([i915#2426] / [i915#4312])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/fi-bdw-5557u/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_pm_rpm@module-reload:
- {bat-rpls-2}:   [FAIL][14] ([i915#5323]) -> [PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-rpls-2/igt@i915_pm_...@module-reload.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/bat-rpls-2/igt@i915_pm_...@module-reload.html

  * igt@i915_selftest@live@workarounds:
- {bat-adlp-6}:   [DMESG-WARN][16] ([i915#5068]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/bat-adlp-6/igt@i915_selftest@l...@workarounds.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
- {bat-adlp-6}:   [DMESG-WARN][18] ([i915#3576]) -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-adlp-6/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22578/bat-adlp-6/igt@kms_flip@basic-flip-vs-wf_vbl...@a-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: 

[Intel-gfx] [PATCH v2 7/9] drm/i915: Do DRRS disable/enable during pre/post_plane_update()

[Ville Syrjala]

From: Ville Syrjälä 

Let's just do a full DRRS disable/enable across all pipe updates.
This guarantees that the DRRS work doesn't interfere with anything
while the atomic commit is busy reprogramming the pipe.

Needed so that we can start reprogramming M/N seamlessly during
fastsets whenever possible. Also avoids the pre-bdw DRRS PIPECONF
rmw racing with the potential PIPECONF write from the atomic
commit (eg. due to GAMMA_MODE changes).

v2: Include has_drrs in state dump (José)

Reviewed-by: José Roberto de Souza 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  4 --
 drivers/gpu/drm/i915/display/intel_display.c | 13 +++
 drivers/gpu/drm/i915/display/intel_drrs.c| 40 ++--
 drivers/gpu/drm/i915/display/intel_drrs.h|  3 --
 4 files changed, 10 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
b/drivers/gpu/drm/i915/display/intel_ddi.c
index e2b297d2c295..dc208df829f1 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -45,7 +45,6 @@
 #include "intel_dp_link_training.h"
 #include "intel_dp_mst.h"
 #include "intel_dpio_phy.h"
-#include "intel_drrs.h"
 #include "intel_dsi.h"
 #include "intel_fdi.h"
 #include "intel_fifo_underrun.h"
@@ -3010,12 +3009,9 @@ static void intel_ddi_update_pipe_dp(struct 
intel_atomic_state *state,
 const struct intel_crtc_state *crtc_state,
 const struct drm_connector_state 
*conn_state)
 {
-   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-
intel_ddi_set_dp_msa(crtc_state, conn_state);
 
intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
-   intel_drrs_update(state, crtc);
 
intel_backlight_update(state, encoder, crtc_state, conn_state);
drm_connector_update_privacy_screen(conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
b/drivers/gpu/drm/i915/display/intel_display.c
index eb49973621f0..b4dda23bcb70 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1229,7 +1229,6 @@ static void intel_post_plane_update(struct 
intel_atomic_state *state,
 
hsw_ips_post_update(state, crtc);
intel_fbc_post_update(state, crtc);
-   intel_drrs_page_flip(crtc);
 
if (needs_async_flip_vtd_wa(old_crtc_state) &&
!needs_async_flip_vtd_wa(new_crtc_state))
@@ -1247,6 +1246,7 @@ static void intel_post_plane_update(struct 
intel_atomic_state *state,
!needs_cursorclk_wa(new_crtc_state))
icl_wa_cursorclkgating(dev_priv, pipe, false);
 
+   intel_drrs_enable(new_crtc_state);
 }
 
 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
@@ -1324,6 +1324,8 @@ static void intel_pre_plane_update(struct 
intel_atomic_state *state,
intel_atomic_get_new_crtc_state(state, crtc);
enum pipe pipe = crtc->pipe;
 
+   intel_drrs_disable(old_crtc_state);
+
intel_psr_pre_plane_update(state, crtc);
 
if (hsw_ips_pre_update(state, crtc))
@@ -5442,8 +5444,9 @@ static void intel_dump_pipe_config(const struct 
intel_crtc_state *pipe_config,
str_enabled_disabled(pipe_config->pch_pfit.enabled),
str_yes_no(pipe_config->pch_pfit.force_thru));
 
-   drm_dbg_kms(_priv->drm, "ips: %i, double wide: %i\n",
-   pipe_config->ips_enabled, pipe_config->double_wide);
+   drm_dbg_kms(_priv->drm, "ips: %i, double wide: %i, drrs: %i\n",
+   pipe_config->ips_enabled, pipe_config->double_wide,
+   pipe_config->has_drrs);
 
intel_dpll_dump_hw_state(dev_priv, _config->dpll_hw_state);
 
@@ -8127,8 +8130,6 @@ static void intel_enable_crtc(struct intel_atomic_state 
*state,
if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
return;
 
-   intel_drrs_enable(new_crtc_state);
-
/* vblanks work again, re-enable pipe CRC. */
intel_crtc_enable_pipe_crc(crtc);
 }
@@ -8198,8 +8199,6 @@ static void intel_old_crtc_state_disables(struct 
intel_atomic_state *state,
 */
intel_crtc_disable_pipe_crc(crtc);
 
-   intel_drrs_disable(old_crtc_state);
-
dev_priv->display->crtc_disable(state, crtc);
crtc->active = false;
intel_fbc_disable(crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c 
b/drivers/gpu/drm/i915/display/intel_drrs.c
index 8f9e0fde0c5a..44c9af8f8b9b 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -189,13 +189,12 @@ static unsigned int intel_drrs_frontbuffer_bits(const 
struct intel_crtc_state *c
 void intel_drrs_enable(const struct intel_crtc_state *crtc_state)
 {
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-   struct drm_i915_private *dev_priv = 

[Intel-gfx] ✗ Fi.CI.BAT: failure for Add CDCLK checks to atomic check phase (rev4)

[Patchwork]

== Series Details ==

Series: Add CDCLK checks to atomic check phase (rev4)
URL   : https://patchwork.freedesktop.org/series/101068/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11365 -> Patchwork_22577


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22577 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22577, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22577/index.html

Participating hosts (48 -> 26)
--

  Additional (1): fi-kbl-soraka 
  Missing(23): fi-rkl-11600 bat-dg1-6 fi-apl-guc bat-rpls-1 shard-dg1 
fi-bdw-5557u shard-tglu fi-adl-ddr5 fi-glk-dsi bat-dg2-9 fi-kbl-7500u 
fi-ctg-p8600 fi-skl-6700k2 fi-skl-guc fi-cfl-8700k bat-jsl-2 fi-hsw-4200u 
fi-bsw-cyan fi-cfl-guc fi-kbl-x1275 fi-cfl-8109u shard-rkl fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22577:

### IGT changes ###

 Possible regressions 

  * igt@gem_exec_suspend@basic-s0@smem:
- fi-bsw-nick:[PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-bsw-nick/igt@gem_exec_suspend@basic...@smem.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22577/fi-bsw-nick/igt@gem_exec_suspend@basic...@smem.html
- fi-glk-j4005:   [PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-glk-j4005/igt@gem_exec_suspend@basic...@smem.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22577/fi-glk-j4005/igt@gem_exec_suspend@basic...@smem.html
- fi-rkl-guc: [PASS][5] -> [INCOMPLETE][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-rkl-guc/igt@gem_exec_suspend@basic...@smem.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22577/fi-rkl-guc/igt@gem_exec_suspend@basic...@smem.html
- fi-bsw-kefka:   [PASS][7] -> [INCOMPLETE][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-bsw-kefka/igt@gem_exec_suspend@basic...@smem.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22577/fi-bsw-kefka/igt@gem_exec_suspend@basic...@smem.html
- fi-bsw-n3050:   [PASS][9] -> [INCOMPLETE][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-bsw-n3050/igt@gem_exec_suspend@basic...@smem.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22577/fi-bsw-n3050/igt@gem_exec_suspend@basic...@smem.html
- fi-bxt-dsi: [PASS][11] -> [INCOMPLETE][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-bxt-dsi/igt@gem_exec_suspend@basic...@smem.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22577/fi-bxt-dsi/igt@gem_exec_suspend@basic...@smem.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_suspend@basic-s0@smem:
- {fi-ehl-2}: [PASS][13] -> [INCOMPLETE][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22577/fi-ehl-2/igt@gem_exec_suspend@basic...@smem.html
- {fi-jsl-1}: [PASS][15] -> [INCOMPLETE][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-jsl-1/igt@gem_exec_suspend@basic...@smem.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22577/fi-jsl-1/igt@gem_exec_suspend@basic...@smem.html
- {fi-tgl-dsi}:   [PASS][17] -> [INCOMPLETE][18]
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-tgl-dsi/igt@gem_exec_suspend@basic...@smem.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22577/fi-tgl-dsi/igt@gem_exec_suspend@basic...@smem.html
- {bat-adlp-6}:   [PASS][19] -> [INCOMPLETE][20]
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-adlp-6/igt@gem_exec_suspend@basic...@smem.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22577/bat-adlp-6/igt@gem_exec_suspend@basic...@smem.html

  * igt@runner@aborted:
- {bat-jsl-1}:NOTRUN -> [FAIL][21]
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22577/bat-jsl-1/igt@run...@aborted.html

  
Known issues


  Here are the changes found in Patchwork_22577 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][22] ([fdo#109271]) +9 similar issues
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22577/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
   

[Intel-gfx] [PATCH] drm/i915/display/adlp: More voltage swing table updates

[José Roberto de Souza]

A few more updates in the alderlake-P voltage swing tables.

eDP HBR3 table was the same as icelake one but now it has changes for
voltage 0 and pre-emphasis 2 line.
And DP tables also had one line change in each.

Bspec: 49291
Signed-off-by: José Roberto de Souza 
---
 .../drm/i915/display/intel_ddi_buf_trans.c| 22 +++
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c 
b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 9a2b14927895e..94e64661b4fdb 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -907,7 +907,7 @@ static const union intel_ddi_buf_trans_entry 
_adlp_combo_phy_trans_dp_hbr[] = {
{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500  0.0   
*/
{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700  2.9   
*/
{ .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500   900  5.1   
*/
-   { .icl = { 0xC, 0x73, 0x3E, 0x00, 0x01 } }, /* 650   700  0.6   
*/
+   { .icl = { 0xC, 0x7C, 0x3C, 0x00, 0x03 } }, /* 650   700  0.6   
*/
{ .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600   900  3.5   
*/
{ .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900  0.0   
*/
 };
@@ -921,7 +921,7 @@ static const union intel_ddi_buf_trans_entry 
_adlp_combo_phy_trans_dp_hbr2_hbr3[
/* NT mV Trans mV db
*/
{ .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350  0.0   
*/
{ .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500  3.1   
*/
-   { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } }, /* 350   700  6.0   
*/
+   { .icl = { 0xC, 0x71, 0x30, 0x00, 0x0F } }, /* 350   700  6.0   
*/
{ .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350   900  8.2   
*/
{ .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500  0.0   
*/
{ .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700  2.9   
*/
@@ -945,14 +945,28 @@ static const union intel_ddi_buf_trans_entry 
_adlp_combo_phy_trans_edp_hbr2[] =
{ .icl = { 0x4, 0x7A, 0x38, 0x00, 0x07 } }, /* 350   350  0.0   
*/
 };
 
+static const union intel_ddi_buf_trans_entry 
_adlp_combo_phy_trans_dp_hbr2_edp_hbr3[] = {
+   /* NT mV Trans mV db
*/
+   { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } }, /* 350   350  0.0   
*/
+   { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } }, /* 350   500  3.1   
*/
+   { .icl = { 0xC, 0x71, 0x30, 0x00, 0x0f } }, /* 350   700  6.0   
*/
+   { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } }, /* 350   900  8.2   
*/
+   { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } }, /* 500   500  0.0   
*/
+   { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } }, /* 500   700  2.9   
*/
+   { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } }, /* 500   900  5.1   
*/
+   { .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } }, /* 650   700  0.6   
*/
+   { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } }, /* 600   900  3.5   
*/
+   { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } }, /* 900   900  0.0   
*/
+};
+
 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr2_hbr3 = {
.entries = _adlp_combo_phy_trans_dp_hbr2_hbr3,
.num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_hbr3),
 };
 
 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_hbr3 = {
-   .entries = _icl_combo_phy_trans_dp_hbr2_edp_hbr3,
-   .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_dp_hbr2_edp_hbr3),
+   .entries = _adlp_combo_phy_trans_dp_hbr2_edp_hbr3,
+   .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_edp_hbr3),
 };
 
 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_up_to_hbr2 = {
-- 
2.35.1

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/7] drm/i915/lmem: don't treat small BAR as an error

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/7] drm/i915/lmem: don't treat small BAR as 
an error
URL   : https://patchwork.freedesktop.org/series/101398/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11365 -> Patchwork_22576


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/index.html

Participating hosts (48 -> 41)
--

  Additional (3): fi-kbl-soraka bat-dg2-8 fi-pnv-d510 
  Missing(10): shard-tglu fi-hsw-4200u shard-rkl bat-dg2-9 fi-bsw-cyan 
fi-cfl-guc fi-ctg-p8600 bat-rpls-2 shard-dg1 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22576:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_flip@basic-flip-vs-wf_vblank:
- {bat-dg2-8}:NOTRUN -> [SKIP][1] +22 similar issues
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/bat-dg2-8/igt@kms_flip@basic-flip-vs-wf_vblank.html

  
Known issues


  Here are the changes found in Patchwork_22576 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][2] ([fdo#109271]) +9 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][3] ([fdo#109271]) +57 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-kbl-soraka:  NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][6] ([i915#1886])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][7] -> [INCOMPLETE][8] ([i915#4785])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_chamelium@dp-edid-read:
- fi-kbl-soraka:  NOTRUN -> [SKIP][9] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-pnv-d510:NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#5341])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/fi-pnv-d510/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#533])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#1436] / 
[i915#4312])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/fi-hsw-4770/igt@run...@aborted.html
- fi-bdw-5557u:   NOTRUN -> [FAIL][13] ([i915#2426] / [i915#4312])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/fi-bdw-5557u/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_selftest@live@hangcheck:
- bat-dg1-6:  [DMESG-FAIL][14] ([i915#4494] / [i915#4957]) -> 
[PASS][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@workarounds:
- {bat-adlp-6}:   [DMESG-WARN][16] ([i915#5068]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22576/bat-adlp-6/igt@i915_selftest@l...@workarounds.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}:   [DMESG-WARN][18] ([i915#3576]) -> [PASS][19] +1 
similar issue
   [18]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add CDCLK checks to atomic check phase (rev4)

[Patchwork]

== Series Details ==

Series: Add CDCLK checks to atomic check phase (rev4)
URL   : https://patchwork.freedesktop.org/series/101068/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add CDCLK checks to atomic check phase (rev4)

[Patchwork]

== Series Details ==

Series: Add CDCLK checks to atomic check phase (rev4)
URL   : https://patchwork.freedesktop.org/series/101068/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
84e79f618db6 drm/i915/display: Add CDCLK actions to intel_cdclk_state
9ddce2b162f8 drm/i915/display: s/intel_cdclk_can_squash/intel_cdclk_squash
-:28: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#28: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1980:
 {
+

total: 0 errors, 0 warnings, 1 checks, 40 lines checked
daf67d3fddca drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl
-:25: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#25: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:1955:
+static bool intel_cdclk_crawl(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_state *a,

total: 0 errors, 0 warnings, 1 checks, 42 lines checked
7fc8824172e5 drm/i915/display: Add cdclk checks to atomic check
-:197: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#197: FILE: drivers/gpu/drm/i915/display/intel_cdclk.c:2053:
 {
+

total: 0 errors, 0 warnings, 1 checks, 180 lines checked

Re: [Intel-gfx] [PATCH 9/9] drm/i915: s/enable/active/ for DRRS

[Ville Syrjälä]

On Tue, Mar 15, 2022 at 06:54:21PM +, Souza, Jose wrote:
> On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> > 
> > Rename the DRRS functiosn to say "(de)activate" rather than
> > "enable/disable". This let's us differentiate between the
> > logically enabled vs. actually currently active cases.
> > 
> > Signed-off-by: Ville Syrjälä 
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  |  4 ++--
> >  .../drm/i915/display/intel_display_debugfs.c  | 15 -
> >  drivers/gpu/drm/i915/display/intel_drrs.c | 22 ++-
> >  drivers/gpu/drm/i915/display/intel_drrs.h |  6 ++---
> >  4 files changed, 27 insertions(+), 20 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 86fc8ddd0b8f..90d54281535d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1246,7 +1246,7 @@ static void intel_post_plane_update(struct 
> > intel_atomic_state *state,
> > !needs_cursorclk_wa(new_crtc_state))
> > icl_wa_cursorclkgating(dev_priv, pipe, false);
> >  
> > -   intel_drrs_enable(new_crtc_state);
> > +   intel_drrs_activate(new_crtc_state);
> >  }
> >  
> >  static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
> > @@ -1324,7 +1324,7 @@ static void intel_pre_plane_update(struct 
> > intel_atomic_state *state,
> > intel_atomic_get_new_crtc_state(state, crtc);
> > enum pipe pipe = crtc->pipe;
> >  
> > -   intel_drrs_disable(old_crtc_state);
> > +   intel_drrs_deactivate(old_crtc_state);
> >  
> > intel_psr_pre_plane_update(state, crtc);
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
> > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index e0a126e7ebb8..18b98788b23e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -1159,6 +1159,9 @@ static int i915_drrs_status(struct seq_file *m, void 
> > *unused)
> > seq_puts(m, "\n");
> >  
> > for_each_intel_crtc(_priv->drm, crtc) {
> > +   const struct intel_crtc_state *crtc_state =
> > +   to_intel_crtc_state(crtc->base.state);
> > +
> > seq_printf(m, "[CRTC:%d:%s]:\n",
> >crtc->base.base.id, crtc->base.name);
> >  
> > @@ -1166,7 +1169,10 @@ static int i915_drrs_status(struct seq_file *m, void 
> > *unused)
> >  
> > /* DRRS Supported */
> > seq_printf(m, "\tDRRS Enabled: %s\n",
> > -  str_yes_no(intel_drrs_is_enabled(crtc)));
> > +  str_yes_no(crtc_state->has_drrs));
> > +
> > +   seq_printf(m, "\tDRRS Active: %s\n",
> > +  str_yes_no(intel_drrs_is_active(crtc)));
> 
> So there is no way to know if the worker thread have activated the downclock 
> mode?
> I prefer to have the "activated" as meaning that the downlock is in use.

The "DRRS refresh rate" print shows if we're actually running at
high or low refresh rate right now.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH 7/9] drm/i915: Do DRRS disable/enable during pre/post_plane_update()

[Ville Syrjälä]

On Tue, Mar 15, 2022 at 06:48:12PM +, Souza, Jose wrote:
> On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> > @@ -217,13 +216,12 @@ void intel_drrs_enable(const struct intel_crtc_state 
> > *crtc_state)
> >  void intel_drrs_disable(const struct intel_crtc_state *old_crtc_state)
> >  {
> > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> > -   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  
> > if (!old_crtc_state->has_drrs)
> > return;
> >  
> > -   drm_dbg_kms(_priv->drm, "[CRTC:%d:%s] Disabling DRRS\n",
> > -   crtc->base.base.id, crtc->base.name);
> > +   if (!old_crtc_state->hw.active)
> > +   return;
> 
> 
> Changes looks good but now there will not be any DRRS debug message, can you 
> at least add debug message in intel_drrs_compute_config() when DRRS is
> allowed?

I think we should just add it to the crtc state dump. It's sort of there
already by way of non-zero M2/N2, but I guess having a more explicit debug
for it wouldn't hurt.

> 
> With that:
> 
> Reviewed-by: José Roberto de Souza 

Thanks.

-- 
Ville Syrjälä
Intel

[Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915: ttm for stolen

[Patchwork]

== Series Details ==

Series: drm/i915: ttm for stolen
URL   : https://patchwork.freedesktop.org/series/101396/
State : warning

== Summary ==

CALLscripts/checksyscalls.sh
  CALLscripts/atomic/check-atomics.sh
  CHK include/generated/compile.h
  CC [M]  drivers/gpu/drm/i915/display/intel_fbc.o
In file included from ./include/drm/ttm/ttm_resource.h:32,
 from ./include/drm/ttm/ttm_device.h:30,
 from ./drivers/gpu/drm/i915/i915_drv.h:41,
 from drivers/gpu/drm/i915/display/intel_fbc.c:45:
drivers/gpu/drm/i915/display/intel_fbc.c: In function ‘intel_fbc_alloc_cfb’:
drivers/gpu/drm/i915/display/intel_fbc.c:800:7: error: format ‘%lu’ expects 
argument of type ‘long unsigned int’, but argument 4 has type ‘size_t’ {aka 
‘unsigned int’} [-Werror=format=]
   "reserved %lu bytes of contiguous stolen space for FBC, limit: %d\n",
   ^~~~
   fbc->compressed_fb->base.size, fbc->limit);
   ~
./include/drm/drm_print.h:463:53: note: in definition of macro ‘drm_dbg_kms’
  drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_KMS, fmt, ##__VA_ARGS__)
 ^~~
cc1: all warnings being treated as errors
scripts/Makefile.build:288: recipe for target 
'drivers/gpu/drm/i915/display/intel_fbc.o' failed
make[4]: *** [drivers/gpu/drm/i915/display/intel_fbc.o] Error 1
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1831: recipe for target 'drivers' failed
make: *** [drivers] Error 2

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22575/build_32bit.log

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: ttm for stolen

[Patchwork]

== Series Details ==

Series: drm/i915: ttm for stolen
URL   : https://patchwork.freedesktop.org/series/101396/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11365 -> Patchwork_22575


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_22575 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22575, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22575/index.html

Participating hosts (48 -> 34)
--

  Additional (3): fi-kbl-soraka bat-dg2-8 bat-adls-5 
  Missing(17): fi-bxt-dsi shard-tglu fi-hsw-4200u shard-rkl fi-glk-dsi 
bat-dg2-9 fi-cfl-8700k fi-bsw-cyan fi-kbl-7500u fi-ctg-p8600 fi-cfl-guc 
fi-glk-j4005 fi-kbl-x1275 fi-cfl-8109u bat-rpls-2 shard-dg1 fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22575:

### IGT changes ###

 Possible regressions 

  * igt@debugfs_test@read_all_entries:
- fi-elk-e7500:   [PASS][1] -> [INCOMPLETE][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-elk-e7500/igt@debugfs_test@read_all_entries.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22575/fi-elk-e7500/igt@debugfs_test@read_all_entries.html
- fi-snb-2600:[PASS][3] -> [INCOMPLETE][4]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-snb-2600/igt@debugfs_test@read_all_entries.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22575/fi-snb-2600/igt@debugfs_test@read_all_entries.html
- fi-blb-e6850:   [PASS][5] -> [INCOMPLETE][6]
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-blb-e6850/igt@debugfs_test@read_all_entries.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22575/fi-blb-e6850/igt@debugfs_test@read_all_entries.html
- fi-bwr-2160:[PASS][7] -> [INCOMPLETE][8]
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-bwr-2160/igt@debugfs_test@read_all_entries.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22575/fi-bwr-2160/igt@debugfs_test@read_all_entries.html
- fi-snb-2520m:   [PASS][9] -> [INCOMPLETE][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-snb-2520m/igt@debugfs_test@read_all_entries.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22575/fi-snb-2520m/igt@debugfs_test@read_all_entries.html
- fi-ilk-650: [PASS][11] -> [INCOMPLETE][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-ilk-650/igt@debugfs_test@read_all_entries.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22575/fi-ilk-650/igt@debugfs_test@read_all_entries.html
- fi-kbl-soraka:  NOTRUN -> [INCOMPLETE][13]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22575/fi-kbl-soraka/igt@debugfs_test@read_all_entries.html

  * igt@i915_selftest@live@mman:
- fi-bsw-nick:[PASS][14] -> [INCOMPLETE][15]
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-bsw-nick/igt@i915_selftest@l...@mman.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22575/fi-bsw-nick/igt@i915_selftest@l...@mman.html

  * igt@kms_busy@basic@flip:
- fi-tgl-1115g4:  [PASS][16] -> [INCOMPLETE][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-tgl-1115g4/igt@kms_busy@ba...@flip.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22575/fi-tgl-1115g4/igt@kms_busy@ba...@flip.html

  * igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-7567u:   [PASS][18] -> [DMESG-WARN][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-kbl-7567u/igt@kms_force_connector_ba...@force-connector-state.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22575/fi-kbl-7567u/igt@kms_force_connector_ba...@force-connector-state.html
- fi-kbl-guc: [PASS][20] -> [DMESG-WARN][21]
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-kbl-guc/igt@kms_force_connector_ba...@force-connector-state.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22575/fi-kbl-guc/igt@kms_force_connector_ba...@force-connector-state.html

  * igt@runner@aborted:
- fi-bdw-gvtdvm:  NOTRUN -> [FAIL][22]
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22575/fi-bdw-gvtdvm/igt@run...@aborted.html
- fi-ivb-3770:NOTRUN -> [FAIL][23]
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22575/fi-ivb-3770/igt@run...@aborted.html

  
 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@debugfs_test@read_all_entries:
- 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [CI,1/7] drm/i915/lmem: don't treat small BAR as an error

[Patchwork]

== Series Details ==

Series: series starting with [CI,1/7] drm/i915/lmem: don't treat small BAR as 
an error
URL   : https://patchwork.freedesktop.org/series/101398/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] [PATCH 2/4] drm/i915/display: s/intel_cdclk_can_squash/intel_cdclk_squash

[Anusha Srivatsa]

Apart from checking if squashing can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.

Cc: Jani Nikula 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 21 +++--
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index fda8b701..1f879af15d87 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1973,10 +1973,11 @@ static bool intel_cdclk_can_crawl(struct 
drm_i915_private *dev_priv,
a->ref == b->ref;
 }
 
-static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
-  const struct intel_cdclk_config *a,
-  const struct intel_cdclk_config *b)
+static bool intel_cdclk_squash(struct drm_i915_private *dev_priv,
+  const struct intel_cdclk_state *a,
+  struct intel_cdclk_state *b)
 {
+
/*
 * FIXME should store a bit more state in intel_cdclk_config
 * to differentiate squasher vs. cd2x divider properly. For
@@ -1986,10 +1987,10 @@ static bool intel_cdclk_can_squash(struct 
drm_i915_private *dev_priv,
if (!has_cdclk_squasher(dev_priv))
return false;
 
-   return a->cdclk != b->cdclk &&
-   a->vco != 0 &&
-   a->vco == b->vco &&
-   a->ref == b->ref;
+   return a->actual.cdclk != b->actual.cdclk &&
+   a->actual.vco != 0 &&
+   a->actual.vco == b->actual.vco &&
+   a->actual.ref == b->actual.ref;
 }
 
 /**
@@ -2776,9 +2777,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state 
*state)
pipe = INVALID_PIPE;
}
 
-   if (intel_cdclk_can_squash(dev_priv,
-  _cdclk_state->actual,
-  _cdclk_state->actual)) {
+   if (intel_cdclk_squash(dev_priv,
+  old_cdclk_state,
+  new_cdclk_state)) {
drm_dbg_kms(_priv->drm,
"Can change cdclk via squasher\n");
} else if (intel_cdclk_can_crawl(dev_priv,
-- 
2.25.1

[Intel-gfx] [PATCH 3/4] drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl

[Anusha Srivatsa]

Apart from checking if crawling can be performed,
accommodate accessing in-flight cdclk state for any changes
that are needed during commit phase.

Cc: Jani Nikula 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 1f879af15d87..3007710984d4 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1951,9 +1951,9 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
skl_cdclk_uninit_hw(i915);
 }
 
-static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
- const struct intel_cdclk_config *a,
- const struct intel_cdclk_config *b)
+static bool intel_cdclk_crawl(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_state *a,
+ struct intel_cdclk_state *b)
 {
int a_div, b_div;
 
@@ -1964,13 +1964,13 @@ static bool intel_cdclk_can_crawl(struct 
drm_i915_private *dev_priv,
 * The vco and cd2x divider will change independently
 * from each, so we disallow cd2x change when crawling.
 */
-   a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
-   b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
+   a_div = DIV_ROUND_CLOSEST(a->actual.vco, a->actual.cdclk);
+   b_div = DIV_ROUND_CLOSEST(b->actual.vco, b->actual.cdclk);
 
-   return a->vco != 0 && b->vco != 0 &&
-   a->vco != b->vco &&
+   return a->actual.vco != 0 && b->actual.vco != 0 &&
+   a->actual.vco != b->actual.vco &&
a_div == b_div &&
-   a->ref == b->ref;
+   a->actual.ref == b->actual.ref;
 }
 
 static bool intel_cdclk_squash(struct drm_i915_private *dev_priv,
@@ -2782,9 +2782,9 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state 
*state)
   new_cdclk_state)) {
drm_dbg_kms(_priv->drm,
"Can change cdclk via squasher\n");
-   } else if (intel_cdclk_can_crawl(dev_priv,
-_cdclk_state->actual,
-_cdclk_state->actual)) {
+   } else if (intel_cdclk_crawl(dev_priv,
+old_cdclk_state,
+new_cdclk_state)) {
drm_dbg_kms(_priv->drm,
"Can change cdclk via crawl\n");
} else if (pipe != INVALID_PIPE) {
-- 
2.25.1

[Intel-gfx] [PATCH 4/4] drm/i915/display: Add cdclk checks to atomic check

[Anusha Srivatsa]

Checking cdclk conditions during atomic check and preparing
for commit phase so we can have atomic commit as simple
as possible. Add the specific steps to be taken during
cdclk changes, prepare for squashing, crawling and modeset
scenarios.

v2: Add intel_cdclk_modeset() similar to intel_cdclk_squash()
and intel_cdclk_crawl().

Cc: Jani Nikula 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 115 +++--
 1 file changed, 81 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c 
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 3007710984d4..1efeee4200f0 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1700,12 +1700,23 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
  const struct intel_cdclk_config *cdclk_config,
  enum pipe pipe)
 {
+   struct intel_atomic_state *state;
+   struct intel_cdclk_state *new_cdclk_state;
+   struct cdclk_step *cdclk_steps;
+   struct intel_cdclk_state *cdclk_state;
int cdclk = cdclk_config->cdclk;
int vco = cdclk_config->vco;
+   u32 squash_ctl = 0;
u32 val;
u16 waveform;
int clock;
int ret;
+   int i;
+
+   cdclk_state =  to_intel_cdclk_state(dev_priv->cdclk.obj.state);
+   state = cdclk_state->base.state;
+   new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
+   cdclk_steps = new_cdclk_state->steps;
 
/* Inform power controller of upcoming frequency change. */
if (DISPLAY_VER(dev_priv) >= 11)
@@ -1728,45 +1739,48 @@ static void bxt_set_cdclk(struct drm_i915_private 
*dev_priv,
return;
}
 
-   if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) 
{
-   if (dev_priv->cdclk.hw.vco != vco)
+   for (i = 0; i < MAX_CDCLK_ACTIONS; i++) {
+   switch (cdclk_steps[i].action) {
+   case INTEL_CDCLK_MODESET:
+   if (DISPLAY_VER(dev_priv) >= 11) {
+   if (dev_priv->cdclk.hw.vco != 0 &&
+   dev_priv->cdclk.hw.vco != vco)
+   icl_cdclk_pll_disable(dev_priv);
+
+   if (dev_priv->cdclk.hw.vco != vco)
+   icl_cdclk_pll_enable(dev_priv, vco);
+   } else {
+   if (dev_priv->cdclk.hw.vco != 0 &&
+   dev_priv->cdclk.hw.vco != vco)
+   bxt_de_pll_disable(dev_priv);
+
+   if (dev_priv->cdclk.hw.vco != vco)
+   bxt_de_pll_enable(dev_priv, vco);
+   }
+   clock = cdclk;
+   break;
+   case INTEL_CDCLK_CRAWL:
adlp_cdclk_pll_crawl(dev_priv, vco);
-   } else if (DISPLAY_VER(dev_priv) >= 11) {
-   if (dev_priv->cdclk.hw.vco != 0 &&
-   dev_priv->cdclk.hw.vco != vco)
-   icl_cdclk_pll_disable(dev_priv);
-
-   if (dev_priv->cdclk.hw.vco != vco)
-   icl_cdclk_pll_enable(dev_priv, vco);
-   } else {
-   if (dev_priv->cdclk.hw.vco != 0 &&
-   dev_priv->cdclk.hw.vco != vco)
-   bxt_de_pll_disable(dev_priv);
-
-   if (dev_priv->cdclk.hw.vco != vco)
-   bxt_de_pll_enable(dev_priv, vco);
-   }
-
-   waveform = cdclk_squash_waveform(dev_priv, cdclk);
-
-   if (waveform)
-   clock = vco / 2;
-   else
-   clock = cdclk;
-
-   if (has_cdclk_squasher(dev_priv)) {
-   u32 squash_ctl = 0;
-
-   if (waveform)
+   clock = cdclk;
+   break;
+   case INTEL_CDCLK_SQUASH:
+   waveform =  cdclk_squash_waveform(dev_priv, 
cdclk_steps[i].cdclk);
+   clock = vco / 2;
squash_ctl = CDCLK_SQUASH_ENABLE |
-   CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
-
-   intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
+   CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
+   intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl);
+   break;
+   case INTEL_CDCLK_NOOP:
+   break;
+   default:
+   MISSING_CASE(cdclk_steps[i].action);
+   break;
+   }
}
 
val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
-   bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
-   skl_cdclk_decimal(cdclk);
+ bxt_cdclk_cd2x_pipe(dev_priv, pipe) |

[Intel-gfx] [PATCH 1/4] drm/i915/display: Add CDCLK actions to intel_cdclk_state

[Anusha Srivatsa]

This is a prep patch for what the rest of the series does.

Add existing actions that change cdclk - squash, crawl, modeset to
intel_cdclk_state so we have access to the cdclk values
that are in transition.

Cc: Jani Nikula 
Signed-off-by: Anusha Srivatsa 
---
 drivers/gpu/drm/i915/display/intel_cdclk.h | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h 
b/drivers/gpu/drm/i915/display/intel_cdclk.h
index df66f66fbad0..06d7f9f0b253 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -15,6 +15,14 @@ struct drm_i915_private;
 struct intel_atomic_state;
 struct intel_crtc_state;
 
+enum cdclk_actions {
+   INTEL_CDCLK_MODESET = 0,
+   INTEL_CDCLK_SQUASH,
+   INTEL_CDCLK_CRAWL,
+   INTEL_CDCLK_NOOP,
+   MAX_CDCLK_ACTIONS
+};
+
 struct intel_cdclk_config {
unsigned int cdclk, vco, ref, bypass;
u8 voltage_level;
@@ -49,6 +57,11 @@ struct intel_cdclk_state {
 
/* bitmask of active pipes */
u8 active_pipes;
+
+   struct cdclk_step {
+   enum cdclk_actions action;
+   u32 cdclk;
+   } steps[MAX_CDCLK_ACTIONS];
 };
 
 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
-- 
2.25.1

[Intel-gfx] [PATCH 0/5] Add CDCLK checks to atomic check phase

[Anusha Srivatsa]

This version splits the original patch into simpler units.

The intention is to check for squashing, crawling conditions
at atomic check phase and prepare for commit phase. This basically
means the in-flight cdclk state is available. intel_cdclk_can_squash(),
intel_cdclk_can_crawl() and intel_cdclk_needs_modeset() have changes
to accommodate this.

v2: Introduce intel_cdclk_modeset() instead of cramming
all changes into intel_cdclk_needs_modeset().

Cc: Stanislav Lisovskiy 

Anusha Srivatsa (5):
  drm/i915/display: Add CDCLK actions to intel_cdclk_state
  drm/i915/display: s/intel_cdclk_can_squash/intel_cdclk_squash
  drm/i915/display: s/intel_cdclk_can_crawl/intel_cdclk_crawl
  drm/i915/display: Add drm_i915_private to intel_cdclk_needs_modeset()
  drm/i915/display: Add cdclk checks to atomic check

 drivers/gpu/drm/i915/display/intel_cdclk.c| 172 +++---
 drivers/gpu/drm/i915/display/intel_cdclk.h|  16 +-
 .../drm/i915/display/intel_display_power.c|   2 +-
 3 files changed, 125 insertions(+), 65 deletions(-)

-- 
2.25.1

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Add CDCLK checks to atomic check phase (rev3)

[Srivatsa, Anusha]

Checked the logs, a lot of machines not showing tests results even though 
igt_run.txt shows as PASS for most. The boot log shows ACL errors in 
/var/log/journal/ , sending the series again.

Anusha

From: Patchwork 
Sent: Friday, March 11, 2022 12:55 AM
To: Srivatsa, Anusha 
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: failure for Add CDCLK checks to atomic check phase (rev3)

Patch Details
Series:

Add CDCLK checks to atomic check phase (rev3)

URL:

https://patchwork.freedesktop.org/series/101068/

State:

failure

Details:

https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22540/index.html

CI Bug Log - changes from CI_DRM_11350 -> Patchwork_22540
Summary

FAILURE

Serious unknown changes coming with Patchwork_22540 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22540, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22540/index.html

Participating hosts (48 -> 27)

Additional (2): fi-kbl-soraka fi-pnv-d510
Missing (23): fi-rkl-11600 bat-dg1-6 bat-dg1-5 fi-icl-u2 fi-apl-guc bat-rpls-2 
shard-dg1 fi-bdw-5557u shard-tglu fi-adl-ddr5 fi-glk-dsi fi-kbl-7500u 
fi-ctg-p8600 fi-skl-6700k2 fi-skl-guc fi-cfl-8700k fi-hsw-4200u fi-bsw-cyan 
fi-cfl-guc fi-kbl-x1275 fi-cfl-8109u shard-rkl fi-bdw-samus

Possible new issues

Here are the unknown changes that may have been introduced in Patchwork_22540:

IGT changes
Possible regressions

  *   igt@gem_exec_suspend@basic-s0@smem:

 *   fi-bsw-nick: 
PASS
 -> 
INCOMPLETE
 *   fi-glk-j4005: 
PASS
 -> 
INCOMPLETE
 *   fi-rkl-guc: 
PASS
 -> 
INCOMPLETE
 *   fi-bsw-kefka: 
PASS
 -> 
INCOMPLETE
 *   fi-bsw-n3050: 
PASS
 -> 
INCOMPLETE
 *   fi-bxt-dsi: 
PASS
 -> 
INCOMPLETE

Suppressed

The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.

  *   igt@gem_exec_suspend@basic-s0@smem:

 *   {fi-ehl-2}: 
PASS
 -> 
INCOMPLETE
 *   {fi-jsl-1}: 
PASS
 -> 
INCOMPLETE
 *   {fi-tgl-dsi}: 
PASS
 -> 
INCOMPLETE
 *   {bat-adlp-6}: 
PASS
 -> 
INCOMPLETE

  *   igt@runner@aborted:

 *   {bat-jsl-1}: NOTRUN -> 
FAIL

Known issues

Here are the changes found in Patchwork_22540 that come from known issues:

IGT changes
Issues hit

  *   igt@amdgpu/amd_basic@cs-gfx:

 *   fi-hsw-4770: NOTRUN -> 
SKIP
 (fdo#109271 / 
fdo#109315) +17 similar 

[Intel-gfx] ✓ Fi.CI.BAT: success for i915: General multicast steering updates (rev2)

[Patchwork]

== Series Details ==

Series: i915: General multicast steering updates (rev2)
URL   : https://patchwork.freedesktop.org/series/101367/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11365 -> Patchwork_22574


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/index.html

Participating hosts (47 -> 45)
--

  Additional (4): fi-kbl-soraka bat-dg2-8 bat-adlm-1 fi-pnv-d510 
  Missing(6): shard-tglu fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 shard-rkl 
fi-bdw-samus 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22574:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@gt_heartbeat:
- {fi-tgl-dsi}:   [PASS][1] -> [DMESG-FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html

  * igt@kms_cursor_legacy@basic-flip-before-cursor-legacy:
- {bat-adlm-1}:   NOTRUN -> [INCOMPLETE][3]
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/bat-adlm-1/igt@kms_cursor_leg...@basic-flip-before-cursor-legacy.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
- {bat-dg2-8}:NOTRUN -> [SKIP][4] +22 similar issues
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/bat-dg2-8/igt@kms_flip@basic-flip-vs-wf_vblank.html

  
Known issues


  Here are the changes found in Patchwork_22574 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka:  NOTRUN -> [SKIP][5] ([fdo#109271]) +9 similar issues
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html

  * igt@gem_huc_copy@huc-copy:
- fi-pnv-d510:NOTRUN -> [SKIP][6] ([fdo#109271]) +57 similar issues
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/fi-pnv-d510/igt@gem_huc_c...@huc-copy.html
- fi-kbl-soraka:  NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- fi-kbl-soraka:  NOTRUN -> [SKIP][8] ([fdo#109271] / [i915#4613]) +3 
similar issues
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/fi-kbl-soraka/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka:  NOTRUN -> [DMESG-FAIL][9] ([i915#1886])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@kms_chamelium@dp-edid-read:
- fi-kbl-soraka:  NOTRUN -> [SKIP][10] ([fdo#109271] / [fdo#111827]) +8 
similar issues
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/fi-kbl-soraka/igt@kms_chamel...@dp-edid-read.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-pnv-d510:NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#5341])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/fi-pnv-d510/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-c.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka:  NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#533])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-bdw-5557u:   [PASS][13] -> [INCOMPLETE][14] ([i915#146] / 
[i915#])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-bdw-5557u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/fi-bdw-5557u/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html

  
 Possible fixes 

  * igt@i915_pm_rps@basic-api:
- bat-dg1-6:  [FAIL][15] ([i915#4032]) -> [PASS][16]
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-dg1-6/igt@i915_pm_...@basic-api.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/bat-dg1-6/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@perf:
- {bat-rpls-2}:   [DMESG-WARN][17] ([i915#4391]) -> [PASS][18] +1 
similar issue
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-rpls-2/igt@i915_selftest@l...@perf.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22574/bat-rpls-2/igt@i915_selftest@l...@perf.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
- {bat-adlp-6}:   [DMESG-WARN][19] 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: ttm for stolen

[Patchwork]

== Series Details ==

Series: drm/i915: ttm for stolen
URL   : https://patchwork.freedesktop.org/series/101396/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: ttm for stolen

[Patchwork]

== Series Details ==

Series: drm/i915: ttm for stolen
URL   : https://patchwork.freedesktop.org/series/101396/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
26eebf54d3e6 drm/i915: instantiate ttm ranger manager for stolen memory
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

total: 0 errors, 1 warnings, 0 checks, 57 lines checked
882cbce55afd drm/i915: add ability to create memory region object in place
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

total: 0 errors, 1 warnings, 0 checks, 189 lines checked
f844b84b6eeb drm/i915: use gem objects to track stolen nodes
-:66: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#66: FILE: drivers/gpu/drm/i915/display/intel_fbc.c:507:
+   intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id),
+   i915_gem_object_stolen_offset(fbc->compressed_fb));

-:243: CHECK:LINE_SPACING: Please don't use multiple blank lines
#243: FILE: drivers/gpu/drm/i915/gem/i915_gem_stolen.c:969:
+
+

total: 0 errors, 0 warnings, 2 checks, 230 lines checked
743f6cc618c7 drm/i915: stolen memory use ttm backend
-:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one

total: 0 errors, 1 warnings, 0 checks, 516 lines checked
5045ae7a8418 drm/ttm: add range busy check for range manager
-:33: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#33: FILE: drivers/gpu/drm/ttm/ttm_range_manager.c:220:
+ unsigned fpfn, unsigned lpfn)

-:33: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#33: FILE: drivers/gpu/drm/ttm/ttm_range_manager.c:220:
+ unsigned fpfn, unsigned lpfn)

-:53: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#53: FILE: include/drm/ttm/ttm_range_manager.h:58:
+ unsigned fpfn, unsigned lpfn);

-:53: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned'
#53: FILE: include/drm/ttm/ttm_range_manager.h:58:
+ unsigned fpfn, unsigned lpfn);

total: 0 errors, 4 warnings, 0 checks, 31 lines checked
9ed1deb99315 drm/i915: add range busy check for ttm region
673869ce0f7c drm/i915: cleanup old stolen state

[Intel-gfx] ✓ Fi.CI.BAT: success for Add GuC Error Capture Support (rev2)

[Patchwork]

== Series Details ==

Series: Add GuC Error Capture Support (rev2)
URL   : https://patchwork.freedesktop.org/series/101348/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11365 -> Patchwork_22573


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/index.html

Participating hosts (45 -> 42)
--

  Additional (1): bat-dg2-8 
  Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u 

Possible new issues
---

  Here are the unknown changes that may have been introduced in Patchwork_22573:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_selftest@live@gt_pm:
- {bat-rpls-2}:   [PASS][1] -> [DMESG-FAIL][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/bat-rpls-2/igt@i915_selftest@live@gt_pm.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
- {bat-dg2-8}:NOTRUN -> [SKIP][3] +22 similar issues
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/bat-dg2-8/igt@kms_flip@basic-flip-vs-wf_vblank.html

  
Known issues


  Here are the changes found in Patchwork_22573 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][4] -> [INCOMPLETE][5] ([i915#3303])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html

  * igt@runner@aborted:
- fi-bdw-5557u:   NOTRUN -> [FAIL][6] ([i915#2426] / [i915#4312])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/fi-bdw-5557u/igt@run...@aborted.html
- fi-hsw-4770:NOTRUN -> [FAIL][7] ([fdo#109271] / [i915#1436] / 
[i915#4312])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/fi-hsw-4770/igt@run...@aborted.html

  
 Possible fixes 

  * igt@i915_pm_rps@basic-api:
- bat-dg1-6:  [FAIL][8] ([i915#4032]) -> [PASS][9]
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-dg1-6/igt@i915_pm_...@basic-api.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/bat-dg1-6/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@perf:
- {bat-rpls-2}:   [DMESG-WARN][10] ([i915#4391]) -> [PASS][11]
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-rpls-2/igt@i915_selftest@l...@perf.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/bat-rpls-2/igt@i915_selftest@l...@perf.html

  * igt@i915_selftest@live@workarounds:
- {bat-adlp-6}:   [DMESG-WARN][12] ([i915#5068]) -> [PASS][13]
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-adlp-6/igt@i915_selftest@l...@workarounds.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/bat-adlp-6/igt@i915_selftest@l...@workarounds.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}:   [DMESG-WARN][14] ([i915#3576]) -> [PASS][15] +1 
similar issue
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11365/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22573/bat-adlp-6/igt@kms_flip@basic-flip-vs-mode...@a-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: 

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for i915: General multicast steering updates (rev2)

[Patchwork]

== Series Details ==

Series: i915: General multicast steering updates (rev2)
URL   : https://patchwork.freedesktop.org/series/101367/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [Intel-gfx] [PATCH 9/9] drm/i915: s/enable/active/ for DRRS

[Souza, Jose]

On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Rename the DRRS functiosn to say "(de)activate" rather than
> "enable/disable". This let's us differentiate between the
> logically enabled vs. actually currently active cases.
> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |  4 ++--
>  .../drm/i915/display/intel_display_debugfs.c  | 15 -
>  drivers/gpu/drm/i915/display/intel_drrs.c | 22 ++-
>  drivers/gpu/drm/i915/display/intel_drrs.h |  6 ++---
>  4 files changed, 27 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 86fc8ddd0b8f..90d54281535d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1246,7 +1246,7 @@ static void intel_post_plane_update(struct 
> intel_atomic_state *state,
>   !needs_cursorclk_wa(new_crtc_state))
>   icl_wa_cursorclkgating(dev_priv, pipe, false);
>  
> - intel_drrs_enable(new_crtc_state);
> + intel_drrs_activate(new_crtc_state);
>  }
>  
>  static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
> @@ -1324,7 +1324,7 @@ static void intel_pre_plane_update(struct 
> intel_atomic_state *state,
>   intel_atomic_get_new_crtc_state(state, crtc);
>   enum pipe pipe = crtc->pipe;
>  
> - intel_drrs_disable(old_crtc_state);
> + intel_drrs_deactivate(old_crtc_state);
>  
>   intel_psr_pre_plane_update(state, crtc);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index e0a126e7ebb8..18b98788b23e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1159,6 +1159,9 @@ static int i915_drrs_status(struct seq_file *m, void 
> *unused)
>   seq_puts(m, "\n");
>  
>   for_each_intel_crtc(_priv->drm, crtc) {
> + const struct intel_crtc_state *crtc_state =
> + to_intel_crtc_state(crtc->base.state);
> +
>   seq_printf(m, "[CRTC:%d:%s]:\n",
>  crtc->base.base.id, crtc->base.name);
>  
> @@ -1166,7 +1169,10 @@ static int i915_drrs_status(struct seq_file *m, void 
> *unused)
>  
>   /* DRRS Supported */
>   seq_printf(m, "\tDRRS Enabled: %s\n",
> -str_yes_no(intel_drrs_is_enabled(crtc)));
> +str_yes_no(crtc_state->has_drrs));
> +
> + seq_printf(m, "\tDRRS Active: %s\n",
> +str_yes_no(intel_drrs_is_active(crtc)));

So there is no way to know if the worker thread have activated the downclock 
mode?
I prefer to have the "activated" as meaning that the downlock is in use.

>  
>   seq_printf(m, "\tBusy_frontbuffer_bits: 0x%X\n",
>  crtc->drrs.busy_frontbuffer_bits);
> @@ -1864,13 +1870,12 @@ static int i915_drrs_ctl_set(void *data, u64 val)
>   }
>  
>   drm_dbg(_priv->drm,
> - "Manually %sabling DRRS. %llu\n",
> - val ? "en" : "dis", val);
> + "Manually %sactivating DRRS\n", val ? "" : "de");
>  
>   if (val)
> - intel_drrs_enable(crtc_state);
> + intel_drrs_activate(crtc_state);
>   else
> - intel_drrs_disable(crtc_state);
> + intel_drrs_deactivate(crtc_state);
>  
>  out:
>   drm_modeset_unlock(>base.mutex);
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c 
> b/drivers/gpu/drm/i915/display/intel_drrs.c
> index 9a341ab1a848..7703d5a801f9 100644
> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> @@ -147,7 +147,7 @@ intel_drrs_set_refresh_rate_m_n(struct intel_crtc *crtc,
>  >drrs.m2_n2 : >drrs.m_n);
>  }
>  
> -bool intel_drrs_is_enabled(struct intel_crtc *crtc)
> +bool intel_drrs_is_active(struct intel_crtc *crtc)
>  {
>   return crtc->drrs.cpu_transcoder != INVALID_TRANSCODER;
>  }
> @@ -189,12 +189,12 @@ static unsigned int intel_drrs_frontbuffer_bits(const 
> struct intel_crtc_state *c
>  }
>  
>  /**
> - * intel_drrs_enable - init drrs struct if supported
> - * @crtc_state: A pointer to the active crtc state.
> + * intel_drrs_activate - activate DRRS
> + * @crtc_state: the crtc state
>   *
> - * Initializes frontbuffer_bits and drrs.dp
> + * Activates DRRS on the crtc.
>   */
> -void intel_drrs_enable(const struct intel_crtc_state *crtc_state)
> +void intel_drrs_activate(const struct intel_crtc_state *crtc_state)
>  {
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  
> @@ -221,10 +221,12 @@ void intel_drrs_enable(const struct intel_crtc_state 
> 

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: General multicast steering updates (rev2)

[Patchwork]

== Series Details ==

Series: i915: General multicast steering updates (rev2)
URL   : https://patchwork.freedesktop.org/series/101367/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b9726a99fbeb drm/i915: Report steering details in debugfs
-:32: WARNING:STATIC_CONST_CHAR_ARRAY: static const char * array should 
probably be static const char * const
#32: FILE: drivers/gpu/drm/i915/gt/intel_gt.c:99:
+static const char *intel_steering_types[] = {

total: 0 errors, 1 warnings, 0 checks, 122 lines checked
ec0dbb3841d1 drm/i915/guc: add steering info to GuC register save/restore list
c390edc727c1 drm/i915: Add support for steered register writes

Re: [Intel-gfx] [PATCH 00/22] drm: Review of mode copies

[Alex Deucher]

On Mon, Mar 14, 2022 at 6:12 PM Ville Syrjälä
 wrote:
>
> On Fri, Feb 18, 2022 at 12:03:41PM +0200, Ville Syrjala wrote:
> >   drm: Add drm_mode_init()
> >   drm/bridge: Use drm_mode_copy()
> >   drm/imx: Use drm_mode_duplicate()
> >   drm/panel: Use drm_mode_duplicate()
> >   drm/vc4: Use drm_mode_copy()
> These have been pushed to drm-misc-next.
>
> >   drm/amdgpu: Remove pointless on stack mode copies
> >   drm/amdgpu: Use drm_mode_init() for on-stack modes
> >   drm/amdgpu: Use drm_mode_copy()
> amdgpu ones are reviewed, but I'll leave them for the
> AMD folks to push to whichever tree they prefer.

I pulled patches 2, 4, 5 into my tree.  For 3, I'm happy to have it
land via drm-misc with the rest of the mode_init changes if you'd
prefer.

Alex


Alex

>
>
> The rest are still in need of review:
> >   drm/radeon: Use drm_mode_copy()
> >   drm/gma500: Use drm_mode_copy()
> >   drm/hisilicon: Use drm_mode_init() for on-stack modes
> >   drm/msm: Nuke weird on stack mode copy
> >   drm/msm: Use drm_mode_init() for on-stack modes
> >   drm/msm: Use drm_mode_copy()
> >   drm/mtk: Use drm_mode_init() for on-stack modes
> >   drm/rockchip: Use drm_mode_copy()
> >   drm/sti: Use drm_mode_copy()
> >   drm/tilcdc: Use drm_mode_copy()
> >   drm/i915: Use drm_mode_init() for on-stack modes
> >   drm/i915: Use drm_mode_copy()
> >   drm: Use drm_mode_init() for on-stack modes
> >   drm: Use drm_mode_copy()
>
> --
> Ville Syrjälä
> Intel

Re: [Intel-gfx] [PATCH 04/22] drm/amdgpu: Use drm_mode_copy()

[Alex Deucher]

Applied.  Thanks!

Alex

On Fri, Feb 18, 2022 at 11:32 AM Harry Wentland  wrote:
>
>
>
> On 2022-02-18 05:03, Ville Syrjala wrote:
> > From: Ville Syrjälä 
> >
> > struct drm_display_mode embeds a list head, so overwriting
> > the full struct with another one will corrupt the list
> > (if the destination mode is on a list). Use drm_mode_copy()
> > instead which explicitly preserves the list head of
> > the destination mode.
> >
> > Even if we know the destination mode is not on any list
> > using drm_mode_copy() seems decent as it sets a good
> > example. Bad examples of not using it might eventually
> > get copied into code where preserving the list head
> > actually matters.
> >
> > Obviously one case not covered here is when the mode
> > itself is embedded in a larger structure and the whole
> > structure is copied. But if we are careful when copying
> > into modes embedded in structures I think we can be a
> > little more reassured that bogus list heads haven't been
> > propagated in.
> >
> > @is_mode_copy@
> > @@
> > drm_mode_copy(...)
> > {
> > ...
> > }
> >
> > @depends on !is_mode_copy@
> > struct drm_display_mode *mode;
> > expression E, S;
> > @@
> > (
> > - *mode = E
> > + drm_mode_copy(mode, )
> > |
> > - memcpy(mode, E, S)
> > + drm_mode_copy(mode, E)
> > )
> >
> > @depends on !is_mode_copy@
> > struct drm_display_mode mode;
> > expression E;
> > @@
> > (
> > - mode = E
> > + drm_mode_copy(, )
> > |
> > - memcpy(, E, S)
> > + drm_mode_copy(, E)
> > )
> >
> > @@
> > struct drm_display_mode *mode;
> > @@
> > - &*mode
> > + mode
> >
> > Cc: Alex Deucher 
> > Cc: Harry Wentland 
> > Cc: Leo Li 
> > Cc: Rodrigo Siqueira 
> > Cc: amd-...@lists.freedesktop.org
> > Signed-off-by: Ville Syrjälä 
>
> Reviewed-by: Harry Wentland 
>
> Harry
>
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c| 4 ++--
> >  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++---
> >  2 files changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > index fa20261aa928..673078faa27a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > @@ -626,7 +626,7 @@ amdgpu_connector_fixup_lcd_native_mode(struct 
> > drm_encoder *encoder,
> >   if (mode->type & DRM_MODE_TYPE_PREFERRED) {
> >   if (mode->hdisplay != native_mode->hdisplay ||
> >   mode->vdisplay != native_mode->vdisplay)
> > - memcpy(native_mode, mode, sizeof(*mode));
> > + drm_mode_copy(native_mode, mode);
> >   }
> >   }
> >
> > @@ -635,7 +635,7 @@ amdgpu_connector_fixup_lcd_native_mode(struct 
> > drm_encoder *encoder,
> >   list_for_each_entry_safe(mode, t, >probed_modes, 
> > head) {
> >   if (mode->hdisplay == native_mode->hdisplay &&
> >   mode->vdisplay == native_mode->vdisplay) {
> > - *native_mode = *mode;
> > + drm_mode_copy(native_mode, mode);
> >   drm_mode_set_crtcinfo(native_mode, 
> > CRTC_INTERLACE_HALVE_V);
> >   DRM_DEBUG_KMS("Determined LVDS native mode 
> > details from EDID\n");
> >   break;
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > index bd23c9e481eb..514280699ad5 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > @@ -6318,7 +6318,7 @@ get_highest_refresh_rate_mode(struct 
> > amdgpu_dm_connector *aconnector,
> >   }
> >   }
> >
> > - aconnector->freesync_vid_base = *m_pref;
> > + drm_mode_copy(>freesync_vid_base, m_pref);
> >   return m_pref;
> >  }
> >
> > @@ -6432,8 +6432,8 @@ create_stream_for_sink(struct amdgpu_dm_connector 
> > *aconnector,
> >   recalculate_timing = is_freesync_video_mode(, 
> > aconnector);
> >   if (recalculate_timing) {
> >   freesync_mode = 
> > get_highest_refresh_rate_mode(aconnector, false);
> > - saved_mode = mode;
> > - mode = *freesync_mode;
> > + drm_mode_copy(_mode, );
> > + drm_mode_copy(, freesync_mode);
> >   } else {
> >   decide_crtc_timing_for_drm_display_mode(
> >   , preferred_mode, scale);
>

Re: [Intel-gfx] [PATCH 05/22] drm/radeon: Use drm_mode_copy()

[Alex Deucher]

Applied.  Thanks!

Alex

On Fri, Feb 18, 2022 at 5:04 AM Ville Syrjala
 wrote:
>
> From: Ville Syrjälä 
>
> struct drm_display_mode embeds a list head, so overwriting
> the full struct with another one will corrupt the list
> (if the destination mode is on a list). Use drm_mode_copy()
> instead which explicitly preserves the list head of
> the destination mode.
>
> Even if we know the destination mode is not on any list
> using drm_mode_copy() seems decent as it sets a good
> example. Bad examples of not using it might eventually
> get copied into code where preserving the list head
> actually matters.
>
> Obviously one case not covered here is when the mode
> itself is embedded in a larger structure and the whole
> structure is copied. But if we are careful when copying
> into modes embedded in structures I think we can be a
> little more reassured that bogus list heads haven't been
> propagated in.
>
> @is_mode_copy@
> @@
> drm_mode_copy(...)
> {
> ...
> }
>
> @depends on !is_mode_copy@
> struct drm_display_mode *mode;
> expression E, S;
> @@
> (
> - *mode = E
> + drm_mode_copy(mode, )
> |
> - memcpy(mode, E, S)
> + drm_mode_copy(mode, E)
> )
>
> @depends on !is_mode_copy@
> struct drm_display_mode mode;
> expression E;
> @@
> (
> - mode = E
> + drm_mode_copy(, )
> |
> - memcpy(, E, S)
> + drm_mode_copy(, E)
> )
>
> @@
> struct drm_display_mode *mode;
> @@
> - &*mode
> + mode
>
> Cc: Alex Deucher 
> Cc: amd-...@lists.freedesktop.org
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/radeon/radeon_connectors.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
> b/drivers/gpu/drm/radeon/radeon_connectors.c
> index a7925a8290b2..0cb1345c6ba4 100644
> --- a/drivers/gpu/drm/radeon/radeon_connectors.c
> +++ b/drivers/gpu/drm/radeon/radeon_connectors.c
> @@ -777,7 +777,7 @@ static void radeon_fixup_lvds_native_mode(struct 
> drm_encoder *encoder,
> if (mode->type & DRM_MODE_TYPE_PREFERRED) {
> if (mode->hdisplay != native_mode->hdisplay ||
> mode->vdisplay != native_mode->vdisplay)
> -   memcpy(native_mode, mode, sizeof(*mode));
> +   drm_mode_copy(native_mode, mode);
> }
> }
>
> @@ -786,7 +786,7 @@ static void radeon_fixup_lvds_native_mode(struct 
> drm_encoder *encoder,
> list_for_each_entry_safe(mode, t, >probed_modes, 
> head) {
> if (mode->hdisplay == native_mode->hdisplay &&
> mode->vdisplay == native_mode->vdisplay) {
> -   *native_mode = *mode;
> +   drm_mode_copy(native_mode, mode);
> drm_mode_set_crtcinfo(native_mode, 
> CRTC_INTERLACE_HALVE_V);
> DRM_DEBUG_KMS("Determined LVDS native mode 
> details from EDID\n");
> break;
> --
> 2.34.1
>

Re: [Intel-gfx] [PATCH 7/9] drm/i915: Do DRRS disable/enable during pre/post_plane_update()

[Souza, Jose]

On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Let's just do a full DRRS disable/enable across all pipe updates.
> This guarantees that the DRRS work doesn't interfere with anything
> while the atomic commit is busy reprogramming the pipe.
> 
> Needed so that we can start reprogramming M/N seamlessly during
> fastsets whenever possible. Also avoids the pre-bdw DRRS PIPECONF
> rmw racing with the potential PIPECONF write from the atomic
> commit (eg. due to GAMMA_MODE changes).
> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c |  4 --
>  drivers/gpu/drm/i915/display/intel_display.c |  8 ++--
>  drivers/gpu/drm/i915/display/intel_drrs.c| 40 ++--
>  drivers/gpu/drm/i915/display/intel_drrs.h|  3 --
>  4 files changed, 7 insertions(+), 48 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c 
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index e2b297d2c295..dc208df829f1 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -45,7 +45,6 @@
>  #include "intel_dp_link_training.h"
>  #include "intel_dp_mst.h"
>  #include "intel_dpio_phy.h"
> -#include "intel_drrs.h"
>  #include "intel_dsi.h"
>  #include "intel_fdi.h"
>  #include "intel_fifo_underrun.h"
> @@ -3010,12 +3009,9 @@ static void intel_ddi_update_pipe_dp(struct 
> intel_atomic_state *state,
>const struct intel_crtc_state *crtc_state,
>const struct drm_connector_state 
> *conn_state)
>  {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -
>   intel_ddi_set_dp_msa(crtc_state, conn_state);
>  
>   intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> - intel_drrs_update(state, crtc);
>  
>   intel_backlight_update(state, encoder, crtc_state, conn_state);
>   drm_connector_update_privacy_screen(conn_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c 
> b/drivers/gpu/drm/i915/display/intel_display.c
> index eb49973621f0..86fc8ddd0b8f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1229,7 +1229,6 @@ static void intel_post_plane_update(struct 
> intel_atomic_state *state,
>  
>   hsw_ips_post_update(state, crtc);
>   intel_fbc_post_update(state, crtc);
> - intel_drrs_page_flip(crtc);
>  
>   if (needs_async_flip_vtd_wa(old_crtc_state) &&
>   !needs_async_flip_vtd_wa(new_crtc_state))
> @@ -1247,6 +1246,7 @@ static void intel_post_plane_update(struct 
> intel_atomic_state *state,
>   !needs_cursorclk_wa(new_crtc_state))
>   icl_wa_cursorclkgating(dev_priv, pipe, false);
>  
> + intel_drrs_enable(new_crtc_state);
>  }
>  
>  static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
> @@ -1324,6 +1324,8 @@ static void intel_pre_plane_update(struct 
> intel_atomic_state *state,
>   intel_atomic_get_new_crtc_state(state, crtc);
>   enum pipe pipe = crtc->pipe;
>  
> + intel_drrs_disable(old_crtc_state);
> +
>   intel_psr_pre_plane_update(state, crtc);
>  
>   if (hsw_ips_pre_update(state, crtc))
> @@ -8127,8 +8129,6 @@ static void intel_enable_crtc(struct intel_atomic_state 
> *state,
>   if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
>   return;
>  
> - intel_drrs_enable(new_crtc_state);
> -
>   /* vblanks work again, re-enable pipe CRC. */
>   intel_crtc_enable_pipe_crc(crtc);
>  }
> @@ -8198,8 +8198,6 @@ static void intel_old_crtc_state_disables(struct 
> intel_atomic_state *state,
>*/
>   intel_crtc_disable_pipe_crc(crtc);
>  
> - intel_drrs_disable(old_crtc_state);
> -
>   dev_priv->display->crtc_disable(state, crtc);
>   crtc->active = false;
>   intel_fbc_disable(crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c 
> b/drivers/gpu/drm/i915/display/intel_drrs.c
> index 8f9e0fde0c5a..44c9af8f8b9b 100644
> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> @@ -189,13 +189,12 @@ static unsigned int intel_drrs_frontbuffer_bits(const 
> struct intel_crtc_state *c
>  void intel_drrs_enable(const struct intel_crtc_state *crtc_state)
>  {
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
>   if (!crtc_state->has_drrs)
>   return;
>  
> - drm_dbg_kms(_priv->drm, "[CRTC:%d:%s] Enabling DRRS\n",
> - crtc->base.base.id, crtc->base.name);
> + if (!crtc_state->hw.active)
> + return;
>  
>   mutex_lock(>drrs.mutex);
>  
> @@ -217,13 +216,12 @@ void intel_drrs_enable(const struct intel_crtc_state 
> *crtc_state)
>  void intel_drrs_disable(const struct intel_crtc_state *old_crtc_state)
>  {
>   struct intel_crtc *crtc = 

Re: [Intel-gfx] [PATCH 1/9] drm/i915: Put the downclock_mode check back into can_enable_drrs()

[Souza, Jose]

On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> With static DRRS the user might ask for the lowest possible refresh
> rate of the panel, in which case we're not going to find a suitable
> downclock mode for it and we should not try to enable seamless DRRS.
> This will in fact oops.
> 
> We used to check for the presence of the downclock mode here, but
> that got removed in commit f0a57798fb5c ("drm/i915: Introduce
> intel_panel_drrs_type()") as redundant (which it was at the time).
> But we do need the check again now that static DRRS is a thing.
> 
> I must have not re-tested static DRRS fully after introducing
> intel_panel_drrs_type() :/


Reviewed-by: José Roberto de Souza 

> 
> Fixes: c5ee23437cae ("drm/i915: Implement static DRRS")
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_drrs.c | 8 +---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c 
> b/drivers/gpu/drm/i915/display/intel_drrs.c
> index 2bbc0388263a..e1b41b772521 100644
> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> @@ -62,7 +62,8 @@ const char *intel_drrs_type_str(enum drrs_type drrs_type)
>  }
>  
>  static bool can_enable_drrs(struct intel_connector *connector,
> - const struct intel_crtc_state *pipe_config)
> + const struct intel_crtc_state *pipe_config,
> + const struct drm_display_mode *downclock_mode)
>  {
>   if (pipe_config->vrr.enable)
>   return false;
> @@ -76,7 +77,8 @@ static bool can_enable_drrs(struct intel_connector 
> *connector,
>   if (pipe_config->has_psr)
>   return false;
>  
> - return intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
> + return downclock_mode &&
> + intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;
>  }
>  
>  void
> @@ -89,7 +91,7 @@ intel_drrs_compute_config(struct intel_connector *connector,
>   intel_panel_downclock_mode(connector, 
> _config->hw.adjusted_mode);
>   int pixel_clock;
>  
> - if (!can_enable_drrs(connector, pipe_config)) {
> + if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
>   if (intel_cpu_transcoder_has_m2_n2(i915, 
> pipe_config->cpu_transcoder))
>   intel_zero_m_n(_config->dp_m2_n2);
>   return;

Re: [Intel-gfx] [PATCH 6/9] drm/i915: Schedule DRRS work from intel_drrs_enable()

[Souza, Jose]

On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Schedule the DRRS downclock work already from intel_drrs_enable()
> instead of waiting around for a frontbuffer flush that may or
> may not ever come.

Reviewed-by: José Roberto de Souza 

> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_drrs.c | 10 --
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c 
> b/drivers/gpu/drm/i915/display/intel_drrs.c
> index f36394fd85be..8f9e0fde0c5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> @@ -168,6 +168,11 @@ static void intel_drrs_set_state(struct intel_crtc *crtc,
>   crtc->drrs.refresh_rate = refresh_rate;
>  }
>  
> +static void intel_drrs_schedule_work(struct intel_crtc *crtc)
> +{
> + mod_delayed_work(system_wq, >drrs.work, msecs_to_jiffies(1000));
> +}
> +
>  static unsigned int intel_drrs_frontbuffer_bits(const struct 
> intel_crtc_state *crtc_state)
>  {
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -200,6 +205,8 @@ void intel_drrs_enable(const struct intel_crtc_state 
> *crtc_state)
>   crtc->drrs.frontbuffer_bits = intel_drrs_frontbuffer_bits(crtc_state);
>   crtc->drrs.busy_frontbuffer_bits = 0;
>  
> + intel_drrs_schedule_work(crtc);
> +
>   mutex_unlock(>drrs.mutex);
>  }
>  
> @@ -299,8 +306,7 @@ static void intel_drrs_frontbuffer_update(struct 
> drm_i915_private *dev_priv,
>* other fbs are quiescent too
>*/
>   if (!crtc->drrs.busy_frontbuffer_bits)
> - mod_delayed_work(system_wq, >drrs.work,
> -  msecs_to_jiffies(1000));
> + intel_drrs_schedule_work(crtc);
>   else
>   cancel_delayed_work(>drrs.work);
>  

Re: [Intel-gfx] [PATCH 5/9] drm/i915: Don't cancel/schedule drrs work if the pipe wasn't affected

[Souza, Jose]

On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Skip all the DRRS work cancel/schedule stuff if the pipe's
> frontbuffer bits were not among those affected by the frontbuffer
> rendering.

Reviewed-by: José Roberto de Souza 

> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_drrs.c | 17 -
>  1 file changed, 8 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c 
> b/drivers/gpu/drm/i915/display/intel_drrs.c
> index 91aab77c495c..f36394fd85be 100644
> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> @@ -278,32 +278,31 @@ static void intel_drrs_frontbuffer_update(struct 
> drm_i915_private *dev_priv,
>   for_each_intel_crtc(_priv->drm, crtc) {
>   unsigned int frontbuffer_bits;
>  
> - cancel_delayed_work(>drrs.work);
> -
>   mutex_lock(>drrs.mutex);
>  
> - if (!intel_drrs_is_enabled(crtc)) {
> + frontbuffer_bits = all_frontbuffer_bits & 
> crtc->drrs.frontbuffer_bits;
> + if (!frontbuffer_bits) {
>   mutex_unlock(>drrs.mutex);
>   continue;
>   }
>  
> - frontbuffer_bits = all_frontbuffer_bits & 
> crtc->drrs.frontbuffer_bits;
>   if (invalidate)
>   crtc->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
>   else
>   crtc->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
>  
>   /* flush/invalidate means busy screen hence upclock */
> - if (frontbuffer_bits)
> - intel_drrs_set_state(crtc, DRRS_REFRESH_RATE_HIGH);
> + intel_drrs_set_state(crtc, DRRS_REFRESH_RATE_HIGH);
>  
>   /*
>* flush also means no more activity hence schedule downclock, 
> if all
>* other fbs are quiescent too
>*/
> - if (!invalidate && !crtc->drrs.busy_frontbuffer_bits)
> - schedule_delayed_work(>drrs.work,
> -   msecs_to_jiffies(1000));
> + if (!crtc->drrs.busy_frontbuffer_bits)
> + mod_delayed_work(system_wq, >drrs.work,
> +  msecs_to_jiffies(1000));
> + else
> + cancel_delayed_work(>drrs.work);
>  
>   mutex_unlock(>drrs.mutex);
>   }

Re: [Intel-gfx] [PATCH 4/9] drm/i195: Determine DRRS frontbuffer_bits ahead of time

[Souza, Jose]

On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Pre-determine the frontbuffer_bits for the each pipe during
> intel_drrs_enable(). Will become useful for bigjoiner use cases
> soon.

Reviewed-by: José Roberto de Souza 

> 
> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
>  drivers/gpu/drm/i915/display/intel_drrs.c  | 11 ++-
>  2 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d84e82f3eab9..c94eb7d5191d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1302,6 +1302,7 @@ struct intel_crtc {
>   struct mutex mutex;
>   struct delayed_work work;
>   enum drrs_refresh_rate refresh_rate;
> + unsigned int frontbuffer_bits;
>   unsigned int busy_frontbuffer_bits;
>   enum transcoder cpu_transcoder;
>   struct intel_link_m_n m_n, m2_n2;
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c 
> b/drivers/gpu/drm/i915/display/intel_drrs.c
> index e9d622fe66b3..91aab77c495c 100644
> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> @@ -168,6 +168,13 @@ static void intel_drrs_set_state(struct intel_crtc *crtc,
>   crtc->drrs.refresh_rate = refresh_rate;
>  }
>  
> +static unsigned int intel_drrs_frontbuffer_bits(const struct 
> intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
> + return INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe);
> +}
> +
>  /**
>   * intel_drrs_enable - init drrs struct if supported
>   * @crtc_state: A pointer to the active crtc state.
> @@ -190,6 +197,7 @@ void intel_drrs_enable(const struct intel_crtc_state 
> *crtc_state)
>   crtc->drrs.cpu_transcoder = crtc_state->cpu_transcoder;
>   crtc->drrs.m_n = crtc_state->dp_m_n;
>   crtc->drrs.m2_n2 = crtc_state->dp_m2_n2;
> + crtc->drrs.frontbuffer_bits = intel_drrs_frontbuffer_bits(crtc_state);
>   crtc->drrs.busy_frontbuffer_bits = 0;
>  
>   mutex_unlock(>drrs.mutex);
> @@ -216,6 +224,7 @@ void intel_drrs_disable(const struct intel_crtc_state 
> *old_crtc_state)
>   intel_drrs_set_state(crtc, DRRS_REFRESH_RATE_HIGH);
>  
>   crtc->drrs.cpu_transcoder = INVALID_TRANSCODER;
> + crtc->drrs.frontbuffer_bits = 0;
>   crtc->drrs.busy_frontbuffer_bits = 0;
>  
>   mutex_unlock(>drrs.mutex);
> @@ -278,7 +287,7 @@ static void intel_drrs_frontbuffer_update(struct 
> drm_i915_private *dev_priv,
>   continue;
>   }
>  
> - frontbuffer_bits = all_frontbuffer_bits & 
> INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe);
> + frontbuffer_bits = all_frontbuffer_bits & 
> crtc->drrs.frontbuffer_bits;
>   if (invalidate)
>   crtc->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
>   else

Re: [Intel-gfx] [PATCH 3/9] drm/i915: Fix DRRS frontbuffer_bits handling

[Souza, Jose]

On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> Now that DRRS can operate on multiple pipes we need to make sure
> one pipe doesn't throw away the other pipe's frontbuffer_bits before
> said pipe can handle them.
> 

Reviewed-by: José Roberto de Souza 

> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_drrs.c | 6 --
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c 
> b/drivers/gpu/drm/i915/display/intel_drrs.c
> index e1b41b772521..e9d622fe66b3 100644
> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> @@ -258,7 +258,7 @@ static void intel_drrs_downclock_work(struct work_struct 
> *work)
>  }
>  
>  static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv,
> -   unsigned int frontbuffer_bits,
> +   unsigned int all_frontbuffer_bits,
> bool invalidate)
>  {
>   struct intel_crtc *crtc;
> @@ -267,6 +267,8 @@ static void intel_drrs_frontbuffer_update(struct 
> drm_i915_private *dev_priv,
>   return;
>  
>   for_each_intel_crtc(_priv->drm, crtc) {
> + unsigned int frontbuffer_bits;
> +
>   cancel_delayed_work(>drrs.work);
>  
>   mutex_lock(>drrs.mutex);
> @@ -276,7 +278,7 @@ static void intel_drrs_frontbuffer_update(struct 
> drm_i915_private *dev_priv,
>   continue;
>   }
>  
> - frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe);
> + frontbuffer_bits = all_frontbuffer_bits & 
> INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe);
>   if (invalidate)
>   crtc->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
>   else

Re: [Intel-gfx] [PATCH 2/9] drm/i915: Add missing tab to DRRS debugfs

[Souza, Jose]

On Tue, 2022-03-15 at 15:27 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> The DRRS refresh rate should be indented by one tab like the
> other per-crtc DRRS stuff.
> 

Reviewed-by: José Roberto de Souza 

> Signed-off-by: Ville Syrjälä 
> ---
>  drivers/gpu/drm/i915/display/intel_display_debugfs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c 
> b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index b3d426cc3266..e0a126e7ebb8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -1171,7 +1171,7 @@ static int i915_drrs_status(struct seq_file *m, void 
> *unused)
>   seq_printf(m, "\tBusy_frontbuffer_bits: 0x%X\n",
>  crtc->drrs.busy_frontbuffer_bits);
>  
> - seq_printf(m, "DRRS refresh rate: %s\n",
> + seq_printf(m, "\tDRRS refresh rate: %s\n",
>  crtc->drrs.refresh_rate == DRRS_REFRESH_RATE_LOW ?
>  "low" : "high");
>  

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add GuC Error Capture Support (rev2)

[Patchwork]

== Series Details ==

Series: Add GuC Error Capture Support (rev2)
URL   : https://patchwork.freedesktop.org/series/101348/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add GuC Error Capture Support (rev2)

[Patchwork]

== Series Details ==

Series: Add GuC Error Capture Support (rev2)
URL   : https://patchwork.freedesktop.org/series/101348/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
41d2f067e825 drm/i915/guc: Update GuC ADS size for error capture lists
-:40: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#40: 
new file mode 100644

-:324: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#324: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:653:
+   ads_blob_write(guc, ads.capture_class[i][j], 
ads_ggtt + capture_offset);

-:345: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#345: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:674:
+   ads_blob_write(guc, ads.capture_instance[i][j], 
ads_ggtt + capture_offset);

-:469: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'regslist' - possible 
side-effects?
#469: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:63:
+#define MAKE_REGLIST(regslist, regsowner, regstype, class) \
+   { \
+   regslist, \
+   ARRAY_SIZE(regslist), \
+   TO_GCAP_DEF_OWNER(regsowner), \
+   TO_GCAP_DEF_TYPE(regstype), \
+   class, \
+   }

-:513: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional 
statements (16, 16)
#513: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:107:
+   if (reglists[i].owner == owner && reglists[i].type == type &&
[...]
+   return [i];

-:689: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#689: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:283:
+   if (!caplist) {
+   drm_dbg(>drm, "GuC-capture: failed to alloc cached 
caplist");

-:731: WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
#731: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:325:
+   if (!null_header) {
+   drm_dbg(>drm, "GuC-capture: failed to alloc cached 
nulllist");

total: 0 errors, 6 warnings, 1 checks, 749 lines checked
7b2eb12974e1 drm/i915/guc: Add XE_LP static registers for GuC error capture.
-:26: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#26: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:25:
+#define COMMON_GEN12BASE_GLOBAL() \
+   {GEN12_FAULT_TLB_DATA0,0,  0, "GEN12_FAULT_TLB_DATA0"}, \
+   {GEN12_FAULT_TLB_DATA1,0,  0, "GEN12_FAULT_TLB_DATA1"}, \
+   {FORCEWAKE_MT, 0,  0, "FORCEWAKE"}, \
+   {GEN12_AUX_ERR_DBG,0,  0, "AUX_ERR_DBG"}, \
+   {GEN12_GAM_DONE,   0,  0, "GAM_DONE"}, \
+   {GEN12_RING_FAULT_REG, 0,  0, "FAULT_REG"}

-:34: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#34: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c:33:
+#define COMMON_GEN12BASE_ENGINE_INSTANCE() \
+   {RING_PSMI_CTL(0), 0,  0, "RC PSMI"}, \
+   {RING_ESR(0),  0,  0, "ESR"}, \
+   {RING_DMA_FADD(0), 0,  0, "RING_DMA_FADD_LDW"}, \
+   {RING_DMA_FADD_UDW(0), 0,  0, "RING_DMA_FADD_UDW"}, \
+   {RING_IPEIR(0),0,  0, "IPEIR"}, \
+   {RING_IPEHR(0),0,  0, "IPEHR"}, \
+   {RING_INSTPS(0),   0,  0, "INSTPS"}, \
+   {RING_BBADDR(0),   0,  0, "RING_BBADDR_LOW32"}, \
+   {RING_BBADDR_UDW(0),   0,  0, "RING_BBADDR_UP32"}, \
+   {RING_BBSTATE(0),  0,  0, "BB_STATE"}, \
+   {CCID(0),  0,  0, "CCID"}, \
+   {RING_ACTHD(0),0,  0, "ACTHD_LDW"}, \
+   {RING_ACTHD_UDW(0),0,  0, "ACTHD_UDW"}, \
+   {RING_INSTPM(0),   0,  0, "INSTPM"}, \
+   {RING_INSTDONE(0), 0,  0, "INSTDONE"}, \
+   {RING_NOPID(0),0,  0, "RING_NOPID"}, \
+   {RING_START(0),0,  0, "START"}, \
+   {RING_HEAD(0), 0,  0, "HEAD"}, \
+   {RING_TAIL(0), 0,  0, "TAIL"}, \
+   {RING_CTL(0),  0,  0, "CTL"}, \
+   {RING_MI_MODE(0),  0,  0, "MODE"}, \
+   {RING_CONTEXT_CONTROL(0),  0,  0, "RING_CONTEXT_CONTROL"}, \
+   {RING_HWS_PGA(0),  0,  0, "HWS"}, \
+   {RING_MODE_GEN7(0),0,  0, "GFX_MODE"}, \
+   {GEN8_RING_PDP_LDW(0, 0),  0,  0, "PDP0_LDW"}, \
+   {GEN8_RING_PDP_UDW(0, 0),  0,  0, "PDP0_UDW"}, \
+   {GEN8_RING_PDP_LDW(0, 1),  0,  0, "PDP1_LDW"}, \
+   {GEN8_RING_PDP_UDW(0, 1),  0,  0, "PDP1_UDW"}, \
+   {GEN8_RING_PDP_LDW(0, 2),  0,  0, "PDP2_LDW"}, \
+   {GEN8_RING_PDP_UDW(0, 2),  0,  0, "PDP2_UDW"}, \
+   {GEN8_RING_PDP_LDW(0, 3),  0,  0, "PDP3_LDW"}, \
+   {GEN8_RING_PDP_UDW(0, 3),  0,  0, "PDP3_UDW"}

-:71: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in 
parentheses
#71: 

Re: [Intel-gfx] [PATCH 8/9] drm/i915: Deal with bigjoiner vs. DRRS

[Navare, Manasi]

On Tue, Mar 15, 2022 at 03:27:51PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä 
> 
> DRRS operates on transcoder level, so we should only poke at it from
> the master crtc rather than letting every joined pipe give it
> potentially conflicting input.
> 
> Signed-off-by: Ville Syrjälä 

Looks good

Reviewed-by: Manasi Navare 

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_drrs.c | 16 +++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c 
> b/drivers/gpu/drm/i915/display/intel_drrs.c
> index 44c9af8f8b9b..9a341ab1a848 100644
> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> @@ -176,8 +176,16 @@ static void intel_drrs_schedule_work(struct intel_crtc 
> *crtc)
>  static unsigned int intel_drrs_frontbuffer_bits(const struct 
> intel_crtc_state *crtc_state)
>  {
>   struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + unsigned int frontbuffer_bits;
>  
> - return INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe);
> + frontbuffer_bits = INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe);
> +
> + for_each_intel_crtc_in_pipe_mask(>drm, crtc,
> +  crtc_state->bigjoiner_pipes)
> + frontbuffer_bits |= INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe);
> +
> + return frontbuffer_bits;
>  }
>  
>  /**
> @@ -196,6 +204,9 @@ void intel_drrs_enable(const struct intel_crtc_state 
> *crtc_state)
>   if (!crtc_state->hw.active)
>   return;
>  
> + if (intel_crtc_is_bigjoiner_slave(crtc_state))
> + return;
> +
>   mutex_lock(>drrs.mutex);
>  
>   crtc->drrs.cpu_transcoder = crtc_state->cpu_transcoder;
> @@ -223,6 +234,9 @@ void intel_drrs_disable(const struct intel_crtc_state 
> *old_crtc_state)
>   if (!old_crtc_state->hw.active)
>   return;
>  
> + if (intel_crtc_is_bigjoiner_slave(old_crtc_state))
> + return;
> +
>   mutex_lock(>drrs.mutex);
>  
>   if (intel_drrs_is_enabled(crtc))
> -- 
> 2.34.1
> 

[Intel-gfx] [CI 4/7] drm/i915: add i915_gem_object_create_region_at()

[Matthew Auld]

Add a generic interface for allocating an object at some specific
offset, and convert stolen over. Later we will want to hook this up to
different backends.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Reviewed-by: Nirmoy Das 
---
 .../drm/i915/display/intel_plane_initial.c|  4 +-
 drivers/gpu/drm/i915/gem/i915_gem_create.c|  2 +-
 drivers/gpu/drm/i915/gem/i915_gem_region.c| 47 ++--
 drivers/gpu/drm/i915/gem/i915_gem_region.h|  7 ++
 drivers/gpu/drm/i915/gem/i915_gem_shmem.c |  1 +
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 74 ---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.h|  4 -
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c   |  1 +
 drivers/gpu/drm/i915/gem/i915_gem_ttm.h   |  1 +
 drivers/gpu/drm/i915/gt/intel_rc6.c   |  8 +-
 drivers/gpu/drm/i915/intel_memory_region.h|  1 +
 drivers/gpu/drm/i915/selftests/mock_region.c  |  1 +
 12 files changed, 77 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c 
b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index e207d12286b5..5227e5b35206 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -3,6 +3,7 @@
  * Copyright © 2021 Intel Corporation
  */
 
+#include "gem/i915_gem_region.h"
 #include "i915_drv.h"
 #include "intel_atomic_plane.h"
 #include "intel_display.h"
@@ -69,7 +70,8 @@ initial_plane_vma(struct drm_i915_private *i915,
size * 2 > i915->stolen_usable_size)
return NULL;
 
-   obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
+   obj = i915_gem_object_create_region_at(i915->mm.stolen_region,
+  base, size, 0);
if (IS_ERR(obj))
return NULL;
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c 
b/drivers/gpu/drm/i915/gem/i915_gem_create.c
index c6eb023d3d86..5802692ea604 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c
@@ -123,7 +123,7 @@ __i915_gem_object_create_user_ext(struct drm_i915_private 
*i915, u64 size,
 */
flags = I915_BO_ALLOC_USER;
 
-   ret = mr->ops->init_object(mr, obj, size, 0, flags);
+   ret = mr->ops->init_object(mr, obj, I915_BO_INVALID_OFFSET, size, 0, 
flags);
if (ret)
goto object_free;
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c 
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index c9b2e8b91053..3428ddfb2fdb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -27,11 +27,12 @@ void i915_gem_object_release_memory_region(struct 
drm_i915_gem_object *obj)
mutex_unlock(>objects.lock);
 }
 
-struct drm_i915_gem_object *
-i915_gem_object_create_region(struct intel_memory_region *mem,
- resource_size_t size,
- resource_size_t page_size,
- unsigned int flags)
+static struct drm_i915_gem_object *
+__i915_gem_object_create_region(struct intel_memory_region *mem,
+   resource_size_t offset,
+   resource_size_t size,
+   resource_size_t page_size,
+   unsigned int flags)
 {
struct drm_i915_gem_object *obj;
resource_size_t default_page_size;
@@ -86,7 +87,7 @@ i915_gem_object_create_region(struct intel_memory_region *mem,
if (default_page_size < mem->min_page_size)
flags |= I915_BO_ALLOC_PM_EARLY;
 
-   err = mem->ops->init_object(mem, obj, size, page_size, flags);
+   err = mem->ops->init_object(mem, obj, offset, size, page_size, flags);
if (err)
goto err_object_free;
 
@@ -98,6 +99,40 @@ i915_gem_object_create_region(struct intel_memory_region 
*mem,
return ERR_PTR(err);
 }
 
+struct drm_i915_gem_object *
+i915_gem_object_create_region(struct intel_memory_region *mem,
+ resource_size_t size,
+ resource_size_t page_size,
+ unsigned int flags)
+{
+   return __i915_gem_object_create_region(mem, I915_BO_INVALID_OFFSET,
+  size, page_size, flags);
+}
+
+struct drm_i915_gem_object *
+i915_gem_object_create_region_at(struct intel_memory_region *mem,
+resource_size_t offset,
+resource_size_t size,
+unsigned int flags)
+{
+   GEM_BUG_ON(offset == I915_BO_INVALID_OFFSET);
+
+   if (GEM_WARN_ON(!IS_ALIGNED(size, mem->min_page_size)) ||
+   GEM_WARN_ON(!IS_ALIGNED(offset, mem->min_page_size)))
+   return ERR_PTR(-EINVAL);
+
+   if (range_overflows(offset, size, resource_size(>region)))
+   return ERR_PTR(-EINVAL);
+
+

[Intel-gfx] [CI 2/7] drm/i915/stolen: don't treat small BAR as an error

[Matthew Auld]

From: Akeem G Abodunrin 

On client platforms with reduced LMEM BAR, we should be able to continue
with driver load with reduced io_size. Instead of using the BAR size to
determine the how large stolen should be, we should instead use the
ADDR_RANGE register to figure this out(at least on platforms like DG2).
For simplicity we don't attempt to support partially mappable stolen.

v2: rearrange the io_mapping_init_wc slightly, since the stolen setup
might result in reduced io_size.

Signed-off-by: Akeem G Abodunrin 
Co-developed-by: Matthew Auld 
Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Reviewed-by: Nirmoy Das 
---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 62 +++---
 drivers/gpu/drm/i915/i915_reg.h|  3 ++
 2 files changed, 46 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 0bf8f61134af..b860ec954104 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -12,6 +12,8 @@
 
 #include "gem/i915_gem_lmem.h"
 #include "gem/i915_gem_region.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_region_lmem.h"
 #include "i915_drv.h"
 #include "i915_gem_stolen.h"
 #include "i915_reg.h"
@@ -492,7 +494,7 @@ static int i915_gem_init_stolen(struct intel_memory_region 
*mem)
 
/* Exclude the reserved region from driver use */
mem->region.end = reserved_base - 1;
-   mem->io_size = resource_size(>region);
+   mem->io_size = min(mem->io_size, resource_size(>region));
 
/* It is possible for the reserved area to end before the end of stolen
 * memory, so just consider the start. */
@@ -750,11 +752,6 @@ static int init_stolen_lmem(struct intel_memory_region 
*mem)
if (GEM_WARN_ON(resource_size(>region) == 0))
return -ENODEV;
 
-   if (!io_mapping_init_wc(>iomap,
-   mem->io_start,
-   mem->io_size))
-   return -EIO;
-
/*
 * TODO: For stolen lmem we mostly just care about populating the dsm
 * related bits and setting up the drm_mm allocator for the range.
@@ -762,18 +759,26 @@ static int init_stolen_lmem(struct intel_memory_region 
*mem)
 */
err = i915_gem_init_stolen(mem);
if (err)
-   goto err_fini;
+   return err;
+
+   if (mem->io_size && !io_mapping_init_wc(>iomap,
+   mem->io_start,
+   mem->io_size)) {
+   err = -EIO;
+   goto err_cleanup;
+   }
 
return 0;
 
-err_fini:
-   io_mapping_fini(>iomap);
+err_cleanup:
+   i915_gem_cleanup_stolen(mem->i915);
return err;
 }
 
 static int release_stolen_lmem(struct intel_memory_region *mem)
 {
-   io_mapping_fini(>iomap);
+   if (mem->io_size)
+   io_mapping_fini(>iomap);
i915_gem_cleanup_stolen(mem->i915);
return 0;
 }
@@ -790,25 +795,43 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, 
u16 type,
 {
struct intel_uncore *uncore = >uncore;
struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+   resource_size_t dsm_size, dsm_base, lmem_size;
struct intel_memory_region *mem;
+   resource_size_t io_start, io_size;
resource_size_t min_page_size;
-   resource_size_t io_start;
-   resource_size_t lmem_size;
-   u64 lmem_base;
 
-   lmem_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
-   if (GEM_WARN_ON(lmem_base >= pci_resource_len(pdev, 2)))
+   if (WARN_ON_ONCE(instance))
return ERR_PTR(-ENODEV);
 
-   lmem_size = pci_resource_len(pdev, 2) - lmem_base;
-   io_start = pci_resource_start(pdev, 2) + lmem_base;
+   /* Use DSM base address instead for stolen memory */
+   dsm_base = intel_uncore_read64(uncore, GEN12_DSMBASE);
+   if (IS_DG1(uncore->i915)) {
+   lmem_size = pci_resource_len(pdev, 2);
+   if (WARN_ON(lmem_size < dsm_base))
+   return ERR_PTR(-ENODEV);
+   } else {
+   resource_size_t lmem_range;
+
+   lmem_range = intel_gt_read_register(>gt0, 
XEHPSDV_TILE0_ADDR_RANGE) & 0x;
+   lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;
+   lmem_size *= SZ_1G;
+   }
+
+   dsm_size = lmem_size - dsm_base;
+   if (pci_resource_len(pdev, 2) < lmem_size) {
+   io_start = 0;
+   io_size = 0;
+   } else {
+   io_start = pci_resource_start(pdev, 2) + dsm_base;
+   io_size = dsm_size;
+   }
 
min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
I915_GTT_PAGE_SIZE_4K;
 
-   mem = intel_memory_region_create(i915, lmem_base, lmem_size,
+   mem = intel_memory_region_create(i915, 

[Intel-gfx] [CI 5/7] drm/i915/ttm: wire up the object offset

[Matthew Auld]

For the ttm backend we can use existing placements fpfn and lpfn to
force the allocator to place the object at the requested offset,
potentially evicting stuff if the spot is currently occupied.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Reviewed-by: Nirmoy Das 
---
 .../gpu/drm/i915/gem/i915_gem_object_types.h   |  2 ++
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c| 18 ++
 drivers/gpu/drm/i915/i915_ttm_buddy_manager.c  |  3 ++-
 drivers/gpu/drm/i915/intel_region_ttm.c|  7 ++-
 drivers/gpu/drm/i915/intel_region_ttm.h|  1 +
 drivers/gpu/drm/i915/selftests/mock_region.c   |  3 +++
 6 files changed, 28 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h 
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index fd54eb8f4826..2c88bdb8ff7c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -631,6 +631,8 @@ struct drm_i915_gem_object {
 
struct drm_mm_node *stolen;
 
+   resource_size_t bo_offset;
+
unsigned long scratch;
u64 encode;
 
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 5e543ed867a2..e4a06fcf741a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -126,6 +126,8 @@ i915_ttm_select_tt_caching(const struct drm_i915_gem_object 
*obj)
 static void
 i915_ttm_place_from_region(const struct intel_memory_region *mr,
   struct ttm_place *place,
+  resource_size_t offset,
+  resource_size_t size,
   unsigned int flags)
 {
memset(place, 0, sizeof(*place));
@@ -133,7 +135,10 @@ i915_ttm_place_from_region(const struct 
intel_memory_region *mr,
 
if (flags & I915_BO_ALLOC_CONTIGUOUS)
place->flags |= TTM_PL_FLAG_CONTIGUOUS;
-   if (mr->io_size && mr->io_size < mr->total) {
+   if (offset != I915_BO_INVALID_OFFSET) {
+   place->fpfn = offset >> PAGE_SHIFT;
+   place->lpfn = place->fpfn + (size >> PAGE_SHIFT);
+   } else if (mr->io_size && mr->io_size < mr->total) {
if (flags & I915_BO_ALLOC_GPU_ONLY) {
place->flags |= TTM_PL_FLAG_TOPDOWN;
} else {
@@ -155,12 +160,14 @@ i915_ttm_placement_from_obj(const struct 
drm_i915_gem_object *obj,
 
placement->num_placement = 1;
i915_ttm_place_from_region(num_allowed ? obj->mm.placements[0] :
-  obj->mm.region, requested, flags);
+  obj->mm.region, requested, obj->bo_offset,
+  obj->base.size, flags);
 
/* Cache this on object? */
placement->num_busy_placement = num_allowed;
for (i = 0; i < placement->num_busy_placement; ++i)
-   i915_ttm_place_from_region(obj->mm.placements[i], busy + i, 
flags);
+   i915_ttm_place_from_region(obj->mm.placements[i], busy + i,
+  obj->bo_offset, obj->base.size, 
flags);
 
if (num_allowed == 0) {
*busy = *requested;
@@ -802,7 +809,8 @@ static int __i915_ttm_migrate(struct drm_i915_gem_object 
*obj,
struct ttm_placement placement;
int ret;
 
-   i915_ttm_place_from_region(mr, , flags);
+   i915_ttm_place_from_region(mr, , obj->bo_offset,
+  obj->base.size, flags);
placement.num_placement = 1;
placement.num_busy_placement = 1;
placement.placement = 
@@ -1159,6 +1167,8 @@ int __i915_gem_ttm_object_init(struct intel_memory_region 
*mem,
drm_gem_private_object_init(>drm, >base, size);
i915_gem_object_init(obj, _gem_ttm_obj_ops, _class, flags);
 
+   obj->bo_offset = offset;
+
/* Don't put on a region list until we're either locked or fully 
initialized. */
obj->mm.region = mem;
INIT_LIST_HEAD(>mm.region_link);
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c 
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
index 129f668f21ff..8e4e3f72c1ef 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -71,7 +71,8 @@ static int i915_ttm_buddy_man_alloc(struct 
ttm_resource_manager *man,
 
GEM_BUG_ON(min_page_size < mm->chunk_size);
 
-   if (place->flags & TTM_PL_FLAG_CONTIGUOUS) {
+   if (place->fpfn + bman_res->base.num_pages != place->lpfn &&
+   place->flags & TTM_PL_FLAG_CONTIGUOUS) {
unsigned long pages;
 
size = roundup_pow_of_two(size);
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c 
b/drivers/gpu/drm/i915/intel_region_ttm.c
index 737ef3f4ab54..62ff77445b01 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ 

[Intel-gfx] [CI 6/7] drm/i915/display: Check mappable aperture when pinning preallocated vma

[Matthew Auld]

From: CQ Tang 

When system does not have mappable aperture, ggtt->mappable_end=0. In
this case if we pass PIN_MAPPABLE when pinning vma, the pinning code
will return -ENOSPC. So conditionally set PIN_MAPPABLE if HAS_GMCH().

Suggested-by: Chris P Wilson 
Signed-off-by: CQ Tang 
Cc: Radhakrishna Sripada 
Cc: Ap Kamal 
Reviewed-by: Matthew Auld 
Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Ville Syrjälä 
Reviewed-by: Nirmoy Das 
---
 drivers/gpu/drm/i915/display/intel_plane_initial.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c 
b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index 5227e5b35206..f797fcef18fc 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -51,6 +51,7 @@ initial_plane_vma(struct drm_i915_private *i915,
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
u32 base, size;
+   u64 pinctl;
 
if (!mem || plane_config->size == 0)
return NULL;
@@ -101,7 +102,10 @@ initial_plane_vma(struct drm_i915_private *i915,
if (IS_ERR(vma))
goto err_obj;
 
-   if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
+   pinctl = PIN_GLOBAL | PIN_OFFSET_FIXED | base;
+   if (HAS_GMCH(i915))
+   pinctl |= PIN_MAPPABLE;
+   if (i915_vma_pin(vma, 0, 0, pinctl))
goto err_obj;
 
if (i915_gem_object_is_tiled(obj) &&
-- 
2.34.1

[Intel-gfx] [CI 7/7] drm/i915: fixup the initial fb base on DGFX

[Matthew Auld]

On integrated it looks like the GGTT base should always 1:1 maps to
somewhere within DSM. On discrete the base seems to be pre-programmed with
a normal lmem address, and is not 1:1 mapped with the base address. On
such devices probe the lmem address directly from the PTE.

v2(Ville):
  - The base is actually the pre-programmed GGTT address, which is then
meant to 1:1 map to somewhere inside dsm. In the case of dgpu the
base looks to just be some offset within lmem, but this also happens
to be the exact dsm start, on dg1. Therefore we should only need to
fudge the physical address, before allocating from stolen.
  - Bail if it's not located in dsm.
v3:
  - Scratch that. There doesn't seem to be any relationship with the
base and PTE address, on at least DG1. Let's instead just grab the
lmem address from the PTE itself.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Cc: Ville Syrjälä 
Cc: Nirmoy Das 
Reviewed-by: Nirmoy Das 
---
 .../drm/i915/display/intel_plane_initial.c| 50 ---
 1 file changed, 44 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c 
b/drivers/gpu/drm/i915/display/intel_plane_initial.c
index f797fcef18fc..7979929bb632 100644
--- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
+++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
@@ -47,17 +47,55 @@ static struct i915_vma *
 initial_plane_vma(struct drm_i915_private *i915,
  struct intel_initial_plane_config *plane_config)
 {
-   struct intel_memory_region *mem = i915->mm.stolen_region;
+   struct intel_memory_region *mem;
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
+   resource_size_t phys_base;
u32 base, size;
u64 pinctl;
 
-   if (!mem || plane_config->size == 0)
+   if (plane_config->size == 0)
+   return NULL;
+
+   base = round_down(plane_config->base, I915_GTT_MIN_ALIGNMENT);
+   if (IS_DGFX(i915)) {
+   gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm;
+   gen8_pte_t pte;
+
+   gte += base / I915_GTT_PAGE_SIZE;
+
+   pte = ioread64(gte);
+   if (!(pte & GEN12_GGTT_PTE_LM)) {
+   drm_err(>drm,
+   "Initial plane programming missing PTE_LM 
bit\n");
+   return NULL;
+   }
+
+   phys_base = pte & I915_GTT_PAGE_MASK;
+   mem = i915->mm.regions[INTEL_REGION_LMEM];
+
+   /*
+* We don't currently expect this to ever be placed in the
+* stolen portion.
+*/
+   if (phys_base >= resource_size(>region)) {
+   drm_err(>drm,
+   "Initial plane programming using invalid range, 
phys_base=%pa\n",
+   _base);
+   return NULL;
+   }
+
+   drm_dbg(>drm,
+   "Using phys_base=%pa, based on initial plane 
programming\n",
+   _base);
+   } else {
+   phys_base = base;
+   mem = i915->mm.stolen_region;
+   }
+
+   if (!mem)
return NULL;
 
-   base = round_down(plane_config->base,
- I915_GTT_MIN_ALIGNMENT);
size = round_up(plane_config->base + plane_config->size,
mem->min_page_size);
size -= base;
@@ -68,11 +106,11 @@ initial_plane_vma(struct drm_i915_private *i915,
 * features.
 */
if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
+   mem == i915->mm.stolen_region &&
size * 2 > i915->stolen_usable_size)
return NULL;
 
-   obj = i915_gem_object_create_region_at(i915->mm.stolen_region,
-  base, size, 0);
+   obj = i915_gem_object_create_region_at(mem, phys_base, size, 0);
if (IS_ERR(obj))
return NULL;
 
-- 
2.34.1

[Intel-gfx] [CI 3/7] drm/i915/stolen: consider I915_BO_ALLOC_GPU_ONLY

[Matthew Auld]

Keep the behaviour consistent with normal lmem, where we assume CPU
access if by default required.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Reviewed-by: Nirmoy Das 
---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index b860ec954104..17f35892ab7e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -695,6 +695,14 @@ static int _i915_gem_object_stolen_init(struct 
intel_memory_region *mem,
if (size == 0)
return -EINVAL;
 
+   /*
+* With discrete devices, where we lack a mappable aperture there is no
+* possible way to ever access this memory on the CPU side.
+*/
+   if (mem->type == INTEL_MEMORY_STOLEN_LOCAL && !mem->io_size &&
+   !(flags & I915_BO_ALLOC_GPU_ONLY))
+   return -ENOSPC;
+
stolen = kzalloc(sizeof(*stolen), GFP_KERNEL);
if (!stolen)
return -ENOMEM;
-- 
2.34.1

[Intel-gfx] [CI 1/7] drm/i915/lmem: don't treat small BAR as an error

[Matthew Auld]

Just pass along the probed io_size. The backend should be able to
utilize the entire range here, even if some of it is non-mappable.

It does leave open with what to do with stolen local-memory.

Signed-off-by: Matthew Auld 
Cc: Thomas Hellström 
Reviewed-by: Thomas Hellström 
Reviewed-by: Nirmoy Das 
---
 drivers/gpu/drm/i915/gt/intel_region_lmem.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c 
b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
index 6cecfdae07ad..783d81072c3b 100644
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
@@ -93,6 +93,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt 
*gt)
struct intel_memory_region *mem;
resource_size_t min_page_size;
resource_size_t io_start;
+   resource_size_t io_size;
resource_size_t lmem_size;
int err;
 
@@ -124,7 +125,8 @@ static struct intel_memory_region *setup_lmem(struct 
intel_gt *gt)
 
 
io_start = pci_resource_start(pdev, 2);
-   if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2)))
+   io_size = min(pci_resource_len(pdev, 2), lmem_size);
+   if (!io_size)
return ERR_PTR(-ENODEV);
 
min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K :
@@ -134,7 +136,7 @@ static struct intel_memory_region *setup_lmem(struct 
intel_gt *gt)
 lmem_size,
 min_page_size,
 io_start,
-lmem_size,
+io_size,
 INTEL_MEMORY_LOCAL,
 0,
 _region_lmem_ops);
-- 
2.34.1

[Intel-gfx] [RFC PATCH 3/7] drm/i915: use gem objects to track stolen nodes

[Robert Beckett]

Construct gem objects around stolen nodes.
This stops the abuse of interfaces and aids future patches that done use
drm nodes for stolen areas.

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/display/intel_fbc.c   | 72 --
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 60 ++
 drivers/gpu/drm/i915/gem/i915_gem_stolen.h |  7 +++
 3 files changed, 106 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 142280b6ce6d..9df64ecab70e 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -92,8 +92,8 @@ struct intel_fbc {
unsigned int possible_framebuffer_bits;
unsigned int busy_bits;
 
-   struct drm_mm_node compressed_fb;
-   struct drm_mm_node compressed_llb;
+   struct drm_i915_gem_object *compressed_fb;
+   struct drm_i915_gem_object *compressed_llb;
 
enum intel_fbc_id id;
 
@@ -331,16 +331,18 @@ static void i8xx_fbc_nuke(struct intel_fbc *fbc)
 static void i8xx_fbc_program_cfb(struct intel_fbc *fbc)
 {
struct drm_i915_private *i915 = fbc->i915;
+   u64 fb_offset = i915_gem_object_stolen_offset(fbc->compressed_fb);
+   u64 llb_offset = i915_gem_object_stolen_offset(fbc->compressed_llb);
 
GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start,
-fbc->compressed_fb.start, U32_MAX));
+fb_offset, U32_MAX));
GEM_BUG_ON(range_overflows_end_t(u64, i915->dsm.start,
-fbc->compressed_llb.start, U32_MAX));
+llb_offset, U32_MAX));
 
intel_de_write(i915, FBC_CFB_BASE,
-  i915->dsm.start + fbc->compressed_fb.start);
+  i915->dsm.start + fb_offset);
intel_de_write(i915, FBC_LL_BASE,
-  i915->dsm.start + fbc->compressed_llb.start);
+  i915->dsm.start + llb_offset);
 }
 
 static const struct intel_fbc_funcs i8xx_fbc_funcs = {
@@ -449,7 +451,8 @@ static void g4x_fbc_program_cfb(struct intel_fbc *fbc)
 {
struct drm_i915_private *i915 = fbc->i915;
 
-   intel_de_write(i915, DPFC_CB_BASE, fbc->compressed_fb.start);
+   intel_de_write(i915, DPFC_CB_BASE,
+  i915_gem_object_stolen_offset(fbc->compressed_fb));
 }
 
 static const struct intel_fbc_funcs g4x_fbc_funcs = {
@@ -500,7 +503,8 @@ static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
 {
struct drm_i915_private *i915 = fbc->i915;
 
-   intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id), 
fbc->compressed_fb.start);
+   intel_de_write(i915, ILK_DPFC_CB_BASE(fbc->id),
+   i915_gem_object_stolen_offset(fbc->compressed_fb));
 }
 
 static const struct intel_fbc_funcs ilk_fbc_funcs = {
@@ -740,21 +744,24 @@ static int find_compression_limit(struct intel_fbc *fbc,
 {
struct drm_i915_private *i915 = fbc->i915;
u64 end = intel_fbc_stolen_end(i915);
-   int ret, limit = min_limit;
+   int limit = min_limit;
+   struct drm_i915_gem_object *obj;
 
size /= limit;
 
/* Try to over-allocate to reduce reallocations and fragmentation. */
-   ret = i915_gem_stolen_insert_node_in_range(i915, >compressed_fb,
-  size <<= 1, 4096, 0, end);
-   if (ret == 0)
+   obj = i915_gem_object_create_stolen_in_range(i915, size <<= 1, 4096, 0, 
end);
+   if (!IS_ERR(obj)) {
+   fbc->compressed_fb = obj;
return limit;
+   }
 
for (; limit <= intel_fbc_max_limit(i915); limit <<= 1) {
-   ret = i915_gem_stolen_insert_node_in_range(i915, 
>compressed_fb,
-  size >>= 1, 4096, 0, 
end);
-   if (ret == 0)
+   obj = i915_gem_object_create_stolen_in_range(i915, size >>= 1, 
4096, 0, end);
+   if (!IS_ERR(obj)) {
+   fbc->compressed_fb = obj;
return limit;
+   }
}
 
return 0;
@@ -765,17 +772,19 @@ static int intel_fbc_alloc_cfb(struct intel_fbc *fbc,
 {
struct drm_i915_private *i915 = fbc->i915;
int ret;
+   struct drm_i915_gem_object *obj;
 
-   drm_WARN_ON(>drm,
-   drm_mm_node_allocated(>compressed_fb));
-   drm_WARN_ON(>drm,
-   drm_mm_node_allocated(>compressed_llb));
+   drm_WARN_ON(>drm, fbc->compressed_fb);
+   drm_WARN_ON(>drm, fbc->compressed_llb);
 
if (DISPLAY_VER(i915) < 5 && !IS_G4X(i915)) {
-   ret = i915_gem_stolen_insert_node(i915, >compressed_llb,
- 4096, 4096);
-   if (ret)
+   obj = i915_gem_object_create_stolen_in_range(i915, 4096, 4096,
+

[Intel-gfx] [RFC PATCH 5/7] drm/ttm: add range busy check for range manager

[Robert Beckett]

RFC: do we want this to become a generic interface in
ttm_resource_manager_func?

RFC: would we prefer a different interface? e.g.
for_each_resource_in_range or for_each_bo_in_range

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/ttm/ttm_range_manager.c | 21 +
 include/drm/ttm/ttm_range_manager.h |  3 +++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/ttm/ttm_range_manager.c 
b/drivers/gpu/drm/ttm/ttm_range_manager.c
index 8cd4f3fb9f79..5662627bb933 100644
--- a/drivers/gpu/drm/ttm/ttm_range_manager.c
+++ b/drivers/gpu/drm/ttm/ttm_range_manager.c
@@ -206,3 +206,24 @@ int ttm_range_man_fini_nocheck(struct ttm_device *bdev,
return 0;
 }
 EXPORT_SYMBOL(ttm_range_man_fini_nocheck);
+
+/**
+ * ttm_range_man_range_busy - Check whether anything is allocated with a range
+ *
+ * @man: memory manager to check
+ * @fpfn: first page number to check
+ * @lpfn: last page number to check
+ *
+ * Return: true if anything allocated within the range, false otherwise.
+ */
+bool ttm_range_man_range_busy(struct ttm_resource_manager *man,
+ unsigned fpfn, unsigned lpfn)
+{
+   struct ttm_range_manager *rman = to_range_manager(man);
+   struct drm_mm *mm = >mm;
+
+   if (__drm_mm_interval_first(mm, PFN_PHYS(fpfn), PFN_PHYS(lpfn + 1) - 1))
+   return true;
+   return false;
+}
+EXPORT_SYMBOL(ttm_range_man_range_busy);
diff --git a/include/drm/ttm/ttm_range_manager.h 
b/include/drm/ttm/ttm_range_manager.h
index 7963b957e9ef..86794a3f9101 100644
--- a/include/drm/ttm/ttm_range_manager.h
+++ b/include/drm/ttm/ttm_range_manager.h
@@ -53,4 +53,7 @@ static __always_inline int ttm_range_man_fini(struct 
ttm_device *bdev,
BUILD_BUG_ON(__builtin_constant_p(type) && type >= TTM_NUM_MEM_TYPES);
return ttm_range_man_fini_nocheck(bdev, type);
 }
+
+bool ttm_range_man_range_busy(struct ttm_resource_manager *man,
+ unsigned fpfn, unsigned lpfn);
 #endif
-- 
2.25.1

[Intel-gfx] [RFC PATCH 6/7] drm/i915: add range busy check for ttm region

[Robert Beckett]

RFC: should this become a generic interface in intel_memory_region_ops?

RFC: would we prefer an different interface? e.g. for_each_obj_in_range

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/intel_region_ttm.c | 19 +++
 drivers/gpu/drm/i915/intel_region_ttm.h |  3 +++
 2 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c 
b/drivers/gpu/drm/i915/intel_region_ttm.c
index bb564b830c96..2ccefa76348f 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -256,3 +256,22 @@ void intel_region_ttm_resource_free(struct 
intel_memory_region *mem,
 
man->func->free(man, res);
 }
+
+/**
+ * intel_region_ttm_range_busy - check whether range has any allocations
+ * @mem: The region to check
+ * @start: the start of the range to check
+ * @end: the end of the range to check
+ *
+ * Return: true if something is alloceted within the region, false otherwise.
+ */
+bool intel_region_ttm_range_busy(struct intel_memory_region *mem,
+u64 start, u64 end)
+{
+   struct ttm_resource_manager *man = mem->region_private;
+
+   /* currently only supported for range allocator */
+   GEM_BUG_ON(!mem->is_range_manager);
+
+   return ttm_range_man_range_busy(man, PFN_DOWN(start), PFN_UP(end));
+}
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.h 
b/drivers/gpu/drm/i915/intel_region_ttm.h
index fdee5e7bd46c..670ba9b618f7 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.h
+++ b/drivers/gpu/drm/i915/intel_region_ttm.h
@@ -29,6 +29,9 @@ intel_region_ttm_resource_to_rsgt(struct intel_memory_region 
*mem,
 void intel_region_ttm_resource_free(struct intel_memory_region *mem,
struct ttm_resource *res);
 
+bool intel_region_ttm_range_busy(struct intel_memory_region *mem,
+u64 start, u64 end);
+
 int intel_region_to_ttm_type(const struct intel_memory_region *mem);
 
 struct ttm_device_funcs *i915_ttm_driver(void);
-- 
2.25.1

[Intel-gfx] [RFC PATCH 4/7] drm/i915: stolen memory use ttm backend

[Robert Beckett]

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 385 ++---
 drivers/gpu/drm/i915/gem/i915_gem_stolen.h |   9 -
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c|  14 +-
 drivers/gpu/drm/i915/gem/i915_gem_ttm.h|   7 +
 4 files changed, 40 insertions(+), 375 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 265133cb2a47..e58f9902ef47 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -4,19 +4,22 @@
  * Copyright © 2008-2012 Intel Corporation
  */
 
+#include "drm/ttm/ttm_placement.h"
+#include "gem/i915_gem_object_types.h"
 #include 
 #include 
 
-#include 
 #include 
 
 #include "gem/i915_gem_lmem.h"
 #include "gem/i915_gem_region.h"
+#include "gem/i915_gem_ttm.h"
 #include "i915_drv.h"
 #include "i915_gem_stolen.h"
 #include "i915_reg.h"
 #include "i915_vgpu.h"
 #include "intel_mchbar_regs.h"
+#include "intel_region_ttm.h"
 
 /*
  * The BIOS typically reserves some of the system's memory for the exclusive
@@ -30,46 +33,6 @@
  * for is a boon.
  */
 
-int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *i915,
-struct drm_mm_node *node, u64 size,
-unsigned alignment, u64 start, u64 end)
-{
-   int ret;
-
-   if (!drm_mm_initialized(>mm.stolen))
-   return -ENODEV;
-
-   /* WaSkipStolenMemoryFirstPage:bdw+ */
-   if (GRAPHICS_VER(i915) >= 8 && start < 4096)
-   start = 4096;
-
-   mutex_lock(>mm.stolen_lock);
-   ret = drm_mm_insert_node_in_range(>mm.stolen, node,
- size, alignment, 0,
- start, end, DRM_MM_INSERT_BEST);
-   mutex_unlock(>mm.stolen_lock);
-
-   return ret;
-}
-
-int i915_gem_stolen_insert_node(struct drm_i915_private *i915,
-   struct drm_mm_node *node, u64 size,
-   unsigned alignment)
-{
-   return i915_gem_stolen_insert_node_in_range(i915, node,
-   size, alignment,
-   I915_GEM_STOLEN_BIAS,
-   U64_MAX);
-}
-
-void i915_gem_stolen_remove_node(struct drm_i915_private *i915,
-struct drm_mm_node *node)
-{
-   mutex_lock(>mm.stolen_lock);
-   drm_mm_remove_node(node);
-   mutex_unlock(>mm.stolen_lock);
-}
-
 static int i915_adjust_stolen(struct drm_i915_private *i915,
  struct resource *dsm)
 {
@@ -170,14 +133,6 @@ static int i915_adjust_stolen(struct drm_i915_private 
*i915,
return 0;
 }
 
-static void i915_gem_cleanup_stolen(struct drm_i915_private *i915)
-{
-   if (!drm_mm_initialized(>mm.stolen))
-   return;
-
-   drm_mm_takedown(>mm.stolen);
-}
-
 static void g4x_get_stolen_reserved(struct drm_i915_private *i915,
struct intel_uncore *uncore,
resource_size_t *base,
@@ -510,216 +465,15 @@ static int i915_gem_init_stolen(struct 
intel_memory_region *mem)
return 0;
 
/* Basic memrange allocator for stolen space. */
-   drm_mm_init(>mm.stolen, 0, i915->stolen_usable_size);
-
-   return 0;
-}
-
-static void dbg_poison(struct i915_ggtt *ggtt,
-  dma_addr_t addr, resource_size_t size,
-  u8 x)
-{
-#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
-   if (!drm_mm_node_allocated(>error_capture))
-   return;
-
-   if (ggtt->vm.bind_async_flags & I915_VMA_GLOBAL_BIND)
-   return; /* beware stop_machine() inversion */
-
-   GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE));
-
-   mutex_lock(>error_mutex);
-   while (size) {
-   void __iomem *s;
-
-   ggtt->vm.insert_page(>vm, addr,
-ggtt->error_capture.start,
-I915_CACHE_NONE, 0);
-   mb();
-
-   s = io_mapping_map_wc(>iomap,
- ggtt->error_capture.start,
- PAGE_SIZE);
-   memset_io(s, x, PAGE_SIZE);
-   io_mapping_unmap(s);
-
-   addr += PAGE_SIZE;
-   size -= PAGE_SIZE;
-   }
-   mb();
-   ggtt->vm.clear_range(>vm, ggtt->error_capture.start, PAGE_SIZE);
-   mutex_unlock(>error_mutex);
-#endif
-}
-
-static struct sg_table *
-i915_pages_create_for_stolen(struct drm_device *dev,
-resource_size_t offset, resource_size_t size)
-{
-   struct drm_i915_private *i915 = to_i915(dev);
-   struct sg_table *st;
-   struct scatterlist *sg;
-
-   GEM_BUG_ON(range_overflows(offset, size, 

[Intel-gfx] [RFC PATCH 7/7] drm/i915: cleanup old stolen state

[Robert Beckett]

remove i915->mm.stolen
remove i915->mm.stolen_lock

they are no longer needed.

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/display/intel_fbc.c   |  4 ++--
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c |  2 --
 drivers/gpu/drm/i915/gt/selftest_reset.c   | 16 +---
 drivers/gpu/drm/i915/i915_drv.h|  5 -
 4 files changed, 11 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c 
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 9df64ecab70e..644bb599eee6 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -805,7 +805,7 @@ static int intel_fbc_alloc_cfb(struct intel_fbc *fbc,
 err_llb:
i915_gem_object_put(fetch_and_zero(>compressed_llb));
 err:
-   if (drm_mm_initialized(>mm.stolen))
+   if (IS_ERR(obj) && (PTR_ERR(obj) == -ENOMEM || PTR_ERR(obj) == -ENXIO))
drm_info_once(>drm, "not enough stolen space for 
compressed buffer (need %d more bytes), disabling. Hint: you may be able to 
increase stolen memory size in the BIOS to avoid this.\n", size);
return -ENOSPC;
 }
@@ -1708,7 +1708,7 @@ void intel_fbc_init(struct drm_i915_private *i915)
 {
enum intel_fbc_id fbc_id;
 
-   if (!drm_mm_initialized(>mm.stolen))
+   if (!i915->mm.stolen_region)
mkwrite_device_info(i915)->display.fbc_mask = 0;
 
if (need_fbc_vtd_wa(i915))
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c 
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index e58f9902ef47..930521a84607 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -347,8 +347,6 @@ static int i915_gem_init_stolen(struct intel_memory_region 
*mem)
resource_size_t reserved_base, stolen_top;
resource_size_t reserved_total, reserved_size;
 
-   mutex_init(>mm.stolen_lock);
-
if (intel_vgpu_active(i915)) {
drm_notice(>drm,
   "%s, disabling use of stolen memory\n",
diff --git a/drivers/gpu/drm/i915/gt/selftest_reset.c 
b/drivers/gpu/drm/i915/gt/selftest_reset.c
index 37c38bdd5f47..ad2ecc582be2 100644
--- a/drivers/gpu/drm/i915/gt/selftest_reset.c
+++ b/drivers/gpu/drm/i915/gt/selftest_reset.c
@@ -6,6 +6,7 @@
 #include 
 
 #include "gem/i915_gem_stolen.h"
+#include "intel_region_ttm.h"
 
 #include "i915_memcpy.h"
 #include "i915_selftest.h"
@@ -83,6 +84,7 @@ __igt_reset_stolen(struct intel_gt *gt,
dma_addr_t dma = (dma_addr_t)dsm->start + (page << PAGE_SHIFT);
void __iomem *s;
void *in;
+   bool busy;
 
ggtt->vm.insert_page(>vm, dma,
 ggtt->error_capture.start,
@@ -93,9 +95,9 @@ __igt_reset_stolen(struct intel_gt *gt,
  ggtt->error_capture.start,
  PAGE_SIZE);
 
-   if (!__drm_mm_interval_first(>i915->mm.stolen,
-page << PAGE_SHIFT,
-((page + 1) << PAGE_SHIFT) - 1))
+   busy = intel_region_ttm_range_busy(gt->i915->mm.stolen_region,
+  PFN_PHYS(page), 
PFN_PHYS(page + 1) - 1);
+   if (!busy)
memset_io(s, STACK_MAGIC, PAGE_SIZE);
 
in = (void __force *)s;
@@ -124,6 +126,7 @@ __igt_reset_stolen(struct intel_gt *gt,
void __iomem *s;
void *in;
u32 x;
+   bool busy;
 
ggtt->vm.insert_page(>vm, dma,
 ggtt->error_capture.start,
@@ -139,10 +142,9 @@ __igt_reset_stolen(struct intel_gt *gt,
in = tmp;
x = crc32_le(0, in, PAGE_SIZE);
 
-   if (x != crc[page] &&
-   !__drm_mm_interval_first(>i915->mm.stolen,
-page << PAGE_SHIFT,
-((page + 1) << PAGE_SHIFT) - 1)) {
+   busy = intel_region_ttm_range_busy(gt->i915->mm.stolen_region,
+  PFN_PHYS(page), 
PFN_PHYS(page + 1) - 1);
+   if (x != crc[page] && !busy) {
pr_debug("unused stolen page %pa modified by GPU 
reset\n",
 );
if (count++ == 0)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 7d622d1afe93..1f9fa2d6d198 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -247,11 +247,6 @@ struct i915_gem_mm {
 * support stolen.
 */
struct intel_memory_region *stolen_region;
-   /** Memory allocator for GTT stolen memory */
-   struct drm_mm stolen;
-   /** Protects the usage of the GTT stolen memory allocator. This is
-

[Intel-gfx] [RFC PATCH 2/7] drm/i915: add ability to create memory region object in place

[Robert Beckett]

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/gem/i915_gem_region.c | 55 ++
 drivers/gpu/drm/i915/gem/i915_gem_region.h |  6 ++
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c| 84 ++
 drivers/gpu/drm/i915/intel_memory_region.h |  6 ++
 4 files changed, 136 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c 
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index c9b2e8b91053..e25ad0b9b636 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -98,6 +98,61 @@ i915_gem_object_create_region(struct intel_memory_region 
*mem,
return ERR_PTR(err);
 }
 
+struct drm_i915_gem_object *
+i915_gem_object_create_region_in_place(struct intel_memory_region *mem,
+  resource_size_t size,
+  resource_size_t page_size,
+  unsigned int flags,
+  u64 start, u64 end)
+{
+   struct drm_i915_gem_object *obj;
+   resource_size_t default_page_size;
+   int err;
+
+   /*
+* NB: Our use of resource_size_t for the size stems from using struct
+* resource for the mem->region. We might need to revisit this in the
+* future.
+*/
+
+   GEM_BUG_ON(flags & ~I915_BO_ALLOC_FLAGS);
+
+   if (!mem)
+   return ERR_PTR(-ENODEV);
+   if (!mem->ops->init_object_in_place)
+   return ERR_PTR(-EINVAL);
+
+   default_page_size = mem->min_page_size;
+   if (page_size)
+   default_page_size = page_size;
+
+   GEM_BUG_ON(!is_power_of_2_u64(default_page_size));
+   GEM_BUG_ON(default_page_size < PAGE_SIZE);
+
+   size = round_up(size, default_page_size);
+
+   GEM_BUG_ON(!size);
+   GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_MIN_ALIGNMENT));
+
+   if (i915_gem_object_size_2big(size))
+   return ERR_PTR(-E2BIG);
+
+   obj = i915_gem_object_alloc();
+   if (!obj)
+   return ERR_PTR(-ENOMEM);
+
+   err = mem->ops->init_object_in_place(mem, obj, size, page_size, flags, 
start, end);
+   if (err)
+   goto err_object_free;
+
+   trace_i915_gem_object_create(obj);
+   return obj;
+
+err_object_free:
+   i915_gem_object_free(obj);
+   return ERR_PTR(err);
+}
+
 /**
  * i915_gem_process_region - Iterate over all objects of a region using ops
  * to process and optionally skip objects
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.h 
b/drivers/gpu/drm/i915/gem/i915_gem_region.h
index fcaa12d657d4..0cad90ac4a92 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.h
@@ -56,6 +56,12 @@ i915_gem_object_create_region(struct intel_memory_region 
*mem,
  resource_size_t size,
  resource_size_t page_size,
  unsigned int flags);
+struct drm_i915_gem_object *
+i915_gem_object_create_region_in_place(struct intel_memory_region *mem,
+  resource_size_t size,
+  resource_size_t page_size,
+  unsigned int flags,
+  u64 start, u64 end);
 
 int i915_gem_process_region(struct intel_memory_region *mr,
struct i915_gem_apply_to_region *apply);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c 
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 45cc5837ce00..35d1bde19267 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -1131,20 +1131,12 @@ void i915_ttm_bo_destroy(struct ttm_buffer_object *bo)
}
 }
 
-/**
- * __i915_gem_ttm_object_init - Initialize a ttm-backed i915 gem object
- * @mem: The initial memory region for the object.
- * @obj: The gem object.
- * @size: Object size in bytes.
- * @flags: gem object flags.
- *
- * Return: 0 on success, negative error code on failure.
- */
-int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
-  struct drm_i915_gem_object *obj,
-  resource_size_t size,
-  resource_size_t page_size,
-  unsigned int flags)
+static int __i915_gem_ttm_object_init_with_placement(struct 
intel_memory_region *mem,
+struct drm_i915_gem_object 
*obj,
+resource_size_t size,
+resource_size_t page_size,
+unsigned int flags,
+struct ttm_placement 
*placement)
 {
static struct lock_class_key lock_class;
struct drm_i915_private *i915 = mem->i915;
@@ -1188,7 

[Intel-gfx] [RFC PATCH 1/7] drm/i915: instantiate ttm ranger manager for stolen memory

[Robert Beckett]

Signed-off-by: Robert Beckett 
---
 drivers/gpu/drm/i915/intel_region_ttm.c | 29 +++--
 1 file changed, 22 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c 
b/drivers/gpu/drm/i915/intel_region_ttm.c
index 737ef3f4ab54..bb564b830c96 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -57,11 +57,17 @@ int intel_region_to_ttm_type(const struct 
intel_memory_region *mem)
 
GEM_BUG_ON(mem->type != INTEL_MEMORY_LOCAL &&
   mem->type != INTEL_MEMORY_MOCK &&
-  mem->type != INTEL_MEMORY_SYSTEM);
+  mem->type != INTEL_MEMORY_SYSTEM &&
+  mem->type != INTEL_MEMORY_STOLEN_SYSTEM &&
+  mem->type != INTEL_MEMORY_STOLEN_LOCAL);
 
if (mem->type == INTEL_MEMORY_SYSTEM)
return TTM_PL_SYSTEM;
 
+   if (mem->type == INTEL_MEMORY_STOLEN_SYSTEM ||
+   mem->type == INTEL_MEMORY_STOLEN_LOCAL)
+   return TTM_PL_VRAM;
+
type = mem->instance + TTM_PL_PRIV;
GEM_BUG_ON(type >= TTM_NUM_MEM_TYPES);
 
@@ -85,10 +91,16 @@ int intel_region_ttm_init(struct intel_memory_region *mem)
int mem_type = intel_region_to_ttm_type(mem);
int ret;
 
-   ret = i915_ttm_buddy_man_init(bdev, mem_type, false,
- resource_size(>region),
- mem->io_size,
- mem->min_page_size, PAGE_SIZE);
+   if (mem_type == TTM_PL_VRAM) {
+   ret = ttm_range_man_init(bdev, mem_type, false,
+resource_size(>region) >> 
PAGE_SHIFT);
+   mem->is_range_manager = true;
+   } else {
+   ret = i915_ttm_buddy_man_init(bdev, mem_type, false,
+ resource_size(>region),
+ mem->io_size,
+ mem->min_page_size, PAGE_SIZE);
+   }
if (ret)
return ret;
 
@@ -108,6 +120,7 @@ int intel_region_ttm_init(struct intel_memory_region *mem)
 int intel_region_ttm_fini(struct intel_memory_region *mem)
 {
struct ttm_resource_manager *man = mem->region_private;
+   int mem_type = intel_region_to_ttm_type(mem);
int ret = -EBUSY;
int count;
 
@@ -138,8 +151,10 @@ int intel_region_ttm_fini(struct intel_memory_region *mem)
if (ret || !man)
return ret;
 
-   ret = i915_ttm_buddy_man_fini(>i915->bdev,
- intel_region_to_ttm_type(mem));
+   if (mem_type == TTM_PL_VRAM)
+   ret = ttm_range_man_fini(>i915->bdev, mem_type);
+   else
+   ret = i915_ttm_buddy_man_fini(>i915->bdev, mem_type);
GEM_WARN_ON(ret);
mem->region_private = NULL;
 
-- 
2.25.1

[Intel-gfx] [RFC PATCH 0/7] drm/i915: ttm for stolen

[Robert Beckett]

Refactor stolen gem backend to use ttm.

While this series is finished off to handle CI issues, I would
appreciate a design review.
In particulare any opinions on the following would be appreciated:

1. display fbc code using gem objects instead of drm_mm_node. The intent
is rely on memory region as interface, instead of relying on knowledge
of internals. This way ttm can be used in place of original stolen
region without issue.

2. checking if a region has anything alloceted within a range. Instead
of relying on internal access to the stolen region's drm_mm, add an
interface to check if the range is busy that can work with any backend
if implemetned.

3. Instead of region busy checking which is currently only used in
testing, would we prefer a more general interface that could potentially
be used for other infrastructure? e.g. for_each with callback over
each resource/buffer within the range.

Robert Beckett (7):
  drm/i915: instantiate ttm ranger manager for stolen memory
  drm/i915: add ability to create memory region object in place
  drm/i915: use gem objects to track stolen nodes
  drm/i915: stolen memory use ttm backend
  drm/ttm: add range busy check for range manager
  drm/i915: add range busy check for ttm region
  drm/i915: cleanup old stolen state

 drivers/gpu/drm/i915/display/intel_fbc.c   |  76 +++--
 drivers/gpu/drm/i915/gem/i915_gem_region.c |  55 
 drivers/gpu/drm/i915/gem/i915_gem_region.h |   6 +
 drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 351 +++--
 drivers/gpu/drm/i915/gem/i915_gem_stolen.h |  16 +-
 drivers/gpu/drm/i915/gem/i915_gem_ttm.c|  84 -
 drivers/gpu/drm/i915/gem/i915_gem_ttm.h|   7 +
 drivers/gpu/drm/i915/gt/selftest_reset.c   |  16 +-
 drivers/gpu/drm/i915/i915_drv.h|   5 -
 drivers/gpu/drm/i915/intel_memory_region.h |   6 +
 drivers/gpu/drm/i915/intel_region_ttm.c|  48 ++-
 drivers/gpu/drm/i915/intel_region_ttm.h|   3 +
 drivers/gpu/drm/ttm/ttm_range_manager.c|  21 ++
 include/drm/ttm/ttm_range_manager.h|   3 +
 14 files changed, 306 insertions(+), 391 deletions(-)

-- 
2.25.1

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/fbc: FBC frontbuffer stuff

[Patchwork]

== Series Details ==

Series: drm/i915/fbc: FBC frontbuffer stuff
URL   : https://patchwork.freedesktop.org/series/101391/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11363_full -> Patchwork_22572_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_22572_full:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_suspend@basic-s3-devices@smem:
- {shard-dg1}:NOTRUN -> [DMESG-WARN][1]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22572/shard-dg1-13/igt@gem_exec_suspend@basic-s3-devi...@smem.html

  * 
{igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-c-hdmi-a-3-downscale-with-pixel-format}:
- {shard-dg1}:NOTRUN -> [SKIP][2] +11 similar issues
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22572/shard-dg1-18/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0...@pipe-c-hdmi-a-3-downscale-with-pixel-format.html

  
Known issues


  Here are the changes found in Patchwork_22572_full that come from known 
issues:

### CI changes ###

 Issues hit 

  * boot:
- shard-glk:  ([PASS][3], [PASS][4], [PASS][5], [PASS][6], 
[PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], 
[PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], 
[PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], 
[PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], 
[PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], 
[FAIL][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
[PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], 
[PASS][49], [PASS][50], [PASS][51]) ([i915#4392])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk1/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk1/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk2/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk2/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk2/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk3/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk3/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk3/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk4/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk4/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk5/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk5/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk5/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk6/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk6/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk6/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk7/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk7/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk7/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk8/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk8/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk8/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk9/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk9/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-glk9/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22572/shard-glk5/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22572/shard-glk5/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22572/shard-glk9/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22572/shard-glk1/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22572/shard-glk9/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22572/shard-glk9/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22572/shard-glk1/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22572/shard-glk1/boot.html
   [36]: 

Re: [Intel-gfx] [v7 1/5] drm/edid: seek for available CEA and DisplayID block from specific EDID block index

[Drew Davenport]

On Tue, Mar 15, 2022 at 03:21:05PM +, Lee, Shawn C wrote:
> On Tuesday, March 15, 2022 8:33 PM, Nikula, Jani  
> wrote:
> >On Mon, 14 Mar 2022, Drew Davenport  wrote:
> >> On Mon, Mar 14, 2022 at 10:40:47AM +0200, Jani Nikula wrote:
> >>> On Sun, 13 Mar 2022, Lee Shawn C  wrote:
> >>> > drm_find_cea_extension() always look for a top level CEA block. 
> >>> > Pass ext_index from caller then this function to search next 
> >>> > available CEA ext block from a specific EDID block pointer.
> >>> >
> >>> > v2: save proper extension block index if CTA data information
> >>> > was found in DispalyID block.
> >>> > v3: using different parameters to store CEA and DisplayID block index.
> >>> > configure DisplayID extansion block index before search available
> >>> > DisplayID block.
> >>> >
> >>> > Cc: Jani Nikula 
> >>> > Cc: Ville Syrjala 
> >>> > Cc: Ankit Nautiyal 
> >>> > Cc: Drew Davenport 
> >>> > Cc: intel-gfx 
> >>> > Signed-off-by: Lee Shawn C 
> >>> > ---
> >>> >  drivers/gpu/drm/drm_displayid.c | 10 +--
> >>> >  drivers/gpu/drm/drm_edid.c  | 53 ++---
> >>> >  include/drm/drm_displayid.h |  4 +--
> >>> >  3 files changed, 39 insertions(+), 28 deletions(-)
> >>> >
> >>> > diff --git a/drivers/gpu/drm/drm_displayid.c 
> >>> > b/drivers/gpu/drm/drm_displayid.c index 32da557b960f..31c3e6d7d549 
> >>> > 100644
> >>> > --- a/drivers/gpu/drm/drm_displayid.c
> >>> > +++ b/drivers/gpu/drm/drm_displayid.c
> >>> > @@ -59,11 +59,14 @@ static const u8 
> >>> > *drm_find_displayid_extension(const struct edid *edid,  }
> >>> >  
> >>> >  void displayid_iter_edid_begin(const struct edid *edid,
> >>> > -  struct displayid_iter *iter)
> >>> > +  struct displayid_iter *iter, int 
> >>> > *ext_index)
> >>> 
> >>> Please don't do this. This just ruins the clean approach displayid 
> >>> iterator added.
> >>> 
> >>> Instead of making the displayid iterator ugly, and leaking its 
> >>> abstractions, I'll repeat what I said should be done in reply to the 
> >>> very first version of this patch series [1]:
> >>> 
> >>> "I think we're going to need abstracted EDID iteration similar to 
> >>> what I've done for DisplayID iteration. We can't have all places 
> >>> reimplementing the iteration like we have now."
> >>> 
> >>> This isn't a problem that should be solved by having all the callers 
> >>> hold a bunch of local variables and pass them around to all the 
> >>> functions. Nobody's going to be able to keep track of this anymore. 
> >>> And this series, as it is, makes it harder to fix this properly later on.
> >>
> >> I missed your original review comment, so apologies for repeating what 
> >> you said there already.
> >>
> >> I'd agree that passing a starting index to the displayid_iter_* 
> >> functions is probably not the right direction here. More thoughts below.
> >>
> >>> 
> >>> 
> >>> BR,
> >>> Jani.
> >>> 
> >>> 
> >>> [1] https://lore.kernel.org/r/87czjf8dik@intel.com
> >>> 
> >>> 
> >>> 
> >>> >  {
> >>> > memset(iter, 0, sizeof(*iter));
> >>> >  
> >>> > iter->edid = edid;
> >>> > +
> >>> > +   if (ext_index)
> >>> > +   iter->ext_index = *ext_index;
> >>> >  }
> >>> >  
> >>> >  static const struct displayid_block * @@ -126,7 +129,10 @@ 
> >>> > __displayid_iter_next(struct displayid_iter *iter)
> >>> > }
> >>> >  }
> >>> >  
> >>> > -void displayid_iter_end(struct displayid_iter *iter)
> >>> > +void displayid_iter_end(struct displayid_iter *iter, int 
> >>> > +*ext_index)
> >>> >  {
> >>> > +   if (ext_index)
> >>> > +   *ext_index = iter->ext_index;
> >>> > +
> >>> > memset(iter, 0, sizeof(*iter));
> >>> >  }
> >>> > diff --git a/drivers/gpu/drm/drm_edid.c 
> >>> > b/drivers/gpu/drm/drm_edid.c index 561f53831e29..78c415aa6889 
> >>> > 100644
> >>> > --- a/drivers/gpu/drm/drm_edid.c
> >>> > +++ b/drivers/gpu/drm/drm_edid.c
> >>> > @@ -3353,28 +3353,27 @@ const u8 *drm_find_edid_extension(const struct 
> >>> > edid *edid,
> >>> > return edid_ext;
> >>> >  }
> >>> >  
> >>> > -static const u8 *drm_find_cea_extension(const struct edid *edid)
> >>> > +static const u8 *drm_find_cea_extension(const struct edid *edid,
> >>> > +   int *cea_ext_index, int 
> >>> > *displayid_ext_index)
> >>
> >> As discussed above, passing both indices into this function may not be 
> >> the best approach here. But I think we need to keep track of some kind 
> >> of state in order to know which was the last CEA block that was 
> >> returned, and thus this function can return the next one after that, 
> >> whether it's in the CEA extension block or DisplayID block.
> >
> >Per DisplayID v1.3 Appendix B: DisplayID as an EDID Extension, it's 
> >recommended that DisplayID extensions are exposed after all of the CEA 
> >extensions.
> >
> >I think it should be fine to first iterate over all CEA extensions across 
> >the 

[Intel-gfx] [PATCH v2 1/3] drm/i915: Report steering details in debugfs

[Matt Roper]

Add a new 'steering' node in each gt's debugfs directory that tells
whether we're using explicit steering for various types of MCR ranges
and, if so, what MMIO ranges it applies to.

We're going to be transitioning away from implicit steering, even for
slice/dss steering soon, so the information reported here will become
increasingly valuable once that happens.

v2:
 - Adding missing 'static' on intel_steering_types[]  (Jose, sparse)

Cc: Daniele Ceraolo Spurio 
Signed-off-by: Matt Roper 
Reviewed-by: José Roberto de Souza 
---
 drivers/gpu/drm/i915/gt/intel_gt.c  | 46 +
 drivers/gpu/drm/i915/gt/intel_gt.h  |  2 +
 drivers/gpu/drm/i915/gt/intel_gt_debugfs.c  | 13 ++
 drivers/gpu/drm/i915/gt/intel_gt_types.h|  5 +++
 drivers/gpu/drm/i915/gt/intel_workarounds.c |  8 +++-
 5 files changed, 73 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 8a2483ccbfb9..4c7ad9d14f4f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -96,6 +96,12 @@ int intel_gt_assign_ggtt(struct intel_gt *gt)
return gt->ggtt ? 0 : -ENOMEM;
 }
 
+static const char *intel_steering_types[] = {
+   "L3BANK",
+   "MSLICE",
+   "LNCF",
+};
+
 static const struct intel_mmio_range icl_l3bank_steering_table[] = {
{ 0x00B100, 0x00B3FF },
{},
@@ -932,6 +938,46 @@ u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t 
reg)
return intel_uncore_read(gt->uncore, reg);
 }
 
+static void report_steering_type(struct drm_printer *p,
+struct intel_gt *gt,
+enum intel_steering_type type,
+bool dump_table)
+{
+   const struct intel_mmio_range *entry;
+   u8 slice, subslice;
+
+   BUILD_BUG_ON(ARRAY_SIZE(intel_steering_types) != NUM_STEERING_TYPES);
+
+   if (!gt->steering_table[type]) {
+   drm_printf(p, "%s steering: uses default steering\n",
+  intel_steering_types[type]);
+   return;
+   }
+
+   intel_gt_get_valid_steering(gt, type, , );
+   drm_printf(p, "%s steering: sliceid=0x%x, subsliceid=0x%x\n",
+  intel_steering_types[type], slice, subslice);
+
+   if (!dump_table)
+   return;
+
+   for (entry = gt->steering_table[type]; entry->end; entry++)
+   drm_printf(p, "\t0x%06x - 0x%06x\n", entry->start, entry->end);
+}
+
+void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
+ bool dump_table)
+{
+   drm_printf(p, "Default steering: sliceid=0x%x, subsliceid=0x%x\n",
+  gt->default_steering.groupid,
+  gt->default_steering.instanceid);
+
+   if (HAS_MSLICES(gt->i915)) {
+   report_steering_type(p, gt, MSLICE, dump_table);
+   report_steering_type(p, gt, LNCF, dump_table);
+   }
+}
+
 void intel_gt_info_print(const struct intel_gt_info *info,
 struct drm_printer *p)
 {
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h 
b/drivers/gpu/drm/i915/gt/intel_gt.h
index 0f571c8ee22b..3edece1865e4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -87,6 +87,8 @@ static inline bool intel_gt_needs_read_steering(struct 
intel_gt *gt,
 u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg);
 u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
 
+void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
+ bool dump_table);
 void intel_gt_info_print(const struct intel_gt_info *info,
 struct drm_printer *p);
 
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c 
b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
index f103664b71d4..6f45b131a001 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
@@ -6,6 +6,7 @@
 #include 
 
 #include "i915_drv.h"
+#include "intel_gt.h"
 #include "intel_gt_debugfs.h"
 #include "intel_gt_engines_debugfs.h"
 #include "intel_gt_pm_debugfs.h"
@@ -57,10 +58,22 @@ static int __intel_gt_debugfs_reset_store(void *data, u64 
val)
 DEFINE_SIMPLE_ATTRIBUTE(reset_fops, __intel_gt_debugfs_reset_show,
__intel_gt_debugfs_reset_store, "%llu\n");
 
+static int steering_show(struct seq_file *m, void *data)
+{
+   struct drm_printer p = drm_seq_file_printer(m);
+   struct intel_gt *gt = m->private;
+
+   intel_gt_report_steering(, gt, true);
+
+   return 0;
+}
+DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(steering);
+
 static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)
 {
static const struct intel_gt_debugfs_file files[] = {
{ "reset", _fops, NULL },
+   { "steering", _fops },
};
 
intel_gt_debugfs_register_files(root, files, 

Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/gem: Remove logic for wbinvd_on_all_cpus

[Michael Cheng]

+Daniel for additional feedback!

On 2022-03-14 4:06 p.m., Michael Cheng wrote:


On 2022-03-08 10:58 a.m., Lucas De Marchi wrote:

On Tue, Feb 22, 2022 at 08:24:31PM +0100, Thomas Hellström (Intel) 
wrote:

Hi, Michael,

On 2/22/22 18:26, Michael Cheng wrote:

This patch removes logic for wbinvd_on_all_cpus and brings in
drm_cache.h. This header has the logic that outputs a warning
when wbinvd_on_all_cpus when its being used on a non-x86 platform.

Signed-off-by: Michael Cheng 


Linus has been pretty clear that he won't accept patches that add 
macros that works on one arch and warns on others anymore in i915 
and I figure even less so in drm code.


So we shouldn't try to move this out to drm. Instead we should 
restrict the wbinvd() inside our driver to integrated and X86 only. 
For discrete on all architectures we should be coherent and hence 
not be needing wbinvd().


the warn is there to guarantee we don't forget a code path. However
simply adding the warning is the real issue: we should rather guarantee
we can't take that code path. I.e., as you said refactor the code to
guarantee it works on discrete without that logic.

$ git grep wbinvd_on_all_cpus -- drivers/gpu/drm/
drivers/gpu/drm/drm_cache.c:    if (wbinvd_on_all_cpus())
drivers/gpu/drm/drm_cache.c:    if (wbinvd_on_all_cpus())
drivers/gpu/drm/drm_cache.c:    if (wbinvd_on_all_cpus())

drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c:  * Currently we 
just do a heavy handed wbinvd_on_all_cpus() here since

drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c: wbinvd_on_all_cpus();

It looks like we actually go through this on other discrete graphics. Is
this missing an update like s/IS_DG1/IS_DGFX/? Or should we be doing
something else?

drivers/gpu/drm/i915/gem/i915_gem_pm.c:#define 
wbinvd_on_all_cpus() \

drivers/gpu/drm/i915/gem/i915_gem_pm.c: wbinvd_on_all_cpus();

Those are for suspend. Revert ac05a22cd07a ("drm/i915/gem: Almagamate 
clflushes on suspend")

or extract that part to a helper function and implement it differently
for arches != x86?

drivers/gpu/drm/i915/gem/i915_gem_pm.c: wbinvd_on_all_cpus();

Probably take a similar approach to the suspend case?

drivers/gpu/drm/i915/gt/intel_ggtt.c: wbinvd_on_all_cpus();


For a helper function, I have a #define for all non x86 architecture 
that gives a warn on [1] within drm_cache.h Or would it be better to 
implement a helper function instead?


[1]. https://patchwork.freedesktop.org/patch/475750/?series=1=5



This one comes from 64b95df91f44 ("drm/i915: Assume exclusive access 
to objects inside resume")
Shouldn't that be doing the invalidate if the write domain is 
I915_GEM_DOMAIN_CPU


In the end I think the warning would be ok if it was the cherry on top,
to guarantee we don't take those paths. We should probably have a
warn_once() to avoid spamming the console. But we  also have to rework
the code to guarantee we are the only ones who may eventually get that
warning, and not the end user.
Could we first add the helper function/#define for now, and rework the 
code in a different patch series?


Lucas De Marchi



Thanks,

/Thomas

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Reduce stack usage in debugfs due to SSEU (rev2)

[Matt Roper]

On Tue, Mar 15, 2022 at 03:47:11PM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Reduce stack usage in debugfs due to SSEU (rev2)
> URL   : https://patchwork.freedesktop.org/series/101369/
> State : success
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_11363_full -> Patchwork_22567_full
> 
> 
> Summary
> ---
> 
>   **SUCCESS**
> 
>   No regressions found.

Applied to drm-intel-gt-next.  Thanks Jose for the review.


Matt

> 
>   
> 
> Participating hosts (13 -> 13)
> --
> 
>   No changes in participating hosts
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_22567_full:
> 
> ### IGT changes ###
> 
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * igt@gem_exec_schedule@smoketest@bcs0:
> - {shard-rkl}:[PASS][1] -> ([PASS][2], [INCOMPLETE][3])
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-6/igt@gem_exec_schedule@smoket...@bcs0.html
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22567/shard-rkl-4/igt@gem_exec_schedule@smoket...@bcs0.html
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22567/shard-rkl-5/igt@gem_exec_schedule@smoket...@bcs0.html
> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_22567_full that come from known 
> issues:
> 
> ### CI changes ###
> 
>  Possible fixes 
> 
>   * boot:
> - {shard-rkl}:([PASS][4], [PASS][5], [PASS][6], [PASS][7], 
> [PASS][8], [PASS][9], [PASS][10], [FAIL][11], [PASS][12], [PASS][13], 
> [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], 
> [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24]) ([i915#5131]) -> 
> ([PASS][25], [PASS][26], [PASS][27], [PASS][28], [PASS][29], [PASS][30], 
> [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], 
> [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], 
> [PASS][43])
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-6/boot.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-6/boot.html
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-6/boot.html
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-6/boot.html
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-5/boot.html
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-5/boot.html
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-5/boot.html
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-5/boot.html
>[12]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-5/boot.html
>[13]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-5/boot.html
>[14]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-5/boot.html
>[15]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-5/boot.html
>[16]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-4/boot.html
>[17]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-4/boot.html
>[18]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-4/boot.html
>[19]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-2/boot.html
>[20]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-2/boot.html
>[21]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-2/boot.html
>[22]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-1/boot.html
>[23]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-1/boot.html
>[24]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-1/boot.html
>[25]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22567/shard-rkl-5/boot.html
>[26]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22567/shard-rkl-5/boot.html
>[27]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22567/shard-rkl-5/boot.html
>[28]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22567/shard-rkl-5/boot.html
>[29]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22567/shard-rkl-5/boot.html
>[30]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22567/shard-rkl-5/boot.html
>[31]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22567/shard-rkl-4/boot.html
>[32]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22567/shard-rkl-4/boot.html
>[33]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22567/shard-rkl-2/boot.html
>[34]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22567/shard-rkl-2/boot.html
>[35]: 

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Some more bits for small BAR enabling (rev4)

[Vudum, Lakshminarayana]

Filed https://gitlab.freedesktop.org/drm/intel/-/issues/5349
igt@kms_cursor_legacy@pipe-b-torture-bo - incomplete - No warnings/errors

Thanks,
Lakshmi.
-Original Message-
From: Matthew Auld  
Sent: Tuesday, March 15, 2022 5:37 AM
To: Intel Graphics Development ; Vudum, 
Lakshminarayana 
Cc: Auld, Matthew 
Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Some more bits for small BAR 
enabling (rev4)

On Mon, 14 Mar 2022 at 16:49, Patchwork
 wrote:
>
> Patch Details
> Series:Some more bits for small BAR enabling (rev4) 
> URL:https://patchwork.freedesktop.org/series/101052/
> State:failure
> Details:https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22555/index
> .html
>
> CI Bug Log - changes from CI_DRM_11358_full -> Patchwork_22555_full
>
> Summary
>
> FAILURE
>
> Serious unknown changes coming with Patchwork_22555_full absolutely 
> need to be verified manually.
>
> If you think the reported changes have nothing to do with the changes 
> introduced in Patchwork_22555_full, please notify your bug team to 
> allow them to document this new failure mode, which will reduce false 
> positives in CI.
>
> Participating hosts (12 -> 12)
>
> No changes in participating hosts
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in 
> Patchwork_22555_full:
>
> IGT changes
>
> Possible regressions
>
> igt@kms_cursor_legacy@pipe-b-torture-bo:
>
> shard-glk: PASS -> INCOMPLETE

Fairly sure this is unrelated. Realistically this series should only really 
change things for discrete.

>
> Known issues
>
> Here are the changes found in Patchwork_22555_full that come from known 
> issues:
>
> CI changes
>
> Possible fixes
>
> boot:
>
> shard-glk: (PASS, PASS, PASS, PASS, PASS, PASS, FAIL, PASS, PASS, 
> PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, 
> PASS, PASS, PASS, PASS, PASS) ([i915#4392]) -> (PASS, PASS, PASS, 
> PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, 
> PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS)
>
> {shard-rkl}: (PASS, PASS, FAIL, PASS, PASS, PASS, PASS, PASS, PASS, 
> PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, 
> PASS) ([i915#5131]) -> (PASS, PASS, PASS, PASS, PASS, PASS, PASS, 
> PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, PASS, 
> PASS, PASS)
>
> IGT changes
>
> Issues hit
>
> igt@gem_ccs@block-copy-compressed:
>
> shard-tglb: NOTRUN -> SKIP ([i915#5325])
>
> shard-iclb: NOTRUN -> SKIP ([i915#5327])
>
> igt@gem_create@create-massive:
>
> shard-iclb: NOTRUN -> DMESG-WARN ([i915#4991]) +1 similar issue
>
> igt@gem_exec_balancer@parallel-contexts:
>
> shard-kbl: NOTRUN -> DMESG-WARN ([i915#5076])
>
> igt@gem_exec_fair@basic-none-share@rcs0:
>
> shard-iclb: PASS -> FAIL ([i915#2842])
>
> igt@gem_huc_copy@huc-copy:
>
> shard-tglb: PASS -> SKIP ([i915#2190])
>
> igt@gem_lmem_swapping@heavy-verify-multi:
>
> shard-kbl: NOTRUN -> SKIP ([fdo#109271] / [i915#4613])
>
> shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#4613])
>
> igt@gem_lmem_swapping@random-engines:
>
> shard-iclb: NOTRUN -> SKIP ([i915#4613]) +1 similar issue
>
> igt@gem_lmem_swapping@verify-random:
>
> shard-skl: NOTRUN -> SKIP ([fdo#109271] / [i915#4613]) +1 similar 
> issue
>
> igt@gem_pxp@create-protected-buffer:
>
> shard-iclb: NOTRUN -> SKIP ([i915#4270]) +1 similar issue
>
> igt@gem_pxp@verify-pxp-stale-ctx-execution:
>
> shard-tglb: NOTRUN -> SKIP ([i915#4270])
>
> igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
>
> shard-iclb: NOTRUN -> SKIP ([i915#768]) +2 similar issues
>
> igt@gem_userptr_blits@unsync-overlap:
>
> shard-iclb: NOTRUN -> SKIP ([i915#3297]) +1 similar issue
>
> igt@gen7_exec_parse@basic-offset:
>
> shard-tglb: NOTRUN -> SKIP ([fdo#109289])
>
> igt@gen7_exec_parse@chained-batch:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#109289]) +3 similar issues
>
> igt@gen9_exec_parse@allowed-single:
>
> shard-skl: PASS -> DMESG-WARN ([i915#1436] / [i915#716])
>
> igt@gen9_exec_parse@batch-without-end:
>
> shard-iclb: NOTRUN -> SKIP ([i915#2856]) +1 similar issue
>
> igt@i915_pm_dc@dc6-psr:
>
> shard-iclb: PASS -> FAIL ([i915#454])
>
> igt@i915_pm_rpm@dpms-mode-unset-non-lpsp:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#110892])
>
> igt@i915_suspend@fence-restore-untiled:
>
> shard-kbl: PASS -> DMESG-WARN ([i915#180])
>
> igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
>
> shard-iclb: NOTRUN -> SKIP ([i915#3826])
>
> igt@kms_big_fb@4-tiled-32bpp-rotate-270:
>
> shard-iclb: NOTRUN -> SKIP ([i915#5286]) +2 similar issues
>
> igt@kms_big_fb@4-tiled-8bpp-rotate-270:
>
> shard-tglb: NOTRUN -> SKIP ([i915#5286])
>
> igt@kms_big_fb@x-tiled-16bpp-rotate-270:
>
> shard-iclb: NOTRUN -> SKIP ([fdo#110725] / [fdo#111614]) +1 similar 
> issue
>
> igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
>
> shard-skl: NOTRUN -> FAIL ([i915#3743])
>
> igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
>
> shard-apl: NOTRUN -> SKIP ([fdo#109271] / [i915#3777])
>
> shard-skl: NOTRUN -> SKIP 

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Reduce stack usage in debugfs due to SSEU

[Vudum, Lakshminarayana]

Issue is related to https://gitlab.freedesktop.org/drm/intel/-/issues/3576
[ADL-P] KMS tests - dmesg-warn/dmesg-fail - *ERROR* CPU pipe A FIFO underrun: 
(port|soft),transcoder,

And the latest reg from rev 2 is 
https://gitlab.freedesktop.org/drm/intel/-/issues/5343
igt@i915_pm_dc@dc5-psr - crash - Received signal SIGSEGV.

Thanks,
Lakshmi.

-Original Message-
From: Roper, Matthew D  
Sent: Monday, March 14, 2022 9:34 PM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana 
Subject: Re: ✗ Fi.CI.BAT: failure for drm/i915: Reduce stack usage in debugfs 
due to SSEU

On Tue, Mar 15, 2022 at 03:01:44AM +, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915: Reduce stack usage in debugfs due to SSEU
> URL   : https://patchwork.freedesktop.org/series/101369/
> State : failure
> 
> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_11363 -> Patchwork_22566 
> 
> 
> Summary
> ---
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_22566 absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_22566, please notify your bug team to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22566/index.html
> 
> Participating hosts (50 -> 43)
> --
> 
>   Additional (3): bat-adlm-1 bat-adlp-4 fi-kbl-8809g 
>   Missing(10): shard-tglu fi-hsw-4200u shard-rkl fi-icl-u2 fi-bsw-cyan 
> fi-kbl-7500u fi-ctg-p8600 fi-hsw-4770 bat-rpls-2 fi-bdw-samus 
> 
> Possible new issues
> ---
> 
>   Here are the unknown changes that may have been introduced in 
> Patchwork_22566:
> 
> ### IGT changes ###
> 
>  Possible regressions 
> 
>   * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
> - bat-adlp-4: NOTRUN -> [DMESG-WARN][1]
>[1]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22566/bat-adlp-4/ig
> t@kms_flip@basic-flip-vs-mode...@a-edp1.html

<3> [273.206566] i915 :00:02.0: [drm] *ERROR* CPU pipe A FIFO underrun: 
port,transcoder,

A display underrun wouldn't be related to how a debugfs file (which isn't being 
used here) allocates memory.

It seems like there are also a bunch of missing machines listed above for no 
apparent reason.  Submitting a re-test.


Matt

> 
>   
>  Suppressed 
> 
>   The following results come from untrusted machines, tests, or statuses.
>   They do not affect the overall result.
> 
>   * igt@kms_busy@basic@flip:
> - {bat-adlp-6}:   [PASS][2] -> [DMESG-WARN][3]
>[2]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/bat-adlp-6/igt@kms_busy@ba...@flip.html
>[3]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22566/bat-adlp-6/ig
> t@kms_busy@ba...@flip.html
> 
>   * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
> - {bat-dg2-9}:[DMESG-WARN][4] ([i915#5193]) -> [DMESG-FAIL][5]
>[4]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/bat-dg2-9/igt@kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
>[5]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22566/bat-dg2-9/igt
> @kms_pipe_crc_ba...@suspend-read-crc-pipe-a.html
> 
>   
> Known issues
> 
> 
>   Here are the changes found in Patchwork_22566 that come from known issues:
> 
> ### IGT changes ###
> 
>  Issues hit 
> 
>   * igt@gem_exec_suspend@basic-s0@smem:
> - fi-kbl-8809g:   NOTRUN -> [DMESG-WARN][6] ([i915#4962]) +1 similar 
> issue
>[6]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22566/fi-kbl-8809g/
> igt@gem_exec_suspend@basic...@smem.html
> 
>   * igt@gem_huc_copy@huc-copy:
> - fi-kbl-8809g:   NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
>[7]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22566/fi-kbl-8809g/
> igt@gem_huc_c...@huc-copy.html
> 
>   * igt@gem_lmem_swapping@basic:
> - bat-adlp-4: NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues
>[8]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22566/bat-adlp-4/ig
> t@gem_lmem_swapp...@basic.html
> 
>   * igt@gem_lmem_swapping@random-engines:
> - fi-kbl-8809g:   NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 
> similar issues
>[9]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22566/fi-kbl-8809g/
> igt@gem_lmem_swapp...@random-engines.html
> 
>   * igt@gem_tiled_pread_basic:
> - bat-adlp-4: NOTRUN -> [SKIP][10] ([i915#3282])
>[10]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22566/bat-adlp-4/ig
> t@gem_tiled_pread_basic.html
> 
>   * igt@i915_pm_rpm@basic-rte:
> - fi-kbl-8809g:   NOTRUN -> [SKIP][11] ([fdo#109271]) +55 similar 
> issues
>[11]: 
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22566/fi-kbl-8809g/
> igt@i915_pm_...@basic-rte.html
> 
>   * igt@i915_pm_rps@basic-api:
> - 

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: More DRRS work

[Patchwork]

== Series Details ==

Series: drm/i915: More DRRS work
URL   : https://patchwork.freedesktop.org/series/101390/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11363_full -> Patchwork_22571_full


Summary
---

  **SUCCESS**

  No regressions found.

  

Participating hosts (13 -> 13)
--

  No changes in participating hosts

Known issues


  Here are the changes found in Patchwork_22571_full that come from known 
issues:

### CI changes ###

 Possible fixes 

  * boot:
- {shard-rkl}:([PASS][1], [PASS][2], [PASS][3], [PASS][4], 
[PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], 
[PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], 
[PASS][18], [PASS][19], [PASS][20], [FAIL][21]) ([i915#5131]) -> ([PASS][22], 
[PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27], [PASS][28], 
[PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], 
[PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], 
[PASS][41], [PASS][42], [PASS][43])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-5/boot.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-5/boot.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-5/boot.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-5/boot.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-4/boot.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-4/boot.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-4/boot.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-2/boot.html
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-2/boot.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-2/boot.html
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-1/boot.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-1/boot.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-1/boot.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-6/boot.html
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-6/boot.html
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-6/boot.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-6/boot.html
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-5/boot.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-5/boot.html
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-5/boot.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11363/shard-rkl-5/boot.html
   [22]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-6/boot.html
   [23]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-6/boot.html
   [24]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-6/boot.html
   [25]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-6/boot.html
   [26]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-5/boot.html
   [27]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-5/boot.html
   [28]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-5/boot.html
   [29]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-5/boot.html
   [30]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-4/boot.html
   [31]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-4/boot.html
   [32]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-4/boot.html
   [33]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-4/boot.html
   [34]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-2/boot.html
   [35]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-2/boot.html
   [36]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-2/boot.html
   [37]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-2/boot.html
   [38]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-2/boot.html
   [39]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-2/boot.html
   [40]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-2/boot.html
   [41]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-1/boot.html
   [42]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-1/boot.html
   [43]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22571/shard-rkl-1/boot.html

  

### IGT changes ###

 Issues hit 

  * igt@gem_ccs@block-copy-compressed:

Re: [Intel-gfx] [PATCH 1/3] drm/i915: Report steering details in debugfs

[Souza, Jose]

On Mon, 2022-03-14 at 16:42 -0700, Matt Roper wrote:
> Add a new 'steering' node in each gt's debugfs directory that tells
> whether we're using explicit steering for various types of MCR ranges
> and, if so, what MMIO ranges it applies to.
> 
> We're going to be transitioning away from implicit steering, even for
> slice/dss steering soon, so the information reported here will become
> increasingly valuable once that happens.
> 
> Cc: Daniele Ceraolo Spurio 
> Signed-off-by: Matt Roper 
> ---
>  drivers/gpu/drm/i915/gt/intel_gt.c  | 46 +
>  drivers/gpu/drm/i915/gt/intel_gt.h  |  2 +
>  drivers/gpu/drm/i915/gt/intel_gt_debugfs.c  | 13 ++
>  drivers/gpu/drm/i915/gt/intel_gt_types.h|  5 +++
>  drivers/gpu/drm/i915/gt/intel_workarounds.c |  8 +++-
>  5 files changed, 73 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
> b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 8a2483ccbfb9..041add4019fc 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -96,6 +96,12 @@ int intel_gt_assign_ggtt(struct intel_gt *gt)
>   return gt->ggtt ? 0 : -ENOMEM;
>  }
>  
> +const char *intel_steering_types[] = {

missing static as kernel test bot reported.
with that fixed: Reviewed-by: José Roberto de Souza 

> + "L3BANK",
> + "MSLICE",
> + "LNCF",
> +};
> +
>  static const struct intel_mmio_range icl_l3bank_steering_table[] = {
>   { 0x00B100, 0x00B3FF },
>   {},
> @@ -932,6 +938,46 @@ u32 intel_gt_read_register(struct intel_gt *gt, 
> i915_reg_t reg)
>   return intel_uncore_read(gt->uncore, reg);
>  }
>  
> +static void report_steering_type(struct drm_printer *p,
> +  struct intel_gt *gt,
> +  enum intel_steering_type type,
> +  bool dump_table)
> +{
> + const struct intel_mmio_range *entry;
> + u8 slice, subslice;
> +
> + BUILD_BUG_ON(ARRAY_SIZE(intel_steering_types) != NUM_STEERING_TYPES);
> +
> + if (!gt->steering_table[type]) {
> + drm_printf(p, "%s steering: uses default steering\n",
> +intel_steering_types[type]);
> + return;
> + }
> +
> + intel_gt_get_valid_steering(gt, type, , );
> + drm_printf(p, "%s steering: sliceid=0x%x, subsliceid=0x%x\n",
> +intel_steering_types[type], slice, subslice);
> +
> + if (!dump_table)
> + return;
> +
> + for (entry = gt->steering_table[type]; entry->end; entry++)
> + drm_printf(p, "\t0x%06x - 0x%06x\n", entry->start, entry->end);
> +}
> +
> +void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
> +   bool dump_table)
> +{
> + drm_printf(p, "Default steering: sliceid=0x%x, subsliceid=0x%x\n",
> +gt->default_steering.groupid,
> +gt->default_steering.instanceid);
> +
> + if (HAS_MSLICES(gt->i915)) {
> + report_steering_type(p, gt, MSLICE, dump_table);
> + report_steering_type(p, gt, LNCF, dump_table);
> + }
> +}
> +
>  void intel_gt_info_print(const struct intel_gt_info *info,
>struct drm_printer *p)
>  {
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h 
> b/drivers/gpu/drm/i915/gt/intel_gt.h
> index 0f571c8ee22b..3edece1865e4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -87,6 +87,8 @@ static inline bool intel_gt_needs_read_steering(struct 
> intel_gt *gt,
>  u32 intel_gt_read_register_fw(struct intel_gt *gt, i915_reg_t reg);
>  u32 intel_gt_read_register(struct intel_gt *gt, i915_reg_t reg);
>  
> +void intel_gt_report_steering(struct drm_printer *p, struct intel_gt *gt,
> +   bool dump_table);
>  void intel_gt_info_print(const struct intel_gt_info *info,
>struct drm_printer *p);
>  
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c 
> b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> index f103664b71d4..6f45b131a001 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_debugfs.c
> @@ -6,6 +6,7 @@
>  #include 
>  
>  #include "i915_drv.h"
> +#include "intel_gt.h"
>  #include "intel_gt_debugfs.h"
>  #include "intel_gt_engines_debugfs.h"
>  #include "intel_gt_pm_debugfs.h"
> @@ -57,10 +58,22 @@ static int __intel_gt_debugfs_reset_store(void *data, u64 
> val)
>  DEFINE_SIMPLE_ATTRIBUTE(reset_fops, __intel_gt_debugfs_reset_show,
>   __intel_gt_debugfs_reset_store, "%llu\n");
>  
> +static int steering_show(struct seq_file *m, void *data)
> +{
> + struct drm_printer p = drm_seq_file_printer(m);
> + struct intel_gt *gt = m->private;
> +
> + intel_gt_report_steering(, gt, true);
> +
> + return 0;
> +}
> +DEFINE_INTEL_GT_DEBUGFS_ATTRIBUTE(steering);
> +
>  static void gt_debugfs_register(struct intel_gt *gt, struct dentry *root)