Re: [PATCH 1/2] drm/i915/display: remove small micro-optimizations in irq handling

[Lucas De Marchi]

On Mon, Apr 08, 2024 at 03:54:44PM GMT, Jani Nikula wrote:

The raw register reads/writes are there as micro-optimizations to avoid
multiple pointer indirections on uncore->regs. Presumably this is useful
when there are plenty of register reads/writes in the same
function. However, the display irq handling only has a few raw
reads/writes. Remove them for simplification.


I think that comment didn't age well. Not to say there's something wrong
with this commit, but just to make sure we are aware of the additional
stuff going on and we if we are ok with that.

using intel_de_read() in place of raw_reg_read() will do (for newer
platforms):

1) Read FPGA_DBG to detect unclaimed access before the actual read
2) Find the relevant forcewake for that register, acquire and wait for 
ack
3) readl(reg)
4) Read FPGA_DBG to detect unclaimed access after the actual read
5) Trace reg rw

That's much more than a pointer indirection. Are we ok with that in the
irq?  Also, I don't know why but we have variants to skip tracing (step
5 above), but on my books a disabled tracepoint is order of magnitudes
less overhead than 1, 2 and 4.

btw, if we drop the raw accesses, then we can probably drop (1) above.

Lucas De Marchi



Signed-off-by: Jani Nikula 
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c 
b/drivers/gpu/drm/i915/display/intel_display_irq.c
index f846c5b108b5..d4ae9139be39 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -1148,15 +1148,14 @@ void gen8_de_irq_handler(struct drm_i915_private 
*dev_priv, u32 master_ctl)

u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32 master_ctl)
{
-   void __iomem * const regs = intel_uncore_regs(>uncore);
u32 iir;

if (!(master_ctl & GEN11_GU_MISC_IRQ))
return 0;

-   iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
+   iir = intel_de_read(i915, GEN11_GU_MISC_IIR);
if (likely(iir))
-   raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
+   intel_de_write(i915, GEN11_GU_MISC_IIR, iir);

return iir;
}
@@ -1169,18 +1168,18 @@ void gen11_gu_misc_irq_handler(struct drm_i915_private 
*i915, const u32 iir)

void gen11_display_irq_handler(struct drm_i915_private *i915)
{
-   void __iomem * const regs = intel_uncore_regs(>uncore);
-   const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
+   u32 disp_ctl;

disable_rpm_wakeref_asserts(>runtime_pm);
/*
 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
 * for the display related bits.
 */
-   raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
+   disp_ctl = intel_de_read(i915, GEN11_DISPLAY_INT_CTL);
+
+   intel_de_write(i915, GEN11_DISPLAY_INT_CTL, 0);
gen8_de_irq_handler(i915, disp_ctl);
-   raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
- GEN11_DISPLAY_IRQ_ENABLE);
+   intel_de_write(i915, GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);

enable_rpm_wakeref_asserts(>runtime_pm);
}
--
2.39.2

✓ Fi.CI.BAT: success for drm/i915/dg2: wait for HuC load completion before running selftests (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dg2: wait for HuC load completion before running selftests 
(rev2)
URL   : https://patchwork.freedesktop.org/series/132300/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14597 -> Patchwork_132300v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/index.html

Participating hosts (38 -> 38)
--

  Additional (4): fi-cfl-8109u bat-jsl-1 bat-arls-2 fi-bsw-n3050 
  Missing(4): fi-kbl-7567u fi-glk-j4005 fi-snb-2520m fi-elk-e7500 

Known issues


  Here are the changes found in Patchwork_132300v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-jsl-1:  NOTRUN -> [SKIP][1] ([i915#9318])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html
- bat-arls-2: NOTRUN -> [SKIP][2] ([i915#9318])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/bat-arls-2/igt@debugfs_t...@basic-hwmon.html

  * igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u:   NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html
- bat-jsl-1:  NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/bat-jsl-1/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-11: [PASS][5] -> [FAIL][6] ([i915#10378])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14597/bat-dg2-11/igt@gem_lmem_swapping@ba...@lmem0.html
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/bat-dg2-11/igt@gem_lmem_swapping@ba...@lmem0.html
- bat-dg2-9:  [PASS][7] -> [FAIL][8] ([i915#10378])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14597/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html

  * igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050:   NOTRUN -> [SKIP][9] +19 other tests skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/fi-bsw-n3050/igt@gem_lmem_swapp...@random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- fi-cfl-8109u:   NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/fi-cfl-8109u/igt@gem_lmem_swapp...@verify-random.html
- bat-arls-2: NOTRUN -> [SKIP][11] ([i915#10213]) +3 other tests 
skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html
- bat-jsl-1:  NOTRUN -> [SKIP][12] ([i915#4613]) +3 other tests skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/bat-jsl-1/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-arls-2: NOTRUN -> [SKIP][13] ([i915#4083])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/bat-arls-2/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-arls-2: NOTRUN -> [SKIP][14] ([i915#10196] / [i915#4077]) +2 
other tests skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/bat-arls-2/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-arls-2: NOTRUN -> [SKIP][15] ([i915#10197] / [i915#10211] / 
[i915#4079])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/bat-arls-2/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-arls-2: NOTRUN -> [SKIP][16] ([i915#10206] / [i915#4079])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/bat-arls-2/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-arls-2: NOTRUN -> [SKIP][17] ([i915#10209])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/bat-arls-2/igt@i915_pm_...@basic-api.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-arls-2: NOTRUN -> [SKIP][18] ([i915#10200]) +9 other tests 
skip
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/bat-arls-2/igt@kms_addfb_ba...@addfb25-y-tiled-small-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-arls-2: NOTRUN -> [SKIP][19] ([i915#10202]) +1 other test skip
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/bat-arls-2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html
- bat-jsl-1:  NOTRUN -> [SKIP][20] ([i915#4103]) +1 other test skip
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132300v2/bat-jsl-1/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * 

RE: [PATCH 2/2] drm/xe/display: remove compat raw reg read/write support

[Sripada, Radhakrishna]

LGTM,
Reviewed-by: Radhakrishna Sripada 

> -Original Message-
> From: Intel-xe  On Behalf Of Jani 
> Nikula
> Sent: Monday, April 8, 2024 5:55 AM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Nikula, Jani ; De Marchi, Lucas
> 
> Subject: [PATCH 2/2] drm/xe/display: remove compat raw reg read/write support
> 
> The i915 display code no longer uses these interfaces. Remove them.
> 
> Signed-off-by: Jani Nikula 
> ---
>  .../drm/xe/compat-i915-headers/intel_uncore.h | 24 ---
>  1 file changed, 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> index ef79793caa72..a672165ececf 100644
> --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> +++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
> @@ -148,28 +148,4 @@ static inline void intel_uncore_write_notrace(struct
> intel_uncore *uncore,
>   xe_mmio_write32(__compat_uncore_to_gt(uncore), reg, val);
>  }
> 
> -static inline void __iomem *intel_uncore_regs(struct intel_uncore *uncore)
> -{
> - struct xe_device *xe = container_of(uncore, struct xe_device, uncore);
> -
> - return xe_device_get_root_tile(xe)->mmio.regs;
> -}
> -
> -/*
> - * The raw_reg_{read,write} macros are intended as a micro-optimization for
> - * interrupt handlers so that the pointer indirection on uncore->regs can
> - * be computed once (and presumably cached in a register) instead of 
> generating
> - * extra load instructions for each MMIO access.
> - *
> - * Given that these macros are only intended for non-GSI interrupt registers
> - * (and the goal is to avoid extra instructions generated by the compiler),
> - * these macros do not account for uncore->gsi_offset.  Any caller that needs
> - * to use these macros on a GSI register is responsible for adding the
> - * appropriate GSI offset to the 'base' parameter.
> - */
> -#define raw_reg_read(base, reg) \
> - readl(base + i915_mmio_reg_offset(reg))
> -#define raw_reg_write(base, reg, value) \
> - writel(value, base + i915_mmio_reg_offset(reg))
> -
>  #endif /* __INTEL_UNCORE_H__ */
> --
> 2.39.2

RE: [PATCH 1/2] drm/i915/display: remove small micro-optimizations in irq handling

[Sripada, Radhakrishna]

LGTM,
Reviewed-by: Radhakrishna Sripada 

> -Original Message-
> From: Intel-gfx  On Behalf Of Jani
> Nikula
> Sent: Monday, April 8, 2024 5:55 AM
> To: intel-gfx@lists.freedesktop.org; intel...@lists.freedesktop.org
> Cc: Nikula, Jani ; De Marchi, Lucas
> 
> Subject: [PATCH 1/2] drm/i915/display: remove small micro-optimizations in irq
> handling
> 
> The raw register reads/writes are there as micro-optimizations to avoid
> multiple pointer indirections on uncore->regs. Presumably this is useful
> when there are plenty of register reads/writes in the same
> function. However, the display irq handling only has a few raw
> reads/writes. Remove them for simplification.
> 
> Signed-off-by: Jani Nikula 
> ---
>  drivers/gpu/drm/i915/display/intel_display_irq.c | 15 +++
>  1 file changed, 7 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index f846c5b108b5..d4ae9139be39 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -1148,15 +1148,14 @@ void gen8_de_irq_handler(struct drm_i915_private
> *dev_priv, u32 master_ctl)
> 
>  u32 gen11_gu_misc_irq_ack(struct drm_i915_private *i915, const u32
> master_ctl)
>  {
> - void __iomem * const regs = intel_uncore_regs(>uncore);
>   u32 iir;
> 
>   if (!(master_ctl & GEN11_GU_MISC_IRQ))
>   return 0;
> 
> - iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
> + iir = intel_de_read(i915, GEN11_GU_MISC_IIR);
>   if (likely(iir))
> - raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
> + intel_de_write(i915, GEN11_GU_MISC_IIR, iir);
> 
>   return iir;
>  }
> @@ -1169,18 +1168,18 @@ void gen11_gu_misc_irq_handler(struct
> drm_i915_private *i915, const u32 iir)
> 
>  void gen11_display_irq_handler(struct drm_i915_private *i915)
>  {
> - void __iomem * const regs = intel_uncore_regs(>uncore);
> - const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
> + u32 disp_ctl;
> 
>   disable_rpm_wakeref_asserts(>runtime_pm);
>   /*
>* GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
>* for the display related bits.
>*/
> - raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
> + disp_ctl = intel_de_read(i915, GEN11_DISPLAY_INT_CTL);
> +
> + intel_de_write(i915, GEN11_DISPLAY_INT_CTL, 0);
>   gen8_de_irq_handler(i915, disp_ctl);
> - raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
> -   GEN11_DISPLAY_IRQ_ENABLE);
> + intel_de_write(i915, GEN11_DISPLAY_INT_CTL,
> GEN11_DISPLAY_IRQ_ENABLE);
> 
>   enable_rpm_wakeref_asserts(>runtime_pm);
>  }
> --
> 2.39.2

Re: [PATCH v2 1/4] drm/amd/display: Remove unnecessary SIGNAL_TYPE_HDMI_TYPE_A check

[Harry Wentland]

On 2024-01-15 11:05, Andri Yngvason wrote:
> From: Werner Sembach 
> 
> Remove unnecessary SIGNAL_TYPE_HDMI_TYPE_A check that was performed in the
> drm_mode_is_420_only() case, but not in the drm_mode_is_420_also() &&
> force_yuv420_output case.
> 
> Without further knowledge if YCbCr 4:2:0 is supported outside of HDMI,
> there is no reason to use RGB when the display
> reports drm_mode_is_420_only() even on a non HDMI connection.
> 
> This patch also moves both checks in the same if-case. This  eliminates an
> extra else-if-case.
> 
> Signed-off-by: Werner Sembach 
> Signed-off-by: Andri Yngvason 
> Tested-by: Andri Yngvason 
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +-
>  1 file changed, 1 insertion(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index f6575d7dee971..cc4d1f7f97b98 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -5575,11 +5575,7 @@ static void 
> fill_stream_properties_from_drm_display_mode(
>   timing_out->v_border_bottom = 0;
>   /* TODO: un-hardcode */
>   if (drm_mode_is_420_only(info, mode_in)
> - && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
> - timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
> - else if (drm_mode_is_420_also(info, mode_in)
> - && aconnector
> - && aconnector->force_yuv420_output)
> + || (drm_mode_is_420_also(info, mode_in) && 
> aconnector->force_yuv420_output))

We need to keep the && aconnector NULL check here, otherwise
writeback connectors will blow up.

Harry

>   timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
>   else if ((connector->display_info.color_formats & 
> DRM_COLOR_FORMAT_YCBCR444)
>   && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)

Re: [PATCH v2 2/4] drm/uAPI: Add "force color format" drm property as setting for userspace

[Harry Wentland]

I'm a bit late to the game but I don't think this is merged
yet.

On 2024-01-15 11:05, Andri Yngvason wrote:
> From: Werner Sembach 
> 
> Add a new general drm property "force color format" which can be used
> by userspace to tell the graphics driver which color format to use.
> 
> Possible options are:
> - auto (default/current behaviour)
> - rgb
> - ycbcr444
> - ycbcr422 (supported by neither amdgpu or i915)

If no driver uses this should we expose this now? I would
prefer to leave ycbcr422 out of this until we have a driver
that actually uses it.

I've seen too many properties with ever possible value defined
but they're not used by any (open) userspace and then become
the object of intense discussion on how they should work. I
doubt that this would happen here, but I still feel a slight
aversion to defining things that no open userspace can use at
this point.

I agree with all of Sebastian and Pekka's comments elsewhere in
this thread, in particular with Sebastian's comments to not
advertise color formats that a driver can't support. See this
patch for how I implemented something similar for Colorspace
c265f340eaa8 ("drm/connector: Allow drivers to pass list of supported 
colorspaces")

Harry

> - ycbcr420
> 
> In theory the auto option should choose the best available option for the
> current setup, but because of bad internal conversion some monitors look
> better with rgb and some with ycbcr444.
> 
> Also, because of bad shielded connectors and/or cables, it might be
> preferable to use the less bandwidth heavy ycbcr422 and ycbcr420 formats
> for a signal that is less susceptible to interference.
> 
> In the future, automatic color calibration for screens might also depend on
> this option being available.
> 
> Signed-off-by: Werner Sembach 
> Signed-off-by: Andri Yngvason 
> Tested-by: Andri Yngvason 
> ---
> 
> Changes in v2:
>  - Renamed to "force color format" from "preferred color format"
>  - Removed Reported-by pointing to invalid email address
> 
> ---
>  drivers/gpu/drm/drm_atomic_helper.c |  4 +++
>  drivers/gpu/drm/drm_atomic_uapi.c   |  4 +++
>  drivers/gpu/drm/drm_connector.c | 48 +
>  include/drm/drm_connector.h | 16 ++
>  4 files changed, 72 insertions(+)
> 
> diff --git a/drivers/gpu/drm/drm_atomic_helper.c 
> b/drivers/gpu/drm/drm_atomic_helper.c
> index 39ef0a6addeba..1dabd164c4f09 100644
> --- a/drivers/gpu/drm/drm_atomic_helper.c
> +++ b/drivers/gpu/drm/drm_atomic_helper.c
> @@ -707,6 +707,10 @@ drm_atomic_helper_check_modeset(struct drm_device *dev,
>   if (old_connector_state->max_requested_bpc !=
>   new_connector_state->max_requested_bpc)
>   new_crtc_state->connectors_changed = true;
> +
> + if (old_connector_state->force_color_format !=
> + new_connector_state->force_color_format)
> + new_crtc_state->connectors_changed = true;
>   }
>  
>   if (funcs->atomic_check)
> diff --git a/drivers/gpu/drm/drm_atomic_uapi.c 
> b/drivers/gpu/drm/drm_atomic_uapi.c
> index 29d4940188d49..e45949bf4615f 100644
> --- a/drivers/gpu/drm/drm_atomic_uapi.c
> +++ b/drivers/gpu/drm/drm_atomic_uapi.c
> @@ -776,6 +776,8 @@ static int drm_atomic_connector_set_property(struct 
> drm_connector *connector,
>   state->max_requested_bpc = val;
>   } else if (property == connector->privacy_screen_sw_state_property) {
>   state->privacy_screen_sw_state = val;
> + } else if (property == connector->force_color_format_property) {
> + state->force_color_format = val;
>   } else if (connector->funcs->atomic_set_property) {
>   return connector->funcs->atomic_set_property(connector,
>   state, property, val);
> @@ -859,6 +861,8 @@ drm_atomic_connector_get_property(struct drm_connector 
> *connector,
>   *val = state->max_requested_bpc;
>   } else if (property == connector->privacy_screen_sw_state_property) {
>   *val = state->privacy_screen_sw_state;
> + } else if (property == connector->force_color_format_property) {
> + *val = state->force_color_format;
>   } else if (connector->funcs->atomic_get_property) {
>   return connector->funcs->atomic_get_property(connector,
>   state, property, val);
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index b0516505f7ae9..e0535e58b4535 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -1061,6 +1061,14 @@ static const struct drm_prop_enum_list 
> drm_dp_subconnector_enum_list[] = {
>   { DRM_MODE_SUBCONNECTOR_Native,  "Native"}, /* DP */
>  };
>  
> +static const struct drm_prop_enum_list drm_force_color_format_enum_list[] = {
> + { 0, "auto" },
> + { 

[linux-next:master] BUILD REGRESSION 4eab358930711bbeb85bf5ee267d0d42d3394c2c

[kernel test robot]

tree/branch: 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 4eab358930711bbeb85bf5ee267d0d42d3394c2c  Add linux-next specific 
files for 20240417

Error/Warning reports:

https://lore.kernel.org/oe-kbuild-all/202404171743.hfpscodv-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202404171745.zd13ydca-...@intel.com
https://lore.kernel.org/oe-kbuild-all/202404172024.abf4kjuo-...@intel.com

Error/Warning: (recently discovered and may have been fixed)

arch/xtensa/include/asm/irqflags.h:47:(.text+0xf5c): dangerous relocation: 
windowed longcall crosses 1GB boundary; return may fail: (.xiptext+0x210)
mm/page_table_check.c:192:17: error: use of undeclared identifier 
'SWP_DEVICE_EXCLUSIVE_WRITE'
mm/page_table_check.c:192:24: error: 'SWP_DEVICE_EXCLUSIVE_WRITE' undeclared 
(first use in this function)
mm/page_table_check.c:193:14: error: use of undeclared identifier 
'SWP_MIGRATION_WRITE'
mm/page_table_check.c:194:1: warning: control reaches end of non-void function 
[-Wreturn-type]
xtensa-linux-ld: clk-cv18xx-pll.c:(.text+0x2f8): undefined reference to 
`__udivdi3'
xtensa-linux-ld: clk-cv18xx-pll.c:(.text+0x6c8): undefined reference to 
`__umoddi3'

Unverified Error/Warning (likely false positive, please contact us if 
interested):

fs/9p/vfs_inode.c:513 v9fs_remove() error: uninitialized symbol 'v9fid'.

Error/Warning ids grouped by kconfigs:

gcc_recent_errors
|-- alpha-allyesconfig
|   |-- 
drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and
|   `-- 
drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size
|-- alpha-randconfig-r081-20240417
|   `-- fs-9p-vfs_inode.c-v9fs_remove()-error:uninitialized-symbol-v9fid-.
|-- arc-allmodconfig
|   `-- 
arch-arc-include-asm-cmpxchg.h:error:implicit-declaration-of-function-cmpxchg_emu_u8
|-- arc-allnoconfig
|   `-- 
arch-arc-include-asm-cmpxchg.h:error:implicit-declaration-of-function-cmpxchg_emu_u8
|-- arc-allyesconfig
|   `-- 
arch-arc-include-asm-cmpxchg.h:error:implicit-declaration-of-function-cmpxchg_emu_u8
|-- arc-defconfig
|   `-- 
arch-arc-include-asm-cmpxchg.h:error:implicit-declaration-of-function-cmpxchg_emu_u8
|-- arc-randconfig-001-20240417
|   `-- 
arch-arc-include-asm-cmpxchg.h:error:implicit-declaration-of-function-cmpxchg_emu_u8
|-- arc-randconfig-002-20240417
|   `-- 
arch-arc-include-asm-cmpxchg.h:error:implicit-declaration-of-function-cmpxchg_emu_u8
|-- arc-randconfig-r112-20240417
|   `-- 
arch-arc-include-asm-cmpxchg.h:error:implicit-declaration-of-function-cmpxchg_emu_u8
|-- arm-allmodconfig
|   |-- 
drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and
|   `-- 
drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size
|-- arm-allyesconfig
|   |-- 
drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and
|   `-- 
drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size
|-- arm-randconfig-004-20240417
|   `-- clk-cv18xx-pll.c:(.text):undefined-reference-to-__aeabi_uldivmod
|-- csky-allmodconfig
|   |-- 
drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and
|   `-- 
drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size
|-- csky-allyesconfig
|   |-- 
drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and
|   `-- 
drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size
|-- i386-randconfig-003-20240417
|   |-- 
drivers-net-netdevsim-netdev.c:(.text):undefined-reference-to-page_pool_create
|   `-- 
include-net-page_pool-helpers.h:(.text):undefined-reference-to-page_pool_alloc_pages
|-- loongarch-allmodconfig
|   |-- 
drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and
|   `-- 
drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size
|-- loongarch-allyesconfig
|   |-- 
drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between-and
|   `-- 
drivers-gpu-drm-nouveau-nouveau_backlight.c:error:d-directive-output-may-be-truncated-writing-between-and-bytes-into-a-region-of-size
|-- microblaze-allmodconfig
|   |-- 
drivers-gpu-drm-imx-ipuv3-imx-ldb.c:error:_sel-directive-output-may-be-truncated-writing-bytes-into-a-region-of-size-between

✓ Fi.CI.BAT: success for drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup (rev3)
URL   : https://patchwork.freedesktop.org/series/132390/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14597 -> Patchwork_132390v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132390v3/index.html

Participating hosts (38 -> 32)
--

  Missing(6): bat-dg1-7 fi-snb-2520m fi-glk-j4005 fi-kbl-8809g bat-dg2-11 
bat-arls-3 

Known issues


  Here are the changes found in Patchwork_132390v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@i915_selftest@live@gem:
- bat-dg2-9:  [PASS][1] -> [ABORT][2] ([i915#10366])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14597/bat-dg2-9/igt@i915_selftest@l...@gem.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132390v3/bat-dg2-9/igt@i915_selftest@l...@gem.html

  
  [i915#10366]: https://gitlab.freedesktop.org/drm/intel/issues/10366


Build changes
-

  * Linux: CI_DRM_14597 -> Patchwork_132390v3

  CI-20190529: 20190529
  CI_DRM_14597: 64a20aacb61e4ce6d8a0b3dc6e4bff72e316ffa3 @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7810: 189483744e9ff56ea573e07a049c5365404c7ecb @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_132390v3: 64a20aacb61e4ce6d8a0b3dc6e4bff72e316ffa3 @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132390v3/index.html

✗ Fi.CI.SPARSE: warning for drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup (rev3)
URL   : https://patchwork.freedesktop.org/series/132390/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:116:1: warning: unreplaced symbol 'return'

✗ Fi.CI.CHECKPATCH: warning for drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: BXT/GLK per-lane vswing and PHY reg cleanup (rev3)
URL   : https://patchwork.freedesktop.org/series/132390/
State : warning

== Summary ==

Error: dim checkpatch failed
95fc61527473 drm/i915/dpio: Clean up bxt/glk PHY registers
e50c7e29b0ff drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glk
-:93: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'lane' - possible 
side-effects?
#93: FILE: drivers/gpu/drm/i915/i915_reg.h:558:
+#define _BXT_LANE_OFFSET(lane)   (((lane) >> 1) * 0x200 + \
+ ((lane) & 1) * 0x80)

total: 0 errors, 0 warnings, 1 checks, 171 lines checked
bdfcb64b6c69 drm/i915/dpio: Extract bxt_dpio_phy_regs.h
-:17: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#17: 
new file mode 100644

-:49: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'lane' - possible 
side-effects?
#49: FILE: drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h:28:
+#define _BXT_LANE_OFFSET(lane)   (((lane) >> 1) * 0x200 + \
+ ((lane) & 1) * 0x80)

total: 0 errors, 1 warnings, 1 checks, 589 lines checked
6357d153d841 drm/i915/dpio: Introdude bxt_ddi_phy_rmw_grp()
811248f59d6f drm/i915/dpio: Use intel_de_rmw() for BXT DPIO latency optim setup
b31079a95220 drm/i915/dpio: s/ddi/dpio/ for bxt/glk PHY stuff
-:462: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#462: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:80:
 }
+static inline void bxt_dpio_phy_set_signal_levels(struct intel_encoder 
*encoder,

-:467: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#467: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:84:
 }
+static inline void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum 
dpio_phy phy)

-:471: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#471: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:87:
 }
+static inline void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum 
dpio_phy phy)

-:476: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#476: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:90:
 }
+static inline bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,

-:483: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#483: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:95:
 }
+static inline bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,

-:489: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#489: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:100:
 }
+static inline u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count)

-:495: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#495: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:104:
 }
+static inline void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder 
*encoder,

-:500: CHECK:LINE_SPACING: Please use a blank line after 
function/struct/union/enum declarations
#500: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:108:
 }
+static inline u8 bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder 
*encoder)

total: 0 errors, 0 warnings, 8 checks, 444 lines checked
2fd0c9c5ec0f drm/i915/dpio: Program bxt/glk PHY TX registers per-lane
0a53f6553a0d drm/i915: Enable per-lane DP drive settings for bxt/glk

✓ Fi.CI.BAT: success for drm/i915/hwmon: Get rid of devm (rev6)

[Patchwork]

== Series Details ==

Series: drm/i915/hwmon: Get rid of devm (rev6)
URL   : https://patchwork.freedesktop.org/series/132400/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14596 -> Patchwork_132400v6


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/index.html

Participating hosts (37 -> 37)
--

  Additional (5): bat-kbl-2 fi-apl-guc bat-jsl-1 bat-arls-2 bat-mtlp-6 
  Missing(5): fi-bsw-n3050 fi-snb-2520m fi-cfl-8109u fi-kbl-8809g 
bat-dg2-11 

Known issues


  Here are the changes found in Patchwork_132400v6 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-jsl-1:  NOTRUN -> [SKIP][1] ([i915#9318])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html
- bat-mtlp-6: NOTRUN -> [SKIP][2] ([i915#9318])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-mtlp-6/igt@debugfs_t...@basic-hwmon.html
- bat-arls-2: NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-arls-2/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- bat-kbl-2:  NOTRUN -> [SKIP][4] ([i915#1849])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-kbl-2/igt@fb...@info.html
- bat-mtlp-6: NOTRUN -> [SKIP][5] ([i915#1849] / [i915#2582])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-mtlp-6/igt@fb...@info.html

  * igt@fbdev@write:
- bat-mtlp-6: NOTRUN -> [SKIP][6] ([i915#2582]) +3 other tests skip
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-mtlp-6/igt@fb...@write.html

  * igt@gem_huc_copy@huc-copy:
- bat-jsl-1:  NOTRUN -> [SKIP][7] ([i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-jsl-1/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/fi-apl-guc/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2:  NOTRUN -> [SKIP][9] +39 other tests skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- bat-mtlp-6: NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html
- bat-arls-2: NOTRUN -> [SKIP][11] ([i915#10213]) +3 other tests 
skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html
- bat-jsl-1:  NOTRUN -> [SKIP][12] ([i915#4613]) +3 other tests skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-jsl-1/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-arls-2: NOTRUN -> [SKIP][13] ([i915#4083])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-arls-2/igt@gem_m...@basic.html
- bat-mtlp-6: NOTRUN -> [SKIP][14] ([i915#4083])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-mtlp-6/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-arls-2: NOTRUN -> [SKIP][15] ([i915#10196] / [i915#4077]) +2 
other tests skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-arls-2/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-arls-2: NOTRUN -> [SKIP][16] ([i915#10197] / [i915#10211] / 
[i915#4079])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-arls-2/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_blits@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][17] ([i915#4077]) +2 other tests skip
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-mtlp-6/igt@gem_tiled_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-mtlp-6: NOTRUN -> [SKIP][18] ([i915#4079]) +1 other test skip
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-mtlp-6/igt@gem_tiled_pread_basic.html
- bat-arls-2: NOTRUN -> [SKIP][19] ([i915#10206] / [i915#4079])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-arls-2/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-arls-2: NOTRUN -> [SKIP][20] ([i915#10209])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v6/bat-arls-2/igt@i915_pm_...@basic-api.html
- bat-mtlp-6: NOTRUN -> [SKIP][21] ([i915#6621])
   [21]: 

✓ Fi.CI.BAT: success for drm/i915/dp: Few MTL/DSC and a UHBR monitor fix (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Few MTL/DSC and a UHBR monitor fix (rev4)
URL   : https://patchwork.freedesktop.org/series/131386/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14596 -> Patchwork_131386v4


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/index.html

Participating hosts (37 -> 39)
--

  Additional (7): fi-kbl-7567u bat-kbl-2 bat-mtlp-6 fi-apl-guc bat-jsl-1 
bat-arls-2 bat-arls-3 
  Missing(5): fi-bsw-n3050 fi-snb-2520m fi-cfl-8109u fi-kbl-8809g 
bat-dg2-11 

Known issues


  Here are the changes found in Patchwork_131386v4 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-jsl-1:  NOTRUN -> [SKIP][1] ([i915#9318])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-jsl-1/igt@debugfs_t...@basic-hwmon.html
- bat-arls-3: NOTRUN -> [SKIP][2] ([i915#9318])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-arls-3/igt@debugfs_t...@basic-hwmon.html
- bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#9318])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-mtlp-6/igt@debugfs_t...@basic-hwmon.html
- bat-arls-2: NOTRUN -> [SKIP][4] ([i915#9318])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-arls-2/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- bat-kbl-2:  NOTRUN -> [SKIP][5] ([i915#1849])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-kbl-2/igt@fb...@info.html
- bat-mtlp-6: NOTRUN -> [SKIP][6] ([i915#1849] / [i915#2582])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-mtlp-6/igt@fb...@info.html

  * igt@fbdev@write:
- bat-mtlp-6: NOTRUN -> [SKIP][7] ([i915#2582]) +3 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-mtlp-6/igt@fb...@write.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-7567u:   NOTRUN -> [SKIP][8] ([i915#2190])
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/fi-kbl-7567u/igt@gem_huc_c...@huc-copy.html
- bat-jsl-1:  NOTRUN -> [SKIP][9] ([i915#2190])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-jsl-1/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-apl-guc: NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/fi-apl-guc/igt@gem_lmem_swapp...@basic.html
- fi-kbl-7567u:   NOTRUN -> [SKIP][11] ([i915#4613]) +3 other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/fi-kbl-7567u/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-9:  [PASS][12] -> [FAIL][13] ([i915#10378])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14596/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2:  NOTRUN -> [SKIP][14] +39 other tests skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html
- bat-arls-3: NOTRUN -> [SKIP][15] ([i915#10213]) +3 other tests 
skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-arls-3/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- bat-mtlp-6: NOTRUN -> [SKIP][16] ([i915#4613]) +3 other tests skip
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html
- bat-arls-2: NOTRUN -> [SKIP][17] ([i915#10213]) +3 other tests 
skip
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html
- bat-jsl-1:  NOTRUN -> [SKIP][18] ([i915#4613]) +3 other tests skip
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-jsl-1/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-arls-2: NOTRUN -> [SKIP][19] ([i915#4083])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-arls-2/igt@gem_m...@basic.html
- bat-arls-3: NOTRUN -> [SKIP][20] ([i915#4083])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-arls-3/igt@gem_m...@basic.html
- bat-mtlp-6: NOTRUN -> [SKIP][21] ([i915#4083])
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131386v4/bat-mtlp-6/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-arls-2: NOTRUN -> [SKIP][22] ([i915#10196] / 

✗ Fi.CI.SPARSE: warning for drm/i915/dp: Few MTL/DSC and a UHBR monitor fix (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Few MTL/DSC and a UHBR monitor fix (rev4)
URL   : https://patchwork.freedesktop.org/series/131386/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: Few MTL/DSC and a UHBR monitor fix (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Few MTL/DSC and a UHBR monitor fix (rev4)
URL   : https://patchwork.freedesktop.org/series/131386/
State : warning

== Summary ==

Error: dim checkpatch failed
8b46862b3906 drm/i915/dp: Fix DSC line buffer depth programming
0f942ddfee52 drm/i915/dp_mst: Fix symbol clock when calculating the DSC DPT bpp 
limit
7b25a2826ce8 drm/i915/dp_mst: Fix BW limit check when calculating DSC DPT bpp
ae7078c79b46 drm/i915/dp_mst: Account for channel coding efficiency in the DSC 
DPT bpp limit
e216d859bd53 drm/i915/dp_mst: Account with the DSC DPT bpp limit on MTL
85c045743de7 drm/i915/dp_mst: Sanitize calculating the DSC DPT bpp limit
ad1f327b97b2 drm/dp: Add drm_dp_128b132b_supported()
6f14d19a285d drm/dp_mst: Factor out drm_dp_mst_port_is_logical()
6b87d351ae3a drm/dp_mst: Add drm_dp_mst_aux_for_parent()
a9d4d83cb2e4 drm/i915/dp_mst: Make HBLANK expansion quirk work for logical ports
210f94e07d2b drm/i915/dp_mst: Enable HBLANK expansion quirk for UHBR rates
-:39: WARNING:LONG_LINE_COMMENT: line length of 109 exceeds 100 columns
#39: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2284:
+   /* MediaTek panels (at least in U3224KBA) require DSC for modes with a 
short HBLANK on UHBR links. */

-:40: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#40: FILE: drivers/gpu/drm/display/drm_dp_helper.c:2285:
+   { OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, 
BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },

total: 0 errors, 2 warnings, 0 checks, 55 lines checked

Re: [PATCH i-g-t v3] lib/kunit: Read results from debugfs

[Janusz Krzysztofik]

On Wednesday, 17 April 2024 11:37:55 CEST Kamil Konieczny wrote:
> Hi Janusz,
> On 2024-04-15 at 19:31:59 +0200, Janusz Krzysztofik wrote:
> > KUnit can provide KTAP reports from test modules via debugfs files, one
> > per test suite.  Using that source of test results instead of extracting
> > them from dmesg, where they may be interleaved with other kernel messages,
> > seems more easy to handle and less error prone.  Switch to it.
> > 
> > If KUnit debugfs support is found not configured then fall back to legacy
> > processing path.
> > 
> > v3: Try to open KUnit debugfs directory before applying KUnit filters we
> > use for test case listing, otherwise those skip-all filters applied
> > can break legacy path we may enter on missing KUnit debugfs support
> > (detected by Kamil).
> > v2: Check validity of debugfs argument before calling kunit_get_tests()
> > (Kamil),
> >   - replace multiple openat() + fdopen/fdopendir(), each followed by an
> > error check, with less expensive fopen/opendir() of file/dir pathname
> > components concatenated to a local buffer, protected from buffer
> > overflow or truncation with a single check for enough buffer space
> > (Lucas),
> >   - avoid confusing 'if' statement condition (Lucas).
> > 
> > Signed-off-by: Janusz Krzysztofik 
> > Cc: Kamil Konieczny 
> > Reviewed-by: Lucas De Marchi 
> 
> Thank you for fixing legacy path, it works now.
> With this,
> 
> Reviewed-by: Kamil Konieczny 

Thank you Kamil, pushed.

Janusz

> 
> > ---
> > @Lucas: I've assumed your R-b still applies, I hope you don't mind.
> > 
> >  lib/igt_kmod.c | 129 +++--
> >  1 file changed, 93 insertions(+), 36 deletions(-)
> > 
> > diff --git a/lib/igt_kmod.c b/lib/igt_kmod.c
> > index 6659c27eba..33f059199f 100644
> > --- a/lib/igt_kmod.c
> > +++ b/lib/igt_kmod.c
> > @@ -28,6 +28,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -39,6 +40,7 @@
> >  
> >  #include "igt_aux.h"
> >  #include "igt_core.h"
> > +#include "igt_debugfs.h"
> >  #include "igt_kmod.h"
> >  #include "igt_ktap.h"
> >  #include "igt_sysfs.h"
> > @@ -864,6 +866,19 @@ static int open_parameters(const char *module_name)
> > return open(path, O_RDONLY);
> >  }
> >  
> > +static void kunit_debugfs_path(char *kunit_path)
> > +{
> > +   const char *debugfs_path = igt_debugfs_mount();
> > +
> > +   if (igt_debug_on(!debugfs_path))
> > +   return;
> > +
> > +   if (igt_debug_on(strlen(debugfs_path) + strlen("/kunit/") >= PATH_MAX))
> > +   return;
> > +
> > +   strcpy(stpcpy(kunit_path, debugfs_path), "/kunit/");
> > +}
> > +
> >  static bool kunit_set_filtering(const char *filter_glob, const char 
> > *filter,
> > const char *filter_action)
> >  {
> > @@ -1071,21 +1086,41 @@ static void kunit_results_free(struct igt_list_head 
> > *results,
> > free(*suite_name);
> >  }
> >  
> > -static int kunit_get_results(struct igt_list_head *results, int kmsg_fd,
> > -struct igt_ktap_results **ktap)
> > +static int kunit_get_results(struct igt_list_head *results, const char 
> > *debugfs_path,
> > +const char *suite, struct igt_ktap_results **ktap)
> >  {
> > +   char results_path[PATH_MAX];
> > +   FILE *results_stream;
> > +   char *buf = NULL;
> > +   size_t size = 0;
> > +   ssize_t len;
> > int err;
> >  
> > +   if (igt_debug_on(strlen(debugfs_path) + strlen(suite) + 
> > strlen("/results") >= PATH_MAX))
> > +   return -ENOSPC;
> > +
> > +   strcpy(stpcpy(stpcpy(results_path, debugfs_path), suite), "/results");
> > +   results_stream = fopen(results_path, "r");
> > +   if (igt_debug_on(!results_stream))
> > +   return -errno;
> > +
> > *ktap = igt_ktap_alloc(results);
> > -   if (igt_debug_on(!*ktap))
> > -   return -ENOMEM;
> > +   if (igt_debug_on(!*ktap)) {
> > +   err = -ENOMEM;
> > +   goto out_fclose;
> > +   }
> >  
> > -   do
> > -   igt_debug_on((err = kunit_kmsg_result_get(results, NULL, 
> > kmsg_fd, *ktap),
> > - err && err != -EINPROGRESS));
> > -   while (err == -EINPROGRESS);
> > +   while (len = getline(, , results_stream), len > 0) {
> > +   err = igt_ktap_parse(buf, *ktap);
> > +   if (err != -EINPROGRESS)
> > +   break;
> > +   }
> > +
> > +   free(buf);
> >  
> > igt_ktap_free(ktap);
> > +out_fclose:
> > +   fclose(results_stream);
> >  
> > return err;
> >  }
> > @@ -1101,7 +1136,13 @@ static void __igt_kunit_legacy(struct igt_ktest *tst,
> > pthread_mutexattr_t attr;
> > IGT_LIST_HEAD(results);
> > unsigned long taints;
> > -   int ret;
> > +   int flags, ret;
> > +
> > +   igt_skip_on_f(tst->kmsg < 0, "Could not open /dev/kmsg\n");
> > +
> > +   igt_skip_on((flags = fcntl(tst->kmsg, F_GETFL, 0), flags < 0));
> > +   igt_skip_on_f(fcntl(tst->kmsg, 

Re: [PATCH i-g-t] i915/gem_mmap_offset: Partial mmap and munmap

[Kamil Konieczny]

Hi Andi,
On 2024-04-12 at 02:42:55 +0200, Andi Shyti wrote:
> From: Chris Wilson 
> 
> Based on a test case developed by Lionel Landwerlin, this exercises
> creation of partial mmaps using both direct methods of a partial mmap()
> (where the mmap() only covers a portion of the object) and
> munmap() to do the same.
> 
> Signed-off-by: Chris Wilson 
> Signed-off-by: Andi Shyti 
> ---
>  tests/intel/gem_mmap_offset.c | 84 +++
>  1 file changed, 84 insertions(+)
> 
> diff --git a/tests/intel/gem_mmap_offset.c b/tests/intel/gem_mmap_offset.c
> index 95d2158ca88f..0ba2f9591f85 100644
> --- a/tests/intel/gem_mmap_offset.c
> +++ b/tests/intel/gem_mmap_offset.c
> @@ -56,6 +56,8 @@
>   * SUBTEST: isolation
>   * SUBTEST: oob-read
>   * SUBTEST: open-flood
> + * SUBTEST: partial-mmap
> + * SUBTEST: partial-unmap
>   * SUBTEST: perf
>   * SUBTEST: pf-nonblock
>   * SUBTEST: ptrace
> @@ -874,6 +876,83 @@ static void blt_coherency(int i915)
>   igt_assert_f(compare_ok, "Problem with coherency, flush is too late\n");
>  }
>  
> +static void partial_mmap(int i915)
> +{
> + uint32_t handle;
> +
> + handle = gem_create(i915, SZ_2M);
> +
> + for_each_mmap_offset_type(i915, t) {
> + struct drm_i915_gem_mmap_offset arg = {
> + .handle = handle,
> + .flags = t->type,
> + };
> + uint32_t *ptr;
> +
> + if (mmap_offset_ioctl(i915, ))
> + continue;
> +
> + ptr = mmap(0, SZ_4K, PROT_WRITE, MAP_SHARED, i915, arg.offset);
> + if (ptr == MAP_FAILED)
> + continue;
> +
> + memset(ptr, 0xcc, SZ_4K);
> + munmap(ptr, SZ_4K);
> +
> + ptr = mmap(0, SZ_4K, PROT_READ, MAP_SHARED, i915, arg.offset + 
> SZ_2M - SZ_4K);
> + igt_assert(ptr != MAP_FAILED);
> +
> + for (uint32_t i = 0; i < SZ_4K / sizeof(uint32_t); i++)
> + igt_assert_eq_u32(ptr[i], 0);
> +
> + munmap(ptr, SZ_4K);
> + }
> +
> + gem_close(i915, handle);
> +}
> +
> +static void partial_unmap(int i915)
> +{
> + uint32_t handle;
> +
> + handle = gem_create(i915, SZ_2M);
> +
> + for_each_mmap_offset_type(i915, t) {
> + uint8_t *ptr_a, *ptr_b;
> +
> + /* mmap the same GEM BO twice */
> + ptr_a = __mmap_offset(i915, handle, 0, SZ_2M,
> + PROT_READ | PROT_WRITE,
> + t->type);
> + if (!ptr_a)
> + continue;
> +
> + ptr_b = __mmap_offset(i915, handle, 0, SZ_2M,
> + PROT_READ | PROT_WRITE,
> + t->type);
> + if (!ptr_b)
> + continue;

Nit here: before continue ptr_a should be unmaped.

Regards,
Kamil

> +
> + /* unmap the first mapping but the last 4k */
> + munmap(ptr_a, SZ_2M - SZ_4K);
> +
> + /* memset that remaining 4k with 0xcc */
> + memset(ptr_a + SZ_2M - SZ_4K, 0xcc, SZ_4K);
> +
> + /* memset the first page of the 2Mb with 0xdd */
> + memset(ptr_b, 0xdd, SZ_4K);
> +
> + for (uint32_t i = 0; i < SZ_4K; i++)
> + igt_assert_eq_u32(ptr_a[SZ_2M - SZ_4K + i], 0xcc);
> +
> + munmap(ptr_a + SZ_2M - SZ_4K, SZ_4K);
> + memset(ptr_b, 0, SZ_2M);
> + munmap(ptr_b, SZ_2M);
> + }
> +
> + gem_close(i915, handle);
> +}
> +
>  static int mmap_gtt_version(int i915)
>  {
>   int gtt_version = -1;
> @@ -931,6 +1010,11 @@ igt_main
>   igt_subtest_f("open-flood")
>   open_flood(i915, 20);
>  
> + igt_subtest_f("partial-mmap")
> + partial_mmap(i915);
> + igt_subtest_f("partial-unmap")
> + partial_unmap(i915);
> +
>   igt_subtest_with_dynamic("clear") {
>   for_each_memory_region(r, i915) {
>   igt_dynamic_f("%s", r->name)
> -- 
> 2.43.0
> 

Re: [RFC PATCH] drm/i915: Don't reset GuC before engine reset on full GT reset

[Nirmoy Das]

Hi John,

On 4/17/2024 2:37 AM, John Harrison wrote:

On 4/15/2024 09:44, Nirmoy Das wrote:

Currently intel_gt_reset() happens as follows:

reset_prepare() ---> Sends GDRST to GuC, GuC is in GS_MIA_IN_RESET
do_reset()
__intel_gt_reset()
    *_engine_reset_prepare() -->RESET_CTL expects running
    GuC
    *_reset_engines()
intel_gt_init_hw() --> GuC FW loading happens, GuC comes out of
GS_MIA_IN_RESET.

Fix the above flow so that GuC reset happens after all the
engines reset is done.

Cc: John Harrison 
Signed-off-by: Nirmoy Das 
---
  drivers/gpu/drm/i915/gt/intel_reset.c |  9 --
  drivers/gpu/drm/i915/gt/uc/intel_uc.c | 42 +--
  drivers/gpu/drm/i915/gt/uc/intel_uc.h |  1 +
  3 files changed, 41 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c 
b/drivers/gpu/drm/i915/gt/intel_reset.c

index c8e9aa41fdea..9ebd68ce0c22 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -879,8 +879,11 @@ static intel_engine_mask_t reset_prepare(struct 
intel_gt *gt)

  intel_engine_mask_t awake = 0;
  enum intel_engine_id id;
  -    /* For GuC mode, ensure submission is disabled before stopping 
ring */

-    intel_uc_reset_prepare(>uc);
+    /*
+ * For GuC mode, ensure submission is disabled before stopping 
ring.

+ * Don't reset the GuC a engine reset requires GuC to be running.
These two lines appear to be mutually exclusive unless there is a test 
for GuC submission being enabled, which I am not seeing. Note that 
"ensure submission is disabled" means "reset the GuC".



+ */
+    intel_uc_reset_prepare_without_guc_reset(>uc);
    for_each_engine(engine, gt, id) {
  if (intel_engine_pm_get_if_awake(engine))
@@ -1227,6 +1230,8 @@ void intel_gt_reset(struct intel_gt *gt,
    intel_overlay_reset(gt->i915);
  +    /* Now that all engines are clean, Reset the GuC */
+    intel_uc_reset_prepare(>uc);
  /*
   * Next we need to restore the context, but we don't use those
   * yet either...
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c 
b/drivers/gpu/drm/i915/gt/uc/intel_uc.c

index 7a63abf8f644..5feee4db2ccc 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -345,7 +345,7 @@ static void __uc_fini(struct intel_uc *uc)
  intel_guc_fini(>guc);
  }
  -static int __uc_sanitize(struct intel_uc *uc)
+static void __uc_sanitize_without_guc_reset(struct intel_uc *uc)
  {
  struct intel_guc *guc = >guc;
  struct intel_huc *huc = >huc;
@@ -354,7 +354,11 @@ static int __uc_sanitize(struct intel_uc *uc)
    intel_huc_sanitize(huc);
  intel_guc_sanitize(guc);
+}
This seems like an extremely bad idea. You are wiping out all the GuC 
communication structures on the host side while the GuC itself is 
still executing and using those same structures.


Is the failure when doing individual engine resets or when doing a 
full GT reset?


The failed test is doing "intel_gt_reset(gt, ALL_ENGINES, NULL)" so a 
full GT reset.





If the former, I think a better approach would be to just not reset 
GuC at all (or indeed any UC) if not using GuC submission. Although, 
looking at the code, I'm not seeing an engine only reset path that 
does nuke the UC layers?



Yes, intel_engine_reset() doesn't touch UC layer.



If it is the latter, 


This is the case here.


then how/why are individual engine resets happening in the middle of a 
full GT reset? Don't we just splat everything all at once? 


It seems we use __intel_gt_reset(engine->gt, engine_mask) to reset all 
or some engines.


Either way, it would be safer to split at the GT reset code layer 
rather than inside the UC layer. That is, when not using GuC 
submission, do the entire prepare/reset/init sequence of the UC layers 
as one 'atomic' operation either before the GT/engine reset or after 
it (or potentially both before and after?).


I think this should work. Let me try it out


Thanks,

Nirmoy




John.



  +static int __uc_sanitize(struct intel_uc *uc)
+{
+    __uc_sanitize_without_guc_reset(uc);
  return __intel_uc_reset_hw(uc);
  }
  @@ -593,13 +597,7 @@ static void __uc_fini_hw(struct intel_uc *uc)
  __uc_sanitize(uc);
  }
  -/**
- * intel_uc_reset_prepare - Prepare for reset
- * @uc: the intel_uc structure
- *
- * Preparing for full gpu reset.
- */
-void intel_uc_reset_prepare(struct intel_uc *uc)
+static void __intel_uc_reset_prepare(struct intel_uc *uc, bool 
reset_guc)

  {
  struct intel_guc *guc = >guc;
  @@ -617,9 +615,35 @@ void intel_uc_reset_prepare(struct intel_uc *uc)
  intel_guc_submission_reset_prepare(guc);
    sanitize:
-    __uc_sanitize(uc);
+    if (reset_guc)
+    __uc_sanitize(uc);
+    else
+    __uc_sanitize_without_guc_reset(uc);
  }
  +/**
+ * intel_uc_reset_prepare - Prepare for reset
+ * @uc: the intel_uc structure
+ *
+ * Preparing for full gpu reset.
+ */
+void 

Re: [REBASE 7/7] drm/edid: make drm_edid_are_equal() more convenient for its single user

[Jani Nikula]

On Wed, 17 Apr 2024, Thomas Zimmermann  wrote:
>> Many thanks! Just to double check, do you want me to move patch 5
>> earlier and squash patches 6&7?
>
> Your choice. Either is fine by me.

I jumped at the easy option and merged this as-is. :)

Thanks again,
Jani.



-- 
Jani Nikula, Intel

[PATCH v2 3/8] drm/i915/dpio: Extract bxt_dpio_phy_regs.h

[Ville Syrjala]

From: Ville Syrjälä 

Extract the BXT/GLK DPIO PHY register definitions into their own file.

v2: Adjust gvt accordingly

Reviewed-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 .../gpu/drm/i915/display/bxt_dpio_phy_regs.h  | 273 ++
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |   1 +
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |   1 +
 drivers/gpu/drm/i915/gvt/display.c|   1 +
 drivers/gpu/drm/i915/gvt/handlers.c   |   1 +
 drivers/gpu/drm/i915/gvt/mmio.c   |   1 +
 drivers/gpu/drm/i915/i915_reg.h   | 262 -
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   |   1 +
 8 files changed, 279 insertions(+), 262 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h

diff --git a/drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h 
b/drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
new file mode 100644
index ..275f4d9c3fb0
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/bxt_dpio_phy_regs.h
@@ -0,0 +1,273 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __BXT_DPIO_PHY_REGS_H__
+#define __BXT_DPIO_PHY_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+/* BXT PHY registers */
+#define _BXT_PHY0_BASE 0x6C000
+#define _BXT_PHY1_BASE 0x162000
+#define _BXT_PHY2_BASE 0x163000
+#define BXT_PHY_BASE(phy) \
+_PICK_EVEN_2RANGES(phy, 1, \
+   _BXT_PHY0_BASE, _BXT_PHY0_BASE, \
+   _BXT_PHY1_BASE, _BXT_PHY2_BASE)
+
+#define _BXT_PHY(phy, reg) \
+   _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
+
+#define _BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
+   (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
+(reg_ch1) - _BXT_PHY0_BASE))
+#define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) \
+   _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
+#define _BXT_LANE_OFFSET(lane)   (((lane) >> 1) * 0x200 + \
+ ((lane) & 1) * 0x80)
+#define _MMIO_BXT_PHY_CH_LN(phy, ch, lane, reg_ch0, reg_ch1) \
+   _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) + _BXT_LANE_OFFSET(lane))
+
+/* BXT PHY PLL registers */
+#define _PORT_PLL_A0x46074
+#define _PORT_PLL_B0x46078
+#define _PORT_PLL_C0x4607c
+#define   PORT_PLL_ENABLE  REG_BIT(31)
+#define   PORT_PLL_LOCKREG_BIT(30)
+#define   PORT_PLL_REF_SEL REG_BIT(27)
+#define   PORT_PLL_POWER_ENABLEREG_BIT(26)
+#define   PORT_PLL_POWER_STATE REG_BIT(25)
+#define BXT_PORT_PLL_ENABLE(port)  _MMIO_PORT(port, _PORT_PLL_A, 
_PORT_PLL_B)
+
+#define _PORT_PLL_EBB_0_A  0x162034
+#define _PORT_PLL_EBB_0_B  0x6C034
+#define _PORT_PLL_EBB_0_C  0x6C340
+#define   PORT_PLL_P1_MASK REG_GENMASK(15, 13)
+#define   PORT_PLL_P1(p1)  REG_FIELD_PREP(PORT_PLL_P1_MASK, (p1))
+#define   PORT_PLL_P2_MASK REG_GENMASK(12, 8)
+#define   PORT_PLL_P2(p2)  REG_FIELD_PREP(PORT_PLL_P2_MASK, (p2))
+#define BXT_PORT_PLL_EBB_0(phy, ch)_MMIO_BXT_PHY_CH(phy, ch, \
+_PORT_PLL_EBB_0_B, \
+_PORT_PLL_EBB_0_C)
+
+#define _PORT_PLL_EBB_4_A  0x162038
+#define _PORT_PLL_EBB_4_B  0x6C038
+#define _PORT_PLL_EBB_4_C  0x6C344
+#define   PORT_PLL_RECALIBRATE REG_BIT(14)
+#define   PORT_PLL_10BIT_CLK_ENABLEREG_BIT(13)
+#define BXT_PORT_PLL_EBB_4(phy, ch)_MMIO_BXT_PHY_CH(phy, ch, \
+_PORT_PLL_EBB_4_B, \
+_PORT_PLL_EBB_4_C)
+
+#define _PORT_PLL_0_A  0x162100
+#define _PORT_PLL_0_B  0x6C100
+#define _PORT_PLL_0_C  0x6C380
+/* PORT_PLL_0_A */
+#define   PORT_PLL_M2_INT_MASK REG_GENMASK(7, 0)
+#define   PORT_PLL_M2_INT(m2_int)  REG_FIELD_PREP(PORT_PLL_M2_INT_MASK, 
(m2_int))
+/* PORT_PLL_1_A */
+#define   PORT_PLL_N_MASK  REG_GENMASK(11, 8)
+#define   PORT_PLL_N(n)REG_FIELD_PREP(PORT_PLL_N_MASK, 
(n))
+/* PORT_PLL_2_A */
+#define   PORT_PLL_M2_FRAC_MASKREG_GENMASK(21, 0)
+#define   PORT_PLL_M2_FRAC(m2_frac)REG_FIELD_PREP(PORT_PLL_M2_FRAC_MASK, 
(m2_frac))
+/* PORT_PLL_3_A */
+#define   PORT_PLL_M2_FRAC_ENABLE  REG_BIT(16)
+/* PORT_PLL_6_A */
+#define   PORT_PLL_GAIN_CTL_MASK   REG_GENMASK(18, 16)
+#define   PORT_PLL_GAIN_CTL(x) REG_FIELD_PREP(PORT_PLL_GAIN_CTL_MASK, 
(x))
+#define   PORT_PLL_INT_COEFF_MASK  REG_GENMASK(12, 8)
+#define   PORT_PLL_INT_COEFF(x)
REG_FIELD_PREP(PORT_PLL_INT_COEFF_MASK, (x))
+#define   PORT_PLL_PROP_COEFF_MASK 

[PATCH v2 2/8] drm/i915/dpio: Add per-lane PHY TX register definitons for bxt/glk

[Ville Syrjala]

From: Ville Syrjälä 

Add consistent definitions for the per-lane PHY TX registers
on bxt/glk. The current situation is a slight mess with some
registers having a LN0 define, while others have a parametrized
per-lane definition.

v2: Adjust gvt accordingly

Reviewed-by: Jani Nikula 
Signed-off-by: Ville Syrjälä 
---
 drivers/gpu/drm/i915/display/intel_dpio_phy.c |  6 +--
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  2 +-
 drivers/gpu/drm/i915/gvt/handlers.c   |  6 +--
 drivers/gpu/drm/i915/i915_reg.h   | 38 +--
 drivers/gpu/drm/i915/intel_gvt_mmio_table.c   | 18 -
 5 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index d14e80ece8aa..50d6b412d652 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -294,13 +294,13 @@ void bxt_ddi_phy_set_signal_levels(struct intel_encoder 
*encoder,
val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val);
 
-   val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch));
+   val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN(phy, ch, 0));
val &= ~(MARGIN_000_MASK | UNIQ_TRANS_SCALE_MASK);
val |= MARGIN_000(trans->entries[level].bxt.margin) |
UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale);
intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val);
 
-   val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch));
+   val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, 0));
val &= ~SCALE_DCOMP_METHOD;
if (trans->entries[level].bxt.enable)
val |= SCALE_DCOMP_METHOD;
@@ -311,7 +311,7 @@ void bxt_ddi_phy_set_signal_levels(struct intel_encoder 
*encoder,
 
intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val);
 
-   val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch));
+   val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN(phy, ch, 0));
val &= ~DE_EMPHASIS_MASK;
val |= DE_EMPHASIS(trans->entries[level].bxt.deemphasis);
intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val);
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 9ff6c4cc2e4b..cc3acdafdbf8 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2071,7 +2071,7 @@ static void bxt_ddi_pll_enable(struct drm_i915_private 
*i915,
drm_err(>drm, "PLL %d not locked\n", port);
 
if (IS_GEMINILAKE(i915)) {
-   temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN0(phy, ch));
+   temp = intel_de_read(i915, BXT_PORT_TX_DW5_LN(phy, ch, 0));
temp |= DCC_DELAY_RANGE_2;
intel_de_write(i915, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
}
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c 
b/drivers/gpu/drm/i915/gvt/handlers.c
index efcb00472be2..d36092615ae3 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2763,15 +2763,15 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
 
MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,
NULL, bxt_pcs_dw12_grp_write);
-   MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH0), D_BXT,
+   MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT,
bxt_port_tx_dw3_read, NULL);
MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,
NULL, bxt_pcs_dw12_grp_write);
-   MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY0, DPIO_CH1), D_BXT,
+   MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT,
bxt_port_tx_dw3_read, NULL);
MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,
NULL, bxt_pcs_dw12_grp_write);
-   MMIO_DH(BXT_PORT_TX_DW3_LN0(DPIO_PHY1, DPIO_CH0), D_BXT,
+   MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT,
bxt_port_tx_dw3_read, NULL);
MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);
MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9701aad57e3a..261b520da399 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -555,6 +555,10 @@
 (reg_ch1) - _BXT_PHY0_BASE))
 #define _MMIO_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1)\
_MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1))
+#define _BXT_LANE_OFFSET(lane)   (((lane) >> 1) * 0x200 + \
+ ((lane) & 1) * 0x80)
+#define _MMIO_BXT_PHY_CH_LN(phy, ch, lane, reg_ch0, reg_ch1) \
+   _MMIO(_BXT_PHY_CH(phy, ch, reg_ch0, reg_ch1) + _BXT_LANE_OFFSET(lane))
 
 #define 

Re: [PATCH v4] drm/i915/hwmon: Get rid of devm

[Dixit, Ashutosh]

On Wed, 17 Apr 2024 01:28:48 -0700, Andi Shyti wrote:
>

Hi Andi,

> > @@ -839,16 +837,38 @@ void i915_hwmon_register(struct drm_i915_private 
> > *i915)
> > if (!hwm_gt_is_visible(ddat_gt, hwmon_energy, 
> > hwmon_energy_input, 0))
> > continue;
> >
> > -   hwmon_dev = devm_hwmon_device_register_with_info(dev, 
> > ddat_gt->name,
> > -ddat_gt,
> > -
> > _gt_chip_info,
> > -NULL);
> > -   if (!IS_ERR(hwmon_dev))
> > -   ddat_gt->hwmon_dev = hwmon_dev;
> > +   hwmon_dev = hwmon_device_register_with_info(dev, ddat_gt->name,
> > +   ddat_gt,
> > +   _gt_chip_info,
> > +   NULL);
> > +   if (IS_ERR(hwmon_dev))
> > +   goto err;
>
> here the logic is changing, though. Before we were not leaving if
> hwmon_device_register_with_info() was returning error.
>
> Is this wanted? And why isn't it described in the log?

Not sure if the previous logic was intentional or not, anyway I have
restored it in v5 (where I once again forgot to add "PATCH v5" to the
Subject but v5 is there in the version log :/).

Thanks.
--
Ashutosh

[PATCH] drm/i915/hwmon: Get rid of devm

[Ashutosh Dixit]

When both hwmon and hwmon drvdata (on which hwmon depends) are device
managed resources, the expectation, on device unbind, is that hwmon will be
released before drvdata. However, in i915 there are two separate code
paths, which both release either drvdata or hwmon and either can be
released before the other. These code paths (for device unbind) are as
follows (see also the bug referenced below):

Call Trace:
release_nodes+0x11/0x70
devres_release_group+0xb2/0x110
component_unbind_all+0x8d/0xa0
component_del+0xa5/0x140
intel_pxp_tee_component_fini+0x29/0x40 [i915]
intel_pxp_fini+0x33/0x80 [i915]
i915_driver_remove+0x4c/0x120 [i915]
i915_pci_remove+0x19/0x30 [i915]
pci_device_remove+0x32/0xa0
device_release_driver_internal+0x19c/0x200
unbind_store+0x9c/0xb0

and

Call Trace:
release_nodes+0x11/0x70
devres_release_all+0x8a/0xc0
device_unbind_cleanup+0x9/0x70
device_release_driver_internal+0x1c1/0x200
unbind_store+0x9c/0xb0

This means that in i915, if use devm, we cannot gurantee that hwmon will
always be released before drvdata. Which means that we have a uaf if hwmon
sysfs is accessed when drvdata has been released but hwmon hasn't.

The only way out of this seems to be do get rid of devm_ and release/free
everything explicitly during device unbind.

v2: Change commit message and other minor code changes
v3: Cleanup from i915_hwmon_register on error (Armin Wolf)
v4: Eliminate potential static analyzer warning (Rodrigo)
Eliminate fetch_and_zero (Jani)
v5: Restore previous logic for ddat_gt->hwmon_dev error return (Andi)

Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/10366
Reviewed-by: Rodrigo Vivi 
Signed-off-by: Ashutosh Dixit 
---
 drivers/gpu/drm/i915/i915_hwmon.c | 46 +--
 1 file changed, 32 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_hwmon.c 
b/drivers/gpu/drm/i915/i915_hwmon.c
index b758fd110c20..c0662a022f59 100644
--- a/drivers/gpu/drm/i915/i915_hwmon.c
+++ b/drivers/gpu/drm/i915/i915_hwmon.c
@@ -793,7 +793,7 @@ void i915_hwmon_register(struct drm_i915_private *i915)
if (!IS_DGFX(i915))
return;
 
-   hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL);
+   hwmon = kzalloc(sizeof(*hwmon), GFP_KERNEL);
if (!hwmon)
return;
 
@@ -819,14 +819,12 @@ void i915_hwmon_register(struct drm_i915_private *i915)
hwm_get_preregistration_info(i915);
 
/*  hwmon_dev points to device hwmon */
-   hwmon_dev = devm_hwmon_device_register_with_info(dev, ddat->name,
-ddat,
-_chip_info,
-hwm_groups);
-   if (IS_ERR(hwmon_dev)) {
-   i915->hwmon = NULL;
-   return;
-   }
+   hwmon_dev = hwmon_device_register_with_info(dev, ddat->name,
+   ddat,
+   _chip_info,
+   hwm_groups);
+   if (IS_ERR(hwmon_dev))
+   goto err;
 
ddat->hwmon_dev = hwmon_dev;
 
@@ -839,16 +837,36 @@ void i915_hwmon_register(struct drm_i915_private *i915)
if (!hwm_gt_is_visible(ddat_gt, hwmon_energy, 
hwmon_energy_input, 0))
continue;
 
-   hwmon_dev = devm_hwmon_device_register_with_info(dev, 
ddat_gt->name,
-ddat_gt,
-
_gt_chip_info,
-NULL);
+   hwmon_dev = hwmon_device_register_with_info(dev, ddat_gt->name,
+   ddat_gt,
+   _gt_chip_info,
+   NULL);
if (!IS_ERR(hwmon_dev))
ddat_gt->hwmon_dev = hwmon_dev;
}
+   return;
+err:
+   i915_hwmon_unregister(i915);
 }
 
 void i915_hwmon_unregister(struct drm_i915_private *i915)
 {
-   fetch_and_zero(>hwmon);
+   struct i915_hwmon *hwmon = i915->hwmon;
+   struct intel_gt *gt;
+   int i;
+
+   if (!hwmon)
+   return;
+
+   for_each_gt(gt, i915, i)
+   if (hwmon->ddat_gt[i].hwmon_dev)
+   hwmon_device_unregister(hwmon->ddat_gt[i].hwmon_dev);
+
+   if (hwmon->ddat.hwmon_dev)
+   hwmon_device_unregister(hwmon->ddat.hwmon_dev);
+
+   mutex_destroy(>hwmon_lock);
+
+   kfree(i915->hwmon);
+   i915->hwmon = NULL;
 }
-- 
2.41.0

✓ Fi.CI.BAT: success for drm/i915: better high level abstraction for display (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: better high level abstraction for display (rev3)
URL   : https://patchwork.freedesktop.org/series/130805/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14594 -> Patchwork_130805v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/index.html

Participating hosts (41 -> 36)
--

  Additional (1): fi-kbl-8809g 
  Missing(6): bat-kbl-2 fi-bsw-n3050 fi-snb-2520m fi-glk-j4005 fi-elk-e7500 
bat-dg2-11 

Known issues


  Here are the changes found in Patchwork_130805v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g:   NOTRUN -> [SKIP][1] ([i915#2190])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-8809g:   NOTRUN -> [SKIP][2] ([i915#4613]) +3 other tests skip
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-9:  [PASS][3] -> [FAIL][4] ([i915#10378])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14594/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html

  * igt@gem_lmem_swapping@verify-random:
- bat-arls-2: NOTRUN -> [SKIP][5] ([i915#10213]) +3 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html

  * igt@i915_pm_rps@basic-api:
- bat-arls-2: NOTRUN -> [SKIP][6] ([i915#10209])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/bat-arls-2/igt@i915_pm_...@basic-api.html

  * igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-arls-2: NOTRUN -> [SKIP][7] ([i915#10200])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/bat-arls-2/igt@kms_addfb_ba...@tile-pitch-mismatch.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-arls-2: NOTRUN -> [SKIP][8] ([i915#10202]) +1 other test skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/bat-arls-2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
- bat-arls-2: NOTRUN -> [SKIP][9] ([i915#9886])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/bat-arls-2/igt@kms_...@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-8809g:   NOTRUN -> [SKIP][10] +30 other tests skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/fi-kbl-8809g/igt@kms_force_connector_ba...@force-load-detect.html
- bat-arls-2: NOTRUN -> [SKIP][11] ([i915#10207])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/bat-arls-2/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_psr@psr-primary-mmap-gtt@edp-1:
- bat-arls-2: NOTRUN -> [SKIP][12] ([i915#10196] / [i915#4077] / 
[i915#9688])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/bat-arls-2/igt@kms_psr@psr-primary-mmap-...@edp-1.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-arls-2: NOTRUN -> [SKIP][13] ([i915#10208] / [i915#8809])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/bat-arls-2/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-mmap:
- bat-arls-2: NOTRUN -> [SKIP][14] ([i915#10196] / [i915#3708] / 
[i915#4077]) +1 other test skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/bat-arls-2/igt@prime_v...@basic-fence-mmap.html

  * igt@prime_vgem@basic-fence-read:
- bat-arls-2: NOTRUN -> [SKIP][15] ([i915#10212] / [i915#3708])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/bat-arls-2/igt@prime_v...@basic-fence-read.html

  * igt@prime_vgem@basic-read:
- bat-arls-2: NOTRUN -> [SKIP][16] ([i915#10214] / [i915#3708])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/bat-arls-2/igt@prime_v...@basic-read.html

  * igt@prime_vgem@basic-write:
- bat-arls-2: NOTRUN -> [SKIP][17] ([i915#10216] / [i915#3708])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/bat-arls-2/igt@prime_v...@basic-write.html

  
 Possible fixes 

  * igt@kms_addfb_basic@invalid-get-prop-any:
- bat-arls-2: [ABORT][18] -> [PASS][19]
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14594/bat-arls-2/igt@kms_addfb_ba...@invalid-get-prop-any.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_130805v3/bat-arls-2/igt@kms_addfb_ba...@invalid-get-prop-any.html

  
  

Re: [PATCH v4 9/9] drm/i915/dmc: use struct intel_display more

[Rodrigo Vivi]

On Wed, Apr 17, 2024 at 04:02:47PM +0300, Jani Nikula wrote:
> Now that the intel_de_ functions and DISPLAY_VER() accept struct
> intel_display *, use it more.
> 
> Cc: Luca Coelho 
> Signed-off-by: Jani Nikula 

Reviewed-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/display/intel_dmc_wl.c | 24 +
>  1 file changed, 10 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c 
> b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> index e79c45e36722..d9864b9cc429 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> @@ -66,8 +66,8 @@ static void intel_dmc_wl_work(struct work_struct *work)
>  {
>   struct intel_dmc_wl *wl =
>   container_of(work, struct intel_dmc_wl, work.work);
> - struct drm_i915_private *i915 =
> - container_of(wl, struct drm_i915_private, display.wl);
> + struct intel_display *display =
> + container_of(wl, struct intel_display, wl);
>   unsigned long flags;
>  
>   spin_lock_irqsave(>lock, flags);
> @@ -76,9 +76,9 @@ static void intel_dmc_wl_work(struct work_struct *work)
>   if (!refcount_read(>refcount))
>   goto out_unlock;
>  
> - __intel_de_rmw_nowl(i915, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0);
> + __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 
> 0);
>  
> - if (__intel_de_wait_for_register_nowl(i915, DMC_WAKELOCK1_CTL,
> + if (__intel_de_wait_for_register_nowl(display, DMC_WAKELOCK1_CTL,
> DMC_WAKELOCK_CTL_ACK, 0,
> DMC_WAKELOCK_CTL_TIMEOUT)) {
>   WARN_RATELIMIT(1, "DMC wakelock release timed out");
> @@ -111,7 +111,7 @@ static bool __intel_dmc_wl_supported(struct intel_display 
> *display)
>  {
>   struct drm_i915_private *i915 = to_i915(display->drm);
>  
> - if (DISPLAY_VER(i915) < 20 ||
> + if (DISPLAY_VER(display) < 20 ||
>   !intel_dmc_has_payload(i915) ||
>   !display->params.enable_dmc_wl)
>   return false;
> @@ -121,11 +121,10 @@ static bool __intel_dmc_wl_supported(struct 
> intel_display *display)
>  
>  void intel_dmc_wl_init(struct intel_display *display)
>  {
> - struct drm_i915_private *i915 = to_i915(display->drm);
>   struct intel_dmc_wl *wl = >wl;
>  
>   /* don't call __intel_dmc_wl_supported(), DMC is not loaded yet */
> - if (DISPLAY_VER(i915) < 20 || !display->params.enable_dmc_wl)
> + if (DISPLAY_VER(display) < 20 || !display->params.enable_dmc_wl)
>   return;
>  
>   INIT_DELAYED_WORK(>work, intel_dmc_wl_work);
> @@ -135,7 +134,6 @@ void intel_dmc_wl_init(struct intel_display *display)
>  
>  void intel_dmc_wl_enable(struct intel_display *display)
>  {
> - struct drm_i915_private *i915 = to_i915(display->drm);
>   struct intel_dmc_wl *wl = >wl;
>   unsigned long flags;
>  
> @@ -152,7 +150,7 @@ void intel_dmc_wl_enable(struct intel_display *display)
>* wakelock, because we're just enabling it, so call the
>* non-locking version directly here.
>*/
> - __intel_de_rmw_nowl(i915, DMC_WAKELOCK_CFG, 0, DMC_WAKELOCK_CFG_ENABLE);
> + __intel_de_rmw_nowl(display, DMC_WAKELOCK_CFG, 0, 
> DMC_WAKELOCK_CFG_ENABLE);
>  
>   wl->enabled = true;
>   wl->taken = false;
> @@ -163,7 +161,6 @@ void intel_dmc_wl_enable(struct intel_display *display)
>  
>  void intel_dmc_wl_disable(struct intel_display *display)
>  {
> - struct drm_i915_private *i915 = to_i915(display->drm);
>   struct intel_dmc_wl *wl = >wl;
>   unsigned long flags;
>  
> @@ -178,7 +175,7 @@ void intel_dmc_wl_disable(struct intel_display *display)
>   goto out_unlock;
>  
>   /* Disable wakelock in DMC */
> - __intel_de_rmw_nowl(i915, DMC_WAKELOCK_CFG, DMC_WAKELOCK_CFG_ENABLE, 0);
> + __intel_de_rmw_nowl(display, DMC_WAKELOCK_CFG, DMC_WAKELOCK_CFG_ENABLE, 
> 0);
>  
>   refcount_set(>refcount, 0);
>   wl->enabled = false;
> @@ -190,7 +187,6 @@ void intel_dmc_wl_disable(struct intel_display *display)
>  
>  void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg)
>  {
> - struct drm_i915_private *i915 = to_i915(display->drm);
>   struct intel_dmc_wl *wl = >wl;
>   unsigned long flags;
>  
> @@ -219,10 +215,10 @@ void intel_dmc_wl_get(struct intel_display *display, 
> i915_reg_t reg)
>* run yet.
>*/
>   if (!wl->taken) {
> - __intel_de_rmw_nowl(i915, DMC_WAKELOCK1_CTL, 0,
> + __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, 0,
>   DMC_WAKELOCK_CTL_REQ);
>  
> - if (__intel_de_wait_for_register_nowl(i915, DMC_WAKELOCK1_CTL,
> + if (__intel_de_wait_for_register_nowl(display, 
> DMC_WAKELOCK1_CTL,
> DMC_WAKELOCK_CTL_ACK,
>

Re: [PATCH v4 7/9] drm/i915/dmc: convert dmc wakelock interface to struct intel_display

[Rodrigo Vivi]

On Wed, Apr 17, 2024 at 04:02:45PM +0300, Jani Nikula wrote:
> Convert the dmc wakelock interface to struct intel_display instead of
> struct drm_i915_private. We'll want to convert the intel_de interfaces,
> and there's a bit of coupling between the two, so start here.
> 
> Cc: Luca Coelho 
> Signed-off-by: Jani Nikula 

Reviewed-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/display/intel_de.h   | 40 
>  .../drm/i915/display/intel_display_driver.c   |  2 +-
>  .../i915/display/intel_display_power_well.c   |  6 +--
>  drivers/gpu/drm/i915/display/intel_dmc.c  |  4 +-
>  drivers/gpu/drm/i915/display/intel_dmc_wl.c   | 48 +++
>  drivers/gpu/drm/i915/display/intel_dmc_wl.h   | 12 ++---
>  6 files changed, 59 insertions(+), 53 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h 
> b/drivers/gpu/drm/i915/display/intel_de.h
> index 4b51388c6041..15440058ad2a 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -15,11 +15,11 @@ intel_de_read(struct drm_i915_private *i915, i915_reg_t 
> reg)
>  {
>   u32 val;
>  
> - intel_dmc_wl_get(i915, reg);
> + intel_dmc_wl_get(>display, reg);
>  
>   val = intel_uncore_read(>uncore, reg);
>  
> - intel_dmc_wl_put(i915, reg);
> + intel_dmc_wl_put(>display, reg);
>  
>   return val;
>  }
> @@ -29,11 +29,11 @@ intel_de_read8(struct drm_i915_private *i915, i915_reg_t 
> reg)
>  {
>   u8 val;
>  
> - intel_dmc_wl_get(i915, reg);
> + intel_dmc_wl_get(>display, reg);
>  
>   val = intel_uncore_read8(>uncore, reg);
>  
> - intel_dmc_wl_put(i915, reg);
> + intel_dmc_wl_put(>display, reg);
>  
>   return val;
>  }
> @@ -44,13 +44,13 @@ intel_de_read64_2x32(struct drm_i915_private *i915,
>  {
>   u64 val;
>  
> - intel_dmc_wl_get(i915, lower_reg);
> - intel_dmc_wl_get(i915, upper_reg);
> + intel_dmc_wl_get(>display, lower_reg);
> + intel_dmc_wl_get(>display, upper_reg);
>  
>   val = intel_uncore_read64_2x32(>uncore, lower_reg, upper_reg);
>  
> - intel_dmc_wl_put(i915, upper_reg);
> - intel_dmc_wl_put(i915, lower_reg);
> + intel_dmc_wl_put(>display, upper_reg);
> + intel_dmc_wl_put(>display, lower_reg);
>  
>   return val;
>  }
> @@ -58,21 +58,21 @@ intel_de_read64_2x32(struct drm_i915_private *i915,
>  static inline void
>  intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
>  {
> - intel_dmc_wl_get(i915, reg);
> + intel_dmc_wl_get(>display, reg);
>  
>   intel_uncore_posting_read(>uncore, reg);
>  
> - intel_dmc_wl_put(i915, reg);
> + intel_dmc_wl_put(>display, reg);
>  }
>  
>  static inline void
>  intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
>  {
> - intel_dmc_wl_get(i915, reg);
> + intel_dmc_wl_get(>display, reg);
>  
>   intel_uncore_write(>uncore, reg, val);
>  
> - intel_dmc_wl_put(i915, reg);
> + intel_dmc_wl_put(>display, reg);
>  }
>  
>  static inline u32
> @@ -87,11 +87,11 @@ intel_de_rmw(struct drm_i915_private *i915, i915_reg_t 
> reg, u32 clear, u32 set)
>  {
>   u32 val;
>  
> - intel_dmc_wl_get(i915, reg);
> + intel_dmc_wl_get(>display, reg);
>  
>   val = __intel_de_rmw_nowl(i915, reg, clear, set);
>  
> - intel_dmc_wl_put(i915, reg);
> + intel_dmc_wl_put(>display, reg);
>  
>   return val;
>  }
> @@ -110,11 +110,11 @@ intel_de_wait(struct drm_i915_private *i915, i915_reg_t 
> reg,
>  {
>   int ret;
>  
> - intel_dmc_wl_get(i915, reg);
> + intel_dmc_wl_get(>display, reg);
>  
>   ret = __intel_de_wait_for_register_nowl(i915, reg, mask, value, 
> timeout);
>  
> - intel_dmc_wl_put(i915, reg);
> + intel_dmc_wl_put(>display, reg);
>  
>   return ret;
>  }
> @@ -125,11 +125,11 @@ intel_de_wait_fw(struct drm_i915_private *i915, 
> i915_reg_t reg,
>  {
>   int ret;
>  
> - intel_dmc_wl_get(i915, reg);
> + intel_dmc_wl_get(>display, reg);
>  
>   ret = intel_wait_for_register_fw(>uncore, reg, mask, value, 
> timeout);
>  
> - intel_dmc_wl_put(i915, reg);
> + intel_dmc_wl_put(>display, reg);
>  
>   return ret;
>  }
> @@ -142,12 +142,12 @@ intel_de_wait_custom(struct drm_i915_private *i915, 
> i915_reg_t reg,
>  {
>   int ret;
>  
> - intel_dmc_wl_get(i915, reg);
> + intel_dmc_wl_get(>display, reg);
>  
>   ret = __intel_wait_for_register(>uncore, reg, mask, value,
>   fast_timeout_us, slow_timeout_ms, 
> out_value);
>  
> - intel_dmc_wl_put(i915, reg);
> + intel_dmc_wl_put(>display, reg);
>  
>   return ret;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c 
> b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 4f112a69dea8..1b24339e4ab6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -198,7 +198,7 @@ void 

✗ Fi.CI.SPARSE: warning for drm/i915: better high level abstraction for display (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: better high level abstraction for display (rev3)
URL   : https://patchwork.freedesktop.org/series/130805/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✗ Fi.CI.CHECKPATCH: warning for drm/i915: better high level abstraction for display (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915: better high level abstraction for display (rev3)
URL   : https://patchwork.freedesktop.org/series/130805/
State : warning

== Summary ==

Error: dim checkpatch failed
36717544b8f3 drm/i915/display: add intel_display -> drm_device backpointer
1c60fd31e388 drm/i915/display: add generic to_intel_display() macro
-:54: ERROR:SPACING: spaces required around that ':' (ctx:VxW)
#54: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:2223:
+   struct type: __##type##_to_intel_display((struct type *)(p))
   ^

-:57: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#57: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:2226:
+#define to_intel_display(p)\
+   _Generic(*p,\
+__assoc(drm_device, p),\
+__assoc(intel_connector, p),   \
+__assoc(intel_crtc, p),\
+__assoc(intel_crtc_state, p),  \
+__assoc(intel_digital_port, p),\
+__assoc(intel_dp, p),  \
+__assoc(intel_encoder, p), \
+__assoc(intel_hdmi, p))

-:57: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'p' may be better as '(p)' to 
avoid precedence issues
#57: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:2226:
+#define to_intel_display(p)\
+   _Generic(*p,\
+__assoc(drm_device, p),\
+__assoc(intel_connector, p),   \
+__assoc(intel_crtc, p),\
+__assoc(intel_crtc_state, p),  \
+__assoc(intel_digital_port, p),\
+__assoc(intel_dp, p),  \
+__assoc(intel_encoder, p), \
+__assoc(intel_hdmi, p))

-:58: CHECK:CAMELCASE: Avoid CamelCase: <_Generic>
#58: FILE: drivers/gpu/drm/i915/display/intel_display_types.h:2227:
+   _Generic(*p,\

total: 1 errors, 0 warnings, 3 checks, 41 lines checked
333a596d24fe drm/i915: add generic __to_intel_display()
-:20: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does 
MAINTAINERS need updating?
#20: 
new file mode 100644

-:39: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#39: FILE: drivers/gpu/drm/i915/display/intel_display_conversion.h:15:
+#define __to_intel_display(p)  \
+   _Generic(p, \
+const struct drm_i915_private *: (&((const struct 
drm_i915_private *)(p))->display), \
+struct drm_i915_private *: (&((struct drm_i915_private 
*)(p))->display), \
+const struct intel_display *: (p), \
+struct intel_display *: (p))

-:40: CHECK:CAMELCASE: Avoid CamelCase: <_Generic>
#40: FILE: drivers/gpu/drm/i915/display/intel_display_conversion.h:16:
+   _Generic(p, \

-:41: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#41: FILE: drivers/gpu/drm/i915/display/intel_display_conversion.h:17:
+const struct drm_i915_private *: (&((const struct 
drm_i915_private *)(p))->display), \

-:41: CHECK:SPACING: spaces preferred around that '*' (ctx:WxO)
#41: FILE: drivers/gpu/drm/i915/display/intel_display_conversion.h:17:
+const struct drm_i915_private *: (&((const struct 
drm_i915_private *)(p))->display), \
   ^

-:41: ERROR:SPACING: spaces required around that ':' (ctx:OxW)
#41: FILE: drivers/gpu/drm/i915/display/intel_display_conversion.h:17:
+const struct drm_i915_private *: (&((const struct 
drm_i915_private *)(p))->display), \
^

-:42: CHECK:SPACING: spaces preferred around that '*' (ctx:WxO)
#42: FILE: drivers/gpu/drm/i915/display/intel_display_conversion.h:18:
+struct drm_i915_private *: (&((struct drm_i915_private 
*)(p))->display), \
 ^

-:42: ERROR:SPACING: spaces required around that ':' (ctx:OxW)
#42: FILE: drivers/gpu/drm/i915/display/intel_display_conversion.h:18:
+struct drm_i915_private *: (&((struct drm_i915_private 
*)(p))->display), \
  ^

-:43: CHECK:SPACING: spaces preferred around that '*' (ctx:WxO)
#43: FILE: drivers/gpu/drm/i915/display/intel_display_conversion.h:19:
+const struct intel_display *: (p), \
^

-:43: ERROR:SPACING: spaces required around that ':' (ctx:OxW)
#43: FILE: 

[PATCH v3 11/11] drm/i915/dp_mst: Enable HBLANK expansion quirk for UHBR rates

[Imre Deak]

Enabling the 5k@60Hz uncompressed mode on the MediaTek/Dell U3224KBA
monitor results in a blank screen, at least on MTL platforms on UHBR
link rates with some (<30) uncompressed bpp values. Enabling compression
fixes the problem, so do that for now. Windows enables DSC always if the
sink supports it and forcing it to enable the mode without compression
leads to the same problem above (which suggests a panel issue with
uncompressed mode).

The same 5k mode on non-UHBR link rates is not affected and lower
resolution modes are not affected either. The problem is similar to the
one fixed by the HBLANK expansion quirk on Synaptics hubs, with the
difference that the problematic mode has a longer HBLANK duration. Also
the monitor doesn't report supporting HBLANK expansion; either its
internal MST hub does the expansion internally - similarly to the
Synaptics hub - or the issue has another root cause, but still related
to the mode's short HBLANK duration. Enable the quirk for the monitor
adjusting the detection for the above differences.

v2: Rebase on drm_dp_128132b_supported() change.

Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Ankit Nautiyal 
Tested-by: Khaled Almahallawy 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/display/drm_dp_helper.c |  2 ++
 drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +
 2 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
b/drivers/gpu/drm/display/drm_dp_helper.c
index 023907da98581..79a615667aab1 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2281,6 +2281,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, 
BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
/* Synaptics DP1.4 MST hubs require DSC for some modes on which it 
applies HBLANK expansion. */
{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, 
BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
+   /* MediaTek panels (at least in U3224KBA) require DSC for modes with a 
short HBLANK on UHBR links. */
+   { OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, 
BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low 
DP_MAX_LINK_RATE */
{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, 
BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
 };
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index fb5e167c3c659..1cd375963f243 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -421,15 +421,22 @@ static int mode_hblank_period_ns(const struct 
drm_display_mode *mode)
 
 static bool
 hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector,
-const struct intel_crtc_state *crtc_state)
+const struct intel_crtc_state *crtc_state,
+const struct link_config_limits *limits)
 {
const struct drm_display_mode *adjusted_mode =
_state->hw.adjusted_mode;
+   bool is_uhbr_sink = connector->mst_port &&
+   
drm_dp_128b132b_supported(connector->mst_port->dpcd);
+   int hblank_limit = is_uhbr_sink ? 500 : 300;
 
if (!connector->dp.dsc_hblank_expansion_quirk)
return false;
 
-   if (mode_hblank_period_ns(adjusted_mode) > 300)
+   if (is_uhbr_sink && !drm_dp_is_uhbr_rate(limits->max_rate))
+   return false;
+
+   if (mode_hblank_period_ns(adjusted_mode) > hblank_limit)
return false;
 
return true;
@@ -445,7 +452,7 @@ adjust_limits_for_dsc_hblank_expansion_quirk(const struct 
intel_connector *conne
const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
int min_bpp_x16 = limits->link.min_bpp_x16;
 
-   if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state))
+   if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state, limits))
return true;
 
if (!dsc) {
@@ -1604,7 +1611,14 @@ static bool detect_dsc_hblank_expansion_quirk(const 
struct intel_connector *conn
  DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC))
return false;
 
-   if (!(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE))
+   /*
+* UHBR (MST sink) devices requiring this quirk don't advertise the
+* HBLANK expansion support. Presuming that they perform HBLANK
+* expansion internally, or are affected by this issue on modes with a
+* short HBLANK for other reasons.
+*/
+   if (!drm_dp_128b132b_supported(dpcd) &&
+   !(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE))
return false;
 
drm_dbg_kms(>drm,
-- 
2.43.3

[PATCH v3 07/11] drm/dp: Add drm_dp_128b132b_supported()

[Imre Deak]

Factor out a function to check for 128b/132b channel coding support used
by a follow-up patch in the patchset.

v2: s/drm_dp_uhbr_channel_coding_supported()/drm_dp128b132b_supported()
(Jani)

Cc: dri-de...@lists.freedesktop.org
Cc: Jani Nikula 
Reviewed-by: Ankit Nautiyal 
Reviewed-by: Manasi Navare 
Acked-by: Maarten Lankhorst 
Signed-off-by: Imre Deak 
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 include/drm/display/drm_dp_helper.h | 6 ++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
b/drivers/gpu/drm/i915/display/intel_dp.c
index 23808e9d41d5d..e05e25cd4a940 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -225,7 +225,7 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp 
*intel_dp)
 * Sink rates for 128b/132b. If set, sink should support all 8b/10b
 * rates and 10 Gbps.
 */
-   if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) 
{
+   if (drm_dp_128b132b_supported(intel_dp->dpcd)) {
u8 uhbr_rates = 0;
 
BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < 
ARRAY_SIZE(dp_rates) + 3);
diff --git a/include/drm/display/drm_dp_helper.h 
b/include/drm/display/drm_dp_helper.h
index baf9949ff96fc..8bed890eec2c6 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -251,6 +251,12 @@ drm_dp_channel_coding_supported(const u8 
dpcd[DP_RECEIVER_CAP_SIZE])
return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
 }
 
+static inline bool
+drm_dp_128b132b_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+   return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B;
+}
+
 static inline bool
 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 {
-- 
2.43.3

Re: [PATCH v6 3/5] drm: Add support to get EDID from ACPI

[Geert Uytterhoeven]

Hi Mario,

On Thu, Feb 15, 2024 at 8:04 PM Mario Limonciello
 wrote:
> On 2/15/2024 12:47, Ville Syrjälä wrote:
> > On Thu, Feb 15, 2024 at 12:20:56PM -0600, Mario Limonciello wrote:
> >> On 2/14/2024 17:13, Ville Syrjälä wrote:
> >>> On Wed, Feb 14, 2024 at 03:57:54PM -0600, Mario Limonciello wrote:
>  --- a/include/drm/drm_connector.h
>  +++ b/include/drm/drm_connector.h
>  @@ -1886,6 +1886,12 @@ struct drm_connector {
> 
> /** @hdr_sink_metadata: HDR Metadata Information read from 
>  sink */
> struct hdr_sink_metadata hdr_sink_metadata;
>  +
>  +  /**
>  +   * @acpi_edid_allowed: Get the EDID from the BIOS, if available.
>  +   * This is only applicable to eDP and LVDS displays.
>  +   */
>  +  bool acpi_edid_allowed;
> >>>
> >>> Aren't there other bools/small stuff in there for tighter packing?
> >>
> >> Does the compiler automatically do the packing if you put bools nearby
> >> in a struct?  If so; TIL.
> >
> > Yes. Well, depends on the types and their alignment requirements
> > of course, and/or whether you specified __packed or not.
> >
> > You can use 'pahole' to find the holes in structures.
>
> Thanks!  I don't see a __packed attribute on struct drm_connector, but
> I'll put it near by other bools in case that changes in the future.

FTR, don't add __packed unless you have a very good reason to do so.
With __packed, the compiler will emit multiple byte-accesses to
access multi-byte integrals on platforms that do not support unaligned
memory access.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v4 8/9] drm/i915/de: allow intel_display and drm_i915_private for de functions

[Rodrigo Vivi]

On Wed, Apr 17, 2024 at 04:02:46PM +0300, Jani Nikula wrote:
> It would be too much noise to convert the intel_de_* functions from
> using struct drm_i915_private to struct intel_display all at once. Add
> generic wrappers using __to_intel_display() to accept both.
> 
> v2: Take the intel_dmc_wl_* changes into account
> 
> Cc: Luca Coelho 
> Reviewed-by: Rodrigo Vivi  # v1

thanks for sharing the scripts,

Reviewed-by: Rodrigo Vivi 

> Signed-off-by: Jani Nikula 
> 
> ---
> 
> This was done using a cocci + shell script combo:
> 
> #!/bin/bash
> 
> set -e
> 
> FILE=drivers/gpu/drm/i915/display/intel_de.h
> 
> cocci=$(mktemp)
> cat >$cocci < @@
> identifier ptr;
> identifier fn =~ "^_*intel_de_.*";
> fresh identifier __fn = "__" ## fn;
> @@
> 
> - fn(struct drm_i915_private *ptr,
> + __fn(struct intel_display *display,
>   ...) {
>   <...
> (
> - >uncore
> + __to_uncore(display)
> |
> - >display
> + display
> |
> - ptr
> + display
> )
>   ...>
>   }
> + #define fn(p, VARARGS_PLACEHOLDER) __fn(__to_intel_display(p), 
> __VA_ARGS__)
> 
> EOF
> 
> spatch --sp-file $cocci --in-place --linux-spacing $FILE >/dev/null
> 
> # Fixup varargs
> sed -i "s/VARARGS_PLACEHOLDER/.../g" $FILE
> 
> # Add the __to_uncore() helper
> snip=$(mktemp)
> cat >$snip < 
> static inline struct intel_uncore *__to_uncore(struct intel_display 
> *display)
> {
>   return _i915(display->drm)->uncore;
> }
> EOF
> 
> sed -ie "/\#include \"intel_uncore\.h\"/r $snip" $FILE
> 
> rm -f $cocci $snip
> ---
>  drivers/gpu/drm/i915/display/intel_de.h | 157 ++--
>  1 file changed, 93 insertions(+), 64 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h 
> b/drivers/gpu/drm/i915/display/intel_de.h
> index 15440058ad2a..e881bfeafb47 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -10,161 +10,185 @@
>  #include "i915_trace.h"
>  #include "intel_uncore.h"
>  
> +static inline struct intel_uncore *__to_uncore(struct intel_display *display)
> +{
> + return _i915(display->drm)->uncore;
> +}
> +
>  static inline u32
> -intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
> +__intel_de_read(struct intel_display *display, i915_reg_t reg)
>  {
>   u32 val;
>  
> - intel_dmc_wl_get(>display, reg);
> + intel_dmc_wl_get(display, reg);
>  
> - val = intel_uncore_read(>uncore, reg);
> + val = intel_uncore_read(__to_uncore(display), reg);
>  
> - intel_dmc_wl_put(>display, reg);
> + intel_dmc_wl_put(display, reg);
>  
>   return val;
>  }
> +#define intel_de_read(p,...) __intel_de_read(__to_intel_display(p), 
> __VA_ARGS__)
>  
>  static inline u8
> -intel_de_read8(struct drm_i915_private *i915, i915_reg_t reg)
> +__intel_de_read8(struct intel_display *display, i915_reg_t reg)
>  {
>   u8 val;
>  
> - intel_dmc_wl_get(>display, reg);
> + intel_dmc_wl_get(display, reg);
>  
> - val = intel_uncore_read8(>uncore, reg);
> + val = intel_uncore_read8(__to_uncore(display), reg);
>  
> - intel_dmc_wl_put(>display, reg);
> + intel_dmc_wl_put(display, reg);
>  
>   return val;
>  }
> +#define intel_de_read8(p,...) __intel_de_read8(__to_intel_display(p), 
> __VA_ARGS__)
>  
>  static inline u64
> -intel_de_read64_2x32(struct drm_i915_private *i915,
> -  i915_reg_t lower_reg, i915_reg_t upper_reg)
> +__intel_de_read64_2x32(struct intel_display *display,
> +i915_reg_t lower_reg, i915_reg_t upper_reg)
>  {
>   u64 val;
>  
> - intel_dmc_wl_get(>display, lower_reg);
> - intel_dmc_wl_get(>display, upper_reg);
> + intel_dmc_wl_get(display, lower_reg);
> + intel_dmc_wl_get(display, upper_reg);
>  
> - val = intel_uncore_read64_2x32(>uncore, lower_reg, upper_reg);
> + val = intel_uncore_read64_2x32(__to_uncore(display), lower_reg,
> +upper_reg);
>  
> - intel_dmc_wl_put(>display, upper_reg);
> - intel_dmc_wl_put(>display, lower_reg);
> + intel_dmc_wl_put(display, upper_reg);
> + intel_dmc_wl_put(display, lower_reg);
>  
>   return val;
>  }
> +#define intel_de_read64_2x32(p,...) 
> __intel_de_read64_2x32(__to_intel_display(p), __VA_ARGS__)
>  
>  static inline void
> -intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
> +__intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
>  {
> - intel_dmc_wl_get(>display, reg);
> + intel_dmc_wl_get(display, reg);
>  
> - intel_uncore_posting_read(>uncore, reg);
> + intel_uncore_posting_read(__to_uncore(display), reg);
>  
> - intel_dmc_wl_put(>display, reg);
> + intel_dmc_wl_put(display, reg);
>  }
> +#define intel_de_posting_read(p,...) 
> __intel_de_posting_read(__to_intel_display(p), __VA_ARGS__)
>  
>  static inline void
> 

Re: [PATCH v4 6/9] drm/i915/display: rename __intel_wait_for_register_nowl() to indicate intel_de_

[Rodrigo Vivi]

On Wed, Apr 17, 2024 at 04:02:44PM +0300, Jani Nikula wrote:
> Rename __intel_wait_for_register_nowl() to
> __intel_de_wait_for_register_nowl() to be in line with the rest of
> intel_de.h.
> 
> Cc: Luca Coelho 
> Signed-off-by: Jani Nikula 

Reviewed-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/display/intel_de.h |  6 +++---
>  drivers/gpu/drm/i915/display/intel_dmc_wl.c | 14 +++---
>  2 files changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h 
> b/drivers/gpu/drm/i915/display/intel_de.h
> index 0a0fba81e7af..4b51388c6041 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -97,8 +97,8 @@ intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, 
> u32 clear, u32 set)
>  }
>  
>  static inline int
> -__intel_wait_for_register_nowl(struct drm_i915_private *i915, i915_reg_t reg,
> -u32 mask, u32 value, unsigned int timeout)
> +__intel_de_wait_for_register_nowl(struct drm_i915_private *i915, i915_reg_t 
> reg,
> +   u32 mask, u32 value, unsigned int timeout)
>  {
>   return intel_wait_for_register(>uncore, reg, mask,
>  value, timeout);
> @@ -112,7 +112,7 @@ intel_de_wait(struct drm_i915_private *i915, i915_reg_t 
> reg,
>  
>   intel_dmc_wl_get(i915, reg);
>  
> - ret = __intel_wait_for_register_nowl(i915, reg, mask, value, timeout);
> + ret = __intel_de_wait_for_register_nowl(i915, reg, mask, value, 
> timeout);
>  
>   intel_dmc_wl_put(i915, reg);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c 
> b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> index 30f8905fae41..162de0d20554 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> @@ -77,9 +77,9 @@ static void intel_dmc_wl_work(struct work_struct *work)
>  
>   __intel_de_rmw_nowl(i915, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0);
>  
> - if (__intel_wait_for_register_nowl(i915,  DMC_WAKELOCK1_CTL,
> -DMC_WAKELOCK_CTL_ACK, 0,
> -DMC_WAKELOCK_CTL_TIMEOUT)) {
> + if (__intel_de_wait_for_register_nowl(i915, DMC_WAKELOCK1_CTL,
> +   DMC_WAKELOCK_CTL_ACK, 0,
> +   DMC_WAKELOCK_CTL_TIMEOUT)) {
>   WARN_RATELIMIT(1, "DMC wakelock release timed out");
>   goto out_unlock;
>   }
> @@ -216,10 +216,10 @@ void intel_dmc_wl_get(struct drm_i915_private *i915, 
> i915_reg_t reg)
>   __intel_de_rmw_nowl(i915, DMC_WAKELOCK1_CTL, 0,
>   DMC_WAKELOCK_CTL_REQ);
>  
> - if (__intel_wait_for_register_nowl(i915,  DMC_WAKELOCK1_CTL,
> -DMC_WAKELOCK_CTL_ACK,
> -DMC_WAKELOCK_CTL_ACK,
> -DMC_WAKELOCK_CTL_TIMEOUT)) {
> + if (__intel_de_wait_for_register_nowl(i915, DMC_WAKELOCK1_CTL,
> +   DMC_WAKELOCK_CTL_ACK,
> +   DMC_WAKELOCK_CTL_ACK,
> +   
> DMC_WAKELOCK_CTL_TIMEOUT)) {
>   WARN_RATELIMIT(1, "DMC wakelock ack timed out");
>   goto out_unlock;
>   }
> -- 
> 2.39.2
> 

Re: [PATCH v4 4/9] drm/i915/display: accept either i915 or display for feature tests

[Rodrigo Vivi]

On Wed, Apr 17, 2024 at 04:02:42PM +0300, Jani Nikula wrote:
> Use the generic __to_intel_display() to allow passing either struct
> drm_i915_private * or struct intel_display * to the feature test macros.
> 
> Signed-off-by: Jani Nikula 

Reviewed-by: Rodrigo Vivi 

> ---
>  drivers/gpu/drm/i915/display/intel_display_device.h | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h 
> b/drivers/gpu/drm/i915/display/intel_display_device.h
> index 66b51de86e38..17ddf82f0b6e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -8,6 +8,7 @@
>  
>  #include 
>  
> +#include "intel_display_conversion.h"
>  #include "intel_display_limits.h"
>  
>  struct drm_i915_private;
> @@ -100,8 +101,8 @@ struct drm_printer;
>   (IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \
>IS_DISPLAY_STEP((__i915), (from), (until)))
>  
> -#define DISPLAY_INFO(i915)   ((i915)->display.info.__device_info)
> -#define DISPLAY_RUNTIME_INFO(i915)   (&(i915)->display.info.__runtime_info)
> +#define DISPLAY_INFO(i915)   
> (__to_intel_display(i915)->info.__device_info)
> +#define DISPLAY_RUNTIME_INFO(i915)   
> (&__to_intel_display(i915)->info.__runtime_info)
>  
>  #define DISPLAY_VER(i915)(DISPLAY_RUNTIME_INFO(i915)->ip.ver)
>  #define DISPLAY_VER_FULL(i915)   
> IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \
> -- 
> 2.39.2
> 

[PULL] drm-intel-next

[Rodrigo Vivi]

Hi Sima and Dave,

Here goes our biggest pull request of this round.
Likely a small pull request coming end of next week as well.

I had to bypass dim on missed link tag in a patch that was a urgent revert
and ended up without the patchwork link.
(Which btw I'm proposing an option to dim for making that easier for us:
https://gitlab.freedesktop.org/drm/maintainer-tools/-/merge_requests/52
)

Another thing that it is important to highlight is that we have 3 drm level
patches in this pull request where I didn't see any explicit recorded
ack from you (drm maintainers) nor from drm-misc maintainers.
The patches looks good to me and shouldn't cause conflict, so I hope it
is okay to continue with them here instead of a big removal at this
point.

Thanks,
Rodrigo.

drm-intel-next-2024-04-17-1:
Core Changes (DRM):

- Fix documentation of DP tunnel functions (Imre)
- DP MST read sideband messaging cap (Jani)
- Preparation patches for Adaptive Sync SDP Support for DP (Mitul)

Driver Changes:

i915 core (non-display):
- Documentation improvements (Nirmoy)
- Add includes for BUG_ON/BUILD_BUG_ON in i915_memcpy.c (Joonas)
- Do not print 'pxp init failed with 0' when it succeed (Jose)
- Clean-up, including removal of dead code for unsupported platforms (Lucas)
- Adding new DG2 PCI ID (Ravi)

{i915,xe} display:
- Spelling fix (Colin Ian)
- Document CDCLK components (Gustavo)
- Lunar Lake display enabling, including cdclk and other refactors (Gustavo, 
Bala)
- BIOS/VBT/opregion related refactor (Jani, Ville, RK)
- Save a few bytes of memory using {kstrdup,kfree}_const variant (Christophe)
- Digital port related refactor/clean-up (Ville)
- Fix 2s boot time regression on DP panel replay init (Animesh)
- Remove redundant drm_rect_visible() overlay use (Arthur)
- DSC HW state readout fixes (Imre)
- Remove duplication on audio enable/disable on SDVO and g4x+ DP (Ville)
- Disable AuxCCS framebuffers if built for Xe (Juha-Pekka)
- Fix DSI init order (Ville)
- DRRS related refactor and fixes (Bhanuprakash)
- Fix DSB vblank waits with VRR (Ville)
- General improvements on register name and use of REG_BIT (Ville)
- Some display power well related improvements (Ville)
- FBC changes for better w/a handling (Ville)
- Make crtc disable more atomic (Ville)
- Fix hwmon locking inversion in sysfs getter (Janusz)
- Increase DP idle pattern wait timeout to 2ms (Shekhar)
- PSR related fixes and improvents (Jouni)
- Start using container_of_const() for some extra const safety (Ville)
- Use drm_printer more on display code (Ville)
- Fix Jasper Lake boot freeze (Jonathon)
- Update Pipe src size check in skl_update_scaler (Ankit)
- Enable MST mode for 128b/132b single-stream sideband (Jani)
- Pass encoder around more for port/phy checks (Jani)
- Some initial work to make display code more independent from i915 (Jani)
- Pre-populate the cursor physical dma address (Ville)
- Do not bump min backlight brightness to max on enable (Gareth)
- Fix MTL supported DP rates - removal of UHBR13.5 (Arun)
- Fix the computation for compressed_bpp for DISPLAY < 1 (Ankit)
- Bigjoiner modeset sequence redesign and MST support (Ville)
- Enable Adaptive Sync SDP Support for DP (Mitul)
- Implemnt vblank sycnhronized mbus joining changes (Ville, Stanislav)
- HDCP related fixes (Suraj)
- Fix i915_display_info debugfs when connectors are not active (Ville)
- Clean up on Xe compat layer (Jani)
- Add jitter WAs for MST/FEC/DSC links (Imre)
- DMC wakelock implementation (Luca)
The following changes since commit 39cd87c4eb2b893354f3b850f916353f2658ae6f:

  Linux 6.9-rc2 (2024-03-31 14:32:39 -0700)

are available in the Git repository at:

  https://anongit.freedesktop.org/git/drm/drm-intel 
tags/drm-intel-next-2024-04-17-1

for you to fetch changes up to 700c34019555392a348f8c03237c1ebb5bf53eb4:

  drm/i915/display: tie DMC wakelock to DC5/6 state transitions (2024-04-17 
11:41:23 +0300)


Core Changes (DRM):

- Fix documentation of DP tunnel functions (Imre)
- DP MST read sideband messaging cap (Jani)
- Preparation patches for Adaptive Sync SDP Support for DP (Mitul)

Driver Changes:

i915 core (non-display):
- Documentation improvements (Nirmoy)
- Add includes for BUG_ON/BUILD_BUG_ON in i915_memcpy.c (Joonas)
- Do not print 'pxp init failed with 0' when it succeed (Jose)
- Clean-up, including removal of dead code for unsupported platforms (Lucas)
- Adding new DG2 PCI ID (Ravi)

{i915,xe} display:
- Spelling fix (Colin Ian)
- Document CDCLK components (Gustavo)
- Lunar Lake display enabling, including cdclk and other refactors (Gustavo, 
Bala)
- BIOS/VBT/opregion related refactor (Jani, Ville, RK)
- Save a few bytes of memory using {kstrdup,kfree}_const variant (Christophe)
- Digital port related refactor/clean-up (Ville)
- Fix 2s boot time regression on DP panel replay init (Animesh)
- Remove redundant drm_rect_visible() overlay use (Arthur)
- DSC HW state readout fixes (Imre)
- Remove duplication on audio 

Re: [PATCH i-g-t] i915/gem_mmap_offset: Partial mmap and munmap

[Nirmoy Das]

On 4/12/2024 2:42 AM, Andi Shyti wrote:

From: Chris Wilson 

Based on a test case developed by Lionel Landwerlin, this exercises
creation of partial mmaps using both direct methods of a partial mmap()
(where the mmap() only covers a portion of the object) and
munmap() to do the same.

Signed-off-by: Chris Wilson 
Signed-off-by: Andi Shyti 
---
  tests/intel/gem_mmap_offset.c | 84 +++
  1 file changed, 84 insertions(+)

diff --git a/tests/intel/gem_mmap_offset.c b/tests/intel/gem_mmap_offset.c
index 95d2158ca88f..0ba2f9591f85 100644
--- a/tests/intel/gem_mmap_offset.c
+++ b/tests/intel/gem_mmap_offset.c
@@ -56,6 +56,8 @@
   * SUBTEST: isolation
   * SUBTEST: oob-read
   * SUBTEST: open-flood
+ * SUBTEST: partial-mmap
+ * SUBTEST: partial-unmap
   * SUBTEST: perf
   * SUBTEST: pf-nonblock
   * SUBTEST: ptrace
@@ -874,6 +876,83 @@ static void blt_coherency(int i915)
igt_assert_f(compare_ok, "Problem with coherency, flush is too late\n");
  }
  
+static void partial_mmap(int i915)

+{
+   uint32_t handle;
+
+   handle = gem_create(i915, SZ_2M);
+
+   for_each_mmap_offset_type(i915, t) {
+   struct drm_i915_gem_mmap_offset arg = {
+   .handle = handle,
+   .flags = t->type,
+   };
+   uint32_t *ptr;
+
+   if (mmap_offset_ioctl(i915, ))
+   continue;
+
+   ptr = mmap(0, SZ_4K, PROT_WRITE, MAP_SHARED, i915, arg.offset);
+   if (ptr == MAP_FAILED)
+   continue;
+
+   memset(ptr, 0xcc, SZ_4K);
+   munmap(ptr, SZ_4K);
+
+   ptr = mmap(0, SZ_4K, PROT_READ, MAP_SHARED, i915, arg.offset + 
SZ_2M - SZ_4K);
+   igt_assert(ptr != MAP_FAILED);
+
+   for (uint32_t i = 0; i < SZ_4K / sizeof(uint32_t); i++)
+   igt_assert_eq_u32(ptr[i], 0);
+
+   munmap(ptr, SZ_4K);
+   }
+
+   gem_close(i915, handle);
+}
+
+static void partial_unmap(int i915)
+{
+   uint32_t handle;
+
+   handle = gem_create(i915, SZ_2M);
+
+   for_each_mmap_offset_type(i915, t) {
+   uint8_t *ptr_a, *ptr_b;
+
+   /* mmap the same GEM BO twice */
+   ptr_a = __mmap_offset(i915, handle, 0, SZ_2M,
+   PROT_READ | PROT_WRITE,
+   t->type);
+   if (!ptr_a)
+   continue;
+
+   ptr_b = __mmap_offset(i915, handle, 0, SZ_2M,
+   PROT_READ | PROT_WRITE,
+   t->type);
+   if (!ptr_b)
+   continue;
+
+   /* unmap the first mapping but the last 4k */
+   munmap(ptr_a, SZ_2M - SZ_4K);
+
+   /* memset that remaining 4k with 0xcc */
+   memset(ptr_a + SZ_2M - SZ_4K, 0xcc, SZ_4K);
+
+   /* memset the first page of the 2Mb with 0xdd */
+   memset(ptr_b, 0xdd, SZ_4K);
+
+   for (uint32_t i = 0; i < SZ_4K; i++)
+   igt_assert_eq_u32(ptr_a[SZ_2M - SZ_4K + i], 0xcc);
+
+   munmap(ptr_a + SZ_2M - SZ_4K, SZ_4K);
+   memset(ptr_b, 0, SZ_2M);


Do we need this extra memset() ? Otherwise

Reviewed-by: Nirmoy Das 



+   munmap(ptr_b, SZ_2M);
+   }
+
+   gem_close(i915, handle);
+}
+
  static int mmap_gtt_version(int i915)
  {
int gtt_version = -1;
@@ -931,6 +1010,11 @@ igt_main
igt_subtest_f("open-flood")
open_flood(i915, 20);
  
+	igt_subtest_f("partial-mmap")

+   partial_mmap(i915);
+   igt_subtest_f("partial-unmap")
+   partial_unmap(i915);
+
igt_subtest_with_dynamic("clear") {
for_each_memory_region(r, i915) {
igt_dynamic_f("%s", r->name)

Re: [PATCH v3 6/7] drm/i915/de: allow intel_display and drm_i915_private for de functions

[Jani Nikula]

On Tue, 16 Apr 2024, Rodrigo Vivi  wrote:
> On Tue, Apr 09, 2024 at 03:26:48PM +0300, Jani Nikula wrote:
>> It would be too much noise to convert the intel_de_* functions from
>> using struct drm_i915_private to struct intel_display all at once. Add
>> generic wrappers using __to_intel_display() to accept both.
>> 
>> Signed-off-by: Jani Nikula 
>> 
>> ---
>> 
>> This was done using a cocci + shell script combo.
>
> the conversion below seems sane.
> would you mind sharing the scripts in the commit message,
> so scripts could be used when porting this patch to other
> trees?

Done in v4.

>
> Reviewed-by: Rodrigo Vivi 
>
>> ---
>>  drivers/gpu/drm/i915/display/intel_de.h | 102 +++-
>>  1 file changed, 64 insertions(+), 38 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_de.h 
>> b/drivers/gpu/drm/i915/display/intel_de.h
>> index ba7a1c6ebc2a..a08f8ef630f3 100644
>> --- a/drivers/gpu/drm/i915/display/intel_de.h
>> +++ b/drivers/gpu/drm/i915/display/intel_de.h
>> @@ -10,80 +10,101 @@
>>  #include "i915_trace.h"
>>  #include "intel_uncore.h"
>>  
>> +static inline struct intel_uncore *__to_uncore(struct intel_display 
>> *display)
>> +{
>> +return _i915(display->drm)->uncore;
>> +}
>> +
>>  static inline u32
>> -intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
>> +__intel_de_read(struct intel_display *display, i915_reg_t reg)
>>  {
>> -return intel_uncore_read(>uncore, reg);
>> +return intel_uncore_read(__to_uncore(display), reg);
>>  }
>> +#define intel_de_read(p,...) __intel_de_read(__to_intel_display(p), 
>> __VA_ARGS__)
>>  
>>  static inline u8
>> -intel_de_read8(struct drm_i915_private *i915, i915_reg_t reg)
>> +__intel_de_read8(struct intel_display *display, i915_reg_t reg)
>>  {
>> -return intel_uncore_read8(>uncore, reg);
>> +return intel_uncore_read8(__to_uncore(display), reg);
>>  }
>> +#define intel_de_read8(p,...) __intel_de_read8(__to_intel_display(p), 
>> __VA_ARGS__)
>>  
>>  static inline u64
>> -intel_de_read64_2x32(struct drm_i915_private *i915,
>> - i915_reg_t lower_reg, i915_reg_t upper_reg)
>> +__intel_de_read64_2x32(struct intel_display *display,
>> +   i915_reg_t lower_reg, i915_reg_t upper_reg)
>>  {
>> -return intel_uncore_read64_2x32(>uncore, lower_reg, upper_reg);
>> +return intel_uncore_read64_2x32(__to_uncore(display), lower_reg,
>> +upper_reg);
>>  }
>> +#define intel_de_read64_2x32(p,...) 
>> __intel_de_read64_2x32(__to_intel_display(p), __VA_ARGS__)
>>  
>>  static inline void
>> -intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
>> +__intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
>>  {
>> -intel_uncore_posting_read(>uncore, reg);
>> +intel_uncore_posting_read(__to_uncore(display), reg);
>>  }
>> +#define intel_de_posting_read(p,...) 
>> __intel_de_posting_read(__to_intel_display(p), __VA_ARGS__)
>>  
>>  static inline void
>> -intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
>> +__intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
>>  {
>> -intel_uncore_write(>uncore, reg, val);
>> +intel_uncore_write(__to_uncore(display), reg, val);
>>  }
>> +#define intel_de_write(p,...) __intel_de_write(__to_intel_display(p), 
>> __VA_ARGS__)
>>  
>>  static inline u32
>> -intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 
>> set)
>> +__intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear,
>> +   u32 set)
>>  {
>> -return intel_uncore_rmw(>uncore, reg, clear, set);
>> +return intel_uncore_rmw(__to_uncore(display), reg, clear, set);
>>  }
>> +#define intel_de_rmw(p,...) __intel_de_rmw(__to_intel_display(p), 
>> __VA_ARGS__)
>>  
>>  static inline int
>> -intel_de_wait(struct drm_i915_private *i915, i915_reg_t reg,
>> -  u32 mask, u32 value, unsigned int timeout)
>> +__intel_de_wait(struct intel_display *display, i915_reg_t reg,
>> +u32 mask, u32 value, unsigned int timeout)
>>  {
>> -return intel_wait_for_register(>uncore, reg, mask, value, 
>> timeout);
>> +return intel_wait_for_register(__to_uncore(display), reg, mask, value,
>> +   timeout);
>>  }
>> +#define intel_de_wait(p,...) __intel_de_wait(__to_intel_display(p), 
>> __VA_ARGS__)
>>  
>>  static inline int
>> -intel_de_wait_fw(struct drm_i915_private *i915, i915_reg_t reg,
>> - u32 mask, u32 value, unsigned int timeout)
>> +__intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
>> +   u32 mask, u32 value, unsigned int timeout)
>>  {
>> -return intel_wait_for_register_fw(>uncore, reg, mask, value, 
>> timeout);
>> +return intel_wait_for_register_fw(__to_uncore(display), reg, mask,
>> +  value, timeout);
>>  }
>> +#define intel_de_wait_fw(p,...) __intel_de_wait_fw(__to_intel_display(p), 
>> 

Re: [PATCH v3 5/7] drm/i915/display: accept either i915 or display for feature tests

[Jani Nikula]

On Tue, 16 Apr 2024, Rodrigo Vivi  wrote:
> On Tue, Apr 09, 2024 at 03:26:47PM +0300, Jani Nikula wrote:
>> Use the generic __to_intel_display() to allow passing either struct
>> drm_i915_private * or struct intel_display * to the feature test macros.
>> 
>> Unfortunately, this requires including i915_drv.h in xe display
>> code. This is still better than polluting the main xe_device.h or
>> xe_device_types.h files with the __to_intel_display() macro definition.
>
> what about just duplicating these 2 lines in a compat layer
> (perhaps a new temporary one?) and the only including that
> instead of bringing it entirely?

Added a shared header under display for __to_intel_display(), and the
change in xe can be dropped.

BR,
Jani.


>
> or what else wouldbe needed?
>
>> 
>> Signed-off-by: Jani Nikula 
>> ---
>>  drivers/gpu/drm/i915/display/intel_display_device.h | 4 ++--
>>  drivers/gpu/drm/xe/display/xe_hdcp_gsc.c| 1 +
>>  2 files changed, 3 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h 
>> b/drivers/gpu/drm/i915/display/intel_display_device.h
>> index 66b51de86e38..01c6a4bef179 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
>> @@ -100,8 +100,8 @@ struct drm_printer;
>>  (IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \
>>   IS_DISPLAY_STEP((__i915), (from), (until)))
>>  
>> -#define DISPLAY_INFO(i915)  ((i915)->display.info.__device_info)
>> -#define DISPLAY_RUNTIME_INFO(i915)  (&(i915)->display.info.__runtime_info)
>> +#define DISPLAY_INFO(i915)  
>> (__to_intel_display(i915)->info.__device_info)
>> +#define DISPLAY_RUNTIME_INFO(i915)  
>> (&__to_intel_display(i915)->info.__runtime_info)
>>  
>>  #define DISPLAY_VER(i915)   (DISPLAY_RUNTIME_INFO(i915)->ip.ver)
>>  #define DISPLAY_VER_FULL(i915)  
>> IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \
>> diff --git a/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c 
>> b/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
>> index ac4b870f73fa..54314760f47a 100644
>> --- a/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
>> +++ b/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
>> @@ -19,6 +19,7 @@
>>  #include "xe_map.h"
>>  #include "xe_pm.h"
>>  #include "xe_uc_fw.h"
>> +#include "i915_drv.h"
>>  
>>  #define HECI_MEADDRESS_HDCP 18
>>  
>> -- 
>> 2.39.2
>> 

-- 
Jani Nikula, Intel

Re: [PATCH 6/8] drm/i915/dpio: s/ddi/dpio/ for bxt/glk PHY stuff

[Ville Syrjälä]

On Mon, Apr 15, 2024 at 03:39:41PM +0300, Jani Nikula wrote:
> On Fri, 12 Apr 2024, Ville Syrjala  wrote:
> > From: Ville Syrjälä 
> >
> > Since all of this lives in intel_dpio_phy.c let's rename the
> > bxt/glk functions to have bxt_dpio_phy_ namespace.
> 
> Seems like intel_dpio_phy.c could be split to vlv_dpio_phy.c and
> bxt_dpio_phy.c after this. At a glance, there isn't really anything
> shared between VLV/CHV and BXT/GLK code paths. They've just been thrown
> in to the same file.

Yeah, the original idea was that we could perhaps combine the 
CHV and BXT/GLK code into one since it's the same IP block on
both, but we ended up doing things a bit differently between
the two anyway so probably no one will ever do this.

VLV vs. CHV could also be split since the PHY codepaths
are compleletely separate, but perhaps not really worth
it since a lot of the other code is shared between the
two platforms anyway.

-- 
Ville Syrjälä
Intel

Re: [PATCH v3 4/7] drm/xe/display: add generic __to_intel_display()

[Jani Nikula]

On Wed, 17 Apr 2024, Jani Nikula  wrote:
> On Tue, 16 Apr 2024, Rodrigo Vivi  wrote:
>> On Tue, Apr 09, 2024 at 03:26:46PM +0300, Jani Nikula wrote:
>>> Add generic __to_intel_display() macro that accepts either struct
>>> xe_device * or struct intel_display *. This is to be used for
>>> transitional stuff that eventually needs to be converted to use struct
>>> intel_display *, and therefore is not part of to_intel_display().
>>> 
>>> Signed-off-by: Jani Nikula 
>>> ---
>>>  drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 11 +++
>>>  1 file changed, 11 insertions(+)
>>> 
>>> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h 
>>> b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>>> index 2792a497257e..4448eda8b2a4 100644
>>> --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>>> +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>>> @@ -29,6 +29,17 @@
>>>  #include "intel_runtime_pm.h"
>>>  #include 
>>>  
>>> +/*
>>> + * Transitional macro to optionally convert struct xe_device * to struct
>>> + * intel_display *, also accepting the latter.
>>> + */
>>> +#define __to_intel_display(p)  
>>> \
>>> +   _Generic(p, \
>>> +const struct xe_device *: (&((const struct xe_device 
>>> *)(p))->display), \
>>> +struct xe_device *: (&((struct xe_device *)(p))->display), \
>>> +const struct intel_display *: (p), \
>>> +struct intel_display *: (p))
>>
>> hmmm... I thought that with our make magic we didn't need this.
>> but well, at least more awareness and trying to get rid of the make magic
>> earlier?
>
> It's needed because in i915 I wanted to put this in i915_drv.h to not
> create a extra dependency to/from i915_drv.h. I tried, it gets tricky.
> So weed another copy xe side.
>
> The make magic does convert all struct drm_i915_private to struct
> xe_device, so this could have struct drm_i915_private, but the other
> copy is not available here.

Okay, so in v4 I decided to shove the macro to a header, and this patch
and the duplication is no longer needed.

BR,
Jani.


>
> BR,
> Jani.
>
>>
>> Reviewed-by: Rodrigo Vivi 
>>
>>> +
>>>  static inline struct drm_i915_private *to_i915(const struct drm_device 
>>> *dev)
>>>  {
>>> return container_of(dev, struct drm_i915_private, drm);
>>> -- 
>>> 2.39.2
>>> 

-- 
Jani Nikula, Intel

[PATCH v4 9/9] drm/i915/dmc: use struct intel_display more

[Jani Nikula]

Now that the intel_de_ functions and DISPLAY_VER() accept struct
intel_display *, use it more.

Cc: Luca Coelho 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_dmc_wl.c | 24 +
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c 
b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index e79c45e36722..d9864b9cc429 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -66,8 +66,8 @@ static void intel_dmc_wl_work(struct work_struct *work)
 {
struct intel_dmc_wl *wl =
container_of(work, struct intel_dmc_wl, work.work);
-   struct drm_i915_private *i915 =
-   container_of(wl, struct drm_i915_private, display.wl);
+   struct intel_display *display =
+   container_of(wl, struct intel_display, wl);
unsigned long flags;
 
spin_lock_irqsave(>lock, flags);
@@ -76,9 +76,9 @@ static void intel_dmc_wl_work(struct work_struct *work)
if (!refcount_read(>refcount))
goto out_unlock;
 
-   __intel_de_rmw_nowl(i915, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0);
+   __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 
0);
 
-   if (__intel_de_wait_for_register_nowl(i915, DMC_WAKELOCK1_CTL,
+   if (__intel_de_wait_for_register_nowl(display, DMC_WAKELOCK1_CTL,
  DMC_WAKELOCK_CTL_ACK, 0,
  DMC_WAKELOCK_CTL_TIMEOUT)) {
WARN_RATELIMIT(1, "DMC wakelock release timed out");
@@ -111,7 +111,7 @@ static bool __intel_dmc_wl_supported(struct intel_display 
*display)
 {
struct drm_i915_private *i915 = to_i915(display->drm);
 
-   if (DISPLAY_VER(i915) < 20 ||
+   if (DISPLAY_VER(display) < 20 ||
!intel_dmc_has_payload(i915) ||
!display->params.enable_dmc_wl)
return false;
@@ -121,11 +121,10 @@ static bool __intel_dmc_wl_supported(struct intel_display 
*display)
 
 void intel_dmc_wl_init(struct intel_display *display)
 {
-   struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_dmc_wl *wl = >wl;
 
/* don't call __intel_dmc_wl_supported(), DMC is not loaded yet */
-   if (DISPLAY_VER(i915) < 20 || !display->params.enable_dmc_wl)
+   if (DISPLAY_VER(display) < 20 || !display->params.enable_dmc_wl)
return;
 
INIT_DELAYED_WORK(>work, intel_dmc_wl_work);
@@ -135,7 +134,6 @@ void intel_dmc_wl_init(struct intel_display *display)
 
 void intel_dmc_wl_enable(struct intel_display *display)
 {
-   struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_dmc_wl *wl = >wl;
unsigned long flags;
 
@@ -152,7 +150,7 @@ void intel_dmc_wl_enable(struct intel_display *display)
 * wakelock, because we're just enabling it, so call the
 * non-locking version directly here.
 */
-   __intel_de_rmw_nowl(i915, DMC_WAKELOCK_CFG, 0, DMC_WAKELOCK_CFG_ENABLE);
+   __intel_de_rmw_nowl(display, DMC_WAKELOCK_CFG, 0, 
DMC_WAKELOCK_CFG_ENABLE);
 
wl->enabled = true;
wl->taken = false;
@@ -163,7 +161,6 @@ void intel_dmc_wl_enable(struct intel_display *display)
 
 void intel_dmc_wl_disable(struct intel_display *display)
 {
-   struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_dmc_wl *wl = >wl;
unsigned long flags;
 
@@ -178,7 +175,7 @@ void intel_dmc_wl_disable(struct intel_display *display)
goto out_unlock;
 
/* Disable wakelock in DMC */
-   __intel_de_rmw_nowl(i915, DMC_WAKELOCK_CFG, DMC_WAKELOCK_CFG_ENABLE, 0);
+   __intel_de_rmw_nowl(display, DMC_WAKELOCK_CFG, DMC_WAKELOCK_CFG_ENABLE, 
0);
 
refcount_set(>refcount, 0);
wl->enabled = false;
@@ -190,7 +187,6 @@ void intel_dmc_wl_disable(struct intel_display *display)
 
 void intel_dmc_wl_get(struct intel_display *display, i915_reg_t reg)
 {
-   struct drm_i915_private *i915 = to_i915(display->drm);
struct intel_dmc_wl *wl = >wl;
unsigned long flags;
 
@@ -219,10 +215,10 @@ void intel_dmc_wl_get(struct intel_display *display, 
i915_reg_t reg)
 * run yet.
 */
if (!wl->taken) {
-   __intel_de_rmw_nowl(i915, DMC_WAKELOCK1_CTL, 0,
+   __intel_de_rmw_nowl(display, DMC_WAKELOCK1_CTL, 0,
DMC_WAKELOCK_CTL_REQ);
 
-   if (__intel_de_wait_for_register_nowl(i915, DMC_WAKELOCK1_CTL,
+   if (__intel_de_wait_for_register_nowl(display, 
DMC_WAKELOCK1_CTL,
  DMC_WAKELOCK_CTL_ACK,
  DMC_WAKELOCK_CTL_ACK,
  
DMC_WAKELOCK_CTL_TIMEOUT)) {
-- 
2.39.2

[PATCH v4 8/9] drm/i915/de: allow intel_display and drm_i915_private for de functions

[Jani Nikula]

It would be too much noise to convert the intel_de_* functions from
using struct drm_i915_private to struct intel_display all at once. Add
generic wrappers using __to_intel_display() to accept both.

v2: Take the intel_dmc_wl_* changes into account

Cc: Luca Coelho 
Reviewed-by: Rodrigo Vivi  # v1
Signed-off-by: Jani Nikula 

---

This was done using a cocci + shell script combo:

#!/bin/bash

set -e

FILE=drivers/gpu/drm/i915/display/intel_de.h

cocci=$(mktemp)
cat >$cocci display
+ display
|
- ptr
+ display
)
  ...>
  }
+ #define fn(p, VARARGS_PLACEHOLDER) __fn(__to_intel_display(p), 
__VA_ARGS__)

EOF

spatch --sp-file $cocci --in-place --linux-spacing $FILE >/dev/null

# Fixup varargs
sed -i "s/VARARGS_PLACEHOLDER/.../g" $FILE

# Add the __to_uncore() helper
snip=$(mktemp)
cat >$snip uncore;
}
EOF

sed -ie "/\#include \"intel_uncore\.h\"/r $snip" $FILE

rm -f $cocci $snip
---
 drivers/gpu/drm/i915/display/intel_de.h | 157 ++--
 1 file changed, 93 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_de.h 
b/drivers/gpu/drm/i915/display/intel_de.h
index 15440058ad2a..e881bfeafb47 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -10,161 +10,185 @@
 #include "i915_trace.h"
 #include "intel_uncore.h"
 
+static inline struct intel_uncore *__to_uncore(struct intel_display *display)
+{
+   return _i915(display->drm)->uncore;
+}
+
 static inline u32
-intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
+__intel_de_read(struct intel_display *display, i915_reg_t reg)
 {
u32 val;
 
-   intel_dmc_wl_get(>display, reg);
+   intel_dmc_wl_get(display, reg);
 
-   val = intel_uncore_read(>uncore, reg);
+   val = intel_uncore_read(__to_uncore(display), reg);
 
-   intel_dmc_wl_put(>display, reg);
+   intel_dmc_wl_put(display, reg);
 
return val;
 }
+#define intel_de_read(p,...) __intel_de_read(__to_intel_display(p), 
__VA_ARGS__)
 
 static inline u8
-intel_de_read8(struct drm_i915_private *i915, i915_reg_t reg)
+__intel_de_read8(struct intel_display *display, i915_reg_t reg)
 {
u8 val;
 
-   intel_dmc_wl_get(>display, reg);
+   intel_dmc_wl_get(display, reg);
 
-   val = intel_uncore_read8(>uncore, reg);
+   val = intel_uncore_read8(__to_uncore(display), reg);
 
-   intel_dmc_wl_put(>display, reg);
+   intel_dmc_wl_put(display, reg);
 
return val;
 }
+#define intel_de_read8(p,...) __intel_de_read8(__to_intel_display(p), 
__VA_ARGS__)
 
 static inline u64
-intel_de_read64_2x32(struct drm_i915_private *i915,
-i915_reg_t lower_reg, i915_reg_t upper_reg)
+__intel_de_read64_2x32(struct intel_display *display,
+  i915_reg_t lower_reg, i915_reg_t upper_reg)
 {
u64 val;
 
-   intel_dmc_wl_get(>display, lower_reg);
-   intel_dmc_wl_get(>display, upper_reg);
+   intel_dmc_wl_get(display, lower_reg);
+   intel_dmc_wl_get(display, upper_reg);
 
-   val = intel_uncore_read64_2x32(>uncore, lower_reg, upper_reg);
+   val = intel_uncore_read64_2x32(__to_uncore(display), lower_reg,
+  upper_reg);
 
-   intel_dmc_wl_put(>display, upper_reg);
-   intel_dmc_wl_put(>display, lower_reg);
+   intel_dmc_wl_put(display, upper_reg);
+   intel_dmc_wl_put(display, lower_reg);
 
return val;
 }
+#define intel_de_read64_2x32(p,...) 
__intel_de_read64_2x32(__to_intel_display(p), __VA_ARGS__)
 
 static inline void
-intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
+__intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
 {
-   intel_dmc_wl_get(>display, reg);
+   intel_dmc_wl_get(display, reg);
 
-   intel_uncore_posting_read(>uncore, reg);
+   intel_uncore_posting_read(__to_uncore(display), reg);
 
-   intel_dmc_wl_put(>display, reg);
+   intel_dmc_wl_put(display, reg);
 }
+#define intel_de_posting_read(p,...) 
__intel_de_posting_read(__to_intel_display(p), __VA_ARGS__)
 
 static inline void
-intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
+__intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
 {
-   intel_dmc_wl_get(>display, reg);
+   intel_dmc_wl_get(display, reg);
 
-   intel_uncore_write(>uncore, reg, val);
+   intel_uncore_write(__to_uncore(display), reg, val);
 
-   intel_dmc_wl_put(>display, reg);
+   intel_dmc_wl_put(display, reg);
 }
+#define intel_de_write(p,...) __intel_de_write(__to_intel_display(p), 
__VA_ARGS__)
 
 static inline u32
-__intel_de_rmw_nowl(struct drm_i915_private *i915, i915_reg_t reg,
-   u32 clear, u32 set)
+intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,
+ u32 clear, u32 set)

[PATCH v4 7/9] drm/i915/dmc: convert dmc wakelock interface to struct intel_display

[Jani Nikula]

Convert the dmc wakelock interface to struct intel_display instead of
struct drm_i915_private. We'll want to convert the intel_de interfaces,
and there's a bit of coupling between the two, so start here.

Cc: Luca Coelho 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_de.h   | 40 
 .../drm/i915/display/intel_display_driver.c   |  2 +-
 .../i915/display/intel_display_power_well.c   |  6 +--
 drivers/gpu/drm/i915/display/intel_dmc.c  |  4 +-
 drivers/gpu/drm/i915/display/intel_dmc_wl.c   | 48 +++
 drivers/gpu/drm/i915/display/intel_dmc_wl.h   | 12 ++---
 6 files changed, 59 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_de.h 
b/drivers/gpu/drm/i915/display/intel_de.h
index 4b51388c6041..15440058ad2a 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -15,11 +15,11 @@ intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
 {
u32 val;
 
-   intel_dmc_wl_get(i915, reg);
+   intel_dmc_wl_get(>display, reg);
 
val = intel_uncore_read(>uncore, reg);
 
-   intel_dmc_wl_put(i915, reg);
+   intel_dmc_wl_put(>display, reg);
 
return val;
 }
@@ -29,11 +29,11 @@ intel_de_read8(struct drm_i915_private *i915, i915_reg_t 
reg)
 {
u8 val;
 
-   intel_dmc_wl_get(i915, reg);
+   intel_dmc_wl_get(>display, reg);
 
val = intel_uncore_read8(>uncore, reg);
 
-   intel_dmc_wl_put(i915, reg);
+   intel_dmc_wl_put(>display, reg);
 
return val;
 }
@@ -44,13 +44,13 @@ intel_de_read64_2x32(struct drm_i915_private *i915,
 {
u64 val;
 
-   intel_dmc_wl_get(i915, lower_reg);
-   intel_dmc_wl_get(i915, upper_reg);
+   intel_dmc_wl_get(>display, lower_reg);
+   intel_dmc_wl_get(>display, upper_reg);
 
val = intel_uncore_read64_2x32(>uncore, lower_reg, upper_reg);
 
-   intel_dmc_wl_put(i915, upper_reg);
-   intel_dmc_wl_put(i915, lower_reg);
+   intel_dmc_wl_put(>display, upper_reg);
+   intel_dmc_wl_put(>display, lower_reg);
 
return val;
 }
@@ -58,21 +58,21 @@ intel_de_read64_2x32(struct drm_i915_private *i915,
 static inline void
 intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
 {
-   intel_dmc_wl_get(i915, reg);
+   intel_dmc_wl_get(>display, reg);
 
intel_uncore_posting_read(>uncore, reg);
 
-   intel_dmc_wl_put(i915, reg);
+   intel_dmc_wl_put(>display, reg);
 }
 
 static inline void
 intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
 {
-   intel_dmc_wl_get(i915, reg);
+   intel_dmc_wl_get(>display, reg);
 
intel_uncore_write(>uncore, reg, val);
 
-   intel_dmc_wl_put(i915, reg);
+   intel_dmc_wl_put(>display, reg);
 }
 
 static inline u32
@@ -87,11 +87,11 @@ intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, 
u32 clear, u32 set)
 {
u32 val;
 
-   intel_dmc_wl_get(i915, reg);
+   intel_dmc_wl_get(>display, reg);
 
val = __intel_de_rmw_nowl(i915, reg, clear, set);
 
-   intel_dmc_wl_put(i915, reg);
+   intel_dmc_wl_put(>display, reg);
 
return val;
 }
@@ -110,11 +110,11 @@ intel_de_wait(struct drm_i915_private *i915, i915_reg_t 
reg,
 {
int ret;
 
-   intel_dmc_wl_get(i915, reg);
+   intel_dmc_wl_get(>display, reg);
 
ret = __intel_de_wait_for_register_nowl(i915, reg, mask, value, 
timeout);
 
-   intel_dmc_wl_put(i915, reg);
+   intel_dmc_wl_put(>display, reg);
 
return ret;
 }
@@ -125,11 +125,11 @@ intel_de_wait_fw(struct drm_i915_private *i915, 
i915_reg_t reg,
 {
int ret;
 
-   intel_dmc_wl_get(i915, reg);
+   intel_dmc_wl_get(>display, reg);
 
ret = intel_wait_for_register_fw(>uncore, reg, mask, value, 
timeout);
 
-   intel_dmc_wl_put(i915, reg);
+   intel_dmc_wl_put(>display, reg);
 
return ret;
 }
@@ -142,12 +142,12 @@ intel_de_wait_custom(struct drm_i915_private *i915, 
i915_reg_t reg,
 {
int ret;
 
-   intel_dmc_wl_get(i915, reg);
+   intel_dmc_wl_get(>display, reg);
 
ret = __intel_wait_for_register(>uncore, reg, mask, value,
fast_timeout_us, slow_timeout_ms, 
out_value);
 
-   intel_dmc_wl_put(i915, reg);
+   intel_dmc_wl_put(>display, reg);
 
return ret;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c 
b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 4f112a69dea8..1b24339e4ab6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -198,7 +198,7 @@ void intel_display_driver_early_probe(struct 
drm_i915_private *i915)
intel_dpll_init_clock_hook(i915);
intel_init_display_hooks(i915);
intel_fdi_init_hook(i915);
-   intel_dmc_wl_init(i915);
+   intel_dmc_wl_init(>display);
 }
 
 /* part #1: call before irq install */
diff 

[PATCH v4 6/9] drm/i915/display: rename __intel_wait_for_register_nowl() to indicate intel_de_

[Jani Nikula]

Rename __intel_wait_for_register_nowl() to
__intel_de_wait_for_register_nowl() to be in line with the rest of
intel_de.h.

Cc: Luca Coelho 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_de.h |  6 +++---
 drivers/gpu/drm/i915/display/intel_dmc_wl.c | 14 +++---
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_de.h 
b/drivers/gpu/drm/i915/display/intel_de.h
index 0a0fba81e7af..4b51388c6041 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -97,8 +97,8 @@ intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, 
u32 clear, u32 set)
 }
 
 static inline int
-__intel_wait_for_register_nowl(struct drm_i915_private *i915, i915_reg_t reg,
-  u32 mask, u32 value, unsigned int timeout)
+__intel_de_wait_for_register_nowl(struct drm_i915_private *i915, i915_reg_t 
reg,
+ u32 mask, u32 value, unsigned int timeout)
 {
return intel_wait_for_register(>uncore, reg, mask,
   value, timeout);
@@ -112,7 +112,7 @@ intel_de_wait(struct drm_i915_private *i915, i915_reg_t reg,
 
intel_dmc_wl_get(i915, reg);
 
-   ret = __intel_wait_for_register_nowl(i915, reg, mask, value, timeout);
+   ret = __intel_de_wait_for_register_nowl(i915, reg, mask, value, 
timeout);
 
intel_dmc_wl_put(i915, reg);
 
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c 
b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index 30f8905fae41..162de0d20554 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -77,9 +77,9 @@ static void intel_dmc_wl_work(struct work_struct *work)
 
__intel_de_rmw_nowl(i915, DMC_WAKELOCK1_CTL, DMC_WAKELOCK_CTL_REQ, 0);
 
-   if (__intel_wait_for_register_nowl(i915,  DMC_WAKELOCK1_CTL,
-  DMC_WAKELOCK_CTL_ACK, 0,
-  DMC_WAKELOCK_CTL_TIMEOUT)) {
+   if (__intel_de_wait_for_register_nowl(i915, DMC_WAKELOCK1_CTL,
+ DMC_WAKELOCK_CTL_ACK, 0,
+ DMC_WAKELOCK_CTL_TIMEOUT)) {
WARN_RATELIMIT(1, "DMC wakelock release timed out");
goto out_unlock;
}
@@ -216,10 +216,10 @@ void intel_dmc_wl_get(struct drm_i915_private *i915, 
i915_reg_t reg)
__intel_de_rmw_nowl(i915, DMC_WAKELOCK1_CTL, 0,
DMC_WAKELOCK_CTL_REQ);
 
-   if (__intel_wait_for_register_nowl(i915,  DMC_WAKELOCK1_CTL,
-  DMC_WAKELOCK_CTL_ACK,
-  DMC_WAKELOCK_CTL_ACK,
-  DMC_WAKELOCK_CTL_TIMEOUT)) {
+   if (__intel_de_wait_for_register_nowl(i915, DMC_WAKELOCK1_CTL,
+ DMC_WAKELOCK_CTL_ACK,
+ DMC_WAKELOCK_CTL_ACK,
+ 
DMC_WAKELOCK_CTL_TIMEOUT)) {
WARN_RATELIMIT(1, "DMC wakelock ack timed out");
goto out_unlock;
}
-- 
2.39.2

[PATCH v4 5/9] drm/i915/quirks: convert struct drm_i915_private to struct intel_display

[Jani Nikula]

Use struct intel_display instead of struct drm_i915_private for
quirks. Also do drive-by conversions in call sites of intel_has_quirk().

Reviewed-by: Rodrigo Vivi 
Signed-off-by: Jani Nikula 
---
 .../gpu/drm/i915/display/intel_backlight.c| 40 ++---
 drivers/gpu/drm/i915/display/intel_ddi.c  |  6 +-
 .../drm/i915/display/intel_display_driver.c   |  3 +-
 drivers/gpu/drm/i915/display/intel_panel.c| 10 ++--
 drivers/gpu/drm/i915/display/intel_pps.c  |  6 +-
 drivers/gpu/drm/i915/display/intel_quirks.c   | 56 +--
 drivers/gpu/drm/i915/display/intel_quirks.h   |  6 +-
 7 files changed, 65 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c 
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 4d4330410b4d..071668bfe5d1 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -83,16 +83,16 @@ static u32 scale_hw_to_user(struct intel_connector 
*connector,
 
 u32 intel_backlight_invert_pwm_level(struct intel_connector *connector, u32 
val)
 {
-   struct drm_i915_private *i915 = to_i915(connector->base.dev);
+   struct intel_display *display = to_intel_display(connector);
struct intel_panel *panel = >panel;
 
-   drm_WARN_ON(>drm, panel->backlight.pwm_level_max == 0);
+   drm_WARN_ON(display->drm, panel->backlight.pwm_level_max == 0);
 
-   if (i915->display.params.invert_brightness < 0)
+   if (display->params.invert_brightness < 0)
return val;
 
-   if (i915->display.params.invert_brightness > 0 ||
-   intel_has_quirk(i915, QUIRK_INVERT_BRIGHTNESS)) {
+   if (display->params.invert_brightness > 0 ||
+   intel_has_quirk(display, QUIRK_INVERT_BRIGHTNESS)) {
return panel->backlight.pwm_level_max - val + 
panel->backlight.pwm_level_min;
}
 
@@ -126,15 +126,15 @@ u32 intel_backlight_level_to_pwm(struct intel_connector 
*connector, u32 val)
 
 u32 intel_backlight_level_from_pwm(struct intel_connector *connector, u32 val)
 {
-   struct drm_i915_private *i915 = to_i915(connector->base.dev);
+   struct intel_display *display = to_intel_display(connector);
struct intel_panel *panel = >panel;
 
-   drm_WARN_ON_ONCE(>drm,
+   drm_WARN_ON_ONCE(display->drm,
 panel->backlight.max == 0 || 
panel->backlight.pwm_level_max == 0);
 
-   if (i915->display.params.invert_brightness > 0 ||
-   (i915->display.params.invert_brightness == 0 &&
-intel_has_quirk(i915, QUIRK_INVERT_BRIGHTNESS)))
+   if (display->params.invert_brightness > 0 ||
+   (display->params.invert_brightness == 0 &&
+intel_has_quirk(display, QUIRK_INVERT_BRIGHTNESS)))
val = panel->backlight.pwm_level_max - (val - 
panel->backlight.pwm_level_min);
 
return scale(val, panel->backlight.pwm_level_min, 
panel->backlight.pwm_level_max,
@@ -1642,17 +1642,17 @@ void intel_backlight_update(struct intel_atomic_state 
*state,
 
 int intel_backlight_setup(struct intel_connector *connector, enum pipe pipe)
 {
-   struct drm_i915_private *i915 = to_i915(connector->base.dev);
+   struct intel_display *display = to_intel_display(connector);
struct intel_panel *panel = >panel;
int ret;
 
if (!connector->panel.vbt.backlight.present) {
-   if (intel_has_quirk(i915, QUIRK_BACKLIGHT_PRESENT)) {
-   drm_dbg_kms(>drm,
+   if (intel_has_quirk(display, QUIRK_BACKLIGHT_PRESENT)) {
+   drm_dbg_kms(display->drm,
"[CONNECTOR:%d:%s] no backlight present per 
VBT, but present per quirk\n",
connector->base.base.id, 
connector->base.name);
} else {
-   drm_dbg_kms(>drm,
+   drm_dbg_kms(display->drm,
"[CONNECTOR:%d:%s] no backlight present per 
VBT\n",
connector->base.base.id, 
connector->base.name);
return 0;
@@ -1660,16 +1660,16 @@ int intel_backlight_setup(struct intel_connector 
*connector, enum pipe pipe)
}
 
/* ensure intel_panel has been initialized first */
-   if (drm_WARN_ON(>drm, !panel->backlight.funcs))
+   if (drm_WARN_ON(display->drm, !panel->backlight.funcs))
return -ENODEV;
 
/* set level and max in panel struct */
-   mutex_lock(>display.backlight.lock);
+   mutex_lock(>backlight.lock);
ret = panel->backlight.funcs->setup(connector, pipe);
-   mutex_unlock(>display.backlight.lock);
+   mutex_unlock(>backlight.lock);
 
if (ret) {
-   drm_dbg_kms(>drm,
+   drm_dbg_kms(display->drm,
"[CONNECTOR:%d:%s] failed to setup backlight\n",
connector->base.base.id, 

[PATCH v4 4/9] drm/i915/display: accept either i915 or display for feature tests

[Jani Nikula]

Use the generic __to_intel_display() to allow passing either struct
drm_i915_private * or struct intel_display * to the feature test macros.

Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h 
b/drivers/gpu/drm/i915/display/intel_display_device.h
index 66b51de86e38..17ddf82f0b6e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -8,6 +8,7 @@
 
 #include 
 
+#include "intel_display_conversion.h"
 #include "intel_display_limits.h"
 
 struct drm_i915_private;
@@ -100,8 +101,8 @@ struct drm_printer;
(IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \
 IS_DISPLAY_STEP((__i915), (from), (until)))
 
-#define DISPLAY_INFO(i915) ((i915)->display.info.__device_info)
-#define DISPLAY_RUNTIME_INFO(i915) (&(i915)->display.info.__runtime_info)
+#define DISPLAY_INFO(i915) 
(__to_intel_display(i915)->info.__device_info)
+#define DISPLAY_RUNTIME_INFO(i915) 
(&__to_intel_display(i915)->info.__runtime_info)
 
 #define DISPLAY_VER(i915)  (DISPLAY_RUNTIME_INFO(i915)->ip.ver)
 #define DISPLAY_VER_FULL(i915) IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \
-- 
2.39.2

[PATCH v4 3/9] drm/i915: add generic __to_intel_display()

[Jani Nikula]

Add generic __to_intel_display() macro that accepts either struct
drm_i915_private * or struct intel_display *. This is to be used for
transitional stuff that eventually needs to be converted to use struct
intel_display *, and therefore is not part of to_intel_display().

Add new intel_display_conversion.h to host the helper to avoid
duplication between xe and i915 drivers.

v2: put it in the new header (Rodrigo)

Reviewed-by: Rodrigo Vivi  # v1
Signed-off-by: Jani Nikula 
---
 .../i915/display/intel_display_conversion.h   | 22 +++
 1 file changed, 22 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_conversion.h

diff --git a/drivers/gpu/drm/i915/display/intel_display_conversion.h 
b/drivers/gpu/drm/i915/display/intel_display_conversion.h
new file mode 100644
index ..ad8545c8055d
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_conversion.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2024 Intel Corporation */
+
+/*
+ * This header is for transitional struct intel_display conversion helpers 
only.
+ */
+
+#ifndef __INTEL_DISPLAY_CONVERSION__
+#define __INTEL_DISPLAY_CONVERSION__
+
+/*
+ * Transitional macro to optionally convert struct drm_i915_private * to struct
+ * intel_display *, also accepting the latter.
+ */
+#define __to_intel_display(p)  \
+   _Generic(p, \
+const struct drm_i915_private *: (&((const struct 
drm_i915_private *)(p))->display), \
+struct drm_i915_private *: (&((struct drm_i915_private 
*)(p))->display), \
+const struct intel_display *: (p), \
+struct intel_display *: (p))
+
+#endif /* __INTEL_DISPLAY_CONVERSION__ */
-- 
2.39.2

[PATCH v4 2/9] drm/i915/display: add generic to_intel_display() macro

[Jani Nikula]

Convert various pointers to struct intel_display * using _Generic().

Add some macro magic to make adding new conversions easier, and somewhat
abstract the need to cast each generic association. The cast is required
because all associations needs to compile, regardless of the type and
the generic selection.

The use of *p in the generic selection assignment expression removes the
need to add separate associations for const pointers.

Note: This intentionally does *not* cover struct drm_i915_private or
struct xe_device. They are not to be used in the long run, so avoid
using this macro for them.

Reviewed-by: Rodrigo Vivi 
Signed-off-by: Jani Nikula 
---
 .../drm/i915/display/intel_display_types.h| 37 +++
 1 file changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h 
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0f4bd5710796..1be98c4219b0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2197,4 +2197,41 @@ static inline int to_bpp_x16(int bpp)
return bpp << 4;
 }
 
+/*
+ * Conversion functions/macros from various pointer types to struct
+ * intel_display pointer.
+ */
+#define __drm_device_to_intel_display(p) \
+   (_i915(p)->display)
+#define __intel_connector_to_intel_display(p)  \
+   __drm_device_to_intel_display((p)->base.dev)
+#define __intel_crtc_to_intel_display(p)   \
+   __drm_device_to_intel_display((p)->base.dev)
+#define __intel_crtc_state_to_intel_display(p) \
+   __drm_device_to_intel_display((p)->uapi.crtc->dev)
+#define __intel_digital_port_to_intel_display(p)   \
+   __drm_device_to_intel_display((p)->base.base.dev)
+#define __intel_dp_to_intel_display(p) \
+   __drm_device_to_intel_display(dp_to_dig_port(p)->base.base.dev)
+#define __intel_encoder_to_intel_display(p)\
+   __drm_device_to_intel_display((p)->base.dev)
+#define __intel_hdmi_to_intel_display(p)   \
+   __drm_device_to_intel_display(hdmi_to_dig_port(p)->base.base.dev)
+
+/* Helper for generic association. Map types to conversion functions/macros. */
+#define __assoc(type, p) \
+   struct type: __##type##_to_intel_display((struct type *)(p))
+
+/* Convert various pointer types to struct intel_display pointer. */
+#define to_intel_display(p)\
+   _Generic(*p,\
+__assoc(drm_device, p),\
+__assoc(intel_connector, p),   \
+__assoc(intel_crtc, p),\
+__assoc(intel_crtc_state, p),  \
+__assoc(intel_digital_port, p),\
+__assoc(intel_dp, p),  \
+__assoc(intel_encoder, p), \
+__assoc(intel_hdmi, p))
+
 #endif /*  __INTEL_DISPLAY_TYPES_H__ */
-- 
2.39.2

[PATCH v4 1/9] drm/i915/display: add intel_display -> drm_device backpointer

[Jani Nikula]

As a baby step towards making struct intel_display the main data
structure for display, add a backpointer to struct drm_device that can
be used instead of >drm.

Reviewed-by: Rodrigo Vivi 
Signed-off-by: Jani Nikula 
---
 drivers/gpu/drm/i915/display/intel_display_core.h   | 3 +++
 drivers/gpu/drm/i915/display/intel_display_device.c | 3 +++
 2 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h 
b/drivers/gpu/drm/i915/display/intel_display_core.h
index 9d89828e87df..7715fc329057 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -283,6 +283,9 @@ struct intel_wm {
 };
 
 struct intel_display {
+   /* drm device backpointer */
+   struct drm_device *drm;
+
/* Display functions */
struct {
/* Top level crtc-ish functions */
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c 
b/drivers/gpu/drm/i915/display/intel_display_device.c
index b8903bd0e82a..120e209ee74a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -927,6 +927,9 @@ void intel_display_device_probe(struct drm_i915_private 
*i915)
const struct intel_display_device_info *info;
u16 ver, rel, step;
 
+   /* Add drm device backpointer as early as possible. */
+   i915->display.drm = >drm;
+
if (HAS_GMD_ID(i915))
info = probe_gmdid_display(i915, , , );
else
-- 
2.39.2

[PATCH v4 0/9] drm/i915: better high level abstraction for display

[Jani Nikula]

v4 of [1].

Had to do some rebasing and add some more patches to accommodate dmc
wakelock changes and their impact on intel_de.h. As a byproduct, convert
intel_dmc_wl.[ch] to struct intel_display as well.

With the __to_intel_display() shoved into a separate file, no changes
are needed in xe side this time, could drop a patch, and the macro isn't
duplicated.

BR,
Jani.

[1] https://lore.kernel.org/r/cover.1712665176.git.jani.nik...@intel.com

Jani Nikula (9):
  drm/i915/display: add intel_display -> drm_device backpointer
  drm/i915/display: add generic to_intel_display() macro
  drm/i915: add generic __to_intel_display()
  drm/i915/display: accept either i915 or display for feature tests
  drm/i915/quirks: convert struct drm_i915_private to struct
intel_display
  drm/i915/display: rename __intel_wait_for_register_nowl() to indicate
intel_de_
  drm/i915/dmc: convert dmc wakelock interface to struct intel_display
  drm/i915/de: allow intel_display and drm_i915_private for de functions
  drm/i915/dmc: use struct intel_display more

 .../gpu/drm/i915/display/intel_backlight.c|  40 ++---
 drivers/gpu/drm/i915/display/intel_ddi.c  |   6 +-
 drivers/gpu/drm/i915/display/intel_de.h   | 157 +++---
 .../i915/display/intel_display_conversion.h   |  22 +++
 .../gpu/drm/i915/display/intel_display_core.h |   3 +
 .../drm/i915/display/intel_display_device.c   |   3 +
 .../drm/i915/display/intel_display_device.h   |   5 +-
 .../drm/i915/display/intel_display_driver.c   |   5 +-
 .../i915/display/intel_display_power_well.c   |   6 +-
 .../drm/i915/display/intel_display_types.h|  37 +
 drivers/gpu/drm/i915/display/intel_dmc.c  |   4 +-
 drivers/gpu/drm/i915/display/intel_dmc_wl.c   |  72 
 drivers/gpu/drm/i915/display/intel_dmc_wl.h   |  12 +-
 drivers/gpu/drm/i915/display/intel_panel.c|  10 +-
 drivers/gpu/drm/i915/display/intel_pps.c  |   6 +-
 drivers/gpu/drm/i915/display/intel_quirks.c   |  56 +++
 drivers/gpu/drm/i915/display/intel_quirks.h   |   6 +-
 17 files changed, 275 insertions(+), 175 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_display_conversion.h

-- 
2.39.2

Re: [PATCH v2 04/11] drm/i915/dp_mst: Account for channel coding efficiency in the DSC DPT bpp limit

[Nautiyal, Ankit K]

On 4/17/2024 3:40 AM, Imre Deak wrote:

The DSC DPT interface BW limit check should take into account the link
clock's (aka DDI clock in bspec) channel coding efficiency overhead.
Bspec suggests that the FEC overhead needs to be applied, however HW
people claim this isn't the case, nor is any overhead applicable.

However based on testing various 5k/6k modes both on the DELL U3224KBA
monitor and the Unigraf UCD-500 CTS test device, both the channel coding
efficiency (which includes the FEC overhead) and an additional 3%
overhead must be accounted for to get these modes working.

Bspec: 49259

v2:
- Apply an additional 3% overhead, add a commit log and code comment
   about these overheads and the relation to the Bspec BW limit formula.

Reviewed-by: Ankit Nautiyal  (v1)
Signed-off-by: Imre Deak 
---
  drivers/gpu/drm/i915/display/intel_dp_mst.c | 23 +++--
  1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 58eb6bf33c92e..0448cc343a33f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -59,11 +59,30 @@ static int intel_dp_mst_check_constraints(struct 
drm_i915_private *i915, int bpp
if (intel_dp_is_uhbr(crtc_state) && DISPLAY_VER(i915) < 14 && dsc) {
int output_bpp = bpp;
int symbol_clock = 
intel_dp_link_symbol_clock(crtc_state->port_clock);
+   /*
+* Bspec/49259 suggests that the FEC overhead needs to be
+* applied here, though HW people claim that neither this FEC
+* or any other overhead is applicable here (that is the actual
+* available_bw is just symbol_clock * 72). However based on
+* testing on MTL-P the
+* - DELL U3224KBA display
+* - Unigraf UCD-500 CTS test sink
+* devices the
+* - 5120x2880/995.59Mhz
+* - 6016x3384/1357.23Mhz
+* - 6144x3456/1413.39Mhz
+* modes (all which had a DPT limit on the above devices),

nitpick : all 'of' which

+* both the channel coding efficiency and an additional 3%
+* overhead needs to be accounted for.
+*/
+   int available_bw = mul_u32_u32(symbol_clock * 72,
+  
drm_dp_bw_channel_coding_efficiency(true)) /
+  103;


IMHO, generally overhead of 3% would be better represented by 
multiplying available bandwidth with 97%, but since this is measured to 
be around 3%, this way seems simpler.


Patch looks good to me.

Reviewed-by: Ankit Nautiyal 



  
  		if (output_bpp * adjusted_mode->crtc_clock >

-   symbol_clock * 72) {
+   available_bw) {
drm_dbg_kms(>drm, "UHBR check failed(required bw %d 
available %d)\n",
-   output_bpp * adjusted_mode->crtc_clock, 
symbol_clock * 72);
+   output_bpp * adjusted_mode->crtc_clock, 
available_bw);
return -EINVAL;
}
}

RE: ✗ Fi.CI.BAT: failure for drm/i915: limit eDP MSO pipe only for display version 20 and below (rev4)

[Illipilli, TejasreeX]

Hi,

https://patchwork.freedesktop.org/series/129123/ - Re-reported.

Thanks,
Tejasree

From: I915-ci-infra  On Behalf Of 
Luca Coelho
Sent: Wednesday, April 17, 2024 12:49 PM
To: i915-ci-in...@lists.freedesktop.org
Cc: Coelho, Luciano ; intel-gfx@lists.freedesktop.org
Subject: Re: ✗ Fi.CI.BAT: failure for drm/i915: limit eDP MSO pipe only for 
display version 20 and below (rev4)

Hi,

The skip in igt@kms_cursor_legacy@basic-flip-before-cursor-atomic on 
fi-rkl-11600 is not related to my patch.  There doesn't seem to be any displays 
connected to that machine at the moment and all runs are failing, for example 
the latest run with CI_DRM_14591.

Same thing with the other "new" skips.

Can you please mark my run as not really failing?

--
Cheers,
Luca.


On Tue, 2024-04-16 at 09:54 +, Patchwork wrote:
Patch Details
Series:
drm/i915: limit eDP MSO pipe only for display version 20 and below (rev4)
URL:
https://patchwork.freedesktop.org/series/129123/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/index.html
CI Bug Log - changes from CI_DRM_14583 -> Patchwork_129123v4
Summary

FAILURE

Serious unknown changes coming with Patchwork_129123v4 absolutely need to be
verified manually.

If you think the reported changes have nothing to do with the changes
introduced in Patchwork_129123v4, please notify your bug team 
(i915-ci-in...@lists.freedesktop.org)
 to allow them
to document this new failure mode, which will reduce false positives in CI.

External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/index.html

Participating hosts (37 -> 33)

Additional (4): bat-dg1-7 bat-kbl-2 fi-cfl-8109u bat-arls-2
Missing (8): fi-kbl-7567u fi-apl-guc fi-snb-2520m fi-glk-j4005 bat-atsm-1 
fi-elk-e7500 bat-dg2-11 bat-mtlp-6

Possible new issues

Here are the unknown changes that may have been introduced in 
Patchwork_129123v4:

IGT changes
Possible regressions

  *   igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:

 *   fi-rkl-11600: 
PASS
 -> 
SKIP
 +5 other tests skip

  *   igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24:

 *   fi-rkl-11600: NOTRUN -> 
SKIP
 +11 other tests skip

Warnings

  *   igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:

 *   fi-rkl-11600: 
SKIP
 (i915#4103) -> 
SKIP
 +1 other test skip

  *   igt@kms_dsc@dsc-basic:

 *   fi-rkl-11600: 
SKIP
 (i915#3555 / 
i915#3840) -> 
SKIP

Known issues

Here are the changes found in Patchwork_129123v4 that come from known issues:

IGT changes
Issues hit

  *   igt@debugfs_test@basic-hwmon:

 *   bat-arls-2: NOTRUN -> 
SKIP
 (i915#9318)

  *   igt@fbdev@eof:

 *   fi-rkl-11600: 
PASS
 -> 
SKIP
 (i915#2582) +3 other 
tests skip

  *   igt@fbdev@info:

 *   fi-rkl-11600: 
PASS
 -> 
SKIP
 (i915#1849 / 
i915#2582)
 *   bat-kbl-2: NOTRUN -> 
SKIP
 (i915#1849)

  *   igt@gem_huc_copy@huc-copy:

 *   fi-cfl-8109u: NOTRUN -> 
SKIP
 (i915#2190)

  * 

✓ Fi.CI.BAT: success for drm/i915: limit eDP MSO pipe only for display version 20 and below (rev4)

[Patchwork]

== Series Details ==

Series: drm/i915: limit eDP MSO pipe only for display version 20 and below 
(rev4)
URL   : https://patchwork.freedesktop.org/series/129123/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14583 -> Patchwork_129123v4


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/index.html

Participating hosts (37 -> 33)
--

  Additional (4): bat-dg1-7 bat-kbl-2 fi-cfl-8109u bat-arls-2 
  Missing(8): fi-kbl-7567u fi-apl-guc fi-snb-2520m fi-glk-j4005 bat-atsm-1 
fi-elk-e7500 bat-dg2-11 bat-mtlp-6 

Known issues


  Here are the changes found in Patchwork_129123v4 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-arls-2: NOTRUN -> [SKIP][1] ([i915#9318])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/bat-arls-2/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@eof:
- fi-rkl-11600:   [PASS][2] -> [SKIP][3] ([i915#2582]) +3 other tests 
skip
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14583/fi-rkl-11600/igt@fb...@eof.html
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/fi-rkl-11600/igt@fb...@eof.html

  * igt@fbdev@info:
- fi-rkl-11600:   [PASS][4] -> [SKIP][5] ([i915#1849] / [i915#2582])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14583/fi-rkl-11600/igt@fb...@info.html
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/fi-rkl-11600/igt@fb...@info.html
- bat-kbl-2:  NOTRUN -> [SKIP][6] ([i915#1849])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/bat-kbl-2/igt@fb...@info.html

  * igt@gem_huc_copy@huc-copy:
- fi-cfl-8109u:   NOTRUN -> [SKIP][7] ([i915#2190])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/fi-cfl-8109u/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2:  NOTRUN -> [SKIP][8] +39 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@gem_lmem_swapping@verify-random:
- fi-cfl-8109u:   NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/fi-cfl-8109u/igt@gem_lmem_swapp...@verify-random.html
- bat-arls-2: NOTRUN -> [SKIP][10] ([i915#10213]) +3 other tests 
skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/bat-arls-2/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-dg1-7:  NOTRUN -> [SKIP][11] ([i915#4083])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/bat-dg1-7/igt@gem_m...@basic.html
- bat-arls-2: NOTRUN -> [SKIP][12] ([i915#4083])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/bat-arls-2/igt@gem_m...@basic.html

  * igt@gem_mmap_gtt@basic:
- bat-arls-2: NOTRUN -> [SKIP][13] ([i915#10196] / [i915#4077]) +2 
other tests skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/bat-arls-2/igt@gem_mmap_...@basic.html

  * igt@gem_render_tiled_blits@basic:
- bat-arls-2: NOTRUN -> [SKIP][14] ([i915#10197] / [i915#10211] / 
[i915#4079])
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/bat-arls-2/igt@gem_render_tiled_bl...@basic.html

  * igt@gem_tiled_fence_blits@basic:
- bat-dg1-7:  NOTRUN -> [SKIP][15] ([i915#4077]) +2 other tests skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/bat-dg1-7/igt@gem_tiled_fence_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-dg1-7:  NOTRUN -> [SKIP][16] ([i915#4079]) +1 other test skip
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/bat-dg1-7/igt@gem_tiled_pread_basic.html
- bat-arls-2: NOTRUN -> [SKIP][17] ([i915#10206] / [i915#4079])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/bat-arls-2/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-dg1-7:  NOTRUN -> [SKIP][18] ([i915#6621])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/bat-dg1-7/igt@i915_pm_...@basic-api.html
- bat-arls-2: NOTRUN -> [SKIP][19] ([i915#10209])
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/bat-arls-2/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@hangcheck:
- bat-adls-6: NOTRUN -> [DMESG-WARN][20] ([i915#5591])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/bat-adls-6/igt@i915_selftest@l...@hangcheck.html

  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:
- bat-dg1-7:  NOTRUN -> [SKIP][21] ([i915#4212]) +7 other tests skip
   [21]: 

✓ Fi.CI.BAT: success for drm/i915/hdcp: Disable HDCP Line Rekeying for HDCP2.2 on HDMI (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/hdcp: Disable HDCP Line Rekeying for HDCP2.2 on HDMI (rev3)
URL   : https://patchwork.freedesktop.org/series/132479/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14593 -> Patchwork_132479v3


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132479v3/index.html

Participating hosts (38 -> 36)
--

  Additional (3): fi-kbl-7567u fi-elk-e7500 fi-bsw-n3050 
  Missing(5): bat-dg1-7 bat-arls-3 fi-snb-2520m fi-kbl-8809g bat-mtlp-6 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_132479v3:

### IGT changes ###

 Suppressed 

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@debugfs_test@read_all_entries:
- {bat-mtlp-9}:   [PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14593/bat-mtlp-9/igt@debugfs_test@read_all_entries.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132479v3/bat-mtlp-9/igt@debugfs_test@read_all_entries.html

  
Known issues


  Here are the changes found in Patchwork_132479v3 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-7567u:   NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132479v3/fi-kbl-7567u/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-7567u:   NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132479v3/fi-kbl-7567u/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050:   NOTRUN -> [SKIP][5] +19 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132479v3/fi-bsw-n3050/igt@gem_lmem_swapp...@random-engines.html

  * igt@i915_selftest@live@execlists:
- fi-bsw-n3050:   NOTRUN -> [ABORT][6] ([i915#10594])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132479v3/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-7567u:   NOTRUN -> [SKIP][7] +11 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132479v3/fi-kbl-7567u/igt@kms_force_connector_ba...@force-load-detect.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
- fi-elk-e7500:   NOTRUN -> [SKIP][8] +24 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132479v3/fi-elk-e7500/igt@kms_pm_...@basic-pci-d3-state.html

  
 Possible fixes 

  * igt@i915_selftest@live@gem_contexts:
- bat-arls-2: [TIMEOUT][9] -> [PASS][10]
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14593/bat-arls-2/igt@i915_selftest@live@gem_contexts.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132479v3/bat-arls-2/igt@i915_selftest@live@gem_contexts.html

  * igt@i915_selftest@live@hangcheck:
- bat-adls-6: [DMESG-WARN][11] ([i915#5591]) -> [PASS][12]
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14593/bat-adls-6/igt@i915_selftest@l...@hangcheck.html
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132479v3/bat-adls-6/igt@i915_selftest@l...@hangcheck.html

  * igt@i915_selftest@live@perf:
- bat-dg2-14: [ABORT][13] ([i915#10366] / [i915#10461]) -> 
[PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14593/bat-dg2-14/igt@i915_selftest@l...@perf.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132479v3/bat-dg2-14/igt@i915_selftest@l...@perf.html

  
  {name}: This element is suppressed. This means it is ignored when computing
  the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10366]: https://gitlab.freedesktop.org/drm/intel/issues/10366
  [i915#10461]: https://gitlab.freedesktop.org/drm/intel/issues/10461
  [i915#10594]: https://gitlab.freedesktop.org/drm/intel/issues/10594
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#5591]: https://gitlab.freedesktop.org/drm/intel/issues/5591


Build changes
-

  * Linux: CI_DRM_14593 -> Patchwork_132479v3

  CI-20190529: 20190529
  CI_DRM_14593: 75418ec1fe7737396419e6447005b10e666aeaec @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7810: 189483744e9ff56ea573e07a049c5365404c7ecb @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_132479v3: 75418ec1fe7737396419e6447005b10e666aeaec @ 
git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132479v3/index.html

Re: [PATCH v2 07/11] drm/dp: Add drm_dp_uhbr_channel_coding_supported()

[Imre Deak]

On Wed, Apr 17, 2024 at 12:21:58PM +0300, Jani Nikula wrote:
> On Wed, 17 Apr 2024, Imre Deak  wrote:
> > Factor out a function to check for UHBR channel coding support used by a
> > follow-up patch in the patchset.
> >
> > Cc: dri-de...@lists.freedesktop.org
> > Reviewed-by: Ankit Nautiyal 
> > Reviewed-by: Manasi Navare 
> > Acked-by: Maarten Lankhorst 
> > Signed-off-by: Imre Deak 
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> >  include/drm/display/drm_dp_helper.h | 6 ++
> >  2 files changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 23808e9d41d5d..41127069b55e4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -225,7 +225,7 @@ static void intel_dp_set_dpcd_sink_rates(struct 
> > intel_dp *intel_dp)
> >  * Sink rates for 128b/132b. If set, sink should support all 8b/10b
> >  * rates and 10 Gbps.
> >  */
> > -   if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) 
> > {
> > +   if (drm_dp_uhbr_channel_coding_supported(intel_dp->dpcd)) {
> > u8 uhbr_rates = 0;
> >  
> > BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < 
> > ARRAY_SIZE(dp_rates) + 3);
> > diff --git a/include/drm/display/drm_dp_helper.h 
> > b/include/drm/display/drm_dp_helper.h
> > index baf9949ff96fc..8a64fe8d97af2 100644
> > --- a/include/drm/display/drm_dp_helper.h
> > +++ b/include/drm/display/drm_dp_helper.h
> > @@ -251,6 +251,12 @@ drm_dp_channel_coding_supported(const u8 
> > dpcd[DP_RECEIVER_CAP_SIZE])
> > return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
> >  }
> >  
> > +static inline bool
> > +drm_dp_uhbr_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> > +{
> > +   return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B;
> > +}
> 
> Nitpick, "uhbr channel coding" is not pedantically correct, and it does
> rub me the wrong way.
> 
> Yes, using 128b/132b channel coding implies UHBR, and UHBR requires
> 128b/132b channel coding, but they are not the same thing. We do
> conflate the two quite a bit in the code, checking for UHBR when we
> really mean 128b/132b, but embedding this confusion in the function name
> directly is a bit much.
> 
> I've named the link training functions drm_dp_128b132b_* in the same
> file, and I think this one should be named similarly. Maybe just
> drm_dp_128b132b_supported(), and rename
> drm_dp_channel_coding_supported() to drm_dp_8b10b_supported() to unify?

Ok, makes sense, will rename it to drm_dp_128b132b_supported() and
can do the same - as a follow-up - for 8b10b.

> BR,
> Jani.
> 
> 
> 
> > +
> >  static inline bool
> >  drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> >  {
> 
> -- 
> Jani Nikula, Intel

Re: [PATCH v2 11/11] drm/i915/dp_mst: Enable HBLANK expansion quirk for UHBR rates

[Imre Deak]

On Wed, Apr 17, 2024 at 12:39:40PM +0300, Jani Nikula wrote:
> On Wed, 17 Apr 2024, Imre Deak  wrote:
> > Enabling the 5k@60Hz uncompressed mode on the MediaTek/Dell U3224KBA
> > monitor results in a blank screen, at least on MTL platforms on UHBR
> > link rates with some (<30) uncompressed bpp values. Enabling compression
> > fixes the problem, so do that for now. Windows enables DSC always if the
> > sink supports it and forcing it to enable the mode without compression
> > leads to the same problem above (which suggests a panel issue with
> > uncompressed mode).
> >
> > The same 5k mode on non-UHBR link rates is not affected and lower
> > resolution modes are not affected either. The problem is similar to the
> > one fixed by the HBLANK expansion quirk on Synaptics hubs, with the
> > difference that the problematic mode has a longer HBLANK duration. Also
> > the monitor doesn't report supporting HBLANK expansion; either its
> > internal MST hub does the expansion internally - similarly to the
> > Synaptics hub - or the issue has another root cause, but still related
> > to the mode's short HBLANK duration. Enable the quirk for the monitor
> > adjusting the detection for the above differences.
> >
> > Cc: dri-de...@lists.freedesktop.org
> > Reviewed-by: Ankit Nautiyal 
> > Tested-by: Khaled Almahallawy 
> > Signed-off-by: Imre Deak 
> > ---
> >  drivers/gpu/drm/display/drm_dp_helper.c |  2 ++
> >  drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +
> >  2 files changed, 20 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
> > b/drivers/gpu/drm/display/drm_dp_helper.c
> > index 023907da98581..79a615667aab1 100644
> > --- a/drivers/gpu/drm/display/drm_dp_helper.c
> > +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> > @@ -2281,6 +2281,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
> > { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, 
> > BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
> > /* Synaptics DP1.4 MST hubs require DSC for some modes on which it 
> > applies HBLANK expansion. */
> > { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, 
> > BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
> > +   /* MediaTek panels (at least in U3224KBA) require DSC for modes with a 
> > short HBLANK on UHBR links. */
> > +   { OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, 
> > BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
> > /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low 
> > DP_MAX_LINK_RATE */
> > { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, 
> > BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
> >  };
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index fb5e167c3c659..71b01f7631919 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -421,15 +421,22 @@ static int mode_hblank_period_ns(const struct 
> > drm_display_mode *mode)
> >  
> >  static bool
> >  hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector,
> > -const struct intel_crtc_state *crtc_state)
> > +const struct intel_crtc_state *crtc_state,
> > +const struct link_config_limits *limits)
> >  {
> > const struct drm_display_mode *adjusted_mode =
> > _state->hw.adjusted_mode;
> > +   bool is_uhbr_sink = connector->mst_port &&
> > +   
> > drm_dp_uhbr_channel_coding_supported(connector->mst_port->dpcd);
> 
> Why do you combine connector->mst_port to "is uhbr sink"? I think it's
> confusing.

It is a way to get the DPCD of the root port, to determine if it
supports UHBR.

> > +   int hblank_limit = is_uhbr_sink ? 500 : 300;
> >  
> > if (!connector->dp.dsc_hblank_expansion_quirk)
> > return false;
> >  
> > -   if (mode_hblank_period_ns(adjusted_mode) > 300)
> > +   if (is_uhbr_sink && !drm_dp_is_uhbr_rate(limits->max_rate))
> 
> I'm not saying that's not correct, but I find that condition a bit
> surprising. "This does not apply to sinks capable of 128b/132b, but not
> running at UHBR."
> 
> IOW, this applies to sinks not capable of 128b/132b, and sinks capable
> of 128b/132b and running at UHBR.

Yes, on the particular monitor I tested and enabled the quirk for - DELL
U3224KBA - all the modes work fine in decompressed mode on non-UHBR link
rates, so it remains possible to enable those modes without DSC on non-UHBR
link rates.

> A head scratcher.
> 
> > +   return false;
> > +
> > +   if (mode_hblank_period_ns(adjusted_mode) > hblank_limit)
> > return false;
> >  
> > return true;
> > @@ -445,7 +452,7 @@ adjust_limits_for_dsc_hblank_expansion_quirk(const 
> > struct intel_connector *conne
> > const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > int min_bpp_x16 = 

Re: [PATCH v5 1/4] drm/i915/display: add support for DMC wakelocks

[Jani Nikula]

On Wed, 17 Apr 2024, Luca Coelho  wrote:
> On Wed, 2024-04-17 at 12:42 +0300, Jani Nikula wrote:
>> On Mon, 15 Apr 2024, Luca Coelho  wrote:
>> > Thanks a lot for your reviews! Now I just need to get someone to merge
>> > this series, since I don't have commit rights to the repo yet.
>> 
>> Thanks for the patches and review, merged to drm-intel-next with a
>> slightly heavy heart because it sets me back with [1] in a pretty
>> annoying way. Oh well.
>> 
>> BR,
>> Jani.
>> 
>> [1] 
>> https://lore.kernel.org/r/0b48d6bebfe90aa2f901a05be8279ed887d99d7a.1712665176.git.jani.nik...@intel.com
>
> Oh, no! But you do have cocci and scripts, so it should be easy? Let me
> know if I can help you rebase your change.

The cocci script completely broke apart with the changes. :(

I don't know how to tell it to "first do all these transformations, then
these, and then these" which seems to be necessary.

BR,
Jani.





>
> In any case, thanks for merging my patches!
>
> --
> Cheers,
> Luca.

-- 
Jani Nikula, Intel

RE: [5/6] drm/i915/dp: Enable AUX based backlight for HDR

[Kandpal, Suraj]

> -Original Message-
> From: Sebastian Wick 
> Sent: Wednesday, April 17, 2024 3:54 PM
> To: Kandpal, Suraj 
> Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> ; Shankar, Uma
> ; Nautiyal, Ankit K ;
> Murthy, Arun R ; Nikula, Jani
> ; Kumar, Naveen1 
> Subject: Re: [5/6] drm/i915/dp: Enable AUX based backlight for HDR
> 
> On Wed, Apr 17, 2024 at 04:58:06AM +, Kandpal, Suraj wrote:
> >
> >
> > > -Original Message-
> > > From: Sebastian Wick 
> > > Sent: Tuesday, April 16, 2024 7:10 PM
> > > To: Kandpal, Suraj 
> > > Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> > > ; Shankar, Uma
> > > ; Nautiyal, Ankit K
> > > ; Murthy, Arun R
> > > ; Nikula, Jani ;
> > > Kumar, Naveen1 
> > > Subject: Re: [5/6] drm/i915/dp: Enable AUX based backlight for HDR
> > >
> > > On Thu, Apr 11, 2024 at 11:39:24AM +0530, Suraj Kandpal wrote:
> > > > As of now whenerver HDR is switched on we use the PWM to change
> > > > the backlight as opposed to AUX based backlight changes in terms of
> nits.
> > > > This patch writes to the appropriate DPCD registers to enable aux
> > > > based backlight using values in nits.
> > > >
> > > > --v2
> > > > -Fix max_cll and max_fall assignment [Jani] -Fix the size sent in
> > > > drm_dpcd_write [Jani]
> > > >
> > > > --v3
> > > > -Content Luminance needs to be sent only for pre-ICL after that it
> > > > is directly picked up from hdr metadata [Ville]
> > > >
> > > > --v4
> > > > -Add checks for HDR TCON cap bits [Ville] -Check eotf of
> > > > hdr_output_data and sets bits base of that value.
> > > >
> > > > --v5
> > > > -Fix capability check bits.
> > > > -Check colorspace before setting BT2020
> > > >
> > > > --v6
> > > > -Use intel_dp_has_gamut_dip to check if we have capability to send
> > > > sdp [Ville] -Seprate filling of all hdr tcon related bits into
> > > > it's own function.
> > > > -Check eotf data to make sure we are in HDR mode [Sebastian]
> > > >
> > > > --v7
> > > > -Fix confusion function name for hdr mode check [Jani] -Fix the
> > > > condition which tells us if we are in HDR mode or not [Sebastian]
> > > >
> > > > Signed-off-by: Suraj Kandpal 
> > > > ---
> > > >  .../drm/i915/display/intel_dp_aux_backlight.c | 105
> > > > --
> > > >  1 file changed, 94 insertions(+), 11 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > > index b61bad218994..b13eee250dc4 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > > @@ -40,11 +40,6 @@
> > > >  #include "intel_dp.h"
> > > >  #include "intel_dp_aux_backlight.h"
> > > >
> > > > -/* TODO:
> > > > - * Implement HDR, right now we just implement the bare minimum to
> > > > bring us back into SDR mode so we
> > > > - * can make people's backlights work in the mean time
> > > > - */
> > > > -
> > > >  /*
> > > >   * DP AUX registers for Intel's proprietary HDR backlight interface. We
> define
> > > >   * them here since we'll likely be the only driver to ever use these.
> > > > @@ -127,9 +122,6 @@ intel_dp_aux_supports_hdr_backlight(struct
> > > intel_connector *connector)
> > > > if (ret != sizeof(tcon_cap))
> > > > return false;
> > > >
> > > > -   if (!(tcon_cap[1] & INTEL_EDP_HDR_TCON_BRIGHTNESS_NITS_CAP))
> > > > -   return false;
> > > > -
> > > > drm_dbg_kms(>drm, "[CONNECTOR:%d:%s] Detected %s HDR
> > > backlight interface version %d\n",
> > > > connector->base.base.id, connector->base.name,
> > > > is_intel_tcon_cap(tcon_cap) ? "Intel" : 
> > > > "unsupported",
> > > > tcon_cap[0]); @@ -137,6 +129,9 @@
> > > intel_dp_aux_supports_hdr_backlight(struct intel_connector
> > > *connector)
> > > > if (!is_intel_tcon_cap(tcon_cap))
> > > > return false;
> > > >
> > > > +   if (!(tcon_cap[1] & INTEL_EDP_HDR_TCON_BRIGHTNESS_NITS_CAP))
> > > > +   return false;
> > > > +
> > > > /*
> > > >  * If we don't have HDR static metadata there is no way to
> > > >  * runtime detect used range for nits based control. For now @@
> > > > -225,13 +220,27 @@ intel_dp_aux_hdr_set_aux_backlight(const struct
> > > drm_connector_state *conn_state,
> > > > connector->base.base.id, connector->base.name); 
> > > >  }
> > > >
> > > > +static bool
> > > > +intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state)
> {
> > > > +   struct hdr_output_metadata *hdr_metadata;
> > > > +
> > > > +   if (!conn_state->hdr_output_metadata)
> > > > +   return false;
> > > > +
> > > > +   hdr_metadata = conn_state->hdr_output_metadata->data;
> > > > +
> > > > +   return hdr_metadata->hdmi_metadata_type1.eotf ==
> > > > +HDMI_EOTF_SMPTE_ST2084; }
> > > > +
> > > >  static void
> > > >  

Re: [REBASE 7/7] drm/edid: make drm_edid_are_equal() more convenient for its single user

[Thomas Zimmermann]

Hi

Am 17.04.24 um 10:21 schrieb Jani Nikula:

On Tue, 16 Apr 2024, Thomas Zimmermann  wrote:

Hi

Am 16.04.24 um 14:27 schrieb Jani Nikula:

On Tue, 16 Apr 2024, Thomas Zimmermann  wrote:

Hi

Am 16.04.24 um 11:20 schrieb Jani Nikula:

Repurpose drm_edid_are_equal() to be more helpful for its single user,
and rename drm_edid_eq(). Functionally deduce the length from the blob
size, not the blob data, making it more robust against any errors.

Could be squashed into patch 6.

Ack.

Thanks for the review. I'll hold of on resending these until there are
some R-b's... I've send them a few times already with no comments. :(

Feel free to add

Reviewed-by: Thomas Zimmermann 

to the series.

Many thanks! Just to double check, do you want me to move patch 5
earlier and squash patches 6&7?


Your choice. Either is fine by me.

Best regards
Thomas



BR,
Jani.




--
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)

Re: [5/6] drm/i915/dp: Enable AUX based backlight for HDR

[Sebastian Wick]

On Wed, Apr 17, 2024 at 04:58:06AM +, Kandpal, Suraj wrote:
> 
> 
> > -Original Message-
> > From: Sebastian Wick 
> > Sent: Tuesday, April 16, 2024 7:10 PM
> > To: Kandpal, Suraj 
> > Cc: intel-gfx@lists.freedesktop.org; Borah, Chaitanya Kumar
> > ; Shankar, Uma
> > ; Nautiyal, Ankit K ;
> > Murthy, Arun R ; Nikula, Jani
> > ; Kumar, Naveen1 
> > Subject: Re: [5/6] drm/i915/dp: Enable AUX based backlight for HDR
> > 
> > On Thu, Apr 11, 2024 at 11:39:24AM +0530, Suraj Kandpal wrote:
> > > As of now whenerver HDR is switched on we use the PWM to change the
> > > backlight as opposed to AUX based backlight changes in terms of nits.
> > > This patch writes to the appropriate DPCD registers to enable aux
> > > based backlight using values in nits.
> > >
> > > --v2
> > > -Fix max_cll and max_fall assignment [Jani] -Fix the size sent in
> > > drm_dpcd_write [Jani]
> > >
> > > --v3
> > > -Content Luminance needs to be sent only for pre-ICL after that it is
> > > directly picked up from hdr metadata [Ville]
> > >
> > > --v4
> > > -Add checks for HDR TCON cap bits [Ville] -Check eotf of
> > > hdr_output_data and sets bits base of that value.
> > >
> > > --v5
> > > -Fix capability check bits.
> > > -Check colorspace before setting BT2020
> > >
> > > --v6
> > > -Use intel_dp_has_gamut_dip to check if we have capability to send sdp
> > > [Ville] -Seprate filling of all hdr tcon related bits into it's own
> > > function.
> > > -Check eotf data to make sure we are in HDR mode [Sebastian]
> > >
> > > --v7
> > > -Fix confusion function name for hdr mode check [Jani] -Fix the
> > > condition which tells us if we are in HDR mode or not [Sebastian]
> > >
> > > Signed-off-by: Suraj Kandpal 
> > > ---
> > >  .../drm/i915/display/intel_dp_aux_backlight.c | 105
> > > --
> > >  1 file changed, 94 insertions(+), 11 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > index b61bad218994..b13eee250dc4 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> > > @@ -40,11 +40,6 @@
> > >  #include "intel_dp.h"
> > >  #include "intel_dp_aux_backlight.h"
> > >
> > > -/* TODO:
> > > - * Implement HDR, right now we just implement the bare minimum to
> > > bring us back into SDR mode so we
> > > - * can make people's backlights work in the mean time
> > > - */
> > > -
> > >  /*
> > >   * DP AUX registers for Intel's proprietary HDR backlight interface. We 
> > > define
> > >   * them here since we'll likely be the only driver to ever use these.
> > > @@ -127,9 +122,6 @@ intel_dp_aux_supports_hdr_backlight(struct
> > intel_connector *connector)
> > >   if (ret != sizeof(tcon_cap))
> > >   return false;
> > >
> > > - if (!(tcon_cap[1] & INTEL_EDP_HDR_TCON_BRIGHTNESS_NITS_CAP))
> > > - return false;
> > > -
> > >   drm_dbg_kms(>drm, "[CONNECTOR:%d:%s] Detected %s HDR
> > backlight interface version %d\n",
> > >   connector->base.base.id, connector->base.name,
> > >   is_intel_tcon_cap(tcon_cap) ? "Intel" : "unsupported",
> > > tcon_cap[0]); @@ -137,6 +129,9 @@
> > intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector)
> > >   if (!is_intel_tcon_cap(tcon_cap))
> > >   return false;
> > >
> > > + if (!(tcon_cap[1] & INTEL_EDP_HDR_TCON_BRIGHTNESS_NITS_CAP))
> > > + return false;
> > > +
> > >   /*
> > >* If we don't have HDR static metadata there is no way to
> > >* runtime detect used range for nits based control. For now @@
> > > -225,13 +220,27 @@ intel_dp_aux_hdr_set_aux_backlight(const struct
> > drm_connector_state *conn_state,
> > >   connector->base.base.id, connector->base.name);  }
> > >
> > > +static bool
> > > +intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state) {
> > > + struct hdr_output_metadata *hdr_metadata;
> > > +
> > > + if (!conn_state->hdr_output_metadata)
> > > + return false;
> > > +
> > > + hdr_metadata = conn_state->hdr_output_metadata->data;
> > > +
> > > + return hdr_metadata->hdmi_metadata_type1.eotf ==
> > > +HDMI_EOTF_SMPTE_ST2084; }
> > > +
> > >  static void
> > >  intel_dp_aux_hdr_set_backlight(const struct drm_connector_state
> > > *conn_state, u32 level)  {
> > >   struct intel_connector *connector = to_intel_connector(conn_state-
> > >connector);
> > >   struct intel_panel *panel = >panel;
> > >
> > > - if (panel->backlight.edp.intel.sdr_uses_aux) {
> > > + if (intel_dp_in_hdr_mode(conn_state) ||
> > > + panel->backlight.edp.intel.sdr_uses_aux) {
> > >   intel_dp_aux_hdr_set_aux_backlight(conn_state, level);
> > >   } else {
> > >   const u32 pwm_level =
> > intel_backlight_level_to_pwm(connector,
> > > level); @@ -240,6 +249,70 @@ intel_dp_aux_hdr_set_backlight(const
> > struct drm_connector_state *conn_state, u32
> > >   }
> > >  }
> > >
> > > +static 

[PATCH] drm/i915/hdcp: Disable HDCP Line Rekeying for HDCP2.2 on HDMI

[Suraj Kandpal]

Disable HDCP Line Rekeying when HDCP ver > 1.4 and when we are
on HDMI TMDS operation for DISPLAY_VER >= 14.

--v2
-Wa to be mentioned in comments not in commit message [Jani]
-Remove blankline [Jani]

--v3
-No need to write what is being done in comments when code
is self explanatory [Jani]

Bspec: 49273
Bspec: 69964
Signed-off-by: Suraj Kandpal 
---
 drivers/gpu/drm/i915/display/intel_hdcp.c | 17 +
 drivers/gpu/drm/i915/i915_reg.h   |  1 +
 2 files changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c 
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index d5ed4c7dfbc0..78b20f23a2e1 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -30,6 +30,21 @@
 #define KEY_LOAD_TRIES 5
 #define HDCP2_LC_RETRY_CNT 3
 
+/* WA: 16022217614 */
+static void
+intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder,
+ struct intel_hdcp *hdcp)
+{
+   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+
+   if (encoder->type != INTEL_OUTPUT_HDMI)
+   return;
+
+   if (DISPLAY_VER(dev_priv) >= 14)
+   intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(hdcp->cpu_transcoder),
+TRANS_DDI_HDCP_LINE_REKEY_DISABLE, 1);
+}
+
 static int intel_conn_to_vcpi(struct intel_atomic_state *state,
  struct intel_connector *connector)
 {
@@ -2005,6 +2020,8 @@ static int _intel_hdcp2_enable(struct intel_atomic_state 
*state,
connector->base.base.id, connector->base.name,
hdcp->content_type);
 
+   intel_hdcp_disable_hdcp_line_rekeying(connector->encoder, hdcp);
+
ret = hdcp2_authenticate_and_encrypt(state, connector);
if (ret) {
drm_dbg_kms(>drm, "HDCP2 Type%d  Enabling Failed. (%d)\n",
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f34efcd7d6c..fbf4623cd536 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5630,6 +5630,7 @@ enum skl_power_gate {
 #define  TRANS_DDI_EDP_INPUT_B_ONOFF   (5 << 12)
 #define  TRANS_DDI_EDP_INPUT_C_ONOFF   (6 << 12)
 #define  TRANS_DDI_EDP_INPUT_D_ONOFF   (7 << 12)
+#define  TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12)
 #define  TRANS_DDI_MST_TRANSPORT_SELECT_MASK   REG_GENMASK(11, 10)
 #define  TRANS_DDI_MST_TRANSPORT_SELECT(trans) \
REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans)
-- 
2.43.2

Re: [PATCH v3 4/7] drm/xe/display: add generic __to_intel_display()

[Jani Nikula]

On Tue, 16 Apr 2024, Rodrigo Vivi  wrote:
> On Tue, Apr 09, 2024 at 03:26:46PM +0300, Jani Nikula wrote:
>> Add generic __to_intel_display() macro that accepts either struct
>> xe_device * or struct intel_display *. This is to be used for
>> transitional stuff that eventually needs to be converted to use struct
>> intel_display *, and therefore is not part of to_intel_display().
>> 
>> Signed-off-by: Jani Nikula 
>> ---
>>  drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 11 +++
>>  1 file changed, 11 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h 
>> b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> index 2792a497257e..4448eda8b2a4 100644
>> --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> @@ -29,6 +29,17 @@
>>  #include "intel_runtime_pm.h"
>>  #include 
>>  
>> +/*
>> + * Transitional macro to optionally convert struct xe_device * to struct
>> + * intel_display *, also accepting the latter.
>> + */
>> +#define __to_intel_display(p)   
>> \
>> +_Generic(p, \
>> + const struct xe_device *: (&((const struct xe_device 
>> *)(p))->display), \
>> + struct xe_device *: (&((struct xe_device *)(p))->display), \
>> + const struct intel_display *: (p), \
>> + struct intel_display *: (p))
>
> hmmm... I thought that with our make magic we didn't need this.
> but well, at least more awareness and trying to get rid of the make magic
> earlier?

It's needed because in i915 I wanted to put this in i915_drv.h to not
create a extra dependency to/from i915_drv.h. I tried, it gets tricky.
So weed another copy xe side.

The make magic does convert all struct drm_i915_private to struct
xe_device, so this could have struct drm_i915_private, but the other
copy is not available here.

BR,
Jani.

>
> Reviewed-by: Rodrigo Vivi 
>
>> +
>>  static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
>>  {
>>  return container_of(dev, struct drm_i915_private, drm);
>> -- 
>> 2.39.2
>> 

-- 
Jani Nikula, Intel

Re: [PATCH v5 1/4] drm/i915/display: add support for DMC wakelocks

[Luca Coelho]

On Wed, 2024-04-17 at 12:42 +0300, Jani Nikula wrote:
> On Mon, 15 Apr 2024, Luca Coelho  wrote:
> > Thanks a lot for your reviews! Now I just need to get someone to merge
> > this series, since I don't have commit rights to the repo yet.
> 
> Thanks for the patches and review, merged to drm-intel-next with a
> slightly heavy heart because it sets me back with [1] in a pretty
> annoying way. Oh well.
> 
> BR,
> Jani.
> 
> [1] 
> https://lore.kernel.org/r/0b48d6bebfe90aa2f901a05be8279ed887d99d7a.1712665176.git.jani.nik...@intel.com

Oh, no! But you do have cocci and scripts, so it should be easy? Let me
know if I can help you rebase your change.

In any case, thanks for merging my patches!

--
Cheers,
Luca.

Re: [PATCH v5 1/4] drm/i915/display: add support for DMC wakelocks

[Jani Nikula]

On Mon, 15 Apr 2024, Luca Coelho  wrote:
> Thanks a lot for your reviews! Now I just need to get someone to merge
> this series, since I don't have commit rights to the repo yet.

Thanks for the patches and review, merged to drm-intel-next with a
slightly heavy heart because it sets me back with [1] in a pretty
annoying way. Oh well.

BR,
Jani.

[1] 
https://lore.kernel.org/r/0b48d6bebfe90aa2f901a05be8279ed887d99d7a.1712665176.git.jani.nik...@intel.com


-- 
Jani Nikula, Intel

Re: [PATCH v2 11/11] drm/i915/dp_mst: Enable HBLANK expansion quirk for UHBR rates

[Jani Nikula]

On Wed, 17 Apr 2024, Imre Deak  wrote:
> Enabling the 5k@60Hz uncompressed mode on the MediaTek/Dell U3224KBA
> monitor results in a blank screen, at least on MTL platforms on UHBR
> link rates with some (<30) uncompressed bpp values. Enabling compression
> fixes the problem, so do that for now. Windows enables DSC always if the
> sink supports it and forcing it to enable the mode without compression
> leads to the same problem above (which suggests a panel issue with
> uncompressed mode).
>
> The same 5k mode on non-UHBR link rates is not affected and lower
> resolution modes are not affected either. The problem is similar to the
> one fixed by the HBLANK expansion quirk on Synaptics hubs, with the
> difference that the problematic mode has a longer HBLANK duration. Also
> the monitor doesn't report supporting HBLANK expansion; either its
> internal MST hub does the expansion internally - similarly to the
> Synaptics hub - or the issue has another root cause, but still related
> to the mode's short HBLANK duration. Enable the quirk for the monitor
> adjusting the detection for the above differences.
>
> Cc: dri-de...@lists.freedesktop.org
> Reviewed-by: Ankit Nautiyal 
> Tested-by: Khaled Almahallawy 
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/display/drm_dp_helper.c |  2 ++
>  drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +
>  2 files changed, 20 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_helper.c 
> b/drivers/gpu/drm/display/drm_dp_helper.c
> index 023907da98581..79a615667aab1 100644
> --- a/drivers/gpu/drm/display/drm_dp_helper.c
> +++ b/drivers/gpu/drm/display/drm_dp_helper.c
> @@ -2281,6 +2281,8 @@ static const struct dpcd_quirk dpcd_quirk_list[] = {
>   { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, 
> BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
>   /* Synaptics DP1.4 MST hubs require DSC for some modes on which it 
> applies HBLANK expansion. */
>   { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, 
> BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
> + /* MediaTek panels (at least in U3224KBA) require DSC for modes with a 
> short HBLANK on UHBR links. */
> + { OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, 
> BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
>   /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low 
> DP_MAX_LINK_RATE */
>   { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, 
> BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
>  };
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c 
> b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index fb5e167c3c659..71b01f7631919 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -421,15 +421,22 @@ static int mode_hblank_period_ns(const struct 
> drm_display_mode *mode)
>  
>  static bool
>  hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector,
> -  const struct intel_crtc_state *crtc_state)
> +  const struct intel_crtc_state *crtc_state,
> +  const struct link_config_limits *limits)
>  {
>   const struct drm_display_mode *adjusted_mode =
>   _state->hw.adjusted_mode;
> + bool is_uhbr_sink = connector->mst_port &&
> + 
> drm_dp_uhbr_channel_coding_supported(connector->mst_port->dpcd);

Why do you combine connector->mst_port to "is uhbr sink"? I think it's
confusing.

> + int hblank_limit = is_uhbr_sink ? 500 : 300;
>  
>   if (!connector->dp.dsc_hblank_expansion_quirk)
>   return false;
>  
> - if (mode_hblank_period_ns(adjusted_mode) > 300)
> + if (is_uhbr_sink && !drm_dp_is_uhbr_rate(limits->max_rate))

I'm not saying that's not correct, but I find that condition a bit
surprising. "This does not apply to sinks capable of 128b/132b, but not
running at UHBR."

IOW, this applies to sinks not capable of 128b/132b, and sinks capable
of 128b/132b and running at UHBR.

A head scratcher.

> + return false;
> +
> + if (mode_hblank_period_ns(adjusted_mode) > hblank_limit)
>   return false;
>  
>   return true;
> @@ -445,7 +452,7 @@ adjust_limits_for_dsc_hblank_expansion_quirk(const struct 
> intel_connector *conne
>   const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   int min_bpp_x16 = limits->link.min_bpp_x16;
>  
> - if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state))
> + if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state, limits))
>   return true;
>  
>   if (!dsc) {
> @@ -1604,7 +1611,14 @@ static bool detect_dsc_hblank_expansion_quirk(const 
> struct intel_connector *conn
> DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC))
>   return false;
>  
> - if (!(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE))
> + /*

Re: [PATCH i-g-t v3] lib/kunit: Read results from debugfs

[Kamil Konieczny]

Hi Janusz,
On 2024-04-15 at 19:31:59 +0200, Janusz Krzysztofik wrote:
> KUnit can provide KTAP reports from test modules via debugfs files, one
> per test suite.  Using that source of test results instead of extracting
> them from dmesg, where they may be interleaved with other kernel messages,
> seems more easy to handle and less error prone.  Switch to it.
> 
> If KUnit debugfs support is found not configured then fall back to legacy
> processing path.
> 
> v3: Try to open KUnit debugfs directory before applying KUnit filters we
> use for test case listing, otherwise those skip-all filters applied
> can break legacy path we may enter on missing KUnit debugfs support
> (detected by Kamil).
> v2: Check validity of debugfs argument before calling kunit_get_tests()
> (Kamil),
>   - replace multiple openat() + fdopen/fdopendir(), each followed by an
> error check, with less expensive fopen/opendir() of file/dir pathname
> components concatenated to a local buffer, protected from buffer
> overflow or truncation with a single check for enough buffer space
> (Lucas),
>   - avoid confusing 'if' statement condition (Lucas).
> 
> Signed-off-by: Janusz Krzysztofik 
> Cc: Kamil Konieczny 
> Reviewed-by: Lucas De Marchi 

Thank you for fixing legacy path, it works now.
With this,

Reviewed-by: Kamil Konieczny 

> ---
> @Lucas: I've assumed your R-b still applies, I hope you don't mind.
> 
>  lib/igt_kmod.c | 129 +++--
>  1 file changed, 93 insertions(+), 36 deletions(-)
> 
> diff --git a/lib/igt_kmod.c b/lib/igt_kmod.c
> index 6659c27eba..33f059199f 100644
> --- a/lib/igt_kmod.c
> +++ b/lib/igt_kmod.c
> @@ -28,6 +28,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -39,6 +40,7 @@
>  
>  #include "igt_aux.h"
>  #include "igt_core.h"
> +#include "igt_debugfs.h"
>  #include "igt_kmod.h"
>  #include "igt_ktap.h"
>  #include "igt_sysfs.h"
> @@ -864,6 +866,19 @@ static int open_parameters(const char *module_name)
>   return open(path, O_RDONLY);
>  }
>  
> +static void kunit_debugfs_path(char *kunit_path)
> +{
> + const char *debugfs_path = igt_debugfs_mount();
> +
> + if (igt_debug_on(!debugfs_path))
> + return;
> +
> + if (igt_debug_on(strlen(debugfs_path) + strlen("/kunit/") >= PATH_MAX))
> + return;
> +
> + strcpy(stpcpy(kunit_path, debugfs_path), "/kunit/");
> +}
> +
>  static bool kunit_set_filtering(const char *filter_glob, const char *filter,
>   const char *filter_action)
>  {
> @@ -1071,21 +1086,41 @@ static void kunit_results_free(struct igt_list_head 
> *results,
>   free(*suite_name);
>  }
>  
> -static int kunit_get_results(struct igt_list_head *results, int kmsg_fd,
> -  struct igt_ktap_results **ktap)
> +static int kunit_get_results(struct igt_list_head *results, const char 
> *debugfs_path,
> +  const char *suite, struct igt_ktap_results **ktap)
>  {
> + char results_path[PATH_MAX];
> + FILE *results_stream;
> + char *buf = NULL;
> + size_t size = 0;
> + ssize_t len;
>   int err;
>  
> + if (igt_debug_on(strlen(debugfs_path) + strlen(suite) + 
> strlen("/results") >= PATH_MAX))
> + return -ENOSPC;
> +
> + strcpy(stpcpy(stpcpy(results_path, debugfs_path), suite), "/results");
> + results_stream = fopen(results_path, "r");
> + if (igt_debug_on(!results_stream))
> + return -errno;
> +
>   *ktap = igt_ktap_alloc(results);
> - if (igt_debug_on(!*ktap))
> - return -ENOMEM;
> + if (igt_debug_on(!*ktap)) {
> + err = -ENOMEM;
> + goto out_fclose;
> + }
>  
> - do
> - igt_debug_on((err = kunit_kmsg_result_get(results, NULL, 
> kmsg_fd, *ktap),
> -   err && err != -EINPROGRESS));
> - while (err == -EINPROGRESS);
> + while (len = getline(, , results_stream), len > 0) {
> + err = igt_ktap_parse(buf, *ktap);
> + if (err != -EINPROGRESS)
> + break;
> + }
> +
> + free(buf);
>  
>   igt_ktap_free(ktap);
> +out_fclose:
> + fclose(results_stream);
>  
>   return err;
>  }
> @@ -1101,7 +1136,13 @@ static void __igt_kunit_legacy(struct igt_ktest *tst,
>   pthread_mutexattr_t attr;
>   IGT_LIST_HEAD(results);
>   unsigned long taints;
> - int ret;
> + int flags, ret;
> +
> + igt_skip_on_f(tst->kmsg < 0, "Could not open /dev/kmsg\n");
> +
> + igt_skip_on((flags = fcntl(tst->kmsg, F_GETFL, 0), flags < 0));
> + igt_skip_on_f(fcntl(tst->kmsg, F_SETFL, flags & ~O_NONBLOCK) == -1,
> +   "Could not set /dev/kmsg to blocking mode\n");
>  
>   igt_skip_on(lseek(tst->kmsg, 0, SEEK_END) < 0);
>  
> @@ -1224,30 +1265,21 @@ static void __igt_kunit_legacy(struct igt_ktest *tst,
>   igt_skip_on_f(ret, "KTAP parser 

Re: [PATCH v2 07/11] drm/dp: Add drm_dp_uhbr_channel_coding_supported()

[Jani Nikula]

On Wed, 17 Apr 2024, Imre Deak  wrote:
> Factor out a function to check for UHBR channel coding support used by a
> follow-up patch in the patchset.
>
> Cc: dri-de...@lists.freedesktop.org
> Reviewed-by: Ankit Nautiyal 
> Reviewed-by: Manasi Navare 
> Acked-by: Maarten Lankhorst 
> Signed-off-by: Imre Deak 
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
>  include/drm/display/drm_dp_helper.h | 6 ++
>  2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c 
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 23808e9d41d5d..41127069b55e4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -225,7 +225,7 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp 
> *intel_dp)
>* Sink rates for 128b/132b. If set, sink should support all 8b/10b
>* rates and 10 Gbps.
>*/
> - if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) 
> {
> + if (drm_dp_uhbr_channel_coding_supported(intel_dp->dpcd)) {
>   u8 uhbr_rates = 0;
>  
>   BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < 
> ARRAY_SIZE(dp_rates) + 3);
> diff --git a/include/drm/display/drm_dp_helper.h 
> b/include/drm/display/drm_dp_helper.h
> index baf9949ff96fc..8a64fe8d97af2 100644
> --- a/include/drm/display/drm_dp_helper.h
> +++ b/include/drm/display/drm_dp_helper.h
> @@ -251,6 +251,12 @@ drm_dp_channel_coding_supported(const u8 
> dpcd[DP_RECEIVER_CAP_SIZE])
>   return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
>  }
>  
> +static inline bool
> +drm_dp_uhbr_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> +{
> + return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B;
> +}

Nitpick, "uhbr channel coding" is not pedantically correct, and it does
rub me the wrong way.

Yes, using 128b/132b channel coding implies UHBR, and UHBR requires
128b/132b channel coding, but they are not the same thing. We do
conflate the two quite a bit in the code, checking for UHBR when we
really mean 128b/132b, but embedding this confusion in the function name
directly is a bit much.

I've named the link training functions drm_dp_128b132b_* in the same
file, and I think this one should be named similarly. Maybe just
drm_dp_128b132b_supported(), and rename
drm_dp_channel_coding_supported() to drm_dp_8b10b_supported() to unify?

BR,
Jani.



> +
>  static inline bool
>  drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
>  {

-- 
Jani Nikula, Intel

Re: How to fix Linux CMA on x86 with internal graphic card i915/hda_intel ioremap error?

[Jani Nikula]

On Thu, 28 Mar 2024, "Suesens, Sebastian"  wrote:
> Hello,
>
> I enabled the CMA (CONFIG_CMA=y) for an x86 machine on Linux kernel v5.10 and 
> v5.15 When I boot the system the CMA reserved memory, but when the graphic 
> card driver i915 or hda_intel is loaded the system crashed. 
> I see that ioremap on RAM at 0x - 0xd000 get 
> fail. When I blacklist the i915 and hda_intel module the system boots fine 
> with cma memory reserved.
>
> I think this has something to do with the shared memory which this driver use.
>  
> Does anyone know if a kernel config or something else prevents this crash? 

If you can reproduce this with recent kernels, please file a bug as
described at [1].

BR,
Jani.

[1] https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html

-- 
Jani Nikula, Intel

✓ Fi.CI.BAT: success for Add support for partial mapping (rev8)

[Patchwork]

== Series Details ==

Series: Add support for partial mapping (rev8)
URL   : https://patchwork.freedesktop.org/series/131817/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14592 -> Patchwork_131817v8


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/index.html

Participating hosts (40 -> 40)
--

  Additional (4): fi-glk-j4005 fi-kbl-8809g bat-atsm-1 bat-mtlp-6 
  Missing(4): bat-dg2-11 bat-arls-2 bat-jsl-1 fi-snb-2520m 

Known issues


  Here are the changes found in Patchwork_131817v8 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@debugfs_test@basic-hwmon:
- bat-mtlp-6: NOTRUN -> [SKIP][1] ([i915#9318])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/bat-mtlp-6/igt@debugfs_t...@basic-hwmon.html

  * igt@fbdev@info:
- bat-mtlp-6: NOTRUN -> [SKIP][2] ([i915#1849] / [i915#2582])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/bat-mtlp-6/igt@fb...@info.html

  * igt@fbdev@write:
- bat-mtlp-6: NOTRUN -> [SKIP][3] ([i915#2582]) +3 other tests skip
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/bat-mtlp-6/igt@fb...@write.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-8809g:   NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html
- bat-atsm-1: NOTRUN -> [FAIL][5] ([i915#10563])
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/bat-atsm-1/igt@gem_huc_c...@huc-copy.html
- fi-glk-j4005:   NOTRUN -> [SKIP][6] ([i915#2190])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/fi-glk-j4005/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-glk-j4005:   NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/fi-glk-j4005/igt@gem_lmem_swapp...@basic.html
- fi-kbl-8809g:   NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@verify-random:
- bat-mtlp-6: NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/bat-mtlp-6/igt@gem_lmem_swapp...@verify-random.html

  * igt@gem_mmap@basic:
- bat-atsm-1: NOTRUN -> [SKIP][10] ([i915#4083])
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/bat-atsm-1/igt@gem_m...@basic.html
- bat-mtlp-6: NOTRUN -> [SKIP][11] ([i915#4083])
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/bat-mtlp-6/igt@gem_m...@basic.html

  * igt@gem_tiled_blits@basic:
- bat-mtlp-6: NOTRUN -> [SKIP][12] ([i915#4077]) +2 other tests skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/bat-mtlp-6/igt@gem_tiled_bl...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-atsm-1: NOTRUN -> [SKIP][13] ([i915#4079]) +1 other test skip
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/bat-atsm-1/igt@gem_tiled_pread_basic.html
- bat-mtlp-6: NOTRUN -> [SKIP][14] ([i915#4079]) +1 other test skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/bat-mtlp-6/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-atsm-1: NOTRUN -> [SKIP][15] ([i915#6621])
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/bat-atsm-1/igt@i915_pm_...@basic-api.html
- bat-mtlp-6: NOTRUN -> [SKIP][16] ([i915#6621])
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/bat-mtlp-6/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@gem:
- bat-atsm-1: NOTRUN -> [ABORT][17] ([i915#10182] / [i915#10564])
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/bat-atsm-1/igt@i915_selftest@l...@gem.html

  * igt@i915_selftest@live@migrate:
- bat-dg2-9:  [PASS][18] -> [ABORT][19] ([i915#10366] / 
[i915#10677])
   [18]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14592/bat-dg2-9/igt@i915_selftest@l...@migrate.html
   [19]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/bat-dg2-9/igt@i915_selftest@l...@migrate.html

  * igt@i915_selftest@live@workarounds:
- bat-adlp-9: [PASS][20] -> [INCOMPLETE][21] ([i915#9413])
   [20]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14592/bat-adlp-9/igt@i915_selftest@l...@workarounds.html
   [21]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_131817v8/bat-adlp-9/igt@i915_selftest@l...@workarounds.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-mtlp-6: NOTRUN -> [SKIP][22] ([i915#4212] / 

✗ Fi.CI.CHECKPATCH: warning for Add support for partial mapping (rev8)

[Patchwork]

== Series Details ==

Series: Add support for partial mapping (rev8)
URL   : https://patchwork.freedesktop.org/series/131817/
State : warning

== Summary ==

Error: dim checkpatch failed
ab5423884e51 drm/i915/gem: Increment vma offset when mapping fb objects
392a8980f647 drm/i915/gem: Do not look for the exact address in node
3605f2de13e5 drm/i915/gem: Calculate object page offset for partial memory 
mapping
-:67: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#67: FILE: drivers/gpu/drm/i915/gem/i915_gem_mman.c:411:
+  area->vm_start + ((vma->gtt_view.partial.offset 
- obj_offset) << PAGE_SHIFT),

total: 0 errors, 1 warnings, 0 checks, 82 lines checked

Re: [PATCH v4] drm/i915/hwmon: Get rid of devm

[Andi Shyti]

Hi Ashutosh,

> @@ -839,16 +837,38 @@ void i915_hwmon_register(struct drm_i915_private *i915)
>   if (!hwm_gt_is_visible(ddat_gt, hwmon_energy, 
> hwmon_energy_input, 0))
>   continue;
>  
> - hwmon_dev = devm_hwmon_device_register_with_info(dev, 
> ddat_gt->name,
> -  ddat_gt,
> -  
> _gt_chip_info,
> -  NULL);
> - if (!IS_ERR(hwmon_dev))
> - ddat_gt->hwmon_dev = hwmon_dev;
> + hwmon_dev = hwmon_device_register_with_info(dev, ddat_gt->name,
> + ddat_gt,
> + _gt_chip_info,
> + NULL);
> + if (IS_ERR(hwmon_dev))
> + goto err;

here the logic is changing, though. Before we were not leaving if
hwmon_device_register_with_info() was returning error.

Is this wanted? And why isn't it described in the log?

Thanks,
Andi

> +
> + ddat_gt->hwmon_dev = hwmon_dev;
>   }

Re: [REBASE 7/7] drm/edid: make drm_edid_are_equal() more convenient for its single user

[Jani Nikula]

On Tue, 16 Apr 2024, Thomas Zimmermann  wrote:
> Hi
>
> Am 16.04.24 um 14:27 schrieb Jani Nikula:
>> On Tue, 16 Apr 2024, Thomas Zimmermann  wrote:
>>> Hi
>>>
>>> Am 16.04.24 um 11:20 schrieb Jani Nikula:
 Repurpose drm_edid_are_equal() to be more helpful for its single user,
 and rename drm_edid_eq(). Functionally deduce the length from the blob
 size, not the blob data, making it more robust against any errors.
>>> Could be squashed into patch 6.
>> Ack.
>>
>> Thanks for the review. I'll hold of on resending these until there are
>> some R-b's... I've send them a few times already with no comments. :(
>
> Feel free to add
>
> Reviewed-by: Thomas Zimmermann 
>
> to the series.

Many thanks! Just to double check, do you want me to move patch 5
earlier and squash patches 6&7?

BR,
Jani.


-- 
Jani Nikula, Intel

✗ Fi.CI.BAT: failure for drm/i915/hwmon: Get rid of devm (rev5)

[Patchwork]

== Series Details ==

Series: drm/i915/hwmon: Get rid of devm (rev5)
URL   : https://patchwork.freedesktop.org/series/132400/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_14592 -> Patchwork_132400v5


Summary
---

  **FAILURE**

  Serious unknown changes coming with Patchwork_132400v5 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_132400v5, please notify your bug team 
(i915-ci-in...@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v5/index.html

Participating hosts (40 -> 36)
--

  Additional (1): bat-atsm-1 
  Missing(5): fi-bsw-n3050 fi-snb-2520m fi-elk-e7500 bat-jsl-1 bat-arls-3 

Possible new issues
---

  Here are the unknown changes that may have been introduced in 
Patchwork_132400v5:

### IGT changes ###

 Possible regressions 

  * igt@i915_pm_rpm@module-reload:
- bat-arls-2: [PASS][1] -> [ABORT][2]
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14592/bat-arls-2/igt@i915_pm_...@module-reload.html
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v5/bat-arls-2/igt@i915_pm_...@module-reload.html

  
Known issues


  Here are the changes found in Patchwork_132400v5 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@gem_huc_copy@huc-copy:
- bat-atsm-1: NOTRUN -> [FAIL][3] ([i915#10563])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v5/bat-atsm-1/igt@gem_huc_c...@huc-copy.html

  * igt@gem_mmap@basic:
- bat-atsm-1: NOTRUN -> [SKIP][4] ([i915#4083])
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v5/bat-atsm-1/igt@gem_m...@basic.html

  * igt@gem_tiled_pread_basic:
- bat-atsm-1: NOTRUN -> [SKIP][5] ([i915#4079]) +1 other test skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v5/bat-atsm-1/igt@gem_tiled_pread_basic.html

  * igt@i915_pm_rps@basic-api:
- bat-atsm-1: NOTRUN -> [SKIP][6] ([i915#6621])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v5/bat-atsm-1/igt@i915_pm_...@basic-api.html

  * igt@i915_selftest@live@gem:
- bat-atsm-1: NOTRUN -> [ABORT][7] ([i915#10182] / [i915#10564])
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v5/bat-atsm-1/igt@i915_selftest@l...@gem.html

  * igt@kms_addfb_basic@size-max:
- bat-atsm-1: NOTRUN -> [SKIP][8] ([i915#6077]) +37 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v5/bat-atsm-1/igt@kms_addfb_ba...@size-max.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- bat-atsm-1: NOTRUN -> [SKIP][9] ([i915#6078]) +22 other tests skip
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v5/bat-atsm-1/igt@kms_cursor_leg...@basic-flip-after-cursor-atomic.html

  * igt@kms_force_connector_basic@prune-stale-modes:
- bat-atsm-1: NOTRUN -> [SKIP][10] ([i915#6093]) +4 other tests skip
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v5/bat-atsm-1/igt@kms_force_connector_ba...@prune-stale-modes.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24:
- bat-atsm-1: NOTRUN -> [SKIP][11] ([i915#1836]) +6 other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v5/bat-atsm-1/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-xr24.html

  * igt@kms_prop_blob@basic:
- bat-atsm-1: NOTRUN -> [SKIP][12] ([i915#7357])
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v5/bat-atsm-1/igt@kms_prop_b...@basic.html

  * igt@kms_setmode@basic-clone-single-crtc:
- bat-atsm-1: NOTRUN -> [SKIP][13] ([i915#6094])
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v5/bat-atsm-1/igt@kms_setm...@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-mmap:
- bat-atsm-1: NOTRUN -> [SKIP][14] ([i915#4077]) +4 other tests skip
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v5/bat-atsm-1/igt@prime_v...@basic-fence-mmap.html

  * igt@prime_vgem@basic-write:
- bat-atsm-1: NOTRUN -> [SKIP][15] +2 other tests skip
   [15]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v5/bat-atsm-1/igt@prime_v...@basic-write.html

  
 Possible fixes 

  * igt@i915_module_load@load:
- bat-dg2-9:  [DMESG-WARN][16] ([i915#10014]) -> [PASS][17]
   [16]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14592/bat-dg2-9/igt@i915_module_l...@load.html
   [17]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132400v5/bat-dg2-9/igt@i915_module_l...@load.html

  * igt@i915_selftest@live@hugepages:
- fi-apl-guc: [ABORT][18] 

Re: ✗ Fi.CI.BAT: failure for drm/i915: limit eDP MSO pipe only for display version 20 and below (rev4)

[Luca Coelho]

Hi,

The skip in igt@kms_cursor_legacy@basic-flip-before-cursor-atomic on
fi-rkl-11600 is not related to my patch.  There doesn't seem to be any
displays connected to that machine at the moment and all runs are
failing, for example the latest run with CI_DRM_14591.

Same thing with the other "new" skips.

Can you please mark my run as not really failing?

--
Cheers,
Luca.


On Tue, 2024-04-16 at 09:54 +, Patchwork wrote:
> Patch Details
> Series:drm/i915: limit eDP MSO pipe only for display version 20 and
> below (rev4)
> URL:https://patchwork.freedesktop.org/series/129123/
> State:failure
> Details:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_129123v4/index.html
> CI Bug Log - changes from CI_DRM_14583 -> Patchwork_129123v4SummaryFAILURE
> Serious unknown changes coming with Patchwork_129123v4 absolutely
> need to be
> verified manually.
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_129123v4, please notify your bug team (I915-
> ci-in...@lists.freedesktop.org) to allow them
> to document this new failure mode, which will reduce false positives
> in CI.
> External URL: https://intel-gfx-ci.01.org/tree/drm-
> tip/Patchwork_129123v4/index.html
> Participating hosts (37 -> 33)Additional (4): bat-dg1-7 bat-kbl-2 
> fi-cfl-8109u bat-arls-2 
> Missing (8): fi-kbl-7567u fi-apl-guc fi-snb-2520m fi-glk-j4005 bat-
> atsm-1 fi-elk-e7500 bat-dg2-11 bat-mtlp-6 
> Possible new issuesHere are the unknown changes that may have been introduced 
> in
> Patchwork_129123v4:
> IGT changesPossible regressions * 
> igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:fi-rkl-11600:
>PASS -> SKIP +5 other tests skip
>  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24:fi-rkl-11600:
>NOTRUN -> SKIP +11 other tests skip
> Warnings * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:fi-rkl-
>11600: SKIP (i915#4103) -> SKIP +1 other test skip
>  * igt@kms_dsc@dsc-basic:fi-rkl-11600: SKIP (i915#3555 / i915#3840) ->
>SKIP
> Known issuesHere are the changes found in Patchwork_129123v4 that come from 
> known
> issues:
> IGT changesIssues hit * igt@debugfs_test@basic-hwmon:bat-arls-2: NOTRUN -> 
> SKIP (i915#9318)
>  * igt@fbdev@eof:fi-rkl-11600: PASS -> SKIP (i915#2582) +3 other tests
>skip
>  * igt@fbdev@info:fi-rkl-11600: PASS -> SKIP (i915#1849 /
>i915#2582)bat-kbl-2: NOTRUN -> SKIP (i915#1849)
>  * igt@gem_huc_copy@huc-copy:fi-cfl-8109u: NOTRUN -> SKIP (i915#2190)
>  * igt@gem_lmem_swapping@parallel-random-engines:bat-kbl-2: NOTRUN ->
>SKIP +39 other tests skip
>  * igt@gem_lmem_swapping@verify-random:fi-cfl-8109u: NOTRUN -> SKIP
>(i915#4613) +3 other tests skipbat-arls-2: NOTRUN -> SKIP
>(i915#10213) +3 other tests skip
>  * igt@gem_mmap@basic:bat-dg1-7: NOTRUN -> SKIP (i915#4083)bat-arls-2:
>NOTRUN -> SKIP (i915#4083)
>  * igt@gem_mmap_gtt@basic:bat-arls-2: NOTRUN -> SKIP (i915#10196 /
>i915#4077) +2 other tests skip
>  * igt@gem_render_tiled_blits@basic:bat-arls-2: NOTRUN -> SKIP
>(i915#10197 / i915#10211 / i915#4079)
>  * igt@gem_tiled_fence_blits@basic:bat-dg1-7: NOTRUN -> SKIP
>(i915#4077) +2 other tests skip
>  * igt@gem_tiled_pread_basic:bat-dg1-7: NOTRUN -> SKIP (i915#4079) +1
>other test skipbat-arls-2: NOTRUN -> SKIP (i915#10206 / i915#4079)
>  * igt@i915_pm_rps@basic-api:bat-dg1-7: NOTRUN -> SKIP (i915#6621)bat-
>arls-2: NOTRUN -> SKIP (i915#10209)
>  * igt@i915_selftest@live@hangcheck:bat-adls-6: NOTRUN -> DMESG-WARN
>(i915#5591)
>  * igt@kms_addfb_basic@addfb25-x-tiled-mismatch-legacy:bat-dg1-7:
>NOTRUN -> SKIP (i915#4212) +7 other tests skip
>  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:bat-arls-2: NOTRUN
>-> SKIP (i915#10200) +9 other tests skip
>  * igt@kms_addfb_basic@basic-y-tiled-legacy:bat-dg1-7: NOTRUN -> SKIP
>(i915#4215)
>  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:bat-arls-
>2: NOTRUN -> SKIP (i915#10202) +1 other test skipbat-dg1-7: NOTRUN -
>> SKIP (i915#4103 / i915#4213) +1 other test skip
>  * igt@kms_dsc@dsc-basic:bat-arls-2: NOTRUN -> SKIP (i915#9886)bat-dg1-
>7: NOTRUN -> SKIP (i915#3555 / i915#3840)
>  * igt@kms_force_connector_basic@force-load-detect:bat-arls-2: NOTRUN -
>> SKIP (i915#10207)bat-dg1-7: NOTRUN -> SKIP
>  * igt@kms_frontbuffer_tracking@basic:fi-rkl-11600: PASS -> SKIP
>(i915#1849 / i915#5354)
>  * igt@kms_hdmi_inject@inject-audio:bat-dg1-7: NOTRUN -> SKIP
>(i915#433)
>  * igt@kms_pm_backlight@basic-brightness:bat-dg1-7: NOTRUN -> SKIP
>(i915#5354)fi-cfl-8109u: NOTRUN -> SKIP +11 other tests skip
>  * igt@kms_psr@psr-primary-mmap-gtt@edp-1:bat-arls-2: NOTRUN -> SKIP
>(i915#10196 / i915#4077 / i915#9688)
>  * igt@kms_psr@psr-primary-page-flip:bat-dg1-7: NOTRUN -> SKIP
>(i915#1072 / i915#9732) +3 other tests skip
>  * igt@kms_setmode@basic-clone-single-crtc:bat-arls-2: NOTRUN -> SKIP
>(i915#10208 / i915#8809)bat-dg1-7: NOTRUN -> SKIP (i915#3555)
>  * 

✓ Fi.CI.BAT: success for drm/i915/pps: Disable DPLS_GATING around pps sequence (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/pps: Disable DPLS_GATING around pps sequence (rev2)
URL   : https://patchwork.freedesktop.org/series/132495/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_14591 -> Patchwork_132495v2


Summary
---

  **SUCCESS**

  No regressions found.

  External URL: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132495v2/index.html

Participating hosts (39 -> 37)
--

  Additional (3): fi-kbl-7567u bat-kbl-2 fi-kbl-8809g 
  Missing(5): bat-dg1-7 bat-mtlp-9 fi-snb-2520m fi-cfl-8109u bat-jsl-1 

Known issues


  Here are the changes found in Patchwork_132495v2 that come from known issues:

### IGT changes ###

 Issues hit 

  * igt@fbdev@info:
- bat-kbl-2:  NOTRUN -> [SKIP][1] ([i915#1849])
   [1]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132495v2/bat-kbl-2/igt@fb...@info.html

  * igt@gem_huc_copy@huc-copy:
- fi-kbl-7567u:   NOTRUN -> [SKIP][2] ([i915#2190])
   [2]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132495v2/fi-kbl-7567u/igt@gem_huc_c...@huc-copy.html
- fi-kbl-8809g:   NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132495v2/fi-kbl-8809g/igt@gem_huc_c...@huc-copy.html

  * igt@gem_lmem_swapping@basic:
- fi-kbl-7567u:   NOTRUN -> [SKIP][4] ([i915#4613]) +3 other tests skip
   [4]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132495v2/fi-kbl-7567u/igt@gem_lmem_swapp...@basic.html
- fi-kbl-8809g:   NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
   [5]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132495v2/fi-kbl-8809g/igt@gem_lmem_swapp...@basic.html

  * igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-9:  [PASS][6] -> [FAIL][7] ([i915#10378])
   [6]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14591/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html
   [7]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132495v2/bat-dg2-9/igt@gem_lmem_swapping@ba...@lmem0.html

  * igt@gem_lmem_swapping@parallel-random-engines:
- bat-kbl-2:  NOTRUN -> [SKIP][8] +39 other tests skip
   [8]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132495v2/bat-kbl-2/igt@gem_lmem_swapp...@parallel-random-engines.html

  * igt@i915_selftest@live@guc_multi_lrc:
- bat-dg2-11: [PASS][9] -> [ABORT][10] ([i915#10366])
   [9]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14591/bat-dg2-11/igt@i915_selftest@live@guc_multi_lrc.html
   [10]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132495v2/bat-dg2-11/igt@i915_selftest@live@guc_multi_lrc.html

  * igt@kms_force_connector_basic@force-load-detect:
- fi-kbl-7567u:   NOTRUN -> [SKIP][11] +11 other tests skip
   [11]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132495v2/fi-kbl-7567u/igt@kms_force_connector_ba...@force-load-detect.html
- fi-kbl-8809g:   NOTRUN -> [SKIP][12] +30 other tests skip
   [12]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132495v2/fi-kbl-8809g/igt@kms_force_connector_ba...@force-load-detect.html

  
 Possible fixes 

  * igt@i915_selftest@live@execlists:
- bat-adls-6: [TIMEOUT][13] ([i915#10795]) -> [PASS][14]
   [13]: 
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14591/bat-adls-6/igt@i915_selftest@l...@execlists.html
   [14]: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132495v2/bat-adls-6/igt@i915_selftest@l...@execlists.html

  
  [i915#10366]: https://gitlab.freedesktop.org/drm/intel/issues/10366
  [i915#10378]: https://gitlab.freedesktop.org/drm/intel/issues/10378
  [i915#10795]: https://gitlab.freedesktop.org/drm/intel/issues/10795
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613


Build changes
-

  * Linux: CI_DRM_14591 -> Patchwork_132495v2

  CI-20190529: 20190529
  CI_DRM_14591: 6eb009a883a7ae925b3b0f0363b64a026bb4333a @ 
git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7809: 3a71f659700859cab49b8e05a198ba18a5cbd24a @ 
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_132495v2: 6eb009a883a7ae925b3b0f0363b64a026bb4333a @ 
git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

271248c2b436 drm/i915/pps: Disable DPLS_GATING around pps sequence

== Logs ==

For more details see: 
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_132495v2/index.html