Re: [PULL] drm-intel-gt-next
On Thu, 15 Feb 2024 at 20:06, Tvrtko Ursulin wrote: > > Hi Dave, Daniel, > > First pull request for 6.9 with probably one more coming in one to two > weeks. > > Nothing to interesting in this one, mostly a sprinkle of small fixes in > GuC, HuC, Perf/OA, a tiny bit of prep work for future platforms and some > code cleanups. > > One new uapi in the form of a GuC submission version query which Mesa > wants for implementing Vulkan async compute queues. > > Regards, > > Tvrtko > > drm-intel-gt-next-2024-02-15: > UAPI Changes: > > - Add GuC submission interface version query (Tvrtko Ursulin) > > Driver Changes: > > Fixes/improvements/new stuff: > > - Atomically invalidate userptr on mmu-notifier (Jonathan Cavitt) I've pulled this, but the above patch is triggering my this seems wrong spider sense. This and probably the preceeding patch that this references seem to move i915 to a long term pinning of userptr in memory with what I can see no accounting, and away from what the desired behaviour for drivers should be. It also feels like the authorship on this might be lies which also worries me. Dave.
Re: [Intel-gfx] [RFC PATCH 0/6] Supporting GMEM (generalized memory management) for external memory devices
On Tue, 28 Nov 2023 at 23:07, Christian König wrote: > > Am 28.11.23 um 13:50 schrieb Weixi Zhu: > > The problem: > > > > Accelerator driver developers are forced to reinvent external MM subsystems > > case by case, because Linux core MM only considers host memory resources. > > These reinvented MM subsystems have similar orders of magnitude of LoC as > > Linux MM (80K), e.g. Nvidia-UVM has 70K, AMD GPU has 14K and Huawei NPU has > > 30K. Meanwhile, more and more vendors are implementing their own > > accelerators, e.g. Microsoft's Maia 100. At the same time, > > application-level developers suffer from poor programmability -- they must > > consider parallel address spaces and be careful about the limited device > > DRAM capacity. This can be alleviated if a malloc()-ed virtual address can > > be shared by the accelerator, or the abundant host DRAM can further > > transparently backup the device local memory. > > > > These external MM systems share similar mechanisms except for the > > hardware-dependent part, so reinventing them is effectively introducing > > redundant code (14K~70K for each case). Such developing/maintaining is not > > cheap. Furthermore, to share a malloc()-ed virtual address, device drivers > > need to deeply interact with Linux MM via low-level MM APIs, e.g. MMU > > notifiers/HMM. This raises the bar for driver development, since developers > > must understand how Linux MM works. Further, it creates code maintenance > > problems -- any changes to Linux MM potentially require coordinated changes > > to accelerator drivers using low-level MM APIs. > > > > Putting a cache-coherent bus between host and device will not make these > > external MM subsystems disappear. For example, a throughput-oriented > > accelerator will not tolerate executing heavy memory access workload with > > a host MMU/IOMMU via a remote bus. Therefore, devices will still have > > their own MMU and pick a simpler page table format for lower address > > translation overhead, requiring external MM subsystems. > > > > > > > > What GMEM (Generalized Memory Management [1]) does: > > > > GMEM extends Linux MM to share its machine-independent MM code. Only > > high-level interface is provided for device drivers. This prevents > > accelerator drivers from reinventing the wheel, but relies on drivers to > > implement their hardware-dependent functions declared by GMEM. GMEM's key > > interface include gm_dev_create(), gm_as_create(), gm_as_attach() and > > gm_dev_register_physmem(). Here briefly describe how a device driver > > utilizes them: > > 1. At boot time, call gm_dev_create() and registers the implementation of > > hardware-dependent functions as declared in struct gm_mmu. > > - If the device has local DRAM, call gm_dev_register_physmem() to > > register available physical addresses. > > 2. When a device context is initialized (e.g. triggered by ioctl), check if > > the current CPU process has been attached to a gmem address space > > (struct gm_as). If not, call gm_as_create() and point current->mm->gm_as > > to it. > > 3. Call gm_as_attach() to attach the device context to a gmem address space. > > 4. Invoke gm_dev_fault() to resolve a page fault or prepare data before > > device computation happens. > > > > GMEM has changed the following assumptions in Linux MM: > >1. An mm_struct not only handle a single CPU context, but may also handle > > external memory contexts encapsulated as gm_context listed in > > mm->gm_as. An external memory context can include a few or all of the > > following parts: an external MMU (that requires TLB invalidation), an > > external page table (that requires PTE manipulation) and external DRAM > > (that requires physical memory management). > > Well that is pretty much exactly what AMD has already proposed with KFD > and was rejected for rather good reasons. > > > > MMU functions > > The MMU functions peer_map() and peer_unmap() overlap other functions, > > leaving a question if the MMU functions should be decoupled as more basic > > operations. Decoupling them could potentially prevent device drivers > > coalescing these basic steps within a single host-device communication > > operation, while coupling them makes it more difficult for device drivers > > to utilize GMEM interface. > > Well to be honest all of this sounds like history to me. We have already > seen the same basic approach in KFD, HMM and to some extend in TTM as well. > > And all of them more or less failed. Why should this here be different? Any info we have on why this has failed to work in the past would be useful to provide. This is one of those cases where we may not have documented the bad ideas to stop future developers from thinking they are bad. I do think we would want more common code in this area, but I would think we'd have it more on the driver infrastructure side, than in the core mm. Dave.
Re: [Intel-gfx] Build broken in drm-tip
On Tue, 31 Oct 2023 at 15:23, Dave Airlie wrote: > > On Tue, 31 Oct 2023 at 15:09, Borah, Chaitanya Kumar > wrote: > > > > Hello Mario, > > > > This is Chaitanya from the Linux graphics team in Intel. > > > > We are seeing a build issue in drm-tip[1] > > Sorry that was a mismerge from me, let me go fix it for summon someone else. Should be fixed now. sorry for noise, Dave.
Re: [Intel-gfx] Build broken in drm-tip
On Tue, 31 Oct 2023 at 15:09, Borah, Chaitanya Kumar wrote: > > Hello Mario, > > This is Chaitanya from the Linux graphics team in Intel. > > We are seeing a build issue in drm-tip[1] Sorry that was a mismerge from me, let me go fix it for summon someone else. Dave.
Re: [Intel-gfx] [PATCH 02/11] drm/i915/mst: Remove broken MST DSC support
On Wed, 3 May 2023 at 22:23, Lisovskiy, Stanislav wrote: > > On Wed, May 03, 2023 at 02:07:04PM +0300, Ville Syrjälä wrote: > > On Wed, May 03, 2023 at 10:36:42AM +0300, Lisovskiy, Stanislav wrote: > > > On Tue, May 02, 2023 at 05:38:57PM +0300, Ville Syrjala wrote: > > > > From: Ville Syrjälä > > > > > > > > The MST DSC code has a myriad of issues: > > > > - Platform checks are wrong (MST+DSC is TGL+ only IIRC) > > > > - Return values of .mode_valid_ctx() are wrong > > > > - .mode_valid_ctx() assumes bigjoiner might be used, but ther rest > > > > of the code doesn't agree > > > > - compressed bpp calculations don't make sense > > > > - FEC handling needs to consider the entire link as opposed to just > > > > the single stream. Currently FEC would only get enabled if the > > > > first enabled stream is compressed. Also I'm not seeing anything > > > > that would account for the FEC overhead in any bandwidth calculations > > > > - PPS SDP is only handled for the first stream via the dig_port > > > > hooks, other streams will not be transmittitng any PPS SDPs > > > > - PPS SDP readout is missing (also missing for SST!) > > > > - VDSC readout is missing (also missing for SST!) > > > > > > > > The FEC issues is really the big one since we have no way currently > > > > to apply such link wide configuration constraints. Changing that is > > > > going to require a much bigger rework of the higher level modeset > > > > .compute_config() logic. We will also need such a rework to properly > > > > distribute the available bandwidth across all the streams on the > > > > same link (which is a must to eg. enable deep color). > > > > > > Also all the things you mentioned are subject for discussion, for example > > > I see that FEC overhead is actually accounted for bpp calculation for > > > instance. > > > > AFAICS FEC is only accounted for in the data M/N calculations, > > assuming that particular stream happened to be compressed. I'm > > not sure if that actually matters since at least the link M/N > > are not even used by the MST sink. I suppose the data M/N might > > still be used for something though. For any uncompressed stream > > on the same link the data M/N values will be calculated > > incorrectly without FEC. > > > > And as mentioned, the FEC bandwidth overhead doesn't seem to > > be accounted anywhere so no guarantee that we won't try to > > oversubcribe the link. > > > > And FEC will only be enabled if the first stream to be enabled > > is compressed, otherwise we will enable the link without FEC > > and still try to cram other compressed streams through it > > (albeit without the PPS SDP so who knows what will happen) > > and that is illegal. > > > > > We usually improve things by gradually fixing, because if we act same way > > > towards > > > all wrong code in the driver, we could end up removing the whole i915. > > > > We ususally don't merge code that has this many obvious and/or > > fundemental issues. > > Well, this is arguable and subjective judgement. Fact is that, so far we had > more MST hubs > working with that code than without. Also no regressions or anything like > that. > Moreover we usually merge code after code review, in particular those patches > did spend lots of time in review, where you could comment also. > > Regarding merging code with fundamental issues, just recently you had > admitted yourself > that bigjoiner issue for instance, we had recently, was partly caused by your > code, because > we don't anymore copy the pll state to slave crtc. > I would say that words like "obvious" and "fundamental" > issues can be applied to many things, however I thought that we always fix > things in constructive, > but not destructive/negative way. > Should I call also all code completely broken and remove it, once we discover > some flaws > there? Oh, we had many regressions, where I could say the same. > > And once again I'm completely okay, if you did introduce better functionality > instead > AND I know you have some valid points there, but now we are just removing > everything completely, > without providing anything better. > > But okay, I've mentioned what I think about this and from side this is nak. > And once the guys to whom those patches helped will pop up from gitlab, > asking why their MST hubs stopped working - I will just refer them here. > > > > > Now, most of the issues I listed above are probably fixable > > in a way that could be backported to stable kernels, but > > unfortunately the FEC issue is not one of those. That one > > will likely need massive amounts of work all over the driver > > modeset code, making a backport impossible. > > > > > So from my side I would nack it, at least until you have a code which > > > handles > > > all of this better - I have no doubt you probably have some ideas in your > > > mind, so lets be constructive at least and propose something better first. > > > This code doesn't cause any regressions, but still provides
Re: [Intel-gfx] [PATCH 6/9] drm/qxl: stop using ttm_bo_wait
Acked-by: Dave Airlie
On Fri, 16 Dec 2022 at 00:20, Christian König
wrote:
>
> Am 25.11.22 um 11:21 schrieb Christian König:
> > TTM is just wrapping core DMA functionality here, remove the mid-layer.
> > No functional change.
>
> Any objections to this guys?
>
> I'm basically just following a suggestion from Daniel here and it
> already triggered a discussion about the timeout for i915.
>
> Thanks,
> Christian.
>
> >
> > Signed-off-by: Christian König
> > ---
> > drivers/gpu/drm/qxl/qxl_cmd.c | 16 ++--
> > 1 file changed, 14 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/qxl/qxl_cmd.c b/drivers/gpu/drm/qxl/qxl_cmd.c
> > index 63aa96a69752..281edab518cd 100644
> > --- a/drivers/gpu/drm/qxl/qxl_cmd.c
> > +++ b/drivers/gpu/drm/qxl/qxl_cmd.c
> > @@ -579,7 +579,7 @@ void qxl_surface_evict(struct qxl_device *qdev, struct
> > qxl_bo *surf, bool do_upd
> >
> > static int qxl_reap_surf(struct qxl_device *qdev, struct qxl_bo *surf,
> > bool stall)
> > {
> > - int ret;
> > + long ret;
> >
> > ret = qxl_bo_reserve(surf);
> > if (ret)
> > @@ -588,7 +588,19 @@ static int qxl_reap_surf(struct qxl_device *qdev,
> > struct qxl_bo *surf, bool stal
> > if (stall)
> > mutex_unlock(>surf_evict_mutex);
> >
> > - ret = ttm_bo_wait(>tbo, true, !stall);
> > + if (stall) {
> > + ret = dma_resv_wait_timeout(surf->tbo.base.resv,
> > + DMA_RESV_USAGE_BOOKKEEP, true,
> > + 15 * HZ);
> > + if (ret > 0)
> > + ret = 0;
> > + else if (ret == 0)
> > + ret = -EBUSY;
> > + } else {
> > + ret = dma_resv_test_signaled(surf->tbo.base.resv,
> > + DMA_RESV_USAGE_BOOKKEEP);
> > + ret = ret ? -EBUSY : 0;
> > + }
> >
> > if (stall)
> > mutex_lock(>surf_evict_mutex);
>
Re: [Intel-gfx] [PULL] drm-intel-gt-next
On Mon, 31 Oct 2022 at 21:07, Joonas Lahtinen wrote: > > Hi Dave & Daniel, > > Here goes first drm-intel-gt-next pull req towards 6.2. > > We have a fix for #6222 (kernel memory corruption issue) and fix for > display regression after resume. A missing W/A for Gen12 iGPUs and > extension of compute pre-emption timeout to 7.5 seconds to account for > compute corner cases. Improvements to GuC compute error capture, > scheduling hysteresis and SLPC. Fixes to EHL MOCS tables. Better docs > for I915_PARAM_HUC_STATUS and pre-emption control policy. Extending the > grace period for full GPU reset timeout to 60 seconds to better capture > logs or recover, as opposed to just giving up on whole device in 5 seconds. > > We're starting to add HWMON metrics for recent devices. More MTL > enabling, DG2 workarounds, DG2 HuC support, OA for DG2 is enabled. Small > bar enabling, PS64 support added for DG2 page tables. ptrace support for > local memory objects, local-memory migration for display surfaces. > > Note that there is drm/drm-next backmerge and then MEI subsystem patches > around GSC/PXP which are intertwined with i915 change so merged here as > agreed with Tomas and Greg. > > Additionally the usual amount of refactoring, cleanups, debugging > improvements and static checker fixes. Fails to build with clang here. CC [M] drivers/gpu/drm/i915/i915_hwmon.o /home/airlied/devel/kernel/dim/src/drivers/gpu/drm/i915/i915_hwmon.c:115:16: error: result of comparison of constant 18446744073709551615 with expression of type 'typeof (_Generic((field_msk), char: (unsigned char)0, unsigned char: (unsigned char)0, signed char: (unsigned char)0, unsigned short: (unsigned short)0, short: (unsigned short)0, unsigned int: (unsigned int)0, int: (unsigned int)0, unsigned long: (unsigned long)0, long: (unsigned long)0, unsigned long long: (unsigned long long)0, long long: (unsigned long long)0, default: (field_msk)))' (aka 'unsigned int') is always false [-Werror,-Wtautological-constant-out-of-range-compare] bits_to_set = FIELD_PREP(field_msk, nval); ^~~ /home/airlied/devel/kernel/dim/src/include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP' __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: ");\ ^~~ /home/airlied/devel/kernel/dim/src/include/linux/bitfield.h:71:53: note: expanded from macro '__BF_FIELD_CHECK' BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \ ~~^~~ /home/airlied/devel/kernel/dim/src/include/linux/build_bug.h:39:58: note: expanded from macro 'BUILD_BUG_ON_MSG' #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) ~^~~ /home/airlied/devel/kernel/dim/src/include/linux/compiler_types.h:357:22: note: expanded from macro 'compiletime_assert' _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) ^~~ /home/airlied/devel/kernel/dim/src/include/linux/compiler_types.h:345:23: note: expanded from macro '_compiletime_assert' __compiletime_assert(condition, msg, prefix, suffix) ~^~~ /home/airlied/devel/kernel/dim/src/include/linux/compiler_types.h:337:9: note: expanded from macro '__compiletime_assert' if (!(condition)) \ ^ 1 error generated. clang -v clang version 14.0.5 (Fedora 14.0.5-1.fc36) Dave.
Re: [Intel-gfx] [PATCH v3] drm/i915/gvt: fix double free bug in split_2MB_gtt_entry
On Thu, 27 Oct 2022 at 13:26, Zheng Hacker wrote: > > Dave Airlie 于2022年10月27日周四 08:01写道： > > > > On Fri, 7 Oct 2022 at 11:38, Zheng Wang wrote: > > > > > > If intel_gvt_dma_map_guest_page failed, it will call > > > ppgtt_invalidate_spt, which will finally free the spt. > > > But the caller does not notice that, it will free spt again in error path. > > > > > > Fix this by spliting invalidate and free in ppgtt_invalidate_spt. > > > Only free spt when in good case. > > > > > > Reported-by: Zheng Wang > > > Signed-off-by: Zheng Wang > > > > Has this landed in a tree yet, since it's a possible CVE, might be > > good to merge it somewhere. > > > > Dave. > > > > Hi Dave, > > This patched hasn't been merged yet. Could you please help with this? I'll add some more people who can probably look at it. Dave.
Re: [Intel-gfx] [PATCH v3] drm/i915/gvt: fix double free bug in split_2MB_gtt_entry
On Fri, 7 Oct 2022 at 11:38, Zheng Wang wrote:
>
> If intel_gvt_dma_map_guest_page failed, it will call
> ppgtt_invalidate_spt, which will finally free the spt.
> But the caller does not notice that, it will free spt again in error path.
>
> Fix this by spliting invalidate and free in ppgtt_invalidate_spt.
> Only free spt when in good case.
>
> Reported-by: Zheng Wang
> Signed-off-by: Zheng Wang
Has this landed in a tree yet, since it's a possible CVE, might be
good to merge it somewhere.
Dave.
> ---
> v3:
> - correct spelling mistake and remove unused variable suggested by Greg
>
> v2: https://lore.kernel.org/all/20221006165845.1735393-1-zyytlz...@163.com/
>
> v1: https://lore.kernel.org/all/20220928033340.1063949-1-zyytlz...@163.com/
> ---
> drivers/gpu/drm/i915/gvt/gtt.c | 32 +---
> 1 file changed, 21 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index ce0eb03709c3..865d33762e45 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -959,6 +959,7 @@ static inline int ppgtt_put_spt(struct
> intel_vgpu_ppgtt_spt *spt)
> return atomic_dec_return(>refcount);
> }
>
> +static int ppgtt_invalidate_and_free_spt(struct intel_vgpu_ppgtt_spt *spt);
> static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt);
>
> static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
> @@ -995,7 +996,7 @@ static int ppgtt_invalidate_spt_by_shadow_entry(struct
> intel_vgpu *vgpu,
> ops->get_pfn(e));
> return -ENXIO;
> }
> - return ppgtt_invalidate_spt(s);
> + return ppgtt_invalidate_and_free_spt(s);
> }
>
> static inline void ppgtt_invalidate_pte(struct intel_vgpu_ppgtt_spt *spt,
> @@ -1016,18 +1017,30 @@ static inline void ppgtt_invalidate_pte(struct
> intel_vgpu_ppgtt_spt *spt,
> intel_gvt_dma_unmap_guest_page(vgpu, pfn << PAGE_SHIFT);
> }
>
> -static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
> +static int ppgtt_invalidate_and_free_spt(struct intel_vgpu_ppgtt_spt *spt)
> {
> - struct intel_vgpu *vgpu = spt->vgpu;
> - struct intel_gvt_gtt_entry e;
> - unsigned long index;
> int ret;
>
> trace_spt_change(spt->vgpu->id, "die", spt,
> - spt->guest_page.gfn, spt->shadow_page.type);
> -
> + spt->guest_page.gfn, spt->shadow_page.type);
> if (ppgtt_put_spt(spt) > 0)
> return 0;
> + ret = ppgtt_invalidate_spt(spt);
> + if (!ret) {
> + trace_spt_change(spt->vgpu->id, "release", spt,
> +spt->guest_page.gfn, spt->shadow_page.type);
> + ppgtt_free_spt(spt);
> + }
> +
> + return ret;
> +}
> +
> +static int ppgtt_invalidate_spt(struct intel_vgpu_ppgtt_spt *spt)
> +{
> + struct intel_vgpu *vgpu = spt->vgpu;
> + struct intel_gvt_gtt_entry e;
> + unsigned long index;
> + int ret;
>
> for_each_present_shadow_entry(spt, , index) {
> switch (e.type) {
> @@ -1059,9 +1072,6 @@ static int ppgtt_invalidate_spt(struct
> intel_vgpu_ppgtt_spt *spt)
> }
> }
>
> - trace_spt_change(spt->vgpu->id, "release", spt,
> -spt->guest_page.gfn, spt->shadow_page.type);
> - ppgtt_free_spt(spt);
> return 0;
> fail:
> gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
> @@ -1393,7 +1403,7 @@ static int ppgtt_handle_guest_entry_removal(struct
> intel_vgpu_ppgtt_spt *spt,
> ret = -ENXIO;
> goto fail;
> }
> - ret = ppgtt_invalidate_spt(s);
> + ret = ppgtt_invalidate_and_free_spt(s);
> if (ret)
> goto fail;
> } else {
> --
> 2.25.1
>
Re: [Intel-gfx] [RFC PATCH v3 04/17] drm/i915: Implement bind and unbind of object
On Sun, 28 Aug 2022 at 05:45, Andi Shyti wrote: > > From: Niranjana Vishwanathapura > > Implement the bind and unbind of an object at the specified GPU virtual > addresses. > > Signed-off-by: Niranjana Vishwanathapura > Signed-off-by: Prathap Kumar Valsan > Signed-off-by: Ramalingam C > Signed-off-by: Andi Shyti > --- > drivers/gpu/drm/i915/Makefile | 1 + > drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h | 21 ++ > .../drm/i915/gem/i915_gem_vm_bind_object.c| 322 ++ > drivers/gpu/drm/i915/gt/intel_gtt.c | 10 + > drivers/gpu/drm/i915/gt/intel_gtt.h | 9 + > drivers/gpu/drm/i915/i915_driver.c| 1 + > drivers/gpu/drm/i915/i915_vma.c | 3 +- > drivers/gpu/drm/i915/i915_vma.h | 2 - > drivers/gpu/drm/i915/i915_vma_types.h | 14 + > include/uapi/drm/i915_drm.h | 163 + > 10 files changed, 543 insertions(+), 3 deletions(-) > create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h > create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c > > diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile > index 522ef9b4aff32..4e1627e96c6e0 100644 > --- a/drivers/gpu/drm/i915/Makefile > +++ b/drivers/gpu/drm/i915/Makefile > @@ -165,6 +165,7 @@ gem-y += \ > gem/i915_gem_ttm_move.o \ > gem/i915_gem_ttm_pm.o \ > gem/i915_gem_userptr.o \ > + gem/i915_gem_vm_bind_object.o \ > gem/i915_gem_wait.o \ > gem/i915_gemfs.o > i915-y += \ > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h > b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h > new file mode 100644 > index 0..ebc493b7dafc1 > --- /dev/null > +++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind.h > @@ -0,0 +1,21 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2022 Intel Corporation > + */ > + > +#ifndef __I915_GEM_VM_BIND_H > +#define __I915_GEM_VM_BIND_H > + > +#include "i915_drv.h" > + > +struct i915_vma * > +i915_gem_vm_bind_lookup_vma(struct i915_address_space *vm, u64 va); > +void i915_gem_vm_bind_remove(struct i915_vma *vma, bool release_obj); > + > +int i915_gem_vm_bind_ioctl(struct drm_device *dev, void *data, > + struct drm_file *file); > +int i915_gem_vm_unbind_ioctl(struct drm_device *dev, void *data, > +struct drm_file *file); > + > +void i915_gem_vm_unbind_vma_all(struct i915_address_space *vm); > +#endif /* __I915_GEM_VM_BIND_H */ > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c > b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c > new file mode 100644 > index 0..dadd1d4b1761b > --- /dev/null > +++ b/drivers/gpu/drm/i915/gem/i915_gem_vm_bind_object.c > @@ -0,0 +1,322 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright © 2022 Intel Corporation > + */ > + > +#include > + > +#include "gem/i915_gem_vm_bind.h" > +#include "gem/i915_gem_context.h" > +#include "gt/gen8_engine_cs.h" > + > +#include "i915_drv.h" > +#include "i915_gem_gtt.h" > + > +#define START(node) ((node)->start) > +#define LAST(node) ((node)->last) > + > +INTERVAL_TREE_DEFINE(struct i915_vma, rb, u64, __subtree_last, > +START, LAST, static inline, i915_vm_bind_it) > + > +#undef START > +#undef LAST > + > +/** > + * DOC: VM_BIND/UNBIND ioctls > + * > + * DRM_I915_GEM_VM_BIND/UNBIND ioctls allows UMD to bind/unbind GEM buffer > + * objects (BOs) or sections of a BOs at specified GPU virtual addresses on a > + * specified address space (VM). Multiple mappings can map to the same > physical > + * pages of an object (aliasing). These mappings (also referred to as > persistent > + * mappings) will be persistent across multiple GPU submissions (execbuf > calls) > + * issued by the UMD, without user having to provide a list of all required > + * mappings during each submission (as required by older execbuf mode). > + * > + * The VM_BIND/UNBIND calls allow UMDs to request a timeline out fence for > + * signaling the completion of bind/unbind operation. > + * > + * VM_BIND feature is advertised to user via I915_PARAM_VM_BIND_VERSION. > + * User has to opt-in for VM_BIND mode of binding for an address space (VM) > + * during VM creation time via I915_VM_CREATE_FLAGS_USE_VM_BIND extension. > + * > + * VM_BIND/UNBIND ioctl calls executed on different CPU threads concurrently > + * are not ordered. Furthermore, parts of the VM_BIND/UNBIND operations can > be > + * done asynchronously, when valid out fence is specified. > + * > + * VM_BIND locking order is as below. > + * > + * 1) vm_bind_lock mutex will protect vm_bind lists. This lock is taken in > + *vm_bind/vm_unbind ioctl calls, in the execbuf path and while releasing > the > + *mapping. > + * > + *In future, when GPU page faults are supported, we can potentially use a > + *rwsem instead, so that multiple page fault handlers can take the read > + *side lock
Re: [Intel-gfx] linux-next: manual merge of the drm tree with the drm-misc-fixes tree
On Wed, 27 Jul 2022 at 12:55, Stephen Rothwell wrote:
>
> Hi all,
>
> On Mon, 18 Jul 2022 09:44:53 +1000 Stephen Rothwell
> wrote:
> >
> > On Mon, 11 Jul 2022 10:05:45 +0200 Christian König
> > wrote:
> > >
> > > Am 11.07.22 um 04:47 schrieb Stephen Rothwell:
> > > >
> > > > Today's linux-next merge of the drm tree got a conflict in:
> > > >
> > > >drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
> > > >
> > > > between commit:
> > > >
> > > >925b6e59138c ("Revert "drm/amdgpu: add drm buddy support to amdgpu"")
> > > >
> > > > from the drm-misc-fixes tree and commit:
> > > >
> > > >5e3f1e7729ec ("drm/amdgpu: fix start calculation in
> > > > amdgpu_vram_mgr_new")
> > > >
> > > > from the drm tree.
> > > >
> > > > This is a mess :-( I have just reverted the above revert before mergin
> > > > the drm tree for today, please fix it up.
> > >
> > > Sorry for the noise, the patch "5e3f1e7729ec ("drm/amdgpu: fix start
> > > calculation in amdgpu_vram_mgr_new")" and another one is going to be
> > > reverted from the drm tree as well.
> > >
> > > It's just that -fixes patches where faster than -next patches.
> >
> > Here we are a week later, -rc7 has been released and as far as I can
> > tell (though I may have missed it), this is still a problem :-(
> >
> > I am still reverting 925b6e59138c (which is now in Linus' tree).
>
> Ping?
My assumption is I fix this on sending my -next tree to Linus with a
resolution I create at that time?
Is there another option, we have this fixed in out drm-tip tree already.
Dave.
Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Update to GuC version 70.1.1
On Fri, 15 Apr 2022 at 10:15, Matt Roper wrote: > > On Tue, Apr 12, 2022 at 03:59:55PM -0700, john.c.harri...@intel.com wrote: > > From: John Harrison > > > > The latest GuC firmware drops the context descriptor pool in favour of > > passing all creation data in the create H2G. It also greatly simplifies > > the work queue and removes the process descriptor used for multi-LRC > > submission. So, remove all mention of LRC and process descriptors and > > update the registration code accordingly. > > > > Unfortunately, the new API also removes the ability to set default > > values for the scheduling policies at context registration time. > > Instead, a follow up H2G must be sent. The individual scheduling > > policy update H2G commands are also dropped in favour of a single KLV > > based H2G. So, change the update wrappers accordingly and call this > > during context registration.. > > > > Of course, this second H2G per registration might fail due to being > > backed up. The registration code has a complicated state machine to > > cope with the actual registration call failing. However, if that works > > then there is no support for unwinding if a further call should fail. > > Unwinding would require sending a H2G to de-register - but that can't > > be done because the CTB is already backed up. > > > > So instead, add a new flag to say whether the context has a pending > > policy update. This is set if the policy H2G fails at registration > > time. The submission code checks for this flag and retries the policy > > update if set. If that call fails, the submission path early exists > > with a retry error. This is something that is already supported for > > other reasons. > > > > Signed-off-by: John Harrison > > Reviewed-by: Daniele Ceraolo Spurio > > Applied to drm-intel-gt-next. Thanks for the patch and review. > (cc'ing Linus and danvet, as a headsup, there is also a phoronix article where this was discovered). Okay WTF. This is in no way acceptable. This needs to be fixed in 5.19-rc ASAP. Once hardware is released and we remove the gate flag by default, you cannot just bump firmware versions blindly. The kernel needs to retain compatibility with all released firmwares since a device was declared supported. This needs to be reverted, and then 70 should be introduced with a fallback to 69 versions. Very disappointing, I expect this to get dealt with v.quickly. Dave.
Re: [Intel-gfx] [RFC v3 3/3] drm/doc/rfc: VM_BIND uapi definition
On Tue, 24 May 2022 at 05:20, Niranjana Vishwanathapura
wrote:
>
> On Thu, May 19, 2022 at 04:07:30PM -0700, Zanoni, Paulo R wrote:
> >On Tue, 2022-05-17 at 11:32 -0700, Niranjana Vishwanathapura wrote:
> >> VM_BIND and related uapi definitions
> >>
> >> v2: Ensure proper kernel-doc formatting with cross references.
> >> Also add new uapi and documentation as per review comments
> >> from Daniel.
> >>
> >> Signed-off-by: Niranjana Vishwanathapura
> >>
> >> ---
> >> Documentation/gpu/rfc/i915_vm_bind.h | 399 +++
> >> 1 file changed, 399 insertions(+)
> >> create mode 100644 Documentation/gpu/rfc/i915_vm_bind.h
> >>
> >> diff --git a/Documentation/gpu/rfc/i915_vm_bind.h
> >> b/Documentation/gpu/rfc/i915_vm_bind.h
> >> new file mode 100644
> >> index ..589c0a009107
> >> --- /dev/null
> >> +++ b/Documentation/gpu/rfc/i915_vm_bind.h
> >> @@ -0,0 +1,399 @@
> >> +/* SPDX-License-Identifier: MIT */
> >> +/*
> >> + * Copyright © 2022 Intel Corporation
> >> + */
> >> +
> >> +/**
> >> + * DOC: I915_PARAM_HAS_VM_BIND
> >> + *
> >> + * VM_BIND feature availability.
> >> + * See typedef drm_i915_getparam_t param.
> >> + */
> >> +#define I915_PARAM_HAS_VM_BIND 57
> >> +
> >> +/**
> >> + * DOC: I915_VM_CREATE_FLAGS_USE_VM_BIND
> >> + *
> >> + * Flag to opt-in for VM_BIND mode of binding during VM creation.
> >> + * See struct drm_i915_gem_vm_control flags.
> >> + *
> >> + * A VM in VM_BIND mode will not support the older execbuff mode of
> >> binding.
> >> + * In VM_BIND mode, execbuff ioctl will not accept any execlist (ie., the
> >> + * _i915_gem_execbuffer2.buffer_count must be 0).
> >> + * Also, _i915_gem_execbuffer2.batch_start_offset and
> >> + * _i915_gem_execbuffer2.batch_len must be 0.
> >> + * DRM_I915_GEM_EXECBUFFER_EXT_BATCH_ADDRESSES extension must be provided
> >> + * to pass in the batch buffer addresses.
> >> + *
> >> + * Additionally, I915_EXEC_NO_RELOC, I915_EXEC_HANDLE_LUT and
> >> + * I915_EXEC_BATCH_FIRST of _i915_gem_execbuffer2.flags must be 0
> >> + * (not used) in VM_BIND mode. I915_EXEC_USE_EXTENSIONS flag must always
> >> be
> >> + * set (See struct drm_i915_gem_execbuffer_ext_batch_addresses).
> >> + * The buffers_ptr, buffer_count, batch_start_offset and batch_len fields
> >> + * of struct drm_i915_gem_execbuffer2 are also not used and must be 0.
> >> + */
> >
> >From that description, it seems we have:
> >
> >struct drm_i915_gem_execbuffer2 {
> >__u64 buffers_ptr; -> must be 0 (new)
> >__u32 buffer_count; -> must be 0 (new)
> >__u32 batch_start_offset; -> must be 0 (new)
> >__u32 batch_len;-> must be 0 (new)
> >__u32 DR1; -> must be 0 (old)
> >__u32 DR4; -> must be 0 (old)
> >__u32 num_cliprects; (fences) -> must be 0 since using extensions
> >__u64 cliprects_ptr; (fences, extensions) -> contains an actual
> > pointer!
> >__u64 flags;-> some flags must be 0 (new)
> >__u64 rsvd1; (context info) -> repurposed field (old)
> >__u64 rsvd2;-> unused
> >};
> >
> >Based on that, why can't we just get drm_i915_gem_execbuffer3 instead
> >of adding even more complexity to an already abused interface? While
> >the Vulkan-like extension thing is really nice, I don't think what
> >we're doing here is extending the ioctl usage, we're completely
> >changing how the base struct should be interpreted based on how the VM
> >was created (which is an entirely different ioctl).
> >
> >From Rusty Russel's API Design grading, drm_i915_gem_execbuffer2 is
> >already at -6 without these changes. I think after vm_bind we'll need
> >to create a -11 entry just to deal with this ioctl.
> >
>
> The only change here is removing the execlist support for VM_BIND
> mode (other than natual extensions).
> Adding a new execbuffer3 was considered, but I think we need to be careful
> with that as that goes beyond the VM_BIND support, including any future
> requirements (as we don't want an execbuffer4 after VM_BIND).
Why not? it's not like adding extensions here is really that different
than adding new ioctls.
I definitely think this deserves an execbuffer3 without even
considering future requirements. Just to burn down the old
requirements and pointless fields.
Make execbuffer3 be vm bind only, no relocs, no legacy bits, leave the
older sw on execbuf2 for ever.
Dave.
Re: [Intel-gfx] [PATCH 1/1] drm/i915: Inherit submitter nice when scheduling requests
On Fri, 8 Apr 2022 at 18:25, Tvrtko Ursulin wrote: > > > On 08/04/2022 08:58, Daniel Vetter wrote: > > On Thu, Apr 07, 2022 at 04:16:27PM +0100, Tvrtko Ursulin wrote: > >> From: Tvrtko Ursulin > >> > >> Inherit submitter nice at point of request submission to account for long > >> running processes getting either externally or self re-niced. > >> > >> This accounts for the current processing landscape where computational > >> pipelines are composed of CPU and GPU parts working in tandem. > >> > >> Nice value will only apply to requests which originate from user contexts > >> and have default context priority. This is to avoid disturbing any > >> application made choices of low and high (batch processing and latency > >> sensitive compositing). In this case nice value adjusts the effective > >> priority in the narrow band of -19 to +20 around > >> I915_CONTEXT_DEFAULT_PRIORITY. > >> > >> This means that userspace using the context priority uapi directly has a > >> wider range of possible adjustments (in practice that only applies to > >> execlists platforms - with GuC there are only three priority buckets), but > >> in all cases nice adjustment has the expected effect: positive nice > >> lowering the scheduling priority and negative nice raising it. > >> > >> Signed-off-by: Tvrtko Ursulin > > > > I don't think adding any more fancy features to i915-scheduler makes > > sense, at least not before we've cut over to drm/sched. > > Why do you think so? > > Drm/sched has at least low/normal/high priority and surely we will keep > the i915 context priority ABI. > > Then this patch is not touching the i915 scheduler at all, neither it is > fancy. > > The cover letter explains how it implements the same approach as the IO > scheduler. And it explains the reasoning and benefits. Provides an user > experience benefit today, which can easily be preserved. won't this cause uAPI divergence between execlists and GuC, like if something nices to -15 or -18 with execlists and the same with GuC it won't get the same sort of result will it? Dave.
Re: [Intel-gfx] [PULL] drm-intel-gt-next
On Thu, 17 Feb 2022 at 20:26, Joonas Lahtinen wrote: > > Hi Dave & Daniel, > > Here is the first drm-intel-gt-next feature PR towards v5.18. Am I missing some previous drm-intel pull? /home/airlied/devel/kernel/dim/src/drivers/gpu/drm/i915/gt/intel_workarounds.c: In function ‘rcs_engine_wa_init’: /home/airlied/devel/kernel/dim/src/drivers/gpu/drm/i915/gt/intel_workarounds.c:2051:40: error: ‘XEHP_DIS_BBL_SYSPIPE’ undeclared (first use in this function) 2051 | wa_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); |^~~~ /home/airlied/devel/kernel/dim/src/drivers/gpu/drm/i915/gt/intel_workarounds.c:2051:40: note: each undeclared identifier is reported only once for each function it appears in Dave. > > For DG2 adds subplatform G12, missing workarounds and fixes GuC > loading on ARM64. C0/D0 stepping info added for RPL-S. > > For uAPI enables support for simple parallel submission with > execlists which was previously enabled only for GuC. > > Further fixes for PMU metrics when GuC is enabled, better error > reporting for GuC loading failures. Fix for PXP unbind splat. > Updates to GuC version 69.0.3 with improvements to GT reset > scenarios. > > The rest is mostly refactoring of the memory management code, > as highlights introduction of async unbinding/migration and > removal of short-term pinning in execbuf. > > Then a few selftest and coding style fixes. > > Regards, Joonas > > *** > > drm-intel-gt-next-2022-02-17: > > UAPI Changes: > > - Weak parallel submission support for execlists > > Minimal implementation of the parallel submission support for > execlists backend that was previously only implemented for GuC. > Support one sibling non-virtual engine. > > Core Changes: > > - Two backmerges of drm/drm-next for header file renames/changes and > i915_regs reorganization > > Driver Changes: > > - Add new DG2 subplatform: DG2-G12 (Matt R) > - Add new DG2 workarounds (Matt R, Ram, Bruce) > - Handle pre-programmed WOPCM registers for DG2+ (Daniele) > - Update guc shim control programming on XeHP SDV+ (Daniele) > - Add RPL-S C0/D0 stepping information (Anusha) > - Improve GuC ADS initialization to work on ARM64 on dGFX (Lucas) > > - Fix KMD and GuC race on accessing PMU busyness (Umesh) > - Use PM timestamp instead of RING TIMESTAMP for reference in PMU with GuC > (Umesh) > - Report error on invalid reset notification from GuC (John) > - Avoid WARN splat by holding RPM wakelock during PXP unbind (Juston) > - Fixes to parallel submission implementation (Matt B.) > - Improve GuC loading status check/error reports (John) > - Tweak TTM LRU priority hint selection (Matt A.) > - Align the plane_vma to min_page_size of stolen mem (Ram) > > - Introduce vma resources and implement async unbinding (Thomas) > - Use struct vma_resource instead of struct vma_snapshot (Thomas) > - Return some TTM accel move errors instead of trying memcpy move (Thomas) > - Fix a race between vma / object destruction and unbinding (Thomas) > - Remove short-term pins from execbuf (Maarten) > - Update to GuC version 69.0.3 (John, Michal Wa.) > - Improvements to GT reset paths in GuC backend (Matt B.) > - Use shrinker_release_pages instead of writeback in shmem object hooks (Matt > A., Tvrtko) > - Use trylock instead of blocking lock when freeing GEM objects (Maarten) > - Allocate intel_engine_coredump_alloc with ALLOW_FAIL (Matt B.) > - Fixes to object unmapping and purging (Matt A) > - Check for wedged device in GuC backend (John) > - Avoid lockdep splat by locking dpt_obj around set_cache_level (Maarten) > - Allow dead vm to unbind vma's without lock (Maarten) > - s/engine->i915/i915/ for DG2 engine workarounds (Matt R) > > - Use to_gt() helper for GGTT accesses (Michal Wi.) > - Selftest improvements (Matt B., Thomas, Ram) > - Coding style and compiler warning fixes (Matt B., Jasmine, Andi, Colin, > Gustavo, Dan) > > The following changes since commit 53dbee4926d3706ca9e03f3928fa85b5ec3bc0cc: > > Merge tag 'drm-misc-next-2022-01-27' of > git://anongit.freedesktop.org/drm/drm-misc into drm-next (2022-02-01 19:02:41 > +1000) > > are available in the Git repository at: > > git://anongit.freedesktop.org/drm/drm-intel > tags/drm-intel-gt-next-2022-02-17 > > for you to fetch changes up to 154cfae6158141b18d65abb0db679bb51a8294e7: > > drm/i915/dg2: Add Wa_22011100796 (2022-02-11 17:11:44 +0530) > > > UAPI Changes: > > - Weak parallel submission support for execlists > > Minimal implementation of the parallel submission support for > execlists backend that was previously only implemented for GuC. > Support one sibling non-virtual engine. > > Core Changes: > > - Two backmerges of drm/drm-next for header file renames/changes and > i915_regs reorganization > > Driver Changes: > > - Add new DG2 subplatform: DG2-G12 (Matt R) > - Add new DG2 workarounds (Matt R, Ram, Bruce) > - Handle
Re: [Intel-gfx] [PATCH 01/21] MAINTAINERS: Add entry for fbdev core
On Tue, 1 Feb 2022 at 07:06, Daniel Vetter wrote: > > Ever since Tomi extracted the core code in 2014 it's been defacto me > maintaining this, with help from others from dri-devel and sometimes > Linus (but those are mostly merge conflicts): > > $ git shortlog -ns drivers/video/fbdev/core/ | head -n5 > 35 Daniel Vetter > 23 Linus Torvalds > 10 Hans de Goede > 9 Dave Airlie > 6 Peter Rosin Acked-by: Dave Airlie
Re: [Intel-gfx] [PATCH] MAINTAINERS: Add Tvrtko as drm/i915 co-maintainer
On Mon, 25 Oct 2021 at 23:51, Daniel Vetter wrote: > > On Mon, Oct 25, 2021 at 3:49 PM Joonas Lahtinen > wrote: > > > > Add Tvrtko Ursulin as a co-maintainer for drm/i915 driver. > > Tvrtko will bring added bandwidth and focus to the GT/GEM domain > > (drm-intel-gt-next). > > > > This will help with the increased driver maintenance efforts, allows > > alternating the drm-intel-gt-next pull requests and also should increase > > the coverage for the maintenance in general. > > > > Signed-off-by: Joonas Lahtinen > > Cc: David Airlie > > Cc: Daniel Vetter > > Acked-by: Jani Nikula > > Acked-by: Rodrigo Vivi > > Acked-by: Tvrtko Ursulin > > Cc: Sean Paul > > Cc: Maarten Lankhorst > > Cc: Maxime Ripard > > Cc: dri-de...@lists.freedesktop.org > > Acked-by: Daniel Vetter Acked-by: Dave Airlie
Re: [Intel-gfx] [PATCH 0/4] drm/i915: Make the driver not oops on load on old machines
On Thu, 14 Oct 2021 at 19:09, Ville Syrjala wrote: > > From: Ville Syrjälä > > Fix a pile of regression on older machines which just oops the driver > on load. > For all 4: Reviewed-by: Dave Airlie though it would be nice if the clflushes has more justifications on initial patch submission/review, maybe something for gt team to keep an eye for patches coming out from internal. Dave.
[Intel-gfx] [PATCH 3/4] drm/i915/display: drop unused parameter to dpt pin
From: Dave Airlie
The uses_fence isn't used.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 0beb0aa7..721a1477e8b1 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -18,7 +18,6 @@
static struct i915_vma *
intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
const struct i915_ggtt_view *view,
-bool uses_fence,
unsigned long *out_flags,
struct i915_address_space *vm)
{
@@ -236,7 +235,7 @@ int intel_plane_pin_fb(struct intel_plane_state
*plane_state)
plane_state->ggtt_vma = vma;
- vma = intel_pin_fb_obj_dpt(fb, _state->view.gtt, false,
+ vma = intel_pin_fb_obj_dpt(fb, _state->view.gtt,
_state->flags,
intel_fb->dpt_vm);
if (IS_ERR(vma)) {
intel_dpt_unpin(intel_fb->dpt_vm);
--
2.25.4
[Intel-gfx] [PATCH 4/4] drm/i915/display: drop some unused includes
From: Dave Airlie These aren't used since refactoring. Signed-off-by: Dave Airlie --- drivers/gpu/drm/i915/display/intel_display.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ff598b6cd953..73f8c893d52e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -65,11 +65,8 @@ #include "display/intel_vdsc.h" #include "display/intel_vrr.h" -#include "gem/i915_gem_lmem.h" #include "gem/i915_gem_object.h" -#include "gt/gen8_ppgtt.h" - #include "pxp/intel_pxp.h" #include "g4x_dp.h" -- 2.25.4
[Intel-gfx] [PATCH 2/4] drm/i915/display: move fbdev pin code into fb_pin
From: Dave Airlie
This moves the fbdev pin code over and moves the internal
interfaces to static.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 37 +++--
drivers/gpu/drm/i915/display/intel_fb_pin.h | 15 -
drivers/gpu/drm/i915/display/intel_fbdev.c | 32 --
3 files changed, 41 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 3f77f3013584..0beb0aa7 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -71,7 +71,7 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
return vma;
}
-struct i915_vma *
+static struct i915_vma *
intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
bool phys_cursor,
const struct i915_ggtt_view *view,
@@ -199,7 +199,8 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
return vma;
}
-void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
+static void
+intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
{
if (flags & PLANE_HAS_FENCE)
i915_vma_unpin_fence(vma);
@@ -272,3 +273,35 @@ void intel_plane_unpin_fb(struct intel_plane_state
*old_plane_state)
intel_dpt_unpin(intel_fb->dpt_vm);
}
}
+
+void intel_fbdev_unpin(struct intel_fbdev *ifbdev)
+{
+ if (ifbdev->vma)
+ intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags);
+ ifbdev->vma = NULL;
+ ifbdev->vma_flags = 0;
+}
+
+int intel_fbdev_pin_and_fence(struct drm_i915_private *dev_priv,
+ struct intel_fbdev *ifbdev,
+ void **vaddr)
+{
+ const struct i915_ggtt_view view = {
+ .type = I915_GGTT_VIEW_NORMAL,
+ };
+ ifbdev->vma = intel_pin_and_fence_fb_obj(>fb->base, false,
+, false,
>vma_flags);
+
+ if (IS_ERR(ifbdev->vma)) {
+ return PTR_ERR(ifbdev->vma);
+ }
+
+ *vaddr = i915_vma_pin_iomap(ifbdev->vma);
+ if (IS_ERR(*vaddr)) {
+ intel_fbdev_unpin(ifbdev);
+ drm_err(_priv->drm,
+ "Failed to remap framebuffer into virtual memory\n");
+ return PTR_ERR(vaddr);
+ }
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h
b/drivers/gpu/drm/i915/display/intel_fb_pin.h
index e4fcd0218d9d..88d736264348 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.h
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h
@@ -8,21 +8,18 @@
#include
+struct drm_i915_private;
struct drm_framebuffer;
+struct intel_fbdev;
struct i915_vma;
struct intel_plane_state;
struct i915_ggtt_view;
-struct i915_vma *
-intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
- bool phys_cursor,
- const struct i915_ggtt_view *view,
- bool uses_fence,
- unsigned long *out_flags);
-
-void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
-
int intel_plane_pin_fb(struct intel_plane_state *plane_state);
void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state);
+int intel_fbdev_pin_and_fence(struct drm_i915_private *dev_priv,
+ struct intel_fbdev *ifbdev,
+ void **vaddr);
+void intel_fbdev_unpin(struct intel_fbdev *ifbdev);
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index c3ea9639a4ed..cee85fcc2085 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -171,38 +171,6 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
return 0;
}
-static void intel_fbdev_unpin(struct intel_fbdev *ifbdev)
-{
- if (ifbdev->vma)
- intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags);
- ifbdev->vma = NULL;
- ifbdev->vma_flags = 0;
-}
-
-static int intel_fbdev_pin_and_fence(struct drm_i915_private *dev_priv,
-struct intel_fbdev *ifbdev,
-void **vaddr)
-{
- const struct i915_ggtt_view view = {
- .type = I915_GGTT_VIEW_NORMAL,
- };
- ifbdev->vma = intel_pin_and_fence_fb_obj(>fb->base, false,
-, false,
>vma_flags);
-
- if (IS_ERR(ifbdev->vma)) {
- return PTR_ERR(ifbdev->vma);
- }
-
- *vaddr = i915_vma_pin_iomap(ifbdev->vma);
- if (IS_ERR(*vaddr)) {
- intel_fbdev_unpin(ifbdev);
- drm_err(_priv->drm,
- "Failed to remap framebuffer into vir
[Intel-gfx] [PATCH 0/4] finish/rebase fbdev pin refactor.
Jani had some extra review for the refactor patch. Address that. Dave.
[Intel-gfx] [PATCH 1/4] drm/i915/display: refactor fbdev pin/unpin out into functions.
From: Dave Airlie
This just cleans up the calls a bit.
v2: fix unpin in vaddr fail path (Jani)
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 67 +-
1 file changed, 41 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index adc3a81be9f7..c3ea9639a4ed 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -171,6 +171,38 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
return 0;
}
+static void intel_fbdev_unpin(struct intel_fbdev *ifbdev)
+{
+ if (ifbdev->vma)
+ intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags);
+ ifbdev->vma = NULL;
+ ifbdev->vma_flags = 0;
+}
+
+static int intel_fbdev_pin_and_fence(struct drm_i915_private *dev_priv,
+struct intel_fbdev *ifbdev,
+void **vaddr)
+{
+ const struct i915_ggtt_view view = {
+ .type = I915_GGTT_VIEW_NORMAL,
+ };
+ ifbdev->vma = intel_pin_and_fence_fb_obj(>fb->base, false,
+, false,
>vma_flags);
+
+ if (IS_ERR(ifbdev->vma)) {
+ return PTR_ERR(ifbdev->vma);
+ }
+
+ *vaddr = i915_vma_pin_iomap(ifbdev->vma);
+ if (IS_ERR(*vaddr)) {
+ intel_fbdev_unpin(ifbdev);
+ drm_err(_priv->drm,
+ "Failed to remap framebuffer into virtual memory\n");
+ return PTR_ERR(vaddr);
+ }
+ return 0;
+}
+
static int intelfb_create(struct drm_fb_helper *helper,
struct drm_fb_helper_surface_size *sizes)
{
@@ -181,13 +213,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
struct i915_ggtt *ggtt = _priv->ggtt;
- const struct i915_ggtt_view view = {
- .type = I915_GGTT_VIEW_NORMAL,
- };
intel_wakeref_t wakeref;
struct fb_info *info;
- struct i915_vma *vma;
- unsigned long flags = 0;
bool prealloc = false;
void __iomem *vaddr;
struct drm_i915_gem_object *obj;
@@ -224,10 +251,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
* This also validates that any existing fb inherited from the
* BIOS is suitable for own access.
*/
- vma = intel_pin_and_fence_fb_obj(>fb->base, false,
-, false, );
- if (IS_ERR(vma)) {
- ret = PTR_ERR(vma);
+ ret = intel_fbdev_pin_and_fence(dev_priv, ifbdev, );
+ if (ret) {
goto out_unlock;
}
@@ -261,19 +286,12 @@ static int intelfb_create(struct drm_fb_helper *helper,
/* Our framebuffer is the entirety of fbdev's system memory */
info->fix.smem_start =
- (unsigned long)(ggtt->gmadr.start + vma->node.start);
- info->fix.smem_len = vma->node.size;
+ (unsigned long)(ggtt->gmadr.start +
ifbdev->vma->node.start);
+ info->fix.smem_len = ifbdev->vma->node.size;
}
- vaddr = i915_vma_pin_iomap(vma);
- if (IS_ERR(vaddr)) {
- drm_err(_priv->drm,
- "Failed to remap framebuffer into virtual memory\n");
- ret = PTR_ERR(vaddr);
- goto out_unpin;
- }
info->screen_base = vaddr;
- info->screen_size = vma->node.size;
+ info->screen_size = ifbdev->vma->node.size;
drm_fb_helper_fill_info(info, >helper, sizes);
@@ -281,23 +299,21 @@ static int intelfb_create(struct drm_fb_helper *helper,
* If the object is stolen however, it will be full of whatever
* garbage was left in there.
*/
- if (!i915_gem_object_is_shmem(vma->obj) && !prealloc)
+ if (!i915_gem_object_is_shmem(ifbdev->vma->obj) && !prealloc)
memset_io(info->screen_base, 0, info->screen_size);
/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
drm_dbg_kms(_priv->drm, "allocated %dx%d fb: 0x%08x\n",
ifbdev->fb->base.width, ifbdev->fb->base.height,
- i915_ggtt_offset(vma));
- ifbdev->vma = vma;
- ifbdev->vma_flags = flags;
+ i915_ggtt_offset(ifbdev->vma));
intel_runtime_pm_put(_priv->runtime_pm, wakeref);
vga_switcheroo_client_fb_set(pdev, info);
return 0;
out_unpin:
- intel_unpin_fb_vma(vma, flags);
+ intel_fbdev_unpin(ifbdev);
out_unl
Re: [Intel-gfx] [PULL] drm-misc-fixes
> - Respun clock fixes for vc4/hdmi. I was uneasy with these patches due to the number and size of them at this point in the cycle. Is there any major problem leaving them until next? I think fixes needs a hard reset and rebase to rc6 when it's tagged. If these are super-urgent fixes then I'd rather they come in a topic branch I can give to Linus separately. Dave.
Re: [Intel-gfx] [PATCH 0/6] drm/i915: Failsafe migration blits
On Fri, 8 Oct 2021 at 23:36, Thomas Hellström wrote: > > This patch series introduces failsafe migration blits. > The reason for this seemingly strange concept is that if the initial > clearing or readback of LMEM fails for some reason, and we then set up > either GPU- or CPU ptes to the allocated LMEM, we can expose old > contents from other clients. Can we enumerate "for some reason" here? This feels like "security" with no defined threat model. Maybe if the cover letter contains more details on the threat model it would make more sense. Dave.
[Intel-gfx] [PATCH 8/8] drm/i915/display: drop unused parameter to dpt pin
From: Dave Airlie
The uses_fence isn't used.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 7233a2d3c326..1005d36318d1 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -18,7 +18,6 @@
static struct i915_vma *
intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
const struct i915_ggtt_view *view,
-bool uses_fence,
unsigned long *out_flags,
struct i915_address_space *vm)
{
@@ -236,7 +235,7 @@ int intel_plane_pin_fb(struct intel_plane_state
*plane_state)
plane_state->ggtt_vma = vma;
- vma = intel_pin_fb_obj_dpt(fb, _state->view.gtt, false,
+ vma = intel_pin_fb_obj_dpt(fb, _state->view.gtt,
_state->flags,
intel_fb->dpt_vm);
if (IS_ERR(vma)) {
intel_dpt_unpin(intel_fb->dpt_vm);
--
2.25.4
[Intel-gfx] [PATCH 7/8] drm/i915/display: move fbdev pin code into fb_pin
From: Dave Airlie
This moves the fbdev pin code over and moves the internal
interfaces to static.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 34 +++--
drivers/gpu/drm/i915/display/intel_fb_pin.h | 15 -
drivers/gpu/drm/i915/display/intel_fbdev.c | 29 --
3 files changed, 38 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 3f77f3013584..7233a2d3c326 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -71,7 +71,7 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
return vma;
}
-struct i915_vma *
+static struct i915_vma *
intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
bool phys_cursor,
const struct i915_ggtt_view *view,
@@ -199,7 +199,8 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
return vma;
}
-void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
+static void
+intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
{
if (flags & PLANE_HAS_FENCE)
i915_vma_unpin_fence(vma);
@@ -272,3 +273,32 @@ void intel_plane_unpin_fb(struct intel_plane_state
*old_plane_state)
intel_dpt_unpin(intel_fb->dpt_vm);
}
}
+
+int intel_fbdev_pin_and_fence(struct drm_i915_private *dev_priv,
+ struct intel_fbdev *ifbdev,
+ void **vaddr)
+{
+ const struct i915_ggtt_view view = {
+ .type = I915_GGTT_VIEW_NORMAL,
+ };
+ ifbdev->vma = intel_pin_and_fence_fb_obj(>fb->base, false,
+, false,
>vma_flags);
+
+ if (IS_ERR(ifbdev->vma)) {
+ return PTR_ERR(ifbdev->vma);
+ }
+
+ *vaddr = i915_vma_pin_iomap(ifbdev->vma);
+ if (IS_ERR(*vaddr)) {
+ drm_err(_priv->drm,
+ "Failed to remap framebuffer into virtual memory\n");
+ return PTR_ERR(vaddr);
+ }
+ return 0;
+}
+
+void intel_fbdev_unpin(struct intel_fbdev *ifbdev)
+{
+ if (ifbdev->vma)
+ intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h
b/drivers/gpu/drm/i915/display/intel_fb_pin.h
index e4fcd0218d9d..88d736264348 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.h
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h
@@ -8,21 +8,18 @@
#include
+struct drm_i915_private;
struct drm_framebuffer;
+struct intel_fbdev;
struct i915_vma;
struct intel_plane_state;
struct i915_ggtt_view;
-struct i915_vma *
-intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
- bool phys_cursor,
- const struct i915_ggtt_view *view,
- bool uses_fence,
- unsigned long *out_flags);
-
-void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
-
int intel_plane_pin_fb(struct intel_plane_state *plane_state);
void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state);
+int intel_fbdev_pin_and_fence(struct drm_i915_private *dev_priv,
+ struct intel_fbdev *ifbdev,
+ void **vaddr);
+void intel_fbdev_unpin(struct intel_fbdev *ifbdev);
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 7ac9348d20c5..cee85fcc2085 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -171,35 +171,6 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
return 0;
}
-static int intel_fbdev_pin_and_fence(struct drm_i915_private *dev_priv,
-struct intel_fbdev *ifbdev,
-void **vaddr)
-{
- const struct i915_ggtt_view view = {
- .type = I915_GGTT_VIEW_NORMAL,
- };
- ifbdev->vma = intel_pin_and_fence_fb_obj(>fb->base, false,
-, false,
>vma_flags);
-
- if (IS_ERR(ifbdev->vma)) {
- return PTR_ERR(ifbdev->vma);
- }
-
- *vaddr = i915_vma_pin_iomap(ifbdev->vma);
- if (IS_ERR(*vaddr)) {
- drm_err(_priv->drm,
- "Failed to remap framebuffer into virtual memory\n");
- return PTR_ERR(vaddr);
- }
- return 0;
-}
-
-static void intel_fbdev_unpin(struct intel_fbdev *ifbdev)
-{
- if (ifbdev->vma)
- intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags);
-}
-
static int intelfb_create(struct drm_fb_helper *helper,
struct drm_fb_helper_surface_size *sizes)
{
--
2.25.4
[Intel-gfx] [PATCH 6/8] drm/i915/display: refactor fbdev pin/unpin out into functions.
From: Dave Airlie
This just cleans up the calls a bit.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 64 +-
1 file changed, 38 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index adc3a81be9f7..7ac9348d20c5 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -171,6 +171,35 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
return 0;
}
+static int intel_fbdev_pin_and_fence(struct drm_i915_private *dev_priv,
+struct intel_fbdev *ifbdev,
+void **vaddr)
+{
+ const struct i915_ggtt_view view = {
+ .type = I915_GGTT_VIEW_NORMAL,
+ };
+ ifbdev->vma = intel_pin_and_fence_fb_obj(>fb->base, false,
+, false,
>vma_flags);
+
+ if (IS_ERR(ifbdev->vma)) {
+ return PTR_ERR(ifbdev->vma);
+ }
+
+ *vaddr = i915_vma_pin_iomap(ifbdev->vma);
+ if (IS_ERR(*vaddr)) {
+ drm_err(_priv->drm,
+ "Failed to remap framebuffer into virtual memory\n");
+ return PTR_ERR(vaddr);
+ }
+ return 0;
+}
+
+static void intel_fbdev_unpin(struct intel_fbdev *ifbdev)
+{
+ if (ifbdev->vma)
+ intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags);
+}
+
static int intelfb_create(struct drm_fb_helper *helper,
struct drm_fb_helper_surface_size *sizes)
{
@@ -181,13 +210,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
struct i915_ggtt *ggtt = _priv->ggtt;
- const struct i915_ggtt_view view = {
- .type = I915_GGTT_VIEW_NORMAL,
- };
intel_wakeref_t wakeref;
struct fb_info *info;
- struct i915_vma *vma;
- unsigned long flags = 0;
bool prealloc = false;
void __iomem *vaddr;
struct drm_i915_gem_object *obj;
@@ -224,10 +248,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
* This also validates that any existing fb inherited from the
* BIOS is suitable for own access.
*/
- vma = intel_pin_and_fence_fb_obj(>fb->base, false,
-, false, );
- if (IS_ERR(vma)) {
- ret = PTR_ERR(vma);
+ ret = intel_fbdev_pin_and_fence(dev_priv, ifbdev, );
+ if (ret) {
goto out_unlock;
}
@@ -261,19 +283,12 @@ static int intelfb_create(struct drm_fb_helper *helper,
/* Our framebuffer is the entirety of fbdev's system memory */
info->fix.smem_start =
- (unsigned long)(ggtt->gmadr.start + vma->node.start);
- info->fix.smem_len = vma->node.size;
+ (unsigned long)(ggtt->gmadr.start +
ifbdev->vma->node.start);
+ info->fix.smem_len = ifbdev->vma->node.size;
}
- vaddr = i915_vma_pin_iomap(vma);
- if (IS_ERR(vaddr)) {
- drm_err(_priv->drm,
- "Failed to remap framebuffer into virtual memory\n");
- ret = PTR_ERR(vaddr);
- goto out_unpin;
- }
info->screen_base = vaddr;
- info->screen_size = vma->node.size;
+ info->screen_size = ifbdev->vma->node.size;
drm_fb_helper_fill_info(info, >helper, sizes);
@@ -281,23 +296,21 @@ static int intelfb_create(struct drm_fb_helper *helper,
* If the object is stolen however, it will be full of whatever
* garbage was left in there.
*/
- if (!i915_gem_object_is_shmem(vma->obj) && !prealloc)
+ if (!i915_gem_object_is_shmem(ifbdev->vma->obj) && !prealloc)
memset_io(info->screen_base, 0, info->screen_size);
/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
drm_dbg_kms(_priv->drm, "allocated %dx%d fb: 0x%08x\n",
ifbdev->fb->base.width, ifbdev->fb->base.height,
- i915_ggtt_offset(vma));
- ifbdev->vma = vma;
- ifbdev->vma_flags = flags;
+ i915_ggtt_offset(ifbdev->vma));
intel_runtime_pm_put(_priv->runtime_pm, wakeref);
vga_switcheroo_client_fb_set(pdev, info);
return 0;
out_unpin:
- intel_unpin_fb_vma(vma, flags);
+ intel_fbdev_unpin(ifbdev);
out_unlock:
intel_runtime_pm_put(_priv->runtime_pm, wakeref);
return ret;
@@ -316,8 +329,7 @@ static void intel_fbdev_destro
[Intel-gfx] [PATCH 5/8] drm/i915/display: move pin/unpin fb/plane code to a new file.
From: Dave Airlie
This just moves this code out of the i915_display.c into a new
standalone file.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/display/intel_atomic_plane.c | 1 +
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 258 -
drivers/gpu/drm/i915/display/intel_display.h | 8 -
drivers/gpu/drm/i915/display/intel_fb_pin.c | 274 ++
drivers/gpu/drm/i915/display/intel_fb_pin.h | 28 ++
drivers/gpu/drm/i915/display/intel_fbdev.c| 1 +
8 files changed, 306 insertions(+), 267 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_fb_pin.c
create mode 100644 drivers/gpu/drm/i915/display/intel_fb_pin.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5d9794d80bc2..f35485806ec5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -216,6 +216,7 @@ i915-y += \
display/intel_drrs.o \
display/intel_dsb.o \
display/intel_fb.o \
+ display/intel_fb_pin.o \
display/intel_fbc.o \
display/intel_fdi.o \
display/intel_fifo_underrun.o \
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 53ee56453270..0be8c00e3db9 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -39,6 +39,7 @@
#include "intel_atomic_plane.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
+#include "intel_fb_pin.h"
#include "intel_pm.h"
#include "intel_sprite.h"
#include "gt/intel_rps.h"
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index f6dcb5aa63f6..11842f212613 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -17,7 +17,7 @@
#include "intel_display_types.h"
#include "intel_display.h"
#include "intel_fb.h"
-
+#include "intel_fb_pin.h"
#include "intel_frontbuffer.h"
#include "intel_pm.h"
#include "intel_psr.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index b0684537f987..0fe3c2f50971 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -862,198 +862,6 @@ bool intel_plane_uses_fence(const struct
intel_plane_state *plane_state)
plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
}
-static struct i915_vma *
-intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
-const struct i915_ggtt_view *view,
-bool uses_fence,
-unsigned long *out_flags,
-struct i915_address_space *vm)
-{
- struct drm_device *dev = fb->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_i915_gem_object *obj = intel_fb_obj(fb);
- struct i915_vma *vma;
- u32 alignment;
- int ret;
-
- if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
- return ERR_PTR(-EINVAL);
-
- alignment = 4096 * 512;
-
- atomic_inc(_priv->gpu_error.pending_fb_pin);
-
- ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
- if (ret) {
- vma = ERR_PTR(ret);
- goto err;
- }
-
- vma = i915_vma_instance(obj, vm, view);
- if (IS_ERR(vma))
- goto err;
-
- if (i915_vma_misplaced(vma, 0, alignment, 0)) {
- ret = i915_vma_unbind(vma);
- if (ret) {
- vma = ERR_PTR(ret);
- goto err;
- }
- }
-
- ret = i915_vma_pin(vma, 0, alignment, PIN_GLOBAL);
- if (ret) {
- vma = ERR_PTR(ret);
- goto err;
- }
-
- vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
-
- i915_gem_object_flush_if_display(obj);
-
- i915_vma_get(vma);
-err:
- atomic_dec(_priv->gpu_error.pending_fb_pin);
-
- return vma;
-}
-
-struct i915_vma *
-intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
- bool phys_cursor,
- const struct i915_ggtt_view *view,
- bool uses_fence,
- unsigned long *out_flags)
-{
- struct drm_device *dev = fb->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_i915_gem_object *obj = intel_fb_obj(fb);
- intel_wakeref_t wakeref;
- struct i915_gem_ww_ctx ww;
- struct i915_vma *vma;
- unsigned int pinctl;
- u32 alignment;
- int ret;
-
- if (drm_WARN_ON(dev, !i915
[Intel-gfx] [PATCH 4/8] drm/i915/display: refactor initial plane config to a separate file
From: Dave Airlie
This moves this functionality out of intel_display.c to separate
self-contained file.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 279 +
drivers/gpu/drm/i915/display/intel_display.h | 2 +
.../drm/i915/display/intel_plane_initial.c| 283 ++
.../drm/i915/display/intel_plane_initial.h| 13 +
5 files changed, 302 insertions(+), 276 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_plane_initial.c
create mode 100644 drivers/gpu/drm/i915/display/intel_plane_initial.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c36c8a4f0716..5d9794d80bc2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -225,6 +225,7 @@ i915-y += \
display/intel_hotplug.o \
display/intel_lpe_audio.o \
display/intel_overlay.o \
+ display/intel_plane_initial.o \
display/intel_psr.o \
display/intel_quirks.o \
display/intel_sprite.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 39a7b24135c9..b0684537f987 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -95,6 +95,7 @@
#include "intel_overlay.h"
#include "intel_panel.h"
#include "intel_pipe_crc.h"
+#include "intel_plane_initial.h"
#include "intel_pm.h"
#include "intel_pps.h"
#include "intel_psr.h"
@@ -1238,123 +1239,6 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private
*dev_priv,
DRM_MODE_ROTATE_0);
}
-static struct i915_vma *
-initial_plane_vma(struct drm_i915_private *i915,
- struct intel_initial_plane_config *plane_config)
-{
- struct drm_i915_gem_object *obj;
- struct i915_vma *vma;
- u32 base, size;
-
- if (plane_config->size == 0)
- return NULL;
-
- base = round_down(plane_config->base,
- I915_GTT_MIN_ALIGNMENT);
- size = round_up(plane_config->base + plane_config->size,
- I915_GTT_MIN_ALIGNMENT);
- size -= base;
-
- /*
-* If the FB is too big, just don't use it since fbdev is not very
-* important and we should probably use that space with FBC or other
-* features.
-*/
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
- size * 2 > i915->stolen_usable_size)
- return NULL;
-
- obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
- if (IS_ERR(obj))
- return NULL;
-
- /*
-* Mark it WT ahead of time to avoid changing the
-* cache_level during fbdev initialization. The
-* unbind there would get stuck waiting for rcu.
-*/
- i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
- I915_CACHE_WT : I915_CACHE_NONE);
-
- switch (plane_config->tiling) {
- case I915_TILING_NONE:
- break;
- case I915_TILING_X:
- case I915_TILING_Y:
- obj->tiling_and_stride =
- plane_config->fb->base.pitches[0] |
- plane_config->tiling;
- break;
- default:
- MISSING_CASE(plane_config->tiling);
- goto err_obj;
- }
-
- vma = i915_vma_instance(obj, >ggtt.vm, NULL);
- if (IS_ERR(vma))
- goto err_obj;
-
- if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
- goto err_obj;
-
- if (i915_gem_object_is_tiled(obj) &&
- !i915_vma_is_map_and_fenceable(vma))
- goto err_obj;
-
- return vma;
-
-err_obj:
- i915_gem_object_put(obj);
- return NULL;
-}
-
-static bool
-intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
- struct intel_initial_plane_config *plane_config)
-{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_mode_fb_cmd2 mode_cmd = { 0 };
- struct drm_framebuffer *fb = _config->fb->base;
- struct i915_vma *vma;
-
- switch (fb->modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- case I915_FORMAT_MOD_Y_TILED:
- break;
- default:
- drm_dbg(_priv->drm,
- "Unsupported modifier for initial FB: 0x%llx\n",
- fb->modifier);
- return false;
- }
-
- vma = initial_plane_vma(dev_priv, plane_config);
- if (!vma)
- return false;
-
- mode_cmd
[Intel-gfx] [PATCH 3/8] drm/i915/display: refactor out initial plane config for crtcs
From: Dave Airlie
This just pulls this out into a function so it can be moved to
another file easier.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 44 +++-
1 file changed, 25 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 5254180934bb..39a7b24135c9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11460,6 +11460,30 @@ int intel_modeset_init_noirq(struct drm_i915_private
*i915)
return ret;
}
+static void
+intel_crtc_initial_plane_config(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_initial_plane_config plane_config = {};
+
+ /*
+* Note that reserving the BIOS fb up front prevents us
+* from stuffing other stolen allocations like the ring
+* on top. This prevents some ugliness at boot time, and
+* can even allow for smooth boot transitions if the BIOS
+* fb is large enough for the active pipe configuration.
+*/
+ dev_priv->display->get_initial_plane_config(crtc, _config);
+
+ /*
+* If the fb is shared between multiple heads, we'll
+* just get the first one.
+*/
+ intel_find_initial_plane_obj(crtc, _config);
+
+ plane_config_fini(_config);
+}
+
/* part #2: call after irq install, but before gem init */
int intel_modeset_init_nogem(struct drm_i915_private *i915)
{
@@ -11521,27 +11545,9 @@ int intel_modeset_init_nogem(struct drm_i915_private
*i915)
drm_modeset_unlock_all(dev);
for_each_intel_crtc(dev, crtc) {
- struct intel_initial_plane_config plane_config = {};
-
if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
continue;
-
- /*
-* Note that reserving the BIOS fb up front prevents us
-* from stuffing other stolen allocations like the ring
-* on top. This prevents some ugliness at boot time, and
-* can even allow for smooth boot transitions if the BIOS
-* fb is large enough for the active pipe configuration.
-*/
- i915->display->get_initial_plane_config(crtc, _config);
-
- /*
-* If the fb is shared between multiple heads, we'll
-* just get the first one.
-*/
- intel_find_initial_plane_obj(crtc, _config);
-
- plane_config_fini(_config);
+ intel_crtc_initial_plane_config(crtc);
}
/*
--
2.25.4
[Intel-gfx] [PATCH 1/8] drm/i915/display: move plane prepare/cleanup to intel_atomic_plane.c
From: Dave Airlie
Start to refactor more stuff out of intel_display.c. These fit
better in this file.
This moves the rps boosting code as well as this is the only user of it.
Signed-off-by: Dave Airlie
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 208 ++
drivers/gpu/drm/i915/display/intel_display.c | 208 --
drivers/gpu/drm/i915/display/intel_display.h | 4 -
3 files changed, 208 insertions(+), 212 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 47234d898549..53ee56453270 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -41,6 +41,7 @@
#include "intel_display_types.h"
#include "intel_pm.h"
#include "intel_sprite.h"
+#include "gt/intel_rps.h"
static void intel_plane_state_reset(struct intel_plane_state *plane_state,
struct intel_plane *plane)
@@ -601,6 +602,213 @@ int intel_atomic_plane_check_clipping(struct
intel_plane_state *plane_state,
return 0;
}
+struct wait_rps_boost {
+ struct wait_queue_entry wait;
+
+ struct drm_crtc *crtc;
+ struct i915_request *request;
+};
+
+static int do_rps_boost(struct wait_queue_entry *_wait,
+ unsigned mode, int sync, void *key)
+{
+ struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
+ struct i915_request *rq = wait->request;
+
+ /*
+* If we missed the vblank, but the request is already running it
+* is reasonable to assume that it will complete before the next
+* vblank without our intervention, so leave RPS alone.
+*/
+ if (!i915_request_started(rq))
+ intel_rps_boost(rq);
+ i915_request_put(rq);
+
+ drm_crtc_vblank_put(wait->crtc);
+
+ list_del(>wait.entry);
+ kfree(wait);
+ return 1;
+}
+
+static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
+ struct dma_fence *fence)
+{
+ struct wait_rps_boost *wait;
+
+ if (!dma_fence_is_i915(fence))
+ return;
+
+ if (DISPLAY_VER(to_i915(crtc->dev)) < 6)
+ return;
+
+ if (drm_crtc_vblank_get(crtc))
+ return;
+
+ wait = kmalloc(sizeof(*wait), GFP_KERNEL);
+ if (!wait) {
+ drm_crtc_vblank_put(crtc);
+ return;
+ }
+
+ wait->request = to_request(dma_fence_get(fence));
+ wait->crtc = crtc;
+
+ wait->wait.func = do_rps_boost;
+ wait->wait.flags = 0;
+
+ add_wait_queue(drm_crtc_vblank_waitqueue(crtc), >wait);
+}
+
+/**
+ * intel_prepare_plane_fb - Prepare fb for usage on plane
+ * @_plane: drm plane to prepare for
+ * @_new_plane_state: the plane state being prepared
+ *
+ * Prepares a framebuffer for usage on a display plane. Generally this
+ * involves pinning the underlying object and updating the frontbuffer tracking
+ * bits. Some older platforms need special physical address handling for
+ * cursor planes.
+ *
+ * Returns 0 on success, negative error code on failure.
+ */
+static int
+intel_prepare_plane_fb(struct drm_plane *_plane,
+ struct drm_plane_state *_new_plane_state)
+{
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
+ struct intel_plane *plane = to_intel_plane(_plane);
+ struct intel_plane_state *new_plane_state =
+ to_intel_plane_state(_new_plane_state);
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(new_plane_state->uapi.state);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ const struct intel_plane_state *old_plane_state =
+ intel_atomic_get_old_plane_state(state, plane);
+ struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
+ struct drm_i915_gem_object *old_obj =
intel_fb_obj(old_plane_state->hw.fb);
+ int ret;
+
+ if (old_obj) {
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state,
+
to_intel_crtc(old_plane_state->hw.crtc));
+
+ /* Big Hammer, we also need to ensure that any pending
+* MI_WAIT_FOR_EVENT inside a user batch buffer on the
+* current scanout is retired before unpinning the old
+* framebuffer. Note that we rely on userspace rendering
+* into the buffer attached to the pipe they are waiting
+* on. If not, userspace generates a GPU hang with IPEHR
+* point to the MI_WAIT_FOR_EVENT.
+*
+* This should only fail upon a hung GPU, in which case we
+*
[Intel-gfx] [PATCH 2/8] drm/i915/display: let intel_plane_uses_fence be used from other places.
From: Dave Airlie
I want to refactor some stuff using this so make it shared.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d1fa17929b1f..5254180934bb 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -851,7 +851,7 @@ unsigned int intel_remapped_info_size(const struct
intel_remapped_info *rem_info
return size;
}
-static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
+bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
{
struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
diff --git a/drivers/gpu/drm/i915/display/intel_display.h
b/drivers/gpu/drm/i915/display/intel_display.h
index a08903bb7647..d655d996d465 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -615,6 +615,7 @@ void ilk_pfit_disable(const struct intel_crtc_state
*old_crtc_state);
int bdw_get_pipemisc_bpp(struct intel_crtc *crtc);
unsigned int intel_plane_fence_y_offset(const struct intel_plane_state
*plane_state);
+bool intel_plane_uses_fence(const struct intel_plane_state *plane_state);
bool
intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info,
u64 modifier);
--
2.25.4
[Intel-gfx] [RFC PATCH 0/8] drm/i915/display: refactor plane config + pin out (v2)
This is another series in the refactor intel_display.c into more manageable places. This moves the initial plane config and all the fb pin/unpin code out. It also refactors both a little to make the interfaces cleaner. v2: just address the minor comments from Jani. Jani, I think Ville doesn't mind the resulting layout. Dave.
Re: [Intel-gfx] [RFC PATCH 0/8] drm/i915/display: refactor plane config + pin out
On Thu, 7 Oct 2021 at 21:09, Ville Syrjälä wrote: > > On Thu, Oct 07, 2021 at 01:52:42PM +0300, Jani Nikula wrote: > > On Thu, 07 Oct 2021, Dave Airlie wrote: > > > This is another series in the refactor intel_display.c into more > > > manageable > > > places. > > > > > > This moves the initial plane config and all the fb pin/unpin code out. > > > > > > It also refactors both a little to make the interfaces cleaner. > > > > I had a few nitpicks I commented on. Overall this looks good to me, but > > I'd like Ville's input on the code movement at the high level, are the > > split and files sane etc. I can do the detailed review after that. > > Some of it feels a bit ad-hoc, but I don't really have a better > idea for splitting some of these right now. So might as well go > with this I guess. cscope will find the stuff for me in the end, > at least after I remember to have it reindex. My main goal was separation of things that interface with gem into separate files for now. I'd like to formalise that interface a bit more if we can, it might not bear fruit but I think it would be independently useful cleanup anyways. Dave.
[Intel-gfx] [PATCH 8/8] drm/i915/display: drop unused parameter to dpt pin
From: Dave Airlie
The uses_fence isn't used.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index 760436b99a34..fac94e1fec8b 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -18,7 +18,6 @@
static struct i915_vma *
intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
const struct i915_ggtt_view *view,
-bool uses_fence,
unsigned long *out_flags,
struct i915_address_space *vm)
{
@@ -236,7 +235,7 @@ int intel_plane_pin_fb(struct intel_plane_state
*plane_state)
plane_state->ggtt_vma = vma;
- vma = intel_pin_fb_obj_dpt(fb, _state->view.gtt, false,
+ vma = intel_pin_fb_obj_dpt(fb, _state->view.gtt,
_state->flags,
intel_fb->dpt_vm);
if (IS_ERR(vma)) {
intel_dpt_unpin(intel_fb->dpt_vm);
--
2.25.4
[Intel-gfx] [PATCH 7/8] drm/i915/display: move fbdev pin code into fb_pin
From: Dave Airlie
This moves the fbdev pin code over and moves the internal
interfaces to static.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fb_pin.c | 34 +++--
drivers/gpu/drm/i915/display/intel_fb_pin.h | 15 -
drivers/gpu/drm/i915/display/intel_fbdev.c | 29 --
3 files changed, 38 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c
b/drivers/gpu/drm/i915/display/intel_fb_pin.c
index c5f6dd1aab80..760436b99a34 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.c
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c
@@ -71,7 +71,7 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
return vma;
}
-struct i915_vma *
+static struct i915_vma *
intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
bool phys_cursor,
const struct i915_ggtt_view *view,
@@ -199,7 +199,8 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
return vma;
}
-void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
+static void
+intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
{
if (flags & PLANE_HAS_FENCE)
i915_vma_unpin_fence(vma);
@@ -272,3 +273,32 @@ void intel_plane_unpin_fb(struct intel_plane_state
*old_plane_state)
intel_dpt_unpin(intel_fb->dpt_vm);
}
}
+
+int intel_fbdev_pin_and_fence(struct drm_i915_private *dev_priv,
+ struct intel_fbdev *ifbdev,
+ void **vaddr)
+{
+ const struct i915_ggtt_view view = {
+ .type = I915_GGTT_VIEW_NORMAL,
+ };
+ ifbdev->vma = intel_pin_and_fence_fb_obj(>fb->base, false,
+, false,
>vma_flags);
+
+ if (IS_ERR(ifbdev->vma)) {
+ return PTR_ERR(ifbdev->vma);
+ }
+
+ *vaddr = i915_vma_pin_iomap(ifbdev->vma);
+ if (IS_ERR(*vaddr)) {
+ drm_err(_priv->drm,
+ "Failed to remap framebuffer into virtual memory\n");
+ return PTR_ERR(vaddr);
+ }
+ return 0;
+}
+
+void intel_fbdev_unpin(struct intel_fbdev *ifbdev)
+{
+ if (ifbdev->vma)
+ intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h
b/drivers/gpu/drm/i915/display/intel_fb_pin.h
index e4fcd0218d9d..88d736264348 100644
--- a/drivers/gpu/drm/i915/display/intel_fb_pin.h
+++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h
@@ -8,21 +8,18 @@
#include
+struct drm_i915_private;
struct drm_framebuffer;
+struct intel_fbdev;
struct i915_vma;
struct intel_plane_state;
struct i915_ggtt_view;
-struct i915_vma *
-intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
- bool phys_cursor,
- const struct i915_ggtt_view *view,
- bool uses_fence,
- unsigned long *out_flags);
-
-void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
-
int intel_plane_pin_fb(struct intel_plane_state *plane_state);
void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state);
+int intel_fbdev_pin_and_fence(struct drm_i915_private *dev_priv,
+ struct intel_fbdev *ifbdev,
+ void **vaddr);
+void intel_fbdev_unpin(struct intel_fbdev *ifbdev);
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 7ac9348d20c5..cee85fcc2085 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -171,35 +171,6 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
return 0;
}
-static int intel_fbdev_pin_and_fence(struct drm_i915_private *dev_priv,
-struct intel_fbdev *ifbdev,
-void **vaddr)
-{
- const struct i915_ggtt_view view = {
- .type = I915_GGTT_VIEW_NORMAL,
- };
- ifbdev->vma = intel_pin_and_fence_fb_obj(>fb->base, false,
-, false,
>vma_flags);
-
- if (IS_ERR(ifbdev->vma)) {
- return PTR_ERR(ifbdev->vma);
- }
-
- *vaddr = i915_vma_pin_iomap(ifbdev->vma);
- if (IS_ERR(*vaddr)) {
- drm_err(_priv->drm,
- "Failed to remap framebuffer into virtual memory\n");
- return PTR_ERR(vaddr);
- }
- return 0;
-}
-
-static void intel_fbdev_unpin(struct intel_fbdev *ifbdev)
-{
- if (ifbdev->vma)
- intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags);
-}
-
static int intelfb_create(struct drm_fb_helper *helper,
struct drm_fb_helper_surface_size *sizes)
{
--
2.25.4
[Intel-gfx] [PATCH 6/8] drm/i915/display: refactor fbdev pin/unpin out into functions.
From: Dave Airlie
This just cleans up the calls a bit.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fbdev.c | 64 +-
1 file changed, 38 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index adc3a81be9f7..7ac9348d20c5 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -171,6 +171,35 @@ static int intelfb_alloc(struct drm_fb_helper *helper,
return 0;
}
+static int intel_fbdev_pin_and_fence(struct drm_i915_private *dev_priv,
+struct intel_fbdev *ifbdev,
+void **vaddr)
+{
+ const struct i915_ggtt_view view = {
+ .type = I915_GGTT_VIEW_NORMAL,
+ };
+ ifbdev->vma = intel_pin_and_fence_fb_obj(>fb->base, false,
+, false,
>vma_flags);
+
+ if (IS_ERR(ifbdev->vma)) {
+ return PTR_ERR(ifbdev->vma);
+ }
+
+ *vaddr = i915_vma_pin_iomap(ifbdev->vma);
+ if (IS_ERR(*vaddr)) {
+ drm_err(_priv->drm,
+ "Failed to remap framebuffer into virtual memory\n");
+ return PTR_ERR(vaddr);
+ }
+ return 0;
+}
+
+static void intel_fbdev_unpin(struct intel_fbdev *ifbdev)
+{
+ if (ifbdev->vma)
+ intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags);
+}
+
static int intelfb_create(struct drm_fb_helper *helper,
struct drm_fb_helper_surface_size *sizes)
{
@@ -181,13 +210,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
struct i915_ggtt *ggtt = _priv->ggtt;
- const struct i915_ggtt_view view = {
- .type = I915_GGTT_VIEW_NORMAL,
- };
intel_wakeref_t wakeref;
struct fb_info *info;
- struct i915_vma *vma;
- unsigned long flags = 0;
bool prealloc = false;
void __iomem *vaddr;
struct drm_i915_gem_object *obj;
@@ -224,10 +248,8 @@ static int intelfb_create(struct drm_fb_helper *helper,
* This also validates that any existing fb inherited from the
* BIOS is suitable for own access.
*/
- vma = intel_pin_and_fence_fb_obj(>fb->base, false,
-, false, );
- if (IS_ERR(vma)) {
- ret = PTR_ERR(vma);
+ ret = intel_fbdev_pin_and_fence(dev_priv, ifbdev, );
+ if (ret) {
goto out_unlock;
}
@@ -261,19 +283,12 @@ static int intelfb_create(struct drm_fb_helper *helper,
/* Our framebuffer is the entirety of fbdev's system memory */
info->fix.smem_start =
- (unsigned long)(ggtt->gmadr.start + vma->node.start);
- info->fix.smem_len = vma->node.size;
+ (unsigned long)(ggtt->gmadr.start +
ifbdev->vma->node.start);
+ info->fix.smem_len = ifbdev->vma->node.size;
}
- vaddr = i915_vma_pin_iomap(vma);
- if (IS_ERR(vaddr)) {
- drm_err(_priv->drm,
- "Failed to remap framebuffer into virtual memory\n");
- ret = PTR_ERR(vaddr);
- goto out_unpin;
- }
info->screen_base = vaddr;
- info->screen_size = vma->node.size;
+ info->screen_size = ifbdev->vma->node.size;
drm_fb_helper_fill_info(info, >helper, sizes);
@@ -281,23 +296,21 @@ static int intelfb_create(struct drm_fb_helper *helper,
* If the object is stolen however, it will be full of whatever
* garbage was left in there.
*/
- if (!i915_gem_object_is_shmem(vma->obj) && !prealloc)
+ if (!i915_gem_object_is_shmem(ifbdev->vma->obj) && !prealloc)
memset_io(info->screen_base, 0, info->screen_size);
/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
drm_dbg_kms(_priv->drm, "allocated %dx%d fb: 0x%08x\n",
ifbdev->fb->base.width, ifbdev->fb->base.height,
- i915_ggtt_offset(vma));
- ifbdev->vma = vma;
- ifbdev->vma_flags = flags;
+ i915_ggtt_offset(ifbdev->vma));
intel_runtime_pm_put(_priv->runtime_pm, wakeref);
vga_switcheroo_client_fb_set(pdev, info);
return 0;
out_unpin:
- intel_unpin_fb_vma(vma, flags);
+ intel_fbdev_unpin(ifbdev);
out_unlock:
intel_runtime_pm_put(_priv->runtime_pm, wakeref);
return ret;
@@ -316,8 +329,7 @@ static void intel_fbdev_destro
[Intel-gfx] [PATCH 5/8] drm/i915/display: move pin/unpin fb/plane code to a new file.
From: Dave Airlie
This just moves this code out of the i915_display.c into a new
standalone file.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/display/intel_atomic_plane.c | 1 +
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 258 -
drivers/gpu/drm/i915/display/intel_display.h | 8 -
drivers/gpu/drm/i915/display/intel_fb_pin.c | 274 ++
drivers/gpu/drm/i915/display/intel_fb_pin.h | 28 ++
drivers/gpu/drm/i915/display/intel_fbdev.c| 1 +
8 files changed, 306 insertions(+), 267 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_fb_pin.c
create mode 100644 drivers/gpu/drm/i915/display/intel_fb_pin.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 5d9794d80bc2..f35485806ec5 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -216,6 +216,7 @@ i915-y += \
display/intel_drrs.o \
display/intel_dsb.o \
display/intel_fb.o \
+ display/intel_fb_pin.o \
display/intel_fbc.o \
display/intel_fdi.o \
display/intel_fifo_underrun.o \
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 53ee56453270..0be8c00e3db9 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -39,6 +39,7 @@
#include "intel_atomic_plane.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
+#include "intel_fb_pin.h"
#include "intel_pm.h"
#include "intel_sprite.h"
#include "gt/intel_rps.h"
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c
b/drivers/gpu/drm/i915/display/intel_cursor.c
index f6dcb5aa63f6..11842f212613 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -17,7 +17,7 @@
#include "intel_display_types.h"
#include "intel_display.h"
#include "intel_fb.h"
-
+#include "intel_fb_pin.h"
#include "intel_frontbuffer.h"
#include "intel_pm.h"
#include "intel_psr.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 537058a7a834..0580ae353013 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -852,198 +852,6 @@ unsigned int intel_remapped_info_size(const struct
intel_remapped_info *rem_info
return size;
}
-static struct i915_vma *
-intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
-const struct i915_ggtt_view *view,
-bool uses_fence,
-unsigned long *out_flags,
-struct i915_address_space *vm)
-{
- struct drm_device *dev = fb->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_i915_gem_object *obj = intel_fb_obj(fb);
- struct i915_vma *vma;
- u32 alignment;
- int ret;
-
- if (WARN_ON(!i915_gem_object_is_framebuffer(obj)))
- return ERR_PTR(-EINVAL);
-
- alignment = 4096 * 512;
-
- atomic_inc(_priv->gpu_error.pending_fb_pin);
-
- ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
- if (ret) {
- vma = ERR_PTR(ret);
- goto err;
- }
-
- vma = i915_vma_instance(obj, vm, view);
- if (IS_ERR(vma))
- goto err;
-
- if (i915_vma_misplaced(vma, 0, alignment, 0)) {
- ret = i915_vma_unbind(vma);
- if (ret) {
- vma = ERR_PTR(ret);
- goto err;
- }
- }
-
- ret = i915_vma_pin(vma, 0, alignment, PIN_GLOBAL);
- if (ret) {
- vma = ERR_PTR(ret);
- goto err;
- }
-
- vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
-
- i915_gem_object_flush_if_display(obj);
-
- i915_vma_get(vma);
-err:
- atomic_dec(_priv->gpu_error.pending_fb_pin);
-
- return vma;
-}
-
-struct i915_vma *
-intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
- bool phys_cursor,
- const struct i915_ggtt_view *view,
- bool uses_fence,
- unsigned long *out_flags)
-{
- struct drm_device *dev = fb->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_i915_gem_object *obj = intel_fb_obj(fb);
- intel_wakeref_t wakeref;
- struct i915_gem_ww_ctx ww;
- struct i915_vma *vma;
- unsigned int pinctl;
- u32 alignment;
- int ret;
-
- if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj)))
-
[Intel-gfx] [PATCH 4/8] drm/i915/display: refactor initial plane config to a separate file
From: Dave Airlie
This moves this functionality out of intel_display.c to separate
self-contained file.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 279 +
drivers/gpu/drm/i915/display/intel_display.h | 2 +
.../drm/i915/display/intel_plane_initial.c| 283 ++
.../drm/i915/display/intel_plane_initial.h| 13 +
5 files changed, 302 insertions(+), 276 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_plane_initial.c
create mode 100644 drivers/gpu/drm/i915/display/intel_plane_initial.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c36c8a4f0716..5d9794d80bc2 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -225,6 +225,7 @@ i915-y += \
display/intel_hotplug.o \
display/intel_lpe_audio.o \
display/intel_overlay.o \
+ display/intel_plane_initial.o \
display/intel_psr.o \
display/intel_quirks.o \
display/intel_sprite.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index cc1707453a94..537058a7a834 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -95,6 +95,7 @@
#include "intel_overlay.h"
#include "intel_panel.h"
#include "intel_pipe_crc.h"
+#include "intel_plane_initial.h"
#include "intel_pm.h"
#include "intel_pps.h"
#include "intel_psr.h"
@@ -1228,123 +1229,6 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private
*dev_priv,
DRM_MODE_ROTATE_0);
}
-static struct i915_vma *
-initial_plane_vma(struct drm_i915_private *i915,
- struct intel_initial_plane_config *plane_config)
-{
- struct drm_i915_gem_object *obj;
- struct i915_vma *vma;
- u32 base, size;
-
- if (plane_config->size == 0)
- return NULL;
-
- base = round_down(plane_config->base,
- I915_GTT_MIN_ALIGNMENT);
- size = round_up(plane_config->base + plane_config->size,
- I915_GTT_MIN_ALIGNMENT);
- size -= base;
-
- /*
-* If the FB is too big, just don't use it since fbdev is not very
-* important and we should probably use that space with FBC or other
-* features.
-*/
- if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) &&
- size * 2 > i915->stolen_usable_size)
- return NULL;
-
- obj = i915_gem_object_create_stolen_for_preallocated(i915, base, size);
- if (IS_ERR(obj))
- return NULL;
-
- /*
-* Mark it WT ahead of time to avoid changing the
-* cache_level during fbdev initialization. The
-* unbind there would get stuck waiting for rcu.
-*/
- i915_gem_object_set_cache_coherency(obj, HAS_WT(i915) ?
- I915_CACHE_WT : I915_CACHE_NONE);
-
- switch (plane_config->tiling) {
- case I915_TILING_NONE:
- break;
- case I915_TILING_X:
- case I915_TILING_Y:
- obj->tiling_and_stride =
- plane_config->fb->base.pitches[0] |
- plane_config->tiling;
- break;
- default:
- MISSING_CASE(plane_config->tiling);
- goto err_obj;
- }
-
- vma = i915_vma_instance(obj, >ggtt.vm, NULL);
- if (IS_ERR(vma))
- goto err_obj;
-
- if (i915_ggtt_pin(vma, NULL, 0, PIN_MAPPABLE | PIN_OFFSET_FIXED | base))
- goto err_obj;
-
- if (i915_gem_object_is_tiled(obj) &&
- !i915_vma_is_map_and_fenceable(vma))
- goto err_obj;
-
- return vma;
-
-err_obj:
- i915_gem_object_put(obj);
- return NULL;
-}
-
-static bool
-intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
- struct intel_initial_plane_config *plane_config)
-{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct drm_mode_fb_cmd2 mode_cmd = { 0 };
- struct drm_framebuffer *fb = _config->fb->base;
- struct i915_vma *vma;
-
- switch (fb->modifier) {
- case DRM_FORMAT_MOD_LINEAR:
- case I915_FORMAT_MOD_X_TILED:
- case I915_FORMAT_MOD_Y_TILED:
- break;
- default:
- drm_dbg(_priv->drm,
- "Unsupported modifier for initial FB: 0x%llx\n",
- fb->modifier);
- return false;
- }
-
- vma = initial_plane_vma(dev_priv, plane_config);
- if (!vma)
- return false;
-
- mode_cmd
[Intel-gfx] [PATCH 3/8] drm/i915/display: refactor out initial plane config for crtcs
From: Dave Airlie
This just pulls this out into a function so it can be moved to
another file easier.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 44 +++-
1 file changed, 25 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index b26e1989b8d8..cc1707453a94 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -11450,6 +11450,30 @@ int intel_modeset_init_noirq(struct drm_i915_private
*i915)
return ret;
}
+static void
+intel_crtc_initial_plane_config(struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_initial_plane_config plane_config = {};
+
+ /*
+* Note that reserving the BIOS fb up front prevents us
+* from stuffing other stolen allocations like the ring
+* on top. This prevents some ugliness at boot time, and
+* can even allow for smooth boot transitions if the BIOS
+* fb is large enough for the active pipe configuration.
+*/
+ dev_priv->display->get_initial_plane_config(crtc, _config);
+
+ /*
+* If the fb is shared between multiple heads, we'll
+* just get the first one.
+*/
+ intel_find_initial_plane_obj(crtc, _config);
+
+ plane_config_fini(_config);
+}
+
/* part #2: call after irq install, but before gem init */
int intel_modeset_init_nogem(struct drm_i915_private *i915)
{
@@ -11511,27 +11535,9 @@ int intel_modeset_init_nogem(struct drm_i915_private
*i915)
drm_modeset_unlock_all(dev);
for_each_intel_crtc(dev, crtc) {
- struct intel_initial_plane_config plane_config = {};
-
if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
continue;
-
- /*
-* Note that reserving the BIOS fb up front prevents us
-* from stuffing other stolen allocations like the ring
-* on top. This prevents some ugliness at boot time, and
-* can even allow for smooth boot transitions if the BIOS
-* fb is large enough for the active pipe configuration.
-*/
- i915->display->get_initial_plane_config(crtc, _config);
-
- /*
-* If the fb is shared between multiple heads, we'll
-* just get the first one.
-*/
- intel_find_initial_plane_obj(crtc, _config);
-
- plane_config_fini(_config);
+ intel_crtc_initial_plane_config(crtc);
}
/*
--
2.25.4
[Intel-gfx] [PATCH 2/8] drm/i915/display: move intel_plane_uses_fence to inline.
From: Dave Airlie
Make future refactoring simpler, but also this function is pretty
trivial.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 10 --
drivers/gpu/drm/i915/display/intel_display_types.h | 10 ++
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index d1fa17929b1f..b26e1989b8d8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -851,16 +851,6 @@ unsigned int intel_remapped_info_size(const struct
intel_remapped_info *rem_info
return size;
}
-static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
-{
- struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-
- return DISPLAY_VER(dev_priv) < 4 ||
- (plane->has_fbc &&
-plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
-}
-
static struct i915_vma *
intel_pin_fb_obj_dpt(struct drm_framebuffer *fb,
const struct i915_ggtt_view *view,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index a811e13720bf..eebb46d0b0b9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2030,6 +2030,16 @@ static inline u32 intel_plane_ggtt_offset(const struct
intel_plane_state *plane_
return i915_ggtt_offset(plane_state->ggtt_vma);
}
+static inline bool intel_plane_uses_fence(const struct intel_plane_state
*plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+
+ return DISPLAY_VER(dev_priv) < 4 ||
+ (plane->has_fbc &&
+plane_state->view.gtt.type == I915_GGTT_VIEW_NORMAL);
+}
+
static inline struct intel_frontbuffer *
to_intel_frontbuffer(struct drm_framebuffer *fb)
{
--
2.25.4
[Intel-gfx] [PATCH 1/8] drm/i915/display: move plane prepare/cleanup to intel_atomic_plane.c
From: Dave Airlie
Start to refactor more stuff out of intel_display.c. These fit
better in this file.
This moves the rps boosting code as well as this is the only user of it.
Signed-off-by: Dave Airlie
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 208 ++
drivers/gpu/drm/i915/display/intel_display.c | 208 --
drivers/gpu/drm/i915/display/intel_display.h | 4 -
3 files changed, 208 insertions(+), 212 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 47234d898549..53ee56453270 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -41,6 +41,7 @@
#include "intel_display_types.h"
#include "intel_pm.h"
#include "intel_sprite.h"
+#include "gt/intel_rps.h"
static void intel_plane_state_reset(struct intel_plane_state *plane_state,
struct intel_plane *plane)
@@ -601,6 +602,213 @@ int intel_atomic_plane_check_clipping(struct
intel_plane_state *plane_state,
return 0;
}
+struct wait_rps_boost {
+ struct wait_queue_entry wait;
+
+ struct drm_crtc *crtc;
+ struct i915_request *request;
+};
+
+static int do_rps_boost(struct wait_queue_entry *_wait,
+ unsigned mode, int sync, void *key)
+{
+ struct wait_rps_boost *wait = container_of(_wait, typeof(*wait), wait);
+ struct i915_request *rq = wait->request;
+
+ /*
+* If we missed the vblank, but the request is already running it
+* is reasonable to assume that it will complete before the next
+* vblank without our intervention, so leave RPS alone.
+*/
+ if (!i915_request_started(rq))
+ intel_rps_boost(rq);
+ i915_request_put(rq);
+
+ drm_crtc_vblank_put(wait->crtc);
+
+ list_del(>wait.entry);
+ kfree(wait);
+ return 1;
+}
+
+static void add_rps_boost_after_vblank(struct drm_crtc *crtc,
+ struct dma_fence *fence)
+{
+ struct wait_rps_boost *wait;
+
+ if (!dma_fence_is_i915(fence))
+ return;
+
+ if (DISPLAY_VER(to_i915(crtc->dev)) < 6)
+ return;
+
+ if (drm_crtc_vblank_get(crtc))
+ return;
+
+ wait = kmalloc(sizeof(*wait), GFP_KERNEL);
+ if (!wait) {
+ drm_crtc_vblank_put(crtc);
+ return;
+ }
+
+ wait->request = to_request(dma_fence_get(fence));
+ wait->crtc = crtc;
+
+ wait->wait.func = do_rps_boost;
+ wait->wait.flags = 0;
+
+ add_wait_queue(drm_crtc_vblank_waitqueue(crtc), >wait);
+}
+
+/**
+ * intel_prepare_plane_fb - Prepare fb for usage on plane
+ * @_plane: drm plane to prepare for
+ * @_new_plane_state: the plane state being prepared
+ *
+ * Prepares a framebuffer for usage on a display plane. Generally this
+ * involves pinning the underlying object and updating the frontbuffer tracking
+ * bits. Some older platforms need special physical address handling for
+ * cursor planes.
+ *
+ * Returns 0 on success, negative error code on failure.
+ */
+static int
+intel_prepare_plane_fb(struct drm_plane *_plane,
+ struct drm_plane_state *_new_plane_state)
+{
+ struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
+ struct intel_plane *plane = to_intel_plane(_plane);
+ struct intel_plane_state *new_plane_state =
+ to_intel_plane_state(_new_plane_state);
+ struct intel_atomic_state *state =
+ to_intel_atomic_state(new_plane_state->uapi.state);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ const struct intel_plane_state *old_plane_state =
+ intel_atomic_get_old_plane_state(state, plane);
+ struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
+ struct drm_i915_gem_object *old_obj =
intel_fb_obj(old_plane_state->hw.fb);
+ int ret;
+
+ if (old_obj) {
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state,
+
to_intel_crtc(old_plane_state->hw.crtc));
+
+ /* Big Hammer, we also need to ensure that any pending
+* MI_WAIT_FOR_EVENT inside a user batch buffer on the
+* current scanout is retired before unpinning the old
+* framebuffer. Note that we rely on userspace rendering
+* into the buffer attached to the pipe they are waiting
+* on. If not, userspace generates a GPU hang with IPEHR
+* point to the MI_WAIT_FOR_EVENT.
+*
+* This should only fail upon a hung GPU, in which case we
+*
[Intel-gfx] [RFC PATCH 0/8] drm/i915/display: refactor plane config + pin out
This is another series in the refactor intel_display.c into more manageable places. This moves the initial plane config and all the fb pin/unpin code out. It also refactors both a little to make the interfaces cleaner. Dave.
[Intel-gfx] [PATCH] drm/i915/irq: don't use gt ptr for no reason.
From: Dave Airlie
Neither of these functions want the gt at all, just pass regs
and i915.
Just noticed in passing.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_irq.c | 21 +
1 file changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 77680bca46ee..67e3ac07f07d 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2652,9 +2652,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
}
static u32
-gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
+gen11_gu_misc_irq_ack(void __iomem * const regs, const u32 master_ctl)
{
- void __iomem * const regs = gt->uncore->regs;
u32 iir;
if (!(master_ctl & GEN11_GU_MISC_IRQ))
@@ -2668,10 +2667,10 @@ gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32
master_ctl)
}
static void
-gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
+gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir)
{
if (iir & GEN11_GU_MISC_GSE)
- intel_opregion_asle_intr(gt->i915);
+ intel_opregion_asle_intr(i915);
}
static inline u32 gen11_master_intr_disable(void __iomem * const regs)
@@ -2715,7 +2714,6 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
{
struct drm_i915_private *i915 = arg;
void __iomem * const regs = i915->uncore.regs;
- struct intel_gt *gt = >gt;
u32 master_ctl;
u32 gu_misc_iir;
@@ -2729,17 +2727,17 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
}
/* Find, queue (onto bottom-halves), then clear each source */
- gen11_gt_irq_handler(gt, master_ctl);
+ gen11_gt_irq_handler(>gt, master_ctl);
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
if (master_ctl & GEN11_DISPLAY_IRQ)
gen11_display_irq_handler(i915);
- gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
+ gu_misc_iir = gen11_gu_misc_irq_ack(regs, master_ctl);
gen11_master_intr_enable(regs);
- gen11_gu_misc_irq_handler(gt, gu_misc_iir);
+ gen11_gu_misc_irq_handler(i915, gu_misc_iir);
pmu_irq_stats(i915, IRQ_HANDLED);
@@ -2771,7 +2769,6 @@ static inline void dg1_master_intr_enable(void __iomem *
const regs)
static irqreturn_t dg1_irq_handler(int irq, void *arg)
{
struct drm_i915_private * const i915 = arg;
- struct intel_gt *gt = >gt;
void __iomem * const regs = i915->uncore.regs;
u32 master_tile_ctl, master_ctl;
u32 gu_misc_iir;
@@ -2795,16 +2792,16 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
return IRQ_NONE;
}
- gen11_gt_irq_handler(gt, master_ctl);
+ gen11_gt_irq_handler(>gt, master_ctl);
if (master_ctl & GEN11_DISPLAY_IRQ)
gen11_display_irq_handler(i915);
- gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
+ gu_misc_iir = gen11_gu_misc_irq_ack(regs, master_ctl);
dg1_master_intr_enable(regs);
- gen11_gu_misc_irq_handler(gt, gu_misc_iir);
+ gen11_gu_misc_irq_handler(i915, gu_misc_iir);
pmu_irq_stats(i915, IRQ_HANDLED);
--
2.25.4
Re: [Intel-gfx] [PATCH 01/24] drm/i915/uncore: split the fw get function into separate vfunc
On Sun, 3 Oct 2021 at 05:27, Ville Syrjälä wrote: > > On Wed, Sep 29, 2021 at 01:57:45AM +0300, Jani Nikula wrote: > > From: Dave Airlie > > > > constify it while here. drop the put function since it was never > > overloaded and always has done the same thing, no point in > > indirecting it for show. > > > > Reviewed-by: Jani Nikula > > Signed-off-by: Dave Airlie > > Signed-off-by: Jani Nikula > > This has totally broken snb and ivb machines. Total death > ensues somewhere in uncore init after some backtraces fly by. > Didn't get any logs out to disk unfortunately. Please revert. > > Sadly CI is still afraid to report when machines disappear. > For the bat report you at least get a list of machines that > were awol, but the shard run seems to not even mention that > all snbs suddenly vanished. > > I've said it before and I'll say it again. We really should > *not* be loading i915 when the machine boots. That way we'd > at least get the machine up and running and can report that > loading i915 is the thing that killed it... That is frustrating, I've sent a oneline fix that should fix it up. hopefully CI will pick it up. Dave.
[Intel-gfx] [PATCH] drm/i915: fix regression with uncore refactoring.
From: Dave Airlie
This was causing infinite recursion on snb/ivb.
Fixes: 5716c8c6f4b6 ("drm/i915/uncore: split the fw get function into separate
vfunc")
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 2dac69d92c1b..f1b816ebcdf6 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -346,7 +346,7 @@ static void __gen6_gt_wait_for_thread_c0(struct
intel_uncore *uncore)
static void fw_domains_get_with_thread_status(struct intel_uncore *uncore,
enum forcewake_domains fw_domains)
{
- fw_domains_get(uncore, fw_domains);
+ fw_domains_get_normal(uncore, fw_domains);
/* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
__gen6_gt_wait_for_thread_c0(uncore);
--
2.25.4
Re: [Intel-gfx] [PATCH 1/5] drm/i915: Do not define vma on stack
On Tue, 14 Sept 2021 at 14:55, Matthew Brost wrote:
>
> From: Venkata Sandeep Dhanalakota
>
> Defining vma on stack can cause stack overflow, if
> vma gets populated with new fields.
Is there some higher level locking stopping that from getting trashed?
or a guarantee that uc_fw_bind_ggtt is only entered by one thread at a
time?
Dave.
>
> Cc: Daniele Ceraolo Spurio
> Cc: Tvrtko Ursulin
> Signed-off-by: Venkata Sandeep Dhanalakota
> Signed-off-by: Matthew Brost
> Reviewed-by: Matthew Brost
> ---
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 18 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h | 2 ++
> 2 files changed, 11 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index 3a16d08608a5..f632dbd32b42 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -413,20 +413,20 @@ static void uc_fw_bind_ggtt(struct intel_uc_fw *uc_fw)
> {
> struct drm_i915_gem_object *obj = uc_fw->obj;
> struct i915_ggtt *ggtt = __uc_fw_to_gt(uc_fw)->ggtt;
> - struct i915_vma dummy = {
> - .node.start = uc_fw_ggtt_offset(uc_fw),
> - .node.size = obj->base.size,
> - .pages = obj->mm.pages,
> - .vm = >vm,
> - };
> + struct i915_vma *dummy = _fw->dummy;
> +
> + dummy->node.start = uc_fw_ggtt_offset(uc_fw);
> + dummy->node.size = obj->base.size;
> + dummy->pages = obj->mm.pages;
> + dummy->vm = >vm;
>
> GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
> - GEM_BUG_ON(dummy.node.size > ggtt->uc_fw.size);
> + GEM_BUG_ON(dummy->node.size > ggtt->uc_fw.size);
>
> /* uc_fw->obj cache domains were not controlled across suspend */
> - drm_clflush_sg(dummy.pages);
> + drm_clflush_sg(dummy->pages);
>
> - ggtt->vm.insert_entries(>vm, , I915_CACHE_NONE, 0);
> + ggtt->vm.insert_entries(>vm, dummy, I915_CACHE_NONE, 0);
> }
>
> static void uc_fw_unbind_ggtt(struct intel_uc_fw *uc_fw)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
> index 99bb1fe1af66..693cc0ebcd63 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h
> @@ -10,6 +10,7 @@
> #include "intel_uc_fw_abi.h"
> #include "intel_device_info.h"
> #include "i915_gem.h"
> +#include "i915_vma.h"
>
> struct drm_printer;
> struct drm_i915_private;
> @@ -75,6 +76,7 @@ struct intel_uc_fw {
> bool user_overridden;
> size_t size;
> struct drm_i915_gem_object *obj;
> + struct i915_vma dummy;
>
> /*
> * The firmware build process will generate a version header file
> with major and
> --
> 2.32.0
>
Re: [Intel-gfx] [PULL] drm-misc-fixes
On Thu, 9 Sept 2021 at 19:30, Daniel Vetter wrote: > > On Thu, Sep 9, 2021 at 5:35 AM Dave Airlie wrote: > > > > On Thu, 9 Sept 2021 at 03:44, Thomas Zimmermann wrote: > > > > > > Hi Dave and Daniel, > > > > > > here's this week's PR for drm-misc-fixes. One patch is a potential > > > deadlock > > > in TTM, the other enables an additional plane in kmb. I'm slightly unhappy > > > that the latter one ended up in -fixes as it's not a bugfix AFAICT. > > > > To avoid messy merge window, I'm not pulling this until after rc1 > > unless there is some major reason? > > Christian misplaced a ttm fix, so we really want this. Maybe > cherry-pick to drm-next and then drm-misc-fixes gets rebased instead. > > And yeah I dunno what do with our conflicts around merge window, maybe > we're letting trees diverge a bit too much. I've cherry-pick the ttm fix, the kmb fix should be somewhere else, I'm not going to pull it in from there. Maybe once rc1 gets out it can be rebased. Please nobody push to drm-misc-fixes until post rc1 + a day or two. Dave.
[Intel-gfx] [PATCH 25/25] drm/i915: constify display wm vtable
From: Dave Airlie
Use a nop table for the cases where CxSR doesn't init properly.
v2: use a nop table (Jani)
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 34 -
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 80 ++--
3 files changed, 75 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 01d15a4c7e25..a8f9e7a3bc7a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -162,16 +162,16 @@ static void intel_modeset_setup_hw_state(struct
drm_device *dev,
*/
static void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
- if (dev_priv->wm_disp.update_wm)
- dev_priv->wm_disp.update_wm(dev_priv);
+ if (dev_priv->wm_disp->update_wm)
+ dev_priv->wm_disp->update_wm(dev_priv);
}
static int intel_compute_pipe_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.compute_pipe_wm)
- return dev_priv->wm_disp.compute_pipe_wm(state, crtc);
+ if (dev_priv->wm_disp->compute_pipe_wm)
+ return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
return 0;
}
@@ -179,20 +179,20 @@ static int intel_compute_intermediate_wm(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (!dev_priv->wm_disp.compute_intermediate_wm)
+ if (!dev_priv->wm_disp->compute_intermediate_wm)
return 0;
if (drm_WARN_ON(_priv->drm,
- !dev_priv->wm_disp.compute_pipe_wm))
+ !dev_priv->wm_disp->compute_pipe_wm))
return 0;
- return dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
+ return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
}
static bool intel_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.initial_watermarks) {
- dev_priv->wm_disp.initial_watermarks(state, crtc);
+ if (dev_priv->wm_disp->initial_watermarks) {
+ dev_priv->wm_disp->initial_watermarks(state, crtc);
return true;
}
return false;
@@ -202,23 +202,23 @@ static void intel_atomic_update_watermarks(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.atomic_update_watermarks)
- dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
+ if (dev_priv->wm_disp->atomic_update_watermarks)
+ dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
}
static void intel_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.optimize_watermarks)
- dev_priv->wm_disp.optimize_watermarks(state, crtc);
+ if (dev_priv->wm_disp->optimize_watermarks)
+ dev_priv->wm_disp->optimize_watermarks(state, crtc);
}
static void intel_compute_global_watermarks(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.compute_global_watermarks)
- dev_priv->wm_disp.compute_global_watermarks(state);
+ if (dev_priv->wm_disp->compute_global_watermarks)
+ dev_priv->wm_disp->compute_global_watermarks(state);
}
/* returns HPLL frequency in kHz */
@@ -3735,7 +3735,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state
*state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
- if (!dev_priv->wm_disp.initial_watermarks)
+ if (!dev_priv->wm_disp->initial_watermarks)
intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
@@ -11409,7 +11409,7 @@ static void sanitize_watermarks(struct drm_i915_private
*dev_priv)
int i;
/* Only supported on platforms that use atomic watermark design */
- if (!dev_priv->wm_disp.optimize_watermarks)
+ if (!dev_priv->wm_disp->optimize_
[Intel-gfx] [PATCH 24/25] drm/i915: constify clock gating init vtable.
From: Dave Airlie
I used a macro to avoid making any really silly mistakes here.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 78 +++--
2 files changed, 55 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5bbdd3b06e6d..fc7466bbc445 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -975,7 +975,7 @@ struct drm_i915_private {
struct workqueue_struct *flip_wq;
/* pm private clock gating functions */
- struct drm_i915_clock_gating_funcs clock_gating_funcs;
+ const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
/* pm display functions */
struct drm_i915_wm_disp_funcs wm_disp;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 826216a115fd..0a5c1e3c798b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating(struct drm_i915_private *dev_priv)
{
- dev_priv->clock_gating_funcs.init_clock_gating(dev_priv);
+ dev_priv->clock_gating_funcs->init_clock_gating(dev_priv);
}
void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7886,6 +7886,36 @@ static void nop_init_clock_gating(struct
drm_i915_private *dev_priv)
"No clock gating settings or workarounds applied.\n");
}
+#define CG_FUNCS(platform) \
+static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs
= { \
+ .init_clock_gating = platform##_init_clock_gating, \
+}
+
+CG_FUNCS(adlp);
+CG_FUNCS(dg1);
+CG_FUNCS(gen12lp);
+CG_FUNCS(icl);
+CG_FUNCS(cfl);
+CG_FUNCS(skl);
+CG_FUNCS(kbl);
+CG_FUNCS(bxt);
+CG_FUNCS(glk);
+CG_FUNCS(bdw);
+CG_FUNCS(chv);
+CG_FUNCS(hsw);
+CG_FUNCS(ivb);
+CG_FUNCS(vlv);
+CG_FUNCS(gen6);
+CG_FUNCS(ilk);
+CG_FUNCS(g4x);
+CG_FUNCS(i965gm);
+CG_FUNCS(i965g);
+CG_FUNCS(gen3);
+CG_FUNCS(i85x);
+CG_FUNCS(i830);
+CG_FUNCS(nop);
+#undef CG_FUNCS
+
/**
* intel_init_clock_gating_hooks - setup the clock gating hooks
* @dev_priv: device private
@@ -7898,52 +7928,52 @@ static void nop_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_ALDERLAKE_P(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
adlp_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_DG1(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
dg1_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 12)
- dev_priv->clock_gating_funcs.init_clock_gating =
gen12lp_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 11)
- dev_priv->clock_gating_funcs.init_clock_gating =
icl_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
cfl_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_SKYLAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
skl_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_KABYLAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
kbl_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_BROXTON(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
bxt_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_GEMINILAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
glk_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_BROADWELL(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
bdw_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
chv_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_HASWELL(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
hsw_init_clock_gating;
+ dev_priv->clock_gating_fun
[Intel-gfx] [PATCH 23/25] drm/i915: constify display function vtable
From: Dave Airlie
Make nice clear tables instead of having things in two places.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 81
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 52 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 1998e7132c30..01d15a4c7e25 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3789,7 +3789,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc
*crtc,
drm_WARN_ON(_priv->drm, IS_ERR(temp_crtc_state) || ret);
- dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
+ dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
drm_atomic_state_put(state);
@@ -5994,7 +5994,7 @@ static bool intel_crtc_get_pipe_config(struct
intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- if (!i915->display.get_pipe_config(crtc, crtc_state))
+ if (!i915->display->get_pipe_config(crtc, crtc_state))
return false;
crtc_state->hw.active = true;
@@ -9802,7 +9802,7 @@ static void intel_enable_crtc(struct intel_atomic_state
*state,
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display.crtc_enable(state, crtc);
+ dev_priv->display->crtc_enable(state, crtc);
if (new_crtc_state->bigjoiner_slave)
return;
@@ -9890,7 +9890,7 @@ static void intel_old_crtc_state_disables(struct
intel_atomic_state *state,
*/
intel_crtc_disable_pipe_crc(crtc);
- dev_priv->display.crtc_disable(state, crtc);
+ dev_priv->display->crtc_disable(state, crtc);
crtc->active = false;
intel_fbc_disable(crtc);
intel_disable_shared_dpll(old_crtc_state);
@@ -10269,7 +10269,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
}
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
- dev_priv->display.commit_modeset_enables(state);
+ dev_priv->display->commit_modeset_enables(state);
if (state->modeset) {
intel_encoders_update_complete(state);
@@ -11272,6 +11272,46 @@ static const struct drm_mode_config_funcs
intel_mode_funcs = {
.atomic_state_free = intel_atomic_state_free,
};
+static const struct drm_i915_display_funcs skl_display_funcs = {
+ .get_pipe_config = hsw_get_pipe_config,
+ .crtc_enable = hsw_crtc_enable,
+ .crtc_disable = hsw_crtc_disable,
+ .commit_modeset_enables = skl_commit_modeset_enables,
+ .get_initial_plane_config = skl_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs ddi_display_funcs = {
+ .get_pipe_config = hsw_get_pipe_config,
+ .crtc_enable = hsw_crtc_enable,
+ .crtc_disable = hsw_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs pch_split_display_funcs = {
+ .get_pipe_config = ilk_get_pipe_config,
+ .crtc_enable = ilk_crtc_enable,
+ .crtc_disable = ilk_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs vlv_display_funcs = {
+ .get_pipe_config = i9xx_get_pipe_config,
+ .crtc_enable = valleyview_crtc_enable,
+ .crtc_disable = i9xx_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs i9xx_display_funcs = {
+ .get_pipe_config = i9xx_get_pipe_config,
+ .crtc_enable = i9xx_crtc_enable,
+ .crtc_disable = i9xx_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
/**
* intel_init_display_hooks - initialize the display modesetting hooks
* @dev_priv: device private
@@ -11287,38 +11327,19 @@ void intel_init_display_hooks(struct drm_i915_private
*dev_priv)
intel_dpll_init_clock_hook(dev_priv);
if (DISPLAY_VER(dev_priv) >= 9) {
- dev_priv->display.get_pipe_config = hsw_get_pipe_config;
- dev_priv->display.crtc_enable = hsw_crtc_enable;
- dev_priv->display.crtc_disable = hsw_crtc_disable;
+ dev_priv->display = _display_funcs;
} else if (HAS_DDI(dev_priv)) {
- dev_priv->display.get_pipe_config =
[Intel-gfx] [PATCH 21/25] drm/i915: constify the cdclk vtable
From: Dave Airlie
This is a bit of a twisty one since each platform is slightly
different, so might take some more review care.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 300 ++---
drivers/gpu/drm/i915/i915_drv.h| 2 +-
2 files changed, 206 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 27a4a226aa49..f501c748458e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -62,32 +62,32 @@
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
- dev_priv->cdclk_funcs.get_cdclk(dev_priv, cdclk_config);
+ dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config);
}
int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- return dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
+ return dev_priv->cdclk_funcs->bw_calc_min_cdclk(state);
}
static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
+ dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe);
}
static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state
*cdclk_config)
{
- return dev_priv->cdclk_funcs.modeset_calc_cdclk(cdclk_config);
+ return dev_priv->cdclk_funcs->modeset_calc_cdclk(cdclk_config);
}
static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
int cdclk)
{
- return dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
+ return dev_priv->cdclk_funcs->calc_voltage_level(cdclk);
}
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
if (!intel_cdclk_changed(_priv->cdclk.hw, cdclk_config))
return;
- if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
+ if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
return;
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -2886,6 +2886,157 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static struct intel_cdclk_funcs tgl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs ehl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = ehl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs icl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = icl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs bxt_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = bxt_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs skl_cdclk_funcs = {
+ .get_cdclk = skl_get_cdclk,
+ .set_cdclk = skl_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = skl_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs bdw_cdclk_funcs = {
+ .get_cdclk = bdw_get_cdclk,
+ .set_cdclk = bdw_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bdw_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs chv_cdclk_funcs = {
+ .get_cdclk = vlv_get_cdclk,
+ .set_cdclk = chv_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs vlv_cdclk_funcs = {
+ .get_cdclk = vlv_get_cdclk,
+ .set_cdclk = vlv_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs hsw_cdclk_funcs = {
+ .get_cdclk = hsw_get_cdclk,
+
[Intel-gfx] [PATCH 22/25] drm/i915: drop unused function ptr and comments.
From: Dave Airlie
There was some excess comments and an unused vtbl ptr.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_drv.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b2c63ed5b8fe..2e8e4db627e3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -409,13 +409,6 @@ struct drm_i915_display_funcs {
void (*crtc_disable)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*commit_modeset_enables)(struct intel_atomic_state *state);
- void (*commit_modeset_disables)(struct intel_atomic_state *state);
-
- /* clock updates for mode set */
- /* cursor updates */
- /* render clock increase/decrease */
- /* display clock increase/decrease */
- /* pll clock increase/decrease */
};
--
2.31.1
[Intel-gfx] [PATCH 20/25] drm/i915: constify the dpll clock vtable
From: Dave Airlie
Most the dpll vtable into read-only memory.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +--
drivers/gpu/drm/i915/display/intel_dpll.c| 48
drivers/gpu/drm/i915/i915_drv.h | 2 +-
3 files changed, 44 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index db7b0d54b6ce..1998e7132c30 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6821,10 +6821,10 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
crtc_state->update_wm_post = true;
if (mode_changed && crtc_state->hw.enable &&
- dev_priv->dpll_funcs.crtc_compute_clock &&
+ dev_priv->dpll_funcs &&
!crtc_state->bigjoiner_slave &&
!drm_WARN_ON(_priv->drm, crtc_state->shared_dpll)) {
- ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
+ ret = dev_priv->dpll_funcs->crtc_compute_clock(crtc_state);
if (ret)
return ret;
}
@@ -8851,7 +8851,7 @@ static void intel_modeset_clear_plls(struct
intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
- if (!dev_priv->dpll_funcs.crtc_compute_clock)
+ if (!dev_priv->dpll_funcs)
return;
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 9326c7cbb05c..231b337df166 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1363,25 +1363,57 @@ static int i8xx_crtc_compute_clock(struct
intel_crtc_state *crtc_state)
return 0;
}
+static const struct intel_dpll_funcs hsw_dpll_funcs = {
+ .crtc_compute_clock = hsw_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs ilk_dpll_funcs = {
+ .crtc_compute_clock = ilk_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs chv_dpll_funcs = {
+ .crtc_compute_clock = chv_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs vlv_dpll_funcs = {
+ .crtc_compute_clock = vlv_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs g4x_dpll_funcs = {
+ .crtc_compute_clock = g4x_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs pnv_dpll_funcs = {
+ .crtc_compute_clock = pnv_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs i9xx_dpll_funcs = {
+ .crtc_compute_clock = i9xx_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs i8xx_dpll_funcs = {
+ .crtc_compute_clock = i8xx_crtc_compute_clock,
+};
+
void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
hsw_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (HAS_PCH_SPLIT(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
ilk_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
chv_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
vlv_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_G4X(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
g4x_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
pnv_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (DISPLAY_VER(dev_priv) != 2)
- dev_priv->dpll_funcs.crtc_compute_clock =
i9xx_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else
- dev_priv->dpll_funcs.crtc_compute_clock =
i8xx_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
}
static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 95f7a7a19a58..5ed624b9c3cc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -994,7 +994,7 @@ struct drm_i915_private {
const struct intel_fdi_funcs *fdi_funcs;
/* display pll funcs */
- struct intel_dpll_funcs dpll_funcs;
+ const struct intel_dpll_funcs *dpll_funcs;
/* Display functions */
struct drm_i915_display_funcs display;
--
2.31.1
[Intel-gfx] [PATCH 19/25] drm/i915: constify the audio function vtable
From: Dave Airlie
Move the functions into read-only tables.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_audio.c | 43 ++
drivers/gpu/drm/i915/i915_drv.h| 2 +-
2 files changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index f539826c0424..0a6ad74d9173 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -848,10 +848,10 @@ void intel_audio_codec_enable(struct intel_encoder
*encoder,
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
- if (dev_priv->audio_funcs.audio_codec_enable)
- dev_priv->audio_funcs.audio_codec_enable(encoder,
-crtc_state,
-conn_state);
+ if (dev_priv->audio_funcs)
+ dev_priv->audio_funcs->audio_codec_enable(encoder,
+ crtc_state,
+ conn_state);
mutex_lock(_priv->av_mutex);
encoder->audio_connector = connector;
@@ -893,10 +893,10 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
- if (dev_priv->audio_funcs.audio_codec_disable)
- dev_priv->audio_funcs.audio_codec_disable(encoder,
- old_crtc_state,
- old_conn_state);
+ if (dev_priv->audio_funcs)
+ dev_priv->audio_funcs->audio_codec_disable(encoder,
+ old_crtc_state,
+ old_conn_state);
mutex_lock(_priv->av_mutex);
encoder->audio_connector = NULL;
@@ -915,6 +915,21 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
}
+static const struct intel_audio_funcs g4x_audio_funcs = {
+ .audio_codec_enable = g4x_audio_codec_enable,
+ .audio_codec_disable = g4x_audio_codec_disable,
+};
+
+static const struct intel_audio_funcs ilk_audio_funcs = {
+ .audio_codec_enable = ilk_audio_codec_enable,
+ .audio_codec_disable = ilk_audio_codec_disable,
+};
+
+static const struct intel_audio_funcs hsw_audio_funcs = {
+ .audio_codec_enable = hsw_audio_codec_enable,
+ .audio_codec_disable = hsw_audio_codec_disable,
+};
+
/**
* intel_init_audio_hooks - Set up chip specific audio hooks
* @dev_priv: device private
@@ -922,17 +937,13 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
{
if (IS_G4X(dev_priv)) {
- dev_priv->audio_funcs.audio_codec_enable =
g4x_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable =
g4x_audio_codec_disable;
+ dev_priv->audio_funcs = _audio_funcs;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- dev_priv->audio_funcs.audio_codec_enable =
ilk_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable =
ilk_audio_codec_disable;
+ dev_priv->audio_funcs = _audio_funcs;
} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->audio_funcs.audio_codec_enable =
hsw_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable =
hsw_audio_codec_disable;
+ dev_priv->audio_funcs = _audio_funcs;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->audio_funcs.audio_codec_enable =
ilk_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable =
ilk_audio_codec_disable;
+ dev_priv->audio_funcs = _audio_funcs;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 28cd816549b8..95f7a7a19a58 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1003,7 +1003,7 @@ struct drm_i915_private {
const struct intel_color_funcs *color_funcs;
/* Display internal audio functions */
- struct intel_audio_funcs audio_funcs;
+ const struct intel_audio_funcs *audio_funcs;
/* Display CDCLK functions */
struct intel_cdclk_funcs cdclk_funcs;
--
2.31.1
[Intel-gfx] [PATCH 18/25] drm/i915: constify color function vtable.
From: Dave Airlie
This clarifies quite well what functions get used on what platforms
instead of having to decipher the old tree.
v2: fixed IVB mistake (Jani)
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_color.c | 138 ++---
drivers/gpu/drm/i915/i915_drv.h| 2 +-
2 files changed, 93 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index ed79075158dd..f5923f1c38bd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct
intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->color_funcs.load_luts(crtc_state);
+ dev_priv->color_funcs->load_luts(crtc_state);
}
void intel_color_commit(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->color_funcs.color_commit(crtc_state);
+ dev_priv->color_funcs->color_commit(crtc_state);
}
static bool intel_can_preload_luts(const struct intel_crtc_state
*new_crtc_state)
@@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- return dev_priv->color_funcs.color_check(crtc_state);
+ return dev_priv->color_funcs->color_check(crtc_state);
}
void intel_color_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (dev_priv->color_funcs.read_luts)
- dev_priv->color_funcs.read_luts(crtc_state);
+ if (dev_priv->color_funcs->read_luts)
+ dev_priv->color_funcs->read_luts(crtc_state);
}
static bool need_plane_update(struct intel_plane *plane,
@@ -2092,6 +2092,76 @@ static void icl_read_luts(struct intel_crtc_state
*crtc_state)
}
}
+static const struct intel_color_funcs chv_color_funcs = {
+ .color_check = chv_color_check,
+ .color_commit = i9xx_color_commit,
+ .load_luts = chv_load_luts,
+ .read_luts = chv_read_luts,
+};
+
+static const struct intel_color_funcs i965_color_funcs = {
+ .color_check = i9xx_color_check,
+ .color_commit = i9xx_color_commit,
+ .load_luts = i965_load_luts,
+ .read_luts = i965_read_luts,
+};
+
+static const struct intel_color_funcs i9xx_color_funcs = {
+ .color_check = i9xx_color_check,
+ .color_commit = i9xx_color_commit,
+ .load_luts = i9xx_load_luts,
+ .read_luts = i9xx_read_luts,
+};
+
+static const struct intel_color_funcs icl_color_funcs = {
+ .color_check = icl_color_check,
+ .color_commit = skl_color_commit,
+ .load_luts = icl_load_luts,
+ .read_luts = icl_read_luts,
+};
+
+static const struct intel_color_funcs glk_color_funcs = {
+ .color_check = glk_color_check,
+ .color_commit = skl_color_commit,
+ .load_luts = glk_load_luts,
+ .read_luts = glk_read_luts,
+};
+
+static const struct intel_color_funcs skl_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = skl_color_commit,
+ .load_luts = bdw_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs bdw_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = hsw_color_commit,
+ .load_luts = bdw_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs hsw_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = hsw_color_commit,
+ .load_luts = ivb_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs ivb_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = ilk_color_commit,
+ .load_luts = ivb_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs ilk_color_funcs = {
+ .color_check = ilk_color_check,
+ .color_commit = ilk_color_commit,
+ .load_luts = ilk_load_luts,
+ .read_luts = ilk_read_luts,
+};
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2101,52 +2171,28 @@ void intel_color_init(struct intel_crtc *crtc)
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->color_funcs.color_check = chv_color_check;
- dev_priv->color_funcs.color_commit = i9xx_color_commit;
- dev_priv->color_funcs.load_luts = chv_load_luts;
- dev_priv->color_funcs.read_luts = chv_read_luts;
+ dev_pri
[Intel-gfx] [PATCH 16/25] drm/i915: constify fdi link training vtable
From: Dave Airlie
Put the vtable into ro memory.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fdi.c | 20
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index 94bb7e039fe7..148fb50035ff 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -15,7 +15,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
+ dev_priv->fdi_funcs->fdi_link_train(crtc, crtc_state);
}
/* units of 100MHz */
@@ -1013,15 +1013,27 @@ void lpt_fdi_program_mphy(struct drm_i915_private
*dev_priv)
intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
}
+static const struct intel_fdi_funcs ilk_funcs = {
+ .fdi_link_train = ilk_fdi_link_train,
+};
+
+static const struct intel_fdi_funcs gen6_funcs = {
+ .fdi_link_train = gen6_fdi_link_train,
+};
+
+static const struct intel_fdi_funcs ivb_funcs = {
+ .fdi_link_train = ivb_manual_fdi_link_train,
+};
+
void
intel_fdi_init_hook(struct drm_i915_private *dev_priv)
{
if (IS_IRONLAKE(dev_priv)) {
- dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
+ dev_priv->fdi_funcs = _funcs;
} else if (IS_SANDYBRIDGE(dev_priv)) {
- dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
+ dev_priv->fdi_funcs = _funcs;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
- dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
+ dev_priv->fdi_funcs = _funcs;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 575c46df5336..bb44ef4f6356 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -991,7 +991,7 @@ struct drm_i915_private {
struct intel_hotplug_funcs hotplug_funcs;
/* fdi display functions */
- struct intel_fdi_funcs fdi_funcs;
+ const struct intel_fdi_funcs *fdi_funcs;
/* display pll funcs */
struct intel_dpll_funcs dpll_funcs;
--
2.31.1
[Intel-gfx] [PATCH 17/25] drm/i915: constify hotplug function vtable.
From: Dave Airlie
Use a macro to avoid mistakes, this type of macro is only used
in a couple of places.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 4 +--
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 28 +++-
3 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 05f76aba4f8a..3c1cec953b42 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct
drm_i915_private *dev_priv)
static void intel_hpd_irq_setup(struct drm_i915_private *i915)
{
- if (i915->display_irqs_enabled && i915->hotplug_funcs.hpd_irq_setup)
- i915->hotplug_funcs.hpd_irq_setup(i915);
+ if (i915->display_irqs_enabled && i915->hotplug_funcs->hpd_irq_setup)
+ i915->hotplug_funcs->hpd_irq_setup(i915);
}
static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bb44ef4f6356..af1960856f19 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -988,7 +988,7 @@ struct drm_i915_private {
struct drm_i915_wm_disp_funcs wm_disp;
/* irq display functions */
- struct intel_hotplug_funcs hotplug_funcs;
+ const struct intel_hotplug_funcs *hotplug_funcs;
/* fdi display functions */
const struct intel_fdi_funcs *fdi_funcs;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c35065f8f429..77680bca46ee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4345,6 +4345,20 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
return ret;
}
+#define HPD_FUNCS(platform) \
+static const struct intel_hotplug_funcs platform##_hpd_funcs = { \
+ .hpd_irq_setup = platform##_hpd_irq_setup, \
+}
+
+HPD_FUNCS(i915);
+HPD_FUNCS(dg1);
+HPD_FUNCS(gen11);
+HPD_FUNCS(bxt);
+HPD_FUNCS(icp);
+HPD_FUNCS(spt);
+HPD_FUNCS(ilk);
+#undef HPD_FUNCS
+
/**
* intel_irq_init - initializes irq support
* @dev_priv: i915 device instance
@@ -4395,20 +4409,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
- dev_priv->hotplug_funcs.hpd_irq_setup =
i915_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
} else {
if (HAS_PCH_DG1(dev_priv))
- dev_priv->hotplug_funcs.hpd_irq_setup =
dg1_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->hotplug_funcs.hpd_irq_setup =
gen11_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->hotplug_funcs.hpd_irq_setup =
bxt_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- dev_priv->hotplug_funcs.hpd_irq_setup =
icp_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- dev_priv->hotplug_funcs.hpd_irq_setup =
spt_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else
- dev_priv->hotplug_funcs.hpd_irq_setup =
ilk_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
}
}
--
2.31.1
[Intel-gfx] [PATCH 15/25] drm/i915: split the dpll clock compute out from display vtable.
From: Dave Airlie
this single function might be possible to merge later, but
for now it's simple to just split it out.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dpll.c| 16
drivers/gpu/drm/i915/i915_drv.h | 8 +++-
3 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 706aa9d385bd..db7b0d54b6ce 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6821,10 +6821,10 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
crtc_state->update_wm_post = true;
if (mode_changed && crtc_state->hw.enable &&
- dev_priv->display.crtc_compute_clock &&
+ dev_priv->dpll_funcs.crtc_compute_clock &&
!crtc_state->bigjoiner_slave &&
!drm_WARN_ON(_priv->drm, crtc_state->shared_dpll)) {
- ret = dev_priv->display.crtc_compute_clock(crtc_state);
+ ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
if (ret)
return ret;
}
@@ -8851,7 +8851,7 @@ static void intel_modeset_clear_plls(struct
intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
- if (!dev_priv->display.crtc_compute_clock)
+ if (!dev_priv->dpll_funcs.crtc_compute_clock)
return;
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 210f91f4a576..9326c7cbb05c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1367,21 +1367,21 @@ void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
- dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
hsw_crtc_compute_clock;
else if (HAS_PCH_SPLIT(dev_priv))
- dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
ilk_crtc_compute_clock;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
chv_crtc_compute_clock;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
vlv_crtc_compute_clock;
else if (IS_G4X(dev_priv))
- dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
g4x_crtc_compute_clock;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
pnv_crtc_compute_clock;
else if (DISPLAY_VER(dev_priv) != 2)
- dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
i9xx_crtc_compute_clock;
else
- dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
i8xx_crtc_compute_clock;
}
static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 680301bce3ab..575c46df5336 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -393,6 +393,10 @@ struct intel_fdi_funcs {
const struct intel_crtc_state *crtc_state);
};
+struct intel_dpll_funcs {
+ int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
+};
+
struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -400,7 +404,6 @@ struct drm_i915_display_funcs {
struct intel_crtc_state *);
void (*get_initial_plane_config)(struct intel_crtc *,
struct intel_initial_plane_config *);
- int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
void (*crtc_enable)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*crtc_disable)(struct intel_atomic_state *state,
@@ -990,6 +993,9 @@ struct drm_i915_private {
/* fdi display functions */
struct i
[Intel-gfx] [PATCH 14/25] drm/i915: split fdi link training from display vtable.
From: Dave Airlie
It may make sense to merge this with display again later,
however the fdi use of the vtable is limited to only a
few generations.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fdi.c | 8
drivers/gpu/drm/i915/i915_drv.h | 11 ---
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index 339243399a65..94bb7e039fe7 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -15,7 +15,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- dev_priv->display.fdi_link_train(crtc, crtc_state);
+ dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
}
/* units of 100MHz */
@@ -1017,11 +1017,11 @@ void
intel_fdi_init_hook(struct drm_i915_private *dev_priv)
{
if (IS_IRONLAKE(dev_priv)) {
- dev_priv->display.fdi_link_train = ilk_fdi_link_train;
+ dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
} else if (IS_SANDYBRIDGE(dev_priv)) {
- dev_priv->display.fdi_link_train = gen6_fdi_link_train;
+ dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
- dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
+ dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index caf854d251a6..680301bce3ab 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -388,6 +388,11 @@ struct intel_hotplug_funcs {
void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
};
+struct intel_fdi_funcs {
+ void (*fdi_link_train)(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state);
+};
+
struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -403,9 +408,6 @@ struct drm_i915_display_funcs {
void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*commit_modeset_disables)(struct intel_atomic_state *state);
- void (*fdi_link_train)(struct intel_crtc *crtc,
- const struct intel_crtc_state *crtc_state);
-
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
@@ -985,6 +987,9 @@ struct drm_i915_private {
/* irq display functions */
struct intel_hotplug_funcs hotplug_funcs;
+ /* fdi display functions */
+ struct intel_fdi_funcs fdi_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
--
2.31.1
[Intel-gfx] [PATCH 13/25] drm/i915: split irq hotplug function from display vtable
From: Dave Airlie
This provide a service from irq to display, so make it separate
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 9 -
drivers/gpu/drm/i915/i915_irq.c | 14 +++---
3 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 47c85ac97c87..05f76aba4f8a 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct
drm_i915_private *dev_priv)
static void intel_hpd_irq_setup(struct drm_i915_private *i915)
{
- if (i915->display_irqs_enabled && i915->display.hpd_irq_setup)
- i915->display.hpd_irq_setup(i915);
+ if (i915->display_irqs_enabled && i915->hotplug_funcs.hpd_irq_setup)
+ i915->hotplug_funcs.hpd_irq_setup(i915);
}
static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 11298f583cc0..caf854d251a6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -384,6 +384,10 @@ struct intel_cdclk_funcs {
u8 (*calc_voltage_level)(int cdclk);
};
+struct intel_hotplug_funcs {
+ void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
+};
+
struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -401,7 +405,7 @@ struct drm_i915_display_funcs {
void (*fdi_link_train)(struct intel_crtc *crtc,
const struct intel_crtc_state *crtc_state);
- void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
+
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
@@ -978,6 +982,9 @@ struct drm_i915_private {
/* pm display functions */
struct drm_i915_wm_disp_funcs wm_disp;
+ /* irq display functions */
+ struct intel_hotplug_funcs hotplug_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0a1681384c84..c35065f8f429 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4395,20 +4395,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
i915_hpd_irq_setup;
} else {
if (HAS_PCH_DG1(dev_priv))
- dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
dg1_hpd_irq_setup;
else if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
gen11_hpd_irq_setup;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
bxt_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
icp_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
spt_hpd_irq_setup;
else
- dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
ilk_hpd_irq_setup;
}
}
--
2.31.1
[Intel-gfx] [PATCH 12/25] drm/i915: split cdclk functions from display vtable.
From: Dave Airlie
This moves all the cdclk related functions into their own vtable.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 142 ++---
drivers/gpu/drm/i915/i915_drv.h| 8 +-
2 files changed, 78 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0e09f259914f..27a4a226aa49 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -62,32 +62,32 @@
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
- dev_priv->display.get_cdclk(dev_priv, cdclk_config);
+ dev_priv->cdclk_funcs.get_cdclk(dev_priv, cdclk_config);
}
int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- return dev_priv->display.bw_calc_min_cdclk(state);
+ return dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
}
static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+ dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
}
static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state
*cdclk_config)
{
- return dev_priv->display.modeset_calc_cdclk(cdclk_config);
+ return dev_priv->cdclk_funcs.modeset_calc_cdclk(cdclk_config);
}
static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
int cdclk)
{
- return dev_priv->display.calc_voltage_level(cdclk);
+ return dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
}
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
if (!intel_cdclk_changed(_priv->cdclk.hw, cdclk_config))
return;
- if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->display.set_cdclk))
+ if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
return;
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -2893,119 +2893,119 @@ u32 intel_read_rawclk(struct drm_i915_private
*dev_priv)
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
if (IS_DG2(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk =
bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level =
tgl_calc_voltage_level;
dev_priv->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk =
bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level =
tgl_calc_voltage_level;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
else
dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk
[Intel-gfx] [PATCH 11/25] drm/i915: split audio functions from display vtable
From: Dave Airlie
These are only used internally in the audio code
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_audio.c | 24 +++---
drivers/gpu/drm/i915/i915_drv.h| 19 +++--
2 files changed, 25 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 532237588511..f539826c0424 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -848,8 +848,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
- if (dev_priv->display.audio_codec_enable)
- dev_priv->display.audio_codec_enable(encoder,
+ if (dev_priv->audio_funcs.audio_codec_enable)
+ dev_priv->audio_funcs.audio_codec_enable(encoder,
crtc_state,
conn_state);
@@ -893,8 +893,8 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
- if (dev_priv->display.audio_codec_disable)
- dev_priv->display.audio_codec_disable(encoder,
+ if (dev_priv->audio_funcs.audio_codec_disable)
+ dev_priv->audio_funcs.audio_codec_disable(encoder,
old_crtc_state,
old_conn_state);
@@ -922,17 +922,17 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
{
if (IS_G4X(dev_priv)) {
- dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
- dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable =
g4x_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable =
g4x_audio_codec_disable;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
- dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable =
ilk_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable =
ilk_audio_codec_disable;
} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
- dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable =
hsw_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable =
hsw_audio_codec_disable;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
- dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable =
ilk_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable =
ilk_audio_codec_disable;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8930bf2db226..1ba94dee683e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -364,6 +364,15 @@ struct intel_color_funcs {
void (*read_luts)(struct intel_crtc_state *crtc_state);
};
+struct intel_audio_funcs {
+ void (*audio_codec_enable)(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state
*conn_state);
+ void (*audio_codec_disable)(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*old_crtc_state,
+ const struct drm_connector_state
*old_conn_state);
+};
+
struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config);
@@ -386,12 +395,7 @@ struct drm_i915_display_funcs {
struct intel_crtc *crtc);
void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*commit_modeset_disables)(struct intel_atomic_state *state);
- void (*audio_codec_enable)(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state
*conn_state);
- void (*audio_codec_disable)(struct intel_encoder *encoder,
- const struct
[Intel-gfx] [PATCH 10/25] drm/i915: split color functions from display vtable
From: Dave Airlie
These are only used internally in the color module
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_color.c | 64 +++---
drivers/gpu/drm/i915/i915_drv.h| 39 +++--
2 files changed, 54 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index afcb4bf3826c..ed79075158dd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct
intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->display.load_luts(crtc_state);
+ dev_priv->color_funcs.load_luts(crtc_state);
}
void intel_color_commit(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->display.color_commit(crtc_state);
+ dev_priv->color_funcs.color_commit(crtc_state);
}
static bool intel_can_preload_luts(const struct intel_crtc_state
*new_crtc_state)
@@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- return dev_priv->display.color_check(crtc_state);
+ return dev_priv->color_funcs.color_check(crtc_state);
}
void intel_color_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (dev_priv->display.read_luts)
- dev_priv->display.read_luts(crtc_state);
+ if (dev_priv->color_funcs.read_luts)
+ dev_priv->color_funcs.read_luts(crtc_state);
}
static bool need_plane_update(struct intel_plane *plane,
@@ -2101,51 +2101,51 @@ void intel_color_init(struct intel_crtc *crtc)
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.color_check = chv_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = chv_load_luts;
- dev_priv->display.read_luts = chv_read_luts;
+ dev_priv->color_funcs.color_check = chv_color_check;
+ dev_priv->color_funcs.color_commit = i9xx_color_commit;
+ dev_priv->color_funcs.load_luts = chv_load_luts;
+ dev_priv->color_funcs.read_luts = chv_read_luts;
} else if (DISPLAY_VER(dev_priv) >= 4) {
- dev_priv->display.color_check = i9xx_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = i965_load_luts;
- dev_priv->display.read_luts = i965_read_luts;
+ dev_priv->color_funcs.color_check = i9xx_color_check;
+ dev_priv->color_funcs.color_commit = i9xx_color_commit;
+ dev_priv->color_funcs.load_luts = i965_load_luts;
+ dev_priv->color_funcs.read_luts = i965_read_luts;
} else {
- dev_priv->display.color_check = i9xx_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = i9xx_load_luts;
- dev_priv->display.read_luts = i9xx_read_luts;
+ dev_priv->color_funcs.color_check = i9xx_color_check;
+ dev_priv->color_funcs.color_commit = i9xx_color_commit;
+ dev_priv->color_funcs.load_luts = i9xx_load_luts;
+ dev_priv->color_funcs.read_luts = i9xx_read_luts;
}
} else {
if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->display.color_check = icl_color_check;
+ dev_priv->color_funcs.color_check = icl_color_check;
else if (DISPLAY_VER(dev_priv) >= 10)
- dev_priv->display.color_check = glk_color_check;
+ dev_priv->color_funcs.color_check = glk_color_check;
else if (DISPLAY_VER(dev_priv) >= 7)
- dev_priv->display.color_check = ivb_color_check;
+ dev_priv->color_funcs.color_check = ivb_color_check;
else
- dev_priv->display.color_check = ilk_color_check;
+ dev_priv->color_funcs.color_check = ilk_color_check;
if (DISPLAY_VER(dev_priv) >= 9)
- dev_priv-&g
[Intel-gfx] [PATCH 09/25] drm/i915: split watermark vfuncs from display vtable.
From: Dave Airlie
These are the watermark api between display and pm.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 35 -
drivers/gpu/drm/i915/i915_drv.h | 24
drivers/gpu/drm/i915/intel_pm.c | 40 ++--
3 files changed, 54 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index aa174192c279..706aa9d385bd 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -162,16 +162,16 @@ static void intel_modeset_setup_hw_state(struct
drm_device *dev,
*/
static void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
- if (dev_priv->display.update_wm)
- dev_priv->display.update_wm(dev_priv);
+ if (dev_priv->wm_disp.update_wm)
+ dev_priv->wm_disp.update_wm(dev_priv);
}
static int intel_compute_pipe_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.compute_pipe_wm)
- return dev_priv->display.compute_pipe_wm(state, crtc);
+ if (dev_priv->wm_disp.compute_pipe_wm)
+ return dev_priv->wm_disp.compute_pipe_wm(state, crtc);
return 0;
}
@@ -179,20 +179,20 @@ static int intel_compute_intermediate_wm(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (!dev_priv->display.compute_intermediate_wm)
+ if (!dev_priv->wm_disp.compute_intermediate_wm)
return 0;
if (drm_WARN_ON(_priv->drm,
- !dev_priv->display.compute_pipe_wm))
+ !dev_priv->wm_disp.compute_pipe_wm))
return 0;
- return dev_priv->display.compute_intermediate_wm(state, crtc);
+ return dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
}
static bool intel_initial_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.initial_watermarks) {
- dev_priv->display.initial_watermarks(state, crtc);
+ if (dev_priv->wm_disp.initial_watermarks) {
+ dev_priv->wm_disp.initial_watermarks(state, crtc);
return true;
}
return false;
@@ -202,23 +202,23 @@ static void intel_atomic_update_watermarks(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.atomic_update_watermarks)
- dev_priv->display.atomic_update_watermarks(state, crtc);
+ if (dev_priv->wm_disp.atomic_update_watermarks)
+ dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
}
static void intel_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.optimize_watermarks)
- dev_priv->display.optimize_watermarks(state, crtc);
+ if (dev_priv->wm_disp.optimize_watermarks)
+ dev_priv->wm_disp.optimize_watermarks(state, crtc);
}
static void intel_compute_global_watermarks(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.compute_global_watermarks)
- dev_priv->display.compute_global_watermarks(state);
+ if (dev_priv->wm_disp.compute_global_watermarks)
+ dev_priv->wm_disp.compute_global_watermarks(state);
}
/* returns HPLL frequency in kHz */
@@ -3669,6 +3669,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state
*state,
if (!intel_initial_watermarks(state, crtc))
intel_update_watermarks(dev_priv);
+
intel_enable_pipe(new_crtc_state);
intel_crtc_vblank_on(new_crtc_state);
@@ -3734,7 +3735,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state
*state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
- if (!dev_priv->display.initial_watermarks)
+ if (!dev_priv->wm_disp.initial_watermarks)
intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
@@ -11387,7 +11388,7 @@ static void sanitize_watermarks(struct drm_i915_private
*dev_priv)
int i;
[Intel-gfx] [PATCH 08/25] drm/i915: split clock gating init from display vtable
From: Dave Airlie
This function is only used inside intel_pm.c
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_drv.h | 9 ++-
drivers/gpu/drm/i915/intel_pm.c | 48 -
2 files changed, 32 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 894c883044ee..48d30b967def 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -323,6 +323,11 @@ struct intel_crtc;
struct intel_limit;
struct dpll;
+/* functions used internal in intel_pm.c */
+struct drm_i915_clock_gating_funcs {
+ void (*init_clock_gating)(struct drm_i915_private *dev_priv);
+};
+
struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config);
@@ -365,7 +370,6 @@ struct drm_i915_display_funcs {
const struct drm_connector_state
*old_conn_state);
void (*fdi_link_train)(struct intel_crtc *crtc,
const struct intel_crtc_state *crtc_state);
- void (*init_clock_gating)(struct drm_i915_private *dev_priv);
void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
/* clock updates for mode set */
/* cursor updates */
@@ -954,6 +958,9 @@ struct drm_i915_private {
/* unbound hipri wq for page flips/plane updates */
struct workqueue_struct *flip_wq;
+ /* pm private clock gating functions */
+ struct drm_i915_clock_gating_funcs clock_gating_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4054c6f7a2f9..add50ff01d7c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating(struct drm_i915_private *dev_priv)
{
- dev_priv->display.init_clock_gating(dev_priv);
+ dev_priv->clock_gating_funcs.init_clock_gating(dev_priv);
}
void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7898,52 +7898,52 @@ static void nop_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_ALDERLAKE_P(dev_priv))
- dev_priv->display.init_clock_gating = adlp_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
adlp_init_clock_gating;
else if (IS_DG1(dev_priv))
- dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
dg1_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 12)
- dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
gen12lp_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 11)
- dev_priv->display.init_clock_gating = icl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
icl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
- dev_priv->display.init_clock_gating = cfl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
cfl_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
- dev_priv->display.init_clock_gating = skl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
skl_init_clock_gating;
else if (IS_KABYLAKE(dev_priv))
- dev_priv->display.init_clock_gating = kbl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
kbl_init_clock_gating;
else if (IS_BROXTON(dev_priv))
- dev_priv->display.init_clock_gating = bxt_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
bxt_init_clock_gating;
else if (IS_GEMINILAKE(dev_priv))
- dev_priv->display.init_clock_gating = glk_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
glk_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
- dev_priv->display.init_clock_gating = bdw_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
bdw_init_clock_gating;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->display.init_clock_gating = chv_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
chv_init_clock_gating;
else if (IS_HASWELL(dev_priv))
- dev_priv->display.init_clock_gating = hsw_init_clock_gating;
+ dev_priv->clock_gating_funcs.init
[Intel-gfx] [PATCH 07/25] drm/i915/display: add intel_fdi_link_train wrapper.
From: Dave Airlie
This wraps the fdi link training vfunc to make it clearer.
Suggested by Jani.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 8
drivers/gpu/drm/i915/display/intel_fdi.h | 2 ++
3 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 71518e71591b..aa174192c279 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2156,7 +2156,7 @@ static void ilk_pch_enable(const struct
intel_atomic_state *state,
assert_pch_transcoder_disabled(dev_priv, pipe);
/* For PCH output, training FDI link */
- dev_priv->display.fdi_link_train(crtc, crtc_state);
+ intel_fdi_link_train(crtc, crtc_state);
/* We need to program the right clock selection before writing the pixel
* mutliplier into the DPLL. */
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index fc09b781f15f..339243399a65 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -10,6 +10,14 @@
#include "intel_fdi.h"
#include "intel_sideband.h"
+void intel_fdi_link_train(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+
+ dev_priv->display.fdi_link_train(crtc, crtc_state);
+}
+
/* units of 100MHz */
static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
{
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h
b/drivers/gpu/drm/i915/display/intel_fdi.h
index 60acf2133145..61cb216a09f5 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.h
+++ b/drivers/gpu/drm/i915/display/intel_fdi.h
@@ -26,4 +26,6 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
void intel_fdi_pll_freq_update(struct drm_i915_private *i915);
void lpt_fdi_program_mphy(struct drm_i915_private *i915);
+void intel_fdi_link_train(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state);
#endif
--
2.31.1
[Intel-gfx] [PATCH 06/25] drm/i915: add wrappers around cdclk vtable funcs.
From: Dave Airlie
This adds wrappers around all the vtable callers so they are in
one place.
Suggested by Jani.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_cdclk.c| 47 +++
drivers/gpu/drm/i915/display/intel_cdclk.h| 4 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
.../drm/i915/display/intel_display_power.c| 2 +-
4 files changed, 44 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9aec17b33819..0e09f259914f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -59,6 +59,37 @@
* dividers can be programmed correctly.
*/
+void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_config *cdclk_config)
+{
+ dev_priv->display.get_cdclk(dev_priv, cdclk_config);
+}
+
+int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ return dev_priv->display.bw_calc_min_cdclk(state);
+}
+
+static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
+ const struct intel_cdclk_config *cdclk_config,
+ enum pipe pipe)
+{
+ dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+}
+
+static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
+ struct intel_cdclk_state
*cdclk_config)
+{
+ return dev_priv->display.modeset_calc_cdclk(cdclk_config);
+}
+
+static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
+int cdclk)
+{
+ return dev_priv->display.calc_voltage_level(cdclk);
+}
+
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
@@ -1466,7 +1497,7 @@ static void bxt_get_cdclk(struct drm_i915_private
*dev_priv,
* at least what the CDCLK frequency requires.
*/
cdclk_config->voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk);
}
static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1777,7 +1808,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private
*dev_priv)
cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
cdclk_config.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
bxt_set_cdclk(dev_priv, _config, INVALID_PIPE);
}
@@ -1789,7 +1820,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private
*dev_priv)
cdclk_config.cdclk = cdclk_config.bypass;
cdclk_config.vco = 0;
cdclk_config.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
bxt_set_cdclk(dev_priv, _config, INVALID_PIPE);
}
@@ -1956,7 +1987,7 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
_priv->gmbus_mutex);
}
- dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+ intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
for_each_intel_dp(_priv->drm, encoder) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2424,7 +2455,7 @@ static int bxt_modeset_calc_cdclk(struct
intel_cdclk_state *cdclk_state)
cdclk_state->logical.cdclk = cdclk;
cdclk_state->logical.voltage_level =
max_t(int, min_voltage_level,
- dev_priv->display.calc_voltage_level(cdclk));
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk));
if (!cdclk_state->active_pipes) {
cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
@@ -2433,7 +2464,7 @@ static int bxt_modeset_calc_cdclk(struct
intel_cdclk_state *cdclk_state)
cdclk_state->actual.vco = vco;
cdclk_state->actual.cdclk = cdclk;
cdclk_state->actual.voltage_level =
- dev_priv->display.calc_voltage_level(cdclk);
+ intel_cdclk_calc_voltage_level(dev_priv, cdclk);
} else {
cdclk_state->actual = cdclk_state->logical;
}
@@ -2525,7 +2556,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state
*state)
new_cdclk_state->active_pipes =
intel_calc_active_pipes(state, old_cdclk_state->active_pipes)
[Intel-gfx] [PATCH 05/25] drm/i915/wm: provide wrappers around watermark vfuncs calls (v2)
From: Dave Airlie
This moves one wrapper from the pm->display side, and creates
wrappers for all the others, this should simplify things later.
One thing to note is that the code checks the existance of some
of these ptrs, so the wrappers are a bit complicated by that.
Suggested by Jani.
v2: fixup warnings in wrong place error.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 187 ---
drivers/gpu/drm/i915/intel_pm.c | 39
drivers/gpu/drm/i915/intel_pm.h | 1 -
3 files changed, 123 insertions(+), 104 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index e62f8317cbda..a1380ce02861 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -126,6 +126,101 @@ static void ilk_pfit_enable(const struct intel_crtc_state
*crtc_state);
static void intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx);
+
+/**
+ * intel_update_watermarks - update FIFO watermark values based on current
modes
+ * @dev_priv: i915 device
+ *
+ * Calculate watermark values for the various WM regs based on current mode
+ * and plane configuration.
+ *
+ * There are several cases to deal with here:
+ * - normal (i.e. non-self-refresh)
+ * - self-refresh (SR) mode
+ * - lines are large relative to FIFO size (buffer can hold up to 2)
+ * - lines are small relative to FIFO size (buffer can hold more than 2
+ * lines), so need to account for TLB latency
+ *
+ * The normal calculation is:
+ * watermark = dotclock * bytes per pixel * latency
+ * where latency is platform & configuration dependent (we assume pessimal
+ * values here).
+ *
+ * The SR calculation is:
+ * watermark = (trunc(latency/line time)+1) * surface width *
+ * bytes per pixel
+ * where
+ * line time = htotal / dotclock
+ * surface width = hdisplay for normal plane and 64 for cursor
+ * and latency is assumed to be high, as above.
+ *
+ * The final value programmed to the register should always be rounded up,
+ * and include an extra 2 entries to account for clock crossings.
+ *
+ * We don't use the sprite, so we can ignore that. And on Crestline we have
+ * to set the non-SR watermarks to 8.
+ */
+static void intel_update_watermarks(struct drm_i915_private *dev_priv)
+{
+ if (dev_priv->display.update_wm)
+ dev_priv->display.update_wm(dev_priv);
+}
+
+static int intel_compute_pipe_wm(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.compute_pipe_wm)
+ return dev_priv->display.compute_pipe_wm(state, crtc);
+ return 0;
+}
+
+static int intel_compute_intermediate_wm(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (!dev_priv->display.compute_intermediate_wm)
+ return 0;
+ if (drm_WARN_ON(_priv->drm,
+ !dev_priv->display.compute_pipe_wm))
+ return 0;
+ return dev_priv->display.compute_intermediate_wm(state, crtc);
+}
+
+static bool intel_initial_watermarks(struct intel_atomic_state *state,
+struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.initial_watermarks) {
+ dev_priv->display.initial_watermarks(state, crtc);
+ return true;
+ }
+ return false;
+}
+
+static void intel_atomic_update_watermarks(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.atomic_update_watermarks)
+ dev_priv->display.atomic_update_watermarks(state, crtc);
+}
+
+static void intel_optimize_watermarks(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.optimize_watermarks)
+ dev_priv->display.optimize_watermarks(state, crtc);
+}
+
+static void intel_compute_global_watermarks(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ if (dev_priv->display.compute_global_watermarks)
+ dev_priv->display.compute_global_watermarks(state);
+}
+
/* returns HPLL frequency in kHz */
int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
{
@@ -2528,9 +2623,8 @@ static void intel_pre_plane_up
[Intel-gfx] [PATCH 04/25] drm/i915: make update_wm take a dev_priv.
From: Dave Airlie
The crtc was never being used here.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 20 +++-
drivers/gpu/drm/i915/intel_pm.h | 2 +-
4 files changed, 14 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 134c792e1dbd..e62f8317cbda 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2374,7 +2374,7 @@ static void intel_post_plane_update(struct
intel_atomic_state *state,
intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
if (hsw_post_update_enable_ips(old_crtc_state, new_crtc_state))
hsw_enable_ips(new_crtc_state);
@@ -2531,7 +2531,7 @@ static void intel_pre_plane_update(struct
intel_atomic_state *state,
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
else if (new_crtc_state->update_wm_pre)
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
}
/*
@@ -3578,7 +3578,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state
*state,
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
else
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
intel_enable_pipe(new_crtc_state);
intel_crtc_vblank_on(new_crtc_state);
@@ -3645,7 +3645,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state
*state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
if (!dev_priv->display.initial_watermarks)
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
if (IS_I830(dev_priv))
@@ -3721,7 +3721,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc
*crtc,
encoder->base.crtc = NULL;
intel_fbc_disable(crtc);
- intel_update_watermarks(crtc);
+ intel_update_watermarks(dev_priv);
intel_disable_shared_dpll(crtc_state);
intel_display_power_put_all_in_set(dev_priv,
>enabled_power_domains);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fc546d2ff0fc..894c883044ee 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -341,7 +341,7 @@ struct drm_i915_display_funcs {
void (*optimize_watermarks)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*compute_global_watermarks)(struct intel_atomic_state *state);
- void (*update_wm)(struct intel_crtc *crtc);
+ void (*update_wm)(struct drm_i915_private *dev_priv);
int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
u8 (*calc_voltage_level)(int cdclk);
/* Returns the active state of the crtc, and if the crtc is active,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d9993eb3730d..be6520756aae 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -881,9 +881,8 @@ static struct intel_crtc *single_enabled_crtc(struct
drm_i915_private *dev_priv)
return enabled;
}
-static void pnv_update_wm(struct intel_crtc *unused_crtc)
+static void pnv_update_wm(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
const struct cxsr_latency *latency;
u32 reg;
@@ -2253,9 +2252,8 @@ static void vlv_optimize_watermarks(struct
intel_atomic_state *state,
mutex_unlock(_priv->wm.wm_mutex);
}
-static void i965_update_wm(struct intel_crtc *unused_crtc)
+static void i965_update_wm(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
struct intel_crtc *crtc;
int srwm = 1;
int cursor_sr = 16;
@@ -2329,9 +2327,8 @@ static void i965_update_wm(struct intel_crtc *unused_crtc)
#undef FW_WM
-static void i9xx_update_wm(struct intel_crtc *unused_crtc)
+static void i9xx_update_wm(struct drm_i915_private *dev_priv)
{
- struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
const struct intel_watermark_params *wm_info;
u32 fwater_lo;
u32 fwater_hi;
@@
[Intel-gfx] [PATCH 03/25] drm/i915/pm: drop get_fifo_size vfunc.
From: Dave Airlie
The i845_update_wm code was always calling the i845 variant,
and the i9xx_update_wm had only a choice between i830 and i9xx
paths, hardly worth the vfunc overhead.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/intel_pm.c | 20 +++-
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a8129153d1db..fc546d2ff0fc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -330,8 +330,6 @@ struct drm_i915_display_funcs {
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe);
int (*bw_calc_min_cdclk)(struct intel_atomic_state *state);
- int (*get_fifo_size)(struct drm_i915_private *dev_priv,
-enum i9xx_plane_id i9xx_plane);
int (*compute_pipe_wm)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
int (*compute_intermediate_wm)(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cfc41f8fa74a..d9993eb3730d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2347,7 +2347,10 @@ static void i9xx_update_wm(struct intel_crtc
*unused_crtc)
else
wm_info = _a_wm_info;
- fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_A);
+ if (DISPLAY_VER(dev_priv) == 2)
+ fifo_size = i830_get_fifo_size(dev_priv, PLANE_A);
+ else
+ fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_A);
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *pipe_mode =
@@ -2374,7 +2377,10 @@ static void i9xx_update_wm(struct intel_crtc
*unused_crtc)
if (DISPLAY_VER(dev_priv) == 2)
wm_info = _bc_wm_info;
- fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B);
+ if (DISPLAY_VER(dev_priv) == 2)
+ fifo_size = i830_get_fifo_size(dev_priv, PLANE_B);
+ else
+ fifo_size = i9xx_get_fifo_size(dev_priv, PLANE_B);
crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
if (intel_crtc_active(crtc)) {
const struct drm_display_mode *pipe_mode =
@@ -2490,7 +2496,7 @@ static void i845_update_wm(struct intel_crtc *unused_crtc)
pipe_mode = >config->hw.pipe_mode;
planea_wm = intel_calculate_wm(pipe_mode->crtc_clock,
_wm_info,
-
dev_priv->display.get_fifo_size(dev_priv, PLANE_A),
+ i845_get_fifo_size(dev_priv, PLANE_A),
4, pessimal_latency_ns);
fwater_lo = intel_uncore_read(_priv->uncore, FW_BLC) & ~0xfff;
fwater_lo |= (3<<8) | planea_wm;
@@ -8054,15 +8060,11 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
dev_priv->display.update_wm = i965_update_wm;
} else if (DISPLAY_VER(dev_priv) == 3) {
dev_priv->display.update_wm = i9xx_update_wm;
- dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
} else if (DISPLAY_VER(dev_priv) == 2) {
- if (INTEL_NUM_PIPES(dev_priv) == 1) {
+ if (INTEL_NUM_PIPES(dev_priv) == 1)
dev_priv->display.update_wm = i845_update_wm;
- dev_priv->display.get_fifo_size = i845_get_fifo_size;
- } else {
+ else
dev_priv->display.update_wm = i9xx_update_wm;
- dev_priv->display.get_fifo_size = i830_get_fifo_size;
- }
} else {
drm_err(_priv->drm,
"unexpected fall-through in %s\n", __func__);
--
2.31.1
[Intel-gfx] [PATCH 02/25] drm/i915/uncore: constify the register vtables.
From: Dave Airlie
This reworks the uncore function vtable so that it's constant.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/intel_uncore.c | 139 +---
drivers/gpu/drm/i915/intel_uncore.h | 8 +-
2 files changed, 89 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 2dac69d92c1b..94bcc0a8dbeb 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1762,32 +1762,24 @@ __vgpu_write(8)
__vgpu_write(16)
__vgpu_write(32)
-#define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
-do { \
- (uncore)->funcs.mmio_writeb = x##_write8; \
- (uncore)->funcs.mmio_writew = x##_write16; \
- (uncore)->funcs.mmio_writel = x##_write32; \
-} while (0)
-
-#define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \
-do { \
- (uncore)->funcs.mmio_readb = x##_read8; \
- (uncore)->funcs.mmio_readw = x##_read16; \
- (uncore)->funcs.mmio_readl = x##_read32; \
- (uncore)->funcs.mmio_readq = x##_read64; \
-} while (0)
-
-#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
-do { \
- ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \
- (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
-} while (0)
-
-#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
-do { \
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \
- (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
-} while (0)
+#define MMIO_RAW_WRITE_VFUNCS(x) \
+ .mmio_writeb = x##_write8, \
+ .mmio_writew = x##_write16, \
+ .mmio_writel = x##_write32
+
+#define MMIO_RAW_READ_VFUNCS(x) \
+ .mmio_readb = x##_read8, \
+ .mmio_readw = x##_read16, \
+ .mmio_readl = x##_read32, \
+ .mmio_readq = x##_read64
+
+#define MMIO_WRITE_FW_VFUNCS(x)\
+ MMIO_RAW_WRITE_VFUNCS(x), \
+ .write_fw_domains = x##_reg_write_fw_domains
+
+#define MMIO_READ_FW_VFUNCS(x) \
+ MMIO_RAW_READ_VFUNCS(x),\
+ .read_fw_domains = x##_reg_read_fw_domains
static int __fw_domain_init(struct intel_uncore *uncore,
enum forcewake_domain_id domain_id,
@@ -2092,22 +2084,70 @@ void intel_uncore_init_early(struct intel_uncore
*uncore,
uncore->debug = >mmio_debug;
}
+static const struct intel_uncore_funcs vgpu_funcs = {
+ MMIO_RAW_WRITE_VFUNCS(vgpu),
+ MMIO_RAW_READ_VFUNCS(vgpu),
+};
+
+static const struct intel_uncore_funcs gen5_funcs = {
+ MMIO_RAW_WRITE_VFUNCS(gen5),
+ MMIO_RAW_READ_VFUNCS(gen5),
+};
+
+static const struct intel_uncore_funcs gen2_funcs = {
+ MMIO_RAW_WRITE_VFUNCS(gen2),
+ MMIO_RAW_READ_VFUNCS(gen2),
+};
+
+
static void uncore_raw_init(struct intel_uncore *uncore)
{
GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
if (intel_vgpu_active(uncore->i915)) {
- ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu);
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu);
+ uncore->funcs = _funcs;
} else if (GRAPHICS_VER(uncore->i915) == 5) {
- ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
+ uncore->funcs = _funcs;
} else {
- ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2);
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2);
+ uncore->funcs = _funcs;
}
}
+static const struct intel_uncore_funcs xehp_funcs = {
+ MMIO_WRITE_FW_VFUNCS(xehp_fwtable),
+ MMIO_READ_FW_VFUNCS(gen11_fwtable)
+};
+
+static const struct intel_uncore_funcs gen12_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen12_fwtable),
+ MMIO_READ_FW_VFUNCS(gen12_fwtable)
+};
+
+static const struct intel_uncore_funcs gen11_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen11_fwtable),
+ MMIO_READ_FW_VFUNCS(gen11_fwtable)
+};
+
+static const struct intel_uncore_funcs fwtable_funcs = {
+ MMIO_WRITE_FW_VFUNCS(fwtable),
+ MMIO_READ_FW_VFUNCS(fwtable)
+};
+
+static const struct intel_uncore_funcs gen8_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen8),
+ MMIO_READ_FW_VFUNCS(gen6)
+};
+
+static const struct intel_uncore_funcs vlv_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen6),
+ MMIO_READ_FW_VFUNCS(fwtable)
+};
+
+static const struct intel_uncore_funcs gen6_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen6),
+ MMIO_READ_FW_VFUNCS(gen6)
+};
+
static int uncore_forcewake_init(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore->i915;
@@ -2122,38 +2162,29 @@ static int uncore_forcewake_init(struct intel_uncore
*uncore)
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
- ASSIGN_WRITE_MMIO_VFUNCS(uncore, xehp_fw
[Intel-gfx] [PATCH 01/25] drm/i915/uncore: split the fw get function into separate vfunc
From: Dave Airlie
constify it while here. drop the put function since it was never
overloaded and always has done the same thing, no point in
indirecting it for show.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/intel_uncore.c | 70 -
drivers/gpu/drm/i915/intel_uncore.h | 7 +--
2 files changed, 43 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 6b38bc2811c1..2dac69d92c1b 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -36,6 +36,12 @@
#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
+static void
+fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
+{
+ uncore->fw_get_funcs->force_wake_get(uncore, fw_domains);
+}
+
void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
{
@@ -248,7 +254,7 @@ fw_domain_put(const struct intel_uncore_forcewake_domain *d)
}
static void
-fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
+fw_domains_get_normal(struct intel_uncore *uncore, enum forcewake_domains
fw_domains)
{
struct intel_uncore_forcewake_domain *d;
unsigned int tmp;
@@ -396,7 +402,7 @@ intel_uncore_fw_release_timer(struct hrtimer *timer)
GEM_BUG_ON(!domain->wake_count);
if (--domain->wake_count == 0)
- uncore->funcs.force_wake_put(uncore, domain->mask);
+ fw_domains_put(uncore, domain->mask);
spin_unlock_irqrestore(>lock, irqflags);
@@ -454,7 +460,7 @@ intel_uncore_forcewake_reset(struct intel_uncore *uncore)
fw = uncore->fw_domains_active;
if (fw)
- uncore->funcs.force_wake_put(uncore, fw);
+ fw_domains_put(uncore, fw);
fw_domains_reset(uncore, uncore->fw_domains);
assert_forcewakes_inactive(uncore);
@@ -562,7 +568,7 @@ static void forcewake_early_sanitize(struct intel_uncore
*uncore,
intel_uncore_forcewake_reset(uncore);
if (restore_forcewake) {
spin_lock_irq(>lock);
- uncore->funcs.force_wake_get(uncore, restore_forcewake);
+ fw_domains_get(uncore, restore_forcewake);
if (intel_uncore_has_fifo(uncore))
uncore->fifo_count = fifo_free_entries(uncore);
@@ -623,7 +629,7 @@ static void __intel_uncore_forcewake_get(struct
intel_uncore *uncore,
}
if (fw_domains)
- uncore->funcs.force_wake_get(uncore, fw_domains);
+ fw_domains_get(uncore, fw_domains);
}
/**
@@ -644,7 +650,7 @@ void intel_uncore_forcewake_get(struct intel_uncore *uncore,
{
unsigned long irqflags;
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
assert_rpm_wakelock_held(uncore->rpm);
@@ -711,7 +717,7 @@ void intel_uncore_forcewake_get__locked(struct intel_uncore
*uncore,
{
lockdep_assert_held(>lock);
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
__intel_uncore_forcewake_get(uncore, fw_domains);
@@ -733,7 +739,7 @@ static void __intel_uncore_forcewake_put(struct
intel_uncore *uncore,
continue;
}
- uncore->funcs.force_wake_put(uncore, domain->mask);
+ fw_domains_put(uncore, domain->mask);
}
}
@@ -750,7 +756,7 @@ void intel_uncore_forcewake_put(struct intel_uncore *uncore,
{
unsigned long irqflags;
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
spin_lock_irqsave(>lock, irqflags);
@@ -769,7 +775,7 @@ void intel_uncore_forcewake_flush(struct intel_uncore
*uncore,
struct intel_uncore_forcewake_domain *domain;
unsigned int tmp;
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
fw_domains &= uncore->fw_domains;
@@ -793,7 +799,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore
*uncore,
{
lockdep_assert_held(>lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
__intel_uncore_forcewake_put(uncore, fw_domains);
@@ -801,7 +807,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore
*uncore,
void assert_forcewakes_inactive(struct intel_uncore *uncore)
{
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
drm_WARN(>i915->drm, uncore->fw_domains_active,
@@ -818,7 +824,7 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
[Intel-gfx] i915/display: split and constify vtable (v4)
v4: I know I could have resent one patch but there was a bit of rebase fallout from it, and it had another subtle bug, I also fixed the kerneldoc. (v3 just adds some missing ,) Details below, I've taken all the review feedback (thanks Jani). I added 3 patches moving to wrappers before refactoring, and one other patch is unreviewed (07) but the main comment was wanting the wrappers. Jani if you are happy with the final 4 patches can you land this series, I don't think I have drm-intel commit rights. v1: This is orthogonal to my display ptr refactoring and should probably be applied first. The display funcs vtable was a bit of mess, lots of intermixing of internal display functionality and interfaces to watermarks/irqs. It's also considered not great security practice to leave writeable function pointers around for exploits to get into. This series attempts to address both problems, first there are a few cleanups, then it splits the function table into multiple pieces. Some of the splits might be bikesheds but I think we should apply first and merge things later if there is good reason. The second half converts all the vtables to static const structs, I've used macros in some of them to make it less messy, the cdclk one is probably the worst one. v2: Added some patches adding wrappers around things before refactoring them as suggested by Jani. Fixed up all struct names as suggested by Jani. Added s-o-b lines Added commit msgs. v3: added missing , (Jani) v4: fix wm bug the crept in (Jani), fix kernel doc warning (CI) Dave.
Re: [Intel-gfx] [PULL] drm-misc-fixes
On Thu, 9 Sept 2021 at 03:44, Thomas Zimmermann wrote: > > Hi Dave and Daniel, > > here's this week's PR for drm-misc-fixes. One patch is a potential deadlock > in TTM, the other enables an additional plane in kmb. I'm slightly unhappy > that the latter one ended up in -fixes as it's not a bugfix AFAICT. To avoid messy merge window, I'm not pulling this until after rc1 unless there is some major reason? the current drm-next doesn't have v5.14 in it, and the merge is rather ugly right now. (maybe I should always pull it in before sending to Linus to avoid this in future). Dave.
[Intel-gfx] [PATCH 2/2] drm/i915/uncore: constify the register vtables. (v2)
From: Dave Airlie
This reworks the uncore function vtable so that it's constant.
v2: fixup selftest mocking.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/intel_uncore.c | 133 +++
drivers/gpu/drm/i915/intel_uncore.h | 8 +-
drivers/gpu/drm/i915/selftests/mock_uncore.c | 9 +-
3 files changed, 89 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 8652e4221404..e0e7f133f2b9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1737,32 +1737,24 @@ __vgpu_write(8)
__vgpu_write(16)
__vgpu_write(32)
-#define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
-do { \
- (uncore)->funcs.mmio_writeb = x##_write8; \
- (uncore)->funcs.mmio_writew = x##_write16; \
- (uncore)->funcs.mmio_writel = x##_write32; \
-} while (0)
-
-#define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \
-do { \
- (uncore)->funcs.mmio_readb = x##_read8; \
- (uncore)->funcs.mmio_readw = x##_read16; \
- (uncore)->funcs.mmio_readl = x##_read32; \
- (uncore)->funcs.mmio_readq = x##_read64; \
-} while (0)
-
-#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
-do { \
- ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \
- (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
-} while (0)
-
-#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
-do { \
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \
- (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
-} while (0)
+#define MMIO_RAW_WRITE_VFUNCS(x) \
+ .mmio_writeb = x##_write8, \
+ .mmio_writew = x##_write16, \
+ .mmio_writel = x##_write32
+
+#define MMIO_RAW_READ_VFUNCS(x) \
+ .mmio_readb = x##_read8, \
+ .mmio_readw = x##_read16, \
+ .mmio_readl = x##_read32, \
+ .mmio_readq = x##_read64
+
+#define MMIO_WRITE_FW_VFUNCS(x)\
+ MMIO_RAW_WRITE_VFUNCS(x), \
+ .write_fw_domains = x##_reg_write_fw_domains
+
+#define MMIO_READ_FW_VFUNCS(x) \
+ MMIO_RAW_READ_VFUNCS(x),\
+ .read_fw_domains = x##_reg_read_fw_domains
static int __fw_domain_init(struct intel_uncore *uncore,
enum forcewake_domain_id domain_id,
@@ -2067,22 +2059,64 @@ void intel_uncore_init_early(struct intel_uncore
*uncore,
uncore->debug = >mmio_debug;
}
+static const struct intel_uncore_funcs vgpu_funcs = {
+ MMIO_RAW_WRITE_VFUNCS(vgpu),
+ MMIO_RAW_READ_VFUNCS(vgpu),
+};
+
+static const struct intel_uncore_funcs gen5_funcs = {
+ MMIO_RAW_WRITE_VFUNCS(gen5),
+ MMIO_RAW_READ_VFUNCS(gen5),
+};
+
+static const struct intel_uncore_funcs gen2_funcs = {
+ MMIO_RAW_WRITE_VFUNCS(gen2),
+ MMIO_RAW_READ_VFUNCS(gen2),
+};
+
static void uncore_raw_init(struct intel_uncore *uncore)
{
GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
if (intel_vgpu_active(uncore->i915)) {
- ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu);
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu);
+ uncore->funcs = _funcs;
} else if (GRAPHICS_VER(uncore->i915) == 5) {
- ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
+ uncore->funcs = _funcs;
} else {
- ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2);
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2);
+ uncore->funcs = _funcs;
}
}
+static const struct intel_uncore_funcs gen12_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen12_fwtable),
+ MMIO_READ_FW_VFUNCS(gen11_fwtable)
+};
+
+static const struct intel_uncore_funcs gen11_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen11_fwtable),
+ MMIO_READ_FW_VFUNCS(gen11_fwtable)
+};
+
+static const struct intel_uncore_funcs fwtable_funcs = {
+ MMIO_WRITE_FW_VFUNCS(fwtable),
+ MMIO_READ_FW_VFUNCS(fwtable)
+};
+
+static const struct intel_uncore_funcs gen8_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen8),
+ MMIO_READ_FW_VFUNCS(gen6)
+};
+
+static const struct intel_uncore_funcs vlv_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen6),
+ MMIO_READ_FW_VFUNCS(fwtable)
+};
+
+static const struct intel_uncore_funcs gen6_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen6),
+ MMIO_READ_FW_VFUNCS(gen6)
+};
+
static int uncore_forcewake_init(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore->i915;
@@ -2097,38 +2131,29 @@ static int uncore_forcewake_init(struct intel_uncore
*uncore)
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
- ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
- ASSIGN_READ_MMIO_VFUNCS(uncore,
[Intel-gfx] [PATCH 1/2] drm/i915/uncore: split the fw get function into separate vfunc
From: Dave Airlie
constify it while here. drop the put function since it was never
overloaded and always has done the same thing, no point in
indirecting it for show.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/intel_uncore.c | 70 -
drivers/gpu/drm/i915/intel_uncore.h | 7 +--
2 files changed, 43 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index f9767054dbdf..8652e4221404 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -36,6 +36,12 @@
#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
+static void
+fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
+{
+ uncore->fw_get_funcs->force_wake_get(uncore, fw_domains);
+}
+
void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
{
@@ -248,7 +254,7 @@ fw_domain_put(const struct intel_uncore_forcewake_domain *d)
}
static void
-fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
+fw_domains_get_normal(struct intel_uncore *uncore, enum forcewake_domains
fw_domains)
{
struct intel_uncore_forcewake_domain *d;
unsigned int tmp;
@@ -396,7 +402,7 @@ intel_uncore_fw_release_timer(struct hrtimer *timer)
GEM_BUG_ON(!domain->wake_count);
if (--domain->wake_count == 0)
- uncore->funcs.force_wake_put(uncore, domain->mask);
+ fw_domains_put(uncore, domain->mask);
spin_unlock_irqrestore(>lock, irqflags);
@@ -454,7 +460,7 @@ intel_uncore_forcewake_reset(struct intel_uncore *uncore)
fw = uncore->fw_domains_active;
if (fw)
- uncore->funcs.force_wake_put(uncore, fw);
+ fw_domains_put(uncore, fw);
fw_domains_reset(uncore, uncore->fw_domains);
assert_forcewakes_inactive(uncore);
@@ -562,7 +568,7 @@ static void forcewake_early_sanitize(struct intel_uncore
*uncore,
intel_uncore_forcewake_reset(uncore);
if (restore_forcewake) {
spin_lock_irq(>lock);
- uncore->funcs.force_wake_get(uncore, restore_forcewake);
+ fw_domains_get(uncore, restore_forcewake);
if (intel_uncore_has_fifo(uncore))
uncore->fifo_count = fifo_free_entries(uncore);
@@ -623,7 +629,7 @@ static void __intel_uncore_forcewake_get(struct
intel_uncore *uncore,
}
if (fw_domains)
- uncore->funcs.force_wake_get(uncore, fw_domains);
+ fw_domains_get(uncore, fw_domains);
}
/**
@@ -644,7 +650,7 @@ void intel_uncore_forcewake_get(struct intel_uncore *uncore,
{
unsigned long irqflags;
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
assert_rpm_wakelock_held(uncore->rpm);
@@ -711,7 +717,7 @@ void intel_uncore_forcewake_get__locked(struct intel_uncore
*uncore,
{
lockdep_assert_held(>lock);
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
__intel_uncore_forcewake_get(uncore, fw_domains);
@@ -733,7 +739,7 @@ static void __intel_uncore_forcewake_put(struct
intel_uncore *uncore,
continue;
}
- uncore->funcs.force_wake_put(uncore, domain->mask);
+ fw_domains_put(uncore, domain->mask);
}
}
@@ -750,7 +756,7 @@ void intel_uncore_forcewake_put(struct intel_uncore *uncore,
{
unsigned long irqflags;
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
spin_lock_irqsave(>lock, irqflags);
@@ -769,7 +775,7 @@ void intel_uncore_forcewake_flush(struct intel_uncore
*uncore,
struct intel_uncore_forcewake_domain *domain;
unsigned int tmp;
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
fw_domains &= uncore->fw_domains;
@@ -793,7 +799,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore
*uncore,
{
lockdep_assert_held(>lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
__intel_uncore_forcewake_put(uncore, fw_domains);
@@ -801,7 +807,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore
*uncore,
void assert_forcewakes_inactive(struct intel_uncore *uncore)
{
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
drm_WARN(>i915->drm, uncore->fw_domains_active,
@@ -818,7 +824,7 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
[Intel-gfx] [PATCH 0/2] i915/uncore: constify the uncore vtables.
static const vtables are more secure than writeable function pointers. These two patches cleanup the uncore vtable to use static const tables. v2: rebased onto drm-tip v3: fix selftests build failure. Dave.
[Intel-gfx] [PATCH 2/2] drm/i915/uncore: constify the register vtables.
From: Dave Airlie
This reworks the uncore function vtable so that it's constant.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/intel_uncore.c | 133 +---
drivers/gpu/drm/i915/intel_uncore.h | 8 +-
2 files changed, 83 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 8652e4221404..e0e7f133f2b9 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1737,32 +1737,24 @@ __vgpu_write(8)
__vgpu_write(16)
__vgpu_write(32)
-#define ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, x) \
-do { \
- (uncore)->funcs.mmio_writeb = x##_write8; \
- (uncore)->funcs.mmio_writew = x##_write16; \
- (uncore)->funcs.mmio_writel = x##_write32; \
-} while (0)
-
-#define ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x) \
-do { \
- (uncore)->funcs.mmio_readb = x##_read8; \
- (uncore)->funcs.mmio_readw = x##_read16; \
- (uncore)->funcs.mmio_readl = x##_read32; \
- (uncore)->funcs.mmio_readq = x##_read64; \
-} while (0)
-
-#define ASSIGN_WRITE_MMIO_VFUNCS(uncore, x) \
-do { \
- ASSIGN_RAW_WRITE_MMIO_VFUNCS((uncore), x); \
- (uncore)->funcs.write_fw_domains = x##_reg_write_fw_domains; \
-} while (0)
-
-#define ASSIGN_READ_MMIO_VFUNCS(uncore, x) \
-do { \
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, x); \
- (uncore)->funcs.read_fw_domains = x##_reg_read_fw_domains; \
-} while (0)
+#define MMIO_RAW_WRITE_VFUNCS(x) \
+ .mmio_writeb = x##_write8, \
+ .mmio_writew = x##_write16, \
+ .mmio_writel = x##_write32
+
+#define MMIO_RAW_READ_VFUNCS(x) \
+ .mmio_readb = x##_read8, \
+ .mmio_readw = x##_read16, \
+ .mmio_readl = x##_read32, \
+ .mmio_readq = x##_read64
+
+#define MMIO_WRITE_FW_VFUNCS(x)\
+ MMIO_RAW_WRITE_VFUNCS(x), \
+ .write_fw_domains = x##_reg_write_fw_domains
+
+#define MMIO_READ_FW_VFUNCS(x) \
+ MMIO_RAW_READ_VFUNCS(x),\
+ .read_fw_domains = x##_reg_read_fw_domains
static int __fw_domain_init(struct intel_uncore *uncore,
enum forcewake_domain_id domain_id,
@@ -2067,22 +2059,64 @@ void intel_uncore_init_early(struct intel_uncore
*uncore,
uncore->debug = >mmio_debug;
}
+static const struct intel_uncore_funcs vgpu_funcs = {
+ MMIO_RAW_WRITE_VFUNCS(vgpu),
+ MMIO_RAW_READ_VFUNCS(vgpu),
+};
+
+static const struct intel_uncore_funcs gen5_funcs = {
+ MMIO_RAW_WRITE_VFUNCS(gen5),
+ MMIO_RAW_READ_VFUNCS(gen5),
+};
+
+static const struct intel_uncore_funcs gen2_funcs = {
+ MMIO_RAW_WRITE_VFUNCS(gen2),
+ MMIO_RAW_READ_VFUNCS(gen2),
+};
+
static void uncore_raw_init(struct intel_uncore *uncore)
{
GEM_BUG_ON(intel_uncore_has_forcewake(uncore));
if (intel_vgpu_active(uncore->i915)) {
- ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, vgpu);
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, vgpu);
+ uncore->funcs = _funcs;
} else if (GRAPHICS_VER(uncore->i915) == 5) {
- ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen5);
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen5);
+ uncore->funcs = _funcs;
} else {
- ASSIGN_RAW_WRITE_MMIO_VFUNCS(uncore, gen2);
- ASSIGN_RAW_READ_MMIO_VFUNCS(uncore, gen2);
+ uncore->funcs = _funcs;
}
}
+static const struct intel_uncore_funcs gen12_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen12_fwtable),
+ MMIO_READ_FW_VFUNCS(gen11_fwtable)
+};
+
+static const struct intel_uncore_funcs gen11_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen11_fwtable),
+ MMIO_READ_FW_VFUNCS(gen11_fwtable)
+};
+
+static const struct intel_uncore_funcs fwtable_funcs = {
+ MMIO_WRITE_FW_VFUNCS(fwtable),
+ MMIO_READ_FW_VFUNCS(fwtable)
+};
+
+static const struct intel_uncore_funcs gen8_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen8),
+ MMIO_READ_FW_VFUNCS(gen6)
+};
+
+static const struct intel_uncore_funcs vlv_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen6),
+ MMIO_READ_FW_VFUNCS(fwtable)
+};
+
+static const struct intel_uncore_funcs gen6_funcs = {
+ MMIO_WRITE_FW_VFUNCS(gen6),
+ MMIO_READ_FW_VFUNCS(gen6)
+};
+
static int uncore_forcewake_init(struct intel_uncore *uncore)
{
struct drm_i915_private *i915 = uncore->i915;
@@ -2097,38 +2131,29 @@ static int uncore_forcewake_init(struct intel_uncore
*uncore)
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
ASSIGN_FW_DOMAINS_TABLE(uncore, __dg2_fw_ranges);
- ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen12_fwtable);
- ASSIGN_READ_MMIO_VFUNCS(uncore, gen11_fwtable);
+ uncore->funcs = _funcs;
} else if (GRAPHICS_VER_FULL(i915) >
[Intel-gfx] i915/uncore: constify the uncore vtables. (v2)
static const vtables are more secure than writeable function pointers. These two patches cleanup the uncore vtable to use static const tables. These are based on drm-tip, and should apply to the gt tree cleanly. Dave.
[Intel-gfx] [PATCH 1/2] drm/i915/uncore: split the fw get function into separate vfunc
From: Dave Airlie
constify it while here. drop the put function since it was never
overloaded and always has done the same thing, no point in
indirecting it for show.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/intel_uncore.c | 70 -
drivers/gpu/drm/i915/intel_uncore.h | 7 +--
2 files changed, 43 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index f9767054dbdf..8652e4221404 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -36,6 +36,12 @@
#define __raw_posting_read(...) ((void)__raw_uncore_read32(__VA_ARGS__))
+static void
+fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
+{
+ uncore->fw_get_funcs->force_wake_get(uncore, fw_domains);
+}
+
void
intel_uncore_mmio_debug_init_early(struct intel_uncore_mmio_debug *mmio_debug)
{
@@ -248,7 +254,7 @@ fw_domain_put(const struct intel_uncore_forcewake_domain *d)
}
static void
-fw_domains_get(struct intel_uncore *uncore, enum forcewake_domains fw_domains)
+fw_domains_get_normal(struct intel_uncore *uncore, enum forcewake_domains
fw_domains)
{
struct intel_uncore_forcewake_domain *d;
unsigned int tmp;
@@ -396,7 +402,7 @@ intel_uncore_fw_release_timer(struct hrtimer *timer)
GEM_BUG_ON(!domain->wake_count);
if (--domain->wake_count == 0)
- uncore->funcs.force_wake_put(uncore, domain->mask);
+ fw_domains_put(uncore, domain->mask);
spin_unlock_irqrestore(>lock, irqflags);
@@ -454,7 +460,7 @@ intel_uncore_forcewake_reset(struct intel_uncore *uncore)
fw = uncore->fw_domains_active;
if (fw)
- uncore->funcs.force_wake_put(uncore, fw);
+ fw_domains_put(uncore, fw);
fw_domains_reset(uncore, uncore->fw_domains);
assert_forcewakes_inactive(uncore);
@@ -562,7 +568,7 @@ static void forcewake_early_sanitize(struct intel_uncore
*uncore,
intel_uncore_forcewake_reset(uncore);
if (restore_forcewake) {
spin_lock_irq(>lock);
- uncore->funcs.force_wake_get(uncore, restore_forcewake);
+ fw_domains_get(uncore, restore_forcewake);
if (intel_uncore_has_fifo(uncore))
uncore->fifo_count = fifo_free_entries(uncore);
@@ -623,7 +629,7 @@ static void __intel_uncore_forcewake_get(struct
intel_uncore *uncore,
}
if (fw_domains)
- uncore->funcs.force_wake_get(uncore, fw_domains);
+ fw_domains_get(uncore, fw_domains);
}
/**
@@ -644,7 +650,7 @@ void intel_uncore_forcewake_get(struct intel_uncore *uncore,
{
unsigned long irqflags;
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
assert_rpm_wakelock_held(uncore->rpm);
@@ -711,7 +717,7 @@ void intel_uncore_forcewake_get__locked(struct intel_uncore
*uncore,
{
lockdep_assert_held(>lock);
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
__intel_uncore_forcewake_get(uncore, fw_domains);
@@ -733,7 +739,7 @@ static void __intel_uncore_forcewake_put(struct
intel_uncore *uncore,
continue;
}
- uncore->funcs.force_wake_put(uncore, domain->mask);
+ fw_domains_put(uncore, domain->mask);
}
}
@@ -750,7 +756,7 @@ void intel_uncore_forcewake_put(struct intel_uncore *uncore,
{
unsigned long irqflags;
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
spin_lock_irqsave(>lock, irqflags);
@@ -769,7 +775,7 @@ void intel_uncore_forcewake_flush(struct intel_uncore
*uncore,
struct intel_uncore_forcewake_domain *domain;
unsigned int tmp;
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
fw_domains &= uncore->fw_domains;
@@ -793,7 +799,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore
*uncore,
{
lockdep_assert_held(>lock);
- if (!uncore->funcs.force_wake_put)
+ if (!uncore->fw_get_funcs)
return;
__intel_uncore_forcewake_put(uncore, fw_domains);
@@ -801,7 +807,7 @@ void intel_uncore_forcewake_put__locked(struct intel_uncore
*uncore,
void assert_forcewakes_inactive(struct intel_uncore *uncore)
{
- if (!uncore->funcs.force_wake_get)
+ if (!uncore->fw_get_funcs)
return;
drm_WARN(>i915->drm, uncore->fw_domains_active,
@@ -818,7 +824,7 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
[Intel-gfx] [PATCH 23/23] drm/i915: constify display wm vtable
From: Dave Airlie
Use a nop table for the cases where CxSR doesn't init properly.
v2: use a nop table (Jani)
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 34 -
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 80 ++--
3 files changed, 75 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 8b9727d84435..502e9ac70de1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -162,16 +162,16 @@ static void intel_modeset_setup_hw_state(struct
drm_device *dev,
*/
static void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
- if (dev_priv->wm_disp.update_wm)
- dev_priv->wm_disp.update_wm(dev_priv);
+ if (dev_priv->wm_disp->update_wm)
+ dev_priv->wm_disp->update_wm(dev_priv);
}
static int intel_compute_pipe_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.compute_pipe_wm)
- return dev_priv->wm_disp.compute_pipe_wm(state, crtc);
+ if (dev_priv->wm_disp->compute_pipe_wm)
+ return dev_priv->wm_disp->compute_pipe_wm(state, crtc);
return 0;
}
@@ -180,10 +180,10 @@ static int intel_compute_intermediate_wm(struct
intel_atomic_state *state,
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
if (drm_WARN_ON(_priv->drm,
- !dev_priv->wm_disp.compute_pipe_wm))
+ !dev_priv->wm_disp->compute_pipe_wm))
return 0;
- if (dev_priv->wm_disp.compute_pipe_wm)
- return dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
+ if (dev_priv->wm_disp->compute_pipe_wm)
+ return dev_priv->wm_disp->compute_intermediate_wm(state, crtc);
return 0;
}
@@ -191,8 +191,8 @@ static bool intel_initial_watermarks(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.initial_watermarks) {
- dev_priv->wm_disp.initial_watermarks(state, crtc);
+ if (dev_priv->wm_disp->initial_watermarks) {
+ dev_priv->wm_disp->initial_watermarks(state, crtc);
return true;
}
return false;
@@ -202,23 +202,23 @@ static void intel_atomic_update_watermarks(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.atomic_update_watermarks)
- dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
+ if (dev_priv->wm_disp->atomic_update_watermarks)
+ dev_priv->wm_disp->atomic_update_watermarks(state, crtc);
}
static void intel_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.optimize_watermarks)
- dev_priv->wm_disp.optimize_watermarks(state, crtc);
+ if (dev_priv->wm_disp->optimize_watermarks)
+ dev_priv->wm_disp->optimize_watermarks(state, crtc);
}
static void intel_compute_global_watermarks(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->wm_disp.compute_global_watermarks)
- dev_priv->wm_disp.compute_global_watermarks(state);
+ if (dev_priv->wm_disp->compute_global_watermarks)
+ dev_priv->wm_disp->compute_global_watermarks(state);
}
/* returns HPLL frequency in kHz */
@@ -3735,7 +3735,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state
*state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
- if (!dev_priv->wm_disp.initial_watermarks)
+ if (!dev_priv->wm_disp->initial_watermarks)
intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
@@ -11409,7 +11409,7 @@ static void sanitize_watermarks(struct drm_i915_private
*dev_priv)
int i;
/* Only supported on platforms that use atomic watermark design */
- if (!dev_priv->wm_disp.optimize_watermarks)
+ if (!dev_priv->wm_disp->optimize_watermarks)
return;
state = dr
[Intel-gfx] [PATCH 22/23] drm/i915: constify clock gating init vtable.
From: Dave Airlie
I used a macro to avoid making any really silly mistakes here.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 78 +++--
2 files changed, 55 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5bbdd3b06e6d..fc7466bbc445 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -975,7 +975,7 @@ struct drm_i915_private {
struct workqueue_struct *flip_wq;
/* pm private clock gating functions */
- struct drm_i915_clock_gating_funcs clock_gating_funcs;
+ const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
/* pm display functions */
struct drm_i915_wm_disp_funcs wm_disp;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 826216a115fd..0a5c1e3c798b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating(struct drm_i915_private *dev_priv)
{
- dev_priv->clock_gating_funcs.init_clock_gating(dev_priv);
+ dev_priv->clock_gating_funcs->init_clock_gating(dev_priv);
}
void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7886,6 +7886,36 @@ static void nop_init_clock_gating(struct
drm_i915_private *dev_priv)
"No clock gating settings or workarounds applied.\n");
}
+#define CG_FUNCS(platform) \
+static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs
= { \
+ .init_clock_gating = platform##_init_clock_gating, \
+}
+
+CG_FUNCS(adlp);
+CG_FUNCS(dg1);
+CG_FUNCS(gen12lp);
+CG_FUNCS(icl);
+CG_FUNCS(cfl);
+CG_FUNCS(skl);
+CG_FUNCS(kbl);
+CG_FUNCS(bxt);
+CG_FUNCS(glk);
+CG_FUNCS(bdw);
+CG_FUNCS(chv);
+CG_FUNCS(hsw);
+CG_FUNCS(ivb);
+CG_FUNCS(vlv);
+CG_FUNCS(gen6);
+CG_FUNCS(ilk);
+CG_FUNCS(g4x);
+CG_FUNCS(i965gm);
+CG_FUNCS(i965g);
+CG_FUNCS(gen3);
+CG_FUNCS(i85x);
+CG_FUNCS(i830);
+CG_FUNCS(nop);
+#undef CG_FUNCS
+
/**
* intel_init_clock_gating_hooks - setup the clock gating hooks
* @dev_priv: device private
@@ -7898,52 +7928,52 @@ static void nop_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_ALDERLAKE_P(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
adlp_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_DG1(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
dg1_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 12)
- dev_priv->clock_gating_funcs.init_clock_gating =
gen12lp_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (GRAPHICS_VER(dev_priv) == 11)
- dev_priv->clock_gating_funcs.init_clock_gating =
icl_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
cfl_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_SKYLAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
skl_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_KABYLAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
kbl_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_BROXTON(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
bxt_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_GEMINILAKE(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
glk_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_BROADWELL(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
bdw_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
chv_init_clock_gating;
+ dev_priv->clock_gating_funcs = _clock_gating_funcs;
else if (IS_HASWELL(dev_priv))
- dev_priv->clock_gating_funcs.init_clock_gating =
hsw_init_clock_gating;
+ dev_priv->clock_gating_fun
[Intel-gfx] [PATCH 20/23] drm/i915: drop unused function ptr and comments.
From: Dave Airlie
There was some excess comments and an unused vtbl ptr.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_drv.h | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b2c63ed5b8fe..2e8e4db627e3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -409,13 +409,6 @@ struct drm_i915_display_funcs {
void (*crtc_disable)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*commit_modeset_enables)(struct intel_atomic_state *state);
- void (*commit_modeset_disables)(struct intel_atomic_state *state);
-
- /* clock updates for mode set */
- /* cursor updates */
- /* render clock increase/decrease */
- /* display clock increase/decrease */
- /* pll clock increase/decrease */
};
--
2.31.1
[Intel-gfx] [PATCH 21/23] drm/i915: constify display function vtable
From: Dave Airlie
Make nice clear tables instead of having things in two places.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 81
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 52 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 2e672b988343..8b9727d84435 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3789,7 +3789,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc
*crtc,
drm_WARN_ON(_priv->drm, IS_ERR(temp_crtc_state) || ret);
- dev_priv->display.crtc_disable(to_intel_atomic_state(state), crtc);
+ dev_priv->display->crtc_disable(to_intel_atomic_state(state), crtc);
drm_atomic_state_put(state);
@@ -5994,7 +5994,7 @@ static bool intel_crtc_get_pipe_config(struct
intel_crtc_state *crtc_state)
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
- if (!i915->display.get_pipe_config(crtc, crtc_state))
+ if (!i915->display->get_pipe_config(crtc, crtc_state))
return false;
crtc_state->hw.active = true;
@@ -9802,7 +9802,7 @@ static void intel_enable_crtc(struct intel_atomic_state
*state,
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display.crtc_enable(state, crtc);
+ dev_priv->display->crtc_enable(state, crtc);
if (new_crtc_state->bigjoiner_slave)
return;
@@ -9890,7 +9890,7 @@ static void intel_old_crtc_state_disables(struct
intel_atomic_state *state,
*/
intel_crtc_disable_pipe_crc(crtc);
- dev_priv->display.crtc_disable(state, crtc);
+ dev_priv->display->crtc_disable(state, crtc);
crtc->active = false;
intel_fbc_disable(crtc);
intel_disable_shared_dpll(old_crtc_state);
@@ -10269,7 +10269,7 @@ static void intel_atomic_commit_tail(struct
intel_atomic_state *state)
}
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
- dev_priv->display.commit_modeset_enables(state);
+ dev_priv->display->commit_modeset_enables(state);
if (state->modeset) {
intel_encoders_update_complete(state);
@@ -11272,6 +11272,46 @@ static const struct drm_mode_config_funcs
intel_mode_funcs = {
.atomic_state_free = intel_atomic_state_free,
};
+static const struct drm_i915_display_funcs skl_display_funcs = {
+ .get_pipe_config = hsw_get_pipe_config,
+ .crtc_enable = hsw_crtc_enable,
+ .crtc_disable = hsw_crtc_disable,
+ .commit_modeset_enables = skl_commit_modeset_enables,
+ .get_initial_plane_config = skl_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs ddi_display_funcs = {
+ .get_pipe_config = hsw_get_pipe_config,
+ .crtc_enable = hsw_crtc_enable,
+ .crtc_disable = hsw_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs pch_split_display_funcs = {
+ .get_pipe_config = ilk_get_pipe_config,
+ .crtc_enable = ilk_crtc_enable,
+ .crtc_disable = ilk_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs vlv_display_funcs = {
+ .get_pipe_config = i9xx_get_pipe_config,
+ .crtc_enable = valleyview_crtc_enable,
+ .crtc_disable = i9xx_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
+static const struct drm_i915_display_funcs i9xx_display_funcs = {
+ .get_pipe_config = i9xx_get_pipe_config,
+ .crtc_enable = i9xx_crtc_enable,
+ .crtc_disable = i9xx_crtc_disable,
+ .commit_modeset_enables = intel_commit_modeset_enables,
+ .get_initial_plane_config = i9xx_get_initial_plane_config,
+};
+
/**
* intel_init_display_hooks - initialize the display modesetting hooks
* @dev_priv: device private
@@ -11287,38 +11327,19 @@ void intel_init_display_hooks(struct drm_i915_private
*dev_priv)
intel_dpll_init_clock_hook(dev_priv);
if (DISPLAY_VER(dev_priv) >= 9) {
- dev_priv->display.get_pipe_config = hsw_get_pipe_config;
- dev_priv->display.crtc_enable = hsw_crtc_enable;
- dev_priv->display.crtc_disable = hsw_crtc_disable;
+ dev_priv->display = _display_funcs;
} else if (HAS_DDI(dev_priv)) {
- dev_priv->display.get_pipe_config =
[Intel-gfx] [PATCH 19/23] drm/i915: constify the cdclk vtable
From: Dave Airlie
This is a bit of a twisty one since each platform is slightly
different, so might take some more review care.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 300 ++---
drivers/gpu/drm/i915/i915_drv.h| 2 +-
2 files changed, 206 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 27a4a226aa49..f501c748458e 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -62,32 +62,32 @@
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
- dev_priv->cdclk_funcs.get_cdclk(dev_priv, cdclk_config);
+ dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config);
}
int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- return dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
+ return dev_priv->cdclk_funcs->bw_calc_min_cdclk(state);
}
static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
+ dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe);
}
static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state
*cdclk_config)
{
- return dev_priv->cdclk_funcs.modeset_calc_cdclk(cdclk_config);
+ return dev_priv->cdclk_funcs->modeset_calc_cdclk(cdclk_config);
}
static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
int cdclk)
{
- return dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
+ return dev_priv->cdclk_funcs->calc_voltage_level(cdclk);
}
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
if (!intel_cdclk_changed(_priv->cdclk.hw, cdclk_config))
return;
- if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
+ if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs->set_cdclk))
return;
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -2886,6 +2886,157 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
return freq;
}
+static struct intel_cdclk_funcs tgl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = tgl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs ehl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = ehl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs icl_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = icl_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs bxt_cdclk_funcs = {
+ .get_cdclk = bxt_get_cdclk,
+ .set_cdclk = bxt_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
+ .calc_voltage_level = bxt_calc_voltage_level,
+};
+
+static struct intel_cdclk_funcs skl_cdclk_funcs = {
+ .get_cdclk = skl_get_cdclk,
+ .set_cdclk = skl_set_cdclk,
+ .bw_calc_min_cdclk = skl_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = skl_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs bdw_cdclk_funcs = {
+ .get_cdclk = bdw_get_cdclk,
+ .set_cdclk = bdw_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = bdw_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs chv_cdclk_funcs = {
+ .get_cdclk = vlv_get_cdclk,
+ .set_cdclk = chv_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs vlv_cdclk_funcs = {
+ .get_cdclk = vlv_get_cdclk,
+ .set_cdclk = vlv_set_cdclk,
+ .bw_calc_min_cdclk = intel_bw_calc_min_cdclk,
+ .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
+};
+
+static struct intel_cdclk_funcs hsw_cdclk_funcs = {
+ .get_cdclk = hsw_get_cdclk,
+
[Intel-gfx] [PATCH 17/23] drm/i915: constify the audio function vtable
From: Dave Airlie
Move the functions into read-only tables.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_audio.c | 43 ++
drivers/gpu/drm/i915/i915_drv.h| 2 +-
2 files changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index f539826c0424..0a6ad74d9173 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -848,10 +848,10 @@ void intel_audio_codec_enable(struct intel_encoder
*encoder,
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
- if (dev_priv->audio_funcs.audio_codec_enable)
- dev_priv->audio_funcs.audio_codec_enable(encoder,
-crtc_state,
-conn_state);
+ if (dev_priv->audio_funcs)
+ dev_priv->audio_funcs->audio_codec_enable(encoder,
+ crtc_state,
+ conn_state);
mutex_lock(_priv->av_mutex);
encoder->audio_connector = connector;
@@ -893,10 +893,10 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
- if (dev_priv->audio_funcs.audio_codec_disable)
- dev_priv->audio_funcs.audio_codec_disable(encoder,
- old_crtc_state,
- old_conn_state);
+ if (dev_priv->audio_funcs)
+ dev_priv->audio_funcs->audio_codec_disable(encoder,
+ old_crtc_state,
+ old_conn_state);
mutex_lock(_priv->av_mutex);
encoder->audio_connector = NULL;
@@ -915,6 +915,21 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
}
+static const struct intel_audio_funcs g4x_audio_funcs = {
+ .audio_codec_enable = g4x_audio_codec_enable,
+ .audio_codec_disable = g4x_audio_codec_disable,
+};
+
+static const struct intel_audio_funcs ilk_audio_funcs = {
+ .audio_codec_enable = ilk_audio_codec_enable,
+ .audio_codec_disable = ilk_audio_codec_disable,
+};
+
+static const struct intel_audio_funcs hsw_audio_funcs = {
+ .audio_codec_enable = hsw_audio_codec_enable,
+ .audio_codec_disable = hsw_audio_codec_disable,
+};
+
/**
* intel_init_audio_hooks - Set up chip specific audio hooks
* @dev_priv: device private
@@ -922,17 +937,13 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
{
if (IS_G4X(dev_priv)) {
- dev_priv->audio_funcs.audio_codec_enable =
g4x_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable =
g4x_audio_codec_disable;
+ dev_priv->audio_funcs = _audio_funcs;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- dev_priv->audio_funcs.audio_codec_enable =
ilk_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable =
ilk_audio_codec_disable;
+ dev_priv->audio_funcs = _audio_funcs;
} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->audio_funcs.audio_codec_enable =
hsw_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable =
hsw_audio_codec_disable;
+ dev_priv->audio_funcs = _audio_funcs;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->audio_funcs.audio_codec_enable =
ilk_audio_codec_enable;
- dev_priv->audio_funcs.audio_codec_disable =
ilk_audio_codec_disable;
+ dev_priv->audio_funcs = _audio_funcs;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 28cd816549b8..95f7a7a19a58 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1003,7 +1003,7 @@ struct drm_i915_private {
const struct intel_color_funcs *color_funcs;
/* Display internal audio functions */
- struct intel_audio_funcs audio_funcs;
+ const struct intel_audio_funcs *audio_funcs;
/* Display CDCLK functions */
struct intel_cdclk_funcs cdclk_funcs;
--
2.31.1
[Intel-gfx] [PATCH 18/23] drm/i915: constify the dpll clock vtable
From: Dave Airlie
Most the dpll vtable into read-only memory.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +--
drivers/gpu/drm/i915/display/intel_dpll.c| 48
drivers/gpu/drm/i915/i915_drv.h | 2 +-
3 files changed, 44 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 02a9e684c86b..2e672b988343 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6821,10 +6821,10 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
crtc_state->update_wm_post = true;
if (mode_changed && crtc_state->hw.enable &&
- dev_priv->dpll_funcs.crtc_compute_clock &&
+ dev_priv->dpll_funcs &&
!crtc_state->bigjoiner_slave &&
!drm_WARN_ON(_priv->drm, crtc_state->shared_dpll)) {
- ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
+ ret = dev_priv->dpll_funcs->crtc_compute_clock(crtc_state);
if (ret)
return ret;
}
@@ -8851,7 +8851,7 @@ static void intel_modeset_clear_plls(struct
intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
- if (!dev_priv->dpll_funcs.crtc_compute_clock)
+ if (!dev_priv->dpll_funcs)
return;
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 9326c7cbb05c..231b337df166 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1363,25 +1363,57 @@ static int i8xx_crtc_compute_clock(struct
intel_crtc_state *crtc_state)
return 0;
}
+static const struct intel_dpll_funcs hsw_dpll_funcs = {
+ .crtc_compute_clock = hsw_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs ilk_dpll_funcs = {
+ .crtc_compute_clock = ilk_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs chv_dpll_funcs = {
+ .crtc_compute_clock = chv_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs vlv_dpll_funcs = {
+ .crtc_compute_clock = vlv_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs g4x_dpll_funcs = {
+ .crtc_compute_clock = g4x_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs pnv_dpll_funcs = {
+ .crtc_compute_clock = pnv_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs i9xx_dpll_funcs = {
+ .crtc_compute_clock = i9xx_crtc_compute_clock,
+};
+
+static const struct intel_dpll_funcs i8xx_dpll_funcs = {
+ .crtc_compute_clock = i8xx_crtc_compute_clock,
+};
+
void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
hsw_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (HAS_PCH_SPLIT(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
ilk_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
chv_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
vlv_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_G4X(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
g4x_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->dpll_funcs.crtc_compute_clock =
pnv_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else if (DISPLAY_VER(dev_priv) != 2)
- dev_priv->dpll_funcs.crtc_compute_clock =
i9xx_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
else
- dev_priv->dpll_funcs.crtc_compute_clock =
i8xx_crtc_compute_clock;
+ dev_priv->dpll_funcs = _dpll_funcs;
}
static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 95f7a7a19a58..5ed624b9c3cc 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -994,7 +994,7 @@ struct drm_i915_private {
const struct intel_fdi_funcs *fdi_funcs;
/* display pll funcs */
- struct intel_dpll_funcs dpll_funcs;
+ const struct intel_dpll_funcs *dpll_funcs;
/* Display functions */
struct drm_i915_display_funcs display;
--
2.31.1
[Intel-gfx] [PATCH 16/23] drm/i915: constify color function vtable.
From: Dave Airlie
This clarifies quite well what functions get used on what platforms
instead of having to decipher the old tree.
v2: fixed IVB mistake (Jani)
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_color.c | 138 ++---
drivers/gpu/drm/i915/i915_drv.h| 2 +-
2 files changed, 93 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index ed79075158dd..f5923f1c38bd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct
intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->color_funcs.load_luts(crtc_state);
+ dev_priv->color_funcs->load_luts(crtc_state);
}
void intel_color_commit(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->color_funcs.color_commit(crtc_state);
+ dev_priv->color_funcs->color_commit(crtc_state);
}
static bool intel_can_preload_luts(const struct intel_crtc_state
*new_crtc_state)
@@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- return dev_priv->color_funcs.color_check(crtc_state);
+ return dev_priv->color_funcs->color_check(crtc_state);
}
void intel_color_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (dev_priv->color_funcs.read_luts)
- dev_priv->color_funcs.read_luts(crtc_state);
+ if (dev_priv->color_funcs->read_luts)
+ dev_priv->color_funcs->read_luts(crtc_state);
}
static bool need_plane_update(struct intel_plane *plane,
@@ -2092,6 +2092,76 @@ static void icl_read_luts(struct intel_crtc_state
*crtc_state)
}
}
+static const struct intel_color_funcs chv_color_funcs = {
+ .color_check = chv_color_check,
+ .color_commit = i9xx_color_commit,
+ .load_luts = chv_load_luts,
+ .read_luts = chv_read_luts,
+};
+
+static const struct intel_color_funcs i965_color_funcs = {
+ .color_check = i9xx_color_check,
+ .color_commit = i9xx_color_commit,
+ .load_luts = i965_load_luts,
+ .read_luts = i965_read_luts,
+};
+
+static const struct intel_color_funcs i9xx_color_funcs = {
+ .color_check = i9xx_color_check,
+ .color_commit = i9xx_color_commit,
+ .load_luts = i9xx_load_luts,
+ .read_luts = i9xx_read_luts,
+};
+
+static const struct intel_color_funcs icl_color_funcs = {
+ .color_check = icl_color_check,
+ .color_commit = skl_color_commit,
+ .load_luts = icl_load_luts,
+ .read_luts = icl_read_luts,
+};
+
+static const struct intel_color_funcs glk_color_funcs = {
+ .color_check = glk_color_check,
+ .color_commit = skl_color_commit,
+ .load_luts = glk_load_luts,
+ .read_luts = glk_read_luts,
+};
+
+static const struct intel_color_funcs skl_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = skl_color_commit,
+ .load_luts = bdw_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs bdw_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = hsw_color_commit,
+ .load_luts = bdw_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs hsw_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = hsw_color_commit,
+ .load_luts = ivb_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs ivb_color_funcs = {
+ .color_check = ivb_color_check,
+ .color_commit = ilk_color_commit,
+ .load_luts = ivb_load_luts,
+ .read_luts = NULL,
+};
+
+static const struct intel_color_funcs ilk_color_funcs = {
+ .color_check = ilk_color_check,
+ .color_commit = ilk_color_commit,
+ .load_luts = ilk_load_luts,
+ .read_luts = ilk_read_luts,
+};
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -2101,52 +2171,28 @@ void intel_color_init(struct intel_crtc *crtc)
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->color_funcs.color_check = chv_color_check;
- dev_priv->color_funcs.color_commit = i9xx_color_commit;
- dev_priv->color_funcs.load_luts = chv_load_luts;
- dev_priv->color_funcs.read_luts = chv_read_luts;
+ dev_pri
[Intel-gfx] [PATCH 14/23] drm/i915: constify fdi link training vtable
From: Dave Airlie
Put the vtable into ro memory.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fdi.c | 20
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index 94bb7e039fe7..148fb50035ff 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -15,7 +15,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
+ dev_priv->fdi_funcs->fdi_link_train(crtc, crtc_state);
}
/* units of 100MHz */
@@ -1013,15 +1013,27 @@ void lpt_fdi_program_mphy(struct drm_i915_private
*dev_priv)
intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
}
+static const struct intel_fdi_funcs ilk_funcs = {
+ .fdi_link_train = ilk_fdi_link_train,
+};
+
+static const struct intel_fdi_funcs gen6_funcs = {
+ .fdi_link_train = gen6_fdi_link_train,
+};
+
+static const struct intel_fdi_funcs ivb_funcs = {
+ .fdi_link_train = ivb_manual_fdi_link_train,
+};
+
void
intel_fdi_init_hook(struct drm_i915_private *dev_priv)
{
if (IS_IRONLAKE(dev_priv)) {
- dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
+ dev_priv->fdi_funcs = _funcs;
} else if (IS_SANDYBRIDGE(dev_priv)) {
- dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
+ dev_priv->fdi_funcs = _funcs;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
- dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
+ dev_priv->fdi_funcs = _funcs;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 575c46df5336..bb44ef4f6356 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -991,7 +991,7 @@ struct drm_i915_private {
struct intel_hotplug_funcs hotplug_funcs;
/* fdi display functions */
- struct intel_fdi_funcs fdi_funcs;
+ const struct intel_fdi_funcs *fdi_funcs;
/* display pll funcs */
struct intel_dpll_funcs dpll_funcs;
--
2.31.1
[Intel-gfx] [PATCH 15/23] drm/i915: constify hotplug function vtable.
From: Dave Airlie
Use a macro to avoid mistakes, this type of macro is only used
in a couple of places.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 4 +--
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 28 +++-
3 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 05f76aba4f8a..3c1cec953b42 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct
drm_i915_private *dev_priv)
static void intel_hpd_irq_setup(struct drm_i915_private *i915)
{
- if (i915->display_irqs_enabled && i915->hotplug_funcs.hpd_irq_setup)
- i915->hotplug_funcs.hpd_irq_setup(i915);
+ if (i915->display_irqs_enabled && i915->hotplug_funcs->hpd_irq_setup)
+ i915->hotplug_funcs->hpd_irq_setup(i915);
}
static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bb44ef4f6356..af1960856f19 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -988,7 +988,7 @@ struct drm_i915_private {
struct drm_i915_wm_disp_funcs wm_disp;
/* irq display functions */
- struct intel_hotplug_funcs hotplug_funcs;
+ const struct intel_hotplug_funcs *hotplug_funcs;
/* fdi display functions */
const struct intel_fdi_funcs *fdi_funcs;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index c35065f8f429..77680bca46ee 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4345,6 +4345,20 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
return ret;
}
+#define HPD_FUNCS(platform) \
+static const struct intel_hotplug_funcs platform##_hpd_funcs = { \
+ .hpd_irq_setup = platform##_hpd_irq_setup, \
+}
+
+HPD_FUNCS(i915);
+HPD_FUNCS(dg1);
+HPD_FUNCS(gen11);
+HPD_FUNCS(bxt);
+HPD_FUNCS(icp);
+HPD_FUNCS(spt);
+HPD_FUNCS(ilk);
+#undef HPD_FUNCS
+
/**
* intel_irq_init - initializes irq support
* @dev_priv: i915 device instance
@@ -4395,20 +4409,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
- dev_priv->hotplug_funcs.hpd_irq_setup =
i915_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
} else {
if (HAS_PCH_DG1(dev_priv))
- dev_priv->hotplug_funcs.hpd_irq_setup =
dg1_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->hotplug_funcs.hpd_irq_setup =
gen11_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->hotplug_funcs.hpd_irq_setup =
bxt_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- dev_priv->hotplug_funcs.hpd_irq_setup =
icp_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- dev_priv->hotplug_funcs.hpd_irq_setup =
spt_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
else
- dev_priv->hotplug_funcs.hpd_irq_setup =
ilk_hpd_irq_setup;
+ dev_priv->hotplug_funcs = _hpd_funcs;
}
}
--
2.31.1
[Intel-gfx] [PATCH 13/23] drm/i915: split the dpll clock compute out from display vtable.
From: Dave Airlie
this single function might be possible to merge later, but
for now it's simple to just split it out.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dpll.c| 16
drivers/gpu/drm/i915/i915_drv.h | 8 +++-
3 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 413bc4667e47..02a9e684c86b 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6821,10 +6821,10 @@ static int intel_crtc_atomic_check(struct
intel_atomic_state *state,
crtc_state->update_wm_post = true;
if (mode_changed && crtc_state->hw.enable &&
- dev_priv->display.crtc_compute_clock &&
+ dev_priv->dpll_funcs.crtc_compute_clock &&
!crtc_state->bigjoiner_slave &&
!drm_WARN_ON(_priv->drm, crtc_state->shared_dpll)) {
- ret = dev_priv->display.crtc_compute_clock(crtc_state);
+ ret = dev_priv->dpll_funcs.crtc_compute_clock(crtc_state);
if (ret)
return ret;
}
@@ -8851,7 +8851,7 @@ static void intel_modeset_clear_plls(struct
intel_atomic_state *state)
struct intel_crtc *crtc;
int i;
- if (!dev_priv->display.crtc_compute_clock)
+ if (!dev_priv->dpll_funcs.crtc_compute_clock)
return;
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c
b/drivers/gpu/drm/i915/display/intel_dpll.c
index 210f91f4a576..9326c7cbb05c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1367,21 +1367,21 @@ void
intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv)
{
if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv))
- dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
hsw_crtc_compute_clock;
else if (HAS_PCH_SPLIT(dev_priv))
- dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
ilk_crtc_compute_clock;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
chv_crtc_compute_clock;
else if (IS_VALLEYVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
vlv_crtc_compute_clock;
else if (IS_G4X(dev_priv))
- dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
g4x_crtc_compute_clock;
else if (IS_PINEVIEW(dev_priv))
- dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
pnv_crtc_compute_clock;
else if (DISPLAY_VER(dev_priv) != 2)
- dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
i9xx_crtc_compute_clock;
else
- dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
+ dev_priv->dpll_funcs.crtc_compute_clock =
i8xx_crtc_compute_clock;
}
static bool i9xx_has_pps(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 680301bce3ab..575c46df5336 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -393,6 +393,10 @@ struct intel_fdi_funcs {
const struct intel_crtc_state *crtc_state);
};
+struct intel_dpll_funcs {
+ int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
+};
+
struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -400,7 +404,6 @@ struct drm_i915_display_funcs {
struct intel_crtc_state *);
void (*get_initial_plane_config)(struct intel_crtc *,
struct intel_initial_plane_config *);
- int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state);
void (*crtc_enable)(struct intel_atomic_state *state,
struct intel_crtc *crtc);
void (*crtc_disable)(struct intel_atomic_state *state,
@@ -990,6 +993,9 @@ struct drm_i915_private {
/* fdi display functions */
struct i
[Intel-gfx] [PATCH 12/23] drm/i915: split fdi link training from display vtable.
From: Dave Airlie
It may make sense to merge this with display again later,
however the fdi use of the vtable is limited to only a
few generations.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_fdi.c | 8
drivers/gpu/drm/i915/i915_drv.h | 11 ---
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
b/drivers/gpu/drm/i915/display/intel_fdi.c
index 339243399a65..94bb7e039fe7 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -15,7 +15,7 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- dev_priv->display.fdi_link_train(crtc, crtc_state);
+ dev_priv->fdi_funcs.fdi_link_train(crtc, crtc_state);
}
/* units of 100MHz */
@@ -1017,11 +1017,11 @@ void
intel_fdi_init_hook(struct drm_i915_private *dev_priv)
{
if (IS_IRONLAKE(dev_priv)) {
- dev_priv->display.fdi_link_train = ilk_fdi_link_train;
+ dev_priv->fdi_funcs.fdi_link_train = ilk_fdi_link_train;
} else if (IS_SANDYBRIDGE(dev_priv)) {
- dev_priv->display.fdi_link_train = gen6_fdi_link_train;
+ dev_priv->fdi_funcs.fdi_link_train = gen6_fdi_link_train;
} else if (IS_IVYBRIDGE(dev_priv)) {
/* FIXME: detect B0+ stepping and use auto training */
- dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
+ dev_priv->fdi_funcs.fdi_link_train = ivb_manual_fdi_link_train;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index caf854d251a6..680301bce3ab 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -388,6 +388,11 @@ struct intel_hotplug_funcs {
void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
};
+struct intel_fdi_funcs {
+ void (*fdi_link_train)(struct intel_crtc *crtc,
+ const struct intel_crtc_state *crtc_state);
+};
+
struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -403,9 +408,6 @@ struct drm_i915_display_funcs {
void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*commit_modeset_disables)(struct intel_atomic_state *state);
- void (*fdi_link_train)(struct intel_crtc *crtc,
- const struct intel_crtc_state *crtc_state);
-
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
@@ -985,6 +987,9 @@ struct drm_i915_private {
/* irq display functions */
struct intel_hotplug_funcs hotplug_funcs;
+ /* fdi display functions */
+ struct intel_fdi_funcs fdi_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
--
2.31.1
[Intel-gfx] [PATCH 10/23] drm/i915: split cdclk functions from display vtable.
From: Dave Airlie
This moves all the cdclk related functions into their own vtable.
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 142 ++---
drivers/gpu/drm/i915/i915_drv.h| 8 +-
2 files changed, 78 insertions(+), 72 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0e09f259914f..27a4a226aa49 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -62,32 +62,32 @@
void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config)
{
- dev_priv->display.get_cdclk(dev_priv, cdclk_config);
+ dev_priv->cdclk_funcs.get_cdclk(dev_priv, cdclk_config);
}
int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- return dev_priv->display.bw_calc_min_cdclk(state);
+ return dev_priv->cdclk_funcs.bw_calc_min_cdclk(state);
}
static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
const struct intel_cdclk_config *cdclk_config,
enum pipe pipe)
{
- dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
+ dev_priv->cdclk_funcs.set_cdclk(dev_priv, cdclk_config, pipe);
}
static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
struct intel_cdclk_state
*cdclk_config)
{
- return dev_priv->display.modeset_calc_cdclk(cdclk_config);
+ return dev_priv->cdclk_funcs.modeset_calc_cdclk(cdclk_config);
}
static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
int cdclk)
{
- return dev_priv->display.calc_voltage_level(cdclk);
+ return dev_priv->cdclk_funcs.calc_voltage_level(cdclk);
}
static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
@@ -1963,7 +1963,7 @@ static void intel_set_cdclk(struct drm_i915_private
*dev_priv,
if (!intel_cdclk_changed(_priv->cdclk.hw, cdclk_config))
return;
- if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->display.set_cdclk))
+ if (drm_WARN_ON_ONCE(_priv->drm, !dev_priv->cdclk_funcs.set_cdclk))
return;
intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
@@ -2893,119 +2893,119 @@ u32 intel_read_rawclk(struct drm_i915_private
*dev_priv)
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
if (IS_DG2(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk =
bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level =
tgl_calc_voltage_level;
dev_priv->cdclk.table = dg2_cdclk_table;
} else if (IS_ALDERLAKE_P(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk =
bxt_modeset_calc_cdclk;
+ dev_priv->cdclk_funcs.calc_voltage_level =
tgl_calc_voltage_level;
/* Wa_22011320316:adl-p[a0] */
if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
dev_priv->cdclk.table = adlp_a_step_cdclk_table;
else
dev_priv->cdclk.table = adlp_cdclk_table;
} else if (IS_ROCKETLAKE(dev_priv)) {
- dev_priv->display.set_cdclk = bxt_set_cdclk;
- dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
- dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
- dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
+ dev_priv->cdclk_funcs.set_cdclk = bxt_set_cdclk;
+ dev_priv->cdclk_funcs.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
+ dev_priv->cdclk_funcs.modeset_calc_cdclk
[Intel-gfx] [PATCH 11/23] drm/i915: split irq hotplug function from display vtable
From: Dave Airlie
This provide a service from irq to display, so make it separate
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_hotplug.c | 4 ++--
drivers/gpu/drm/i915/i915_drv.h | 9 -
drivers/gpu/drm/i915/i915_irq.c | 14 +++---
3 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug.c
b/drivers/gpu/drm/i915/display/intel_hotplug.c
index 47c85ac97c87..05f76aba4f8a 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug.c
@@ -215,8 +215,8 @@ intel_hpd_irq_storm_switch_to_polling(struct
drm_i915_private *dev_priv)
static void intel_hpd_irq_setup(struct drm_i915_private *i915)
{
- if (i915->display_irqs_enabled && i915->display.hpd_irq_setup)
- i915->display.hpd_irq_setup(i915);
+ if (i915->display_irqs_enabled && i915->hotplug_funcs.hpd_irq_setup)
+ i915->hotplug_funcs.hpd_irq_setup(i915);
}
static void intel_hpd_irq_storm_reenable_work(struct work_struct *work)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 11298f583cc0..caf854d251a6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -384,6 +384,10 @@ struct intel_cdclk_funcs {
u8 (*calc_voltage_level)(int cdclk);
};
+struct intel_hotplug_funcs {
+ void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
+};
+
struct drm_i915_display_funcs {
/* Returns the active state of the crtc, and if the crtc is active,
* fills out the pipe-config with the hw state. */
@@ -401,7 +405,7 @@ struct drm_i915_display_funcs {
void (*fdi_link_train)(struct intel_crtc *crtc,
const struct intel_crtc_state *crtc_state);
- void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
+
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
@@ -978,6 +982,9 @@ struct drm_i915_private {
/* pm display functions */
struct drm_i915_wm_disp_funcs wm_disp;
+ /* irq display functions */
+ struct intel_hotplug_funcs hotplug_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0a1681384c84..c35065f8f429 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4395,20 +4395,20 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
if (HAS_GMCH(dev_priv)) {
if (I915_HAS_HOTPLUG(dev_priv))
- dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
i915_hpd_irq_setup;
} else {
if (HAS_PCH_DG1(dev_priv))
- dev_priv->display.hpd_irq_setup = dg1_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
dg1_hpd_irq_setup;
else if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
gen11_hpd_irq_setup;
else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
bxt_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- dev_priv->display.hpd_irq_setup = icp_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
icp_hpd_irq_setup;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
spt_hpd_irq_setup;
else
- dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
+ dev_priv->hotplug_funcs.hpd_irq_setup =
ilk_hpd_irq_setup;
}
}
--
2.31.1
[Intel-gfx] [PATCH 09/23] drm/i915: split audio functions from display vtable
From: Dave Airlie
These are only used internally in the audio code
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_audio.c | 24 +++---
drivers/gpu/drm/i915/i915_drv.h| 19 +++--
2 files changed, 25 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 532237588511..f539826c0424 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -848,8 +848,8 @@ void intel_audio_codec_enable(struct intel_encoder *encoder,
connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
- if (dev_priv->display.audio_codec_enable)
- dev_priv->display.audio_codec_enable(encoder,
+ if (dev_priv->audio_funcs.audio_codec_enable)
+ dev_priv->audio_funcs.audio_codec_enable(encoder,
crtc_state,
conn_state);
@@ -893,8 +893,8 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
enum port port = encoder->port;
enum pipe pipe = crtc->pipe;
- if (dev_priv->display.audio_codec_disable)
- dev_priv->display.audio_codec_disable(encoder,
+ if (dev_priv->audio_funcs.audio_codec_disable)
+ dev_priv->audio_funcs.audio_codec_disable(encoder,
old_crtc_state,
old_conn_state);
@@ -922,17 +922,17 @@ void intel_audio_codec_disable(struct intel_encoder
*encoder,
void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
{
if (IS_G4X(dev_priv)) {
- dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
- dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable =
g4x_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable =
g4x_audio_codec_disable;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
- dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable =
ilk_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable =
ilk_audio_codec_disable;
} else if (IS_HASWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 8) {
- dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
- dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable =
hsw_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable =
hsw_audio_codec_disable;
} else if (HAS_PCH_SPLIT(dev_priv)) {
- dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
- dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
+ dev_priv->audio_funcs.audio_codec_enable =
ilk_audio_codec_enable;
+ dev_priv->audio_funcs.audio_codec_disable =
ilk_audio_codec_disable;
}
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8930bf2db226..1ba94dee683e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -364,6 +364,15 @@ struct intel_color_funcs {
void (*read_luts)(struct intel_crtc_state *crtc_state);
};
+struct intel_audio_funcs {
+ void (*audio_codec_enable)(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ const struct drm_connector_state
*conn_state);
+ void (*audio_codec_disable)(struct intel_encoder *encoder,
+ const struct intel_crtc_state
*old_crtc_state,
+ const struct drm_connector_state
*old_conn_state);
+};
+
struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config);
@@ -386,12 +395,7 @@ struct drm_i915_display_funcs {
struct intel_crtc *crtc);
void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*commit_modeset_disables)(struct intel_atomic_state *state);
- void (*audio_codec_enable)(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state,
- const struct drm_connector_state
*conn_state);
- void (*audio_codec_disable)(struct intel_encoder *encoder,
- const struct
[Intel-gfx] [PATCH 08/23] drm/i915: split color functions from display vtable
From: Dave Airlie
These are only used internally in the color module
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_color.c | 64 +++---
drivers/gpu/drm/i915/i915_drv.h| 39 +++--
2 files changed, 54 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index afcb4bf3826c..ed79075158dd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1137,14 +1137,14 @@ void intel_color_load_luts(const struct
intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->display.load_luts(crtc_state);
+ dev_priv->color_funcs.load_luts(crtc_state);
}
void intel_color_commit(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- dev_priv->display.color_commit(crtc_state);
+ dev_priv->color_funcs.color_commit(crtc_state);
}
static bool intel_can_preload_luts(const struct intel_crtc_state
*new_crtc_state)
@@ -1200,15 +1200,15 @@ int intel_color_check(struct intel_crtc_state
*crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- return dev_priv->display.color_check(crtc_state);
+ return dev_priv->color_funcs.color_check(crtc_state);
}
void intel_color_get_config(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- if (dev_priv->display.read_luts)
- dev_priv->display.read_luts(crtc_state);
+ if (dev_priv->color_funcs.read_luts)
+ dev_priv->color_funcs.read_luts(crtc_state);
}
static bool need_plane_update(struct intel_plane *plane,
@@ -2101,51 +2101,51 @@ void intel_color_init(struct intel_crtc *crtc)
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv)) {
- dev_priv->display.color_check = chv_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = chv_load_luts;
- dev_priv->display.read_luts = chv_read_luts;
+ dev_priv->color_funcs.color_check = chv_color_check;
+ dev_priv->color_funcs.color_commit = i9xx_color_commit;
+ dev_priv->color_funcs.load_luts = chv_load_luts;
+ dev_priv->color_funcs.read_luts = chv_read_luts;
} else if (DISPLAY_VER(dev_priv) >= 4) {
- dev_priv->display.color_check = i9xx_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = i965_load_luts;
- dev_priv->display.read_luts = i965_read_luts;
+ dev_priv->color_funcs.color_check = i9xx_color_check;
+ dev_priv->color_funcs.color_commit = i9xx_color_commit;
+ dev_priv->color_funcs.load_luts = i965_load_luts;
+ dev_priv->color_funcs.read_luts = i965_read_luts;
} else {
- dev_priv->display.color_check = i9xx_color_check;
- dev_priv->display.color_commit = i9xx_color_commit;
- dev_priv->display.load_luts = i9xx_load_luts;
- dev_priv->display.read_luts = i9xx_read_luts;
+ dev_priv->color_funcs.color_check = i9xx_color_check;
+ dev_priv->color_funcs.color_commit = i9xx_color_commit;
+ dev_priv->color_funcs.load_luts = i9xx_load_luts;
+ dev_priv->color_funcs.read_luts = i9xx_read_luts;
}
} else {
if (DISPLAY_VER(dev_priv) >= 11)
- dev_priv->display.color_check = icl_color_check;
+ dev_priv->color_funcs.color_check = icl_color_check;
else if (DISPLAY_VER(dev_priv) >= 10)
- dev_priv->display.color_check = glk_color_check;
+ dev_priv->color_funcs.color_check = glk_color_check;
else if (DISPLAY_VER(dev_priv) >= 7)
- dev_priv->display.color_check = ivb_color_check;
+ dev_priv->color_funcs.color_check = ivb_color_check;
else
- dev_priv->display.color_check = ilk_color_check;
+ dev_priv->color_funcs.color_check = ilk_color_check;
if (DISPLAY_VER(dev_priv) >= 9)
- dev_priv-&g
[Intel-gfx] [PATCH 06/23] drm/i915: split clock gating init from display vtable
From: Dave Airlie
This function is only used inside intel_pm.c
Reviewed-by: Jani Nikula
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/i915_drv.h | 9 ++-
drivers/gpu/drm/i915/intel_pm.c | 48 -
2 files changed, 32 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 894c883044ee..48d30b967def 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -323,6 +323,11 @@ struct intel_crtc;
struct intel_limit;
struct dpll;
+/* functions used internal in intel_pm.c */
+struct drm_i915_clock_gating_funcs {
+ void (*init_clock_gating)(struct drm_i915_private *dev_priv);
+};
+
struct drm_i915_display_funcs {
void (*get_cdclk)(struct drm_i915_private *dev_priv,
struct intel_cdclk_config *cdclk_config);
@@ -365,7 +370,6 @@ struct drm_i915_display_funcs {
const struct drm_connector_state
*old_conn_state);
void (*fdi_link_train)(struct intel_crtc *crtc,
const struct intel_crtc_state *crtc_state);
- void (*init_clock_gating)(struct drm_i915_private *dev_priv);
void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
/* clock updates for mode set */
/* cursor updates */
@@ -954,6 +958,9 @@ struct drm_i915_private {
/* unbound hipri wq for page flips/plane updates */
struct workqueue_struct *flip_wq;
+ /* pm private clock gating functions */
+ struct drm_i915_clock_gating_funcs clock_gating_funcs;
+
/* Display functions */
struct drm_i915_display_funcs display;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4054c6f7a2f9..add50ff01d7c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7871,7 +7871,7 @@ static void i830_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating(struct drm_i915_private *dev_priv)
{
- dev_priv->display.init_clock_gating(dev_priv);
+ dev_priv->clock_gating_funcs.init_clock_gating(dev_priv);
}
void intel_suspend_hw(struct drm_i915_private *dev_priv)
@@ -7898,52 +7898,52 @@ static void nop_init_clock_gating(struct
drm_i915_private *dev_priv)
void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
{
if (IS_ALDERLAKE_P(dev_priv))
- dev_priv->display.init_clock_gating = adlp_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
adlp_init_clock_gating;
else if (IS_DG1(dev_priv))
- dev_priv->display.init_clock_gating = dg1_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
dg1_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 12)
- dev_priv->display.init_clock_gating = gen12lp_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
gen12lp_init_clock_gating;
else if (GRAPHICS_VER(dev_priv) == 11)
- dev_priv->display.init_clock_gating = icl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
icl_init_clock_gating;
else if (IS_COFFEELAKE(dev_priv) || IS_COMETLAKE(dev_priv))
- dev_priv->display.init_clock_gating = cfl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
cfl_init_clock_gating;
else if (IS_SKYLAKE(dev_priv))
- dev_priv->display.init_clock_gating = skl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
skl_init_clock_gating;
else if (IS_KABYLAKE(dev_priv))
- dev_priv->display.init_clock_gating = kbl_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
kbl_init_clock_gating;
else if (IS_BROXTON(dev_priv))
- dev_priv->display.init_clock_gating = bxt_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
bxt_init_clock_gating;
else if (IS_GEMINILAKE(dev_priv))
- dev_priv->display.init_clock_gating = glk_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
glk_init_clock_gating;
else if (IS_BROADWELL(dev_priv))
- dev_priv->display.init_clock_gating = bdw_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
bdw_init_clock_gating;
else if (IS_CHERRYVIEW(dev_priv))
- dev_priv->display.init_clock_gating = chv_init_clock_gating;
+ dev_priv->clock_gating_funcs.init_clock_gating =
chv_init_clock_gating;
else if (IS_HASWELL(dev_priv))
- dev_priv->display.init_clock_gating = hsw_init_clock_gating;
+ dev_priv->clock_gating_funcs.init
[Intel-gfx] [PATCH 07/23] drm/i915: split watermark vfuncs from display vtable.
From: Dave Airlie
These are the watermark api between display and pm.
Signed-off-by: Dave Airlie
---
drivers/gpu/drm/i915/display/intel_display.c | 35 -
drivers/gpu/drm/i915/i915_drv.h | 24
drivers/gpu/drm/i915/intel_pm.c | 40 ++--
3 files changed, 54 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index f2678d26cd17..413bc4667e47 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -162,16 +162,16 @@ static void intel_modeset_setup_hw_state(struct
drm_device *dev,
*/
static void intel_update_watermarks(struct drm_i915_private *dev_priv)
{
- if (dev_priv->display.update_wm)
- dev_priv->display.update_wm(dev_priv);
+ if (dev_priv->wm_disp.update_wm)
+ dev_priv->wm_disp.update_wm(dev_priv);
}
static int intel_compute_pipe_wm(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.compute_pipe_wm)
- return dev_priv->display.compute_pipe_wm(state, crtc);
+ if (dev_priv->wm_disp.compute_pipe_wm)
+ return dev_priv->wm_disp.compute_pipe_wm(state, crtc);
return 0;
}
@@ -180,10 +180,10 @@ static int intel_compute_intermediate_wm(struct
intel_atomic_state *state,
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
if (drm_WARN_ON(_priv->drm,
- !dev_priv->display.compute_pipe_wm))
+ !dev_priv->wm_disp.compute_pipe_wm))
return 0;
- if (dev_priv->display.compute_pipe_wm)
- return dev_priv->display.compute_intermediate_wm(state, crtc);
+ if (dev_priv->wm_disp.compute_pipe_wm)
+ return dev_priv->wm_disp.compute_intermediate_wm(state, crtc);
return 0;
}
@@ -191,8 +191,8 @@ static bool intel_initial_watermarks(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.initial_watermarks) {
- dev_priv->display.initial_watermarks(state, crtc);
+ if (dev_priv->wm_disp.initial_watermarks) {
+ dev_priv->wm_disp.initial_watermarks(state, crtc);
return true;
}
return false;
@@ -202,23 +202,23 @@ static void intel_atomic_update_watermarks(struct
intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.atomic_update_watermarks)
- dev_priv->display.atomic_update_watermarks(state, crtc);
+ if (dev_priv->wm_disp.atomic_update_watermarks)
+ dev_priv->wm_disp.atomic_update_watermarks(state, crtc);
}
static void intel_optimize_watermarks(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.optimize_watermarks)
- dev_priv->display.optimize_watermarks(state, crtc);
+ if (dev_priv->wm_disp.optimize_watermarks)
+ dev_priv->wm_disp.optimize_watermarks(state, crtc);
}
static void intel_compute_global_watermarks(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- if (dev_priv->display.compute_global_watermarks)
- dev_priv->display.compute_global_watermarks(state);
+ if (dev_priv->wm_disp.compute_global_watermarks)
+ dev_priv->wm_disp.compute_global_watermarks(state);
}
/* returns HPLL frequency in kHz */
@@ -3669,6 +3669,7 @@ static void i9xx_crtc_enable(struct intel_atomic_state
*state,
if (!intel_initial_watermarks(state, crtc))
intel_update_watermarks(dev_priv);
+
intel_enable_pipe(new_crtc_state);
intel_crtc_vblank_on(new_crtc_state);
@@ -3734,7 +3735,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state
*state,
if (DISPLAY_VER(dev_priv) != 2)
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
- if (!dev_priv->display.initial_watermarks)
+ if (!dev_priv->wm_disp.initial_watermarks)
intel_update_watermarks(dev_priv);
/* clock the pipe down to 640x480@60 to potentially save power */
@@ -11387,7 +11388,7 @@ static void sanitize_watermarks(struct drm_i915_private
*dev_priv)
int i;
/* Only supported on platforms that use atomic water
