Re: [PATCH 6/7] drm/i915: Define the PIPE_CRC_EXP registers
On Fri, 31 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > I need a scratch register which fill the following requirements: > - can be accessed via DSB > - all the bits can be read/written > - no serious side effects > > So far the only thing I could think of is the "expected CRC" > register. Add the definition so I can use it. > > While I only need the hsw+ variant currently, let's define the > older variants as well for completeness. I'm having a hard time finding the spec for the old ones. The hsw+ is fine. Acked-by: Jani Nikula > > Signed-off-by: Ville Syrjälä > --- > .../drm/i915/display/intel_pipe_crc_regs.h| 47 +++ > 1 file changed, 47 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h > b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h > index 4f4bf51e1940..383910a785f6 100644 > --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h > @@ -56,6 +56,24 @@ > #define PIPE_CRC_SOURCE_DP_C_G4X > REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) > /* gen2 doesn't have source selection bits */ > #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) > +#define PIPE_CRC_EXP_RED_MASK REG_BIT(22, 0) /* pre-ivb */ > +#define PIPE_CRC_EXP_1_MASK_IVBREG_BIT(22, 0) /* ivb */ > + > +#define _PIPE_CRC_EXP_GREEN_A0x60054 > +#define PIPE_CRC_EXP_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, > _PIPE_CRC_EXP_GREEN_A) > +#define PIPE_CRC_EXP_GREEN_MASKREG_BIT(22, 0) /* pre-ivb */ > + > +#define _PIPE_CRC_EXP_BLUE_A 0x60058 > +#define PIPE_CRC_EXP_BLUE(dev_priv, pipe)_MMIO_TRANS2(dev_priv, pipe, > _PIPE_CRC_EXP_BLUE_A) > +#define PIPE_CRC_EXP_BLUE_MASK REG_BIT(22, 0) /* pre-ivb */ > + > +#define _PIPE_CRC_EXP_RES1_A_I9150x6005c /* i915+ */ > +#define PIPE_CRC_EXP_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, > pipe, _PIPE_CRC_EXP_RES1_A_I915) > +#define PIPE_CRC_EXP_RES1_MASK REG_BIT(22, 0) /* pre-ivb */ > + > +#define _PIPE_CRC_EXP_RES2_A_G4X 0x60080 /* g4x+ */ > +#define PIPE_CRC_EXP_RES2_G4X(dev_priv, pipe)_MMIO_TRANS2(dev_priv, > pipe, _PIPE_CRC_EXP_RES2_A_G4X) > +#define PIPE_CRC_EXP_RES2_MASK REG_BIT(22, 0) /* pre-ivb */ > > #define _PIPE_CRC_RES_RED_A 0x60060 > #define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, > _PIPE_CRC_RES_RED_A) > @@ -72,6 +90,30 @@ > #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 /* g4x+ */ > #define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)_MMIO_TRANS2(dev_priv, > pipe, _PIPE_CRC_RES_RES2_A_G4X) > > +/* ivb */ > +#define _PIPE_CRC_EXP_2_A_IVB0x60054 > +#define _PIPE_CRC_EXP_2_B_IVB0x61054 > +#define PIPE_CRC_EXP_2_IVB(pipe) _MMIO_PIPE(pipe, > _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB) > +#define PIPE_CRC_EXP_2_MASK_IVBREG_BIT(22, 0) /* ivb */ > + > +/* ivb */ > +#define _PIPE_CRC_EXP_3_A_IVB0x60058 > +#define _PIPE_CRC_EXP_3_B_IVB0x61058 > +#define PIPE_CRC_EXP_3_IVB(pipe) _MMIO_PIPE(pipe, > _PIPE_CRC_EXP_3_A_IVB, _PIPE_CRC_EXP_3_B_IVB) > +#define PIPE_CRC_EXP_3_MASK_IVBREG_BIT(22, 0) /* ivb */ > + > +/* ivb */ > +#define _PIPE_CRC_EXP_4_A_IVB0x6005c > +#define _PIPE_CRC_EXP_4_B_IVB0x6105c > +#define PIPE_CRC_EXP_4_IVB(pipe) _MMIO_PIPE(pipe, > _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB) > +#define PIPE_CRC_EXP_4_MASK_IVBREG_BIT(22, 0) /* ivb */ > + > +/* ivb */ > +#define _PIPE_CRC_EXP_5_A_IVB0x60060 > +#define _PIPE_CRC_EXP_5_B_IVB0x61060 > +#define PIPE_CRC_EXP_5_IVB(pipe) _MMIO_PIPE(pipe, > _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB) > +#define PIPE_CRC_EXP_5_MASK_IVBREG_BIT(22, 0) /* ivb */ > + > /* ivb */ > #define _PIPE_CRC_RES_1_A_IVB0x60064 > #define _PIPE_CRC_RES_1_B_IVB0x61064 > @@ -97,6 +139,11 @@ > #define _PIPE_CRC_RES_5_B_IVB0x61074 > #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, > _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) > > +/* hsw+ */ > +#define _PIPE_CRC_EXP_A_HSW 0x60054 > +#define _PIPE_CRC_EXP_B_HSW 0x61054 > +#define PIPE_CRC_EXP_HSW(pipe) _MMIO_PIPE(pipe, > _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW) > + > /* hsw+ */ > #define _PIPE_CRC_RES_A_HSW 0x60064 > #define _PIPE_CRC_RES_B_HSW 0x61064 -- Jani Nikula, Intel
Re: [PATCH v2 00/10] drm: move Intel drm headers to a subdirectory
On Thu, 30 May 2024, Jani Nikula wrote:
> We've accumulated enough Intel specific header files under include/drm
> that they warrant a subdirectory of their own. Clean up the top drm
> header directory by moving the Intel files under include/drm/intel.
>
> Since i915 is most impacted, I suggest merging the lot via
> drm-intel-next. Please ack if this is fine for you.
Pushed to drm-intel-next.
BR,
Jani.
>
> BR,
> Jani.
>
> Jani Nikula (10):
> drm: move intel-gtt.h under include/drm/intel
> drm: move i915_gsc_proxy_mei_interface.h under include/drm/intel
> drm: move i915_component.h under include/drm/intel
> drm: move intel_lpe_audio.h under include/drm/intel
> drm: move i915_drm.h under include/drm/intel
> drm: move i915_pxp_tee_interface.h under include/drm/intel
> drm: move i915_pciids.h under include/drm/intel
> drm: move xe_pciids.h under include/drm/intel
> drm: move i915_hdcp_interface.h under include/drm/intel
> MAINTAINERS: update i915 and xe entries for include/drm/intel
>
> Documentation/gpu/i915.rst | 2 +-
> MAINTAINERS| 5 +++--
> arch/x86/kernel/early-quirks.c | 4 ++--
> drivers/char/agp/intel-agp.c | 2 +-
> drivers/char/agp/intel-gtt.c | 2 +-
> drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_device.c| 2 +-
> drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
> drivers/gpu/drm/i915/display/intel_lpe_audio.c | 2 +-
> drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 ++--
> drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_rps.c| 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 4 ++--
> drivers/gpu/drm/i915/i915_pci.c| 2 +-
> drivers/gpu/drm/i915/intel_device_info.c | 2 +-
> drivers/gpu/drm/i915/intel_pci_config.h| 2 +-
> drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 4 ++--
> drivers/gpu/drm/i915/soc/intel_gmch.c | 2 +-
> drivers/gpu/drm/xe/display/xe_hdcp_gsc.c | 2 +-
> drivers/gpu/drm/xe/xe_ggtt.c | 2 +-
> drivers/gpu/drm/xe/xe_gsc_proxy.c | 4 ++--
> drivers/gpu/drm/xe/xe_pci.c| 2 +-
> drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c | 4 ++--
> drivers/misc/mei/hdcp/mei_hdcp.c | 4 ++--
> drivers/misc/mei/pxp/mei_pxp.c | 4 ++--
> drivers/platform/x86/intel_ips.c | 2 +-
> include/drm/{ => intel}/i915_component.h | 0
> include/drm/{ => intel}/i915_drm.h | 0
> include/drm/{ => intel}/i915_gsc_proxy_mei_interface.h | 0
> include/drm/{ => intel}/i915_hdcp_interface.h | 0
> include/drm/{ => intel}/i915_pciids.h | 0
> include/drm/{ => intel}/i915_pxp_tee_interface.h | 0
> include/drm/{ => intel}/intel-gtt.h| 0
> include/drm/{ => intel}/intel_lpe_audio.h | 0
> include/drm/{ => intel}/xe_pciids.h| 0
> include/sound/hdaudio.h| 2 +-
> sound/x86/intel_hdmi_audio.c | 2 +-
> 43 files changed, 44 insertions(+), 43 deletions(-)
> rename include/drm/{ => intel}/i915_component.h (100%)
> rename include/drm/{ => intel}/i915_drm.h (100%)
> rename include/drm/{ => intel}/i915_gsc_proxy_mei_interface.h (100%)
> rename include/drm/{ => intel}/i915_hdcp_interface.h (100%)
> rename include/drm/{ => intel}/i915_pciids.h (100%)
> rename include/drm/{ => intel}/i915_pxp_tee_interface.h (100%)
> rename include/drm/{ => intel}/intel-gtt.h (100%)
> rename include/drm/{ => intel}/intel_lpe_audio.h (100%)
> rename include/drm/{ => intel}/xe_pciids.h (100%)
--
Jani Nikula, Intel
Re: [PATCH 5/7] drm/i915: Document which platforms have which CRC registers
On Fri, 31 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Sprinkle some comments around to indicate which CRC registers > are valid for which platforms. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula -- Jani Nikula, Intel
Re: [PATCH 4/7] drm/i915: Add a separate defintiion for PIPE_CRC_RES_HSW
Subject: *definition On Fri, 31 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > On hsw+ we only have one CRC result registers, instead of the *register > five we have on ivb, and some of the others have been repurposed > to serve other CRC related purposed. *purposes > > Since the hsw+ vs. pre-hsw register operate quite diffently *differently > let's add a separate definition for the hsw+ variant to make the > situation a bit more clear. Also since we only use this from a > hsw+ codepath there is no real benefit to be had with reusing > the ivb register definition. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula -- Jani Nikula, Intel
Re: [PATCH 3/7] drm/i915: Regroup pipe CRC regs
On Fri, 31 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Put all the definitions related to a single pipe CRC register > in one place, instead of the current approach where things are > spread all over the place. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula -- Jani Nikula, Intel
Re: [PATCH 2/7] drm/i915: Switch PIPE_CRC_RES_*_IVB to _MMIO_PIPE()
On Fri, 31 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > PIPE_CRC_RES_*_IVB are proper pipe registers, and only valid > for IVB+ where pipe register blocks are equally spaced, so we > can switch from _MMIO_TRANS2() to the simpler _MMIO_PIPE() for > these. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula -- Jani Nikula, Intel
Re: [PATCH 1/7] drm/i915: Extract intel_pipe_crc_regs.h
On Fri, 31 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > The CRC registers are a pretty self contained bunch. > Extract them to a separate header to declutter i915_reg.h. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula -- Jani Nikula, Intel
Re: [PATCH 1/2] drm/i915: drop unnecessary i915_reg.h includes
On Fri, 31 May 2024, Ville Syrjälä wrote: > On Thu, May 30, 2024 at 01:07:46PM +0300, Jani Nikula wrote: >> With the register header refactoring, some of the includes of i915_reg.h >> have become unnecessary. Remove. >> >> Signed-off-by: Jani Nikula >> --- >> drivers/gpu/drm/i915/display/dvo_ns2501.c | 1 - >> drivers/gpu/drm/i915/display/intel_atomic.c | 1 - >> drivers/gpu/drm/i915/display/intel_atomic_plane.c | 1 - >> drivers/gpu/drm/i915/display/intel_dkl_phy.c | 1 - >> drivers/gpu/drm/i915/display/intel_dsb.c | 1 - >> drivers/gpu/drm/i915/display/intel_sprite.c | 1 - >> drivers/gpu/drm/i915/display/intel_vdsc.c | 1 - >> 7 files changed, 7 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/dvo_ns2501.c >> b/drivers/gpu/drm/i915/display/dvo_ns2501.c >> index 1df212fb000e..21486008dae9 100644 >> --- a/drivers/gpu/drm/i915/display/dvo_ns2501.c >> +++ b/drivers/gpu/drm/i915/display/dvo_ns2501.c >> @@ -27,7 +27,6 @@ >> */ >> >> #include "i915_drv.h" >> -#include "i915_reg.h" >> #include "intel_display_types.h" >> #include "intel_dvo_dev.h" >> >> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c >> b/drivers/gpu/drm/i915/display/intel_atomic.c >> index 7a77ae3dc394..76aa10b6f647 100644 >> --- a/drivers/gpu/drm/i915/display/intel_atomic.c >> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c >> @@ -35,7 +35,6 @@ >> #include >> >> #include "i915_drv.h" >> -#include "i915_reg.h" >> #include "intel_atomic.h" >> #include "intel_cdclk.h" >> #include "intel_display_types.h" >> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c >> b/drivers/gpu/drm/i915/display/intel_atomic_plane.c >> index a2a827070c33..a4ce39a7f265 100644 >> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c >> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c >> @@ -39,7 +39,6 @@ >> #include >> >> #include "i915_config.h" >> -#include "i915_reg.h" > > That has sure spread into some weird places. > > As it seems to build, the series is > Reviewed-by: Ville Syrjälä Thanks, pushed to din. BR, Jani. > >> #include "i9xx_plane_regs.h" >> #include "intel_atomic_plane.h" >> #include "intel_cdclk.h" >> diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c >> b/drivers/gpu/drm/i915/display/intel_dkl_phy.c >> index a001232ad445..b146b4c46943 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dkl_phy.c >> +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c >> @@ -4,7 +4,6 @@ >> */ >> >> #include "i915_drv.h" >> -#include "i915_reg.h" >> >> #include "intel_de.h" >> #include "intel_display.h" >> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c >> b/drivers/gpu/drm/i915/display/intel_dsb.c >> index 4baaa92ceaec..bcc9de047fac 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dsb.c >> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c >> @@ -6,7 +6,6 @@ >> >> #include "i915_drv.h" >> #include "i915_irq.h" >> -#include "i915_reg.h" >> #include "intel_crtc.h" >> #include "intel_de.h" >> #include "intel_display_types.h" >> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c >> b/drivers/gpu/drm/i915/display/intel_sprite.c >> index 36a253a19c74..e1c907f601da 100644 >> --- a/drivers/gpu/drm/i915/display/intel_sprite.c >> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c >> @@ -39,7 +39,6 @@ >> #include >> >> #include "i915_drv.h" >> -#include "i915_reg.h" >> #include "i9xx_plane.h" >> #include "intel_atomic_plane.h" >> #include "intel_de.h" >> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c >> b/drivers/gpu/drm/i915/display/intel_vdsc.c >> index 17d6572f9d0a..d76e70846a8c 100644 >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c >> @@ -10,7 +10,6 @@ >> #include >> >> #include "i915_drv.h" >> -#include "i915_reg.h" >> #include "intel_crtc.h" >> #include "intel_de.h" >> #include "intel_display_types.h" >> -- >> 2.39.2 -- Jani Nikula, Intel
Re: [PATCH 0/5] drm/i915: DP AUX CH macro cleanups
On Fri, 31 May 2024, Ville Syrjälä wrote: > On Tue, May 28, 2024 at 02:15:37PM +0300, Jani Nikula wrote: >> Jani Nikula (5): >> drm/i915/gvt: use proper macros for DP AUX CH CTL registers >> drm/i915: remove unused DP AUX CH register macros >> drm/i915: rearrange DP AUX register macros >> drm/i915: move PCH DP AUX CH regs to intel_dp_aux_regs.h >> drm/i915: remove intermediate _PCH_DP_* macros > > Didn't spot anything off. > > Series is > Reviewed-by: Ville Syrjälä Thanks, pushed to din. BR, Jani. > >> >> .../gpu/drm/i915/display/intel_dp_aux_regs.h | 18 +++--- >> drivers/gpu/drm/i915/gvt/handlers.c | 35 +-- >> drivers/gpu/drm/i915/i915_reg.h | 32 ++--- >> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++--- >> 4 files changed, 37 insertions(+), 56 deletions(-) >> >> -- >> 2.39.2 -- Jani Nikula, Intel
Re: [PATCH 03/10] drm/i915/display: include i915_gpu_error.h where needed
On Fri, 31 May 2024, Jani Nikula wrote: > On Fri, 31 May 2024, Ville Syrjälä wrote: >> On Wed, May 29, 2024 at 08:48:07PM +0300, Jani Nikula wrote: >>> Include what you use. With this, we can drop the include from xe compat >>> i915_drv.h. >>> >>> Signed-off-by: Jani Nikula >>> --- >>> drivers/gpu/drm/i915/display/intel_dmc.c | 1 + >>> drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 - >>> 2 files changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c >>> b/drivers/gpu/drm/i915/display/intel_dmc.c >>> index 63fccdda56c0..b5ebb0f5b269 100644 >>> --- a/drivers/gpu/drm/i915/display/intel_dmc.c >>> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c >>> @@ -26,6 +26,7 @@ >>> #include >>> >>> #include "i915_drv.h" >>> +#include "i915_gpu_error.h" >> >> Someone should probably convert intel_dmc_print_error_state() >> to use the drm_printer interface instead, assuming that is the >> only thing that needs this header in intel_dmc.c. > > I don't disagree, but kind of wanted to keep this series focused on just > rearranging the headers. And this serves a purpose: now you can look at > the files under display to have a better grasp at what's needed from > outside of display. i915_gpu_error.h include flags one case. Seems straightforward, I can do it on top. -- Jani Nikula, Intel
Re: [PATCH 05/10] drm/i915/display: include intel_step.h where needed
On Fri, 31 May 2024, Rodrigo Vivi wrote: > On Wed, May 29, 2024 at 08:48:09PM +0300, Jani Nikula wrote: >> Include what you use. With this, we can drop the include along with >> xe_step.h from xe compat i915_drv.h. > > it was hard to see this one... > > 'intel_display_step' inside the intel_step component is not the right way. > > we should probably move intel_display_step_name to intel_dmc.c which is the > only user. It's a bit of a bummer. Looks like we'll need to have this duplicated in i915, xe, and display. :/ > > But this can be a follow up since for that we will still need the intel_step.h > include in here. > > Reviewed-by: Rodrigo Vivi > >> >> Signed-off-by: Jani Nikula >> --- >> drivers/gpu/drm/i915/display/intel_dmc.c | 1 + >> drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 2 -- >> 2 files changed, 1 insertion(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c >> b/drivers/gpu/drm/i915/display/intel_dmc.c >> index b5ebb0f5b269..852c11aa3205 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dmc.c >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c >> @@ -31,6 +31,7 @@ >> #include "intel_de.h" >> #include "intel_dmc.h" >> #include "intel_dmc_regs.h" >> +#include "intel_step.h" >> >> /** >> * DOC: DMC Firmware Support >> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h >> b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h >> index e5966f07a924..3e930ce25c90 100644 >> --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h >> +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h >> @@ -18,10 +18,8 @@ >> #include "xe_device.h" >> #include "xe_bo.h" >> #include "xe_pm.h" >> -#include "xe_step.h" >> #include "i915_reg_defs.h" >> #include "i915_utils.h" >> -#include "intel_step.h" >> #include "intel_runtime_pm.h" >> #include >> >> -- >> 2.39.2 >> -- Jani Nikula, Intel
Re: [PATCH 03/10] drm/i915/display: include i915_gpu_error.h where needed
On Fri, 31 May 2024, Ville Syrjälä wrote: > On Wed, May 29, 2024 at 08:48:07PM +0300, Jani Nikula wrote: >> Include what you use. With this, we can drop the include from xe compat >> i915_drv.h. >> >> Signed-off-by: Jani Nikula >> --- >> drivers/gpu/drm/i915/display/intel_dmc.c | 1 + >> drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 - >> 2 files changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c >> b/drivers/gpu/drm/i915/display/intel_dmc.c >> index 63fccdda56c0..b5ebb0f5b269 100644 >> --- a/drivers/gpu/drm/i915/display/intel_dmc.c >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c >> @@ -26,6 +26,7 @@ >> #include >> >> #include "i915_drv.h" >> +#include "i915_gpu_error.h" > > Someone should probably convert intel_dmc_print_error_state() > to use the drm_printer interface instead, assuming that is the > only thing that needs this header in intel_dmc.c. I don't disagree, but kind of wanted to keep this series focused on just rearranging the headers. And this serves a purpose: now you can look at the files under display to have a better grasp at what's needed from outside of display. i915_gpu_error.h include flags one case. BR, Jani. -- Jani Nikula, Intel
Re: [PATCH 01/10] drm/i915/display: include gem/i915_gem_stolen.h where needed
On Fri, 31 May 2024, Rodrigo Vivi wrote:
> On Wed, May 29, 2024 at 08:48:05PM +0300, Jani Nikula wrote:
>> Include what you use. We need to move the compat i915_gem_stolen.h under
>> gem subdir.
>
> The patch below looks fine, but this message here is strange.
> It looks like this patch is moving the header file from a top dir to
> under 'gem' dir. But the header is already there.
Huh, in compat-i915-headers it's not? And that's the point, the
hierarchy should match i915 but for a couple of files it doesn't.
BR,
Jani.
>
>> With this, we can drop the include from xe compat
>> i915_drv.h.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
>> .../gpu/drm/xe/compat-i915-headers/{ => gem}/i915_gem_stolen.h | 0
>> drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h| 1 -
>> 3 files changed, 1 insertion(+), 1 deletion(-)
>> rename drivers/gpu/drm/xe/compat-i915-headers/{ => gem}/i915_gem_stolen.h
>> (100%)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
>> b/drivers/gpu/drm/i915/display/intel_fbc.c
>> index e9189a864f69..6985abeb6102 100644
>> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>> @@ -43,6 +43,7 @@
>> #include
>> #include
>>
>> +#include "gem/i915_gem_stolen.h"
>> #include "i915_drv.h"
>> #include "i915_reg.h"
>> #include "i915_utils.h"
>> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_gem_stolen.h
>> b/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_stolen.h
>> similarity index 100%
>> rename from drivers/gpu/drm/xe/compat-i915-headers/i915_gem_stolen.h
>> rename to drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_stolen.h
>> diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> index cd4632276141..3be3d419530a 100644
>> --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
>> @@ -19,7 +19,6 @@
>> #include "xe_bo.h"
>> #include "xe_pm.h"
>> #include "xe_step.h"
>> -#include "i915_gem_stolen.h"
>> #include "i915_gpu_error.h"
>> #include "i915_reg_defs.h"
>> #include "i915_utils.h"
>> --
>> 2.39.2
>>
--
Jani Nikula, Intel
RE: [PATCH v10 1/8] drm/i915: Separate VRR related register definitions
On Fri, 31 May 2024, "Golani, Mitulkumar Ajitkumar" wrote: > Hi Jani, > >> -Original Message- >> From: Nikula, Jani >> Sent: Thursday, May 30, 2024 7:19 PM >> To: Golani, Mitulkumar Ajitkumar ; >> intel-gfx@lists.freedesktop.org >> Cc: dri-de...@lists.freedesktop.org; Nautiyal, Ankit K >> >> Subject: Re: [PATCH v10 1/8] drm/i915: Separate VRR related register >> definitions >> >> On Thu, 30 May 2024, Mitul Golani >> wrote: >> > Move VRR related register definitions to a separate file called >> > intel_vrr_regs.h. >> >> But this is not just movement... there's a bunch of other (mostly >> unwanted?) changes there too. >> >> 'git show --color-moved' is a powerful tool for reviewing code movement. If >> it's >> not just movement, you have to fallback to manual review of the whole thing. > > I have moved the VRR-related registers from i915_reg.h to > intel_vrr_regs.h and reordered them based on their register > offsets. However, if preferred, I can move only the VRR-related > registers for now and handle the reordering in a separate patch series > later. Please let me know if this approach is acceptable. Yes. You can check with 'git show --color-moved'. Also avoid the indentation changes. BR, Jani. > > Regards, > Mitul >> >> > Signed-off-by: Mitul Golani >> > --- >> > drivers/gpu/drm/i915/display/intel_vrr.c | 1 + >> > drivers/gpu/drm/i915/display/intel_vrr_regs.h | 117 ++ >> > drivers/gpu/drm/i915/i915_reg.h | 100 --- >> > 3 files changed, 118 insertions(+), 100 deletions(-) create mode >> > 100644 drivers/gpu/drm/i915/display/intel_vrr_regs.h >> > > -- Jani Nikula, Intel
[PATCH 3/3] drm/amd/display: switch to guid_gen() to generate valid GUIDs
Instead of just smashing jiffies into a GUID, use guid_gen() to generate
RFC 4122 compliant GUIDs.
Signed-off-by: Jani Nikula
---
Side note, it baffles me why amdgpu has a copy of this instead of
plumbing it into drm mst code.
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 ++-
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 65ebc01dc90f..a1bd847857b8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2403,9 +2403,9 @@ static int dm_late_init(void *handle)
static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr)
{
+ u8 buf[UUID_SIZE];
+ guid_t guid;
int ret;
- u8 guid[16];
- u64 tmp64;
mutex_lock(>lock);
if (!mgr->mst_primary)
@@ -2426,26 +2426,27 @@ static void resume_mst_branch_status(struct
drm_dp_mst_topology_mgr *mgr)
}
/* Some hubs forget their guids after they resume */
- ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16);
- if (ret != 16) {
+ ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf));
+ if (ret != sizeof(buf)) {
drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during
suspend?\n");
goto out_fail;
}
- if (memchr_inv(guid, 0, 16) == NULL) {
- tmp64 = get_jiffies_64();
- memcpy([0], , sizeof(u64));
- memcpy([8], , sizeof(u64));
+ import_guid(, buf);
- ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16);
+ if (guid_is_null()) {
+ guid_gen();
+ export_guid(buf, );
- if (ret != 16) {
+ ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf));
+
+ if (ret != sizeof(buf)) {
drm_dbg_kms(mgr->dev, "check mstb guid failed -
undocked during suspend?\n");
goto out_fail;
}
}
- import_guid(>mst_primary->guid, guid);
+ guid_copy(>mst_primary->guid, );
out_fail:
mutex_unlock(>lock);
--
2.39.2
[PATCH 1/3] drm/mst: switch to guid_t type for GUID
The kernel has a guid_t type for GUIDs. Switch to using it, but avoid
any functional changes here.
Signed-off-by: Jani Nikula
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
drivers/gpu/drm/display/drm_dp_mst_topology.c | 67 +++
include/drm/display/drm_dp_mst_helper.h | 12 ++--
3 files changed, 45 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 516eb3968e26..65ebc01dc90f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2445,7 +2445,7 @@ static void resume_mst_branch_status(struct
drm_dp_mst_topology_mgr *mgr)
}
}
- memcpy(mgr->mst_primary->guid, guid, 16);
+ import_guid(>mst_primary->guid, guid);
out_fail:
mutex_unlock(>lock);
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 7f8e1cfbe19d..9b1f35b1a2da 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -89,7 +89,7 @@ static int drm_dp_send_enum_path_resources(struct
drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_branch *mstb,
struct drm_dp_mst_port *port);
static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr,
-u8 *guid);
+guid_t *guid);
static int drm_dp_mst_register_i2c_bus(struct drm_dp_mst_port *port);
static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_mst_port *port);
@@ -801,7 +801,7 @@ static bool drm_dp_sideband_parse_link_address(const struct
drm_dp_mst_topology_
int idx = 1;
int i;
- memcpy(repmsg->u.link_addr.guid, >msg[idx], 16);
+ import_guid(>u.link_addr.guid, >msg[idx]);
idx += 16;
repmsg->u.link_addr.nports = raw->msg[idx] & 0xf;
idx++;
@@ -829,7 +829,7 @@ static bool drm_dp_sideband_parse_link_address(const struct
drm_dp_mst_topology_
idx++;
if (idx > raw->curlen)
goto fail_len;
- memcpy(repmsg->u.link_addr.ports[i].peer_guid,
>msg[idx], 16);
+ import_guid(>u.link_addr.ports[i].peer_guid,
>msg[idx]);
idx += 16;
if (idx > raw->curlen)
goto fail_len;
@@ -1029,7 +1029,7 @@ static bool drm_dp_sideband_parse_reply(const struct
drm_dp_mst_topology_mgr *mg
msg->req_type = (raw->msg[0] & 0x7f);
if (msg->reply_type == DP_SIDEBAND_REPLY_NAK) {
- memcpy(msg->u.nak.guid, >msg[1], 16);
+ import_guid(>u.nak.guid, >msg[1]);
msg->u.nak.reason = raw->msg[17];
msg->u.nak.nak_data = raw->msg[18];
return false;
@@ -1078,7 +1078,7 @@ drm_dp_sideband_parse_connection_status_notify(const
struct drm_dp_mst_topology_
if (idx > raw->curlen)
goto fail_len;
- memcpy(msg->u.conn_stat.guid, >msg[idx], 16);
+ import_guid(>u.conn_stat.guid, >msg[idx]);
idx += 16;
if (idx > raw->curlen)
goto fail_len;
@@ -1107,7 +1107,7 @@ static bool
drm_dp_sideband_parse_resource_status_notify(const struct drm_dp_mst
if (idx > raw->curlen)
goto fail_len;
- memcpy(msg->u.resource_stat.guid, >msg[idx], 16);
+ import_guid(>u.resource_stat.guid, >msg[idx]);
idx += 16;
if (idx > raw->curlen)
goto fail_len;
@@ -2174,20 +2174,24 @@ ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux,
offset, size, buffer);
}
-static int drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, u8 *guid)
+static int drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, guid_t *guid)
{
int ret = 0;
- memcpy(mstb->guid, guid, 16);
+ guid_copy(>guid, guid);
+
+ if (!drm_dp_validate_guid(mstb->mgr, >guid)) {
+ u8 buf[UUID_SIZE];
+
+ export_guid(buf, >guid);
- if (!drm_dp_validate_guid(mstb->mgr, mstb->guid)) {
if (mstb->port_parent) {
ret = drm_dp_send_dpcd_write(mstb->mgr,
mstb->port_parent,
-DP_GUID, 16, mstb->guid);
+DP_GUID, sizeof(buf), buf);
} else {
ret = drm_dp_dpcd_write(mstb->mgr->aux,
-
[PATCH 2/3] drm/mst: switch to guid_gen() to generate valid GUIDs
Instead of just smashing jiffies into a GUID, use guid_gen() to generate
RFC 4122 compliant GUIDs.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c
b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 9b1f35b1a2da..1cb071daab8f 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -2698,18 +2698,10 @@ static void drm_dp_mst_link_probe_work(struct
work_struct *work)
static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr,
guid_t *guid)
{
- u64 salt;
- u8 buf[UUID_SIZE];
-
if (!guid_is_null(guid))
return true;
- salt = get_jiffies_64();
-
- memcpy([0], , sizeof(u64));
- memcpy([8], , sizeof(u64));
-
- import_guid(guid, buf);
+ guid_gen(guid);
return false;
}
--
2.39.2
[PATCH 0/3] drm/mst & drm/amd/display: switch to using guid_t
We have a guid_t type for GUIDs, switch to using it instead of hand rolling buffers. Convert to guid_gen() in separate patches to pinpoint the functional changes. BR, Jani. Jani Nikula (3): drm/mst: switch to guid_t type for GUID drm/mst: switch to guid_gen() to generate valid GUIDs drm/amd/display: switch to guid_gen() to generate valid GUIDs .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 --- drivers/gpu/drm/display/drm_dp_mst_topology.c | 67 ++- include/drm/display/drm_dp_mst_helper.h | 12 ++-- 3 files changed, 52 insertions(+), 50 deletions(-) -- 2.39.2
Re: [PATCH 00/10] drm/i915: identify all platforms in display probe
On Wed, 22 May 2024, Jani Nikula wrote: > Add independent platform probe in display, in preparation for breaking > free from i915 and xe code. Merged to din, thanks for the review. BR, Jani. -- Jani Nikula, Intel
Re: [v6 0/3] Fix cursor FB unpinning.
On Wed, 22 May 2024, Maarten Lankhorst wrote: > Hopefully last attempt. > Small bug in drm_vblank_work_flush_all left, fixed now hopefully. Acked-by: Jani Nikula for merging via drm-misc, but drm-intel is also fine by me. No big deal this time of the cycle when we can get the backmerge fairly quickly. > > Maarten Lankhorst (2): > drm: Add drm_vblank_work_flush_all(). > drm/i915: Use the same vblank worker for atomic unpin > > Ville Syrjälä (1): > drm/i915: Use vblank worker to unpin old legacy cursor fb safely > > drivers/gpu/drm/drm_vblank_work.c | 22 + > .../gpu/drm/i915/display/intel_atomic_plane.c | 13 +++- > .../gpu/drm/i915/display/intel_atomic_plane.h | 2 ++ > drivers/gpu/drm/i915/display/intel_crtc.c | 31 +++ > drivers/gpu/drm/i915/display/intel_cursor.c | 26 ++-- > drivers/gpu/drm/i915/display/intel_cursor.h | 3 ++ > drivers/gpu/drm/i915/display/intel_display.c | 3 ++ > .../drm/i915/display/intel_display_types.h| 3 ++ > include/drm/drm_vblank_work.h | 2 ++ > 9 files changed, 102 insertions(+), 3 deletions(-) -- Jani Nikula, Intel
Re: [PATCH v10 1/8] drm/i915: Separate VRR related register definitions
ine VRR_CTL_PIPELINE_FULL(x) > REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) > -#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) > -#defineXELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) > -#defineXELPD_VRR_CTL_VRR_GUARDBAND(x) > REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) > - > -#define _TRANS_VRR_VMAX_A0x60424 > -#define _TRANS_VRR_VMAX_B0x61424 > -#define _TRANS_VRR_VMAX_C0x62424 > -#define _TRANS_VRR_VMAX_D0x63424 > -#define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, > trans, _TRANS_VRR_VMAX_A) > -#define VRR_VMAX_MASK REG_GENMASK(19, 0) > - > -#define _TRANS_VRR_VMIN_A0x60434 > -#define _TRANS_VRR_VMIN_B0x61434 > -#define _TRANS_VRR_VMIN_C0x62434 > -#define _TRANS_VRR_VMIN_D0x63434 > -#define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, > trans, _TRANS_VRR_VMIN_A) > -#define VRR_VMIN_MASK REG_GENMASK(15, 0) > - > -#define _TRANS_VRR_VMAXSHIFT_A 0x60428 > -#define _TRANS_VRR_VMAXSHIFT_B 0x61428 > -#define _TRANS_VRR_VMAXSHIFT_C 0x62428 > -#define _TRANS_VRR_VMAXSHIFT_D 0x63428 > -#define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ > - _TRANS_VRR_VMAXSHIFT_A) > -#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) > -#define VRR_VMAXSHIFT_DEC REG_BIT(16) > -#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) > - > -#define _TRANS_VRR_STATUS_A 0x6042C > -#define _TRANS_VRR_STATUS_B 0x6142C > -#define _TRANS_VRR_STATUS_C 0x6242C > -#define _TRANS_VRR_STATUS_D 0x6342C > -#define TRANS_VRR_STATUS(dev_priv, trans)_MMIO_TRANS2(dev_priv, > trans, _TRANS_VRR_STATUS_A) > -#define VRR_STATUS_VMAX_REACHEDREG_BIT(31) > -#define VRR_STATUS_NOFLIP_TILL_BNDRREG_BIT(30) > -#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) > -#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) > -#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) > -#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) > -#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) > -#define STATUS_FSM_IDLEREG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, > 0) > -#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, > 1) > -#define STATUS_FSM_WAIT_TILL_FSREG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, > 2) > -#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, > 3) > -#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, > 4) > -#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, > 5) > -#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, > 6) > - > -#define _TRANS_VRR_VTOTAL_PREV_A 0x60480 > -#define _TRANS_VRR_VTOTAL_PREV_B 0x61480 > -#define _TRANS_VRR_VTOTAL_PREV_C 0x62480 > -#define _TRANS_VRR_VTOTAL_PREV_D 0x63480 > -#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, > trans, \ > - _TRANS_VRR_VTOTAL_PREV_A) > -#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) > -#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) > -#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) > -#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) > - > -#define _TRANS_VRR_FLIPLINE_A0x60438 > -#define _TRANS_VRR_FLIPLINE_B0x61438 > -#define _TRANS_VRR_FLIPLINE_C0x62438 > -#define _TRANS_VRR_FLIPLINE_D0x63438 > -#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ > - _TRANS_VRR_FLIPLINE_A) > -#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) > - > -#define _TRANS_VRR_STATUS2_A 0x6043C > -#define _TRANS_VRR_STATUS2_B 0x6143C > -#define _TRANS_VRR_STATUS2_C 0x6243C > -#define _TRANS_VRR_STATUS2_D 0x6343C > -#define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, > _TRANS_VRR_STATUS2_A) > -#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) > - > -#define _TRANS_PUSH_A0x60A70 > -#define _TRANS_PUSH_B0x61A70 > -#define _TRANS_PUSH_C 0x62A70 > -#define _TRANS_PUSH_D0x63A70 > -#define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, > _TRANS_PUSH_A) > -#define TRANS_PUSH_EN REG_BIT(31) > -#define TRANS_PUSH_SENDREG_BIT(30) > - > -#define _TRANS_VRR_VSYNC_A 0x60078 > -#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, > trans, _TRANS_VRR_VSYNC_A) > -#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) > -#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, > (vsync_end)) > -#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) > -#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, > (vsync_start)) > - > /* VGA port control */ > #define ADPA _MMIO(0x61100) > #define PCH_ADPA_MMIO(0xe1100) -- Jani Nikula, Intel
[PATCH v2 09/10] drm: move i915_hdcp_interface.h under include/drm/intel
Clean up the top level include/drm directory by grouping all the Intel
specific files under a common subdirectory.
Cc: Daniel Vetter
Cc: Dave Airlie
Cc: Lucas De Marchi
Cc: Tomas Winkler
Acked-by: Lucas De Marchi
Acked-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display_types.h| 2 +-
drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c | 2 +-
drivers/gpu/drm/xe/display/xe_hdcp_gsc.c | 2 +-
drivers/misc/mei/hdcp/mei_hdcp.c | 2 +-
include/drm/{ => intel}/i915_hdcp_interface.h | 0
6 files changed, 5 insertions(+), 5 deletions(-)
rename include/drm/{ => intel}/i915_hdcp_interface.h (100%)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6fbfe8a18f45..9210643c9fdf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -44,7 +44,7 @@
#include
#include
#include
-#include
+#include
#include
#include "i915_vma.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
index 35823e1f65d6..16afeb8a3a8d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c
@@ -3,7 +3,7 @@
* Copyright 2023, Intel Corporation.
*/
-#include
+#include
#include "gem/i915_gem_region.h"
#include "gt/intel_gt.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
index 240b00849f3d..6548e71b4c49 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c
@@ -4,7 +4,7 @@
*/
#include
-#include
+#include
#include "i915_drv.h"
#include "intel_hdcp_gsc_message.h"
diff --git a/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
b/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
index eb67ecf08db2..14b8b4278317 100644
--- a/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
+++ b/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c
@@ -4,7 +4,7 @@
*/
#include
-#include
+#include
#include
#include "abi/gsc_command_header_abi.h"
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index e43ea536c947..323f10620d90 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -24,7 +24,7 @@
#include
#include
#include
-#include
+#include
#include "mei_hdcp.h"
diff --git a/include/drm/i915_hdcp_interface.h
b/include/drm/intel/i915_hdcp_interface.h
similarity index 100%
rename from include/drm/i915_hdcp_interface.h
rename to include/drm/intel/i915_hdcp_interface.h
--
2.39.2
[PATCH v2 10/10] MAINTAINERS: update i915 and xe entries for include/drm/intel
With all the Intel specific drm files under include/drm/intel, update the i915, xe, and the shared display entries. Do not discriminate based on file name pattern, just add the entire directory for all three entries. Cc: Joonas Lahtinen Cc: Lucas De Marchi Cc: Oded Gabbay Cc: Rodrigo Vivi Cc: Thomas Hellström Cc: Tvrtko Ursulin Reviewed-by: Andi Shyti Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula --- MAINTAINERS | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 21aad782f1ea..572be0546e21 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11013,6 +11013,7 @@ S: Supported F: drivers/gpu/drm/i915/display/ F: drivers/gpu/drm/xe/display/ F: drivers/gpu/drm/xe/compat-i915-headers +F: include/drm/intel/ INTEL DRM I915 DRIVER (Meteor Lake, DG2 and older excluding Poulsbo, Moorestown and derivative) M: Jani Nikula @@ -11030,7 +11031,7 @@ F: Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon F: Documentation/gpu/i915.rst F: drivers/gpu/drm/ci/xfails/i915* F: drivers/gpu/drm/i915/ -F: include/drm/i915* +F: include/drm/intel/ F: include/uapi/drm/i915_drm.h INTEL DRM XE DRIVER (Lunar Lake and newer) @@ -11046,7 +11047,7 @@ T: git https://gitlab.freedesktop.org/drm/xe/kernel.git F: Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon F: Documentation/gpu/xe/ F: drivers/gpu/drm/xe/ -F: include/drm/xe* +F: include/drm/intel/ F: include/uapi/drm/xe_drm.h INTEL ETHERNET DRIVERS -- 2.39.2
[PATCH v2 08/10] drm: move xe_pciids.h under include/drm/intel
Clean up the top level include/drm directory by grouping all the Intel
specific files under a common subdirectory.
Cc: Daniel Vetter
Cc: Dave Airlie
Cc: Lucas De Marchi
Acked-by: Lucas De Marchi
Acked-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/xe_pci.c | 2 +-
include/drm/{ => intel}/xe_pciids.h | 0
2 files changed, 1 insertion(+), 1 deletion(-)
rename include/drm/{ => intel}/xe_pciids.h (100%)
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 1385d68c12c9..5655222aa4e1 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -13,7 +13,7 @@
#include
#include
-#include
+#include
#include "display/xe_display.h"
#include "regs/xe_gt_regs.h"
diff --git a/include/drm/xe_pciids.h b/include/drm/intel/xe_pciids.h
similarity index 100%
rename from include/drm/xe_pciids.h
rename to include/drm/intel/xe_pciids.h
--
2.39.2
[PATCH v2 07/10] drm: move i915_pciids.h under include/drm/intel
Clean up the top level include/drm directory by grouping all the Intel
specific files under a common subdirectory.
Cc: Daniel Vetter
Cc: Dave Airlie
Cc: Lucas De Marchi
Cc: Bjorn Helgaas
Acked-by: Lucas De Marchi
Acked-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
arch/x86/kernel/early-quirks.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_device.c | 2 +-
drivers/gpu/drm/i915/i915_pci.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c| 2 +-
include/drm/{ => intel}/i915_pciids.h | 0
5 files changed, 4 insertions(+), 4 deletions(-)
rename include/drm/{ => intel}/i915_pciids.h (100%)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index ec1a7943c228..29d1f9104e94 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -18,7 +18,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index cf093bc0cb28..11e6edc03358 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -3,7 +3,7 @@
* Copyright © 2023 Intel Corporation
*/
-#include
+#include
#include
#include
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 84cd2f0343a2..ce4dfd65fafa 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -24,7 +24,7 @@
#include
#include
-#include
+#include
#include "display/intel_display.h"
#include "display/intel_display_driver.h"
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 862f4b705227..d26de37719a7 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -25,7 +25,7 @@
#include
#include
-#include
+#include
#include "gt/intel_gt_regs.h"
#include "i915_drv.h"
diff --git a/include/drm/i915_pciids.h b/include/drm/intel/i915_pciids.h
similarity index 100%
rename from include/drm/i915_pciids.h
rename to include/drm/intel/i915_pciids.h
--
2.39.2
[PATCH v2 06/10] drm: move i915_pxp_tee_interface.h under include/drm/intel
Clean up the top level include/drm directory by grouping all the Intel
specific files under a common subdirectory.
Cc: Daniel Vetter
Cc: Dave Airlie
Cc: Lucas De Marchi
Cc: Tomas Winkler
Acked-by: Lucas De Marchi
Acked-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 2 +-
drivers/misc/mei/pxp/mei_pxp.c | 2 +-
include/drm/{ => intel}/i915_pxp_tee_interface.h | 0
3 files changed, 2 insertions(+), 2 deletions(-)
rename include/drm/{ => intel}/i915_pxp_tee_interface.h (100%)
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index 051b6cdcf721..1784153f0cf8 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -5,7 +5,7 @@
#include
-#include
+#include
#include
#include "gem/i915_gem_lmem.h"
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
index ed88d6df4397..2820d389c88e 100644
--- a/drivers/misc/mei/pxp/mei_pxp.c
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -20,7 +20,7 @@
#include
#include
#include
-#include
+#include
#include "mei_pxp.h"
diff --git a/include/drm/i915_pxp_tee_interface.h
b/include/drm/intel/i915_pxp_tee_interface.h
similarity index 100%
rename from include/drm/i915_pxp_tee_interface.h
rename to include/drm/intel/i915_pxp_tee_interface.h
--
2.39.2
[PATCH v2 05/10] drm: move i915_drm.h under include/drm/intel
Clean up the top level include/drm directory by grouping all the Intel
specific files under a common subdirectory.
v2: Also fix comment in intel_pci_config.h (Ilpo)
Cc: Daniel Vetter
Cc: Dave Airlie
Cc: Lucas De Marchi
Cc: Bjorn Helgaas
Cc: Hans de Goede
Cc: Ilpo Järvinen
Acked-by: Lucas De Marchi
Acked-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
arch/x86/kernel/early-quirks.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c| 2 +-
drivers/gpu/drm/i915/intel_pci_config.h| 2 +-
drivers/gpu/drm/i915/soc/intel_gmch.c | 2 +-
drivers/gpu/drm/xe/xe_ggtt.c | 2 +-
drivers/platform/x86/intel_ips.c | 2 +-
include/drm/{ => intel}/i915_drm.h | 0
9 files changed, 8 insertions(+), 8 deletions(-)
rename include/drm/{ => intel}/i915_drm.h (100%)
diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c
index 1c137771c5d2..ec1a7943c228 100644
--- a/arch/x86/kernel/early-quirks.c
+++ b/arch/x86/kernel/early-quirks.c
@@ -17,7 +17,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index ad6dd7f3259b..30595b2b63e1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -8,7 +8,7 @@
#include
#include
-#include
+#include
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 2717699c6591..206a5e0fedf1 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -9,7 +9,7 @@
#include
#include
-#include
+#include
#include
#include "display/intel_display.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index c9cb2a391942..70176be269d3 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -5,7 +5,7 @@
#include
-#include
+#include
#include "display/intel_display.h"
#include "display/intel_display_irq.h"
diff --git a/drivers/gpu/drm/i915/intel_pci_config.h
b/drivers/gpu/drm/i915/intel_pci_config.h
index 23b8e519f333..ebe040828e20 100644
--- a/drivers/gpu/drm/i915/intel_pci_config.h
+++ b/drivers/gpu/drm/i915/intel_pci_config.h
@@ -31,7 +31,7 @@ static inline int intel_mmio_bar(int graphics_ver)
}
}
-/* BSM in include/drm/i915_drm.h */
+/* BSM in include/drm/intel/i915_drm.h */
#define MCHBAR_I9150x44
#define MCHBAR_I9650x48
diff --git a/drivers/gpu/drm/i915/soc/intel_gmch.c
b/drivers/gpu/drm/i915/soc/intel_gmch.c
index 40874ebfb64c..734e9f2801ea 100644
--- a/drivers/gpu/drm/i915/soc/intel_gmch.c
+++ b/drivers/gpu/drm/i915/soc/intel_gmch.c
@@ -8,7 +8,7 @@
#include
#include
-#include
+#include
#include "i915_drv.h"
#include "intel_gmch.h"
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index b01a670fecb8..8ff91fd1b7c8 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -10,7 +10,7 @@
#include
#include
-#include
+#include
#include "regs/xe_gt_regs.h"
#include "regs/xe_gtt_defs.h"
diff --git a/drivers/platform/x86/intel_ips.c b/drivers/platform/x86/intel_ips.c
index 73ec4460a151..523fb18a7ace 100644
--- a/drivers/platform/x86/intel_ips.c
+++ b/drivers/platform/x86/intel_ips.c
@@ -59,7 +59,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#include "intel_ips.h"
diff --git a/include/drm/i915_drm.h b/include/drm/intel/i915_drm.h
similarity index 100%
rename from include/drm/i915_drm.h
rename to include/drm/intel/i915_drm.h
--
2.39.2
[PATCH v2 03/10] drm: move i915_component.h under include/drm/intel
Clean up the top level include/drm directory by grouping all the Intel
specific files under a common subdirectory.
v2: Also change Documentation/gpu/i915.rst (Andi)
Cc: Daniel Vetter
Cc: Dave Airlie
Cc: Lucas De Marchi
Cc: Tomas Winkler
Cc: Jaroslav Kysela
Cc: Takashi Iwai
Acked-by: Lucas De Marchi
Acked-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
Documentation/gpu/i915.rst | 2 +-
drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 2 +-
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 2 +-
drivers/gpu/drm/xe/xe_gsc_proxy.c| 2 +-
drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c | 2 +-
drivers/misc/mei/hdcp/mei_hdcp.c | 2 +-
drivers/misc/mei/pxp/mei_pxp.c | 2 +-
include/drm/{ => intel}/i915_component.h | 0
include/sound/hdaudio.h | 2 +-
11 files changed, 10 insertions(+), 10 deletions(-)
rename include/drm/{ => intel}/i915_component.h (100%)
diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 3113e36f14cf..ad59ae579237 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -150,7 +150,7 @@ High Definition Audio
.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c
:internal:
-.. kernel-doc:: include/drm/i915_component.h
+.. kernel-doc:: include/drm/intel/i915_component.h
:internal:
Intel HDMI LPE Audio Support
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 4c031e97f9a5..b9bafec06fb8 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -26,7 +26,7 @@
#include
#include
-#include
+#include
#include "i915_drv.h"
#include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 5767070248bb..ba3eca919900 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -13,7 +13,7 @@
#include
#include
-#include
+#include
#include "i915_drv.h"
#include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
index e7619d81353c..d8edd7c054c8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
@@ -5,7 +5,7 @@
#include
-#include
+#include
#include
#include "gt/intel_gt.h"
diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
index b00d6c280159..051b6cdcf721 100644
--- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
+++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
@@ -6,7 +6,7 @@
#include
#include
-#include
+#include
#include "gem/i915_gem_lmem.h"
#include "gt/intel_gt_print.h"
diff --git a/drivers/gpu/drm/xe/xe_gsc_proxy.c
b/drivers/gpu/drm/xe/xe_gsc_proxy.c
index cc3426fcfa89..aa812a2bc3ed 100644
--- a/drivers/gpu/drm/xe/xe_gsc_proxy.c
+++ b/drivers/gpu/drm/xe/xe_gsc_proxy.c
@@ -9,7 +9,7 @@
#include
#include
-#include
+#include
#include
#include "abi/gsc_proxy_commands_abi.h"
diff --git a/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
b/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
index d5fbaf5d0c8e..f52fe23a6c0b 100644
--- a/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
+++ b/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
@@ -17,7 +17,7 @@
#include
#include
#include
-#include
+#include
#include
/**
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index f8759a6c9ed3..e43ea536c947 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -23,7 +23,7 @@
#include
#include
#include
-#include
+#include
#include
#include "mei_hdcp.h"
diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c
index 49abc95677cd..ed88d6df4397 100644
--- a/drivers/misc/mei/pxp/mei_pxp.c
+++ b/drivers/misc/mei/pxp/mei_pxp.c
@@ -19,7 +19,7 @@
#include
#include
#include
-#include
+#include
#include
#include "mei_pxp.h"
diff --git a/include/drm/i915_component.h b/include/drm/intel/i915_component.h
similarity index 100%
rename from include/drm/i915_component.h
rename to include/drm/intel/i915_component.h
diff --git a/include/sound/hdaudio.h b/include/sound/hdaudio.h
index 1d10939e40af..7e39d486374a 100644
--- a/include/sound/hdaudio.h
+++ b/include/sound/hdaudio.h
@@ -18,7 +18,7 @@
#include
#include
#include
-#include
+#include
/* codec node id */
typedef u16 hda_nid_t;
--
2.39.2
[PATCH v2 04/10] drm: move intel_lpe_audio.h under include/drm/intel
Clean up the top level include/drm directory by grouping all the Intel
specific files under a common subdirectory.
Cc: Daniel Vetter
Cc: Dave Airlie
Cc: Lucas De Marchi
Cc: Jaroslav Kysela
Cc: Takashi Iwai
Reviewed-by: Andi Shyti
Acked-by: Lucas De Marchi
Acked-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/display/intel_lpe_audio.c | 2 +-
include/drm/{ => intel}/intel_lpe_audio.h | 0
sound/x86/intel_hdmi_audio.c | 2 +-
4 files changed, 3 insertions(+), 3 deletions(-)
rename include/drm/{ => intel}/intel_lpe_audio.h (100%)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 3767be0bdba8..06ec9ce7fe1c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -38,7 +38,7 @@
#include
#include
#include
-#include
+#include
#include "g4x_hdmi.h"
#include "i915_drv.h"
diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
index 93e6cac9a4ed..f11626176fe2 100644
--- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
@@ -68,7 +68,7 @@
#include
#include
-#include
+#include
#include "i915_drv.h"
#include "i915_irq.h"
diff --git a/include/drm/intel_lpe_audio.h b/include/drm/intel/intel_lpe_audio.h
similarity index 100%
rename from include/drm/intel_lpe_audio.h
rename to include/drm/intel/intel_lpe_audio.h
diff --git a/sound/x86/intel_hdmi_audio.c b/sound/x86/intel_hdmi_audio.c
index 02f5a7f9b728..d41ea09ffbe5 100644
--- a/sound/x86/intel_hdmi_audio.c
+++ b/sound/x86/intel_hdmi_audio.c
@@ -31,7 +31,7 @@
#include
#include
#include
-#include
+#include
#include "intel_hdmi_audio.h"
#define INTEL_HDMI_AUDIO_SUSPEND_DELAY_MS 5000
--
2.39.2
[PATCH v2 02/10] drm: move i915_gsc_proxy_mei_interface.h under include/drm/intel
Clean up the top level include/drm directory by grouping all the Intel
specific files under a common subdirectory.
Cc: Daniel Vetter
Cc: Dave Airlie
Cc: Lucas De Marchi
Cc: Tomas Winkler
Reviewed-by: Andi Shyti
Acked-by: Lucas De Marchi
Acked-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 2 +-
drivers/gpu/drm/xe/xe_gsc_proxy.c | 2 +-
drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c | 2 +-
include/drm/{ => intel}/i915_gsc_proxy_mei_interface.h | 0
4 files changed, 3 insertions(+), 3 deletions(-)
rename include/drm/{ => intel}/i915_gsc_proxy_mei_interface.h (100%)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
b/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
index a7d5465655f9..e7619d81353c 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c
@@ -6,7 +6,7 @@
#include
#include
-#include
+#include
#include "gt/intel_gt.h"
#include "gt/intel_gt_print.h"
diff --git a/drivers/gpu/drm/xe/xe_gsc_proxy.c
b/drivers/gpu/drm/xe/xe_gsc_proxy.c
index 6d6d1068cf23..cc3426fcfa89 100644
--- a/drivers/gpu/drm/xe/xe_gsc_proxy.c
+++ b/drivers/gpu/drm/xe/xe_gsc_proxy.c
@@ -10,7 +10,7 @@
#include
#include
-#include
+#include
#include "abi/gsc_proxy_commands_abi.h"
#include "regs/xe_gsc_regs.h"
diff --git a/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
b/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
index 89364bdbb129..d5fbaf5d0c8e 100644
--- a/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
+++ b/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c
@@ -18,7 +18,7 @@
#include
#include
#include
-#include
+#include
/**
* mei_gsc_proxy_send - Sends a proxy message to ME FW.
diff --git a/include/drm/i915_gsc_proxy_mei_interface.h
b/include/drm/intel/i915_gsc_proxy_mei_interface.h
similarity index 100%
rename from include/drm/i915_gsc_proxy_mei_interface.h
rename to include/drm/intel/i915_gsc_proxy_mei_interface.h
--
2.39.2
[PATCH v2 01/10] drm: move intel-gtt.h under include/drm/intel
Clean up the top level include/drm directory by grouping all the Intel
specific files under a common subdirectory.
Cc: Daniel Vetter
Cc: Dave Airlie
Cc: Lucas De Marchi
Reviewed-by: Andi Shyti
Acked-by: Lucas De Marchi
Acked-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/char/agp/intel-agp.c | 2 +-
drivers/char/agp/intel-gtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c| 2 +-
include/drm/{ => intel}/intel-gtt.h | 0
6 files changed, 5 insertions(+), 5 deletions(-)
rename include/drm/{ => intel}/intel-gtt.h (100%)
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index c518b3a9db04..eec80db6402d 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -12,7 +12,7 @@
#include
#include "agp.h"
#include "intel-agp.h"
-#include
+#include
static int intel_fetch_size(void)
{
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index bf6716ff863b..11f5cf853c46 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -25,7 +25,7 @@
#include
#include "agp.h"
#include "intel-agp.h"
-#include
+#include
#include
/*
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 0d0a0dc9f610..2717699c6591 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -10,7 +10,7 @@
#include
#include
-#include
+#include
#include "display/intel_display.h"
#include "gem/i915_gem_lmem.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
index 866c416afb73..59eed0a0ce90 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c
@@ -5,7 +5,7 @@
#include "intel_ggtt_gmch.h"
-#include
+#include
#include
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c
b/drivers/gpu/drm/i915/gt/intel_gt.c
index 626b166e67ef..a6c69a706fd7 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -4,7 +4,7 @@
*/
#include
-#include
+#include
#include "gem/i915_gem_internal.h"
#include "gem/i915_gem_lmem.h"
diff --git a/include/drm/intel-gtt.h b/include/drm/intel/intel-gtt.h
similarity index 100%
rename from include/drm/intel-gtt.h
rename to include/drm/intel/intel-gtt.h
--
2.39.2
[PATCH v2 00/10] drm: move Intel drm headers to a subdirectory
We've accumulated enough Intel specific header files under include/drm
that they warrant a subdirectory of their own. Clean up the top drm
header directory by moving the Intel files under include/drm/intel.
Since i915 is most impacted, I suggest merging the lot via
drm-intel-next. Please ack if this is fine for you.
BR,
Jani.
Jani Nikula (10):
drm: move intel-gtt.h under include/drm/intel
drm: move i915_gsc_proxy_mei_interface.h under include/drm/intel
drm: move i915_component.h under include/drm/intel
drm: move intel_lpe_audio.h under include/drm/intel
drm: move i915_drm.h under include/drm/intel
drm: move i915_pxp_tee_interface.h under include/drm/intel
drm: move i915_pciids.h under include/drm/intel
drm: move xe_pciids.h under include/drm/intel
drm: move i915_hdcp_interface.h under include/drm/intel
MAINTAINERS: update i915 and xe entries for include/drm/intel
Documentation/gpu/i915.rst | 2 +-
MAINTAINERS| 5 +++--
arch/x86/kernel/early-quirks.c | 4 ++--
drivers/char/agp/intel-agp.c | 2 +-
drivers/char/agp/intel-gtt.c | 2 +-
drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_device.c| 2 +-
drivers/gpu/drm/i915/display/intel_display_types.h | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
drivers/gpu/drm/i915/display/intel_lpe_audio.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 4 ++--
drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rps.c| 2 +-
drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 4 ++--
drivers/gpu/drm/i915/i915_pci.c| 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
drivers/gpu/drm/i915/intel_pci_config.h| 2 +-
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 4 ++--
drivers/gpu/drm/i915/soc/intel_gmch.c | 2 +-
drivers/gpu/drm/xe/display/xe_hdcp_gsc.c | 2 +-
drivers/gpu/drm/xe/xe_ggtt.c | 2 +-
drivers/gpu/drm/xe/xe_gsc_proxy.c | 4 ++--
drivers/gpu/drm/xe/xe_pci.c| 2 +-
drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c | 4 ++--
drivers/misc/mei/hdcp/mei_hdcp.c | 4 ++--
drivers/misc/mei/pxp/mei_pxp.c | 4 ++--
drivers/platform/x86/intel_ips.c | 2 +-
include/drm/{ => intel}/i915_component.h | 0
include/drm/{ => intel}/i915_drm.h | 0
include/drm/{ => intel}/i915_gsc_proxy_mei_interface.h | 0
include/drm/{ => intel}/i915_hdcp_interface.h | 0
include/drm/{ => intel}/i915_pciids.h | 0
include/drm/{ => intel}/i915_pxp_tee_interface.h | 0
include/drm/{ => intel}/intel-gtt.h| 0
include/drm/{ => intel}/intel_lpe_audio.h | 0
include/drm/{ => intel}/xe_pciids.h| 0
include/sound/hdaudio.h| 2 +-
sound/x86/intel_hdmi_audio.c | 2 +-
43 files changed, 44 insertions(+), 43 deletions(-)
rename include/drm/{ => intel}/i915_component.h (100%)
rename include/drm/{ => intel}/i915_drm.h (100%)
rename include/drm/{ => intel}/i915_gsc_proxy_mei_interface.h (100%)
rename include/drm/{ => intel}/i915_hdcp_interface.h (100%)
rename include/drm/{ => intel}/i915_pciids.h (100%)
rename include/drm/{ => intel}/i915_pxp_tee_interface.h (100%)
rename include/drm/{ => intel}/intel-gtt.h (100%)
rename include/drm/{ => intel}/intel_lpe_audio.h (100%)
rename include/drm/{ => intel}/xe_pciids.h (100%)
--
2.39.2
Re: [PATCH 3/3] drm/i915: Plumb the full atomic state into skl_ddb_add_affected_planes()
On Tue, 28 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> skl_ddb_add_affected_planes() needs the full atomic state. Instead
> of digging that out from dubious sources plumb it in explicitly.
>
> The wm counterpart (skl_wm_add_affected_planes()) already does
> things in the proper way.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 19 +--
> 1 file changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 2064f72da675..a2726364b34d 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -2429,12 +2429,14 @@ bool skl_ddb_allocation_overlaps(const struct
> skl_ddb_entry *ddb,
> }
>
> static int
> -skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
> - struct intel_crtc_state *new_crtc_state)
> +skl_ddb_add_affected_planes(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_atomic_state *state =
> to_intel_atomic_state(new_crtc_state->uapi.state);
> - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + const struct intel_crtc_state *old_crtc_state =
> + intel_atomic_get_old_crtc_state(state, crtc);
> + struct intel_crtc_state *new_crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_plane *plane;
>
> for_each_intel_plane_on_crtc(>drm, crtc, plane) {
> @@ -2489,7 +2491,6 @@ skl_compute_ddb(struct intel_atomic_state *state)
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> const struct intel_dbuf_state *old_dbuf_state;
> struct intel_dbuf_state *new_dbuf_state = NULL;
> - const struct intel_crtc_state *old_crtc_state;
> struct intel_crtc_state *new_crtc_state;
> struct intel_crtc *crtc;
> int ret, i;
> @@ -2577,14 +2578,12 @@ skl_compute_ddb(struct intel_atomic_state *state)
> return ret;
> }
>
> - for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> - new_crtc_state, i) {
> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> ret = skl_crtc_allocate_plane_ddb(state, crtc);
> if (ret)
> return ret;
>
> - ret = skl_ddb_add_affected_planes(old_crtc_state,
> - new_crtc_state);
> + ret = skl_ddb_add_affected_planes(state, crtc);
> if (ret)
> return ret;
> }
--
Jani Nikula, Intel
Re: [PATCH 2/3] drm/i915: Plumb the full atomic state into icl_check_nv12_planes()
On Tue, 28 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> icl_check_nv12_planes() needs the full atomic state. Instead of
> digging that out from dubious sources plumb it in explicitly.
>
> Signed-off-by: Ville Syrjälä
Are most to_intel_atomic_state() uses suspect...?
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 11 ++-
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 071ba95a1472..dbbc72494a46 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4033,11 +4033,12 @@ static int icl_add_linked_planes(struct
> intel_atomic_state *state)
> return 0;
> }
>
> -static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
> +static int icl_check_nv12_planes(struct intel_atomic_state *state,
> + struct intel_crtc *crtc)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct intel_atomic_state *state =
> to_intel_atomic_state(crtc_state->uapi.state);
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_crtc_state *crtc_state =
> + intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_plane *plane, *linked;
> struct intel_plane_state *plane_state;
> int i;
> @@ -5786,7 +5787,7 @@ static int intel_atomic_check_planes(struct
> intel_atomic_state *state)
> new_crtc_state, i) {
> u8 old_active_planes, new_active_planes;
>
> - ret = icl_check_nv12_planes(new_crtc_state);
> + ret = icl_check_nv12_planes(state, crtc);
> if (ret)
> return ret;
--
Jani Nikula, Intel
Re: [PATCH 1/3] drm/i915/cdclk: Plumb the full atomic state deeper
On Tue, 28 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Various parts of the cdclk code need access the full atomic
> state. Currently it's being dug out via the cdclk_state->base.state
> pointer, which is not great as that pointer isn't always valid.
> Instead plumb the full atomic state from the top so that it's
> clear that it is in fact valid.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 60 +-
> 1 file changed, 35 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index b78154c82a71..7ef8dcb1601a 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -113,7 +113,7 @@ struct intel_cdclk_funcs {
> void (*set_cdclk)(struct drm_i915_private *i915,
> const struct intel_cdclk_config *cdclk_config,
> enum pipe pipe);
> - int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
> + int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
> u8 (*calc_voltage_level)(int cdclk);
> };
>
> @@ -130,10 +130,11 @@ static void intel_cdclk_set_cdclk(struct
> drm_i915_private *dev_priv,
> dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe);
> }
>
> -static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
> - struct intel_cdclk_state
> *cdclk_config)
> +static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state)
> {
> - return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config);
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +
> + return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(state);
The dev_priv is an eyesore. Could already start doing:
const struct intel_display *display = to_intel_display(state->base.dev);
return display->funcs.cdclk->modeset_calc_cdclk(state);
And if you wanted to, could also make to_intel_display() handle struct
intel_atomic_state so it would only need to_intel_display(state).
Regardless,
Reviewed-by: Jani Nikula
> }
>
> static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
> @@ -2834,10 +2835,11 @@ int intel_crtc_compute_min_cdclk(const struct
> intel_crtc_state *crtc_state)
> return min_cdclk;
> }
>
> -static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
> +static int intel_compute_min_cdclk(struct intel_atomic_state *state)
> {
> - struct intel_atomic_state *state = cdclk_state->base.state;
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_cdclk_state *cdclk_state =
> + intel_atomic_get_new_cdclk_state(state);
> const struct intel_bw_state *bw_state;
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> @@ -2916,10 +2918,11 @@ static int intel_compute_min_cdclk(struct
> intel_cdclk_state *cdclk_state)
> * future platforms this code will need to be
> * adjusted.
> */
> -static int bxt_compute_min_voltage_level(struct intel_cdclk_state
> *cdclk_state)
> +static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
> {
> - struct intel_atomic_state *state = cdclk_state->base.state;
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_cdclk_state *cdclk_state =
> + intel_atomic_get_new_cdclk_state(state);
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
> u8 min_voltage_level;
> @@ -2952,13 +2955,14 @@ static int bxt_compute_min_voltage_level(struct
> intel_cdclk_state *cdclk_state)
> return min_voltage_level;
> }
>
> -static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
> +static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
> {
> - struct intel_atomic_state *state = cdclk_state->base.state;
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + struct intel_cdclk_state *cdclk_state =
> + intel_atomic_get_new_cdclk_state(state);
> int min_cdclk, cdclk;
>
> - min_cdclk = intel_compute_min_cdclk(cdclk_state);
> + min_cdclk = intel_compute_min_cdclk(state);
> if (min_cdclk < 0)
> return min_cdclk;
>
> @@ -2981,11 +2985,13 @@ static int vlv_modeset_calc_cdclk(struct
> intel_cdclk_state *cdclk_state)
> return 0;
> }
>
> -static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_sta
[PATCH 1/2] drm/i915/gvt: stop using drm_edid_block_valid()
We'll want to stop drm_edid_block_valid() usage. KVMGT is the last
user. Replace with drm_edid_valid(), which unfortunately requires an
allocated drm_edid. However, on the plus side, this would be required to
handle the TODO comment about EDID extension block support.
Signed-off-by: Jani Nikula
---
Cc: Zhenyu Wang
Cc: Zhi Wang
Cc: intel-gvt-...@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/i915/gvt/kvmgt.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index 4f74d867fe1a..7e3e5382c0c0 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -425,6 +425,18 @@ static const struct intel_vgpu_regops
intel_vgpu_regops_opregion = {
.release = intel_vgpu_reg_release_opregion,
};
+static bool edid_valid(const void *edid, size_t size)
+{
+ const struct drm_edid *drm_edid;
+ bool is_valid;
+
+ drm_edid = drm_edid_alloc(edid, size);
+ is_valid = drm_edid_valid(drm_edid);
+ drm_edid_free(drm_edid);
+
+ return is_valid;
+}
+
static int handle_edid_regs(struct intel_vgpu *vgpu,
struct vfio_edid_region *region, char *buf,
size_t count, u16 offset, bool is_write)
@@ -443,11 +455,7 @@ static int handle_edid_regs(struct intel_vgpu *vgpu,
switch (offset) {
case offsetof(struct vfio_region_gfx_edid, link_state):
if (data == VFIO_DEVICE_GFX_LINK_STATE_UP) {
- if (!drm_edid_block_valid(
- (u8 *)region->edid_blob,
- 0,
- true,
- NULL)) {
+ if (!edid_valid(region->edid_blob, EDID_SIZE)) {
gvt_vgpu_err("invalid EDID blob\n");
return -EINVAL;
}
--
2.39.2
[PATCH 2/2] drm/edid: make drm_edid_block_valid() static
drm_edid_block_valid() is no longer used outside of drm_edid.c. Make it
static.
Signed-off-by: Jani Nikula
---
Cc: Zhenyu Wang
Cc: Zhi Wang
Cc: intel-gvt-...@lists.freedesktop.org
Cc: intel-gfx@lists.freedesktop.org
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/drm_edid.c | 17 -
include/drm/drm_edid.h | 2 --
2 files changed, 4 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index f68a41eeb1fa..13b3fd351b16 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1966,22 +1966,14 @@ static void edid_block_dump(const char *level, const
void *block, int block_num)
block, EDID_LENGTH, false);
}
-/**
- * drm_edid_block_valid - Sanity check the EDID block (base or extension)
- * @_block: pointer to raw EDID block
- * @block_num: type of block to validate (0 for base, extension otherwise)
- * @print_bad_edid: if true, dump bad EDID blocks to the console
- * @edid_corrupt: if true, the header or checksum is invalid
- *
+/*
* Validate a base or extension EDID block and optionally dump bad blocks to
* the console.
- *
- * Return: True if the block is valid, false otherwise.
*/
-bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
- bool *edid_corrupt)
+static bool drm_edid_block_valid(void *_block, int block_num, bool
print_bad_edid,
+bool *edid_corrupt)
{
- struct edid *block = (struct edid *)_block;
+ struct edid *block = _block;
enum edid_block_status status;
bool is_base_block = block_num == 0;
bool valid;
@@ -2024,7 +2016,6 @@ bool drm_edid_block_valid(u8 *_block, int block_num, bool
print_bad_edid,
return valid;
}
-EXPORT_SYMBOL(drm_edid_block_valid);
/**
* drm_edid_is_valid - sanity check EDID data
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 6bdfa254a1c1..eaac5e665892 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -440,8 +440,6 @@ int drm_add_modes_noedid(struct drm_connector *connector,
int hdisplay, int vdisplay);
int drm_edid_header_is_valid(const void *edid);
-bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
- bool *edid_corrupt);
bool drm_edid_is_valid(struct edid *edid);
void drm_edid_get_monitor_name(const struct edid *edid, char *name,
int buflen);
--
2.39.2
[PATCH 2/2] drm/i915: reduce includes in intel_clock_gating.c
With the refactoring in the file, some excessive includes were left behind and are now unnecessary. Remove. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_clock_gating.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index db4fbb6a803d..26c4dbda076e 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -26,11 +26,7 @@ */ #include "display/i9xx_plane_regs.h" -#include "display/intel_de.h" #include "display/intel_display.h" -#include "display/intel_display_trace.h" -#include "display/intel_fbc_regs.h" -#include "display/skl_watermark.h" #include "gt/intel_engine_regs.h" #include "gt/intel_gt.h" -- 2.39.2
[PATCH 1/2] drm/i915: drop unnecessary i915_reg.h includes
With the register header refactoring, some of the includes of i915_reg.h have become unnecessary. Remove. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/dvo_ns2501.c | 1 - drivers/gpu/drm/i915/display/intel_atomic.c | 1 - drivers/gpu/drm/i915/display/intel_atomic_plane.c | 1 - drivers/gpu/drm/i915/display/intel_dkl_phy.c | 1 - drivers/gpu/drm/i915/display/intel_dsb.c | 1 - drivers/gpu/drm/i915/display/intel_sprite.c | 1 - drivers/gpu/drm/i915/display/intel_vdsc.c | 1 - 7 files changed, 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/dvo_ns2501.c b/drivers/gpu/drm/i915/display/dvo_ns2501.c index 1df212fb000e..21486008dae9 100644 --- a/drivers/gpu/drm/i915/display/dvo_ns2501.c +++ b/drivers/gpu/drm/i915/display/dvo_ns2501.c @@ -27,7 +27,6 @@ */ #include "i915_drv.h" -#include "i915_reg.h" #include "intel_display_types.h" #include "intel_dvo_dev.h" diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index 7a77ae3dc394..76aa10b6f647 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -35,7 +35,6 @@ #include #include "i915_drv.h" -#include "i915_reg.h" #include "intel_atomic.h" #include "intel_cdclk.h" #include "intel_display_types.h" diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index a2a827070c33..a4ce39a7f265 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -39,7 +39,6 @@ #include #include "i915_config.h" -#include "i915_reg.h" #include "i9xx_plane_regs.h" #include "intel_atomic_plane.h" #include "intel_cdclk.h" diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c b/drivers/gpu/drm/i915/display/intel_dkl_phy.c index a001232ad445..b146b4c46943 100644 --- a/drivers/gpu/drm/i915/display/intel_dkl_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c @@ -4,7 +4,6 @@ */ #include "i915_drv.h" -#include "i915_reg.h" #include "intel_de.h" #include "intel_display.h" diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 4baaa92ceaec..bcc9de047fac 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -6,7 +6,6 @@ #include "i915_drv.h" #include "i915_irq.h" -#include "i915_reg.h" #include "intel_crtc.h" #include "intel_de.h" #include "intel_display_types.h" diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 36a253a19c74..e1c907f601da 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -39,7 +39,6 @@ #include #include "i915_drv.h" -#include "i915_reg.h" #include "i9xx_plane.h" #include "intel_atomic_plane.h" #include "intel_de.h" diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 17d6572f9d0a..d76e70846a8c 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -10,7 +10,6 @@ #include #include "i915_drv.h" -#include "i915_reg.h" #include "intel_crtc.h" #include "intel_de.h" #include "intel_display_types.h" -- 2.39.2
[PULL] drm-intel-fixes
Hi Dave & Sima - drm-intel-fixes-2024-05-30: drm/i915 fixes for v6.10-rc2: - Fix a race in audio component by registering it later - Make DPT object unshrinkable to avoid shrinking when framebuffer has not shrunk - Fix CCS id calculation to fix a perf regression - Fix selftest caching mode - Fix FIELD_PREP compiler warnings - Fix indefinite wait for GT wakeref release - Revert overeager multi-gt pm reference removal BR, Jani. The following changes since commit 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0: Linux 6.10-rc1 (2024-05-26 15:20:12 -0700) are available in the Git repository at: https://gitlab.freedesktop.org/drm/i915/kernel.git tags/drm-intel-fixes-2024-05-30 for you to fetch changes up to 75800e2e4203ea83bbc9d4f63ad97ea582244a08: drm/i915: Fix audio component initialization (2024-05-29 11:35:48 +0300) drm/i915 fixes for v6.10-rc2: - Fix a race in audio component by registering it later - Make DPT object unshrinkable to avoid shrinking when framebuffer has not shrunk - Fix CCS id calculation to fix a perf regression - Fix selftest caching mode - Fix FIELD_PREP compiler warnings - Fix indefinite wait for GT wakeref release - Revert overeager multi-gt pm reference removal Andi Shyti (1): drm/i915/gt: Fix CCS id's calculation for CCS mode setting Arnd Bergmann (1): drm/i915/guc: avoid FIELD_PREP warning Chris Wilson (1): drm/i915/gt: Disarm breadcrumbs if engines are already idle Imre Deak (1): drm/i915: Fix audio component initialization Janusz Krzysztofik (1): Revert "drm/i915: Remove extra multi-gt pm-references" Nirmoy Das (1): drm/i915/selftests: Set always_coherent to false when reading from CPU Vidya Srinivas (1): drm/i915/dpt: Make DPT object unshrinkable drivers/gpu/drm/i915/display/intel_audio.c | 32 ++ drivers/gpu/drm/i915/display/intel_audio.h | 1 + .../gpu/drm/i915/display/intel_display_driver.c| 2 ++ drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 18 drivers/gpu/drm/i915/gem/i915_gem_object.h | 4 ++- .../gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 2 +- drivers/gpu/drm/i915/gt/intel_breadcrumbs.c| 15 +- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c| 2 +- drivers/gpu/drm/i915/gt/intel_gt_types.h | 8 ++ drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h | 6 ++-- 11 files changed, 71 insertions(+), 25 deletions(-) -- Jani Nikula, Intel
Re: [PATCH 07/12] drm/i915: extend the fsb_freq initialization to more platforms
On Wed, 29 May 2024, Matt Roper wrote:
> On Tue, May 28, 2024 at 05:24:56PM +0300, Jani Nikula wrote:
>> Initialize fsb frequency for more platforms to be able to use it for GT
>> clock and rawclk frequency initialization.
>>
>> Note: There's a discrepancy between existing pnv_fsb_freq() and
>> i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is
>> mobile.
>
> Do you just mean we assume PNV always treats CLKCFG the same way mobile
> platforms do? Because we have both mobile and non-mobile platforms
> defined in the driver (pnv_m_info vs pnv_g_info) and that matches
> https://ark.intel.com/content/www/us/en/ark/products/codename/32201/products-formerly-pineview.html
> that lists both desktop and mobile.
Yeah. The problem is, current code in intel_dram.c and intel_cdclk.c
interpret the CLKCFG register differently for desktop PNV. At least one
of them is wrong. Basically I just picked one, and secretly hoped Ville
would tell me. ;)
BR,
Jani.
>
>
> Matt
>
>>
>> FIXME: What should the default or failure mode be when the value is
>> unknown?
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/soc/intel_dram.c | 54 ---
>> 1 file changed, 40 insertions(+), 14 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
>> b/drivers/gpu/drm/i915/soc/intel_dram.c
>> index ace9372244a4..74b5b70e91f9 100644
>> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
>> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
>> @@ -142,24 +142,50 @@ static void detect_mem_freq(struct drm_i915_private
>> *i915)
>> drm_dbg(>drm, "DDR speed: %d kHz\n", i915->mem_freq);
>> }
>>
>> -static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
>> +static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
>> {
>> u32 fsb;
>>
>> fsb = intel_uncore_read(>uncore, CLKCFG) & CLKCFG_FSB_MASK;
>>
>> -switch (fsb) {
>> -case CLKCFG_FSB_400:
>> -return 40;
>> -case CLKCFG_FSB_533:
>> -return 53;
>> -case CLKCFG_FSB_667:
>> -return 67;
>> -case CLKCFG_FSB_800:
>> -return 80;
>> +if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {
>> +switch (fsb) {
>> +case CLKCFG_FSB_400:
>> +return 40;
>> +case CLKCFG_FSB_533:
>> +return 53;
>> +case CLKCFG_FSB_667:
>> +return 67;
>> +case CLKCFG_FSB_800:
>> +return 80;
>> +case CLKCFG_FSB_1067:
>> +return 107;
>> +case CLKCFG_FSB_1333:
>> +return 133;
>> +default:
>> +MISSING_CASE(fsb);
>> +return 133;
>> +}
>> +} else {
>> +switch (fsb) {
>> +case CLKCFG_FSB_400_ALT:
>> +return 40;
>> +case CLKCFG_FSB_533:
>> +return 53;
>> +case CLKCFG_FSB_667:
>> +return 67;
>> +case CLKCFG_FSB_800:
>> +return 80;
>> +case CLKCFG_FSB_1067_ALT:
>> +return 107;
>> +case CLKCFG_FSB_1333_ALT:
>> +return 133;
>> +case CLKCFG_FSB_1600_ALT:
>> +return 160;
>> +default:
>> +return 53;
>> +}
>> }
>> -
>> -return 0;
>> }
>>
>> static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
>> @@ -193,8 +219,8 @@ static void detect_fsb_freq(struct drm_i915_private
>> *i915)
>> {
>> if (GRAPHICS_VER(i915) == 5)
>> i915->fsb_freq = ilk_fsb_freq(i915);
>> -else if (IS_PINEVIEW(i915))
>> -i915->fsb_freq = pnv_fsb_freq(i915);
>> +else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
>> +i915->fsb_freq = i9xx_fsb_freq(i915);
>>
>> if (i915->fsb_freq)
>> drm_dbg(>drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
>> --
>> 2.39.2
>>
--
Jani Nikula, Intel
Re: [PATCH 06/12] drm/i915: convert fsb_freq and mem_freq to kHz
On Wed, 29 May 2024, Matt Roper wrote:
> On Tue, May 28, 2024 at 05:24:55PM +0300, Jani Nikula wrote:
>> We'll want to use fsb frequency for deriving GT clock and rawclk
>> frequencies in the future. Increase the accuracy by converting to
>> kHz. Do the same for mem freq to be aligned.
>>
>> Round the frequencies ending in 666 to 667.
>>
>> Signed-off-by: Jani Nikula
>
> Would it be worth adding a "_khz" suffix to the structure fields to help
> clarify the units?
Thought about it, but decided kHz is pretty much the norm, and it's
everything else that should have a suffix to clarify the units!
> Either way,
>
> Reviewed-by: Matt Roper
Thanks,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/display/i9xx_wm.c | 6 ++--
>> drivers/gpu/drm/i915/gt/intel_rps.c| 4 +--
>> drivers/gpu/drm/i915/soc/intel_dram.c | 50 +-
>> 3 files changed, 30 insertions(+), 30 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
>> b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> index 8b8a0f305c3a..08c5d122af8f 100644
>> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
>> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> @@ -83,14 +83,14 @@ static const struct cxsr_latency
>> *pnv_get_cxsr_latency(struct drm_i915_private *
>>
>> if (is_desktop == latency->is_desktop &&
>> i915->is_ddr3 == latency->is_ddr3 &&
>> -i915->fsb_freq == latency->fsb_freq &&
>> -i915->mem_freq == latency->mem_freq)
>> +DIV_ROUND_CLOSEST(i915->fsb_freq, 1000) ==
>> latency->fsb_freq &&
>> +DIV_ROUND_CLOSEST(i915->mem_freq, 1000) ==
>> latency->mem_freq)
>> return latency;
>> }
>>
>> err:
>> drm_dbg_kms(>drm,
>> -"Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u
>> MHz\n",
>> +"Could not find CxSR latency for DDR%s, FSB %u kHz, MEM %u
>> kHz\n",
>> i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
>>
>> return NULL;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
>> b/drivers/gpu/drm/i915/gt/intel_rps.c
>> index c9cb2a391942..5d3de1cddcf6 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
>> @@ -280,9 +280,9 @@ static void gen5_rps_init(struct intel_rps *rps)
>> u32 rgvmodectl;
>> int c_m, i;
>>
>> -if (i915->fsb_freq <= 3200)
>> +if (i915->fsb_freq <= 320)
>> c_m = 0;
>> -else if (i915->fsb_freq <= 4800)
>> +else if (i915->fsb_freq <= 480)
>> c_m = 1;
>> else
>> c_m = 2;
>> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
>> b/drivers/gpu/drm/i915/soc/intel_dram.c
>> index 266ed6cfa485..ace9372244a4 100644
>> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
>> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
>> @@ -56,11 +56,11 @@ static unsigned int pnv_mem_freq(struct drm_i915_private
>> *dev_priv)
>>
>> switch (tmp & CLKCFG_MEM_MASK) {
>> case CLKCFG_MEM_533:
>> -return 533;
>> +return 53;
>> case CLKCFG_MEM_667:
>> -return 667;
>> +return 67;
>> case CLKCFG_MEM_800:
>> -return 800;
>> +return 80;
>> }
>>
>> return 0;
>> @@ -73,13 +73,13 @@ static unsigned int ilk_mem_freq(struct drm_i915_private
>> *dev_priv)
>> ddrpll = intel_uncore_read16(_priv->uncore, DDRMPLL1);
>> switch (ddrpll & 0xff) {
>> case 0xc:
>> -return 800;
>> +return 80;
>> case 0x10:
>> -return 1066;
>> +return 107;
>> case 0x14:
>> -return 1333;
>> +return 133;
>> case 0x18:
>> -return 1600;
>> +return 160;
>> default:
>> drm_dbg(_priv->drm, "unknown memory frequency 0x%02x\n",
>> ddrpll & 0xff);
>> @@ -97,9 +97,9 @@ static unsigned int chv_mem_freq(struct drm_i915_private
>> *i915)
>>
>> switch ((val >> 2) & 0x7) {
>> case 3:
>> -return 2000;
>> +return 2
Re: [PATCH 02/12] drm/i915/wm: clarify logging on not finding CxSR latency config
On Wed, 29 May 2024, Matt Roper wrote:
> On Tue, May 28, 2024 at 05:24:51PM +0300, Jani Nikula wrote:
>> Clarify and unify the logging on not finding PNV CxSR latency config.
>>
>> Signed-off-by: Jani Nikula
>> ---
>> drivers/gpu/drm/i915/display/i9xx_wm.c | 17 +++--
>> 1 file changed, 7 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
>> b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> index 8657ec0abd2d..8b8a0f305c3a 100644
>> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
>> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
>> @@ -75,7 +75,7 @@ static const struct cxsr_latency
>> *pnv_get_cxsr_latency(struct drm_i915_private *
>> int i;
>>
>> if (i915->fsb_freq == 0 || i915->mem_freq == 0)
>> -return NULL;
>> +goto err;
>
> Is there even a need for this check? 0/0 will fail to match anything in
> the table and will just drop through to the debug message anyway, right?
True, could be dropped. I just thought it was more explicit this way,
but maybe fewer lines is better.
BR,
Jani.
>
>
> Matt
>
>>
>> for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
>> const struct cxsr_latency *latency = _latency_table[i];
>> @@ -88,7 +88,10 @@ static const struct cxsr_latency
>> *pnv_get_cxsr_latency(struct drm_i915_private *
>> return latency;
>> }
>>
>> -drm_dbg_kms(>drm, "Unknown FSB/MEM found, disable CxSR\n");
>> +err:
>> +drm_dbg_kms(>drm,
>> +"Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u
>> MHz\n",
>> +i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
>>
>> return NULL;
>> }
>> @@ -637,8 +640,7 @@ static void pnv_update_wm(struct drm_i915_private
>> *dev_priv)
>>
>> latency = pnv_get_cxsr_latency(dev_priv);
>> if (!latency) {
>> -drm_dbg_kms(_priv->drm,
>> -"Unknown FSB/MEM found, disable CxSR\n");
>> +drm_dbg_kms(_priv->drm, "Unknown FSB/MEM, disabling
>> CxSR\n");
>> intel_set_memory_cxsr(dev_priv, false);
>> return;
>> }
>> @@ -4023,12 +4025,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
>> dev_priv->display.funcs.wm = _wm_funcs;
>> } else if (IS_PINEVIEW(dev_priv)) {
>> if (!pnv_get_cxsr_latency(dev_priv)) {
>> -drm_info(_priv->drm,
>> - "failed to find known CxSR latency "
>> - "(found ddr%s fsb freq %d, mem freq %d), "
>> - "disabling CxSR\n",
>> - (dev_priv->is_ddr3 == 1) ? "3" : "2",
>> - dev_priv->fsb_freq, dev_priv->mem_freq);
>> +drm_info(_priv->drm, "Unknown FSB/MEM, disabling
>> CxSR\n");
>> /* Disable CxSR and never update its watermark again */
>> intel_set_memory_cxsr(dev_priv, false);
>> dev_priv->display.funcs.wm = _funcs;
>> --
>> 2.39.2
>>
--
Jani Nikula, Intel
[PATCH 10/10] drm/xe/display: drop i915_drv.h include from xe code
Drop i915_drv.h include from xe display code as much as possible, and
switch to xe types where necessary.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/display/ext/i915_irq.c | 1 -
drivers/gpu/drm/xe/display/intel_fb_bo.c | 5 ++---
drivers/gpu/drm/xe/display/intel_fbdev_fb.c | 17 -
drivers/gpu/drm/xe/display/xe_dsb_buffer.c| 9 -
drivers/gpu/drm/xe/display/xe_fb_pin.c| 1 -
drivers/gpu/drm/xe/display/xe_plane_initial.c | 18 --
6 files changed, 22 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/ext/i915_irq.c
b/drivers/gpu/drm/xe/display/ext/i915_irq.c
index bee191a4a97d..eb40f1cb44f6 100644
--- a/drivers/gpu/drm/xe/display/ext/i915_irq.c
+++ b/drivers/gpu/drm/xe/display/ext/i915_irq.c
@@ -3,7 +3,6 @@
* Copyright © 2023 Intel Corporation
*/
-#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_reg.h"
#include "intel_uncore.h"
diff --git a/drivers/gpu/drm/xe/display/intel_fb_bo.c
b/drivers/gpu/drm/xe/display/intel_fb_bo.c
index b89cda053d2c..f835492f73fb 100644
--- a/drivers/gpu/drm/xe/display/intel_fb_bo.c
+++ b/drivers/gpu/drm/xe/display/intel_fb_bo.c
@@ -6,7 +6,6 @@
#include
#include
-#include "i915_drv.h"
#include "intel_display_types.h"
#include "intel_fb_bo.h"
#include "xe_bo.h"
@@ -26,7 +25,7 @@ int intel_fb_bo_framebuffer_init(struct intel_framebuffer
*intel_fb,
struct xe_bo *bo,
struct drm_mode_fb_cmd2 *mode_cmd)
{
- struct drm_i915_private *i915 = to_i915(bo->ttm.base.dev);
+ struct xe_device *xe = to_xe_device(bo->ttm.base.dev);
int ret;
xe_bo_get(bo);
@@ -42,7 +41,7 @@ int intel_fb_bo_framebuffer_init(struct intel_framebuffer
*intel_fb,
* mode when the boect is VM_BINDed, so we can only set
* coherency with display when unbound.
*/
- if (XE_IOCTL_DBG(i915, !list_empty(>ttm.base.gpuva.list))) {
+ if (XE_IOCTL_DBG(xe, !list_empty(>ttm.base.gpuva.list))) {
ttm_bo_unreserve(>ttm);
ret = -EINVAL;
goto err;
diff --git a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
index 5ecc7d467934..3a2f3a5ac2f9 100644
--- a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
+++ b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
@@ -5,7 +5,6 @@
#include
-#include "i915_drv.h"
#include "intel_display_types.h"
#include "intel_fbdev_fb.h"
#include "xe_bo.h"
@@ -17,7 +16,7 @@ struct intel_framebuffer *intel_fbdev_fb_alloc(struct
drm_fb_helper *helper,
{
struct drm_framebuffer *fb;
struct drm_device *dev = helper->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct xe_device *xe = to_xe_device(dev);
struct drm_mode_fb_cmd2 mode_cmd = {};
struct drm_i915_gem_object *obj;
int size;
@@ -38,26 +37,26 @@ struct intel_framebuffer *intel_fbdev_fb_alloc(struct
drm_fb_helper *helper,
size = PAGE_ALIGN(size);
obj = ERR_PTR(-ENODEV);
- if (!IS_DGFX(dev_priv)) {
- obj = xe_bo_create_pin_map(dev_priv,
xe_device_get_root_tile(dev_priv),
+ if (!IS_DGFX(xe)) {
+ obj = xe_bo_create_pin_map(xe, xe_device_get_root_tile(xe),
NULL, size,
ttm_bo_type_kernel,
XE_BO_FLAG_SCANOUT |
XE_BO_FLAG_STOLEN |
XE_BO_FLAG_PINNED);
if (!IS_ERR(obj))
- drm_info(_priv->drm, "Allocated fbdev into
stolen\n");
+ drm_info(>drm, "Allocated fbdev into stolen\n");
else
- drm_info(_priv->drm, "Allocated fbdev into stolen
failed: %li\n", PTR_ERR(obj));
+ drm_info(>drm, "Allocated fbdev into stolen failed:
%li\n", PTR_ERR(obj));
}
if (IS_ERR(obj)) {
- obj = xe_bo_create_pin_map(dev_priv,
xe_device_get_root_tile(dev_priv), NULL, size,
+ obj = xe_bo_create_pin_map(xe, xe_device_get_root_tile(xe),
NULL, size,
ttm_bo_type_kernel,
XE_BO_FLAG_SCANOUT |
-
XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(dev_priv)) |
+
XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) |
XE_BO_FLAG_PINNED);
}
if (IS_ERR(obj)) {
- drm_err(_priv->drm, "failed to allocate framebuffer
(%pe)\n", obj);
+ drm_err(&
[PATCH 09/10] drm/xe/display: reduce includes in compat i915_drv.h
Remove some unnecessary includes, and replace xe_device.h with the
sufficient xe_device_types.h.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index fb37da4850c5..2feedddf1e40 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -12,11 +12,9 @@
#include
-#include "soc/intel_pch.h"
-#include "xe_device.h"
-#include "i915_reg_defs.h"
#include "i915_utils.h"
#include "intel_runtime_pm.h"
+#include "xe_device_types.h"
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
--
2.39.2
[PATCH 05/10] drm/i915/display: include intel_step.h where needed
Include what you use. With this, we can drop the include along with xe_step.h from xe compat i915_drv.h. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dmc.c | 1 + drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index b5ebb0f5b269..852c11aa3205 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -31,6 +31,7 @@ #include "intel_de.h" #include "intel_dmc.h" #include "intel_dmc_regs.h" +#include "intel_step.h" /** * DOC: DMC Firmware Support diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index e5966f07a924..3e930ce25c90 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -18,10 +18,8 @@ #include "xe_device.h" #include "xe_bo.h" #include "xe_pm.h" -#include "xe_step.h" #include "i915_reg_defs.h" #include "i915_utils.h" -#include "intel_step.h" #include "intel_runtime_pm.h" #include -- 2.39.2
[PATCH 08/10] drm/xe/display: move compat runtime pm stubs to the correct file
Move things that belong to intel_runtime_pm.h to the correct place. Add
missing header guards while at it.
Signed-off-by: Jani Nikula
---
.../gpu/drm/xe/compat-i915-headers/i915_drv.h | 48 -
.../xe/compat-i915-headers/intel_runtime_pm.h | 51 +++
2 files changed, 51 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index 60544633ddf7..fb37da4850c5 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -14,11 +14,9 @@
#include "soc/intel_pch.h"
#include "xe_device.h"
-#include "xe_pm.h"
#include "i915_reg_defs.h"
#include "i915_utils.h"
#include "intel_runtime_pm.h"
-#include
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
@@ -113,58 +111,12 @@ static inline struct drm_i915_private
*kdev_to_i915(struct device *kdev)
#define HAS_128_BYTE_Y_TILING(xe) (xe || 1)
-#include "intel_wakeref.h"
-
-static inline intel_wakeref_t intel_runtime_pm_get(struct xe_runtime_pm *pm)
-{
- struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm);
-
- return xe_pm_runtime_resume_and_get(xe);
-}
-
-static inline intel_wakeref_t intel_runtime_pm_get_if_in_use(struct
xe_runtime_pm *pm)
-{
- struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm);
-
- return xe_pm_runtime_get_if_in_use(xe);
-}
-
-static inline intel_wakeref_t intel_runtime_pm_get_noresume(struct
xe_runtime_pm *pm)
-{
- struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm);
-
- xe_pm_runtime_get_noresume(xe);
- return true;
-}
-
-static inline void intel_runtime_pm_put_unchecked(struct xe_runtime_pm *pm)
-{
- struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm);
-
- xe_pm_runtime_put(xe);
-}
-
-static inline void intel_runtime_pm_put(struct xe_runtime_pm *pm,
intel_wakeref_t wakeref)
-{
- if (wakeref)
- intel_runtime_pm_put_unchecked(pm);
-}
-
-#define intel_runtime_pm_get_raw intel_runtime_pm_get
-#define intel_runtime_pm_put_raw intel_runtime_pm_put
-#define assert_rpm_wakelock_held(x) do { } while (0)
-#define assert_rpm_raw_wakeref_held(x) do { } while (0)
-
#define I915_PRIORITY_DISPLAY 0
struct i915_sched_attr {
int priority;
};
#define i915_gem_fence_wait_priority(fence, attr) do { (void) attr; } while (0)
-#define with_intel_runtime_pm(rpm, wf) \
- for ((wf) = intel_runtime_pm_get(rpm); (wf); \
-intel_runtime_pm_put((rpm), (wf)), (wf) = 0)
-
#define pdev_to_i915 pdev_to_xe_device
#define RUNTIME_INFO(xe) (&(xe)->info.i915_runtime)
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h
b/drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h
index 89da3cc62f39..8c7b315aa8ac 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h
@@ -3,7 +3,12 @@
* Copyright © 2023 Intel Corporation
*/
+#ifndef __INTEL_RUNTIME_PM_H__
+#define __INTEL_RUNTIME_PM_H__
+
#include "intel_wakeref.h"
+#include "xe_device_types.h"
+#include "xe_pm.h"
#define intel_runtime_pm xe_runtime_pm
@@ -14,3 +19,49 @@ static inline void disable_rpm_wakeref_asserts(void *rpm)
static inline void enable_rpm_wakeref_asserts(void *rpm)
{
}
+
+static inline intel_wakeref_t intel_runtime_pm_get(struct xe_runtime_pm *pm)
+{
+ struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm);
+
+ return xe_pm_runtime_resume_and_get(xe);
+}
+
+static inline intel_wakeref_t intel_runtime_pm_get_if_in_use(struct
xe_runtime_pm *pm)
+{
+ struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm);
+
+ return xe_pm_runtime_get_if_in_use(xe);
+}
+
+static inline intel_wakeref_t intel_runtime_pm_get_noresume(struct
xe_runtime_pm *pm)
+{
+ struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm);
+
+ xe_pm_runtime_get_noresume(xe);
+ return true;
+}
+
+static inline void intel_runtime_pm_put_unchecked(struct xe_runtime_pm *pm)
+{
+ struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm);
+
+ xe_pm_runtime_put(xe);
+}
+
+static inline void intel_runtime_pm_put(struct xe_runtime_pm *pm,
intel_wakeref_t wakeref)
+{
+ if (wakeref)
+ intel_runtime_pm_put_unchecked(pm);
+}
+
+#define intel_runtime_pm_get_raw intel_runtime_pm_get
+#define intel_runtime_pm_put_raw intel_runtime_pm_put
+#define assert_rpm_wakelock_held(x) do { } while (0)
+#define assert_rpm_raw_wakeref_held(x) do { } while (0)
+
+#define with_intel_runtime_pm(rpm, wf) \
+ for ((wf) = intel_runtime_pm_get(rpm); (wf); \
+intel_runtime_pm_put((rpm), (wf)), (wf) = 0)
+
+#endif
--
2.39.2
[PATCH 07/10] drm/xe/display: move compat uncore stubs to the correct file
Move things that belong to intel_uncore.h to the correct place.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 5 -
drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h | 5 +
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index 7b3f53427b03..60544633ddf7 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -155,11 +155,6 @@ static inline void intel_runtime_pm_put(struct
xe_runtime_pm *pm, intel_wakeref_
#define assert_rpm_wakelock_held(x) do { } while (0)
#define assert_rpm_raw_wakeref_held(x) do { } while (0)
-#define intel_uncore_forcewake_get(x, y) do { } while (0)
-#define intel_uncore_forcewake_put(x, y) do { } while (0)
-
-#define intel_uncore_arm_unclaimed_mmio_detection(x) do { } while (0)
-
#define I915_PRIORITY_DISPLAY 0
struct i915_sched_attr {
int priority;
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
index ef79793caa72..083c4da2ea41 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
@@ -172,4 +172,9 @@ static inline void __iomem *intel_uncore_regs(struct
intel_uncore *uncore)
#define raw_reg_write(base, reg, value) \
writel(value, base + i915_mmio_reg_offset(reg))
+#define intel_uncore_forcewake_get(x, y) do { } while (0)
+#define intel_uncore_forcewake_put(x, y) do { } while (0)
+
+#define intel_uncore_arm_unclaimed_mmio_detection(x) do { } while (0)
+
#endif /* __INTEL_UNCORE_H__ */
--
2.39.2
[PATCH 06/10] drm/i915/display: include xe_bo.h, gem_object_types etc. where needed
Include what you use. The dependencies on the headers, and what they
include, is a bit convoluted. Add xe compat gem/gem_object_types.h. Fix
all the places needed.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 1 +
drivers/gpu/drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_fb.c | 1 +
drivers/gpu/drm/i915/display/intel_fbdev.c| 1 +
.../compat-i915-headers/gem/i915_gem_object_types.h | 11 +++
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 4
drivers/gpu/drm/xe/display/intel_fb_bo.c | 2 ++
drivers/gpu/drm/xe/display/intel_fbdev_fb.c | 9 -
drivers/gpu/drm/xe/display/xe_fb_pin.c| 5 +++--
drivers/gpu/drm/xe/display/xe_plane_initial.c | 1 +
10 files changed, 25 insertions(+), 11 deletions(-)
create mode 100644
drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_types.h
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index a2a827070c33..1143ba5b4f7c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -32,6 +32,7 @@
*/
#include
+#include
#include
#include
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6fbfe8a18f45..4de86e299c91 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -47,6 +47,7 @@
#include
#include
+#include "gem/i915_gem_object_types.h" /* for to_intel_bo() */
#include "i915_vma.h"
#include "i915_vma_types.h"
#include "intel_bios.h"
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c
b/drivers/gpu/drm/i915/display/intel_fb.c
index b6638726949d..8069abf91c5e 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -9,6 +9,7 @@
#include
#include
+#include "gem/i915_gem_object.h"
#include "i915_drv.h"
#include "intel_display.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c
b/drivers/gpu/drm/i915/display/intel_fbdev.c
index 5ad0b4c8a0fd..37ae176bfeb0 100644
--- a/drivers/gpu/drm/i915/display/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/display/intel_fbdev.c
@@ -44,6 +44,7 @@
#include
#include "gem/i915_gem_mman.h"
+#include "gem/i915_gem_object.h"
#include "i915_drv.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_types.h
b/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_types.h
new file mode 100644
index ..7d6bb1abab73
--- /dev/null
+++ b/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_types.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2024 Intel Corporation */
+
+#ifndef __I915_GEM_OBJECT_TYPES_H__
+#define __I915_GEM_OBJECT_TYPES_H__
+
+#include "xe_bo.h"
+
+#define to_intel_bo(x) gem_to_xe_bo((x))
+
+#endif
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index 3e930ce25c90..7b3f53427b03 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -12,11 +12,8 @@
#include
-#include "gem/i915_gem_object.h"
-
#include "soc/intel_pch.h"
#include "xe_device.h"
-#include "xe_bo.h"
#include "xe_pm.h"
#include "i915_reg_defs.h"
#include "i915_utils.h"
@@ -113,7 +110,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct
device *kdev)
#define IS_RAPTORLAKE_U(xe) ((xe)->info.subplatform ==
XE_SUBPLATFORM_ALDERLAKE_P_RPLU)
#define IS_ICL_WITH_PORT_F(xe) (xe && 0)
#define HAS_FLAT_CCS(xe) (xe_device_has_flat_ccs(xe))
-#define to_intel_bo(x) gem_to_xe_bo((x))
#define HAS_128_BYTE_Y_TILING(xe) (xe || 1)
diff --git a/drivers/gpu/drm/xe/display/intel_fb_bo.c
b/drivers/gpu/drm/xe/display/intel_fb_bo.c
index e18521acc516..b89cda053d2c 100644
--- a/drivers/gpu/drm/xe/display/intel_fb_bo.c
+++ b/drivers/gpu/drm/xe/display/intel_fb_bo.c
@@ -4,10 +4,12 @@
*/
#include
+#include
#include "i915_drv.h"
#include "intel_display_types.h"
#include "intel_fb_bo.h"
+#include "xe_bo.h"
void intel_fb_bo_framebuffer_fini(struct xe_bo *bo)
{
diff --git a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
index f6bf5896ff1b..5ecc7d467934 100644
--- a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
+++ b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c
@@ -3,15 +3,14 @@
* Copyright © 2023 Intel Corporation
*/
-#include "intel_fbdev_fb.h
[PATCH 04/10] drm/i915/display: include intel_uncore.h where needed
Include what you use. With this, we can drop the include from xe compat i915_drv.h. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_bios.c | 1 + drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index b0a49b2f957f..e53a789e3170 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -36,6 +36,7 @@ #include "intel_display.h" #include "intel_display_types.h" #include "intel_gmbus.h" +#include "intel_uncore.h" #define _INTEL_BIOS_PRIVATE #include "intel_vbt_defs.h" diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index 9776cc3332fe..e5966f07a924 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -22,7 +22,6 @@ #include "i915_reg_defs.h" #include "i915_utils.h" #include "intel_step.h" -#include "intel_uncore.h" #include "intel_runtime_pm.h" #include -- 2.39.2
[PATCH 03/10] drm/i915/display: include i915_gpu_error.h where needed
Include what you use. With this, we can drop the include from xe compat i915_drv.h. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dmc.c | 1 + drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 63fccdda56c0..b5ebb0f5b269 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -26,6 +26,7 @@ #include #include "i915_drv.h" +#include "i915_gpu_error.h" #include "i915_reg.h" #include "intel_de.h" #include "intel_dmc.h" diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index fb784ab64cd4..9776cc3332fe 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -19,7 +19,6 @@ #include "xe_bo.h" #include "xe_pm.h" #include "xe_step.h" -#include "i915_gpu_error.h" #include "i915_reg_defs.h" #include "i915_utils.h" #include "intel_step.h" -- 2.39.2
[PATCH 02/10] drm/i915/display: include gt/intel_gt_types.h where needed
Include what you use. We need to move the compat intel_gt_types.h under
gt subdir. With this, we can drop the include from xe compat i915_drv.h.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
drivers/gpu/drm/xe/compat-i915-headers/{ => gt}/intel_gt_types.h | 0
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h| 1 -
3 files changed, 1 insertion(+), 1 deletion(-)
rename drivers/gpu/drm/xe/compat-i915-headers/{ => gt}/intel_gt_types.h (100%)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index 6985abeb6102..8e956e7a1964 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -44,6 +44,7 @@
#include
#include "gem/i915_gem_stolen.h"
+#include "gt/intel_gt_types.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_utils.h"
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_gt_types.h
b/drivers/gpu/drm/xe/compat-i915-headers/gt/intel_gt_types.h
similarity index 100%
rename from drivers/gpu/drm/xe/compat-i915-headers/intel_gt_types.h
rename to drivers/gpu/drm/xe/compat-i915-headers/gt/intel_gt_types.h
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index 3be3d419530a..fb784ab64cd4 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -22,7 +22,6 @@
#include "i915_gpu_error.h"
#include "i915_reg_defs.h"
#include "i915_utils.h"
-#include "intel_gt_types.h"
#include "intel_step.h"
#include "intel_uncore.h"
#include "intel_runtime_pm.h"
--
2.39.2
[PATCH 01/10] drm/i915/display: include gem/i915_gem_stolen.h where needed
Include what you use. We need to move the compat i915_gem_stolen.h under
gem subdir. With this, we can drop the include from xe compat
i915_drv.h.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
.../gpu/drm/xe/compat-i915-headers/{ => gem}/i915_gem_stolen.h | 0
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h| 1 -
3 files changed, 1 insertion(+), 1 deletion(-)
rename drivers/gpu/drm/xe/compat-i915-headers/{ => gem}/i915_gem_stolen.h
(100%)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
b/drivers/gpu/drm/i915/display/intel_fbc.c
index e9189a864f69..6985abeb6102 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -43,6 +43,7 @@
#include
#include
+#include "gem/i915_gem_stolen.h"
#include "i915_drv.h"
#include "i915_reg.h"
#include "i915_utils.h"
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_gem_stolen.h
b/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_stolen.h
similarity index 100%
rename from drivers/gpu/drm/xe/compat-i915-headers/i915_gem_stolen.h
rename to drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_stolen.h
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index cd4632276141..3be3d419530a 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -19,7 +19,6 @@
#include "xe_bo.h"
#include "xe_pm.h"
#include "xe_step.h"
-#include "i915_gem_stolen.h"
#include "i915_gpu_error.h"
#include "i915_reg_defs.h"
#include "i915_utils.h"
--
2.39.2
[PATCH 00/10] drm/i915 and drm/xe display and compat cleanups
While the i915 i915_drv.h includes absolutely everything, the xe compat
i915_drv.h is handy for reducing includes and including what's really
needed where needed. Do just that. This is also useful for figuring out
what the display code actually needs outside of display. Do some
additional header cleanups on top.
I suggest merging the lot via drm-intel-next.
BR,
Jani.
Jani Nikula (10):
drm/i915/display: include gem/i915_gem_stolen.h where needed
drm/i915/display: include gt/intel_gt_types.h where needed
drm/i915/display: include i915_gpu_error.h where needed
drm/i915/display: include intel_uncore.h where needed
drm/i915/display: include intel_step.h where needed
drm/i915/display: include xe_bo.h, gem_object_types etc. where needed
drm/xe/display: move compat uncore stubs to the correct file
drm/xe/display: move compat runtime pm stubs to the correct file
drm/xe/display: reduce includes in compat i915_drv.h
drm/xe/display: drop i915_drv.h include from xe code
.../gpu/drm/i915/display/intel_atomic_plane.c | 1 +
drivers/gpu/drm/i915/display/intel_bios.c | 1 +
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/intel_dmc.c | 2 +
drivers/gpu/drm/i915/display/intel_fb.c | 1 +
drivers/gpu/drm/i915/display/intel_fbc.c | 2 +
drivers/gpu/drm/i915/display/intel_fbdev.c| 1 +
.../gem/i915_gem_object_types.h | 11 +++
.../{ => gem}/i915_gem_stolen.h | 0
.../{ => gt}/intel_gt_types.h | 0
.../gpu/drm/xe/compat-i915-headers/i915_drv.h | 67 +--
.../xe/compat-i915-headers/intel_runtime_pm.h | 51 ++
.../drm/xe/compat-i915-headers/intel_uncore.h | 5 ++
drivers/gpu/drm/xe/display/ext/i915_irq.c | 1 -
drivers/gpu/drm/xe/display/intel_fb_bo.c | 7 +-
drivers/gpu/drm/xe/display/intel_fbdev_fb.c | 24 +++
drivers/gpu/drm/xe/display/xe_dsb_buffer.c| 9 ++-
drivers/gpu/drm/xe/display/xe_fb_pin.c| 6 +-
drivers/gpu/drm/xe/display/xe_plane_initial.c | 19 +++---
19 files changed, 108 insertions(+), 101 deletions(-)
create mode 100644
drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_types.h
rename drivers/gpu/drm/xe/compat-i915-headers/{ => gem}/i915_gem_stolen.h
(100%)
rename drivers/gpu/drm/xe/compat-i915-headers/{ => gt}/intel_gt_types.h (100%)
--
2.39.2
Re: [core-for-CI PATCH] PCI: Make PCI cfg_access_lock lockdep key a singleton
On Wed, 29 May 2024, Imre Deak wrote:
> From: Dan Williams
>
> The new lockdep annotation for cfg_access_lock naively registered a new
> key per device. This is overkill and leads to warnings on hash
> collisions at dynamic registration time:
>
> WARNING: CPU: 0 PID: 1 at kernel/locking/lockdep.c:1226
> lockdep_register_key+0xb0/0x240
> RIP: 0010:lockdep_register_key+0xb0/0x240
> [..]
> Call Trace:
>
> ? __warn+0x8c/0x190
> ? lockdep_register_key+0xb0/0x240
> ? report_bug+0x1f8/0x200
> ? handle_bug+0x3c/0x70
> ? exc_invalid_op+0x18/0x70
> ? asm_exc_invalid_op+0x1a/0x20
> ? lockdep_register_key+0xb0/0x240
> pci_device_add+0x14b/0x560
> ? pci_setup_device+0x42e/0x6a0
> pci_scan_single_device+0xa7/0xd0
> p2sb_scan_and_cache_devfn+0xc/0x90
> p2sb_fs_init+0x15f/0x170
>
> Switch to a shared static key for all instances.
>
> Fixes: 7e89efc6e9e4 ("PCI: Lock upstream bridge for pci_reset_function()")
> Reported-by: Jani Saarinen
> Closes:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14834/bat-apl-1/boot0.txt
> Cc: Dave Jiang
> Cc: Bjorn Helgaas
> Signed-off-by: Dan Williams
Dropped extra Cc's.
Acked-by: Jani Nikula
for merging to topic/core-for-CI. Please create the issue at gitlab,
label it core-for-CI, and add References: to it here.
> ---
> drivers/pci/probe.c | 7 ---
> include/linux/pci.h | 1 -
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 8e696e547565c..15168881ec941 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -2533,6 +2533,8 @@ static void pci_set_msi_domain(struct pci_dev *dev)
> dev_set_msi_domain(>dev, d);
> }
>
> +static struct lock_class_key cfg_access_key;
> +
> void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
> {
> int ret;
> @@ -2546,9 +2548,8 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus
> *bus)
> dev->dev.dma_mask = >dma_mask;
> dev->dev.dma_parms = >dma_parms;
> dev->dev.coherent_dma_mask = 0xull;
> - lockdep_register_key(>cfg_access_key);
> - lockdep_init_map(>cfg_access_lock, dev_name(>dev),
> - >cfg_access_key, 0);
> + lockdep_init_map(>cfg_access_lock, ">cfg_access_lock",
> + _access_key, 0);
>
> dma_set_max_seg_size(>dev, 65536);
> dma_set_seg_boundary(>dev, 0x);
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index fb004fd4e8890..5bece7fd11f88 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -413,7 +413,6 @@ struct pci_dev {
> struct resource driver_exclusive_resource; /* driver exclusive
> resource ranges */
>
> boolmatch_driver; /* Skip attaching driver */
> - struct lock_class_key cfg_access_key;
> struct lockdep_map cfg_access_lock;
>
> unsigned inttransparent:1; /* Subtractive decode bridge */
--
Jani Nikula, Intel
Re: [PATCH v2 0/2] drm/i915/display: Add comparison for pipe config for MTL+ >
On Thu, 23 May 2024, Mika Kahola wrote: > Currently, we may bump into pll mismatch errors during the > state verification stage. This happens when we try to use > fastset instead of full modeset. Hence, we would need to add > a check for pipe configuration to ensure that the sw and the > hw configuration will match. In case of hw and sw mismatch, > we would need to disable fastset and use full modeset instead. > > However, first we need to revert the patch that disables fastset > for C10. I think the patch order should be reversed. Each commit should work. Can be applied in a different order without resending. There's maybe a bit too much happening in patch 2 for my liking, but *shrug*. Reviewed-by: Jani Nikula > > v2: Fix C10 error on PLL comparison (BAT) > Use memcmp instead of fixed loops for pll config > comparison (Jani) > Clean up and use intel_cx0pll_dump_hw_state() to dump > pll information (Jani) > > Signed-off-by: Mika Kahola > > Mika Kahola (2): > drm/i915/display: Revert "drm/i915/display: Skip C10 state > verification in case of fastset" > drm/i915/display: Add compare config for MTL+ platforms > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 80 --- > drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +- > drivers/gpu/drm/i915/display/intel_display.c | 33 > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + > 4 files changed, 109 insertions(+), 13 deletions(-) -- Jani Nikula, Intel
Re: [PATCH 10/12] drm/i915: move rawclk init to intel_cdclk_init()
On Tue, 28 May 2024, Jani Nikula wrote:
> The rawclk initialization is a bit out of place in
> intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a
> bit of refactoring on intel_read_rawclk().
Note: This also starts to initialize rawclk_frew for xe, which didn't
happen before. Apparently we didn't need it yet? Or the only user was
backlight max deduction?
BR,
Jani.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++---
> drivers/gpu/drm/i915/display/intel_cdclk.h | 1 -
> drivers/gpu/drm/i915/intel_device_info.c | 4
> 3 files changed, 11 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index c731c489c925..55c2dfe5422f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3218,6 +3218,8 @@ int intel_cdclk_state_set_joined_mbus(struct
> intel_atomic_state *state, bool joi
> return intel_atomic_lock_global_state(_state->base);
> }
>
> +static void intel_rawclk_init(struct drm_i915_private *dev_priv);
> +
> int intel_cdclk_init(struct drm_i915_private *dev_priv)
> {
> struct intel_cdclk_state *cdclk_state;
> @@ -3229,6 +3231,8 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv)
> intel_atomic_global_obj_init(dev_priv, _priv->display.cdclk.obj,
>_state->base, _cdclk_funcs);
>
> + intel_rawclk_init(dev_priv);
> +
> return 0;
> }
>
> @@ -3545,16 +3549,13 @@ static int i9xx_hrawclk(struct drm_i915_private *i915)
> return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
> }
>
> -/**
> - * intel_read_rawclk - Determine the current RAWCLK frequency
> - * @dev_priv: i915 device
> - *
> - * Determine the current RAWCLK frequency. RAWCLK is a fixed
> - * frequency clock so this needs to done only once.
> +/*
> + * Initialize the current RAWCLK frequency. RAWCLK is a fixed frequency
> clock so
> + * this needs to done only once.
> */
> -u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
> +static void intel_rawclk_init(struct drm_i915_private *dev_priv)
> {
> - u32 freq;
> + u32 freq = 0;
>
> if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
> /*
> @@ -3573,11 +3574,9 @@ u32 intel_read_rawclk(struct drm_i915_private
> *dev_priv)
> freq = vlv_hrawclk(dev_priv);
> else if (DISPLAY_VER(dev_priv) >= 3)
> freq = i9xx_hrawclk(dev_priv);
> - else
> - /* no rawclk on other platforms, or no need to know it */
> - return 0;
>
> - return freq;
> + RUNTIME_INFO(dev_priv)->rawclk_freq = freq;
> + drm_dbg_kms(_priv->drm, "rawclk rate: %d kHz\n", freq);
> }
>
> static int i915_cdclk_info_show(struct seq_file *m, void *unused)
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
> b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index cfdcdec07a4d..a3f950d5a366 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -64,7 +64,6 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
> void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
> void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
> void intel_update_cdclk(struct drm_i915_private *dev_priv);
> -u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
> bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
> const struct intel_cdclk_config *b);
> int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index 862f4b705227..cc7a8fb0a87d 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -370,10 +370,6 @@ void intel_device_info_runtime_init(struct
> drm_i915_private *dev_priv)
>"Disabling ppGTT for VT-d support\n");
> runtime->ppgtt_type = INTEL_PPGTT_NONE;
> }
> -
> - runtime->rawclk_freq = intel_read_rawclk(dev_priv);
> - drm_dbg(_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
> -
> }
>
> /*
--
Jani Nikula, Intel
[core-for-CI PATCH] PCI: Fix missing lockdep annotation for pci_cfg_access_trylock()
From: Dan Williams
Alex reports a new vfio-pci lockdep warning resulting from the
cfg_access_lock lock_map added recently.
Add the missing annotation to pci_cfg_access_trylock() and adjust the
lock_map acquisition to be symmetrical relative to pci_lock.
Fixes: 7e89efc6e9e4 ("PCI: Lock upstream bridge for pci_reset_function()")
Reported-by: Alex Williamson
Closes:
http://lore.kernel.org/r/20240523131005.5578e3de.alex.william...@redhat.com
Tested-by: Alex Williamson
Cc: Dave Jiang
Cc: Bjorn Helgaas
Signed-off-by: Dan Williams
Reviewed-by: Dave Jiang
---
drivers/pci/access.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 30f031de9cfe..3595130ff719 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -289,11 +289,10 @@ void pci_cfg_access_lock(struct pci_dev *dev)
{
might_sleep();
- lock_map_acquire(>cfg_access_lock);
-
raw_spin_lock_irq(_lock);
if (dev->block_cfg_access)
pci_wait_cfg(dev);
+ lock_map_acquire(>cfg_access_lock);
dev->block_cfg_access = 1;
raw_spin_unlock_irq(_lock);
}
@@ -315,8 +314,10 @@ bool pci_cfg_access_trylock(struct pci_dev *dev)
raw_spin_lock_irqsave(_lock, flags);
if (dev->block_cfg_access)
locked = false;
- else
+ else {
+ lock_map_acquire(>cfg_access_lock);
dev->block_cfg_access = 1;
+ }
raw_spin_unlock_irqrestore(_lock, flags);
return locked;
@@ -342,11 +343,10 @@ void pci_cfg_access_unlock(struct pci_dev *dev)
WARN_ON(!dev->block_cfg_access);
dev->block_cfg_access = 0;
+ lock_map_release(>cfg_access_lock);
raw_spin_unlock_irqrestore(_lock, flags);
wake_up_all(_cfg_wait);
-
- lock_map_release(>cfg_access_lock);
}
EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
--
2.39.2
Re: [PATCH 7/7] drm/i915/dsb: Convert dewake_scanline to a hw scanline number earlier
On Tue, 28 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we switch from out software idea of a scanline
> to the hw's idea of a scanline during the commit phase in
> _intel_dsb_commit(). While that is slightly easier due to
> fastsets fiddling with the timings, we'll also need to
> generate proper hw scanline numbers already when emitting
> DSB scanline wait instructions. So this approach won't
> do in the future. Switch to hw scanline numbers earlier.
>
> Also intel_dsb_dewake_scanline() itself already makes
> some assumptions about VRR that don't take into account
> VRR toggling during fastsets, so technically delaying
> the sw->hw conversion doesn't even help us.
>
> The other reason for delaying the conversion was that we
> are using intel_get_crtc_scanline() during intel_dsb_commit()
> which gives us the current sw scanline. But this is pretty
> low level stuff anyway so just using raw PIPEDSL reads seems
> fine here, and that of course gives us the hw scanline
> directly, reducing the need to do so many conversions.
I'll take your word for the PIPEDSL part,
Reviewed-by: Jani Nikula
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_dsb.c| 16 +---
> drivers/gpu/drm/i915/display/intel_vblank.c | 9 -
> drivers/gpu/drm/i915/display/intel_vblank.h | 3 ++-
> 3 files changed, 15 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 319fbebd7008..63268ed2e53f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -326,14 +326,16 @@ static int intel_dsb_dewake_scanline(const struct
> intel_crtc_state *crtc_state)
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> const struct drm_display_mode *adjusted_mode =
> _state->hw.adjusted_mode;
> unsigned int latency = skl_watermark_max_latency(i915, 0);
> - int vblank_start;
> + int vblank_start, dewake_scanline;
>
> if (crtc_state->vrr.enable)
> vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> else
> vblank_start = intel_mode_vblank_start(adjusted_mode);
>
> - return max(0, vblank_start - intel_usecs_to_scanlines(adjusted_mode,
> latency));
> + dewake_scanline = max(0, vblank_start -
> intel_usecs_to_scanlines(adjusted_mode, latency));
> +
> + return intel_crtc_scanline_to_hw(crtc_state, dewake_scanline);
> }
>
> static u32 dsb_chicken(struct intel_crtc *crtc)
> @@ -376,19 +378,19 @@ static void _intel_dsb_commit(struct intel_dsb *dsb,
> u32 ctrl,
> intel_dsb_buffer_ggtt_offset(>dsb_buf));
>
> if (dewake_scanline >= 0) {
> - int diff, hw_dewake_scanline;
> -
> - hw_dewake_scanline = intel_crtc_scanline_to_hw(crtc,
> dewake_scanline);
> + int diff, position;
>
> intel_de_write_fw(dev_priv, DSB_PMCTRL(pipe, dsb->id),
> DSB_ENABLE_DEWAKE |
> - DSB_SCANLINE_FOR_DEWAKE(hw_dewake_scanline));
> + DSB_SCANLINE_FOR_DEWAKE(dewake_scanline));
>
> /*
>* Force DEwake immediately if we're already past
>* or close to racing past the target scanline.
>*/
> - diff = dewake_scanline - intel_get_crtc_scanline(crtc);
> + position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) &
> PIPEDSL_LINE_MASK;
> + diff = dewake_scanline - position;
> +
> intel_de_write_fw(dev_priv, DSB_PMCTRL_2(pipe, dsb->id),
> (diff >= 0 && diff < 5 ? DSB_FORCE_DEWAKE :
> 0) |
> DSB_BLOCK_DEWAKE_EXTENSION);
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c
> b/drivers/gpu/drm/i915/display/intel_vblank.c
> index eb80952b0cfd..2e3442fe5a5d 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -281,13 +281,12 @@ static int __intel_get_crtc_scanline(struct intel_crtc
> *crtc)
> return (position + vtotal + crtc->scanline_offset) % vtotal;
> }
>
> -int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline)
> +int intel_crtc_scanline_to_hw(const struct intel_crtc_state *crtc_state,
> + int scanline)
> {
> - const struct drm_vblank_crtc *vblank =
> drm_crtc_vblank_crtc(>base);
> - const struct drm_display_mode *mode = >hwmode;
> - int vto
Re: [PATCH 6/7] drm/i915: Switch intel_usecs_to_scanlines() to 64bit maths
On Tue, 28 May 2024, Ville Syrjala wrote: > From: Ville Syrjälä > > Dotclocks can reach ~1GHz these days, so intel_usecs_to_scanlines(), > with its 32bit maths, is currently limited to a few milliseconds. > I want bigger numbers in DSB selftests, so switch over to 64bit > maths. > > Signed-off-by: Ville Syrjälä Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_crtc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c > b/drivers/gpu/drm/i915/display/intel_crtc.c > index ca6dc1dc56c8..17edd6099287 100644 > --- a/drivers/gpu/drm/i915/display/intel_crtc.c > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c > @@ -454,8 +454,8 @@ int intel_usecs_to_scanlines(const struct > drm_display_mode *adjusted_mode, > if (!adjusted_mode->crtc_htotal) > return 1; > > - return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, > - 1000 * adjusted_mode->crtc_htotal); > + return DIV_ROUND_UP_ULL(mul_u32_u32(usecs, adjusted_mode->crtc_clock), > + 1000 * adjusted_mode->crtc_htotal); > } > > /** -- Jani Nikula, Intel
Re: [PATCH 5/7] drm/i915: Move intel_crtc_scanline_offset()
On Tue, 28 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> I want to use intel_crtc_scanline_offset() in
> intel_crtc_scanline_to_hw(). Relocate intel_crtc_scanline_offset()
> a bit to avoid a forward declaration.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_vblank.c | 76 ++---
> 1 file changed, 38 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c
> b/drivers/gpu/drm/i915/display/intel_vblank.c
> index b0e95a4c680d..eb80952b0cfd 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -188,6 +188,44 @@ static u32
> __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
> return scanline;
> }
>
> +static int intel_crtc_scanline_offset(const struct intel_crtc_state
> *crtc_state)
> +{
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> +
> + /*
> + * The scanline counter increments at the leading edge of hsync.
> + *
> + * On most platforms it starts counting from vtotal-1 on the
> + * first active line. That means the scanline counter value is
> + * always one less than what we would expect. Ie. just after
> + * start of vblank, which also occurs at start of hsync (on the
> + * last active line), the scanline counter will read vblank_start-1.
> + *
> + * On gen2 the scanline counter starts counting from 1 instead
> + * of vtotal-1, so we have to subtract one.
> + *
> + * On HSW+ the behaviour of the scanline counter depends on the output
> + * type. For DP ports it behaves like most other platforms, but on HDMI
> + * there's an extra 1 line difference. So we need to add two instead of
> + * one to the value.
> + *
> + * On VLV/CHV DSI the scanline counter would appear to increment
> + * approx. 1/3 of a scanline before start of vblank. Unfortunately
> + * that means we can't tell whether we're in vblank or not while
> + * we're on that particular line. We must still set scanline_offset
> + * to 1 so that the vblank timestamps come out correct when we query
> + * the scanline counter from within the vblank interrupt handler.
> + * However if queried just before the start of vblank we'll get an
> + * answer that's slightly in the future.
> + */
> + if (DISPLAY_VER(i915) == 2)
> + return -1;
> + else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_HDMI))
> + return 2;
> + else
> + return 1;
> +}
> +
> /*
> * intel_de_read_fw(), only for fast reads of display block, no need for
> * forcewake etc.
> @@ -467,44 +505,6 @@ void intel_wait_for_pipe_scanline_moving(struct
> intel_crtc *crtc)
> wait_for_pipe_scanline_moving(crtc, true);
> }
>
> -static int intel_crtc_scanline_offset(const struct intel_crtc_state
> *crtc_state)
> -{
> - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> -
> - /*
> - * The scanline counter increments at the leading edge of hsync.
> - *
> - * On most platforms it starts counting from vtotal-1 on the
> - * first active line. That means the scanline counter value is
> - * always one less than what we would expect. Ie. just after
> - * start of vblank, which also occurs at start of hsync (on the
> - * last active line), the scanline counter will read vblank_start-1.
> - *
> - * On gen2 the scanline counter starts counting from 1 instead
> - * of vtotal-1, so we have to subtract one.
> - *
> - * On HSW+ the behaviour of the scanline counter depends on the output
> - * type. For DP ports it behaves like most other platforms, but on HDMI
> - * there's an extra 1 line difference. So we need to add two instead of
> - * one to the value.
> - *
> - * On VLV/CHV DSI the scanline counter would appear to increment
> - * approx. 1/3 of a scanline before start of vblank. Unfortunately
> - * that means we can't tell whether we're in vblank or not while
> - * we're on that particular line. We must still set scanline_offset
> - * to 1 so that the vblank timestamps come out correct when we query
> - * the scanline counter from within the vblank interrupt handler.
> - * However if queried just before the start of vblank we'll get an
> - * answer that's slightly in the future.
> - */
> - if (DISPLAY_VER(i915) == 2)
> - return -1;
> - else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_HDMI))
> - return 2;
> - else
> - return 1;
> -}
> -
> void intel_crtc_update_active_timings(const struct intel_crtc_state
> *crtc_state,
> bool vrr_enable)
> {
--
Jani Nikula, Intel
Re: [PATCH 4/7] drm/i915: Simplify scanline_offset handling for gen2
On Tue, 28 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently intel_crtc_scanline_offset() is careful to always
> return a positive offset. That is not actually necessary
> as long as we take care of negative values when applying the
> offset in __intel_get_crtc_scanline().
>
> This simplifies intel_crtc_scanline_offset(), and makes
> the scanline_offfset arithmetic more symmetric between
> the forwad (__intel_get_crtc_scanline()) and reverse
*forward
Reviewed-by: Jani Nikula
> (intel_crtc_scanline_to_hw()) directions.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/intel_vblank.c | 8 +++-
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c
> b/drivers/gpu/drm/i915/display/intel_vblank.c
> index 31fa5867e1a7..b0e95a4c680d 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -240,7 +240,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc
> *crtc)
>* See update_scanline_offset() for the details on the
>* scanline_offset adjustment.
>*/
> - return (position + crtc->scanline_offset) % vtotal;
> + return (position + vtotal + crtc->scanline_offset) % vtotal;
> }
>
> int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline)
> @@ -470,7 +470,6 @@ void intel_wait_for_pipe_scanline_moving(struct
> intel_crtc *crtc)
> static int intel_crtc_scanline_offset(const struct intel_crtc_state
> *crtc_state)
> {
> struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> - const struct drm_display_mode *adjusted_mode =
> _state->hw.adjusted_mode;
>
> /*
>* The scanline counter increments at the leading edge of hsync.
> @@ -482,8 +481,7 @@ static int intel_crtc_scanline_offset(const struct
> intel_crtc_state *crtc_state)
>* last active line), the scanline counter will read vblank_start-1.
>*
>* On gen2 the scanline counter starts counting from 1 instead
> - * of vtotal-1, so we have to subtract one (or rather add vtotal-1
> - * to keep the value positive), instead of adding one.
> + * of vtotal-1, so we have to subtract one.
>*
>* On HSW+ the behaviour of the scanline counter depends on the output
>* type. For DP ports it behaves like most other platforms, but on HDMI
> @@ -500,7 +498,7 @@ static int intel_crtc_scanline_offset(const struct
> intel_crtc_state *crtc_state)
>* answer that's slightly in the future.
>*/
> if (DISPLAY_VER(i915) == 2)
> - return intel_mode_vtotal(adjusted_mode) - 1;
> + return -1;
> else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_HDMI))
> return 2;
> else
--
Jani Nikula, Intel
Re: [PATCH 3/7] drm/i915: Extract intel_mode_vtotal()
On Tue, 28 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We have several copies of code calculating the hardware's
> idea of vtotal. Pull that to a helper, similar to
> intel_mode_vblank_{start,end}().
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_vblank.c | 40 +
> drivers/gpu/drm/i915/display/intel_vblank.h | 1 +
> 2 files changed, 18 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c
> b/drivers/gpu/drm/i915/display/intel_vblank.c
> index ba56015f2c40..31fa5867e1a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -207,9 +207,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc
> *crtc)
> if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
> return __intel_get_crtc_scanline_from_timestamp(crtc);
>
> - vtotal = mode->crtc_vtotal;
> - if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> - vtotal /= 2;
> + vtotal = intel_mode_vtotal(mode);
>
> position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) &
> PIPEDSL_LINE_MASK;
>
> @@ -249,11 +247,7 @@ int intel_crtc_scanline_to_hw(struct intel_crtc *crtc,
> int scanline)
> {
> const struct drm_vblank_crtc *vblank =
> drm_crtc_vblank_crtc(>base);
> const struct drm_display_mode *mode = >hwmode;
> - int vtotal;
> -
> - vtotal = mode->crtc_vtotal;
> - if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> - vtotal /= 2;
> + int vtotal = intel_mode_vtotal(mode);
>
> return (scanline + vtotal - crtc->scanline_offset) % vtotal;
> }
> @@ -310,13 +304,10 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc
> *_crtc,
>
> htotal = mode->crtc_htotal;
> hsync_start = mode->crtc_hsync_start;
> - vtotal = mode->crtc_vtotal;
> + vtotal = intel_mode_vtotal(mode);
> vbl_start = intel_mode_vblank_start(mode);
> vbl_end = intel_mode_vblank_end(mode);
>
> - if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> - vtotal /= 2;
> -
> /*
>* Enter vblank critical section, as we will do multiple
>* timing critical raw register reads, potentially with
> @@ -508,19 +499,12 @@ static int intel_crtc_scanline_offset(const struct
> intel_crtc_state *crtc_state)
>* However if queried just before the start of vblank we'll get an
>* answer that's slightly in the future.
>*/
> - if (DISPLAY_VER(i915) == 2) {
> - int vtotal;
> -
> - vtotal = adjusted_mode->crtc_vtotal;
> - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> - vtotal /= 2;
> -
> - return vtotal - 1;
> - } else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_HDMI)) {
> + if (DISPLAY_VER(i915) == 2)
> + return intel_mode_vtotal(adjusted_mode) - 1;
> + else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state,
> INTEL_OUTPUT_HDMI))
> return 2;
> - } else {
> + else
> return 1;
> - }
> }
>
> void intel_crtc_update_active_timings(const struct intel_crtc_state
> *crtc_state,
> @@ -592,6 +576,16 @@ int intel_mode_vblank_end(const struct drm_display_mode
> *mode)
> return vblank_end;
> }
>
> +int intel_mode_vtotal(const struct drm_display_mode *mode)
> +{
> + int vtotal = mode->crtc_vtotal;
> +
> + if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> + vtotal /= 2;
> +
> + return vtotal;
> +}
> +
> void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
>const struct intel_crtc_state *new_crtc_state,
>struct intel_vblank_evade_ctx *evade)
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h
> b/drivers/gpu/drm/i915/display/intel_vblank.h
> index 6f11fd070f19..b51ae2c1039e 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.h
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.h
> @@ -22,6 +22,7 @@ struct intel_vblank_evade_ctx {
>
> int intel_mode_vblank_start(const struct drm_display_mode *mode);
> int intel_mode_vblank_end(const struct drm_display_mode *mode);
> +int intel_mode_vtotal(const struct drm_display_mode *mode);
>
> void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
>const struct intel_crtc_state *new_crtc_state,
--
Jani Nikula, Intel
Re: [PATCH 2/7] drm/i915: Extract intel_mode_vblank_end()
On Tue, 28 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Extract intel_mode_vblank_end() in the same vein as
> intel_mode_vblank_start(). While we have only one use
> of this it seems nicer to unify the approach.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_vblank.c | 16
> drivers/gpu/drm/i915/display/intel_vblank.h | 1 +
> 2 files changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c
> b/drivers/gpu/drm/i915/display/intel_vblank.c
> index 1f57596f8208..ba56015f2c40 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -312,12 +312,10 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc
> *_crtc,
> hsync_start = mode->crtc_hsync_start;
> vtotal = mode->crtc_vtotal;
> vbl_start = intel_mode_vblank_start(mode);
> - vbl_end = mode->crtc_vblank_end;
> + vbl_end = intel_mode_vblank_end(mode);
>
> - if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
> - vbl_end /= 2;
> + if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> vtotal /= 2;
> - }
>
> /*
>* Enter vblank critical section, as we will do multiple
> @@ -584,6 +582,16 @@ int intel_mode_vblank_start(const struct
> drm_display_mode *mode)
> return vblank_start;
> }
>
> +int intel_mode_vblank_end(const struct drm_display_mode *mode)
> +{
> + int vblank_end = mode->crtc_vblank_end;
> +
> + if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> + vblank_end /= 2;
> +
> + return vblank_end;
> +}
> +
> void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
>const struct intel_crtc_state *new_crtc_state,
>struct intel_vblank_evade_ctx *evade)
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h
> b/drivers/gpu/drm/i915/display/intel_vblank.h
> index 08825a4d8fb7..6f11fd070f19 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.h
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.h
> @@ -21,6 +21,7 @@ struct intel_vblank_evade_ctx {
> };
>
> int intel_mode_vblank_start(const struct drm_display_mode *mode);
> +int intel_mode_vblank_end(const struct drm_display_mode *mode);
>
> void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
>const struct intel_crtc_state *new_crtc_state,
--
Jani Nikula, Intel
Re: [PATCH 1/7] drm/i915: Reuse intel_mode_vblank_start()
On Tue, 28 May 2024, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Replace a few hand rolled copies of intel_mode_vblank_start() with
> the real thing.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dsb.c| 10 +++---
> drivers/gpu/drm/i915/display/intel_vblank.c | 9 +++--
> drivers/gpu/drm/i915/display/intel_vblank.h | 3 +++
> 3 files changed, 9 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 4baaa92ceaec..319fbebd7008 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -328,14 +328,10 @@ static int intel_dsb_dewake_scanline(const struct
> intel_crtc_state *crtc_state)
> unsigned int latency = skl_watermark_max_latency(i915, 0);
> int vblank_start;
>
> - if (crtc_state->vrr.enable) {
> + if (crtc_state->vrr.enable)
> vblank_start = intel_vrr_vmin_vblank_start(crtc_state);
> - } else {
> - vblank_start = adjusted_mode->crtc_vblank_start;
> -
> - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
> - vblank_start = DIV_ROUND_UP(vblank_start, 2);
> - }
> + else
> + vblank_start = intel_mode_vblank_start(adjusted_mode);
>
> return max(0, vblank_start - intel_usecs_to_scanlines(adjusted_mode,
> latency));
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c
> b/drivers/gpu/drm/i915/display/intel_vblank.c
> index 951190bcbc50..1f57596f8208 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -89,9 +89,7 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
>
> htotal = mode->crtc_htotal;
> hsync_start = mode->crtc_hsync_start;
> - vbl_start = mode->crtc_vblank_start;
> - if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> - vbl_start = DIV_ROUND_UP(vbl_start, 2);
> + vbl_start = intel_mode_vblank_start(mode);
>
> /* Convert to pixel count */
> vbl_start *= htotal;
> @@ -313,11 +311,10 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc
> *_crtc,
> htotal = mode->crtc_htotal;
> hsync_start = mode->crtc_hsync_start;
> vtotal = mode->crtc_vtotal;
> - vbl_start = mode->crtc_vblank_start;
> + vbl_start = intel_mode_vblank_start(mode);
> vbl_end = mode->crtc_vblank_end;
>
> if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
> - vbl_start = DIV_ROUND_UP(vbl_start, 2);
> vbl_end /= 2;
> vtotal /= 2;
> }
> @@ -577,7 +574,7 @@ void intel_crtc_update_active_timings(const struct
> intel_crtc_state *crtc_state,
> spin_unlock_irqrestore(>drm.vblank_time_lock, irqflags);
> }
>
> -static int intel_mode_vblank_start(const struct drm_display_mode *mode)
> +int intel_mode_vblank_start(const struct drm_display_mode *mode)
> {
> int vblank_start = mode->crtc_vblank_start;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h
> b/drivers/gpu/drm/i915/display/intel_vblank.h
> index ec6c3da3eeac..08825a4d8fb7 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.h
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.h
> @@ -10,6 +10,7 @@
> #include
>
> struct drm_crtc;
> +struct drm_display_mode;
> struct intel_crtc;
> struct intel_crtc_state;
>
> @@ -19,6 +20,8 @@ struct intel_vblank_evade_ctx {
> bool need_vlv_dsi_wa;
> };
>
> +int intel_mode_vblank_start(const struct drm_display_mode *mode);
> +
> void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
>const struct intel_crtc_state *new_crtc_state,
>struct intel_vblank_evade_ctx *evade);
--
Jani Nikula, Intel
Re: Lockdep annotation introduced warn in VMD driver
; 17.354747] ---[ end trace ]---
>>
>> <4>[ 17.487274] =
>> <4>[ 17.487277] WARNING: bad unlock balance detected!
>> <4>[ 17.487279] 6.10.0-rc1-Patchwork_134112v1-gabaeae202dfb+ #1
>> Tainted: GW <4>[ 17.487282]
>> - <4>[ 17.487284] swapper/0/1
>> is trying to release lock (1:e1:00.0) at: <4>[ 17.487287]
>> [] pci_cfg_access_unlock+0x57/0x60 <4>[
>> 17.487292] but there are no more locks to release! <4>[ 17.487294]
>> other info that might help us debug this:
>> <4>[ 17.487297] 2 locks held by swapper/0/1:
>> <4>[ 17.487299] #0: 888102c1c1b0 (>mutex){}-{3:3},
>> at: __driver_attach+0xab/0x180 <4>[ 17.487306] #1:
>> 8881056041b0 (>mutex){}-{3:3}, at:
>> pci_dev_trylock+0x19/0x50 <4>[ 17.487312] stack backtrace:
>> <4>[ 17.487314] CPU: 0 PID: 1 Comm: swapper/0 Tainted: GW
>>6.10.0-rc1-Patchwork_134112v1-gabaeae202dfb+ #1 <4>[
>> 17.487318] Hardware name: Intel Corporation Alder Lake Client
>> Platform/AlderLake-P LP5 RVP, BIOS RPLPFWI1.R00.4035.A00.2301200723
>> 01/20/2023 <4>[ 17.487322] Call Trace: <4>[ 17.487324]
>> <4>[ 17.487325] dump_stack_lvl+0x82/0xd0 <4>[ 17.487329]
>> lock_release+0x20b/0x2d0 <4>[ 17.487334] pci_bus_unlock+0x25/0x40
>> <4>[ 17.487337] pci_reset_bus+0x1eb/0x270
>> <4>[ 17.487340] vmd_probe+0x778/0xa10
>> <4>[ 17.487344] pci_device_probe+0x95/0x120
>> <4>[ 17.487346] really_probe+0xd9/0x370
>> <4>[ 17.487349] ? __pfx___driver_attach+0x10/0x10
>> <4>[ 17.487352] __driver_probe_device+0x73/0x150
>> <4>[ 17.487354] driver_probe_device+0x19/0xa0
>> <4>[ 17.487357] __driver_attach+0xb6/0x180
>> <4>[ 17.487359] ? __pfx___driver_attach+0x10/0x10
>> <4>[ 17.487362] bus_for_each_dev+0x77/0xd0
>> <4>[ 17.487365] bus_add_driver+0x110/0x240
>> <4>[ 17.487369] driver_register+0x5b/0x110
>> <4>[ 17.487371] ? __pfx_vmd_drv_init+0x10/0x10
>> <4>[ 17.487374] do_one_initcall+0x5c/0x2b0
>> <4>[ 17.487378] kernel_init_freeable+0x18e/0x340
>> <4>[ 17.487381] ? __pfx_kernel_init+0x10/0x10
>> <4>[ 17.487384] kernel_init+0x15/0x130
>> <4>[ 17.487387] ret_from_fork+0x2c/0x50
>> <4>[ 17.487390] ? __pfx_kernel_init+0x10/0x10
>> <4>[ 17.487392] ret_from_fork_asm+0x1a/0x30
>> <4>[ 17.487396]
>>
>
--
Jani Nikula, Intel
[PATCH 12/12] drm/xe/display: drop unused rawclk_freq and RUNTIME_INFO()
With rawclk_freq moved to display runtime info, xe has no users left for
them.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 -
drivers/gpu/drm/xe/xe_device_types.h | 6 --
2 files changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index cd4632276141..6c5830875091 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -181,7 +181,6 @@ struct i915_sched_attr {
intel_runtime_pm_put((rpm), (wf)), (wf) = 0)
#define pdev_to_i915 pdev_to_xe_device
-#define RUNTIME_INFO(xe) (&(xe)->info.i915_runtime)
#define FORCEWAKE_ALL XE_FORCEWAKE_ALL
diff --git a/drivers/gpu/drm/xe/xe_device_types.h
b/drivers/gpu/drm/xe/xe_device_types.h
index d834905a3786..0211e4d8a0f2 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -288,12 +288,6 @@ struct xe_device {
u8 has_atomic_enable_pte_bit:1;
/** @info.has_device_atomics_on_smem: Supports device atomics
on SMEM */
u8 has_device_atomics_on_smem:1;
-
-#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
- struct {
- u32 rawclk_freq;
- } i915_runtime;
-#endif
} info;
/** @irq: device interrupt state */
--
2.39.2
[PATCH 11/12] drm/i915: move rawclk from runtime to display runtime info
It's mostly about display, so move it under display.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_backlight.c | 10 +-
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_device.c| 2 ++
drivers/gpu/drm/i915/display/intel_display_device.h| 2 ++
.../gpu/drm/i915/display/intel_display_power_well.c| 4 ++--
drivers/gpu/drm/i915/display/intel_dp_aux.c| 4 ++--
drivers/gpu/drm/i915/display/intel_pps.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 1 -
drivers/gpu/drm/i915/intel_device_info.h | 2 --
9 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
b/drivers/gpu/drm/i915/display/intel_backlight.c
index 071668bfe5d1..66ee925287c2 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -1011,7 +1011,7 @@ static u32 cnp_hz_to_pwm(struct intel_connector
*connector, u32 pwm_freq_hz)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),
+ return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),
pwm_freq_hz);
}
@@ -1073,7 +1073,7 @@ static u32 pch_hz_to_pwm(struct intel_connector
*connector, u32 pwm_freq_hz)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq),
+ return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq),
pwm_freq_hz * 128);
}
@@ -1091,7 +1091,7 @@ static u32 i9xx_hz_to_pwm(struct intel_connector
*connector, u32 pwm_freq_hz)
int clock;
if (IS_PINEVIEW(i915))
- clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
+ clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
else
clock = KHz(i915->display.cdclk.hw.cdclk);
@@ -1109,7 +1109,7 @@ static u32 i965_hz_to_pwm(struct intel_connector
*connector, u32 pwm_freq_hz)
int clock;
if (IS_G4X(i915))
- clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
+ clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
else
clock = KHz(i915->display.cdclk.hw.cdclk);
@@ -1133,7 +1133,7 @@ static u32 vlv_hz_to_pwm(struct intel_connector
*connector, u32 pwm_freq_hz)
clock = MHz(25);
mul = 16;
} else {
- clock = KHz(RUNTIME_INFO(i915)->rawclk_freq);
+ clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq);
mul = 128;
}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 55c2dfe5422f..ced320fbad46 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3575,7 +3575,7 @@ static void intel_rawclk_init(struct drm_i915_private
*dev_priv)
else if (DISPLAY_VER(dev_priv) >= 3)
freq = i9xx_hrawclk(dev_priv);
- RUNTIME_INFO(dev_priv)->rawclk_freq = freq;
+ DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq = freq;
drm_dbg_kms(_priv->drm, "rawclk rate: %d kHz\n", freq);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c
b/drivers/gpu/drm/i915/display/intel_display_device.c
index cf093bc0cb28..a3d4d9ef6e33 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1151,6 +1151,8 @@ void intel_display_device_info_print(const struct
intel_display_device_info *inf
drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
+
+ drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
}
/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
b/drivers/gpu/drm/i915/display/intel_display_device.h
index 17ddf82f0b6e..aa627885758b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -111,6 +111,8 @@ struct drm_printer;
(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
struct intel_display_runtime_info {
+ u32 rawclk_freq;
+
struct {
u16 ver;
u16 rel;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 83f616097a29..a6b156c4388e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/dis
[PATCH 10/12] drm/i915: move rawclk init to intel_cdclk_init()
The rawclk initialization is a bit out of place in
intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a
bit of refactoring on intel_read_rawclk().
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++---
drivers/gpu/drm/i915/display/intel_cdclk.h | 1 -
drivers/gpu/drm/i915/intel_device_info.c | 4
3 files changed, 11 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index c731c489c925..55c2dfe5422f 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3218,6 +3218,8 @@ int intel_cdclk_state_set_joined_mbus(struct
intel_atomic_state *state, bool joi
return intel_atomic_lock_global_state(_state->base);
}
+static void intel_rawclk_init(struct drm_i915_private *dev_priv);
+
int intel_cdclk_init(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_state *cdclk_state;
@@ -3229,6 +3231,8 @@ int intel_cdclk_init(struct drm_i915_private *dev_priv)
intel_atomic_global_obj_init(dev_priv, _priv->display.cdclk.obj,
_state->base, _cdclk_funcs);
+ intel_rawclk_init(dev_priv);
+
return 0;
}
@@ -3545,16 +3549,13 @@ static int i9xx_hrawclk(struct drm_i915_private *i915)
return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
}
-/**
- * intel_read_rawclk - Determine the current RAWCLK frequency
- * @dev_priv: i915 device
- *
- * Determine the current RAWCLK frequency. RAWCLK is a fixed
- * frequency clock so this needs to done only once.
+/*
+ * Initialize the current RAWCLK frequency. RAWCLK is a fixed frequency clock
so
+ * this needs to done only once.
*/
-u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
+static void intel_rawclk_init(struct drm_i915_private *dev_priv)
{
- u32 freq;
+ u32 freq = 0;
if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL)
/*
@@ -3573,11 +3574,9 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
freq = vlv_hrawclk(dev_priv);
else if (DISPLAY_VER(dev_priv) >= 3)
freq = i9xx_hrawclk(dev_priv);
- else
- /* no rawclk on other platforms, or no need to know it */
- return 0;
- return freq;
+ RUNTIME_INFO(dev_priv)->rawclk_freq = freq;
+ drm_dbg_kms(_priv->drm, "rawclk rate: %d kHz\n", freq);
}
static int i915_cdclk_info_show(struct seq_file *m, void *unused)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
b/drivers/gpu/drm/i915/display/intel_cdclk.h
index cfdcdec07a4d..a3f950d5a366 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -64,7 +64,6 @@ void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
void intel_update_cdclk(struct drm_i915_private *dev_priv);
-u32 intel_read_rawclk(struct drm_i915_private *dev_priv);
bool intel_cdclk_clock_changed(const struct intel_cdclk_config *a,
const struct intel_cdclk_config *b);
int intel_mdclk_cdclk_ratio(struct drm_i915_private *i915,
diff --git a/drivers/gpu/drm/i915/intel_device_info.c
b/drivers/gpu/drm/i915/intel_device_info.c
index 862f4b705227..cc7a8fb0a87d 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -370,10 +370,6 @@ void intel_device_info_runtime_init(struct
drm_i915_private *dev_priv)
"Disabling ppGTT for VT-d support\n");
runtime->ppgtt_type = INTEL_PPGTT_NONE;
}
-
- runtime->rawclk_freq = intel_read_rawclk(dev_priv);
- drm_dbg(_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
-
}
/*
--
2.39.2
[PATCH 09/12] drm/i915/cdclk: use i9xx_fsb_freq() for rawclk_freq initialization
Instead of duplicating the CLKCFG parsing, reuse i9xx_fsb_freq() to
figure out rawclk_freq where applicable.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 46 ++
1 file changed, 3 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
index b78154c82a71..c731c489c925 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -23,6 +23,7 @@
#include
+#include "soc/intel_dram.h"
#include "hsw_ips.h"
#include "i915_reg.h"
#include "intel_atomic.h"
@@ -3529,10 +3530,8 @@ static int vlv_hrawclk(struct drm_i915_private *dev_priv)
CCK_DISPLAY_REF_CLOCK_CONTROL);
}
-static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
+static int i9xx_hrawclk(struct drm_i915_private *i915)
{
- u32 clkcfg;
-
/*
* hrawclock is 1/4 the FSB frequency
*
@@ -3543,46 +3542,7 @@ static int i9xx_hrawclk(struct drm_i915_private
*dev_priv)
* don't know which registers have that information,
* and all the relevant docs have gone to bit heaven :(
*/
- clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;
-
- if (IS_MOBILE(dev_priv)) {
- switch (clkcfg) {
- case CLKCFG_FSB_400:
- return 10;
- case CLKCFG_FSB_533:
- return 13;
- case CLKCFG_FSB_667:
- return 17;
- case CLKCFG_FSB_800:
- return 20;
- case CLKCFG_FSB_1067:
- return 27;
- case CLKCFG_FSB_1333:
- return 33;
- default:
- MISSING_CASE(clkcfg);
- return 13;
- }
- } else {
- switch (clkcfg) {
- case CLKCFG_FSB_400_ALT:
- return 10;
- case CLKCFG_FSB_533:
- return 13;
- case CLKCFG_FSB_667:
- return 17;
- case CLKCFG_FSB_800:
- return 20;
- case CLKCFG_FSB_1067_ALT:
- return 27;
- case CLKCFG_FSB_1333_ALT:
- return 33;
- case CLKCFG_FSB_1600_ALT:
- return 40;
- default:
- return 13;
- }
- }
+ return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4);
}
/**
--
2.39.2
[PATCH 08/12] drm/i915: use i9xx_fsb_freq() for GT clock frequency
Reuse i9xx_fsb_freq() for GT clock frequency initialization instead of
depending on rawclk_freq.
Note: If the init order was changed, we could use i915->fsb_freq
directly. However, GT clock initialization is done in
i915_driver_mmio_probe(), but intel_dram_detect() later in
i915_driver_hw_probe(), with a dependency on intel_pcode_init().
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 3 ++-
drivers/gpu/drm/i915/soc/intel_dram.c | 2 +-
drivers/gpu/drm/i915/soc/intel_dram.h | 1 +
3 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index 7c9be4fd1c8c..6e63505fe478 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -9,6 +9,7 @@
#include "intel_gt_clock_utils.h"
#include "intel_gt_print.h"
#include "intel_gt_regs.h"
+#include "soc/intel_dram.h"
static u32 read_reference_ts_freq(struct intel_uncore *uncore)
{
@@ -151,7 +152,7 @@ static u32 gen4_read_clock_frequency(struct intel_uncore
*uncore)
*
* Testing on actual hardware has shown there is no /16.
*/
- return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000;
+ return DIV_ROUND_CLOSEST(i9xx_fsb_freq(uncore->i915), 4) * 1000;
}
static u32 read_clock_frequency(struct intel_uncore *uncore)
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
b/drivers/gpu/drm/i915/soc/intel_dram.c
index 74b5b70e91f9..389bcf4b1abd 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -142,7 +142,7 @@ static void detect_mem_freq(struct drm_i915_private *i915)
drm_dbg(>drm, "DDR speed: %d kHz\n", i915->mem_freq);
}
-static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
+unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
{
u32 fsb;
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.h
b/drivers/gpu/drm/i915/soc/intel_dram.h
index 4ba13c13162c..a10136eda674 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.h
+++ b/drivers/gpu/drm/i915/soc/intel_dram.h
@@ -10,5 +10,6 @@ struct drm_i915_private;
void intel_dram_edram_detect(struct drm_i915_private *i915);
void intel_dram_detect(struct drm_i915_private *i915);
+unsigned int i9xx_fsb_freq(struct drm_i915_private *i915);
#endif /* __INTEL_DRAM_H__ */
--
2.39.2
[PATCH 07/12] drm/i915: extend the fsb_freq initialization to more platforms
Initialize fsb frequency for more platforms to be able to use it for GT
clock and rawclk frequency initialization.
Note: There's a discrepancy between existing pnv_fsb_freq() and
i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is
mobile.
FIXME: What should the default or failure mode be when the value is
unknown?
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/soc/intel_dram.c | 54 ---
1 file changed, 40 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
b/drivers/gpu/drm/i915/soc/intel_dram.c
index ace9372244a4..74b5b70e91f9 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -142,24 +142,50 @@ static void detect_mem_freq(struct drm_i915_private *i915)
drm_dbg(>drm, "DDR speed: %d kHz\n", i915->mem_freq);
}
-static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
+static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915)
{
u32 fsb;
fsb = intel_uncore_read(>uncore, CLKCFG) & CLKCFG_FSB_MASK;
- switch (fsb) {
- case CLKCFG_FSB_400:
- return 40;
- case CLKCFG_FSB_533:
- return 53;
- case CLKCFG_FSB_667:
- return 67;
- case CLKCFG_FSB_800:
- return 80;
+ if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) {
+ switch (fsb) {
+ case CLKCFG_FSB_400:
+ return 40;
+ case CLKCFG_FSB_533:
+ return 53;
+ case CLKCFG_FSB_667:
+ return 67;
+ case CLKCFG_FSB_800:
+ return 80;
+ case CLKCFG_FSB_1067:
+ return 107;
+ case CLKCFG_FSB_1333:
+ return 133;
+ default:
+ MISSING_CASE(fsb);
+ return 133;
+ }
+ } else {
+ switch (fsb) {
+ case CLKCFG_FSB_400_ALT:
+ return 40;
+ case CLKCFG_FSB_533:
+ return 53;
+ case CLKCFG_FSB_667:
+ return 67;
+ case CLKCFG_FSB_800:
+ return 80;
+ case CLKCFG_FSB_1067_ALT:
+ return 107;
+ case CLKCFG_FSB_1333_ALT:
+ return 133;
+ case CLKCFG_FSB_1600_ALT:
+ return 160;
+ default:
+ return 53;
+ }
}
-
- return 0;
}
static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
@@ -193,8 +219,8 @@ static void detect_fsb_freq(struct drm_i915_private *i915)
{
if (GRAPHICS_VER(i915) == 5)
i915->fsb_freq = ilk_fsb_freq(i915);
- else if (IS_PINEVIEW(i915))
- i915->fsb_freq = pnv_fsb_freq(i915);
+ else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4)
+ i915->fsb_freq = i9xx_fsb_freq(i915);
if (i915->fsb_freq)
drm_dbg(>drm, "FSB frequency: %d kHz\n", i915->fsb_freq);
--
2.39.2
[PATCH 06/12] drm/i915: convert fsb_freq and mem_freq to kHz
We'll want to use fsb frequency for deriving GT clock and rawclk
frequencies in the future. Increase the accuracy by converting to
kHz. Do the same for mem freq to be aligned.
Round the frequencies ending in 666 to 667.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 6 ++--
drivers/gpu/drm/i915/gt/intel_rps.c| 4 +--
drivers/gpu/drm/i915/soc/intel_dram.c | 50 +-
3 files changed, 30 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 8b8a0f305c3a..08c5d122af8f 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -83,14 +83,14 @@ static const struct cxsr_latency
*pnv_get_cxsr_latency(struct drm_i915_private *
if (is_desktop == latency->is_desktop &&
i915->is_ddr3 == latency->is_ddr3 &&
- i915->fsb_freq == latency->fsb_freq &&
- i915->mem_freq == latency->mem_freq)
+ DIV_ROUND_CLOSEST(i915->fsb_freq, 1000) ==
latency->fsb_freq &&
+ DIV_ROUND_CLOSEST(i915->mem_freq, 1000) ==
latency->mem_freq)
return latency;
}
err:
drm_dbg_kms(>drm,
- "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u
MHz\n",
+ "Could not find CxSR latency for DDR%s, FSB %u kHz, MEM %u
kHz\n",
i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
return NULL;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c
b/drivers/gpu/drm/i915/gt/intel_rps.c
index c9cb2a391942..5d3de1cddcf6 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -280,9 +280,9 @@ static void gen5_rps_init(struct intel_rps *rps)
u32 rgvmodectl;
int c_m, i;
- if (i915->fsb_freq <= 3200)
+ if (i915->fsb_freq <= 320)
c_m = 0;
- else if (i915->fsb_freq <= 4800)
+ else if (i915->fsb_freq <= 480)
c_m = 1;
else
c_m = 2;
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
b/drivers/gpu/drm/i915/soc/intel_dram.c
index 266ed6cfa485..ace9372244a4 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -56,11 +56,11 @@ static unsigned int pnv_mem_freq(struct drm_i915_private
*dev_priv)
switch (tmp & CLKCFG_MEM_MASK) {
case CLKCFG_MEM_533:
- return 533;
+ return 53;
case CLKCFG_MEM_667:
- return 667;
+ return 67;
case CLKCFG_MEM_800:
- return 800;
+ return 80;
}
return 0;
@@ -73,13 +73,13 @@ static unsigned int ilk_mem_freq(struct drm_i915_private
*dev_priv)
ddrpll = intel_uncore_read16(_priv->uncore, DDRMPLL1);
switch (ddrpll & 0xff) {
case 0xc:
- return 800;
+ return 80;
case 0x10:
- return 1066;
+ return 107;
case 0x14:
- return 1333;
+ return 133;
case 0x18:
- return 1600;
+ return 160;
default:
drm_dbg(_priv->drm, "unknown memory frequency 0x%02x\n",
ddrpll & 0xff);
@@ -97,9 +97,9 @@ static unsigned int chv_mem_freq(struct drm_i915_private
*i915)
switch ((val >> 2) & 0x7) {
case 3:
- return 2000;
+ return 200;
default:
- return 1600;
+ return 160;
}
}
@@ -114,11 +114,11 @@ static unsigned int vlv_mem_freq(struct drm_i915_private
*i915)
switch ((val >> 6) & 3) {
case 0:
case 1:
- return 800;
+ return 80;
case 2:
- return 1066;
+ return 107;
case 3:
- return 1333;
+ return 133;
}
return 0;
@@ -139,7 +139,7 @@ static void detect_mem_freq(struct drm_i915_private *i915)
i915->is_ddr3 = pnv_is_ddr3(i915);
if (i915->mem_freq)
- drm_dbg(>drm, "DDR speed: %d MHz\n", i915->mem_freq);
+ drm_dbg(>drm, "DDR speed: %d kHz\n", i915->mem_freq);
}
static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
@@ -150,13 +150,13 @@ static unsigned int pnv_fsb_freq(struct drm_i915_private
*i915)
switch (fsb) {
case CLKCFG_FSB_400:
- return 400;
+ return 40;
case CLKCFG_FSB_533:
- return 533;
+ return 5
[PATCH 05/12] drm/i915/dram: rearrange mem freq init
Follow the same style in mem freq init as in fsb freq init, returning
the value instead of assigning in multiple places.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/soc/intel_dram.c | 59 ---
1 file changed, 25 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
b/drivers/gpu/drm/i915/soc/intel_dram.c
index 1a4db52ac258..266ed6cfa485 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -48,7 +48,7 @@ static bool pnv_is_ddr3(struct drm_i915_private *i915)
return intel_uncore_read(>uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3;
}
-static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
+static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv)
{
u32 tmp;
@@ -56,44 +56,38 @@ static void pnv_detect_mem_freq(struct drm_i915_private
*dev_priv)
switch (tmp & CLKCFG_MEM_MASK) {
case CLKCFG_MEM_533:
- dev_priv->mem_freq = 533;
- break;
+ return 533;
case CLKCFG_MEM_667:
- dev_priv->mem_freq = 667;
- break;
+ return 667;
case CLKCFG_MEM_800:
- dev_priv->mem_freq = 800;
- break;
+ return 800;
}
+
+ return 0;
}
-static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv)
+static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv)
{
u16 ddrpll;
ddrpll = intel_uncore_read16(_priv->uncore, DDRMPLL1);
switch (ddrpll & 0xff) {
case 0xc:
- dev_priv->mem_freq = 800;
- break;
+ return 800;
case 0x10:
- dev_priv->mem_freq = 1066;
- break;
+ return 1066;
case 0x14:
- dev_priv->mem_freq = 1333;
- break;
+ return 1333;
case 0x18:
- dev_priv->mem_freq = 1600;
- break;
+ return 1600;
default:
drm_dbg(_priv->drm, "unknown memory frequency 0x%02x\n",
ddrpll & 0xff);
- dev_priv->mem_freq = 0;
- break;
+ return 0;
}
}
-static void chv_detect_mem_freq(struct drm_i915_private *i915)
+static unsigned int chv_mem_freq(struct drm_i915_private *i915)
{
u32 val;
@@ -103,15 +97,13 @@ static void chv_detect_mem_freq(struct drm_i915_private
*i915)
switch ((val >> 2) & 0x7) {
case 3:
- i915->mem_freq = 2000;
- break;
+ return 2000;
default:
- i915->mem_freq = 1600;
- break;
+ return 1600;
}
}
-static void vlv_detect_mem_freq(struct drm_i915_private *i915)
+static unsigned int vlv_mem_freq(struct drm_i915_private *i915)
{
u32 val;
@@ -122,27 +114,26 @@ static void vlv_detect_mem_freq(struct drm_i915_private
*i915)
switch ((val >> 6) & 3) {
case 0:
case 1:
- i915->mem_freq = 800;
- break;
+ return 800;
case 2:
- i915->mem_freq = 1066;
- break;
+ return 1066;
case 3:
- i915->mem_freq = 1333;
- break;
+ return 1333;
}
+
+ return 0;
}
static void detect_mem_freq(struct drm_i915_private *i915)
{
if (IS_PINEVIEW(i915))
- pnv_detect_mem_freq(i915);
+ i915->mem_freq = pnv_mem_freq(i915);
else if (GRAPHICS_VER(i915) == 5)
- ilk_detect_mem_freq(i915);
+ i915->mem_freq = ilk_mem_freq(i915);
else if (IS_CHERRYVIEW(i915))
- chv_detect_mem_freq(i915);
+ i915->mem_freq = chv_mem_freq(i915);
else if (IS_VALLEYVIEW(i915))
- vlv_detect_mem_freq(i915);
+ i915->mem_freq = vlv_mem_freq(i915);
if (IS_PINEVIEW(i915))
i915->is_ddr3 = pnv_is_ddr3(i915);
--
2.39.2
[PATCH 04/12] drm/i915/dram: split out pnv DDR3 detection
Split out the PNV DDR3 detection to a distinct step instead of
conflating it with mem freq detection.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/soc/intel_dram.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
b/drivers/gpu/drm/i915/soc/intel_dram.c
index 3dce9b9a2c5e..1a4db52ac258 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -43,6 +43,11 @@ static const char *intel_dram_type_str(enum intel_dram_type
type)
#undef DRAM_TYPE_STR
+static bool pnv_is_ddr3(struct drm_i915_private *i915)
+{
+ return intel_uncore_read(>uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3;
+}
+
static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
{
u32 tmp;
@@ -60,10 +65,6 @@ static void pnv_detect_mem_freq(struct drm_i915_private
*dev_priv)
dev_priv->mem_freq = 800;
break;
}
-
- /* detect pineview DDR3 setting */
- tmp = intel_uncore_read(_priv->uncore, CSHRDDR3CTL);
- dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
}
static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv)
@@ -143,6 +144,9 @@ static void detect_mem_freq(struct drm_i915_private *i915)
else if (IS_VALLEYVIEW(i915))
vlv_detect_mem_freq(i915);
+ if (IS_PINEVIEW(i915))
+ i915->is_ddr3 = pnv_is_ddr3(i915);
+
if (i915->mem_freq)
drm_dbg(>drm, "DDR speed: %d MHz\n", i915->mem_freq);
}
--
2.39.2
[PATCH 03/12] drm/i915/dram: separate fsb freq detection from mem freq
To simplify further changes, add separate functions for reading the fsb
frequency.
This ends up reading CLKCFG register twice, but it's not a big deal.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/soc/intel_dram.c | 106 +++---
1 file changed, 60 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c
b/drivers/gpu/drm/i915/soc/intel_dram.c
index 18a879e98f03..3dce9b9a2c5e 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -49,21 +49,6 @@ static void pnv_detect_mem_freq(struct drm_i915_private
*dev_priv)
tmp = intel_uncore_read(_priv->uncore, CLKCFG);
- switch (tmp & CLKCFG_FSB_MASK) {
- case CLKCFG_FSB_533:
- dev_priv->fsb_freq = 533; /* 133*4 */
- break;
- case CLKCFG_FSB_800:
- dev_priv->fsb_freq = 800; /* 200*4 */
- break;
- case CLKCFG_FSB_667:
- dev_priv->fsb_freq = 667; /* 167*4 */
- break;
- case CLKCFG_FSB_400:
- dev_priv->fsb_freq = 400; /* 100*4 */
- break;
- }
-
switch (tmp & CLKCFG_MEM_MASK) {
case CLKCFG_MEM_533:
dev_priv->mem_freq = 533;
@@ -83,7 +68,7 @@ static void pnv_detect_mem_freq(struct drm_i915_private
*dev_priv)
static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv)
{
- u16 ddrpll, csipll;
+ u16 ddrpll;
ddrpll = intel_uncore_read16(_priv->uncore, DDRMPLL1);
switch (ddrpll & 0xff) {
@@ -105,36 +90,6 @@ static void ilk_detect_mem_freq(struct drm_i915_private
*dev_priv)
dev_priv->mem_freq = 0;
break;
}
-
- csipll = intel_uncore_read16(_priv->uncore, CSIPLL0);
- switch (csipll & 0x3ff) {
- case 0x00c:
- dev_priv->fsb_freq = 3200;
- break;
- case 0x00e:
- dev_priv->fsb_freq = 3733;
- break;
- case 0x010:
- dev_priv->fsb_freq = 4266;
- break;
- case 0x012:
- dev_priv->fsb_freq = 4800;
- break;
- case 0x014:
- dev_priv->fsb_freq = 5333;
- break;
- case 0x016:
- dev_priv->fsb_freq = 5866;
- break;
- case 0x018:
- dev_priv->fsb_freq = 6400;
- break;
- default:
- drm_dbg(_priv->drm, "unknown fsb frequency 0x%04x\n",
- csipll & 0x3ff);
- dev_priv->fsb_freq = 0;
- break;
- }
}
static void chv_detect_mem_freq(struct drm_i915_private *i915)
@@ -192,6 +147,64 @@ static void detect_mem_freq(struct drm_i915_private *i915)
drm_dbg(>drm, "DDR speed: %d MHz\n", i915->mem_freq);
}
+static unsigned int pnv_fsb_freq(struct drm_i915_private *i915)
+{
+ u32 fsb;
+
+ fsb = intel_uncore_read(>uncore, CLKCFG) & CLKCFG_FSB_MASK;
+
+ switch (fsb) {
+ case CLKCFG_FSB_400:
+ return 400;
+ case CLKCFG_FSB_533:
+ return 533;
+ case CLKCFG_FSB_667:
+ return 667;
+ case CLKCFG_FSB_800:
+ return 800;
+ }
+
+ return 0;
+}
+
+static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv)
+{
+ u16 fsb;
+
+ fsb = intel_uncore_read16(_priv->uncore, CSIPLL0) & 0x3ff;
+
+ switch (fsb) {
+ case 0x00c:
+ return 3200;
+ case 0x00e:
+ return 3733;
+ case 0x010:
+ return 4266;
+ case 0x012:
+ return 4800;
+ case 0x014:
+ return 5333;
+ case 0x016:
+ return 5866;
+ case 0x018:
+ return 6400;
+ default:
+ drm_dbg(_priv->drm, "unknown fsb frequency 0x%04x\n", fsb);
+ return 0;
+ }
+}
+
+static void detect_fsb_freq(struct drm_i915_private *i915)
+{
+ if (GRAPHICS_VER(i915) == 5)
+ i915->fsb_freq = ilk_fsb_freq(i915);
+ else if (IS_PINEVIEW(i915))
+ i915->fsb_freq = pnv_fsb_freq(i915);
+
+ if (i915->fsb_freq)
+ drm_dbg(>drm, "FSB frequency: %d MHz\n", i915->fsb_freq);
+}
+
static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
{
return dimm->ranks * 64 / (dimm->width ?: 1);
@@ -661,6 +674,7 @@ void intel_dram_detect(struct drm_i915_private *i915)
struct dram_info *dram_info = >dram_info;
int ret;
+ detect_fsb_freq(i915);
detect_mem_freq(i915);
if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915))
--
2.39.2
[PATCH 01/12] drm/i915/wm: rename intel_get_cxsr_latency -> pnv_get_cxsr_latency
Clarify that the function is specific to PNV, making subsequent changes
slightly easier to grasp.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 628e7192ebc9..8657ec0abd2d 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -70,7 +70,7 @@ static const struct cxsr_latency cxsr_latency_table[] = {
{0, 1, 400, 800, 6042, 36042, 6584, 36584},/* DDR3-800 SC */
};
-static const struct cxsr_latency *intel_get_cxsr_latency(struct
drm_i915_private *i915)
+static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private
*i915)
{
int i;
@@ -635,7 +635,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
u32 reg;
unsigned int wm;
- latency = intel_get_cxsr_latency(dev_priv);
+ latency = pnv_get_cxsr_latency(dev_priv);
if (!latency) {
drm_dbg_kms(_priv->drm,
"Unknown FSB/MEM found, disable CxSR\n");
@@ -4022,7 +4022,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
g4x_setup_wm_latency(dev_priv);
dev_priv->display.funcs.wm = _wm_funcs;
} else if (IS_PINEVIEW(dev_priv)) {
- if (!intel_get_cxsr_latency(dev_priv)) {
+ if (!pnv_get_cxsr_latency(dev_priv)) {
drm_info(_priv->drm,
"failed to find known CxSR latency "
"(found ddr%s fsb freq %d, mem freq %d), "
--
2.39.2
[PATCH 02/12] drm/i915/wm: clarify logging on not finding CxSR latency config
Clarify and unify the logging on not finding PNV CxSR latency config.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 8657ec0abd2d..8b8a0f305c3a 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -75,7 +75,7 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct
drm_i915_private *
int i;
if (i915->fsb_freq == 0 || i915->mem_freq == 0)
- return NULL;
+ goto err;
for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
const struct cxsr_latency *latency = _latency_table[i];
@@ -88,7 +88,10 @@ static const struct cxsr_latency
*pnv_get_cxsr_latency(struct drm_i915_private *
return latency;
}
- drm_dbg_kms(>drm, "Unknown FSB/MEM found, disable CxSR\n");
+err:
+ drm_dbg_kms(>drm,
+ "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u
MHz\n",
+ i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq);
return NULL;
}
@@ -637,8 +640,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv)
latency = pnv_get_cxsr_latency(dev_priv);
if (!latency) {
- drm_dbg_kms(_priv->drm,
- "Unknown FSB/MEM found, disable CxSR\n");
+ drm_dbg_kms(_priv->drm, "Unknown FSB/MEM, disabling
CxSR\n");
intel_set_memory_cxsr(dev_priv, false);
return;
}
@@ -4023,12 +4025,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv)
dev_priv->display.funcs.wm = _wm_funcs;
} else if (IS_PINEVIEW(dev_priv)) {
if (!pnv_get_cxsr_latency(dev_priv)) {
- drm_info(_priv->drm,
-"failed to find known CxSR latency "
-"(found ddr%s fsb freq %d, mem freq %d), "
-"disabling CxSR\n",
-(dev_priv->is_ddr3 == 1) ? "3" : "2",
-dev_priv->fsb_freq, dev_priv->mem_freq);
+ drm_info(_priv->drm, "Unknown FSB/MEM, disabling
CxSR\n");
/* Disable CxSR and never update its watermark again */
intel_set_memory_cxsr(dev_priv, false);
dev_priv->display.funcs.wm = _funcs;
--
2.39.2
[PATCH 00/12] drm/i915: mem/fsb/rawclk freq cleanups
This is a rewitten version of [1]. I think it's good progress overall though there are still minor issues here and there. BR, Jani. [1] https://lore.kernel.org/all/20240408172315.3418692-1-jani.nik...@intel.com/ Jani Nikula (12): drm/i915/wm: rename intel_get_cxsr_latency -> pnv_get_cxsr_latency drm/i915/wm: clarify logging on not finding CxSR latency config drm/i915/dram: separate fsb freq detection from mem freq drm/i915/dram: split out pnv DDR3 detection drm/i915/dram: rearrange mem freq init drm/i915: convert fsb_freq and mem_freq to kHz drm/i915: extend the fsb_freq initialization to more platforms drm/i915: use i9xx_fsb_freq() for GT clock frequency drm/i915/cdclk: use i9xx_fsb_freq() for rawclk_freq initialization drm/i915: move rawclk init to intel_cdclk_init() drm/i915: move rawclk from runtime to display runtime info drm/xe/display: drop unused rawclk_freq and RUNTIME_INFO() drivers/gpu/drm/i915/display/i9xx_wm.c| 27 ++- .../gpu/drm/i915/display/intel_backlight.c| 10 +- drivers/gpu/drm/i915/display/intel_cdclk.c| 69 ++ drivers/gpu/drm/i915/display/intel_cdclk.h| 1 - .../drm/i915/display/intel_display_device.c | 2 + .../drm/i915/display/intel_display_device.h | 2 + .../i915/display/intel_display_power_well.c | 4 +- drivers/gpu/drm/i915/display/intel_dp_aux.c | 4 +- drivers/gpu/drm/i915/display/intel_pps.c | 2 +- .../gpu/drm/i915/gt/intel_gt_clock_utils.c| 3 +- drivers/gpu/drm/i915/gt/intel_rps.c | 4 +- drivers/gpu/drm/i915/intel_device_info.c | 5 - drivers/gpu/drm/i915/intel_device_info.h | 2 - drivers/gpu/drm/i915/soc/intel_dram.c | 203 ++ drivers/gpu/drm/i915/soc/intel_dram.h | 1 + .../gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 - drivers/gpu/drm/xe/xe_device_types.h | 6 - 17 files changed, 164 insertions(+), 182 deletions(-) -- 2.39.2
Re: [PATCH v2] drm/i915/display: update handling of FBC when VT-d active workaround
On Tue, 28 May 2024, Vinod Govindapillai wrote:
> Move the handling of the disabling FBC when VT-d is active wa
> as part of the intel_fbc_check_plane(). As the hw is still there,
> intel_fbc_sanitize should be able to handle the state properly.
>
> v2: update the patch description (Jani Nikula)
>
> Bspec: 21664
> Suggested-by: Ville Syrjälä
> Signed-off-by: Vinod Govindapillai
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 22 ++
> 1 file changed, 6 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index e9189a864f69..492dc26ecfa2 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1235,6 +1235,12 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
> return 0;
> }
>
> + /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
> + if (i915_vtd_active(i915) && (IS_SKYLAKE(i915) || IS_BROXTON(i915))) {
> + plane_state->no_fbc_reason = "VT-d enabled";
> + return true;
Sorry for only glancing at the commit message first time around.
This one here returns true from a function that uses int error codes and
0 means success. And the 1 is interpreted as an error.
BR,
Jani.
> + }
> +
> crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
>
> if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> @@ -1820,19 +1826,6 @@ static int intel_sanitize_fbc_option(struct
> drm_i915_private *i915)
> return 0;
> }
>
> -static bool need_fbc_vtd_wa(struct drm_i915_private *i915)
> -{
> - /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
> - if (i915_vtd_active(i915) &&
> - (IS_SKYLAKE(i915) || IS_BROXTON(i915))) {
> - drm_info(>drm,
> - "Disabling framebuffer compression (FBC) to prevent
> screen flicker with VT-d enabled\n");
> - return true;
> - }
> -
> - return false;
> -}
> -
> void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)
> {
> plane->fbc = fbc;
> @@ -1878,9 +1871,6 @@ void intel_fbc_init(struct drm_i915_private *i915)
> {
> enum intel_fbc_id fbc_id;
>
> - if (need_fbc_vtd_wa(i915))
> - DISPLAY_RUNTIME_INFO(i915)->fbc_mask = 0;
> -
> i915->display.params.enable_fbc = intel_sanitize_fbc_option(i915);
> drm_dbg_kms(>drm, "Sanitized enable_fbc value: %d\n",
> i915->display.params.enable_fbc);
--
Jani Nikula, Intel
[PATCH 5/5] drm/i915: remove intermediate _PCH_DP_* macros
The intermediate macros are unused. Remove them. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 11 +++ 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 06e41afd5c4e..6877e2f0fbc3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3599,14 +3599,9 @@ #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) -#define _PCH_DP_B 0xe4100 -#define PCH_DP_B _MMIO(_PCH_DP_B) - -#define _PCH_DP_C 0xe4200 -#define PCH_DP_C _MMIO(_PCH_DP_C) - -#define _PCH_DP_D 0xe4300 -#define PCH_DP_D _MMIO(_PCH_DP_D) +#define PCH_DP_B _MMIO(0xe4100) +#define PCH_DP_C _MMIO(0xe4200) +#define PCH_DP_D _MMIO(0xe4300) /* CPT */ #define _TRANS_DP_CTL_A0xe0300 -- 2.39.2
[PATCH 4/5] drm/i915: move PCH DP AUX CH regs to intel_dp_aux_regs.h
Move the macros where they belong. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dp_aux_regs.h | 8 drivers/gpu/drm/i915/i915_reg.h | 7 --- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h index a438f6003ce4..4e109e81409b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h @@ -28,6 +28,10 @@ #define VLV_DP_AUX_CH_CTL(aux_ch) _MMIO(VLV_DISPLAY_BASE + \ _PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)) +#define _PCH_DPB_AUX_CH_CTL0xe4110 +#define _PCH_DPC_AUX_CH_CTL0xe4210 +#define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) + #define _XELPDP_USBC1_AUX_CH_CTL 0x16f210 #define _XELPDP_USBC2_AUX_CH_CTL 0x16f410 #define _XELPDP_DP_AUX_CH_CTL(aux_ch) \ @@ -78,6 +82,10 @@ #define VLV_DP_AUX_CH_DATA(aux_ch, i) _MMIO(VLV_DISPLAY_BASE + _PORT(aux_ch, _DPA_AUX_CH_DATA1, \ _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ +#define _PCH_DPB_AUX_CH_DATA1 0xe4114 +#define _PCH_DPC_AUX_CH_DATA1 0xe4214 +#define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ + #define _XELPDP_USBC1_AUX_CH_DATA1 0x16f214 #define _XELPDP_USBC2_AUX_CH_DATA1 0x16f414 #define _XELPDP_DP_AUX_CH_DATA(aux_ch, i) \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 989cc5691490..06e41afd5c4e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3601,20 +3601,13 @@ #define _PCH_DP_B 0xe4100 #define PCH_DP_B _MMIO(_PCH_DP_B) -#define _PCH_DPB_AUX_CH_CTL0xe4110 -#define _PCH_DPB_AUX_CH_DATA1 0xe4114 #define _PCH_DP_C 0xe4200 #define PCH_DP_C _MMIO(_PCH_DP_C) -#define _PCH_DPC_AUX_CH_CTL0xe4210 -#define _PCH_DPC_AUX_CH_DATA1 0xe4214 #define _PCH_DP_D 0xe4300 #define PCH_DP_D _MMIO(_PCH_DP_D) -#define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) -#define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ - /* CPT */ #define _TRANS_DP_CTL_A0xe0300 #define _TRANS_DP_CTL_B0xe1300 -- 2.39.2
[PATCH 3/5] drm/i915: rearrange DP AUX register macros
Follow the recommended style for grouping register macros. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dp_aux_regs.h | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h index e642445364d2..a438f6003ce4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h @@ -23,12 +23,13 @@ #define _DPA_AUX_CH_CTL0x64010 #define _DPB_AUX_CH_CTL0x64110 -#define _XELPDP_USBC1_AUX_CH_CTL 0x16f210 -#define _XELPDP_USBC2_AUX_CH_CTL 0x16f410 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, \ _DPB_AUX_CH_CTL) #define VLV_DP_AUX_CH_CTL(aux_ch) _MMIO(VLV_DISPLAY_BASE + \ _PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)) + +#define _XELPDP_USBC1_AUX_CH_CTL 0x16f210 +#define _XELPDP_USBC2_AUX_CH_CTL 0x16f410 #define _XELPDP_DP_AUX_CH_CTL(aux_ch) \ _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \ _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL, \ @@ -72,12 +73,13 @@ #define _DPA_AUX_CH_DATA1 0x64014 #define _DPB_AUX_CH_DATA1 0x64114 -#define _XELPDP_USBC1_AUX_CH_DATA1 0x16f214 -#define _XELPDP_USBC2_AUX_CH_DATA1 0x16f414 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, \ _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ #define VLV_DP_AUX_CH_DATA(aux_ch, i) _MMIO(VLV_DISPLAY_BASE + _PORT(aux_ch, _DPA_AUX_CH_DATA1, \ _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ + +#define _XELPDP_USBC1_AUX_CH_DATA1 0x16f214 +#define _XELPDP_USBC2_AUX_CH_DATA1 0x16f414 #define _XELPDP_DP_AUX_CH_DATA(aux_ch, i) \ _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \ _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1, \ -- 2.39.2
[PATCH 2/5] drm/i915: remove unused DP AUX CH register macros
The intermediate macros are no longer needed. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 14 -- 1 file changed, 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index be57812a6b07..989cc5691490 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3603,28 +3603,14 @@ #define PCH_DP_B _MMIO(_PCH_DP_B) #define _PCH_DPB_AUX_CH_CTL0xe4110 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 -#define _PCH_DPB_AUX_CH_DATA2 0xe4118 -#define _PCH_DPB_AUX_CH_DATA3 0xe411c -#define _PCH_DPB_AUX_CH_DATA4 0xe4120 -#define _PCH_DPB_AUX_CH_DATA5 0xe4124 #define _PCH_DP_C 0xe4200 #define PCH_DP_C _MMIO(_PCH_DP_C) #define _PCH_DPC_AUX_CH_CTL0xe4210 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 -#define _PCH_DPC_AUX_CH_DATA2 0xe4218 -#define _PCH_DPC_AUX_CH_DATA3 0xe421c -#define _PCH_DPC_AUX_CH_DATA4 0xe4220 -#define _PCH_DPC_AUX_CH_DATA5 0xe4224 #define _PCH_DP_D 0xe4300 #define PCH_DP_D _MMIO(_PCH_DP_D) -#define _PCH_DPD_AUX_CH_CTL0xe4310 -#define _PCH_DPD_AUX_CH_DATA1 0xe4314 -#define _PCH_DPD_AUX_CH_DATA2 0xe4318 -#define _PCH_DPD_AUX_CH_DATA3 0xe431c -#define _PCH_DPD_AUX_CH_DATA4 0xe4320 -#define _PCH_DPD_AUX_CH_DATA5 0xe4324 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ -- 2.39.2
[PATCH 1/5] drm/i915/gvt: use proper macros for DP AUX CH CTL registers
Use the proper helpers for DP AUX CH CTL registers, instead of
reinventing the wheels.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/gvt/handlers.c | 35 ++---
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++---
2 files changed, 20 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
b/drivers/gpu/drm/i915/gvt/handlers.c
index cd4ec480138b..708b99be02ac 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -1084,13 +1084,13 @@ static int trigger_aux_channel_interrupt(struct
intel_vgpu *vgpu,
if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A)))
event = AUX_CHANNEL_A;
- else if (reg == _PCH_DPB_AUX_CH_CTL ||
+ else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_B)) ||
reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B)))
event = AUX_CHANNEL_B;
- else if (reg == _PCH_DPC_AUX_CH_CTL ||
+ else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_C)) ||
reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C)))
event = AUX_CHANNEL_C;
- else if (reg == _PCH_DPD_AUX_CH_CTL ||
+ else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_D)) ||
reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))
event = AUX_CHANNEL_D;
else {
@@ -1154,11 +1154,6 @@ static void dp_aux_ch_ctl_link_training(struct
intel_vgpu_dpcd_data *dpcd,
}
}
-#define _REG_HSW_DP_AUX_CH_CTL(dp) \
- ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
-
-#define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
-
#define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
#define dpy_is_valid_port(port)\
@@ -1182,12 +1177,14 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu
*vgpu,
write_vreg(vgpu, offset, p_data, bytes);
data = vgpu_vreg(vgpu, offset);
- if ((GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9)
- && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
+ if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9 &&
+ offset != i915_mmio_reg_offset(DP_AUX_CH_CTL(port_index))) {
/* SKL DPB/C/D aux ctl register changed */
return 0;
} else if (IS_BROADWELL(vgpu->gvt->gt->i915) &&
- offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
+ offset != i915_mmio_reg_offset(port_index ?
+ PCH_DP_AUX_CH_CTL(port_index)
:
+ DP_AUX_CH_CTL(port_index))) {
/* write to the data registers */
return 0;
}
@@ -2300,12 +2297,12 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
gmbus_mmio_write);
MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
- MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
- dp_aux_ch_ctl_mmio_write);
- MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
- dp_aux_ch_ctl_mmio_write);
- MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
- dp_aux_ch_ctl_mmio_write);
+ MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
+ dp_aux_ch_ctl_mmio_write);
+ MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
+ dp_aux_ch_ctl_mmio_write);
+ MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
+ dp_aux_ch_ctl_mmio_write);
MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write);
@@ -2342,8 +2339,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
- MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL,
- dp_aux_ch_ctl_mmio_write);
+ MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4, 0, 0, 0, D_ALL, NULL,
+ dp_aux_ch_ctl_mmio_write);
MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index 349578cc0fc8..f5c4e4e2f11f 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -517,7 +517,7 @@ static int iterate_generic_mmio(struct
intel_gvt_mmio_table_iter *iter)
MMIO_D(SBI_DATA);
MMIO_D(SBI_CTL_STAT);
MMIO_D(PIXCLK_GATE);
- MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4);
+ MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4);
MMIO_D(DDI_BUF_CTL(PORT_A));
MMIO_D(DDI_BUF_CTL(PORT_B));
MMIO_D(DDI_BU
[PATCH 0/5] drm/i915: DP AUX CH macro cleanups
Jani Nikula (5): drm/i915/gvt: use proper macros for DP AUX CH CTL registers drm/i915: remove unused DP AUX CH register macros drm/i915: rearrange DP AUX register macros drm/i915: move PCH DP AUX CH regs to intel_dp_aux_regs.h drm/i915: remove intermediate _PCH_DP_* macros .../gpu/drm/i915/display/intel_dp_aux_regs.h | 18 +++--- drivers/gpu/drm/i915/gvt/handlers.c | 35 +-- drivers/gpu/drm/i915/i915_reg.h | 32 ++--- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++--- 4 files changed, 37 insertions(+), 56 deletions(-) -- 2.39.2
Re: [PATCH] drm/i915/display: update handling of FBC when VT-d active workaround
On Tue, 28 May 2024, Vinod Govindapillai wrote:
> Move the handling of the disabling FBC when VT-d is active wa
> as part of the intel_fbc_check_plane()
I can see that from the code.
The commit message must answer the question "why".
BR,
Jani.
>
> Bspec: 21664
> Signed-off-by: Vinod Govindapillai
> ---
> drivers/gpu/drm/i915/display/intel_fbc.c | 22 ++
> 1 file changed, 6 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> b/drivers/gpu/drm/i915/display/intel_fbc.c
> index e9189a864f69..492dc26ecfa2 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -1235,6 +1235,12 @@ static int intel_fbc_check_plane(struct
> intel_atomic_state *state,
> return 0;
> }
>
> + /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
> + if (i915_vtd_active(i915) && (IS_SKYLAKE(i915) || IS_BROXTON(i915))) {
> + plane_state->no_fbc_reason = "VT-d enabled";
> + return true;
> + }
> +
> crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
>
> if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> @@ -1820,19 +1826,6 @@ static int intel_sanitize_fbc_option(struct
> drm_i915_private *i915)
> return 0;
> }
>
> -static bool need_fbc_vtd_wa(struct drm_i915_private *i915)
> -{
> - /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
> - if (i915_vtd_active(i915) &&
> - (IS_SKYLAKE(i915) || IS_BROXTON(i915))) {
> - drm_info(>drm,
> - "Disabling framebuffer compression (FBC) to prevent
> screen flicker with VT-d enabled\n");
> - return true;
> - }
> -
> - return false;
> -}
> -
> void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane)
> {
> plane->fbc = fbc;
> @@ -1878,9 +1871,6 @@ void intel_fbc_init(struct drm_i915_private *i915)
> {
> enum intel_fbc_id fbc_id;
>
> - if (need_fbc_vtd_wa(i915))
> - DISPLAY_RUNTIME_INFO(i915)->fbc_mask = 0;
> -
> i915->display.params.enable_fbc = intel_sanitize_fbc_option(i915);
> drm_dbg_kms(>drm, "Sanitized enable_fbc value: %d\n",
> i915->display.params.enable_fbc);
--
Jani Nikula, Intel
Re: ✗ Fi.CI.BAT: failure for Revert "igc: fix a log entry using uninitialized netdev"
ther test skip >[80]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134112v1/bat-arls-1/igt@prime_v...@basic-gtt.html > > * igt@prime_vgem@basic-read: > - fi-rkl-11600: NOTRUN -> [SKIP][81] ([i915#3291] / [i915#3708]) +2 > other tests skip >[81]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134112v1/fi-rkl-11600/igt@prime_v...@basic-read.html > - bat-arls-2: NOTRUN -> [SKIP][82] ([i915#10214] / [i915#3708]) >[82]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134112v1/bat-arls-2/igt@prime_v...@basic-read.html > - bat-arls-1: NOTRUN -> [SKIP][83] ([i915#10214] / [i915#3708]) >[83]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134112v1/bat-arls-1/igt@prime_v...@basic-read.html > > * igt@prime_vgem@basic-write: > - bat-arls-2: NOTRUN -> [SKIP][84] ([i915#10216] / [i915#3708]) >[84]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134112v1/bat-arls-2/igt@prime_v...@basic-write.html > - bat-arls-1: NOTRUN -> [SKIP][85] ([i915#10216] / [i915#3708]) >[85]: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134112v1/bat-arls-1/igt@prime_v...@basic-write.html > > > [i915#10196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10196 > [i915#10197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10197 > [i915#10200]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10200 > [i915#10202]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10202 > [i915#10206]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10206 > [i915#10207]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10207 > [i915#10208]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10208 > [i915#10209]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10209 > [i915#10211]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10211 > [i915#10212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10212 > [i915#10213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10213 > [i915#10214]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10214 > [i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216 > [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072 > [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849 > [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190 > [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282 > [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291 > [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555 > [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708 > [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840 > [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077 > [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079 > [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083 > [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103 > [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212 > [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213 > [i915#4215]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4215 > [i915#433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/433 > [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613 > [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354 > [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621 > [i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809 > [i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318 > [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688 > [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732 > [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812 > [i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886 > > > Build changes > - > > * Linux: CI_DRM_14828 -> Patchwork_134112v1 > > CI-20190529: 20190529 > CI_DRM_14828: abaeae202dfb4e361edd660a124e22178340725d @ > git://anongit.freedesktop.org/gfx-ci/linux > IGT_7871: 1d7b961235e345db20933c057f265898e2e96fd2 @ > https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_134112v1: abaeae202dfb4e361edd660a124e22178340725d @ > git://anongit.freedesktop.org/gfx-ci/linux > > == Logs == > > For more details see: > https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_134112v1/index.html -- Jani Nikula, Intel
RE: [PATCH 0/6] drm/i915/pps: pass dev_priv explicitly to PPS regs
On Tue, 28 May 2024, "Borah, Chaitanya Kumar" wrote: >> -Original Message- >> From: Intel-gfx On Behalf Of Jani >> Nikula >> Sent: Monday, May 27, 2024 4:12 PM >> To: intel-gfx@lists.freedesktop.org >> Cc: Nikula, Jani ; ville.syrj...@linux.intel.com >> Subject: [PATCH 0/6] drm/i915/pps: pass dev_priv explicitly to PPS regs >> >> Continue avoiding the implicit dev_priv local variable. >> > > LGTM > Reviewed-by: Chaitanya Kumar Borah Thanks for the review, pushed to din. BR, Jani. -- Jani Nikula, Intel
RE: [PATCH 00/11] drm/i915: pass dev_priv explicitly to DIP regs
On Tue, 28 May 2024, "Borah, Chaitanya Kumar" wrote: >> -Original Message- >> From: Intel-gfx On Behalf Of Jani >> Nikula >> Sent: Monday, May 27, 2024 4:41 PM >> To: intel-gfx@lists.freedesktop.org >> Cc: Nikula, Jani >> Subject: [PATCH 00/11] drm/i915: pass dev_priv explicitly to DIP regs >> >> Continue removing implicit dev_priv references. >> > > LGTM > Reviewed-by: Chaitanya Kumar Borah Thanks for the review, pushed to din. BR, Jani. -- Jani Nikula, Intel
[core-for-CI PATCH] Revert "igc: fix a log entry using uninitialized netdev"
This reverts commit 86167183a17e03ec77198897975e9fdfbd53cb0b. The commit moved igc_ptp_init() which initializes spinlocks after igt_reset() which ends up using the adapter->ptp_tx_lock. Lockdep isn't happy: <3>[ 10.648947] INFO: trying to register non-static key. <3>[ 10.648950] The code is fine but needs lockdep annotation, or maybe <3>[ 10.648951] you didn't initialize this object before use? <3>[ 10.648952] turning off the locking correctness validator. <4>[ 10.648954] CPU: 2 PID: 313 Comm: systemd-udevd Not tainted 6.9.0-next-20240513-next-20240513-g6ba6c795dc73+ #1 <4>[ 10.648958] Hardware name: Intel Corporation Arrow Lake Client Platform/MTL-S UDIMM 2DPC EVCRB, BIOS MTLSFWI1.R00.3473.D80.2311222130 11/22/2023 <4>[ 10.648960] Call Trace: <4>[ 10.648962] <4>[ 10.648964] dump_stack_lvl+0x82/0xd0 <4>[ 10.648971] register_lock_class+0x795/0x7e0 <4>[ 10.648978] ? __free_object+0xa1/0x340 <4>[ 10.648983] ? lockdep_hardirqs_on+0xc1/0x140 <4>[ 10.648990] __lock_acquire+0x75/0x2260 <4>[ 10.648993] ? __switch_to+0x123/0x600 <4>[ 10.648997] ? _raw_spin_unlock_irqrestore+0x58/0x70 <4>[ 10.649002] lock_acquire+0xd9/0x2f0 <4>[ 10.649006] ? igc_ptp_clear_tx_tstamp+0x28/0x60 [igc] <4>[ 10.649027] _raw_spin_lock_irqsave+0x3d/0x60 <4>[ 10.649030] ? igc_ptp_clear_tx_tstamp+0x28/0x60 [igc] <4>[ 10.649038] igc_ptp_clear_tx_tstamp+0x28/0x60 [igc] <4>[ 10.649048] igc_ptp_set_timestamp_mode.isra.0+0x20b/0x230 [igc] <4>[ 10.649056] igc_ptp_reset+0x31/0x180 [igc] <4>[ 10.649066] igc_reset+0xb4/0x100 [igc] <4>[ 10.649079] igc_probe+0x797/0x8e0 [igc] <4>[ 10.649091] pci_device_probe+0x95/0x120 <4>[ 10.649095] really_probe+0xd9/0x370 <4>[ 10.649099] ? __pfx___driver_attach+0x10/0x10 <4>[ 10.649101] __driver_probe_device+0x73/0x150 <4>[ 10.649103] driver_probe_device+0x19/0xa0 <4>[ 10.649105] __driver_attach+0xb6/0x180 <4>[ 10.649107] ? __pfx___driver_attach+0x10/0x10 <4>[ 10.649109] bus_for_each_dev+0x77/0xd0 <4>[ 10.649114] bus_add_driver+0x110/0x240 <4>[ 10.649117] driver_register+0x5b/0x110 <4>[ 10.649120] ? __pfx_igc_init_module+0x10/0x10 [igc] <4>[ 10.649130] do_one_initcall+0x5c/0x2b0 <4>[ 10.649134] ? kmalloc_trace_noprof+0x22f/0x290 <4>[ 10.649141] ? do_init_module+0x1e/0x210 <4>[ 10.669989] do_init_module+0x5f/0x210 <4>[ 10.669993] load_module+0x1d44/0x1fc0 <4>[ 10.670001] ? init_module_from_file+0x86/0xd0 <4>[ 10.670004] init_module_from_file+0x86/0xd0 <4>[ 10.670009] idempotent_init_module+0x17c/0x230 <4>[ 10.670015] __x64_sys_finit_module+0x56/0xb0 <4>[ 10.670019] do_syscall_64+0x69/0x140 <4>[ 10.670023] entry_SYSCALL_64_after_hwframe+0x76/0x7e <4>[ 10.670027] RIP: 0033:0x7f6d2704595d <4>[ 10.670030] Code: 00 c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 03 35 0d 00 f7 d8 64 89 01 48 <4>[ 10.670032] RSP: 002b:7ffc72aad018 EFLAGS: 0246 ORIG_RAX: 0139 <4>[ 10.670036] RAX: ffda RBX: 55d3f0e69690 RCX: 7f6d2704595d <4>[ 10.670038] RDX: RSI: 7f6d26f25ded RDI: 0010 <4>[ 10.670039] RBP: 0002 R08: R09: <4>[ 10.670041] R10: 0010 R11: 0246 R12: 00007f6d26f25ded <4>[ 10.670042] R13: R14: 55d3f0c64d20 R15: 55d3f0e69690 <4>[ 10.670046] <6>[ 10.672046] pps pps0: new PPS source ptp0 References: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11198 References: https://lore.kernel.org/r/87o78rmkhu@intel.com Signed-off-by: Jani Nikula --- drivers/net/ethernet/intel/igc/igc_main.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c index 12f004f46082..ace2fbfd87d6 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -7028,6 +7028,8 @@ static int igc_probe(struct pci_dev *pdev, device_set_wakeup_enable(>pdev->dev, adapter->flags & IGC_FLAG_WOL_SUPPORTED); + igc_ptp_init(adapter); + igc_tsn_clear_schedule(adapter); /* reset the hardware with the new settings */ @@ -7049,9 +7051,6 @@ static int igc_probe(struct pci_dev *pdev, /* Check if Media Autosense is enabled */ adapter->ei = *ei; - /* do hw tstamp init after resetting */ - igc_ptp_init(adapter); - /* print pcie link status and MAC address */ pcie_print_link_status(pdev); netdev_info(netdev, "MAC: %pM\n", netdev->dev_addr); -- 2.39.2
Re: [PATCH 1/2] drm/i915: move rawclk init to intel_cdclk_init()
On Mon, 27 May 2024, Jani Nikula wrote:
> On Mon, 08 Apr 2024, Ville Syrjälä wrote:
>> On Mon, Apr 08, 2024 at 08:28:27PM +0300, Ville Syrjälä wrote:
>>> On Mon, Apr 08, 2024 at 08:23:14PM +0300, Jani Nikula wrote:
>>> > The rawclk initialization is a bit out of place in
>>> > intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a
>>> > bit of refactoring on intel_read_rawclk().
>>>
>>> rawclk is used outside of display.
>>
>> The correct solution would likely be to extract a
>> i9xx_fsb_freq(), and use that to populate both rawclk_freq
>> and fsb_freq (and switch over to fsb_freq in the
>> non-display code).
>
> I circled back to this, and PNV seems to be the problem case for making
> this happen.
>
> pnv_detect_mem_freq() in intel_dram.c and i9xx_hrawclk() in
> intel_cdclk.c interpret the CLKCFG register slightly differently.
>
> I'm presuming PNV only supports a subset of the values covered by
> i9xx_hrawclk(). For IS_MOBILE() they all match, but for !IS_MOBILE()
> there's a different value for 400 MHz FSB.
>
> So how should desktop PNV interpret the register, I wonder? I can't find
> any specs on that anymore.
My guess would be this:
index b78154c82a71..19ca3ed5212a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3545,7 +3545,7 @@ static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
*/
clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;
- if (IS_MOBILE(dev_priv)) {
+ if (IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv)) {
switch (clkcfg) {
case CLKCFG_FSB_400:
return 10;
--
Jani Nikula, Intel
Re: [PATCH 1/2] drm/i915: move rawclk init to intel_cdclk_init()
On Mon, 08 Apr 2024, Ville Syrjälä wrote: > On Mon, Apr 08, 2024 at 08:28:27PM +0300, Ville Syrjälä wrote: >> On Mon, Apr 08, 2024 at 08:23:14PM +0300, Jani Nikula wrote: >> > The rawclk initialization is a bit out of place in >> > intel_device_info_runtime_init(). Move it to intel_cdclk_init(), with a >> > bit of refactoring on intel_read_rawclk(). >> >> rawclk is used outside of display. > > The correct solution would likely be to extract a > i9xx_fsb_freq(), and use that to populate both rawclk_freq > and fsb_freq (and switch over to fsb_freq in the > non-display code). I circled back to this, and PNV seems to be the problem case for making this happen. pnv_detect_mem_freq() in intel_dram.c and i9xx_hrawclk() in intel_cdclk.c interpret the CLKCFG register slightly differently. I'm presuming PNV only supports a subset of the values covered by i9xx_hrawclk(). For IS_MOBILE() they all match, but for !IS_MOBILE() there's a different value for 400 MHz FSB. So how should desktop PNV interpret the register, I wonder? I can't find any specs on that anymore. BR, Jani. -- Jani Nikula, Intel
Re: [PATCH 2/2] drm: use mem_is_zero() instead of !memchr_inv(s, 0, n)
On Mon, 27 May 2024, Andy Shevchenko wrote:
> On Mon, May 27, 2024 at 12:43 PM Jani Nikula wrote:
>>
>> Use the mem_is_zero() helper where possible.
>
> ...
>
>> - if (memchr_inv(guid, 0, 16) == NULL) {
>> + if (mem_is_zero(guid, 16)) {
>> tmp64 = get_jiffies_64();
>> memcpy([0], , sizeof(u64));
>> memcpy([8], , sizeof(u64));
>
> What is the type of guid? Shouldn't it be guid_t with the respective
> guid_is_null()
I can leave out these parts of the patch.
BR,
Jani.
>
> ...
>
>> - if (memchr_inv(guid, 0, 16))
>> + if (!mem_is_zero(guid, 16))
>> return true;
>
> Ditto.
--
Jani Nikula, Intel
Re: [PATCH 1/2] string: add mem_is_zero() helper to check if memory area is all zeros
On Mon, 27 May 2024, Andy Shevchenko wrote:
> On Mon, May 27, 2024 at 12:43 PM Jani Nikula wrote:
>>
>> Almost two thirds of the memchr_inv() usages check if the memory area is
>> all zeros, with no interest in where in the buffer the first non-zero
>> byte is located. Checking for !memchr_inv(s, 0, n) is also not very
>> intuitive or discoverable. Add an explicit mem_is_zero() helper for this
>> use case.
>
> ...
>
>> +static inline bool mem_is_zero(const void *s, size_t n)
>> +{
>> + return !memchr_inv(s, 0, n);
>> +}
>
> There are potential users for the 0xff check as well. Hence the
> following question:
> Are we going to have a new function per byte in question, or do we
> come up with a common denominator, like mem_is_all_of(mem, byte)?
No. As I wrote in the commit message rationale, "Almost two thirds of
the memchr_inv() usages check if the memory area is all zeros". This is
by far the most common use case of memchr_inv().
BR,
Jani.
--
Jani Nikula, Intel
REGRESSION: 86167183a17e ("igc: fix a log entry using uninitialized netdev")
Hi all, the Intel graphics CI hits a lockdep issue with commit
86167183a17e ("igc: fix a log entry using uninitialized netdev") in
v6.10-rc1.
The commit moved igc_ptp_init() which initializes spinlocks after
igt_reset() which ends up using the adapter->ptp_tx_lock. Lockdep isn't
happy:
<3>[ 10.648947] INFO: trying to register non-static key.
<3>[ 10.648950] The code is fine but needs lockdep annotation, or maybe
<3>[ 10.648951] you didn't initialize this object before use?
<3>[ 10.648952] turning off the locking correctness validator.
<4>[ 10.648954] CPU: 2 PID: 313 Comm: systemd-udevd Not tainted
6.9.0-next-20240513-next-20240513-g6ba6c795dc73+ #1
<4>[ 10.648958] Hardware name: Intel Corporation Arrow Lake Client
Platform/MTL-S UDIMM 2DPC EVCRB, BIOS MTLSFWI1.R00.3473.D80.2311222130
11/22/2023
<4>[ 10.648960] Call Trace:
<4>[ 10.648962]
<4>[ 10.648964] dump_stack_lvl+0x82/0xd0
<4>[ 10.648971] register_lock_class+0x795/0x7e0
<4>[ 10.648978] ? __free_object+0xa1/0x340
<4>[ 10.648983] ? lockdep_hardirqs_on+0xc1/0x140
<4>[ 10.648990] __lock_acquire+0x75/0x2260
<4>[ 10.648993] ? __switch_to+0x123/0x600
<4>[ 10.648997] ? _raw_spin_unlock_irqrestore+0x58/0x70
<4>[ 10.649002] lock_acquire+0xd9/0x2f0
<4>[ 10.649006] ? igc_ptp_clear_tx_tstamp+0x28/0x60 [igc]
<4>[ 10.649027] _raw_spin_lock_irqsave+0x3d/0x60
<4>[ 10.649030] ? igc_ptp_clear_tx_tstamp+0x28/0x60 [igc]
<4>[ 10.649038] igc_ptp_clear_tx_tstamp+0x28/0x60 [igc]
<4>[ 10.649048] igc_ptp_set_timestamp_mode.isra.0+0x20b/0x230 [igc]
<4>[ 10.649056] igc_ptp_reset+0x31/0x180 [igc]
<4>[ 10.649066] igc_reset+0xb4/0x100 [igc]
<4>[ 10.649079] igc_probe+0x797/0x8e0 [igc]
<4>[ 10.649091] pci_device_probe+0x95/0x120
<4>[ 10.649095] really_probe+0xd9/0x370
<4>[ 10.649099] ? __pfx___driver_attach+0x10/0x10
<4>[ 10.649101] __driver_probe_device+0x73/0x150
<4>[ 10.649103] driver_probe_device+0x19/0xa0
<4>[ 10.649105] __driver_attach+0xb6/0x180
<4>[ 10.649107] ? __pfx___driver_attach+0x10/0x10
<4>[ 10.649109] bus_for_each_dev+0x77/0xd0
<4>[ 10.649114] bus_add_driver+0x110/0x240
<4>[ 10.649117] driver_register+0x5b/0x110
<4>[ 10.649120] ? __pfx_igc_init_module+0x10/0x10 [igc]
<4>[ 10.649130] do_one_initcall+0x5c/0x2b0
<4>[ 10.649134] ? kmalloc_trace_noprof+0x22f/0x290
<4>[ 10.649141] ? do_init_module+0x1e/0x210
<4>[ 10.669989] do_init_module+0x5f/0x210
<4>[ 10.669993] load_module+0x1d44/0x1fc0
<4>[ 10.670001] ? init_module_from_file+0x86/0xd0
<4>[ 10.670004] init_module_from_file+0x86/0xd0
<4>[ 10.670009] idempotent_init_module+0x17c/0x230
<4>[ 10.670015] __x64_sys_finit_module+0x56/0xb0
<4>[ 10.670019] do_syscall_64+0x69/0x140
<4>[ 10.670023] entry_SYSCALL_64_after_hwframe+0x76/0x7e
<4>[ 10.670027] RIP: 0033:0x7f6d2704595d
<4>[ 10.670030] Code: 00 c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa 48
89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d
01 f0 ff ff 73 01 c3 48 8b 0d 03 35 0d 00 f7 d8 64 89 01 48
<4>[ 10.670032] RSP: 002b:7ffc72aad018 EFLAGS: 0246 ORIG_RAX:
0139
<4>[ 10.670036] RAX: ffda RBX: 55d3f0e69690 RCX:
7f6d2704595d
<4>[ 10.670038] RDX: RSI: 7f6d26f25ded RDI:
0010
<4>[ 10.670039] RBP: 0002 R08: R09:
0000
<4>[ 10.670041] R10: 0010 R11: 0246 R12:
7f6d26f25ded
<4>[ 10.670042] R13: R14: 55d3f0c64d20 R15:
55d3f0e69690
<4>[ 10.670046]
<6>[ 10.672046] pps pps0: new PPS source ptp0
Bug: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11189
BR,
Jani.
--
Jani Nikula, Intel
[PATCH 11/11] drm/i915: pass dev_priv explicitly to ADL_TVIDEO_DIP_AS_SDP_DATA
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the ADL_TVIDEO_DIP_AS_SDP_DATA register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 184fec37211b..3767be0bdba8 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -169,7 +169,7 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, case DP_SDP_VSC: return HSW_TVIDEO_DIP_VSC_DATA(dev_priv, cpu_transcoder, i); case DP_SDP_ADAPTIVE_SYNC: - return ADL_TVIDEO_DIP_AS_SDP_DATA(cpu_transcoder, i); + return ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, cpu_transcoder, i); case DP_SDP_PPS: return ICL_VIDEO_DIP_PPS_DATA(dev_priv, cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_AVI: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 57e805dcf4c6..be57812a6b07 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3486,7 +3486,7 @@ #define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) #define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) /*ADLP and later: */ -#define ADL_TVIDEO_DIP_AS_SDP_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans,\ +#define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans,\ _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4) #define _HSW_STEREO_3D_CTL_A 0x70020 -- 2.39.2
[PATCH 09/11] drm/i915: pass dev_priv explicitly to ICL_VIDEO_DIP_PPS_DATA
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the ICL_VIDEO_DIP_PPS_DATA register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index a26ce1e4befd..184fec37211b 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -171,7 +171,7 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, case DP_SDP_ADAPTIVE_SYNC: return ADL_TVIDEO_DIP_AS_SDP_DATA(cpu_transcoder, i); case DP_SDP_PPS: - return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); + return ICL_VIDEO_DIP_PPS_DATA(dev_priv, cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_AVI: return HSW_TVIDEO_DIP_AVI_DATA(dev_priv, cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_SPD: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4645476bb29e..5fe0a0c6514f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3483,7 +3483,7 @@ #define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i)_MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i)_MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) #define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i)_MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) -#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) +#define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) #define ICL_VIDEO_DIP_PPS_ECC(trans, i)_MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) /*ADLP and later: */ #define ADL_TVIDEO_DIP_AS_SDP_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans,\ -- 2.39.2
[PATCH 10/11] drm/i915: pass dev_priv explicitly to ICL_VIDEO_DIP_PPS_ECC
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the ICL_VIDEO_DIP_PPS_ECC register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5fe0a0c6514f..57e805dcf4c6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3484,7 +3484,7 @@ #define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i)_MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) #define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i)_MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) #define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) -#define ICL_VIDEO_DIP_PPS_ECC(trans, i)_MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) +#define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) /*ADLP and later: */ #define ADL_TVIDEO_DIP_AS_SDP_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans,\ _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4) -- 2.39.2
[PATCH 08/11] drm/i915: pass dev_priv explicitly to GLK_TVIDEO_DIP_DRM_DATA
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the GLK_TVIDEO_DIP_DRM_DATA register macro. Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index f7605ff547a3..a26ce1e4befd 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -179,7 +179,7 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, case HDMI_INFOFRAME_TYPE_VENDOR: return HSW_TVIDEO_DIP_VS_DATA(dev_priv, cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_DRM: - return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); + return GLK_TVIDEO_DIP_DRM_DATA(dev_priv, cpu_transcoder, i); default: MISSING_CASE(type); return INVALID_MMIO_REG; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1cb60a2ffa54..4645476bb29e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3482,7 +3482,7 @@ #define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i)_MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i)_MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i)_MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) -#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) +#define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i)_MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) #define ICL_VIDEO_DIP_PPS_ECC(trans, i)_MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) /*ADLP and later: */ -- 2.39.2
