Re: [Intel-gfx] [PATCH] drm/i915: Set guardband clipping workaround bit in the right register.
On Sun, 7 Oct 2012 08:51:07 -0700, Kenneth Graunke kenn...@whitecape.org wrote: A previous patch, namely: commit bf97b276ca04cee9ab65ffd378fa8e6aedd71ff6 Author: Daniel Vetter daniel.vet...@ffwll.ch Date: Wed Apr 11 20:42:41 2012 +0200 drm/i915: implement w/a for incorrect guarband clipping accidentally set bit 5 in 3D_CHICKEN, which has nothing to do with clipping. This patch changes it to be set in 3D_CHICKEN3, where it belongs. The game Dante demonstrates random clipping issues when guardband clipping is enabled and bit 5 of 3D_CHICKEN3 isn't set. So the workaround is actually necessary. Cc: Daniel Vetter daniel.vet...@ffwll.ch Cc: Oliver McFadden oliver.mcfad...@linux.intel.com Acked-by: Paul Menzel paulepan...@users.sourceforge.net Signed-off-by: Kenneth Graunke kenn...@whitecape.org Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Set guardband clipping workaround bit in the right register.
On Tue, Oct 09, 2012 at 10:43:10AM +0300, Mika Kuoppala wrote: On Sun, 7 Oct 2012 08:51:07 -0700, Kenneth Graunke kenn...@whitecape.org wrote: A previous patch, namely: commit bf97b276ca04cee9ab65ffd378fa8e6aedd71ff6 Author: Daniel Vetter daniel.vet...@ffwll.ch Date: Wed Apr 11 20:42:41 2012 +0200 drm/i915: implement w/a for incorrect guarband clipping accidentally set bit 5 in 3D_CHICKEN, which has nothing to do with clipping. This patch changes it to be set in 3D_CHICKEN3, where it belongs. The game Dante demonstrates random clipping issues when guardband clipping is enabled and bit 5 of 3D_CHICKEN3 isn't set. So the workaround is actually necessary. Cc: Daniel Vetter daniel.vet...@ffwll.ch Cc: Oliver McFadden oliver.mcfad...@linux.intel.com Acked-by: Paul Menzel paulepan...@users.sourceforge.net Signed-off-by: Kenneth Graunke kenn...@whitecape.org Reviewed-by: Mika Kuoppala mika.kuopp...@intel.com Applied to -fixes, thanks for the patchreview. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Set guardband clipping workaround bit in the right register.
A previous patch, namely: commit bf97b276ca04cee9ab65ffd378fa8e6aedd71ff6 Author: Daniel Vetter daniel.vet...@ffwll.ch Date: Wed Apr 11 20:42:41 2012 +0200 drm/i915: implement w/a for incorrect guarband clipping accidentally set bit 5 in 3D_CHICKEN, which has nothing to do with clipping. This patch changes it to be set in 3D_CHICKEN3, where it belongs. The game Dante demonstrates random clipping issues when guardband clipping is enabled and bit 5 of 3D_CHICKEN3 isn't set. So the workaround is actually necessary. Cc: Daniel Vetter daniel.vet...@ffwll.ch Cc: Oliver McFadden oliver.mcfad...@linux.intel.com Acked-by: Paul Menzel paulepan...@users.sourceforge.net Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a828e90..438bb7a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -521,7 +521,7 @@ */ # define _3D_CHICKEN2_WM_READ_PIPELINED(1 14) #define _3D_CHICKEN3 0x02090 -#define _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL (1 5) +#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 5) #define MI_MODE0x0209c # define VS_TIMER_DISPATCH (1 6) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 82ca172..7ac8a48 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3410,8 +3410,8 @@ static void gen6_init_clock_gating(struct drm_device *dev) GEN6_RCCUNIT_CLOCK_GATE_DISABLE); /* Bspec says we need to always set all mask bits. */ - I915_WRITE(_3D_CHICKEN, (0x 16) | - _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL); + I915_WRITE(_3D_CHICKEN3, (0x 16) | + _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL); /* * According to the spec the following bits should be -- 1.7.12.2 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH] drm/i915: Set guardband clipping workaround bit in the right register.
Dear Kenneth, thanks for the patch. Am Freitag, den 05.10.2012, 17:46 -0700 schrieb Kenneth Graunke: Commit bf97b276ca04 Could you please paste the date, author and commit summary of this commit too? At least I cannot memorize hashes that well and having the summary pasted would give me enough information most of the time about the other commit. ;-) accidentally set bit 5 in 3D_CHICKEN, which has nothing to do with clipping. This patch changes it to be set in 3D_CHICKEN3, where it belongs. The game Dante demonstrates random clipping issues when guardband clipping is enabled and bit 5 of 3D_CHICKEN3 isn't set. So the workaround actually is necessary. Cc: Daniel Vetter daniel.vet...@ffwll.ch Cc: Oliver McFadden oliver.mcfad...@linux.intel.com Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) […] Acked-by: Paul Menzel paulepan...@users.sourceforge.net Thanks, Paul signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH] drm/i915: Set guardband clipping workaround bit in the right register.
Commit bf97b276ca04 accidentally set bit 5 in 3D_CHICKEN, which has nothing to do with clipping. This patch changes it to be set in 3D_CHICKEN3, where it belongs. The game Dante demonstrates random clipping issues when guardband clipping is enabled and bit 5 of 3D_CHICKEN3 isn't set. So the workaround actually is necessary. Cc: Daniel Vetter daniel.vet...@ffwll.ch Cc: Oliver McFadden oliver.mcfad...@linux.intel.com Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a828e90..438bb7a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -521,7 +521,7 @@ */ # define _3D_CHICKEN2_WM_READ_PIPELINED(1 14) #define _3D_CHICKEN3 0x02090 -#define _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL (1 5) +#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 5) #define MI_MODE0x0209c # define VS_TIMER_DISPATCH (1 6) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 82ca172..7ac8a48 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3410,8 +3410,8 @@ static void gen6_init_clock_gating(struct drm_device *dev) GEN6_RCCUNIT_CLOCK_GATE_DISABLE); /* Bspec says we need to always set all mask bits. */ - I915_WRITE(_3D_CHICKEN, (0x 16) | - _3D_CHICKEN_SF_DISABLE_FASTCLIP_CULL); + I915_WRITE(_3D_CHICKEN3, (0x 16) | + _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL); /* * According to the spec the following bits should be -- 1.7.11.4 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
