Re: [Intel-gfx] [PATCH 1/3] drm/i915: Introduce i9xx_set_pipeconf()
On Tue, 02 Apr 2013, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Extract the PIPECONF setup into i9xx_set_pipeconf(). This makes the
=Gen4/VLV code follow the same pattern as the Gen5+ codepaths.
Reviewed-by: Jani Nikula jani.nik...@intel.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 123
+++
1 file changed, 68 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 298bc0c..dfaea15 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4514,6 +4514,71 @@ static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc,
((mode-hdisplay - 1) 16) | (mode-vdisplay - 1));
}
+static void i9xx_set_pipeconf(struct drm_crtc *crtc,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode,
+ bool is_dp)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc-pipe;
+ u32 pipeconf;
+
+ /* setup pipeconf */
+ pipeconf = I915_READ(PIPECONF(pipe));
+
+ if (pipe == 0 INTEL_INFO(dev)-gen 4) {
+ /* Enable pixel doubling when the dot clock is 90% of the
(display)
+ * core speed.
+ *
+ * XXX: No double-wide on 915GM pipe B. Is that the only reason
for the
+ * pipe == 0 check?
+ */
+ if (mode-clock
+ dev_priv-display.get_display_clock_speed(dev) * 9 / 10)
+ pipeconf |= PIPECONF_DOUBLE_WIDE;
+ else
+ pipeconf = ~PIPECONF_DOUBLE_WIDE;
+ }
+
+ /* default to 8bpc */
+ pipeconf = ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
+ if (is_dp intel_crtc-config.dither) {
+ pipeconf |= PIPECONF_6BPC |
+ PIPECONF_DITHER_EN |
+ PIPECONF_DITHER_TYPE_SP;
+ }
+
+ if (IS_VALLEYVIEW(dev)
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)
+ intel_crtc-config.dither) {
+ pipeconf |= PIPECONF_6BPC |
+ PIPECONF_ENABLE |
+ I965_PIPECONF_ACTIVE;
+ }
+
+ if (HAS_PIPE_CXSR(dev)) {
+ if (intel_crtc-lowfreq_avail) {
+ DRM_DEBUG_KMS(enabling CxSR downclocking\n);
+ pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
+ } else {
+ DRM_DEBUG_KMS(disabling CxSR downclocking\n);
+ pipeconf = ~PIPECONF_CXSR_DOWNCLOCK;
+ }
+ }
+
+ pipeconf = ~PIPECONF_INTERLACE_MASK;
+ if (!IS_GEN2(dev)
+ adjusted_mode-flags DRM_MODE_FLAG_INTERLACE)
+ pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
+ else
+ pipeconf |= PIPECONF_PROGRESSIVE;
+
+ I915_WRITE(PIPECONF(pipe), pipeconf);
+ POSTING_READ(PIPECONF(pipe));
+}
+
static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
int x, int y,
struct drm_framebuffer *fb)
@@ -4528,7 +4593,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
int plane = intel_crtc-plane;
int refclk, num_connectors = 0;
intel_clock_t clock, reduced_clock;
- u32 dspcntr, pipeconf;
+ u32 dspcntr;
bool ok, has_reduced_clock = false, is_sdvo = false;
bool is_lvds = false, is_tv = false, is_dp = false;
struct intel_encoder *encoder;
@@ -4605,9 +4670,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
has_reduced_clock ? reduced_clock : NULL,
num_connectors);
- /* setup pipeconf */
- pipeconf = I915_READ(PIPECONF(pipe));
-
/* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -4618,58 +4680,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
dspcntr |= DISPPLANE_SEL_PIPE_B;
}
- if (pipe == 0 INTEL_INFO(dev)-gen 4) {
- /* Enable pixel doubling when the dot clock is 90% of the
(display)
- * core speed.
- *
- * XXX: No double-wide on 915GM pipe B. Is that the only reason
for the
- * pipe == 0 check?
- */
- if (mode-clock
- dev_priv-display.get_display_clock_speed(dev) * 9 / 10)
- pipeconf |= PIPECONF_DOUBLE_WIDE;
- else
- pipeconf = ~PIPECONF_DOUBLE_WIDE;
- }
-
- /* default to 8bpc */
- pipeconf = ~(PIPECONF_BPC_MASK |
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Introduce i9xx_set_pipeconf()
On Wed, Apr 03, 2013 at 01:08:16PM +0300, Jani Nikula wrote:
On Tue, 02 Apr 2013, ville.syrj...@linux.intel.com wrote:
From: Ville Syrjälä ville.syrj...@linux.intel.com
Extract the PIPECONF setup into i9xx_set_pipeconf(). This makes the
=Gen4/VLV code follow the same pattern as the Gen5+ codepaths.
Reviewed-by: Jani Nikula jani.nik...@intel.com
Queued for -next with a pretty massive bikeshed (extended conflict
resolutions ftw), thanks for the patch.
-Daniel
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 123
+++
1 file changed, 68 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 298bc0c..dfaea15 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4514,6 +4514,71 @@ static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc,
((mode-hdisplay - 1) 16) | (mode-vdisplay - 1));
}
+static void i9xx_set_pipeconf(struct drm_crtc *crtc,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode,
+ bool is_dp)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc-pipe;
+ u32 pipeconf;
+
+ /* setup pipeconf */
+ pipeconf = I915_READ(PIPECONF(pipe));
+
+ if (pipe == 0 INTEL_INFO(dev)-gen 4) {
+ /* Enable pixel doubling when the dot clock is 90% of the
(display)
+* core speed.
+*
+* XXX: No double-wide on 915GM pipe B. Is that the only reason
for the
+* pipe == 0 check?
+*/
+ if (mode-clock
+ dev_priv-display.get_display_clock_speed(dev) * 9 / 10)
+ pipeconf |= PIPECONF_DOUBLE_WIDE;
+ else
+ pipeconf = ~PIPECONF_DOUBLE_WIDE;
+ }
+
+ /* default to 8bpc */
+ pipeconf = ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
+ if (is_dp intel_crtc-config.dither) {
+ pipeconf |= PIPECONF_6BPC |
+ PIPECONF_DITHER_EN |
+ PIPECONF_DITHER_TYPE_SP;
+ }
+
+ if (IS_VALLEYVIEW(dev)
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)
+ intel_crtc-config.dither) {
+ pipeconf |= PIPECONF_6BPC |
+ PIPECONF_ENABLE |
+ I965_PIPECONF_ACTIVE;
+ }
+
+ if (HAS_PIPE_CXSR(dev)) {
+ if (intel_crtc-lowfreq_avail) {
+ DRM_DEBUG_KMS(enabling CxSR downclocking\n);
+ pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
+ } else {
+ DRM_DEBUG_KMS(disabling CxSR downclocking\n);
+ pipeconf = ~PIPECONF_CXSR_DOWNCLOCK;
+ }
+ }
+
+ pipeconf = ~PIPECONF_INTERLACE_MASK;
+ if (!IS_GEN2(dev)
+ adjusted_mode-flags DRM_MODE_FLAG_INTERLACE)
+ pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
+ else
+ pipeconf |= PIPECONF_PROGRESSIVE;
+
+ I915_WRITE(PIPECONF(pipe), pipeconf);
+ POSTING_READ(PIPECONF(pipe));
+}
+
static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
int x, int y,
struct drm_framebuffer *fb)
@@ -4528,7 +4593,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
int plane = intel_crtc-plane;
int refclk, num_connectors = 0;
intel_clock_t clock, reduced_clock;
- u32 dspcntr, pipeconf;
+ u32 dspcntr;
bool ok, has_reduced_clock = false, is_sdvo = false;
bool is_lvds = false, is_tv = false, is_dp = false;
struct intel_encoder *encoder;
@@ -4605,9 +4670,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
has_reduced_clock ? reduced_clock : NULL,
num_connectors);
- /* setup pipeconf */
- pipeconf = I915_READ(PIPECONF(pipe));
-
/* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -4618,58 +4680,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
dspcntr |= DISPPLANE_SEL_PIPE_B;
}
- if (pipe == 0 INTEL_INFO(dev)-gen 4) {
- /* Enable pixel doubling when the dot clock is 90% of the
(display)
-* core speed.
-*
-* XXX: No double-wide on 915GM pipe B. Is that the only reason
for the
-* pipe == 0 check?
-*/
- if (mode-clock
- dev_priv-display.get_display_clock_speed(dev) * 9 / 10)
- pipeconf |= PIPECONF_DOUBLE_WIDE;
- else
-
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Introduce i9xx_set_pipeconf()
On Wed, Apr 03, 2013 at 07:06:01PM +0200, Daniel Vetter wrote: On Wed, Apr 03, 2013 at 01:08:16PM +0300, Jani Nikula wrote: On Tue, 02 Apr 2013, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä ville.syrj...@linux.intel.com Extract the PIPECONF setup into i9xx_set_pipeconf(). This makes the =Gen4/VLV code follow the same pattern as the Gen5+ codepaths. Reviewed-by: Jani Nikula jani.nik...@intel.com Queued for -next with a pretty massive bikeshed (extended conflict resolutions ftw), thanks for the patch. I've changed my mind after trying to rebase my current pipe_config stuff on top of latest dinq - I've noticed that I've written this exact patch, but in slightly different colors: https://patchwork.kernel.org/patch/2173951/ The slightly different colors resulted in rebase hell in my pipe_config branch, so I've ditched your patch here and exchanged it with mine - rebasing your two patches on top was much easier ;-) Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/3] drm/i915: Introduce i9xx_set_pipeconf()
From: Ville Syrjälä ville.syrj...@linux.intel.com
Extract the PIPECONF setup into i9xx_set_pipeconf(). This makes the
=Gen4/VLV code follow the same pattern as the Gen5+ codepaths.
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
drivers/gpu/drm/i915/intel_display.c | 123 +++
1 file changed, 68 insertions(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 298bc0c..dfaea15 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4514,6 +4514,71 @@ static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc,
((mode-hdisplay - 1) 16) | (mode-vdisplay - 1));
}
+static void i9xx_set_pipeconf(struct drm_crtc *crtc,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adjusted_mode,
+ bool is_dp)
+{
+ struct drm_device *dev = crtc-dev;
+ struct drm_i915_private *dev_priv = dev-dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc-pipe;
+ u32 pipeconf;
+
+ /* setup pipeconf */
+ pipeconf = I915_READ(PIPECONF(pipe));
+
+ if (pipe == 0 INTEL_INFO(dev)-gen 4) {
+ /* Enable pixel doubling when the dot clock is 90% of the
(display)
+* core speed.
+*
+* XXX: No double-wide on 915GM pipe B. Is that the only reason
for the
+* pipe == 0 check?
+*/
+ if (mode-clock
+ dev_priv-display.get_display_clock_speed(dev) * 9 / 10)
+ pipeconf |= PIPECONF_DOUBLE_WIDE;
+ else
+ pipeconf = ~PIPECONF_DOUBLE_WIDE;
+ }
+
+ /* default to 8bpc */
+ pipeconf = ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
+ if (is_dp intel_crtc-config.dither) {
+ pipeconf |= PIPECONF_6BPC |
+ PIPECONF_DITHER_EN |
+ PIPECONF_DITHER_TYPE_SP;
+ }
+
+ if (IS_VALLEYVIEW(dev)
+ intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)
+ intel_crtc-config.dither) {
+ pipeconf |= PIPECONF_6BPC |
+ PIPECONF_ENABLE |
+ I965_PIPECONF_ACTIVE;
+ }
+
+ if (HAS_PIPE_CXSR(dev)) {
+ if (intel_crtc-lowfreq_avail) {
+ DRM_DEBUG_KMS(enabling CxSR downclocking\n);
+ pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
+ } else {
+ DRM_DEBUG_KMS(disabling CxSR downclocking\n);
+ pipeconf = ~PIPECONF_CXSR_DOWNCLOCK;
+ }
+ }
+
+ pipeconf = ~PIPECONF_INTERLACE_MASK;
+ if (!IS_GEN2(dev)
+ adjusted_mode-flags DRM_MODE_FLAG_INTERLACE)
+ pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
+ else
+ pipeconf |= PIPECONF_PROGRESSIVE;
+
+ I915_WRITE(PIPECONF(pipe), pipeconf);
+ POSTING_READ(PIPECONF(pipe));
+}
+
static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
int x, int y,
struct drm_framebuffer *fb)
@@ -4528,7 +4593,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
int plane = intel_crtc-plane;
int refclk, num_connectors = 0;
intel_clock_t clock, reduced_clock;
- u32 dspcntr, pipeconf;
+ u32 dspcntr;
bool ok, has_reduced_clock = false, is_sdvo = false;
bool is_lvds = false, is_tv = false, is_dp = false;
struct intel_encoder *encoder;
@@ -4605,9 +4670,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
has_reduced_clock ? reduced_clock : NULL,
num_connectors);
- /* setup pipeconf */
- pipeconf = I915_READ(PIPECONF(pipe));
-
/* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -4618,58 +4680,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
dspcntr |= DISPPLANE_SEL_PIPE_B;
}
- if (pipe == 0 INTEL_INFO(dev)-gen 4) {
- /* Enable pixel doubling when the dot clock is 90% of the
(display)
-* core speed.
-*
-* XXX: No double-wide on 915GM pipe B. Is that the only reason
for the
-* pipe == 0 check?
-*/
- if (mode-clock
- dev_priv-display.get_display_clock_speed(dev) * 9 / 10)
- pipeconf |= PIPECONF_DOUBLE_WIDE;
- else
- pipeconf = ~PIPECONF_DOUBLE_WIDE;
- }
-
- /* default to 8bpc */
- pipeconf = ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
- if (is_dp) {
- if
