Re: [Intel-gfx] [PATCH 1/7] drm/i915: implement ColorBlt w/a
On Tue, Apr 10, 2012 at 03:24:13PM -0700, Ben Widawsky wrote: On Sat, Mar 31, 2012 at 11:21:57AM +0200, Daniel Vetter wrote: According to an internal workaround master list, we need to set bit 5 of register 9400 to avoid issues with color blits. Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch I'm having a lot of trouble actually tracking this one down in something other than the magical spreadsheet. So I'll for now, this is only Acked-by: Ben Widawsky b...@bwidawsk.net I've picked this up for -fixes, thanks for wrestling through hsd and that ugly xls. -Daniel -- Daniel Vetter Mail: dan...@ffwll.ch Mobile: +41 (0)79 365 57 48 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/7] drm/i915: implement ColorBlt w/a
-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 Hello everyone, it looks like this does indeed fix the fbc problem. I applied the patch, and did some testing. I am using a Dell Latitude e6420, this is my setup: brotscheibe brot # cat /sys/kernel/debug/dri/0/i915_fbc_status FBC enabled brotscheibe brot # uname -a Linux brotscheibe 3.4.0-rc2+ #52 SMP PREEMPT Mon Apr 9 21:51:57 CEST 2012 x86_64 Intel(R) Core(TM) i5-2540M CPU @ 2.60GHz GenuineIntel GNU/Linux After nearly an hour of testing, i got no hangs. Even when using rxvt and while (true) do dmesg; done. I will do more testing tomorrow, but i dont think anything will fail. You can add my tested-by: Michael brot Groh michael.g...@minad.de Thanks for your work and have a nice day, Michael -BEGIN PGP SIGNATURE- Version: GnuPG v2.0.19 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iF4EAREIAAYFAk+D+I8ACgkQ+SqCF1IBR0SzSgD/bkf6W7axjuaWe855f/5oqFSC Opt4J1pz6HP/qNYFD/AA/0Hw4XvvY085OkEQ++Hd+Q1dvvWXLeukuSf6dDfgokFq =Dt1V -END PGP SIGNATURE- ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/7] drm/i915: implement ColorBlt w/a
Am Samstag, den 31.03.2012, 11:21 +0200 schrieb Daniel Vetter: According to an internal workaround master list, we need to set bit 5 of register 9400 to avoid issues with color blits. Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/i915/i915_reg.h |3 +++ drivers/gpu/drm/i915/intel_display.c |4 2 files changed, 7 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3886cf0..233dbd5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3727,6 +3727,9 @@ #define GT_FIFO_FREE_ENTRIES0x120008 #defineGT_FIFO_NUM_RESERVED_ENTRIES 20 +#define GEN6_UCGCTL1 0x9400 +# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 5) + #define GEN6_UCGCTL2 0x9404 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 13) # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE(1 12) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d514719..aa0c6df 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8510,6 +8510,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) I915_WRITE(WM2_LP_ILK, 0); I915_WRITE(WM1_LP_ILK, 0); + I915_WRITE(GEN6_UCGCTL1, +I915_READ(GEN6_UCGCTL1) | +GEN6_BLBUNIT_CLOCK_GATE_DISABLE); + Should a comment be added to the header file or here that this is from an internal workaround list? (Same for patch 7/7 I think.) /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock * gating disable must be set. Failure to set it results in * flickering pixels due to Z write ordering failures after Thanks, Paul signature.asc Description: This is a digitally signed message part ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/7] drm/i915: implement ColorBlt w/a
On Sat, Mar 31, 2012 at 11:21:57AM +0200, Daniel Vetter wrote: According to an internal workaround master list, we need to set bit 5 of register 9400 to avoid issues with color blits. Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch I'm having a lot of trouble actually tracking this one down in something other than the magical spreadsheet. So I'll for now, this is only Acked-by: Ben Widawsky b...@bwidawsk.net ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
[Intel-gfx] [PATCH 1/7] drm/i915: implement ColorBlt w/a
According to an internal workaround master list, we need to set bit 5 of register 9400 to avoid issues with color blits. Signed-Off-by: Daniel Vetter daniel.vet...@ffwll.ch --- drivers/gpu/drm/i915/i915_reg.h |3 +++ drivers/gpu/drm/i915/intel_display.c |4 2 files changed, 7 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3886cf0..233dbd5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3727,6 +3727,9 @@ #define GT_FIFO_FREE_ENTRIES 0x120008 #defineGT_FIFO_NUM_RESERVED_ENTRIES20 +#define GEN6_UCGCTL1 0x9400 +# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 5) + #define GEN6_UCGCTL2 0x9404 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 13) # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 12) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index d514719..aa0c6df 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8510,6 +8510,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) I915_WRITE(WM2_LP_ILK, 0); I915_WRITE(WM1_LP_ILK, 0); + I915_WRITE(GEN6_UCGCTL1, + I915_READ(GEN6_UCGCTL1) | + GEN6_BLBUNIT_CLOCK_GATE_DISABLE); + /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock * gating disable must be set. Failure to set it results in * flickering pixels due to Z write ordering failures after -- 1.7.7.6 ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Re: [Intel-gfx] [PATCH 1/7] drm/i915: implement ColorBlt w/a
On Sat, 31 Mar 2012 11:21:57 +0200, Daniel Vetter daniel.vet...@ffwll.ch wrote: According to an internal workaround master list, we need to set bit 5 of register 9400 to avoid issues with color blits. This sounds like it could be the root cause behind the FBC + BLT hangs. But not the XY_COPY hangs. -Chris -- Chris Wilson, Intel Open Source Technology Centre ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
