[Intel-gfx] [PATCH v2 4/9] drm/i915: Split bxt_ddi_pll_select()

[Manasi Navare]

From: Durgadoss R 

Split out of bxt_ddi_pll_select() the logic that calculates the pll
dividers and dpll_hw_state into a new function that doesn't depend on
crtc state. This will be used for enabling the port pll when doing
upfront link training.

v2:
* Refactored code so that bxt_clk_div need not be exported (Durga)
v1:
* Rebased on top of intel_dpll_mgr.c (Durga)
* Initial version from Ander on top of intel_ddi.c

Reviewed-by:  Manasi Navare 
Signed-off-by: Ander Conselvan de Oliveira 

Signed-off-by: Durgadoss R 
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 165 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.h |   3 +
 2 files changed, 104 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 0e1af4d..61d2311 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1460,6 +1460,8 @@ struct bxt_clk_div {
uint32_t m2_frac;
bool m2_frac_en;
uint32_t n;
+
+   int vco;
 };
 
 /* pre-calculated values for DP linkrates */
@@ -1473,57 +1475,60 @@ static const struct bxt_clk_div bxt_dp_clk_val[] = {
{432000, 3, 1, 32, 1677722, 1, 1}
 };
 
-static struct intel_shared_dpll *
-bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
-struct intel_encoder *encoder)
+static bool
+bxt_ddi_hdmi_pll_dividers(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state, int clock,
+ struct bxt_clk_div *clk_div)
 {
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   struct intel_shared_dpll *pll;
-   enum intel_dpll_id i;
-   struct intel_digital_port *intel_dig_port;
-   struct bxt_clk_div clk_div = {0};
-   int vco = 0;
-   uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
-   uint32_t lanestagger;
-   int clock = crtc_state->port_clock;
+   struct dpll best_clock;
 
-   if (encoder->type == INTEL_OUTPUT_HDMI) {
-   struct dpll best_clock;
+   /* Calculate HDMI div */
+   /*
+* FIXME: tie the following calculation into
+* i9xx_crtc_compute_clock
+*/
+   if (!bxt_find_best_dpll(crtc_state, clock, _clock)) {
+   DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
+clock, pipe_name(intel_crtc->pipe));
+   return false;
+   }
 
-   /* Calculate HDMI div */
-   /*
-* FIXME: tie the following calculation into
-* i9xx_crtc_compute_clock
-*/
-   if (!bxt_find_best_dpll(crtc_state, clock, _clock)) {
-   DRM_DEBUG_DRIVER("no PLL dividers found for clock %d 
pipe %c\n",
-clock, pipe_name(crtc->pipe));
-   return NULL;
-   }
+   clk_div->p1 = best_clock.p1;
+   clk_div->p2 = best_clock.p2;
+   WARN_ON(best_clock.m1 != 2);
+   clk_div->n = best_clock.n;
+   clk_div->m2_int = best_clock.m2 >> 22;
+   clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
+   clk_div->m2_frac_en = clk_div->m2_frac != 0;
 
-   clk_div.p1 = best_clock.p1;
-   clk_div.p2 = best_clock.p2;
-   WARN_ON(best_clock.m1 != 2);
-   clk_div.n = best_clock.n;
-   clk_div.m2_int = best_clock.m2 >> 22;
-   clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
-   clk_div.m2_frac_en = clk_div.m2_frac != 0;
+   clk_div->vco = best_clock.vco;
 
-   vco = best_clock.vco;
-   } else if (encoder->type == INTEL_OUTPUT_DP ||
-  encoder->type == INTEL_OUTPUT_EDP) {
-   int i;
+   return true;
+}
 
-   clk_div = bxt_dp_clk_val[0];
-   for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
-   if (bxt_dp_clk_val[i].clock == clock) {
-   clk_div = bxt_dp_clk_val[i];
-   break;
-   }
+static void bxt_ddi_dp_pll_dividers(int clock, struct bxt_clk_div *clk_div)
+{
+   int i;
+
+   *clk_div = bxt_dp_clk_val[0];
+   for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
+   if (bxt_dp_clk_val[i].clock == clock) {
+   *clk_div = bxt_dp_clk_val[i];
+   break;
}
-   vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
}
 
+   clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
+}
+
+static bool bxt_ddi_set_dpll_hw_state(int clock,
+ struct bxt_clk_div *clk_div,
+ struct intel_dpll_hw_state *dpll_hw_state)
+{
+   int vco = clk_div->vco;
+   

[Intel-gfx] [PATCH v2 4/9] drm/i915: Split bxt_ddi_pll_select()

[Manasi Navare]

From: Durgadoss R 

Split out of bxt_ddi_pll_select() the logic that calculates the pll
dividers and dpll_hw_state into a new function that doesn't depend on
crtc state. This will be used for enabling the port pll when doing
upfront link training.

v2:
* Refactored code so that bxt_clk_div need not be exported (Durga)
v1:
* Rebased on top of intel_dpll_mgr.c (Durga)
* Initial version from Ander on top of intel_ddi.c

Signed-off-by: Ander Conselvan de Oliveira 

Signed-off-by: Durgadoss R 
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 165 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.h |   3 +
 2 files changed, 104 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 0e1af4d..61d2311 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1460,6 +1460,8 @@ struct bxt_clk_div {
uint32_t m2_frac;
bool m2_frac_en;
uint32_t n;
+
+   int vco;
 };
 
 /* pre-calculated values for DP linkrates */
@@ -1473,57 +1475,60 @@ static const struct bxt_clk_div bxt_dp_clk_val[] = {
{432000, 3, 1, 32, 1677722, 1, 1}
 };
 
-static struct intel_shared_dpll *
-bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
-struct intel_encoder *encoder)
+static bool
+bxt_ddi_hdmi_pll_dividers(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state, int clock,
+ struct bxt_clk_div *clk_div)
 {
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   struct intel_shared_dpll *pll;
-   enum intel_dpll_id i;
-   struct intel_digital_port *intel_dig_port;
-   struct bxt_clk_div clk_div = {0};
-   int vco = 0;
-   uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
-   uint32_t lanestagger;
-   int clock = crtc_state->port_clock;
+   struct dpll best_clock;
 
-   if (encoder->type == INTEL_OUTPUT_HDMI) {
-   struct dpll best_clock;
+   /* Calculate HDMI div */
+   /*
+* FIXME: tie the following calculation into
+* i9xx_crtc_compute_clock
+*/
+   if (!bxt_find_best_dpll(crtc_state, clock, _clock)) {
+   DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
+clock, pipe_name(intel_crtc->pipe));
+   return false;
+   }
 
-   /* Calculate HDMI div */
-   /*
-* FIXME: tie the following calculation into
-* i9xx_crtc_compute_clock
-*/
-   if (!bxt_find_best_dpll(crtc_state, clock, _clock)) {
-   DRM_DEBUG_DRIVER("no PLL dividers found for clock %d 
pipe %c\n",
-clock, pipe_name(crtc->pipe));
-   return NULL;
-   }
+   clk_div->p1 = best_clock.p1;
+   clk_div->p2 = best_clock.p2;
+   WARN_ON(best_clock.m1 != 2);
+   clk_div->n = best_clock.n;
+   clk_div->m2_int = best_clock.m2 >> 22;
+   clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
+   clk_div->m2_frac_en = clk_div->m2_frac != 0;
 
-   clk_div.p1 = best_clock.p1;
-   clk_div.p2 = best_clock.p2;
-   WARN_ON(best_clock.m1 != 2);
-   clk_div.n = best_clock.n;
-   clk_div.m2_int = best_clock.m2 >> 22;
-   clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
-   clk_div.m2_frac_en = clk_div.m2_frac != 0;
+   clk_div->vco = best_clock.vco;
 
-   vco = best_clock.vco;
-   } else if (encoder->type == INTEL_OUTPUT_DP ||
-  encoder->type == INTEL_OUTPUT_EDP) {
-   int i;
+   return true;
+}
 
-   clk_div = bxt_dp_clk_val[0];
-   for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
-   if (bxt_dp_clk_val[i].clock == clock) {
-   clk_div = bxt_dp_clk_val[i];
-   break;
-   }
+static void bxt_ddi_dp_pll_dividers(int clock, struct bxt_clk_div *clk_div)
+{
+   int i;
+
+   *clk_div = bxt_dp_clk_val[0];
+   for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
+   if (bxt_dp_clk_val[i].clock == clock) {
+   *clk_div = bxt_dp_clk_val[i];
+   break;
}
-   vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
}
 
+   clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
+}
+
+static bool bxt_ddi_set_dpll_hw_state(int clock,
+ struct bxt_clk_div *clk_div,
+ struct intel_dpll_hw_state *dpll_hw_state)
+{
+   int vco = clk_div->vco;
+   uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
+  

[Intel-gfx] [PATCH v2 4/9] drm/i915: Split bxt_ddi_pll_select()

[Manasi Navare]

From: Durgadoss R 

Split out of bxt_ddi_pll_select() the logic that calculates the pll
dividers and dpll_hw_state into a new function that doesn't depend on
crtc state. This will be used for enabling the port pll when doing
upfront link training.

v2:
* Refactored code so that bxt_clk_div need not be exported (Durga)
v1:
* Rebased on top of intel_dpll_mgr.c (Durga)
* Initial version from Ander on top of intel_ddi.c

Signed-off-by: Ander Conselvan de Oliveira 

Signed-off-by: Durgadoss R 
---
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 165 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.h |   3 +
 2 files changed, 104 insertions(+), 64 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c 
b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 0e1af4d..61d2311 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1460,6 +1460,8 @@ struct bxt_clk_div {
uint32_t m2_frac;
bool m2_frac_en;
uint32_t n;
+
+   int vco;
 };
 
 /* pre-calculated values for DP linkrates */
@@ -1473,57 +1475,60 @@ static const struct bxt_clk_div bxt_dp_clk_val[] = {
{432000, 3, 1, 32, 1677722, 1, 1}
 };
 
-static struct intel_shared_dpll *
-bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
-struct intel_encoder *encoder)
+static bool
+bxt_ddi_hdmi_pll_dividers(struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state, int clock,
+ struct bxt_clk_div *clk_div)
 {
-   struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-   struct intel_shared_dpll *pll;
-   enum intel_dpll_id i;
-   struct intel_digital_port *intel_dig_port;
-   struct bxt_clk_div clk_div = {0};
-   int vco = 0;
-   uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
-   uint32_t lanestagger;
-   int clock = crtc_state->port_clock;
+   struct dpll best_clock;
 
-   if (encoder->type == INTEL_OUTPUT_HDMI) {
-   struct dpll best_clock;
+   /* Calculate HDMI div */
+   /*
+* FIXME: tie the following calculation into
+* i9xx_crtc_compute_clock
+*/
+   if (!bxt_find_best_dpll(crtc_state, clock, _clock)) {
+   DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
+clock, pipe_name(intel_crtc->pipe));
+   return false;
+   }
 
-   /* Calculate HDMI div */
-   /*
-* FIXME: tie the following calculation into
-* i9xx_crtc_compute_clock
-*/
-   if (!bxt_find_best_dpll(crtc_state, clock, _clock)) {
-   DRM_DEBUG_DRIVER("no PLL dividers found for clock %d 
pipe %c\n",
-clock, pipe_name(crtc->pipe));
-   return NULL;
-   }
+   clk_div->p1 = best_clock.p1;
+   clk_div->p2 = best_clock.p2;
+   WARN_ON(best_clock.m1 != 2);
+   clk_div->n = best_clock.n;
+   clk_div->m2_int = best_clock.m2 >> 22;
+   clk_div->m2_frac = best_clock.m2 & ((1 << 22) - 1);
+   clk_div->m2_frac_en = clk_div->m2_frac != 0;
 
-   clk_div.p1 = best_clock.p1;
-   clk_div.p2 = best_clock.p2;
-   WARN_ON(best_clock.m1 != 2);
-   clk_div.n = best_clock.n;
-   clk_div.m2_int = best_clock.m2 >> 22;
-   clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
-   clk_div.m2_frac_en = clk_div.m2_frac != 0;
+   clk_div->vco = best_clock.vco;
 
-   vco = best_clock.vco;
-   } else if (encoder->type == INTEL_OUTPUT_DP ||
-  encoder->type == INTEL_OUTPUT_EDP) {
-   int i;
+   return true;
+}
 
-   clk_div = bxt_dp_clk_val[0];
-   for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
-   if (bxt_dp_clk_val[i].clock == clock) {
-   clk_div = bxt_dp_clk_val[i];
-   break;
-   }
+static void bxt_ddi_dp_pll_dividers(int clock, struct bxt_clk_div *clk_div)
+{
+   int i;
+
+   *clk_div = bxt_dp_clk_val[0];
+   for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
+   if (bxt_dp_clk_val[i].clock == clock) {
+   *clk_div = bxt_dp_clk_val[i];
+   break;
}
-   vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
}
 
+   clk_div->vco = clock * 10 / 2 * clk_div->p1 * clk_div->p2;
+}
+
+static bool bxt_ddi_set_dpll_hw_state(int clock,
+ struct bxt_clk_div *clk_div,
+ struct intel_dpll_hw_state *dpll_hw_state)
+{
+   int vco = clk_div->vco;
+   uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
+