Re: [PATCH V4 1/2] crypto: Add Imagination Technologies hw hash accelerator

2015-03-12 Thread Andrew Bresticker 
Hi James,

On Wed, Mar 11, 2015 at 7:06 PM, James Hartley james.hart...@imgtec.com wrote:
 This adds support for the Imagination Technologies hash accelerator which
 provides hardware acceleration for SHA1 SHA224 SHA256 and MD5 hashes.

 Signed-off-by: James Hartley james.hart...@imgtec.com

One comment below, otherwise this looks fine to me.

 --- /dev/null
 +++ b/drivers/crypto/img-hash.c

 +static int img_hash_hw_init(struct img_hash_dev *hdev)
 +{
 +   unsigned long long nbits;
 +   u32 u, l;
 +   int ret;
 +
 +   ret = clk_prepare_enable(hdev-hash_clk);
 +   if (ret)
 +   return ret;
 +
 +   ret = clk_prepare_enable(hdev-sys_clk);
 +   if (ret) {
 +   clk_disable_unprepare(hdev-hash_clk);
 +   return ret;
 +   }

I think you'll still end up with inflated prepare/enable counts for
these clocks since this function may get called multiple times and the
only clk_disable_unprepare() calls are in the remove() path.  Perhaps
it's best to just enable the clocks in probe() until runtime PM
support is added?

Thanks,
Andrew
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RE: [PATCH V4 1/2] crypto: Add Imagination Technologies hw hash accelerator

2015-03-12 Thread James Hartley 
Hi Andrew, 

 -Original Message-
 From: abres...@google.com [mailto:abres...@google.com] On Behalf Of
 Andrew Bresticker
 Sent: 12 March 2015 18:57
 To: James Hartley
 Cc: Herbert Xu; smuel...@chronox.de; devicet...@vger.kernel.org; Ezequiel
 Garcia; linux-crypto@vger.kernel.org
 Subject: Re: [PATCH V4 1/2] crypto: Add Imagination Technologies hw hash
 accelerator
 
 Hi James,
 
 On Wed, Mar 11, 2015 at 7:06 PM, James Hartley
 james.hart...@imgtec.com wrote:
  This adds support for the Imagination Technologies hash accelerator
  which provides hardware acceleration for SHA1 SHA224 SHA256 and MD5
 hashes.
 
  Signed-off-by: James Hartley james.hart...@imgtec.com
 
 One comment below, otherwise this looks fine to me.
 
  --- /dev/null
  +++ b/drivers/crypto/img-hash.c
 
  +static int img_hash_hw_init(struct img_hash_dev *hdev) {
  +   unsigned long long nbits;
  +   u32 u, l;
  +   int ret;
  +
  +   ret = clk_prepare_enable(hdev-hash_clk);
  +   if (ret)
  +   return ret;
  +
  +   ret = clk_prepare_enable(hdev-sys_clk);
  +   if (ret) {
  +   clk_disable_unprepare(hdev-hash_clk);
  +   return ret;
  +   }
 
 I think you'll still end up with inflated prepare/enable counts for these 
 clocks
 since this function may get called multiple times and the only
 clk_disable_unprepare() calls are in the remove() path.  Perhaps it's best to
 just enable the clocks in probe() until runtime PM support is added?

Yes, I'll do that and upload a V5 set.

 
 Thanks,
 Andrew

Thanks
James.

[PATCH V4 1/2] crypto: Add Imagination Technologies hw hash accelerator

2015-03-11 Thread James Hartley 
This adds support for the Imagination Technologies hash accelerator which
provides hardware acceleration for SHA1 SHA224 SHA256 and MD5 hashes.

Signed-off-by: James Hartley james.hart...@imgtec.com
---
 drivers/crypto/Kconfig|   14 +
 drivers/crypto/Makefile   |1 +
 drivers/crypto/img-hash.c | 1028 +
 3 files changed, 1043 insertions(+)
 create mode 100644 drivers/crypto/img-hash.c

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 2fb0fdf..c72223e 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -436,4 +436,18 @@ config CRYPTO_DEV_QCE
  hardware. To compile this driver as a module, choose M here. The
  module will be called qcrypto.
 
+config CRYPTO_DEV_IMGTEC_HASH
+   depends on MIPS || COMPILE_TEST
+   tristate Imagination Technologies hardware hash accelerator
+   select CRYPTO_ALG_API
+   select CRYPTO_MD5
+   select CRYPTO_SHA1
+   select CRYPTO_SHA224
+   select CRYPTO_SHA256
+   select CRYPTO_HASH
+   help
+ This driver interfaces with the Imagination Technologies
+ hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256
+ hashing algorithms.
+
 endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 3924f93..1c34fff 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_CRYPTO_DEV_CCP) += ccp/
 obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam/
 obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-aes.o
 obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o
+obj-$(CONFIG_CRYPTO_DEV_IMGTEC_HASH) += img-hash.o
 obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o
 obj-$(CONFIG_CRYPTO_DEV_MV_CESA) += mv_cesa.o
 obj-$(CONFIG_CRYPTO_DEV_MXS_DCP) += mxs-dcp.o
diff --git a/drivers/crypto/img-hash.c b/drivers/crypto/img-hash.c
new file mode 100644
index 000..5c19905
--- /dev/null
+++ b/drivers/crypto/img-hash.c
@@ -0,0 +1,1028 @@
+/*
+ * Copyright (c) 2014 Imagination Technologies
+ * Authors:  Will Thomas, James Hartley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Interface structure taken from omap-sham driver
+ */
+
+#include linux/clk.h
+#include linux/dmaengine.h
+#include linux/interrupt.h
+#include linux/io.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/of_device.h
+#include linux/platform_device.h
+#include linux/scatterlist.h
+
+#include crypto/internal/hash.h
+#include crypto/md5.h
+#include crypto/sha.h
+
+#define CR_RESET   0
+#define CR_RESET_SET   1
+#define CR_RESET_UNSET 0
+
+#define CR_MESSAGE_LENGTH_H0x4
+#define CR_MESSAGE_LENGTH_L0x8
+
+#define CR_CONTROL 0xc
+#define CR_CONTROL_BYTE_ORDER_3210 0
+#define CR_CONTROL_BYTE_ORDER_0123 1
+#define CR_CONTROL_BYTE_ORDER_2310 2
+#define CR_CONTROL_BYTE_ORDER_1032 3
+#define CR_CONTROL_BYTE_ORDER_SHIFT8
+#define CR_CONTROL_ALGO_MD50
+#define CR_CONTROL_ALGO_SHA1   1
+#define CR_CONTROL_ALGO_SHA224 2
+#define CR_CONTROL_ALGO_SHA256 3
+
+#define CR_INTSTAT 0x10
+#define CR_INTENAB 0x14
+#define CR_INTCLEAR0x18
+#define CR_INT_RESULTS_AVAILABLE   BIT(0)
+#define CR_INT_NEW_RESULTS_SET BIT(1)
+#define CR_INT_RESULT_READ_ERR BIT(2)
+#define CR_INT_MESSAGE_WRITE_ERROR BIT(3)
+#define CR_INT_STATUS  BIT(8)
+
+#define CR_RESULT_QUEUE0x1c
+#define CR_RSD00x40
+#define CR_CORE_REV0x50
+#define CR_CORE_DES1   0x60
+#define CR_CORE_DES2   0x70
+
+#define DRIVER_FLAGS_BUSY  BIT(0)
+#define DRIVER_FLAGS_FINAL BIT(1)
+#define DRIVER_FLAGS_DMA_ACTIVEBIT(2)
+#define DRIVER_FLAGS_OUTPUT_READY  BIT(3)
+#define DRIVER_FLAGS_INIT  BIT(4)
+#define DRIVER_FLAGS_CPU   BIT(5)
+#define DRIVER_FLAGS_DMA_READY BIT(6)
+#define DRIVER_FLAGS_ERROR BIT(7)
+#define DRIVER_FLAGS_SGBIT(8)
+#define DRIVER_FLAGS_SHA1  BIT(18)
+#define DRIVER_FLAGS_SHA224BIT(19)
+#define DRIVER_FLAGS_SHA256BIT(20)
+#define DRIVER_FLAGS_MD5   BIT(21)
+
+#define IMG_HASH_QUEUE_LENGTH  20
+#define IMG_HASH_DMA_THRESHOLD 64
+
+#ifdef __LITTLE_ENDIAN
+#define IMG_HASH_BYTE_ORDERCR_CONTROL_BYTE_ORDER_3210
+#else
+#define IMG_HASH_BYTE_ORDERCR_CONTROL_BYTE_ORDER_0123
+#endif
+
+struct img_hash_dev;
+
+struct img_hash_request_ctx {
+   struct img_hash_dev *hdev;
+   u8 digest[SHA256_DIGEST_SIZE] __aligned(sizeof(u32));
+   unsigned long   flags;
+   size_t  digsize;
+
+