RE: [PATCH v2 2/3] i2c: xilinx: Set tx direction in write operation
Hi Michal, -Original Message- From: Michal Simek [mailto:mon...@monstr.eu] Sent: Friday, October 04, 2013 7:08 PM To: Lars-Peter Clausen Cc: Wolfram Sang; Michal Simek; linux-ker...@vger.kernel.org; Appana Durga Kedareswara Rao; Appana Durga Kedareswara Rao; Jean Delvare; Peter Korsgaard; linux-i2c@vger.kernel.org; Richard Röjfors; Steven A. Falco Subject: Re: [PATCH v2 2/3] i2c: xilinx: Set tx direction in write operation On 10/04/2013 03:38 PM, Lars-Peter Clausen wrote: On 10/04/2013 03:09 PM, Michal Simek wrote: On 10/04/2013 02:12 PM, Lars-Peter Clausen wrote: On 10/04/2013 01:55 PM, Wolfram Sang wrote: On Fri, Oct 04, 2013 at 11:53:49AM +0200, Michal Simek wrote: On 10/04/2013 07:46 AM, Wolfram Sang wrote: + cr = xiic_getreg32(i2c, XIIC_CR_REG_OFFSET); + cr |= XIIC_CR_DIR_IS_TX_MASK; + xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, cr); + Is there no need to clear the bit again when receiving? This bit is cleared in xiic_xfer() - xiic_start_xfer() -xiic_reinit() xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); A bit implicit, but OK. And did transferring ever work if this bit was never set before? I really don't know. We have switched from old driver to this new mainline one and based on our eeprom testing we have found that this bit hasn't been setup properly. It is described here. http://www.xilinx.com/support/documentation/ip_documentation/axi_i ic/v1_02_a/axi_iic_ds756.pdf page 28 - step 3. IIC Master Transmitter with a Repeated Start 1. Write the IIC device address to the TX_FIFO. 2. Write data to TX_FIFO. 3. Write to Control Register (CR) to set MSMS = 1 and TX = 1. 4. Continue writing data to TX_FIFO. 5. Wait for transmit FIFO empty interrupt. This implies the IIC has throttled the bus. 6. Write to CR to set RSTA = 1. Repeated start is not happening in the driver as well, or am I overlooking something? 7. Write IIC device address to TX_FIFO. 8. Write all data except last byte to TX_FIFO. 9. Wait for transmit FIFO empty interrupt. This implies the IIC has throttled the bus. 10. Write to CR to set MSMS = 0. The IIC generates a stop condition at the end of the last byte. 11. Write last byte of data to TX_FIFO. CCing more people who worked on the driver in the past and might have experiences The current version works fine here. The driver uses whats described in the datasheet as dynamic controller logic flow and not the standard controller logic flow. The sequence Michal mentioned above is from the standard controller logic flow section. Does this change break dynamic controller logic flow? Not sure, but I would assume that the bit is ignored in this mode. But I don't think the patch should be applied since this step is not in the sequence of steps that should be done. Kedar: Can you please look at both these modes and provide feedback? The driver is following the Dynamic controller logic flow as per the dynamic Controller logic flow. These bits need not to be set. It was my mistake. Please ignore this patch. There was an incorrect h/w design on which I tested this that's why I thought it is a Solution for this. Now I tested with the proper h/w design it is working fine for me without setting this bit. Thanks lars for the feedback. Regards, Kedar. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U- BOOT custodian and responsible for u-boot arm zynq platform This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. -- To unsubscribe from this list: send the line unsubscribe linux-i2c in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH] i2c: omap: Clear ARDY bit twice
Initially commit cb527ede1bf6ff2008a025606f25344b8ed7b4ac
i2c-omap: Double clear of ARDY status in IRQ handler
added a workaround for undocumented errata ProDB0017052.
But then commit 1d7afc95946487945cc7f5019b41255b72224b70
i2c: omap: ack IRQ in parts refactored code and missed
one of ARDY clearings. So current code violates errata.
It causes often i2c bus timeouts on my Pandaboard.
This patch adds a second clearing in place.
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
Signed-off-by: Taras Kondratiuk taras.kondrat...@linaro.org
---
Cc: Felipe Balbi ba...@ti.com
Cc: Richard woodruff r-woodru...@ti.com
Cc: Tony Lindgren t...@atomide.com
Cc: Wolfram Sang w...@the-dreams.de
Cc: linux-o...@vger.kernel.org
Cc: linux-i2c@vger.kernel.org
Cc: linux-ker...@vger.kernel.org
---
drivers/i2c/busses/i2c-omap.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index f5d6de0..d69826e 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -939,6 +939,9 @@ omap_i2c_isr_thread(int this_irq, void *dev_id)
/*
* ProDB0017052: Clear ARDY bit twice
*/
+ if (stat OMAP_I2C_STAT_ARDY)
+ omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ARDY);
+
if (stat (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
OMAP_I2C_STAT_AL)) {
omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
--
1.7.9.5
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[PATCH 3/4] ARM: dts: bcm281xx: Add i2c busses
Add the DTS nodes for all the i2c busses in the SoC.
Signed-off-by: Tim Kryger tim.kry...@linaro.org
Reviewed-by: Christian Daudt c...@broadcom.com
Reviewed-by: Matt Porter matt.por...@linaro.org
Reviewed-by: Markus Mayer markus.ma...@linaro.org
---
arch/arm/boot/dts/bcm11351.dtsi | 40
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 1246885..4bfd7e3 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -146,6 +146,46 @@
status = disabled;
};
+ i2c@3e016000 {
+ compatible = brcm,bcm11351-i2c, brcm,kona-i2c;
+ reg = 0x3e016000 0x80;
+ interrupts = GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = bsc1_clk;
+ status = disabled;
+ };
+
+ i2c@3e017000 {
+ compatible = brcm,bcm11351-i2c, brcm,kona-i2c;
+ reg = 0x3e017000 0x80;
+ interrupts = GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = bsc2_clk;
+ status = disabled;
+ };
+
+ i2c@3e018000 {
+ compatible = brcm,bcm11351-i2c, brcm,kona-i2c;
+ reg = 0x3e018000 0x80;
+ interrupts = GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = bsc3_clk;
+ status = disabled;
+ };
+
+ i2c@3500d000 {
+ compatible = brcm,bcm11351-i2c, brcm,kona-i2c;
+ reg = 0x3500d000 0x80;
+ interrupts = GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH;
+ #address-cells = 1;
+ #size-cells = 0;
+ clocks = pmu_bsc_clk;
+ status = disabled;
+ };
+
clocks {
bsc1_clk: bsc1 {
compatible = fixed-clock;
--
1.8.0.1
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[PATCH 4/4] ARM: dts: bcm28155-ap: Enable all the i2c busses
Enable all available i2c busses.
Signed-off-by: Tim Kryger tim.kry...@linaro.org
Reviewed-by: Christian Daudt c...@broadcom.com
Reviewed-by: Matt Porter matt.por...@linaro.org
Reviewed-by: Markus Mayer markus.ma...@linaro.org
---
arch/arm/boot/dts/bcm28155-ap.dts | 20
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/bcm28155-ap.dts
b/arch/arm/boot/dts/bcm28155-ap.dts
index 08e47c2..bab302d 100644
--- a/arch/arm/boot/dts/bcm28155-ap.dts
+++ b/arch/arm/boot/dts/bcm28155-ap.dts
@@ -27,6 +27,26 @@
status = okay;
};
+ i2c@3e016000 {
+ status=okay;
+ clock-frequency = 40;
+ };
+
+ i2c@3e017000 {
+ status=okay;
+ clock-frequency = 40;
+ };
+
+ i2c@3e018000 {
+ status=okay;
+ clock-frequency = 40;
+ };
+
+ i2c@3500d000 {
+ status=okay;
+ clock-frequency = 40;
+ };
+
sdio1: sdio@3f18 {
max-frequency = 4800;
status = okay;
--
1.8.0.1
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[PATCH 0/4] Add-Broadcom-Kona-I2C-Support
This series adds support for the Kona I2C bus found on Broadcom mobile SoCs like the bcm11351 (aka bcm281xx) and enables it on the bcm28155-ap board. It depends upon the following commits: https://lkml.org/lkml/2013/10/7/481 http://www.spinics.net/lists/arm-kernel/msg274964.html Tim Kryger (4): i2c: i2c-bcm-kona: Introduce Broadcom I2C Driver i2c: i2c-bcm-kona: Add support for high-speed mode ARM: dts: bcm281xx: Add i2c busses ARM: dts: bcm28155-ap: Enable all the i2c busses .../devicetree/bindings/i2c/i2c-bcm-kona.txt | 30 + arch/arm/boot/dts/bcm11351.dtsi| 40 + arch/arm/boot/dts/bcm28155-ap.dts | 20 + drivers/i2c/busses/Kconfig | 10 + drivers/i2c/busses/Makefile| 1 + drivers/i2c/busses/i2c-bcm-kona.c | 936 + 6 files changed, 1037 insertions(+) create mode 100644 Documentation/devicetree/bindings/i2c/i2c-bcm-kona.txt create mode 100644 drivers/i2c/busses/i2c-bcm-kona.c -- 1.8.0.1 -- To unsubscribe from this list: send the line unsubscribe linux-i2c in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/4] i2c: i2c-bcm-kona: Introduce Broadcom I2C Driver
Introduce support for Broadcom Serial Controller (BSC) I2C bus found
in the Kona family of Mobile SoCs. FIFO hardware is utilized but only
standard mode (100kHz), fast mode (400kHz), and fast mode plus (1MHz)
bus speeds are supported.
Signed-off-by: Tim Kryger tim.kry...@linaro.org
Reviewed-by: Matt Porter matt.por...@linaro.org
Reviewed-by: Markus Mayer markus.ma...@linaro.org
---
.../devicetree/bindings/i2c/i2c-bcm-kona.txt | 30 +
drivers/i2c/busses/Kconfig | 10 +
drivers/i2c/busses/Makefile| 1 +
drivers/i2c/busses/i2c-bcm-kona.c | 820 +
4 files changed, 861 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-bcm-kona.txt
create mode 100644 drivers/i2c/busses/i2c-bcm-kona.c
diff --git a/Documentation/devicetree/bindings/i2c/i2c-bcm-kona.txt
b/Documentation/devicetree/bindings/i2c/i2c-bcm-kona.txt
new file mode 100644
index 000..fc71a60
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-bcm-kona.txt
@@ -0,0 +1,30 @@
+Broadcom Kona Family I2C
+=
+
+This I2C controller is used in the following Broadcom SoCs:
+
+ BCM11130
+ BCM11140
+ BCM11351
+ BCM28145
+ BCM28155
+
+Required Properties
+---
+- compatible: brcm,bcm11351-i2c, brcm,kona-i2c
+- reg: Physical base address and length of controller registers
+- interrupts: The interrupt number used by the controller
+- clock-frequency: The I2C bus frequency in Hz
+- #address-cells: Should be 1
+- #size-cells: Should be 0
+
+Example:
+
+i2c@3e016000 {
+ compatible = brcm,bcm11351-i2c,brcm,kona-i2c;
+ reg = 0x3e016000 0x80;
+ interrupts = GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH;
+ clock-frequency = 40;
+ #address-cells = 1;
+ #size-cells = 0;
+};
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index cdcbd83..41a3f34 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -963,4 +963,14 @@ config SCx200_ACB
This support is also available as a module. If so, the module
will be called scx200_acb.
+config I2C_BCM_KONA
+ tristate BCM Kona I2C adapter
+ depends on ARCH_BCM_MOBILE
+ default y
+ help
+ If you say yes to this option, support will be included for the
+ I2C interface on the Broadcom Kona family of processors.
+
+ If you do not need KONA I2C inteface, say N.
+
endmenu
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index d00997f..91de826 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_I2C_VIPERBOARD) += i2c-viperboard.o
# Other I2C/SMBus bus drivers
obj-$(CONFIG_I2C_ACORN)+= i2c-acorn.o
+obj-$(CONFIG_I2C_BCM_KONA) += i2c-bcm-kona.o
obj-$(CONFIG_I2C_ELEKTOR) += i2c-elektor.o
obj-$(CONFIG_I2C_PCA_ISA) += i2c-pca-isa.o
obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o
diff --git a/drivers/i2c/busses/i2c-bcm-kona.c
b/drivers/i2c/busses/i2c-bcm-kona.c
new file mode 100644
index 000..2936acf
--- /dev/null
+++ b/drivers/i2c/busses/i2c-bcm-kona.c
@@ -0,0 +1,820 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed as is WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/device.h
+#include linux/kernel.h
+#include linux/module.h
+#include linux/sched.h
+#include linux/i2c.h
+#include linux/interrupt.h
+#include linux/platform_device.h
+#include linux/clk.h
+#include linux/io.h
+#include linux/clk.h
+#include linux/slab.h
+
+/* Hardware register offsets and field defintions */
+#define CS_OFFSET 0x0020
+#define CS_ACK_SHIFT 3
+#define CS_ACK_MASK0x0008
+#define CS_ACK_CMD_GEN_START 0x
+#define CS_ACK_CMD_GEN_RESTART 0x0001
+#define CS_CMD_SHIFT 1
+#define CS_CMD_CMD_NO_ACTION 0x
+#define CS_CMD_CMD_START_RESTART 0x0001
+#define CS_CMD_CMD_STOP0x0002
+#define CS_EN_SHIFT0
+#define CS_EN_CMD_ENABLE_BSC 0x0001
+
+#define TIM_OFFSET 0x0024
+#define TIM_PRESCALE_SHIFT 6
+#define TIM_P_SHIFT3
+#define TIM_NO_DIV_SHIFT 2
+#define TIM_DIV_SHIFT 0
+
+#define DAT_OFFSET 0x0028
+
[PATCH 2/4] i2c: i2c-bcm-kona: Add support for high-speed mode
Add support for I2C high-speed mode (3.4 MHz).
Signed-off-by: Tim Kryger tim.kry...@linaro.org
Reviewed-by: Matt Porter matt.por...@linaro.org
Reviewed-by: Markus Mayer markus.ma...@linaro.org
---
drivers/i2c/busses/i2c-bcm-kona.c | 116 ++
1 file changed, 116 insertions(+)
diff --git a/drivers/i2c/busses/i2c-bcm-kona.c
b/drivers/i2c/busses/i2c-bcm-kona.c
index 2936acf..458714f 100644
--- a/drivers/i2c/busses/i2c-bcm-kona.c
+++ b/drivers/i2c/busses/i2c-bcm-kona.c
@@ -77,6 +77,9 @@
#define HSTIM_OFFSET 0x0058
#define HSTIM_HS_MODE_MASK 0x8000
+#define HSTIM_HS_HOLD_SHIFT10
+#define HSTIM_HS_HIGH_PHASE_SHIFT 5
+#define HSTIM_HS_SETUP_SHIFT 0
#define PADCTL_OFFSET 0x005c
#define PADCTL_PAD_OUT_EN_MASK 0x0004
@@ -91,6 +94,9 @@
#define MAX_TX_FIFO_SIZE 64U /* bytes */
#define STD_EXT_CLK_FREQ 1300UL
+#define HS_EXT_CLK_FREQ10400UL
+
+#define MASTERCODE 0x08 /* Mastercodes are _1xxxb */
#define I2C_TIMEOUT100 /* msecs */
@@ -108,6 +114,10 @@ enum bus_speed_index {
BCM_SPD_1MHZ,
};
+enum hs_bus_speed_index {
+ BCM_SPD_3P4MHZ = 0,
+};
+
/* Internal divider settings for standard mode, fast mode and fast mode plus */
struct bus_speed_cfg {
uint8_t time_m; /* Number of cycles for setup time */
@@ -118,12 +128,30 @@ struct bus_speed_cfg {
uint8_t time_div; /* Post-prescale divider */
};
+/* Internal divider settings for high-speed mode */
+struct hs_bus_speed_cfg {
+ uint8_t hs_hold;/* Number of clock cycles SCL stays low until
+ the end of bit period */
+ uint8_t hs_high_phase; /* Number of clock cycles SCL stays high
+ before it falls */
+ uint8_t hs_setup; /* Number of clock cycles SCL stays low
+ before it rises */
+ uint8_t prescale; /* Prescale divider */
+ uint8_t time_p; /* Timing coefficient */
+ uint8_t no_div; /* Disable clock divider */
+ uint8_t time_div; /* Post-prescale divider */
+};
+
static const struct bus_speed_cfg std_cfg_table[] = {
[BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
[BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
[BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
};
+static const struct hs_bus_speed_cfg hs_cfg_table[] = {
+ [BCM_SPD_3P4MHZ] = {0x01, 0x08, 0x14, 0x00, 0x06, 0x01, 0x00},
+};
+
struct bcm_kona_i2c_dev {
/* Pointer to linux device struct */
struct device *device;
@@ -137,6 +165,9 @@ struct bcm_kona_i2c_dev {
/* Standard Speed configuration */
const struct bus_speed_cfg *std_cfg;
+ /* High Speed configuration (if applicable) */
+ const struct hs_bus_speed_cfg *hs_cfg;
+
/* Linux I2C adapter struct */
struct i2c_adapter adapter;
@@ -520,6 +551,72 @@ static void bcm_kona_i2c_config_timing(struct
bcm_kona_i2c_dev *dev)
dev-base + CLKEN_OFFSET);
}
+static void bcm_kona_i2c_config_timing_hs(struct bcm_kona_i2c_dev *dev)
+{
+ writel((dev-hs_cfg-prescale TIM_PRESCALE_SHIFT) |
+ (dev-hs_cfg-time_p TIM_P_SHIFT) |
+ (dev-hs_cfg-no_div TIM_NO_DIV_SHIFT) |
+ (dev-hs_cfg-time_div TIM_DIV_SHIFT),
+ dev-base + TIM_OFFSET);
+
+ writel((dev-hs_cfg-hs_hold HSTIM_HS_HOLD_SHIFT) |
+ (dev-hs_cfg-hs_high_phase HSTIM_HS_HIGH_PHASE_SHIFT) |
+ (dev-hs_cfg-hs_setup HSTIM_HS_SETUP_SHIFT),
+ dev-base + HSTIM_OFFSET);
+
+ writel(readl(dev-base + HSTIM_OFFSET) | HSTIM_HS_MODE_MASK,
+ dev-base + HSTIM_OFFSET);
+}
+
+static int bcm_kona_i2c_switch_to_hs(struct bcm_kona_i2c_dev *dev)
+{
+ int rc;
+
+ /* Send mastercode at standard speed */
+ rc = bcm_kona_i2c_write_byte(dev, MASTERCODE, 1);
+ if (rc 0) {
+ pr_err(High speed handshake failed\n);
+ return rc;
+ }
+
+ /* Configure external clock to higher frequency */
+ rc = clk_set_rate(dev-external_clk, HS_EXT_CLK_FREQ);
+ if (rc) {
+ dev_err(dev-device, %s: clk_set_rate returned %d\n,
+ __func__, rc);
+ return rc;
+ }
+
+ /* Reconfigure internal dividers */
+ bcm_kona_i2c_config_timing_hs(dev);
+
+ /* Send a restart command */
+ rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
+ if (rc 0) {
+ dev_err(dev-device,
+ High speed restart command failed rc = %d\n, rc);
+ }
+
+ return rc;
+}
+
+static int bcm_kona_i2c_switch_to_std(struct bcm_kona_i2c_dev
Re: getting rid of subsys_initcall usage? (was: Re: [PATCH RESEND] i2c: designware: use module_platform_driver)
On Thu, Sep 12, 2013 at 9:12 AM, zhangfei gao zhangfei@gmail.com wrote: On Fri, Aug 30, 2013 at 4:27 PM, Tony Lindgren t...@atomide.com wrote: * zhangfei gao zhangfei@gmail.com [130829 23:36]: What about concerns from Wolfram: Other people might be depending on subsys_initcall to get I2C active before they want to activate, say, PMICs. So, I fear regressions, since deferred probing might not be available in the needed places to avoid these regressions. There should not be any reason to get a PMIC activated early on. The system should be booting already at that point, and the PMIC related init can be done later on. Is it too late using module_init for PMIC? You can probably do it as a fix early on during the -rc cycle too. Of course it needs to be verified to work first :) Dear Wolfram What's your suggestion about this issue. Use subsys_initcall, deferred probing still exist if base on pin control driver. Thanks Dear Wolfram Any plan about the patch? On one hand, module_X_driver is trend to replace subsys_initcall Refer from Mark We're trying to move away from needing to do this and to using deferred probing to resolve init ordering issues. Should we not be able to convert the drivers to module_X_driver()? On the other hand, subsys_initcall still been defered if pin controller driver been relied on. Thanks -- To unsubscribe from this list: send the line unsubscribe linux-i2c in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: getting rid of subsys_initcall usage? (was: Re: [PATCH RESEND] i2c: designware: use module_platform_driver)
Any plan about the patch? I am right now working on a patch series dealing with this. signature.asc Description: Digital signature
