RE: [PATCH 1/2] watchdog: uniphier: add UniPhier watchdog driver

[yamada.masahiro]

Hi Hayashibara-san


> a/Documentation/devicetree/bindings/watchdog/uniphier-wdt.txt
> b/Documentation/devicetree/bindings/watchdog/uniphier-wdt.txt
> new file mode 100644
> index 000..a59d1ba
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/watchdog/uniphier-wdt.txt
> @@ -0,0 +1,20 @@
> +UniPhier watchdog timer controller
> +
> +This UniPhier watchdog timer controller must be under sysctrl compatible
> node.
> +
> +Required properties:
> +- compatible: should be "socionext,uniphier-wdt"
> +
> +Example:
> +
> + sysctrl@6184 {
> + compatible = "socionext,uniphier-ld11-sysctrl",
> +  "simple-mfd", "syscon";
> + reg = <0x6184 0x4000>;
> +
> + sys_wdt: watchdog {
> + compatible = "socionext,uniphier-wdt";
> + }
> +
> + other nodes ...
> + };


Next time, please include
devicet...@vger.kernel.org
(and Rob) in your CC list for binding review.

I think scripts/get_maintainer.pl will do it correctly for you.





> +#include 

Is this used?


Thanks.

RE: [PATCH 1/2] watchdog: uniphier: add UniPhier watchdog driver

[yamada.masahiro]

Hi Hayashibara-san


> a/Documentation/devicetree/bindings/watchdog/uniphier-wdt.txt
> b/Documentation/devicetree/bindings/watchdog/uniphier-wdt.txt
> new file mode 100644
> index 000..a59d1ba
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/watchdog/uniphier-wdt.txt
> @@ -0,0 +1,20 @@
> +UniPhier watchdog timer controller
> +
> +This UniPhier watchdog timer controller must be under sysctrl compatible
> node.
> +
> +Required properties:
> +- compatible: should be "socionext,uniphier-wdt"
> +
> +Example:
> +
> + sysctrl@6184 {
> + compatible = "socionext,uniphier-ld11-sysctrl",
> +  "simple-mfd", "syscon";
> + reg = <0x6184 0x4000>;
> +
> + sys_wdt: watchdog {
> + compatible = "socionext,uniphier-wdt";
> + }
> +
> + other nodes ...
> + };


Next time, please include
devicet...@vger.kernel.org
(and Rob) in your CC list for binding review.

I think scripts/get_maintainer.pl will do it correctly for you.





> +#include 

Is this used?


Thanks.

Re: Patch 0727d35de ("Make initramfs honor CONFIG_DEVTMPFS_MOUNT") breaks boot

[Rob Landley]

On 05/23/2017 06:08 PM, Yury Norov wrote:
>> It was 2 years ago, but AFAIR I took the Ubuntu image here:
>> http://cdimage.ubuntu.com/ubuntu-base/releases/14.04.1/release/ubuntu-base-14.04.1-core-arm64.tar.gz

Have you applied updates since then? (Maybe they fixed their init script
since 2 years ago?)

>> Kernel config is attached. I build the kernel with simple 'make'.
>>
>> Yury
> 
> Sorry, config is here.

$ diff -u yury.conf /boot/config-4.4.0-78-generic | grep '^[-+]' | wc -l
10384

So that's not Ubuntu's current 14.04 kernel config.

$ diff -u yury.conf /boot/config-4.2.0-36-generic | grep '^[-+]' | wc -l
10212

And it's not the oldest Ubuntu 14.04 config I have lying around (from a
year ago).

$ cd linux && make defconfig
$ diff -u ~/yury.conf .config | grep '^[-+]' | wc -l
4369

It's much closer to the current defconfig, but still significantly
different.

So you're using a custom config, and can't switch off a symbol.

Rob

Re: Patch 0727d35de ("Make initramfs honor CONFIG_DEVTMPFS_MOUNT") breaks boot

[Rob Landley]

On 05/23/2017 06:08 PM, Yury Norov wrote:
>> It was 2 years ago, but AFAIR I took the Ubuntu image here:
>> http://cdimage.ubuntu.com/ubuntu-base/releases/14.04.1/release/ubuntu-base-14.04.1-core-arm64.tar.gz

Have you applied updates since then? (Maybe they fixed their init script
since 2 years ago?)

>> Kernel config is attached. I build the kernel with simple 'make'.
>>
>> Yury
> 
> Sorry, config is here.

$ diff -u yury.conf /boot/config-4.4.0-78-generic | grep '^[-+]' | wc -l
10384

So that's not Ubuntu's current 14.04 kernel config.

$ diff -u yury.conf /boot/config-4.2.0-36-generic | grep '^[-+]' | wc -l
10212

And it's not the oldest Ubuntu 14.04 config I have lying around (from a
year ago).

$ cd linux && make defconfig
$ diff -u ~/yury.conf .config | grep '^[-+]' | wc -l
4369

It's much closer to the current defconfig, but still significantly
different.

So you're using a custom config, and can't switch off a symbol.

Rob

Re: [patch] compiler, clang: suppress warning for unused static inline functions

[Ingo Molnar]

* Matthias Kaehlcke  wrote:

> El Wed, May 24, 2017 at 02:01:15PM -0700 David Rientjes ha dit:
> 
> > GCC explicitly does not warn for unused static inline functions for
> > -Wunused-function.  The manual states:
> > 
> > Warn whenever a static function is declared but not defined or
> > a non-inline static function is unused.
> > 
> > Clang does warn for static inline functions that are unused.
> > 
> > It turns out that suppressing the warnings avoids potentially complex
> > #ifdef directives, which also reduces LOC.
> > 
> > Supress the warning for clang.
> > 
> > Signed-off-by: David Rientjes 
> > ---
> 
> As expressed earlier in other threads, I don't think gcc's behavior is
> preferable in this case. The warning on static inline functions (only
> in .c files) allows to detect truly unused code. About 50% of the
> warnings I have looked into so far fall into this category.
> 
> In my opinion it is more valuable to detect dead code than not having
> a few more __maybe_unused attributes (there aren't really that many
> instances, at least with x86 and arm64 defconfig). In most cases it is
> not necessary to use #ifdef, it is an option which is preferred by
> some maintainers. The reduced LOC is arguable, since dectecting dead
> code allows to remove it.

Static inline functions in headers are often not dead code.

Thanks,

Ingo

Re: [patch] compiler, clang: suppress warning for unused static inline functions

[Ingo Molnar]

* Matthias Kaehlcke  wrote:

> El Wed, May 24, 2017 at 02:01:15PM -0700 David Rientjes ha dit:
> 
> > GCC explicitly does not warn for unused static inline functions for
> > -Wunused-function.  The manual states:
> > 
> > Warn whenever a static function is declared but not defined or
> > a non-inline static function is unused.
> > 
> > Clang does warn for static inline functions that are unused.
> > 
> > It turns out that suppressing the warnings avoids potentially complex
> > #ifdef directives, which also reduces LOC.
> > 
> > Supress the warning for clang.
> > 
> > Signed-off-by: David Rientjes 
> > ---
> 
> As expressed earlier in other threads, I don't think gcc's behavior is
> preferable in this case. The warning on static inline functions (only
> in .c files) allows to detect truly unused code. About 50% of the
> warnings I have looked into so far fall into this category.
> 
> In my opinion it is more valuable to detect dead code than not having
> a few more __maybe_unused attributes (there aren't really that many
> instances, at least with x86 and arm64 defconfig). In most cases it is
> not necessary to use #ifdef, it is an option which is preferred by
> some maintainers. The reduced LOC is arguable, since dectecting dead
> code allows to remove it.

Static inline functions in headers are often not dead code.

Thanks,

Ingo

Re: Fwd: Watchdog detected hard lockup.

[Sergey Senozhatsky]

On (05/25/17 11:14), Sumit Gemini wrote:
>Thanks Sergey and i forgot to add other guys in discussion.
> 
> 
>[1]lkml.kernel.org/r/20170509082859.854-1-sergey.senozhat...@gmail.com
> 
>Now I'm going for backporting the kernel with RFC, as you suggested me
>yesterday.

or you can try to reduce the amount of data you printk from IRQ. do you
need to hex dump sbks all the time? switching to a deferred printk won't
do the trick, probably, because you gonna console_unlock() from IRQ in
the worst case anyway.

-ss

Re: Fwd: Watchdog detected hard lockup.

[Sergey Senozhatsky]

On (05/25/17 11:14), Sumit Gemini wrote:
>Thanks Sergey and i forgot to add other guys in discussion.
> 
> 
>[1]lkml.kernel.org/r/20170509082859.854-1-sergey.senozhat...@gmail.com
> 
>Now I'm going for backporting the kernel with RFC, as you suggested me
>yesterday.

or you can try to reduce the amount of data you printk from IRQ. do you
need to hex dump sbks all the time? switching to a deferred printk won't
do the trick, probably, because you gonna console_unlock() from IRQ in
the worst case anyway.

-ss

Re: [PATCH/RFC] iio: hi8435: do not enable all events by default

[Nikita Yushchenko]

24.05.2017 22:27, Jonathan Cameron wrote:
> On Tue, 23 May 2017 11:08:30 +0300
> Nikita Yushchenko  wrote:
> 
>> Having all events enabled by default is misleading.
>> Userspace should explicitly enable events they want to receive.
>>
>> Signed-off-by: Nikita Yushchenko 
> I agree in principle, but this is a userspace ABI change.  Sadly we
> can't do it with out risking breaking userspace code...
> 
> One of those we should have caught in review, but now it's there
> we can't actually do anything about it unless we are absolutely
> sure no one will notice!

I see your point.

Still, isn't there subsystem-level default that all events are disabled
by default?  If such, then current hi8435 state breaks subsystem-level
rules, which is a [userspace-visible] bug.  I'm not sure how far should
we go in bug compatibility.

One crazy idea could be - make default selectable via device tree (with
default set to all-enabled to keep bug-compatibility).  But perhaps
that's over-reaction.

Re: [PATCH/RFC] iio: hi8435: do not enable all events by default

[Nikita Yushchenko]

24.05.2017 22:27, Jonathan Cameron wrote:
> On Tue, 23 May 2017 11:08:30 +0300
> Nikita Yushchenko  wrote:
> 
>> Having all events enabled by default is misleading.
>> Userspace should explicitly enable events they want to receive.
>>
>> Signed-off-by: Nikita Yushchenko 
> I agree in principle, but this is a userspace ABI change.  Sadly we
> can't do it with out risking breaking userspace code...
> 
> One of those we should have caught in review, but now it's there
> we can't actually do anything about it unless we are absolutely
> sure no one will notice!

I see your point.

Still, isn't there subsystem-level default that all events are disabled
by default?  If such, then current hi8435 state breaks subsystem-level
rules, which is a [userspace-visible] bug.  I'm not sure how far should
we go in bug compatibility.

One crazy idea could be - make default selectable via device tree (with
default set to all-enabled to keep bug-compatibility).  But perhaps
that's over-reaction.

[PATCH v5 03/10] VAS: Define vas_init() and vas_exit()

[Sukadev Bhattiprolu]

Implement vas_init() and vas_exit() functions for a new VAS module.
This VAS module is essentially a library for other device drivers
and kernel users of the NX coprocessors like NX-842 and NX-GZIP.
In the future this will be extended to add support for user space
to access the NX coprocessors.

VAS is currently only supported with 64K page size.

Signed-off-by: Sukadev Bhattiprolu 
---
Changelog[v5]:
- [Ben Herrenschmidt]: Create and use platform device tree nodes,
  fix up the "reg" properties for the VAS DT node and use the
  platform device helpers to parse the reg properties; Use linked
  list of VAS instances (don't assume vasids are sequential);
  Use CONFIG_PPC_VAS instead of CONFIG_VAS.

Changelog[v4]:
- [Michael Neuling] Fix some accidental deletions; fix help text
  in Kconfig; change vas_initialized to a function; move from
  drivers/misc to arch/powerpc/kernel
- Drop the vas_window_reset() interface. It is not needed as
  window will be initialized before each use.
- Add a "depends on PPC_64K_PAGES"

Changelog[v3]:
- Zero vas_instances memory on allocation
- [Haren Myneni] Fix description in Kconfig
Changelog[v2]:
- Get HVWC, UWC and window address parameters from device tree.
---
 .../devicetree/bindings/powerpc/ibm,vas.txt|  24 +++
 MAINTAINERS|   8 +
 arch/powerpc/platforms/powernv/Kconfig |  14 ++
 arch/powerpc/platforms/powernv/Makefile|   1 +
 arch/powerpc/platforms/powernv/vas-window.c|  19 +++
 arch/powerpc/platforms/powernv/vas.c   | 183 +
 arch/powerpc/platforms/powernv/vas.h   |  10 +-
 7 files changed, 257 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/powerpc/ibm,vas.txt
 create mode 100644 arch/powerpc/platforms/powernv/vas-window.c
 create mode 100644 arch/powerpc/platforms/powernv/vas.c

diff --git a/Documentation/devicetree/bindings/powerpc/ibm,vas.txt 
b/Documentation/devicetree/bindings/powerpc/ibm,vas.txt
new file mode 100644
index 000..8468a3a
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/ibm,vas.txt
@@ -0,0 +1,24 @@
+* IBM Powerpc Virtual Accelerator Switchboard (VAS)
+
+VAS is a hardware mechanism that allows ekrnel subsystems and user processes
+to directly submit compression and other requests to Nest accelerators (NX)
+or other coprocessors functions.
+
+Required properties:
+- compatible : should be "ibm,vas" or "ibm,power9-vas"
+- ibm,vas-id : A unique identifier for each instance of VAS in the system
+- reg : Should contain 4 pairs of 64-bit fields specifying the Hypervisor
+  window context start and length, OS/User window context start and length,
+  "Paste address" start and length, "Paste window id" start bit and number
+  of bits)
+- name : "vas"
+
+Example:
+
+   vas@60191 {
+   compatible = "ibm,vas", "ibm,power9-vas";
+   reg = <0x60191 0x200 0x60190 0x1 
0x8 0x1 0x20 0x10>;
+   name = "vas";
+   ibm,vas-id = <0x1>;
+   };
+
diff --git a/MAINTAINERS b/MAINTAINERS
index 9e98464..4c4f05e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6331,6 +6331,14 @@ F:   drivers/crypto/nx/nx.*
 F: drivers/crypto/nx/nx_csbcpb.h
 F: drivers/crypto/nx/nx_debugfs.h
 
+IBM Power Virtual Accelerator Switchboard
+M: Sukadev Bhattiprolu
+L: linuxppc-...@lists.ozlabs.org
+S: Supported
+F: arch/powerpc/platforms/powernv/vas*
+F: arch/powerpc/include/asm/vas.h
+F: arch/powerpc/include/uapi/asm/vas.h
+
 IBM Power 842 compression accelerator
 M: Haren Myneni 
 S: Supported
diff --git a/arch/powerpc/platforms/powernv/Kconfig 
b/arch/powerpc/platforms/powernv/Kconfig
index 6a6f4ef..f565454 100644
--- a/arch/powerpc/platforms/powernv/Kconfig
+++ b/arch/powerpc/platforms/powernv/Kconfig
@@ -30,3 +30,17 @@ config OPAL_PRD
help
  This enables the opal-prd driver, a facility to run processor
  recovery diagnostics on OpenPower machines
+
+config PPC_VAS
+   bool "IBM Virtual Accelerator Switchboard (VAS)"
+   depends on PPC_POWERNV && PPC_64K_PAGES
+   default n
+   help
+ This enables support for IBM Virtual Accelerator Switchboard (VAS).
+
+ VAS allows accelerators in co-processors like NX-GZIP and NX-842
+ to be accessible to kernel subsystems and user processes.
+
+ VAS adapters are found in POWER9 based systems.
+
+ If unsure, say N.
diff --git a/arch/powerpc/platforms/powernv/Makefile 
b/arch/powerpc/platforms/powernv/Makefile
index b5d98cb..e4db292 100644
--- a/arch/powerpc/platforms/powernv/Makefile
+++ b/arch/powerpc/platforms/powernv/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_PPC_SCOM)+= opal-xscom.o
 

[PATCH v5 03/10] VAS: Define vas_init() and vas_exit()

[Sukadev Bhattiprolu]

Implement vas_init() and vas_exit() functions for a new VAS module.
This VAS module is essentially a library for other device drivers
and kernel users of the NX coprocessors like NX-842 and NX-GZIP.
In the future this will be extended to add support for user space
to access the NX coprocessors.

VAS is currently only supported with 64K page size.

Signed-off-by: Sukadev Bhattiprolu 
---
Changelog[v5]:
- [Ben Herrenschmidt]: Create and use platform device tree nodes,
  fix up the "reg" properties for the VAS DT node and use the
  platform device helpers to parse the reg properties; Use linked
  list of VAS instances (don't assume vasids are sequential);
  Use CONFIG_PPC_VAS instead of CONFIG_VAS.

Changelog[v4]:
- [Michael Neuling] Fix some accidental deletions; fix help text
  in Kconfig; change vas_initialized to a function; move from
  drivers/misc to arch/powerpc/kernel
- Drop the vas_window_reset() interface. It is not needed as
  window will be initialized before each use.
- Add a "depends on PPC_64K_PAGES"

Changelog[v3]:
- Zero vas_instances memory on allocation
- [Haren Myneni] Fix description in Kconfig
Changelog[v2]:
- Get HVWC, UWC and window address parameters from device tree.
---
 .../devicetree/bindings/powerpc/ibm,vas.txt|  24 +++
 MAINTAINERS|   8 +
 arch/powerpc/platforms/powernv/Kconfig |  14 ++
 arch/powerpc/platforms/powernv/Makefile|   1 +
 arch/powerpc/platforms/powernv/vas-window.c|  19 +++
 arch/powerpc/platforms/powernv/vas.c   | 183 +
 arch/powerpc/platforms/powernv/vas.h   |  10 +-
 7 files changed, 257 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/powerpc/ibm,vas.txt
 create mode 100644 arch/powerpc/platforms/powernv/vas-window.c
 create mode 100644 arch/powerpc/platforms/powernv/vas.c

diff --git a/Documentation/devicetree/bindings/powerpc/ibm,vas.txt 
b/Documentation/devicetree/bindings/powerpc/ibm,vas.txt
new file mode 100644
index 000..8468a3a
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/ibm,vas.txt
@@ -0,0 +1,24 @@
+* IBM Powerpc Virtual Accelerator Switchboard (VAS)
+
+VAS is a hardware mechanism that allows ekrnel subsystems and user processes
+to directly submit compression and other requests to Nest accelerators (NX)
+or other coprocessors functions.
+
+Required properties:
+- compatible : should be "ibm,vas" or "ibm,power9-vas"
+- ibm,vas-id : A unique identifier for each instance of VAS in the system
+- reg : Should contain 4 pairs of 64-bit fields specifying the Hypervisor
+  window context start and length, OS/User window context start and length,
+  "Paste address" start and length, "Paste window id" start bit and number
+  of bits)
+- name : "vas"
+
+Example:
+
+   vas@60191 {
+   compatible = "ibm,vas", "ibm,power9-vas";
+   reg = <0x60191 0x200 0x60190 0x1 
0x8 0x1 0x20 0x10>;
+   name = "vas";
+   ibm,vas-id = <0x1>;
+   };
+
diff --git a/MAINTAINERS b/MAINTAINERS
index 9e98464..4c4f05e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6331,6 +6331,14 @@ F:   drivers/crypto/nx/nx.*
 F: drivers/crypto/nx/nx_csbcpb.h
 F: drivers/crypto/nx/nx_debugfs.h
 
+IBM Power Virtual Accelerator Switchboard
+M: Sukadev Bhattiprolu
+L: linuxppc-...@lists.ozlabs.org
+S: Supported
+F: arch/powerpc/platforms/powernv/vas*
+F: arch/powerpc/include/asm/vas.h
+F: arch/powerpc/include/uapi/asm/vas.h
+
 IBM Power 842 compression accelerator
 M: Haren Myneni 
 S: Supported
diff --git a/arch/powerpc/platforms/powernv/Kconfig 
b/arch/powerpc/platforms/powernv/Kconfig
index 6a6f4ef..f565454 100644
--- a/arch/powerpc/platforms/powernv/Kconfig
+++ b/arch/powerpc/platforms/powernv/Kconfig
@@ -30,3 +30,17 @@ config OPAL_PRD
help
  This enables the opal-prd driver, a facility to run processor
  recovery diagnostics on OpenPower machines
+
+config PPC_VAS
+   bool "IBM Virtual Accelerator Switchboard (VAS)"
+   depends on PPC_POWERNV && PPC_64K_PAGES
+   default n
+   help
+ This enables support for IBM Virtual Accelerator Switchboard (VAS).
+
+ VAS allows accelerators in co-processors like NX-GZIP and NX-842
+ to be accessible to kernel subsystems and user processes.
+
+ VAS adapters are found in POWER9 based systems.
+
+ If unsure, say N.
diff --git a/arch/powerpc/platforms/powernv/Makefile 
b/arch/powerpc/platforms/powernv/Makefile
index b5d98cb..e4db292 100644
--- a/arch/powerpc/platforms/powernv/Makefile
+++ b/arch/powerpc/platforms/powernv/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_PPC_SCOM)+= opal-xscom.o
 obj-$(CONFIG_MEMORY_FAILURE)   += opal-memory-errors.o
 

[PATCH v5 02/10] Move GET_FIELD/SET_FIELD to vas.h

[Sukadev Bhattiprolu]

Move the GET_FIELD and SET_FIELD macros to vas.h as VAS and other
users of VAS, including NX-842 can use those macros.

There is a lot of related code between the VAS/NX kernel drivers
and skiboot. For consistency switch the order of parameters in
SET_FIELD to match the order in skiboot.

Signed-off-by: Sukadev Bhattiprolu 
Reviewed-by: Dan Streetman 
---

Changelog[v3]
- Fix order of parameters in nx-842 driver.
---
 arch/powerpc/include/uapi/asm/vas.h | 8 
 drivers/crypto/nx/nx-842-powernv.c  | 7 ---
 drivers/crypto/nx/nx-842.h  | 5 -
 3 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/include/uapi/asm/vas.h 
b/arch/powerpc/include/uapi/asm/vas.h
index ddfe046..21249f5 100644
--- a/arch/powerpc/include/uapi/asm/vas.h
+++ b/arch/powerpc/include/uapi/asm/vas.h
@@ -22,4 +22,12 @@
 #define VAS_THRESH_FIFO_GT_QTR_FULL2
 #define VAS_THRESH_FIFO_GT_EIGHTH_FULL 3
 
+/*
+ * Get/Set bit fields
+ */
+#define GET_FIELD(m, v)(((v) & (m)) >> MASK_LSH(m))
+#define MASK_LSH(m)(__builtin_ffsl(m) - 1)
+#define SET_FIELD(m, v, val)   \
+   (((v) & ~(m)) | typeof(v))(val)) << MASK_LSH(m)) & (m)))
+
 #endif /* _UAPI_MISC_VAS_H */
diff --git a/drivers/crypto/nx/nx-842-powernv.c 
b/drivers/crypto/nx/nx-842-powernv.c
index 1710f80..3abb045 100644
--- a/drivers/crypto/nx/nx-842-powernv.c
+++ b/drivers/crypto/nx/nx-842-powernv.c
@@ -22,6 +22,7 @@
 
 #include 
 #include 
+#include 
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Dan Streetman ");
@@ -424,9 +425,9 @@ static int nx842_powernv_function(const unsigned char *in, 
unsigned int inlen,
 
/* set up CCW */
ccw = 0;
-   ccw = SET_FIELD(ccw, CCW_CT, nx842_ct);
-   ccw = SET_FIELD(ccw, CCW_CI_842, 0); /* use 0 for hw auto-selection */
-   ccw = SET_FIELD(ccw, CCW_FC_842, fc);
+   ccw = SET_FIELD(CCW_CT, ccw, nx842_ct);
+   ccw = SET_FIELD(CCW_CI_842, ccw, 0); /* use 0 for hw auto-selection */
+   ccw = SET_FIELD(CCW_FC_842, ccw, fc);
 
/* set up CRB's CSB addr */
csb_addr = nx842_get_pa(csb) & CRB_CSB_ADDRESS;
diff --git a/drivers/crypto/nx/nx-842.h b/drivers/crypto/nx/nx-842.h
index a4eee3b..30929bd 100644
--- a/drivers/crypto/nx/nx-842.h
+++ b/drivers/crypto/nx/nx-842.h
@@ -100,11 +100,6 @@ static inline unsigned long nx842_get_pa(void *addr)
return page_to_phys(vmalloc_to_page(addr)) + offset_in_page(addr);
 }
 
-/* Get/Set bit fields */
-#define MASK_LSH(m)(__builtin_ffsl(m) - 1)
-#define GET_FIELD(v, m)(((v) & (m)) >> MASK_LSH(m))
-#define SET_FIELD(v, m, val)   (((v) & ~(m)) | (((val) << MASK_LSH(m)) & (m)))
-
 /**
  * This provides the driver's constraints.  Different nx842 implementations
  * may have varying requirements.  The constraints are:
-- 
2.7.4

[PATCH v5 02/10] Move GET_FIELD/SET_FIELD to vas.h

[Sukadev Bhattiprolu]

Move the GET_FIELD and SET_FIELD macros to vas.h as VAS and other
users of VAS, including NX-842 can use those macros.

There is a lot of related code between the VAS/NX kernel drivers
and skiboot. For consistency switch the order of parameters in
SET_FIELD to match the order in skiboot.

Signed-off-by: Sukadev Bhattiprolu 
Reviewed-by: Dan Streetman 
---

Changelog[v3]
- Fix order of parameters in nx-842 driver.
---
 arch/powerpc/include/uapi/asm/vas.h | 8 
 drivers/crypto/nx/nx-842-powernv.c  | 7 ---
 drivers/crypto/nx/nx-842.h  | 5 -
 3 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/include/uapi/asm/vas.h 
b/arch/powerpc/include/uapi/asm/vas.h
index ddfe046..21249f5 100644
--- a/arch/powerpc/include/uapi/asm/vas.h
+++ b/arch/powerpc/include/uapi/asm/vas.h
@@ -22,4 +22,12 @@
 #define VAS_THRESH_FIFO_GT_QTR_FULL2
 #define VAS_THRESH_FIFO_GT_EIGHTH_FULL 3
 
+/*
+ * Get/Set bit fields
+ */
+#define GET_FIELD(m, v)(((v) & (m)) >> MASK_LSH(m))
+#define MASK_LSH(m)(__builtin_ffsl(m) - 1)
+#define SET_FIELD(m, v, val)   \
+   (((v) & ~(m)) | typeof(v))(val)) << MASK_LSH(m)) & (m)))
+
 #endif /* _UAPI_MISC_VAS_H */
diff --git a/drivers/crypto/nx/nx-842-powernv.c 
b/drivers/crypto/nx/nx-842-powernv.c
index 1710f80..3abb045 100644
--- a/drivers/crypto/nx/nx-842-powernv.c
+++ b/drivers/crypto/nx/nx-842-powernv.c
@@ -22,6 +22,7 @@
 
 #include 
 #include 
+#include 
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Dan Streetman ");
@@ -424,9 +425,9 @@ static int nx842_powernv_function(const unsigned char *in, 
unsigned int inlen,
 
/* set up CCW */
ccw = 0;
-   ccw = SET_FIELD(ccw, CCW_CT, nx842_ct);
-   ccw = SET_FIELD(ccw, CCW_CI_842, 0); /* use 0 for hw auto-selection */
-   ccw = SET_FIELD(ccw, CCW_FC_842, fc);
+   ccw = SET_FIELD(CCW_CT, ccw, nx842_ct);
+   ccw = SET_FIELD(CCW_CI_842, ccw, 0); /* use 0 for hw auto-selection */
+   ccw = SET_FIELD(CCW_FC_842, ccw, fc);
 
/* set up CRB's CSB addr */
csb_addr = nx842_get_pa(csb) & CRB_CSB_ADDRESS;
diff --git a/drivers/crypto/nx/nx-842.h b/drivers/crypto/nx/nx-842.h
index a4eee3b..30929bd 100644
--- a/drivers/crypto/nx/nx-842.h
+++ b/drivers/crypto/nx/nx-842.h
@@ -100,11 +100,6 @@ static inline unsigned long nx842_get_pa(void *addr)
return page_to_phys(vmalloc_to_page(addr)) + offset_in_page(addr);
 }
 
-/* Get/Set bit fields */
-#define MASK_LSH(m)(__builtin_ffsl(m) - 1)
-#define GET_FIELD(v, m)(((v) & (m)) >> MASK_LSH(m))
-#define SET_FIELD(v, m, val)   (((v) & ~(m)) | (((val) << MASK_LSH(m)) & (m)))
-
 /**
  * This provides the driver's constraints.  Different nx842 implementations
  * may have varying requirements.  The constraints are:
-- 
2.7.4

[PATCH v5 06/10] VAS: Define helpers to alloc/free windows

[Sukadev Bhattiprolu]

Define helpers to allocate/free VAS window objects. These will
be used in follow-on patches when opening/closing windows.

Signed-off-by: Sukadev Bhattiprolu 
---
 arch/powerpc/platforms/powernv/vas-window.c | 61 +
 1 file changed, 61 insertions(+)

diff --git a/arch/powerpc/platforms/powernv/vas-window.c 
b/arch/powerpc/platforms/powernv/vas-window.c
index 4135ab0..aba8d1e 100644
--- a/arch/powerpc/platforms/powernv/vas-window.c
+++ b/arch/powerpc/platforms/powernv/vas-window.c
@@ -444,6 +444,67 @@ int init_winctx_regs(struct vas_window *window, struct 
vas_winctx *winctx)
return 0;
 }
 
+DEFINE_SPINLOCK(vas_ida_lock);
+
+void vas_release_window_id(struct ida *ida, int winid)
+{
+   spin_lock(_ida_lock);
+   ida_remove(ida, winid);
+   spin_unlock(_ida_lock);
+}
+
+int vas_assign_window_id(struct ida *ida)
+{
+   int rc, winid;
+
+   rc = ida_pre_get(ida, GFP_KERNEL);
+   if (!rc)
+   return -EAGAIN;
+
+   spin_lock(_ida_lock);
+   rc = ida_get_new_above(ida, 0, );
+   spin_unlock(_ida_lock);
+
+   if (rc)
+   return rc;
+
+   if (winid > VAS_WINDOWS_PER_CHIP) {
+   pr_err("VAS: Too many (%d) open windows\n", winid);
+   vas_release_window_id(ida, winid);
+   return -EAGAIN;
+   }
+
+   return winid;
+}
+
+void vas_window_free(struct vas_window *window)
+{
+   unmap_winctx_mmio_bars(window);
+   kfree(window->paste_addr_name);
+   kfree(window);
+}
+
+struct vas_window *vas_window_alloc(struct vas_instance *vinst, int id)
+{
+   struct vas_window *window;
+
+   window = kzalloc(sizeof(*window), GFP_KERNEL);
+   if (!window)
+   return NULL;
+
+   window->vinst = vinst;
+   window->winid = id;
+
+   if (map_winctx_mmio_bars(window))
+   goto out_free;
+
+   return window;
+
+out_free:
+   kfree(window);
+   return NULL;
+}
+
 /* stub for now */
 int vas_win_close(struct vas_window *window)
 {
-- 
2.7.4

[PATCH v5 06/10] VAS: Define helpers to alloc/free windows

[Sukadev Bhattiprolu]

Define helpers to allocate/free VAS window objects. These will
be used in follow-on patches when opening/closing windows.

Signed-off-by: Sukadev Bhattiprolu 
---
 arch/powerpc/platforms/powernv/vas-window.c | 61 +
 1 file changed, 61 insertions(+)

diff --git a/arch/powerpc/platforms/powernv/vas-window.c 
b/arch/powerpc/platforms/powernv/vas-window.c
index 4135ab0..aba8d1e 100644
--- a/arch/powerpc/platforms/powernv/vas-window.c
+++ b/arch/powerpc/platforms/powernv/vas-window.c
@@ -444,6 +444,67 @@ int init_winctx_regs(struct vas_window *window, struct 
vas_winctx *winctx)
return 0;
 }
 
+DEFINE_SPINLOCK(vas_ida_lock);
+
+void vas_release_window_id(struct ida *ida, int winid)
+{
+   spin_lock(_ida_lock);
+   ida_remove(ida, winid);
+   spin_unlock(_ida_lock);
+}
+
+int vas_assign_window_id(struct ida *ida)
+{
+   int rc, winid;
+
+   rc = ida_pre_get(ida, GFP_KERNEL);
+   if (!rc)
+   return -EAGAIN;
+
+   spin_lock(_ida_lock);
+   rc = ida_get_new_above(ida, 0, );
+   spin_unlock(_ida_lock);
+
+   if (rc)
+   return rc;
+
+   if (winid > VAS_WINDOWS_PER_CHIP) {
+   pr_err("VAS: Too many (%d) open windows\n", winid);
+   vas_release_window_id(ida, winid);
+   return -EAGAIN;
+   }
+
+   return winid;
+}
+
+void vas_window_free(struct vas_window *window)
+{
+   unmap_winctx_mmio_bars(window);
+   kfree(window->paste_addr_name);
+   kfree(window);
+}
+
+struct vas_window *vas_window_alloc(struct vas_instance *vinst, int id)
+{
+   struct vas_window *window;
+
+   window = kzalloc(sizeof(*window), GFP_KERNEL);
+   if (!window)
+   return NULL;
+
+   window->vinst = vinst;
+   window->winid = id;
+
+   if (map_winctx_mmio_bars(window))
+   goto out_free;
+
+   return window;
+
+out_free:
+   kfree(window);
+   return NULL;
+}
+
 /* stub for now */
 int vas_win_close(struct vas_window *window)
 {
-- 
2.7.4

[PATCH v5 08/10] VAS: Define vas_win_close() interface

[Sukadev Bhattiprolu]

Define the vas_win_close() interface which should be used to close a
send or receive windows.

While the hardware configurations required to open send and receive windows
differ, the configuration to close a window is the same for both. So we use
a single interface to close the window.

Signed-off-by: Sukadev Bhattiprolu 
---
Changelog[v4]:
- Drop the poll for credits return (we can set the required credit,
  but cannot really find the available credit at a point in time)
- Export the symbol

Changelog[v3]:
- Fix order of parameters in GET_FIELD().
- Update references and sequence for closing/quiescing a window.
---
 arch/powerpc/include/asm/vas.h  |  7 +++
 arch/powerpc/platforms/powernv/vas-window.c | 97 +++--
 2 files changed, 100 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
index 09ea6f7..c923b8f 100644
--- a/arch/powerpc/include/asm/vas.h
+++ b/arch/powerpc/include/asm/vas.h
@@ -76,4 +76,11 @@ extern void vas_init_rx_win_attr(struct vas_rx_win_attr 
*rxattr,
 extern struct vas_window *vas_rx_win_open(int vasid, enum vas_cop_type cop,
struct vas_rx_win_attr *attr);
 
+/*
+ * Close the send or receive window identified by @win. For receive windows
+ * return -EAGAIN if there are active send windows attached to this receive
+ * window.
+ */
+int vas_win_close(struct vas_window *win);
+
 #endif /* _MISC_VAS_H */
diff --git a/arch/powerpc/platforms/powernv/vas-window.c 
b/arch/powerpc/platforms/powernv/vas-window.c
index 2cc9850..caacc28 100644
--- a/arch/powerpc/platforms/powernv/vas-window.c
+++ b/arch/powerpc/platforms/powernv/vas-window.c
@@ -477,7 +477,7 @@ int vas_assign_window_id(struct ida *ida)
return winid;
 }
 
-void vas_window_free(struct vas_window *window)
+static void vas_window_free(struct vas_window *window)
 {
unmap_winctx_mmio_bars(window);
kfree(window->paste_addr_name);
@@ -505,10 +505,12 @@ static struct vas_window *vas_window_alloc(struct 
vas_instance *vinst, int id)
return NULL;
 }
 
-/* stub for now */
-int vas_win_close(struct vas_window *window)
+static void put_rx_win(struct vas_window *rxwin)
 {
-   return -1;
+   /* Better not be a send window! */
+   WARN_ON_ONCE(rxwin->tx_win);
+
+   atomic_dec(>num_txwins);
 }
 
 struct vas_window *get_vinstance_rxwin(struct vas_instance *vinst,
@@ -715,3 +717,90 @@ struct vas_window *vas_rx_win_open(int vasid, enum 
vas_cop_type cop,
return ERR_PTR(rc);
 }
 EXPORT_SYMBOL_GPL(vas_rx_win_open);
+
+static void poll_window_busy_state(struct vas_window *window)
+{
+   int busy;
+   uint64_t val;
+
+retry:
+   /*
+* Poll Window Busy flag
+*/
+   val = read_hvwc_reg(window, VREG(WIN_STATUS));
+   busy = GET_FIELD(VAS_WIN_BUSY, val);
+   if (busy) {
+   val = 0;
+   schedule_timeout(2000);
+   goto retry;
+   }
+}
+
+static void poll_window_castout(struct vas_window *window)
+{
+   int cached;
+   uint64_t val;
+
+   /* Cast window context out of the cache */
+retry:
+   val = read_hvwc_reg(window, VREG(WIN_CTX_CACHING_CTL));
+   cached = GET_FIELD(VAS_WIN_CACHE_STATUS, val);
+   if (cached) {
+   val = 0ULL;
+   val = SET_FIELD(VAS_CASTOUT_REQ, val, 1);
+   val = SET_FIELD(VAS_PUSH_TO_MEM, val, 0);
+   write_hvwc_reg(window, VREG(WIN_CTX_CACHING_CTL), val);
+
+   schedule_timeout(2000);
+   goto retry;
+   }
+}
+
+/*
+ * Close a window.
+ *
+ * See Section 1.12.1 of VAS workbook v1.05 for details on closing window:
+ * - disable new paste operations (unmap paste address)
+ * - Poll for the "Window Busy" bit to be cleared
+ * - Clear the Open/Enable bit for the Window.
+ * - Poll for return of window Credits (implies FIFO empty for Rx win?)
+ * - Unpin and cast window context out of cache
+ *
+ * Besides the hardware, kernel has some bookkeeping of course.
+ */
+int vas_win_close(struct vas_window *window)
+{
+   uint64_t val;
+
+   if (!window)
+   return 0;
+
+   if (!window->tx_win && atomic_read(>num_txwins) != 0) {
+   pr_devel("VAS: Attempting to close an active Rx window!\n");
+   WARN_ON_ONCE(1);
+   return -EAGAIN;
+   }
+
+   unmap_winctx_paste_kaddr(window);
+
+   poll_window_busy_state(window);
+
+   /* Unpin window from cache and close it */
+   val = read_hvwc_reg(window, VREG(WINCTL));
+   val = SET_FIELD(VAS_WINCTL_PIN, val, 0);
+   val = SET_FIELD(VAS_WINCTL_OPEN, val, 0);
+   write_hvwc_reg(window, VREG(WINCTL), val);
+
+   poll_window_castout(window);
+
+   /* if send window, drop reference to matching receive window */
+   if (window->tx_win)
+   put_rx_win(window->rxwin);

[PATCH v5 08/10] VAS: Define vas_win_close() interface

[Sukadev Bhattiprolu]

Define the vas_win_close() interface which should be used to close a
send or receive windows.

While the hardware configurations required to open send and receive windows
differ, the configuration to close a window is the same for both. So we use
a single interface to close the window.

Signed-off-by: Sukadev Bhattiprolu 
---
Changelog[v4]:
- Drop the poll for credits return (we can set the required credit,
  but cannot really find the available credit at a point in time)
- Export the symbol

Changelog[v3]:
- Fix order of parameters in GET_FIELD().
- Update references and sequence for closing/quiescing a window.
---
 arch/powerpc/include/asm/vas.h  |  7 +++
 arch/powerpc/platforms/powernv/vas-window.c | 97 +++--
 2 files changed, 100 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
index 09ea6f7..c923b8f 100644
--- a/arch/powerpc/include/asm/vas.h
+++ b/arch/powerpc/include/asm/vas.h
@@ -76,4 +76,11 @@ extern void vas_init_rx_win_attr(struct vas_rx_win_attr 
*rxattr,
 extern struct vas_window *vas_rx_win_open(int vasid, enum vas_cop_type cop,
struct vas_rx_win_attr *attr);
 
+/*
+ * Close the send or receive window identified by @win. For receive windows
+ * return -EAGAIN if there are active send windows attached to this receive
+ * window.
+ */
+int vas_win_close(struct vas_window *win);
+
 #endif /* _MISC_VAS_H */
diff --git a/arch/powerpc/platforms/powernv/vas-window.c 
b/arch/powerpc/platforms/powernv/vas-window.c
index 2cc9850..caacc28 100644
--- a/arch/powerpc/platforms/powernv/vas-window.c
+++ b/arch/powerpc/platforms/powernv/vas-window.c
@@ -477,7 +477,7 @@ int vas_assign_window_id(struct ida *ida)
return winid;
 }
 
-void vas_window_free(struct vas_window *window)
+static void vas_window_free(struct vas_window *window)
 {
unmap_winctx_mmio_bars(window);
kfree(window->paste_addr_name);
@@ -505,10 +505,12 @@ static struct vas_window *vas_window_alloc(struct 
vas_instance *vinst, int id)
return NULL;
 }
 
-/* stub for now */
-int vas_win_close(struct vas_window *window)
+static void put_rx_win(struct vas_window *rxwin)
 {
-   return -1;
+   /* Better not be a send window! */
+   WARN_ON_ONCE(rxwin->tx_win);
+
+   atomic_dec(>num_txwins);
 }
 
 struct vas_window *get_vinstance_rxwin(struct vas_instance *vinst,
@@ -715,3 +717,90 @@ struct vas_window *vas_rx_win_open(int vasid, enum 
vas_cop_type cop,
return ERR_PTR(rc);
 }
 EXPORT_SYMBOL_GPL(vas_rx_win_open);
+
+static void poll_window_busy_state(struct vas_window *window)
+{
+   int busy;
+   uint64_t val;
+
+retry:
+   /*
+* Poll Window Busy flag
+*/
+   val = read_hvwc_reg(window, VREG(WIN_STATUS));
+   busy = GET_FIELD(VAS_WIN_BUSY, val);
+   if (busy) {
+   val = 0;
+   schedule_timeout(2000);
+   goto retry;
+   }
+}
+
+static void poll_window_castout(struct vas_window *window)
+{
+   int cached;
+   uint64_t val;
+
+   /* Cast window context out of the cache */
+retry:
+   val = read_hvwc_reg(window, VREG(WIN_CTX_CACHING_CTL));
+   cached = GET_FIELD(VAS_WIN_CACHE_STATUS, val);
+   if (cached) {
+   val = 0ULL;
+   val = SET_FIELD(VAS_CASTOUT_REQ, val, 1);
+   val = SET_FIELD(VAS_PUSH_TO_MEM, val, 0);
+   write_hvwc_reg(window, VREG(WIN_CTX_CACHING_CTL), val);
+
+   schedule_timeout(2000);
+   goto retry;
+   }
+}
+
+/*
+ * Close a window.
+ *
+ * See Section 1.12.1 of VAS workbook v1.05 for details on closing window:
+ * - disable new paste operations (unmap paste address)
+ * - Poll for the "Window Busy" bit to be cleared
+ * - Clear the Open/Enable bit for the Window.
+ * - Poll for return of window Credits (implies FIFO empty for Rx win?)
+ * - Unpin and cast window context out of cache
+ *
+ * Besides the hardware, kernel has some bookkeeping of course.
+ */
+int vas_win_close(struct vas_window *window)
+{
+   uint64_t val;
+
+   if (!window)
+   return 0;
+
+   if (!window->tx_win && atomic_read(>num_txwins) != 0) {
+   pr_devel("VAS: Attempting to close an active Rx window!\n");
+   WARN_ON_ONCE(1);
+   return -EAGAIN;
+   }
+
+   unmap_winctx_paste_kaddr(window);
+
+   poll_window_busy_state(window);
+
+   /* Unpin window from cache and close it */
+   val = read_hvwc_reg(window, VREG(WINCTL));
+   val = SET_FIELD(VAS_WINCTL_PIN, val, 0);
+   val = SET_FIELD(VAS_WINCTL_OPEN, val, 0);
+   write_hvwc_reg(window, VREG(WINCTL), val);
+
+   poll_window_castout(window);
+
+   /* if send window, drop reference to matching receive window */
+   if (window->tx_win)
+   put_rx_win(window->rxwin);
+
+   

[PATCH v5 10/10] VAS: Define copy/paste interfaces

[Sukadev Bhattiprolu]

Define interfaces (wrappers) to the 'copy' and 'paste' instructions
(which are new in PowerISA 3.0). These are intended to be used to
by NX driver(s) to submit Coprocessor Request Blocks (CRBs) to the
NX hardware engines.

Signed-off-by: Sukadev Bhattiprolu 

---
Changelog[v4]
- Export symbols
Changelog[v3]
- Map raw CR value from paste instruction into an error code.
---
 arch/powerpc/include/asm/vas.h  | 13 +
 arch/powerpc/platforms/powernv/copy-paste.h | 74 +
 arch/powerpc/platforms/powernv/vas-window.c | 52 
 arch/powerpc/platforms/powernv/vas.h| 14 ++
 4 files changed, 153 insertions(+)
 create mode 100644 arch/powerpc/platforms/powernv/copy-paste.h

diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
index 944bb4b..4e5a470 100644
--- a/arch/powerpc/include/asm/vas.h
+++ b/arch/powerpc/include/asm/vas.h
@@ -125,4 +125,17 @@ struct vas_window *vas_tx_win_open(int vasid, enum 
vas_cop_type cop,
  */
 int vas_win_close(struct vas_window *win);
 
+/*
+ * Copy the co-processor request block (CRB) @crb into the local L2 cache.
+ * For now, @offset must be 0 and @first must be true.
+ */
+extern int vas_copy_crb(void *crb, int offset, bool first);
+
+/*
+ * Paste a previously copied CRB (see vas_copy_crb()) from the L2 cache to
+ * the hardware address associated with the window @win. For now, @off must
+ * 0 and @last must be true. @re is expected/assumed to be true for NX windows.
+ */
+extern int vas_paste_crb(struct vas_window *win, int off, bool last, bool re);
+
 #endif /* _MISC_VAS_H */
diff --git a/arch/powerpc/platforms/powernv/copy-paste.h 
b/arch/powerpc/platforms/powernv/copy-paste.h
new file mode 100644
index 000..7783bb8
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/copy-paste.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2016 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/*
+ * Macros taken from tools/testing/selftests/powerpc/context_switch/cp_abort.c
+ */
+#define PASTE(RA, RB, L, RC) \
+   .long (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) \
+ | (L) << (31-10) | (RC) << (31-31))
+
+#define COPY(RA, RB, L) \
+   .long (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) \
+ | (L) << (31-10))
+
+#define CR0_FXM"0x80"
+#define CR0_SHIFT  28
+#define CR0_MASK   0xF
+/*
+ * Copy/paste instructions:
+ *
+ * copy RA,RB,L
+ * Copy contents of address (RA) + effective_address(RB)
+ * to internal copy-buffer.
+ *
+ * L == 1 indicates this is the first copy.
+ *
+ * L == 0 indicates its a continuation of a prior first copy.
+ *
+ * paste RA,RB,L
+ * Paste contents of internal copy-buffer to the address
+ * (RA) + effective_address(RB)
+ *
+ * L == 0 indicates its a continuation of a prior paste. i.e.
+ * don't wait for the completion or update status.
+ *
+ * L == 1 indicates this is the last paste in the group (i.e.
+ * wait for the group to complete and update status in CR0).
+ *
+ * For Power9, the L bit must be 'true' in both copy and paste.
+ */
+
+static inline int vas_copy(void *crb, int offset, int first)
+{
+   WARN_ON_ONCE(!first);
+
+   __asm__ __volatile(stringify_in_c(COPY(%0, %1, %2))";"
+   :
+   : "b" (offset), "b" (crb), "i" (1)
+   : "memory");
+
+   return 0;
+}
+
+static inline int vas_paste(void *paste_address, int offset, int last)
+{
+   unsigned long long cr;
+
+   WARN_ON_ONCE(!last);
+
+   cr = 0;
+   __asm__ __volatile(stringify_in_c(PASTE(%1, %2, 1, 1))";"
+   "mfocrf %0," CR0_FXM ";"
+   : "=r" (cr)
+   : "b" (paste_address), "b" (offset)
+   : "memory");
+
+   return cr;
+}
diff --git a/arch/powerpc/platforms/powernv/vas-window.c 
b/arch/powerpc/platforms/powernv/vas-window.c
index 4a4fd68..06e9c39 100644
--- a/arch/powerpc/platforms/powernv/vas-window.c
+++ b/arch/powerpc/platforms/powernv/vas-window.c
@@ -14,6 +14,7 @@
 #include 
 
 #include "vas.h"
+#include "copy-paste.h"
 
 static int fault_winid;
 
@@ -901,6 +902,57 @@ struct vas_window *vas_tx_win_open(int vasid, enum 
vas_cop_type cop,
 }
 EXPORT_SYMBOL_GPL(vas_tx_win_open);
 
+int vas_copy_crb(void *crb, int offset, bool first)
+{
+   if (!vas_initialized())
+   return -1;
+
+   return vas_copy(crb, offset, first);
+}
+EXPORT_SYMBOL_GPL(vas_copy_crb);
+
+#define RMA_LSMP_REPORT_ENABLE PPC_BIT(53)
+int vas_paste_crb(struct vas_window *txwin, int offset, bool last, bool re)
+{
+   int rc;
+   

[PATCH v5 09/10] VAS: Define vas_tx_win_open()

[Sukadev Bhattiprolu]

Define an interface to open a VAS send window. This interface is
intended to be used the Nest Accelerator (NX) driver(s) to open
a send window and use it to submit compression/encryption requests
to a VAS receive window.

The receive window, identified by the [vasid, cop] parameters, must
already be open in VAS (i.e connected to an NX engine).

Signed-off-by: Sukadev Bhattiprolu 

---
Changelog[v5]:
- [Ben Herrenschmidt] MMIO regions must be mapped non-cached and
  paste regions must be mapped cached. Define/use map_paste_region().

Changelog [v3]:
- Distinguish between hardware PID (SPRN_PID) and Linux pid.
- Use macros rather than enum for threshold-control mode
- Set the pid of send window from attr (needed for user space
  send windows).
- Ignore irq port setting for now. They are needed for user space
  windows and will be added later
---
 arch/powerpc/include/asm/vas.h  |  42 +++
 arch/powerpc/platforms/powernv/vas-window.c | 183 
 2 files changed, 225 insertions(+)

diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
index c923b8f..944bb4b 100644
--- a/arch/powerpc/include/asm/vas.h
+++ b/arch/powerpc/include/asm/vas.h
@@ -61,6 +61,29 @@ struct vas_rx_win_attr {
 };
 
 /*
+ * Window attributes specified by the in-kernel owner of a send window.
+ */
+struct vas_tx_win_attr {
+   enum vas_cop_type cop;
+   int wcreds_max;
+   int lpid;
+   int pidr;   /* hardware PID (from SPRN_PID) */
+   int pid;/* linux process id */
+   int pswid;
+   int rsvd_txbuf_count;
+   int tc_mode;
+
+   bool user_win;
+   bool pin_win;
+   bool rej_no_credit;
+   bool rsvd_txbuf_enable;
+   bool tx_wcred_mode;
+   bool rx_wcred_mode;
+   bool tx_win_ord_mode;
+   bool rx_win_ord_mode;
+};
+
+/*
  * Helper to initialize receive window attributes to defaults for an
  * NX window.
  */
@@ -77,6 +100,25 @@ extern struct vas_window *vas_rx_win_open(int vasid, enum 
vas_cop_type cop,
struct vas_rx_win_attr *attr);
 
 /*
+ * Helper to initialize send window attributes to defaults for an NX window.
+ */
+extern void vas_init_tx_win_attr(struct vas_tx_win_attr *txattr,
+   enum vas_cop_type cop);
+
+/*
+ * Open a VAS send window for the instance of VAS identified by @vasid
+ * and the co-processor type @cop. Use @attr to initialize attributes
+ * of the window.
+ *
+ * Note: The instance of VAS must already have an open receive window for
+ * the coprocessor type @cop.
+ *
+ * Return a handle to the send window or ERR_PTR() on error.
+ */
+struct vas_window *vas_tx_win_open(int vasid, enum vas_cop_type cop,
+   struct vas_tx_win_attr *attr);
+
+/*
  * Close the send or receive window identified by @win. For receive windows
  * return -EAGAIN if there are active send windows attached to this receive
  * window.
diff --git a/arch/powerpc/platforms/powernv/vas-window.c 
b/arch/powerpc/platforms/powernv/vas-window.c
index caacc28..4a4fd68 100644
--- a/arch/powerpc/platforms/powernv/vas-window.c
+++ b/arch/powerpc/platforms/powernv/vas-window.c
@@ -56,6 +56,30 @@ static inline void get_uwc_mmio_bar(struct vas_window 
*window,
*len = VAS_UWC_SIZE;
 }
 
+/*
+ * Unlike MMIO regions (map_mmio_region() below), paste region must be mapped
+ * cache-able.
+ */
+static void *map_paste_region(char *name, uint64_t start, int len)
+{
+   void *map;
+
+   if (!request_mem_region(start, len, name)) {
+   pr_devel("%s(): request_mem_region(0x%llx, %d) failed\n",
+   __func__, start, len);
+   return NULL;
+   }
+
+   map = __ioremap(start, len, pgprot_val(pgprot_cached(__pgprot(0;
+   if (!map) {
+   pr_devel("%s(): ioremap(0x%llx, %d) failed\n", __func__, start,
+   len);
+   return NULL;
+   }
+
+   return map;
+}
+
 static void *map_mmio_region(char *name, uint64_t start, int len)
 {
void *map;
@@ -718,6 +742,165 @@ struct vas_window *vas_rx_win_open(int vasid, enum 
vas_cop_type cop,
 }
 EXPORT_SYMBOL_GPL(vas_rx_win_open);
 
+void vas_init_tx_win_attr(struct vas_tx_win_attr *txattr, enum vas_cop_type 
cop)
+{
+   memset(txattr, 0, sizeof(*txattr));
+
+   if (cop == VAS_COP_TYPE_842 || cop == VAS_COP_TYPE_842_HIPRI) {
+   txattr->rej_no_credit = false;
+   txattr->rx_wcred_mode = true;
+   txattr->tx_wcred_mode = true;
+   txattr->rx_win_ord_mode = true;
+   txattr->tx_win_ord_mode = true;
+   }
+}
+EXPORT_SYMBOL_GPL(vas_init_tx_win_attr);
+
+static void init_winctx_for_txwin(struct vas_window *txwin,
+   struct vas_tx_win_attr *txattr,
+   struct vas_winctx *winctx)
+{
+ 

[PATCH v5 10/10] VAS: Define copy/paste interfaces

[Sukadev Bhattiprolu]

Define interfaces (wrappers) to the 'copy' and 'paste' instructions
(which are new in PowerISA 3.0). These are intended to be used to
by NX driver(s) to submit Coprocessor Request Blocks (CRBs) to the
NX hardware engines.

Signed-off-by: Sukadev Bhattiprolu 

---
Changelog[v4]
- Export symbols
Changelog[v3]
- Map raw CR value from paste instruction into an error code.
---
 arch/powerpc/include/asm/vas.h  | 13 +
 arch/powerpc/platforms/powernv/copy-paste.h | 74 +
 arch/powerpc/platforms/powernv/vas-window.c | 52 
 arch/powerpc/platforms/powernv/vas.h| 14 ++
 4 files changed, 153 insertions(+)
 create mode 100644 arch/powerpc/platforms/powernv/copy-paste.h

diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
index 944bb4b..4e5a470 100644
--- a/arch/powerpc/include/asm/vas.h
+++ b/arch/powerpc/include/asm/vas.h
@@ -125,4 +125,17 @@ struct vas_window *vas_tx_win_open(int vasid, enum 
vas_cop_type cop,
  */
 int vas_win_close(struct vas_window *win);
 
+/*
+ * Copy the co-processor request block (CRB) @crb into the local L2 cache.
+ * For now, @offset must be 0 and @first must be true.
+ */
+extern int vas_copy_crb(void *crb, int offset, bool first);
+
+/*
+ * Paste a previously copied CRB (see vas_copy_crb()) from the L2 cache to
+ * the hardware address associated with the window @win. For now, @off must
+ * 0 and @last must be true. @re is expected/assumed to be true for NX windows.
+ */
+extern int vas_paste_crb(struct vas_window *win, int off, bool last, bool re);
+
 #endif /* _MISC_VAS_H */
diff --git a/arch/powerpc/platforms/powernv/copy-paste.h 
b/arch/powerpc/platforms/powernv/copy-paste.h
new file mode 100644
index 000..7783bb8
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/copy-paste.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright 2016 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/*
+ * Macros taken from tools/testing/selftests/powerpc/context_switch/cp_abort.c
+ */
+#define PASTE(RA, RB, L, RC) \
+   .long (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) \
+ | (L) << (31-10) | (RC) << (31-31))
+
+#define COPY(RA, RB, L) \
+   .long (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) \
+ | (L) << (31-10))
+
+#define CR0_FXM"0x80"
+#define CR0_SHIFT  28
+#define CR0_MASK   0xF
+/*
+ * Copy/paste instructions:
+ *
+ * copy RA,RB,L
+ * Copy contents of address (RA) + effective_address(RB)
+ * to internal copy-buffer.
+ *
+ * L == 1 indicates this is the first copy.
+ *
+ * L == 0 indicates its a continuation of a prior first copy.
+ *
+ * paste RA,RB,L
+ * Paste contents of internal copy-buffer to the address
+ * (RA) + effective_address(RB)
+ *
+ * L == 0 indicates its a continuation of a prior paste. i.e.
+ * don't wait for the completion or update status.
+ *
+ * L == 1 indicates this is the last paste in the group (i.e.
+ * wait for the group to complete and update status in CR0).
+ *
+ * For Power9, the L bit must be 'true' in both copy and paste.
+ */
+
+static inline int vas_copy(void *crb, int offset, int first)
+{
+   WARN_ON_ONCE(!first);
+
+   __asm__ __volatile(stringify_in_c(COPY(%0, %1, %2))";"
+   :
+   : "b" (offset), "b" (crb), "i" (1)
+   : "memory");
+
+   return 0;
+}
+
+static inline int vas_paste(void *paste_address, int offset, int last)
+{
+   unsigned long long cr;
+
+   WARN_ON_ONCE(!last);
+
+   cr = 0;
+   __asm__ __volatile(stringify_in_c(PASTE(%1, %2, 1, 1))";"
+   "mfocrf %0," CR0_FXM ";"
+   : "=r" (cr)
+   : "b" (paste_address), "b" (offset)
+   : "memory");
+
+   return cr;
+}
diff --git a/arch/powerpc/platforms/powernv/vas-window.c 
b/arch/powerpc/platforms/powernv/vas-window.c
index 4a4fd68..06e9c39 100644
--- a/arch/powerpc/platforms/powernv/vas-window.c
+++ b/arch/powerpc/platforms/powernv/vas-window.c
@@ -14,6 +14,7 @@
 #include 
 
 #include "vas.h"
+#include "copy-paste.h"
 
 static int fault_winid;
 
@@ -901,6 +902,57 @@ struct vas_window *vas_tx_win_open(int vasid, enum 
vas_cop_type cop,
 }
 EXPORT_SYMBOL_GPL(vas_tx_win_open);
 
+int vas_copy_crb(void *crb, int offset, bool first)
+{
+   if (!vas_initialized())
+   return -1;
+
+   return vas_copy(crb, offset, first);
+}
+EXPORT_SYMBOL_GPL(vas_copy_crb);
+
+#define RMA_LSMP_REPORT_ENABLE PPC_BIT(53)
+int vas_paste_crb(struct vas_window *txwin, int offset, bool last, bool re)
+{
+   int rc;
+   uint64_t val;
+   void 

[PATCH v5 09/10] VAS: Define vas_tx_win_open()

[Sukadev Bhattiprolu]

Define an interface to open a VAS send window. This interface is
intended to be used the Nest Accelerator (NX) driver(s) to open
a send window and use it to submit compression/encryption requests
to a VAS receive window.

The receive window, identified by the [vasid, cop] parameters, must
already be open in VAS (i.e connected to an NX engine).

Signed-off-by: Sukadev Bhattiprolu 

---
Changelog[v5]:
- [Ben Herrenschmidt] MMIO regions must be mapped non-cached and
  paste regions must be mapped cached. Define/use map_paste_region().

Changelog [v3]:
- Distinguish between hardware PID (SPRN_PID) and Linux pid.
- Use macros rather than enum for threshold-control mode
- Set the pid of send window from attr (needed for user space
  send windows).
- Ignore irq port setting for now. They are needed for user space
  windows and will be added later
---
 arch/powerpc/include/asm/vas.h  |  42 +++
 arch/powerpc/platforms/powernv/vas-window.c | 183 
 2 files changed, 225 insertions(+)

diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
index c923b8f..944bb4b 100644
--- a/arch/powerpc/include/asm/vas.h
+++ b/arch/powerpc/include/asm/vas.h
@@ -61,6 +61,29 @@ struct vas_rx_win_attr {
 };
 
 /*
+ * Window attributes specified by the in-kernel owner of a send window.
+ */
+struct vas_tx_win_attr {
+   enum vas_cop_type cop;
+   int wcreds_max;
+   int lpid;
+   int pidr;   /* hardware PID (from SPRN_PID) */
+   int pid;/* linux process id */
+   int pswid;
+   int rsvd_txbuf_count;
+   int tc_mode;
+
+   bool user_win;
+   bool pin_win;
+   bool rej_no_credit;
+   bool rsvd_txbuf_enable;
+   bool tx_wcred_mode;
+   bool rx_wcred_mode;
+   bool tx_win_ord_mode;
+   bool rx_win_ord_mode;
+};
+
+/*
  * Helper to initialize receive window attributes to defaults for an
  * NX window.
  */
@@ -77,6 +100,25 @@ extern struct vas_window *vas_rx_win_open(int vasid, enum 
vas_cop_type cop,
struct vas_rx_win_attr *attr);
 
 /*
+ * Helper to initialize send window attributes to defaults for an NX window.
+ */
+extern void vas_init_tx_win_attr(struct vas_tx_win_attr *txattr,
+   enum vas_cop_type cop);
+
+/*
+ * Open a VAS send window for the instance of VAS identified by @vasid
+ * and the co-processor type @cop. Use @attr to initialize attributes
+ * of the window.
+ *
+ * Note: The instance of VAS must already have an open receive window for
+ * the coprocessor type @cop.
+ *
+ * Return a handle to the send window or ERR_PTR() on error.
+ */
+struct vas_window *vas_tx_win_open(int vasid, enum vas_cop_type cop,
+   struct vas_tx_win_attr *attr);
+
+/*
  * Close the send or receive window identified by @win. For receive windows
  * return -EAGAIN if there are active send windows attached to this receive
  * window.
diff --git a/arch/powerpc/platforms/powernv/vas-window.c 
b/arch/powerpc/platforms/powernv/vas-window.c
index caacc28..4a4fd68 100644
--- a/arch/powerpc/platforms/powernv/vas-window.c
+++ b/arch/powerpc/platforms/powernv/vas-window.c
@@ -56,6 +56,30 @@ static inline void get_uwc_mmio_bar(struct vas_window 
*window,
*len = VAS_UWC_SIZE;
 }
 
+/*
+ * Unlike MMIO regions (map_mmio_region() below), paste region must be mapped
+ * cache-able.
+ */
+static void *map_paste_region(char *name, uint64_t start, int len)
+{
+   void *map;
+
+   if (!request_mem_region(start, len, name)) {
+   pr_devel("%s(): request_mem_region(0x%llx, %d) failed\n",
+   __func__, start, len);
+   return NULL;
+   }
+
+   map = __ioremap(start, len, pgprot_val(pgprot_cached(__pgprot(0;
+   if (!map) {
+   pr_devel("%s(): ioremap(0x%llx, %d) failed\n", __func__, start,
+   len);
+   return NULL;
+   }
+
+   return map;
+}
+
 static void *map_mmio_region(char *name, uint64_t start, int len)
 {
void *map;
@@ -718,6 +742,165 @@ struct vas_window *vas_rx_win_open(int vasid, enum 
vas_cop_type cop,
 }
 EXPORT_SYMBOL_GPL(vas_rx_win_open);
 
+void vas_init_tx_win_attr(struct vas_tx_win_attr *txattr, enum vas_cop_type 
cop)
+{
+   memset(txattr, 0, sizeof(*txattr));
+
+   if (cop == VAS_COP_TYPE_842 || cop == VAS_COP_TYPE_842_HIPRI) {
+   txattr->rej_no_credit = false;
+   txattr->rx_wcred_mode = true;
+   txattr->tx_wcred_mode = true;
+   txattr->rx_win_ord_mode = true;
+   txattr->tx_win_ord_mode = true;
+   }
+}
+EXPORT_SYMBOL_GPL(vas_init_tx_win_attr);
+
+static void init_winctx_for_txwin(struct vas_window *txwin,
+   struct vas_tx_win_attr *txattr,
+   struct vas_winctx *winctx)
+{
+   /*
+* We first 

[PATCH v5 05/10] VAS: Define helpers to init window context

[Sukadev Bhattiprolu]

Define helpers to initialize window context registers of the VAS
hardware. These will be used in follow-on patches when opening/closing
VAS windows.

Signed-off-by: Sukadev Bhattiprolu 
---
Changelog[v5]
- Fix: Copy the FIFO address into LFIFO_BAR register as is (don't
  shift address into bits 8:53).

Changelog[v4]
- Michael Neuling] Use ilog2(), radix_enabled() helpers;
  drop warning when 32-bit app uses VAS (a follow-on patch
  will check and return error). Set MSR_PR state to 0 for
  kernel (rather than reading from MSR).

Changelog[v3]
- Have caller, rather than init_xlate_regs() reset window regs
  so we don't reset any settings caller may already have set.
- Translation mode should be 0x3 (0b11) not 0x11.
- Skip initilaizing read-only registers NX_UTIL and NX_UTIL_SE
- Skip initializing adder registers from UWC - they are already
  initialized from the HVWC.
- Check winctx->user_win when setting translation registers
---
 arch/powerpc/platforms/powernv/vas-window.c | 306 
 arch/powerpc/platforms/powernv/vas.h|  55 +
 2 files changed, 361 insertions(+)

diff --git a/arch/powerpc/platforms/powernv/vas-window.c 
b/arch/powerpc/platforms/powernv/vas-window.c
index 588aad7..4135ab0 100644
--- a/arch/powerpc/platforms/powernv/vas-window.c
+++ b/arch/powerpc/platforms/powernv/vas-window.c
@@ -11,9 +11,12 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "vas.h"
 
+static int fault_winid;
+
 /*
  * Compute the paste address region for the window @window using the
  * ->paste_base_addr and ->paste_win_id_shift we got from device tree.
@@ -138,6 +141,309 @@ int map_winctx_mmio_bars(struct vas_window *window)
return 0;
 }
 
+/*
+ * Reset all valid registers in the HV and OS/User Window Contexts for
+ * the window identified by @window.
+ *
+ * NOTE: We cannot really use a for loop to reset window context. Not all
+ *  offsets in a window context are valid registers and the valid
+ *  registers are not sequential. And, we can only write to offsets
+ *  with valid registers (or is that only in Simics?).
+ */
+void reset_window_regs(struct vas_window *window)
+{
+   write_hvwc_reg(window, VREG(LPID), 0ULL);
+   write_hvwc_reg(window, VREG(PID), 0ULL);
+   write_hvwc_reg(window, VREG(XLATE_MSR), 0ULL);
+   write_hvwc_reg(window, VREG(XLATE_LPCR), 0ULL);
+   write_hvwc_reg(window, VREG(XLATE_CTL), 0ULL);
+   write_hvwc_reg(window, VREG(AMR), 0ULL);
+   write_hvwc_reg(window, VREG(SEIDR), 0ULL);
+   write_hvwc_reg(window, VREG(FAULT_TX_WIN), 0ULL);
+   write_hvwc_reg(window, VREG(OSU_INTR_SRC_RA), 0ULL);
+   write_hvwc_reg(window, VREG(HV_INTR_SRC_RA), 0ULL);
+   write_hvwc_reg(window, VREG(PSWID), 0ULL);
+   write_hvwc_reg(window, VREG(SPARE1), 0ULL);
+   write_hvwc_reg(window, VREG(SPARE2), 0ULL);
+   write_hvwc_reg(window, VREG(SPARE3), 0ULL);
+   write_hvwc_reg(window, VREG(SPARE4), 0ULL);
+   write_hvwc_reg(window, VREG(SPARE5), 0ULL);
+   write_hvwc_reg(window, VREG(SPARE6), 0ULL);
+   write_hvwc_reg(window, VREG(LFIFO_BAR), 0ULL);
+   write_hvwc_reg(window, VREG(LDATA_STAMP_CTL), 0ULL);
+   write_hvwc_reg(window, VREG(LDMA_CACHE_CTL), 0ULL);
+   write_hvwc_reg(window, VREG(LRFIFO_PUSH), 0ULL);
+   write_hvwc_reg(window, VREG(CURR_MSG_COUNT), 0ULL);
+   write_hvwc_reg(window, VREG(LNOTIFY_AFTER_COUNT), 0ULL);
+   write_hvwc_reg(window, VREG(LRX_WCRED), 0ULL);
+   write_hvwc_reg(window, VREG(LRX_WCRED_ADDER), 0ULL);
+   write_hvwc_reg(window, VREG(TX_WCRED), 0ULL);
+   write_hvwc_reg(window, VREG(TX_WCRED_ADDER), 0ULL);
+   write_hvwc_reg(window, VREG(LFIFO_SIZE), 0ULL);
+   write_hvwc_reg(window, VREG(WINCTL), 0ULL);
+   write_hvwc_reg(window, VREG(WIN_STATUS), 0ULL);
+   write_hvwc_reg(window, VREG(WIN_CTX_CACHING_CTL), 0ULL);
+   write_hvwc_reg(window, VREG(TX_RSVD_BUF_COUNT), 0ULL);
+   write_hvwc_reg(window, VREG(LRFIFO_WIN_PTR), 0ULL);
+   write_hvwc_reg(window, VREG(LNOTIFY_CTL), 0ULL);
+   write_hvwc_reg(window, VREG(LNOTIFY_PID), 0ULL);
+   write_hvwc_reg(window, VREG(LNOTIFY_LPID), 0ULL);
+   write_hvwc_reg(window, VREG(LNOTIFY_TID), 0ULL);
+   write_hvwc_reg(window, VREG(LNOTIFY_SCOPE), 0ULL);
+   write_hvwc_reg(window, VREG(NX_UTIL_ADDER), 0ULL);
+
+   /* Skip read-only registers: NX_UTIL and NX_UTIL_SE */
+
+   /*
+* The send and receive window credit adder registers are also
+* accessible from HVWC and have been initialized above. We don't
+* need to initialize from the OS/User Window Context, so skip
+* following calls:
+*
+*  write_uwc_reg(window, VREG(TX_WCRED_ADDER), 0ULL);
+*  write_uwc_reg(window, VREG(LRX_WCRED_ADDER), 0ULL);
+*/
+}
+
+/*
+ * Initialize window 

[PATCH v5 05/10] VAS: Define helpers to init window context

[Sukadev Bhattiprolu]

Define helpers to initialize window context registers of the VAS
hardware. These will be used in follow-on patches when opening/closing
VAS windows.

Signed-off-by: Sukadev Bhattiprolu 
---
Changelog[v5]
- Fix: Copy the FIFO address into LFIFO_BAR register as is (don't
  shift address into bits 8:53).

Changelog[v4]
- Michael Neuling] Use ilog2(), radix_enabled() helpers;
  drop warning when 32-bit app uses VAS (a follow-on patch
  will check and return error). Set MSR_PR state to 0 for
  kernel (rather than reading from MSR).

Changelog[v3]
- Have caller, rather than init_xlate_regs() reset window regs
  so we don't reset any settings caller may already have set.
- Translation mode should be 0x3 (0b11) not 0x11.
- Skip initilaizing read-only registers NX_UTIL and NX_UTIL_SE
- Skip initializing adder registers from UWC - they are already
  initialized from the HVWC.
- Check winctx->user_win when setting translation registers
---
 arch/powerpc/platforms/powernv/vas-window.c | 306 
 arch/powerpc/platforms/powernv/vas.h|  55 +
 2 files changed, 361 insertions(+)

diff --git a/arch/powerpc/platforms/powernv/vas-window.c 
b/arch/powerpc/platforms/powernv/vas-window.c
index 588aad7..4135ab0 100644
--- a/arch/powerpc/platforms/powernv/vas-window.c
+++ b/arch/powerpc/platforms/powernv/vas-window.c
@@ -11,9 +11,12 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "vas.h"
 
+static int fault_winid;
+
 /*
  * Compute the paste address region for the window @window using the
  * ->paste_base_addr and ->paste_win_id_shift we got from device tree.
@@ -138,6 +141,309 @@ int map_winctx_mmio_bars(struct vas_window *window)
return 0;
 }
 
+/*
+ * Reset all valid registers in the HV and OS/User Window Contexts for
+ * the window identified by @window.
+ *
+ * NOTE: We cannot really use a for loop to reset window context. Not all
+ *  offsets in a window context are valid registers and the valid
+ *  registers are not sequential. And, we can only write to offsets
+ *  with valid registers (or is that only in Simics?).
+ */
+void reset_window_regs(struct vas_window *window)
+{
+   write_hvwc_reg(window, VREG(LPID), 0ULL);
+   write_hvwc_reg(window, VREG(PID), 0ULL);
+   write_hvwc_reg(window, VREG(XLATE_MSR), 0ULL);
+   write_hvwc_reg(window, VREG(XLATE_LPCR), 0ULL);
+   write_hvwc_reg(window, VREG(XLATE_CTL), 0ULL);
+   write_hvwc_reg(window, VREG(AMR), 0ULL);
+   write_hvwc_reg(window, VREG(SEIDR), 0ULL);
+   write_hvwc_reg(window, VREG(FAULT_TX_WIN), 0ULL);
+   write_hvwc_reg(window, VREG(OSU_INTR_SRC_RA), 0ULL);
+   write_hvwc_reg(window, VREG(HV_INTR_SRC_RA), 0ULL);
+   write_hvwc_reg(window, VREG(PSWID), 0ULL);
+   write_hvwc_reg(window, VREG(SPARE1), 0ULL);
+   write_hvwc_reg(window, VREG(SPARE2), 0ULL);
+   write_hvwc_reg(window, VREG(SPARE3), 0ULL);
+   write_hvwc_reg(window, VREG(SPARE4), 0ULL);
+   write_hvwc_reg(window, VREG(SPARE5), 0ULL);
+   write_hvwc_reg(window, VREG(SPARE6), 0ULL);
+   write_hvwc_reg(window, VREG(LFIFO_BAR), 0ULL);
+   write_hvwc_reg(window, VREG(LDATA_STAMP_CTL), 0ULL);
+   write_hvwc_reg(window, VREG(LDMA_CACHE_CTL), 0ULL);
+   write_hvwc_reg(window, VREG(LRFIFO_PUSH), 0ULL);
+   write_hvwc_reg(window, VREG(CURR_MSG_COUNT), 0ULL);
+   write_hvwc_reg(window, VREG(LNOTIFY_AFTER_COUNT), 0ULL);
+   write_hvwc_reg(window, VREG(LRX_WCRED), 0ULL);
+   write_hvwc_reg(window, VREG(LRX_WCRED_ADDER), 0ULL);
+   write_hvwc_reg(window, VREG(TX_WCRED), 0ULL);
+   write_hvwc_reg(window, VREG(TX_WCRED_ADDER), 0ULL);
+   write_hvwc_reg(window, VREG(LFIFO_SIZE), 0ULL);
+   write_hvwc_reg(window, VREG(WINCTL), 0ULL);
+   write_hvwc_reg(window, VREG(WIN_STATUS), 0ULL);
+   write_hvwc_reg(window, VREG(WIN_CTX_CACHING_CTL), 0ULL);
+   write_hvwc_reg(window, VREG(TX_RSVD_BUF_COUNT), 0ULL);
+   write_hvwc_reg(window, VREG(LRFIFO_WIN_PTR), 0ULL);
+   write_hvwc_reg(window, VREG(LNOTIFY_CTL), 0ULL);
+   write_hvwc_reg(window, VREG(LNOTIFY_PID), 0ULL);
+   write_hvwc_reg(window, VREG(LNOTIFY_LPID), 0ULL);
+   write_hvwc_reg(window, VREG(LNOTIFY_TID), 0ULL);
+   write_hvwc_reg(window, VREG(LNOTIFY_SCOPE), 0ULL);
+   write_hvwc_reg(window, VREG(NX_UTIL_ADDER), 0ULL);
+
+   /* Skip read-only registers: NX_UTIL and NX_UTIL_SE */
+
+   /*
+* The send and receive window credit adder registers are also
+* accessible from HVWC and have been initialized above. We don't
+* need to initialize from the OS/User Window Context, so skip
+* following calls:
+*
+*  write_uwc_reg(window, VREG(TX_WCRED_ADDER), 0ULL);
+*  write_uwc_reg(window, VREG(LRX_WCRED_ADDER), 0ULL);
+*/
+}
+
+/*
+ * Initialize window context registers related 

[PATCH v5 04/10] VAS: Define helpers for access MMIO regions

[Sukadev Bhattiprolu]

Define some helper functions to access the MMIO regions. We use these
in a follow-on patches to read/write VAS hardware registers. These
helpers are also used to later issue 'paste' instructions to submit
requests to the NX hardware engines.

Signed-off-by: Sukadev Bhattiprolu 
---
Changelog [v5]:
- [Ben Herrenschmidt]: Need cachable mapping for paste regions
  and non-cachable mapping for the MMIO regions. So, just use
  ioremap() for mapping the MMIO regions; use "winctx" instead
  of "wc" to avoid collision with "write combine".

Changelog [v3]:
- Minor reorg/cleanup of map/unmap functions

Changelog [v2]:
- Get HVWC, UWC and paste addresses from window->vinst (i.e DT)
  rather than kernel macros.
---
 arch/powerpc/platforms/powernv/vas-window.c | 126 
 1 file changed, 126 insertions(+)

diff --git a/arch/powerpc/platforms/powernv/vas-window.c 
b/arch/powerpc/platforms/powernv/vas-window.c
index 6156fbe..588aad7 100644
--- a/arch/powerpc/platforms/powernv/vas-window.c
+++ b/arch/powerpc/platforms/powernv/vas-window.c
@@ -9,9 +9,135 @@
 
 #include 
 #include 
+#include 
+#include 
 
 #include "vas.h"
 
+/*
+ * Compute the paste address region for the window @window using the
+ * ->paste_base_addr and ->paste_win_id_shift we got from device tree.
+ */
+void compute_paste_address(struct vas_window *window, uint64_t *addr, int *len)
+{
+   uint64_t base, shift;
+   int winid;
+
+   base = window->vinst->paste_base_addr;
+   shift = window->vinst->paste_win_id_shift;
+   winid = window->winid;
+
+   *addr  = base + (winid << shift);
+   *len = PAGE_SIZE;
+
+   pr_debug("Txwin #%d: Paste addr 0x%llx\n", winid, *addr);
+}
+
+static inline void get_hvwc_mmio_bar(struct vas_window *window,
+   uint64_t *start, int *len)
+{
+   uint64_t pbaddr;
+
+   pbaddr = window->vinst->hvwc_bar_start;
+   *start = pbaddr + window->winid * VAS_HVWC_SIZE;
+   *len = VAS_HVWC_SIZE;
+}
+
+static inline void get_uwc_mmio_bar(struct vas_window *window,
+   uint64_t *start, int *len)
+{
+   uint64_t pbaddr;
+
+   pbaddr = window->vinst->uwc_bar_start;
+   *start = pbaddr + window->winid * VAS_UWC_SIZE;
+   *len = VAS_UWC_SIZE;
+}
+
+static void *map_mmio_region(char *name, uint64_t start, int len)
+{
+   void *map;
+
+   if (!request_mem_region(start, len, name)) {
+   pr_devel("%s(): request_mem_region(0x%llx, %d) failed\n",
+   __func__, start, len);
+   return NULL;
+   }
+
+   map = ioremap(start, len);
+   if (!map) {
+   pr_devel("%s(): ioremap(0x%llx, %d) failed\n", __func__, start,
+   len);
+   return NULL;
+   }
+
+   return map;
+}
+
+/*
+ * Unmap the MMIO regions for a window.
+ */
+static void unmap_winctx_paste_kaddr(struct vas_window *window)
+{
+   int len;
+   uint64_t busaddr_start;
+
+   if (window->paste_kaddr) {
+   iounmap(window->paste_kaddr);
+   compute_paste_address(window, _start, );
+   release_mem_region((phys_addr_t)busaddr_start, len);
+   window->paste_kaddr = NULL;
+   }
+
+}
+
+static void unmap_winctx_mmio_bars(struct vas_window *window)
+{
+   int len;
+   uint64_t busaddr_start;
+
+   unmap_winctx_paste_kaddr(window);
+
+   if (window->hvwc_map) {
+   iounmap(window->hvwc_map);
+   get_hvwc_mmio_bar(window, _start, );
+   release_mem_region((phys_addr_t)busaddr_start, len);
+   window->hvwc_map = NULL;
+   }
+
+   if (window->uwc_map) {
+   iounmap(window->uwc_map);
+   get_uwc_mmio_bar(window, _start, );
+   release_mem_region((phys_addr_t)busaddr_start, len);
+   window->uwc_map = NULL;
+   }
+}
+
+/*
+ * Find the Hypervisor Window Context (HVWC) MMIO Base Address Region and the
+ * OS/User Window Context (UWC) MMIO Base Address Region for the given window.
+ * Map these bus addresses and save the mapped kernel addresses in @window.
+ */
+int map_winctx_mmio_bars(struct vas_window *window)
+{
+   int len;
+   uint64_t start;
+
+   window->paste_kaddr = window->hvwc_map = window->uwc_map = NULL;
+
+   get_hvwc_mmio_bar(window, , );
+   window->hvwc_map = map_mmio_region("HVWCM_Window", start, len);
+
+   get_uwc_mmio_bar(window, , );
+   window->uwc_map = map_mmio_region("UWCM_Window", start, len);
+
+   if (!window->hvwc_map || !window->uwc_map) {
+   unmap_winctx_mmio_bars(window);
+   return -1;
+   }
+
+   return 0;
+}
+
 /* stub for now */
 int vas_win_close(struct vas_window *window)
 {
-- 
2.7.4

[PATCH v5 07/10] VAS: Define vas_rx_win_open() interface

[Sukadev Bhattiprolu]

Define the vas_rx_win_open() interface. This interface is intended to be
used by the Nest Accelerator (NX) driver(s) to setup receive windows for
one or more NX engines (which implement compression/encryption algorithms
in the hardware).

Follow-on patches will provide an interface to close the window and to open
a send window that kenrel subsystems can use to access the NX engines.

The interface to open a receive window is expected to be invoked for each
instance of VAS in the system.

Signed-off-by: Sukadev Bhattiprolu 
---

Changelog[v4]:
- Export the symbols

Changelog[v3]:
- Fault receive windows must enable interrupts and disable
  notifications. NX Windows are opposite.
- Use macros rather than enum for threshold-control mode
- Ignore irq_ports for in-kernel windows. They are needed for
  user space windows and will be added later
---
 arch/powerpc/include/asm/vas.h  |  45 ++
 arch/powerpc/platforms/powernv/vas-window.c | 207 +++-
 arch/powerpc/platforms/powernv/vas.h|  11 ++
 3 files changed, 262 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
index e2575d5..09ea6f7 100644
--- a/arch/powerpc/include/asm/vas.h
+++ b/arch/powerpc/include/asm/vas.h
@@ -31,4 +31,49 @@ enum vas_cop_type {
VAS_COP_TYPE_MAX,
 };
 
+/*
+ * Receive window attributes specified by the (in-kernel) owner of window.
+ */
+struct vas_rx_win_attr {
+   void *rx_fifo;
+   int rx_fifo_size;
+   int wcreds_max;
+
+   bool pin_win;
+   bool rej_no_credit;
+   bool tx_wcred_mode;
+   bool rx_wcred_mode;
+   bool tx_win_ord_mode;
+   bool rx_win_ord_mode;
+   bool data_stamp;
+   bool nx_win;
+   bool fault_win;
+   bool notify_disable;
+   bool intr_disable;
+   bool notify_early;
+
+   int lnotify_lpid;
+   int lnotify_pid;
+   int lnotify_tid;
+   int pswid;
+
+   int tc_mode;
+};
+
+/*
+ * Helper to initialize receive window attributes to defaults for an
+ * NX window.
+ */
+extern void vas_init_rx_win_attr(struct vas_rx_win_attr *rxattr,
+   enum vas_cop_type cop);
+
+/*
+ * Open a VAS receive window for the instance of VAS identified by @vasid
+ * Use @attr to initialize the attributes of the window.
+ *
+ * Return a handle to the window or ERR_PTR() on error.
+ */
+extern struct vas_window *vas_rx_win_open(int vasid, enum vas_cop_type cop,
+   struct vas_rx_win_attr *attr);
+
 #endif /* _MISC_VAS_H */
diff --git a/arch/powerpc/platforms/powernv/vas-window.c 
b/arch/powerpc/platforms/powernv/vas-window.c
index aba8d1e..2cc9850 100644
--- a/arch/powerpc/platforms/powernv/vas-window.c
+++ b/arch/powerpc/platforms/powernv/vas-window.c
@@ -484,7 +484,7 @@ void vas_window_free(struct vas_window *window)
kfree(window);
 }
 
-struct vas_window *vas_window_alloc(struct vas_instance *vinst, int id)
+static struct vas_window *vas_window_alloc(struct vas_instance *vinst, int id)
 {
struct vas_window *window;
 
@@ -510,3 +510,208 @@ int vas_win_close(struct vas_window *window)
 {
return -1;
 }
+
+struct vas_window *get_vinstance_rxwin(struct vas_instance *vinst,
+   enum vas_cop_type cop)
+{
+   struct vas_window *rxwin;
+
+   mutex_lock(>mutex);
+
+   rxwin = vinst->rxwin[cop];
+   if (rxwin)
+   atomic_inc(>num_txwins);
+
+   mutex_unlock(>mutex);
+
+   return rxwin;
+}
+
+static void set_vinstance_rxwin(struct vas_instance *vinst,
+   enum vas_cop_type cop, struct vas_window *window)
+{
+   mutex_lock(>mutex);
+
+   /*
+* There should only be one receive window for a coprocessor type.
+*/
+   WARN_ON_ONCE(vinst->rxwin[cop]);
+   vinst->rxwin[cop] = window;
+
+   mutex_unlock(>mutex);
+}
+
+static void init_winctx_for_rxwin(struct vas_window *rxwin,
+   struct vas_rx_win_attr *rxattr,
+   struct vas_winctx *winctx)
+{
+   /*
+* We first zero (memset()) all fields and only set non-zero fields.
+* Following fields are 0/false but maybe deserve a comment:
+*
+*  ->user_win  No support for user Rx windows yet
+*  ->notify_os_intr_regIn powerNV, send intrs to HV
+*  ->notify_disableFalse for NX windows
+*  ->intr_disable  False for Fault Windows
+*  ->xtra_writeFalse for NX windows
+*  ->notify_early  NA for NX windows
+*  ->rsvd_txbuf_count  NA for Rx windows
+*  ->lpid, ->pid, ->tidNA for Rx windows
+*/
+
+   memset(winctx, 0, sizeof(struct vas_winctx));
+
+   winctx->rx_fifo = rxattr->rx_fifo;
+   winctx->rx_fifo_size = rxattr->rx_fifo_size;
+   

[PATCH v5 00/11] Enable VAS

[Sukadev Bhattiprolu]

Power9 introduces a hardware subsystem referred to as the Virtual
Accelerator Switchboard (VAS). VAS allows kernel subsystems and user
space processes to directly access the Nest Accelerator (NX) engines
which implement compression and encryption algorithms in the hardware.

NX has been in Power processors since Power7+, but access to the NX
engines was through the 'icswx' instruction which is only available
to the kernel/hypervisor. Starting with Power9, access to the NX
engines is provided to both kernel and user space processes through
VAS.

The switchboard (i.e VAS) multiplexes accesses between "receivers" and
"senders", where the "receivers" are typically the NX engines and
"senders" are the kernel subsystems and user processors that wish to
access the receivers (NX engines).  Once a sender is "connected" to
a receiver through the switchboard, the senders can submit compression/
encryption requests to the hardware using the new (PowerISA 3.0)
"copy" and "paste" instructions.

In the initial OPAL and PowerNV kernel patchsets, the "senders" can
only be kernel subsystems (eg NX-842 driver). A follow-on patch set 
will allow senders to be user-space processes.

This kernel patch set configures the VAS subsystems and provides
kernel interfaces to drivers like NX-842 to open receive and send
windows in VAS and to submit requests to the NX engine.

This patch set that has been tested in Simics and hardware Power9
environment using a modified NX-842 kernel driver and a compression
self-test module from Power8. The corresponding OPAL patchset for VAS
support was posted to skiboot mailing list:

https://lists.ozlabs.org/pipermail/skiboot/2017-May/007400.html

OPAL and kernel patchsets for NX-842 driver will be posted separately.
All four patchsets are needed to effectively use VAS/NX in Power9.

Thanks to input from Ben Herrenschmidt, Michael Neuling, Michael Ellerman
and Haren Myneni.

Changelog[v5]
- [Ben Herrenschmidt] Make VAS a platform device in the device tree
  and use the core platform functions to parse the VAS properties.
  Map the VAS MMIO regions as non-cachable and paste regions as
  cachable. Use CONFIG_PPC_VAS rather than CONFIG_VAS; Don't assume
  VAS ids are sequential.
- Copy the FIFO address as is into LFIFO_BAR (don't shift it).

Changelog[v4]
Comments from Michael Neuling:
- Move VAS code from drivers/misc/vas to arch/powerpc/platforms/powernv
  since VAS only provides interfaces to other drivers like NX-842.
- Drop vas-internal.h and use vas.h in separate dirs for VAS
  internal, kernel API and user API
- Rather than create 6 separate device tree properties windows
  and window context, combine them into 6 "reg" properties.
- Drop vas_window_reset() since windows are reset/cleared before
  being assigned to kernel/users.
- Use ilog2() and radix_enabled() helpers

Changelog[v3]
- Rebase to v4.11-rc1
- Add interfaces to initialize send/receive window attributes to
  defaults that drivers can use (see arch/powerpc/include/asm/vas.h)
- Modify interface vas_paste() to return 0 or error code
- Fix a bug in setting Translation Control Mode (0b11 not 0x11)
- Enable send-window-credit checking 
- Reorg code  in vas_win_close()
- Minor reorgs and tweaks to register field settings to make it
  easier to add support for user space windows.
- Skip writing to read-only registers
- Start window indexing from 0 rather than 1

Changelog[v2]
- Use vas-id, HVWC, UWC and paste address, entries from device tree
  rather than defining/computing them in kernel and reorg code.


Sukadev Bhattiprolu (10):
  VAS: Define macros, register fields and structures
  Move GET_FIELD/SET_FIELD to vas.h
  VAS: Define vas_init() and vas_exit()
  VAS: Define helpers for access MMIO regions
  VAS: Define helpers to init window context
  VAS: Define helpers to alloc/free windows
  VAS: Define vas_rx_win_open() interface
  VAS: Define vas_win_close() interface
  VAS: Define vas_tx_win_open()
  VAS: Define copy/paste interfaces

 .../devicetree/bindings/powerpc/ibm,vas.txt|   24 +
 MAINTAINERS|8 +
 arch/powerpc/include/asm/vas.h |  141 +++
 arch/powerpc/include/uapi/asm/vas.h|   33 +
 arch/powerpc/platforms/powernv/Kconfig |   14 +
 arch/powerpc/platforms/powernv/Makefile|1 +
 arch/powerpc/platforms/powernv/copy-paste.h|   74 ++
 arch/powerpc/platforms/powernv/vas-window.c| 1041 
 arch/powerpc/platforms/powernv/vas.c   |  183 
 arch/powerpc/platforms/powernv/vas.h   |  465 +
 drivers/crypto/nx/nx-842-powernv.c |7 +-
 drivers/crypto/nx/nx-842.h |5 -
 12 

[PATCH v5 01/10] VAS: Define macros, register fields and structures

[Sukadev Bhattiprolu]

Define macros for the VAS hardware registers and bit-fields as well
as couple of data structures needed by the VAS driver.

Signed-off-by: Sukadev Bhattiprolu 
---
Changelog[v4]
- [Michael Neuling] Move VAS code to arch/powerpc; Reorg vas.h and
  vas-internal.h to kernel and uapi versions; rather than creating
  separate properties for window context/address entries in device
  tree, combine them into "reg" properties; drop ->hwirq and irq_port
  fields from vas_window as they are only needed with user space
  windows.
- Drop the error check for CONFIG_PPC_4K_PAGES. Instead in a
  follow-on patch add a "depends on CONFIG_PPC_64K_PAGES".

Changelog[v3]
- Rename winctx->pid to winctx->pidr to reflect that its a value
  from the PID register (SPRN_PID), not the linux process id.
- Make it easier to split header into kernel/user parts
- To keep user interface simple, use macros rather than enum for
  the threshold-control modes.
- Add a pid field to struct vas_window - needed for user space
  send windows.

Changelog[v2]
- Add an overview of VAS in vas-internal.h
- Get window context parameters from device tree and drop
  unnecessary macros.
---
 arch/powerpc/include/asm/vas.h   |  34 
 arch/powerpc/include/uapi/asm/vas.h  |  25 +++
 arch/powerpc/platforms/powernv/vas.h | 379 +++
 3 files changed, 438 insertions(+)
 create mode 100644 arch/powerpc/include/asm/vas.h
 create mode 100644 arch/powerpc/include/uapi/asm/vas.h
 create mode 100644 arch/powerpc/platforms/powernv/vas.h

diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
new file mode 100644
index 000..e2575d5
--- /dev/null
+++ b/arch/powerpc/include/asm/vas.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2016 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _MISC_VAS_H
+#define _MISC_VAS_H
+
+#include 
+
+/*
+ * Min and max FIFO sizes are based on Version 1.05 Section 3.1.4.25
+ * (Local FIFO Size Register) of the VAS workbook.
+ */
+#define VAS_RX_FIFO_SIZE_MIN   (1 << 10)   /* 1KB */
+#define VAS_RX_FIFO_SIZE_MAX   (8 << 20)   /* 8MB */
+
+/*
+ * Co-processor Engine type.
+ */
+enum vas_cop_type {
+   VAS_COP_TYPE_FAULT,
+   VAS_COP_TYPE_842,
+   VAS_COP_TYPE_842_HIPRI,
+   VAS_COP_TYPE_GZIP,
+   VAS_COP_TYPE_GZIP_HIPRI,
+   VAS_COP_TYPE_MAX,
+};
+
+#endif /* _MISC_VAS_H */
diff --git a/arch/powerpc/include/uapi/asm/vas.h 
b/arch/powerpc/include/uapi/asm/vas.h
new file mode 100644
index 000..ddfe046
--- /dev/null
+++ b/arch/powerpc/include/uapi/asm/vas.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2016 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _UAPI_MISC_VAS_H
+#define _UAPI_MISC_VAS_H
+
+/*
+ * Threshold Control Mode: Have paste operation fail if the number of
+ * requests in receive FIFO exceeds a threshold.
+ *
+ * NOTE: No special error code yet if paste is rejected because of these
+ *  limits. So users can't distinguish between this and other errors.
+ */
+#define VAS_THRESH_DISABLED0
+#define VAS_THRESH_FIFO_GT_HALF_FULL   1
+#define VAS_THRESH_FIFO_GT_QTR_FULL2
+#define VAS_THRESH_FIFO_GT_EIGHTH_FULL 3
+
+#endif /* _UAPI_MISC_VAS_H */
diff --git a/arch/powerpc/platforms/powernv/vas.h 
b/arch/powerpc/platforms/powernv/vas.h
new file mode 100644
index 000..c6bcc0c
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/vas.h
@@ -0,0 +1,379 @@
+/*
+ * Copyright 2016 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _VAS_H
+#define _VAS_H
+#include 
+#include 
+#include 
+
+/*
+ * Overview of Virtual Accelerator Switchboard (VAS).
+ *
+ * VAS is a hardware "switchboard" that allows senders and receivers to
+ * exchange messages with _minimal_ kernel involvment. The receivers are
+ * typically NX coprocessor engines that perform compression or encryption
+ * in hardware, but receivers can also be other software threads.
+ *
+ * Senders are user/kernel threads that submit compression/encryption or
+ * other requests to the receivers. Senders must format their messages as
+ * Coprocessor Request Blocks (CRB)s and submit them using the "copy" and
+ * "paste" instructions 

[PATCH v5 04/10] VAS: Define helpers for access MMIO regions

[Sukadev Bhattiprolu]

Define some helper functions to access the MMIO regions. We use these
in a follow-on patches to read/write VAS hardware registers. These
helpers are also used to later issue 'paste' instructions to submit
requests to the NX hardware engines.

Signed-off-by: Sukadev Bhattiprolu 
---
Changelog [v5]:
- [Ben Herrenschmidt]: Need cachable mapping for paste regions
  and non-cachable mapping for the MMIO regions. So, just use
  ioremap() for mapping the MMIO regions; use "winctx" instead
  of "wc" to avoid collision with "write combine".

Changelog [v3]:
- Minor reorg/cleanup of map/unmap functions

Changelog [v2]:
- Get HVWC, UWC and paste addresses from window->vinst (i.e DT)
  rather than kernel macros.
---
 arch/powerpc/platforms/powernv/vas-window.c | 126 
 1 file changed, 126 insertions(+)

diff --git a/arch/powerpc/platforms/powernv/vas-window.c 
b/arch/powerpc/platforms/powernv/vas-window.c
index 6156fbe..588aad7 100644
--- a/arch/powerpc/platforms/powernv/vas-window.c
+++ b/arch/powerpc/platforms/powernv/vas-window.c
@@ -9,9 +9,135 @@
 
 #include 
 #include 
+#include 
+#include 
 
 #include "vas.h"
 
+/*
+ * Compute the paste address region for the window @window using the
+ * ->paste_base_addr and ->paste_win_id_shift we got from device tree.
+ */
+void compute_paste_address(struct vas_window *window, uint64_t *addr, int *len)
+{
+   uint64_t base, shift;
+   int winid;
+
+   base = window->vinst->paste_base_addr;
+   shift = window->vinst->paste_win_id_shift;
+   winid = window->winid;
+
+   *addr  = base + (winid << shift);
+   *len = PAGE_SIZE;
+
+   pr_debug("Txwin #%d: Paste addr 0x%llx\n", winid, *addr);
+}
+
+static inline void get_hvwc_mmio_bar(struct vas_window *window,
+   uint64_t *start, int *len)
+{
+   uint64_t pbaddr;
+
+   pbaddr = window->vinst->hvwc_bar_start;
+   *start = pbaddr + window->winid * VAS_HVWC_SIZE;
+   *len = VAS_HVWC_SIZE;
+}
+
+static inline void get_uwc_mmio_bar(struct vas_window *window,
+   uint64_t *start, int *len)
+{
+   uint64_t pbaddr;
+
+   pbaddr = window->vinst->uwc_bar_start;
+   *start = pbaddr + window->winid * VAS_UWC_SIZE;
+   *len = VAS_UWC_SIZE;
+}
+
+static void *map_mmio_region(char *name, uint64_t start, int len)
+{
+   void *map;
+
+   if (!request_mem_region(start, len, name)) {
+   pr_devel("%s(): request_mem_region(0x%llx, %d) failed\n",
+   __func__, start, len);
+   return NULL;
+   }
+
+   map = ioremap(start, len);
+   if (!map) {
+   pr_devel("%s(): ioremap(0x%llx, %d) failed\n", __func__, start,
+   len);
+   return NULL;
+   }
+
+   return map;
+}
+
+/*
+ * Unmap the MMIO regions for a window.
+ */
+static void unmap_winctx_paste_kaddr(struct vas_window *window)
+{
+   int len;
+   uint64_t busaddr_start;
+
+   if (window->paste_kaddr) {
+   iounmap(window->paste_kaddr);
+   compute_paste_address(window, _start, );
+   release_mem_region((phys_addr_t)busaddr_start, len);
+   window->paste_kaddr = NULL;
+   }
+
+}
+
+static void unmap_winctx_mmio_bars(struct vas_window *window)
+{
+   int len;
+   uint64_t busaddr_start;
+
+   unmap_winctx_paste_kaddr(window);
+
+   if (window->hvwc_map) {
+   iounmap(window->hvwc_map);
+   get_hvwc_mmio_bar(window, _start, );
+   release_mem_region((phys_addr_t)busaddr_start, len);
+   window->hvwc_map = NULL;
+   }
+
+   if (window->uwc_map) {
+   iounmap(window->uwc_map);
+   get_uwc_mmio_bar(window, _start, );
+   release_mem_region((phys_addr_t)busaddr_start, len);
+   window->uwc_map = NULL;
+   }
+}
+
+/*
+ * Find the Hypervisor Window Context (HVWC) MMIO Base Address Region and the
+ * OS/User Window Context (UWC) MMIO Base Address Region for the given window.
+ * Map these bus addresses and save the mapped kernel addresses in @window.
+ */
+int map_winctx_mmio_bars(struct vas_window *window)
+{
+   int len;
+   uint64_t start;
+
+   window->paste_kaddr = window->hvwc_map = window->uwc_map = NULL;
+
+   get_hvwc_mmio_bar(window, , );
+   window->hvwc_map = map_mmio_region("HVWCM_Window", start, len);
+
+   get_uwc_mmio_bar(window, , );
+   window->uwc_map = map_mmio_region("UWCM_Window", start, len);
+
+   if (!window->hvwc_map || !window->uwc_map) {
+   unmap_winctx_mmio_bars(window);
+   return -1;
+   }
+
+   return 0;
+}
+
 /* stub for now */
 int vas_win_close(struct vas_window *window)
 {
-- 
2.7.4

[PATCH v5 07/10] VAS: Define vas_rx_win_open() interface

[Sukadev Bhattiprolu]

Define the vas_rx_win_open() interface. This interface is intended to be
used by the Nest Accelerator (NX) driver(s) to setup receive windows for
one or more NX engines (which implement compression/encryption algorithms
in the hardware).

Follow-on patches will provide an interface to close the window and to open
a send window that kenrel subsystems can use to access the NX engines.

The interface to open a receive window is expected to be invoked for each
instance of VAS in the system.

Signed-off-by: Sukadev Bhattiprolu 
---

Changelog[v4]:
- Export the symbols

Changelog[v3]:
- Fault receive windows must enable interrupts and disable
  notifications. NX Windows are opposite.
- Use macros rather than enum for threshold-control mode
- Ignore irq_ports for in-kernel windows. They are needed for
  user space windows and will be added later
---
 arch/powerpc/include/asm/vas.h  |  45 ++
 arch/powerpc/platforms/powernv/vas-window.c | 207 +++-
 arch/powerpc/platforms/powernv/vas.h|  11 ++
 3 files changed, 262 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
index e2575d5..09ea6f7 100644
--- a/arch/powerpc/include/asm/vas.h
+++ b/arch/powerpc/include/asm/vas.h
@@ -31,4 +31,49 @@ enum vas_cop_type {
VAS_COP_TYPE_MAX,
 };
 
+/*
+ * Receive window attributes specified by the (in-kernel) owner of window.
+ */
+struct vas_rx_win_attr {
+   void *rx_fifo;
+   int rx_fifo_size;
+   int wcreds_max;
+
+   bool pin_win;
+   bool rej_no_credit;
+   bool tx_wcred_mode;
+   bool rx_wcred_mode;
+   bool tx_win_ord_mode;
+   bool rx_win_ord_mode;
+   bool data_stamp;
+   bool nx_win;
+   bool fault_win;
+   bool notify_disable;
+   bool intr_disable;
+   bool notify_early;
+
+   int lnotify_lpid;
+   int lnotify_pid;
+   int lnotify_tid;
+   int pswid;
+
+   int tc_mode;
+};
+
+/*
+ * Helper to initialize receive window attributes to defaults for an
+ * NX window.
+ */
+extern void vas_init_rx_win_attr(struct vas_rx_win_attr *rxattr,
+   enum vas_cop_type cop);
+
+/*
+ * Open a VAS receive window for the instance of VAS identified by @vasid
+ * Use @attr to initialize the attributes of the window.
+ *
+ * Return a handle to the window or ERR_PTR() on error.
+ */
+extern struct vas_window *vas_rx_win_open(int vasid, enum vas_cop_type cop,
+   struct vas_rx_win_attr *attr);
+
 #endif /* _MISC_VAS_H */
diff --git a/arch/powerpc/platforms/powernv/vas-window.c 
b/arch/powerpc/platforms/powernv/vas-window.c
index aba8d1e..2cc9850 100644
--- a/arch/powerpc/platforms/powernv/vas-window.c
+++ b/arch/powerpc/platforms/powernv/vas-window.c
@@ -484,7 +484,7 @@ void vas_window_free(struct vas_window *window)
kfree(window);
 }
 
-struct vas_window *vas_window_alloc(struct vas_instance *vinst, int id)
+static struct vas_window *vas_window_alloc(struct vas_instance *vinst, int id)
 {
struct vas_window *window;
 
@@ -510,3 +510,208 @@ int vas_win_close(struct vas_window *window)
 {
return -1;
 }
+
+struct vas_window *get_vinstance_rxwin(struct vas_instance *vinst,
+   enum vas_cop_type cop)
+{
+   struct vas_window *rxwin;
+
+   mutex_lock(>mutex);
+
+   rxwin = vinst->rxwin[cop];
+   if (rxwin)
+   atomic_inc(>num_txwins);
+
+   mutex_unlock(>mutex);
+
+   return rxwin;
+}
+
+static void set_vinstance_rxwin(struct vas_instance *vinst,
+   enum vas_cop_type cop, struct vas_window *window)
+{
+   mutex_lock(>mutex);
+
+   /*
+* There should only be one receive window for a coprocessor type.
+*/
+   WARN_ON_ONCE(vinst->rxwin[cop]);
+   vinst->rxwin[cop] = window;
+
+   mutex_unlock(>mutex);
+}
+
+static void init_winctx_for_rxwin(struct vas_window *rxwin,
+   struct vas_rx_win_attr *rxattr,
+   struct vas_winctx *winctx)
+{
+   /*
+* We first zero (memset()) all fields and only set non-zero fields.
+* Following fields are 0/false but maybe deserve a comment:
+*
+*  ->user_win  No support for user Rx windows yet
+*  ->notify_os_intr_regIn powerNV, send intrs to HV
+*  ->notify_disableFalse for NX windows
+*  ->intr_disable  False for Fault Windows
+*  ->xtra_writeFalse for NX windows
+*  ->notify_early  NA for NX windows
+*  ->rsvd_txbuf_count  NA for Rx windows
+*  ->lpid, ->pid, ->tidNA for Rx windows
+*/
+
+   memset(winctx, 0, sizeof(struct vas_winctx));
+
+   winctx->rx_fifo = rxattr->rx_fifo;
+   winctx->rx_fifo_size = rxattr->rx_fifo_size;
+   winctx->wcreds_max = 

[PATCH v5 00/11] Enable VAS

[Sukadev Bhattiprolu]

Power9 introduces a hardware subsystem referred to as the Virtual
Accelerator Switchboard (VAS). VAS allows kernel subsystems and user
space processes to directly access the Nest Accelerator (NX) engines
which implement compression and encryption algorithms in the hardware.

NX has been in Power processors since Power7+, but access to the NX
engines was through the 'icswx' instruction which is only available
to the kernel/hypervisor. Starting with Power9, access to the NX
engines is provided to both kernel and user space processes through
VAS.

The switchboard (i.e VAS) multiplexes accesses between "receivers" and
"senders", where the "receivers" are typically the NX engines and
"senders" are the kernel subsystems and user processors that wish to
access the receivers (NX engines).  Once a sender is "connected" to
a receiver through the switchboard, the senders can submit compression/
encryption requests to the hardware using the new (PowerISA 3.0)
"copy" and "paste" instructions.

In the initial OPAL and PowerNV kernel patchsets, the "senders" can
only be kernel subsystems (eg NX-842 driver). A follow-on patch set 
will allow senders to be user-space processes.

This kernel patch set configures the VAS subsystems and provides
kernel interfaces to drivers like NX-842 to open receive and send
windows in VAS and to submit requests to the NX engine.

This patch set that has been tested in Simics and hardware Power9
environment using a modified NX-842 kernel driver and a compression
self-test module from Power8. The corresponding OPAL patchset for VAS
support was posted to skiboot mailing list:

https://lists.ozlabs.org/pipermail/skiboot/2017-May/007400.html

OPAL and kernel patchsets for NX-842 driver will be posted separately.
All four patchsets are needed to effectively use VAS/NX in Power9.

Thanks to input from Ben Herrenschmidt, Michael Neuling, Michael Ellerman
and Haren Myneni.

Changelog[v5]
- [Ben Herrenschmidt] Make VAS a platform device in the device tree
  and use the core platform functions to parse the VAS properties.
  Map the VAS MMIO regions as non-cachable and paste regions as
  cachable. Use CONFIG_PPC_VAS rather than CONFIG_VAS; Don't assume
  VAS ids are sequential.
- Copy the FIFO address as is into LFIFO_BAR (don't shift it).

Changelog[v4]
Comments from Michael Neuling:
- Move VAS code from drivers/misc/vas to arch/powerpc/platforms/powernv
  since VAS only provides interfaces to other drivers like NX-842.
- Drop vas-internal.h and use vas.h in separate dirs for VAS
  internal, kernel API and user API
- Rather than create 6 separate device tree properties windows
  and window context, combine them into 6 "reg" properties.
- Drop vas_window_reset() since windows are reset/cleared before
  being assigned to kernel/users.
- Use ilog2() and radix_enabled() helpers

Changelog[v3]
- Rebase to v4.11-rc1
- Add interfaces to initialize send/receive window attributes to
  defaults that drivers can use (see arch/powerpc/include/asm/vas.h)
- Modify interface vas_paste() to return 0 or error code
- Fix a bug in setting Translation Control Mode (0b11 not 0x11)
- Enable send-window-credit checking 
- Reorg code  in vas_win_close()
- Minor reorgs and tweaks to register field settings to make it
  easier to add support for user space windows.
- Skip writing to read-only registers
- Start window indexing from 0 rather than 1

Changelog[v2]
- Use vas-id, HVWC, UWC and paste address, entries from device tree
  rather than defining/computing them in kernel and reorg code.


Sukadev Bhattiprolu (10):
  VAS: Define macros, register fields and structures
  Move GET_FIELD/SET_FIELD to vas.h
  VAS: Define vas_init() and vas_exit()
  VAS: Define helpers for access MMIO regions
  VAS: Define helpers to init window context
  VAS: Define helpers to alloc/free windows
  VAS: Define vas_rx_win_open() interface
  VAS: Define vas_win_close() interface
  VAS: Define vas_tx_win_open()
  VAS: Define copy/paste interfaces

 .../devicetree/bindings/powerpc/ibm,vas.txt|   24 +
 MAINTAINERS|8 +
 arch/powerpc/include/asm/vas.h |  141 +++
 arch/powerpc/include/uapi/asm/vas.h|   33 +
 arch/powerpc/platforms/powernv/Kconfig |   14 +
 arch/powerpc/platforms/powernv/Makefile|1 +
 arch/powerpc/platforms/powernv/copy-paste.h|   74 ++
 arch/powerpc/platforms/powernv/vas-window.c| 1041 
 arch/powerpc/platforms/powernv/vas.c   |  183 
 arch/powerpc/platforms/powernv/vas.h   |  465 +
 drivers/crypto/nx/nx-842-powernv.c |7 +-
 drivers/crypto/nx/nx-842.h |5 -
 12 

[PATCH v5 01/10] VAS: Define macros, register fields and structures

[Sukadev Bhattiprolu]

Define macros for the VAS hardware registers and bit-fields as well
as couple of data structures needed by the VAS driver.

Signed-off-by: Sukadev Bhattiprolu 
---
Changelog[v4]
- [Michael Neuling] Move VAS code to arch/powerpc; Reorg vas.h and
  vas-internal.h to kernel and uapi versions; rather than creating
  separate properties for window context/address entries in device
  tree, combine them into "reg" properties; drop ->hwirq and irq_port
  fields from vas_window as they are only needed with user space
  windows.
- Drop the error check for CONFIG_PPC_4K_PAGES. Instead in a
  follow-on patch add a "depends on CONFIG_PPC_64K_PAGES".

Changelog[v3]
- Rename winctx->pid to winctx->pidr to reflect that its a value
  from the PID register (SPRN_PID), not the linux process id.
- Make it easier to split header into kernel/user parts
- To keep user interface simple, use macros rather than enum for
  the threshold-control modes.
- Add a pid field to struct vas_window - needed for user space
  send windows.

Changelog[v2]
- Add an overview of VAS in vas-internal.h
- Get window context parameters from device tree and drop
  unnecessary macros.
---
 arch/powerpc/include/asm/vas.h   |  34 
 arch/powerpc/include/uapi/asm/vas.h  |  25 +++
 arch/powerpc/platforms/powernv/vas.h | 379 +++
 3 files changed, 438 insertions(+)
 create mode 100644 arch/powerpc/include/asm/vas.h
 create mode 100644 arch/powerpc/include/uapi/asm/vas.h
 create mode 100644 arch/powerpc/platforms/powernv/vas.h

diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
new file mode 100644
index 000..e2575d5
--- /dev/null
+++ b/arch/powerpc/include/asm/vas.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2016 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _MISC_VAS_H
+#define _MISC_VAS_H
+
+#include 
+
+/*
+ * Min and max FIFO sizes are based on Version 1.05 Section 3.1.4.25
+ * (Local FIFO Size Register) of the VAS workbook.
+ */
+#define VAS_RX_FIFO_SIZE_MIN   (1 << 10)   /* 1KB */
+#define VAS_RX_FIFO_SIZE_MAX   (8 << 20)   /* 8MB */
+
+/*
+ * Co-processor Engine type.
+ */
+enum vas_cop_type {
+   VAS_COP_TYPE_FAULT,
+   VAS_COP_TYPE_842,
+   VAS_COP_TYPE_842_HIPRI,
+   VAS_COP_TYPE_GZIP,
+   VAS_COP_TYPE_GZIP_HIPRI,
+   VAS_COP_TYPE_MAX,
+};
+
+#endif /* _MISC_VAS_H */
diff --git a/arch/powerpc/include/uapi/asm/vas.h 
b/arch/powerpc/include/uapi/asm/vas.h
new file mode 100644
index 000..ddfe046
--- /dev/null
+++ b/arch/powerpc/include/uapi/asm/vas.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2016 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _UAPI_MISC_VAS_H
+#define _UAPI_MISC_VAS_H
+
+/*
+ * Threshold Control Mode: Have paste operation fail if the number of
+ * requests in receive FIFO exceeds a threshold.
+ *
+ * NOTE: No special error code yet if paste is rejected because of these
+ *  limits. So users can't distinguish between this and other errors.
+ */
+#define VAS_THRESH_DISABLED0
+#define VAS_THRESH_FIFO_GT_HALF_FULL   1
+#define VAS_THRESH_FIFO_GT_QTR_FULL2
+#define VAS_THRESH_FIFO_GT_EIGHTH_FULL 3
+
+#endif /* _UAPI_MISC_VAS_H */
diff --git a/arch/powerpc/platforms/powernv/vas.h 
b/arch/powerpc/platforms/powernv/vas.h
new file mode 100644
index 000..c6bcc0c
--- /dev/null
+++ b/arch/powerpc/platforms/powernv/vas.h
@@ -0,0 +1,379 @@
+/*
+ * Copyright 2016 IBM Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#ifndef _VAS_H
+#define _VAS_H
+#include 
+#include 
+#include 
+
+/*
+ * Overview of Virtual Accelerator Switchboard (VAS).
+ *
+ * VAS is a hardware "switchboard" that allows senders and receivers to
+ * exchange messages with _minimal_ kernel involvment. The receivers are
+ * typically NX coprocessor engines that perform compression or encryption
+ * in hardware, but receivers can also be other software threads.
+ *
+ * Senders are user/kernel threads that submit compression/encryption or
+ * other requests to the receivers. Senders must format their messages as
+ * Coprocessor Request Blocks (CRB)s and submit them using the "copy" and
+ * "paste" instructions which were introduced in Power9.

Re: [PATCH] mm/vmalloc: a slight change of compare target in __insert_vmap_area()

[Michal Hocko]

On Wed 24-05-17 23:07:30, Wei Yang wrote:
> On Wed, May 24, 2017 at 02:11:35PM +0200, Michal Hocko wrote:
> >On Wed 24-05-17 18:03:47, Wei Yang wrote:
> >> The vmap RB tree store the elements in order and no overlap between any of
> >> them. The comparison in __insert_vmap_area() is to decide which direction
> >> the search should follow and make sure the new vmap_area is not overlap
> >> with any other.
> >> 
> >> Current implementation fails to do the overlap check.
> >> 
> >> When first "if" is not true, it means
> >> 
> >> va->va_start >= tmp_va->va_end
> >> 
> >> And with the truth
> >> 
> >> xxx->va_end > xxx->va_start
> >> 
> >> The deduction is
> >> 
> >> va->va_end > tmp_va->va_start
> >> 
> >> which is the condition in second "if".
> >> 
> >> This patch changes a little of the comparison in __insert_vmap_area() to
> >> make sure it forbids the overlapped vmap_area.
> >
> >Why do we care about overlapping vmap areas at this level. This is an
> >internal function and all the sanity checks should have been done by
> >that time AFAIR. Could you describe the problem which you are trying to
> >fix/address?
> >
> 
> No problem it tries to fix.

I would prefer the not touch the code if there is no problem to fix.
-- 
Michal Hocko
SUSE Labs

Re: [PATCH] mm/vmalloc: a slight change of compare target in __insert_vmap_area()

[Michal Hocko]

On Wed 24-05-17 23:07:30, Wei Yang wrote:
> On Wed, May 24, 2017 at 02:11:35PM +0200, Michal Hocko wrote:
> >On Wed 24-05-17 18:03:47, Wei Yang wrote:
> >> The vmap RB tree store the elements in order and no overlap between any of
> >> them. The comparison in __insert_vmap_area() is to decide which direction
> >> the search should follow and make sure the new vmap_area is not overlap
> >> with any other.
> >> 
> >> Current implementation fails to do the overlap check.
> >> 
> >> When first "if" is not true, it means
> >> 
> >> va->va_start >= tmp_va->va_end
> >> 
> >> And with the truth
> >> 
> >> xxx->va_end > xxx->va_start
> >> 
> >> The deduction is
> >> 
> >> va->va_end > tmp_va->va_start
> >> 
> >> which is the condition in second "if".
> >> 
> >> This patch changes a little of the comparison in __insert_vmap_area() to
> >> make sure it forbids the overlapped vmap_area.
> >
> >Why do we care about overlapping vmap areas at this level. This is an
> >internal function and all the sanity checks should have been done by
> >that time AFAIR. Could you describe the problem which you are trying to
> >fix/address?
> >
> 
> No problem it tries to fix.

I would prefer the not touch the code if there is no problem to fix.
-- 
Michal Hocko
SUSE Labs

Re: [PATCH] mm/zsmalloc: fix -Wunneeded-internal-declaration warning

[Minchan Kim]

On Tue, May 23, 2017 at 10:38:57PM -0700, Nick Desaulniers wrote:
> is_first_page() is only called from the macro VM_BUG_ON_PAGE() which is
> only compiled in as a runtime check when CONFIG_DEBUG_VM is set,
> otherwise is checked at compile time and not actually compiled in.
> 
> Fixes the following warning, found with Clang:
> 
> mm/zsmalloc.c:472:12: warning: function 'is_first_page' is not needed and
> will not be emitted [-Wunneeded-internal-declaration]
> static int is_first_page(struct page *page)
>^
> 
> Signed-off-by: Nick Desaulniers 
Acked-by: Minchan Kim 

Thanks.

Re: [PATCH] mm/zsmalloc: fix -Wunneeded-internal-declaration warning

[Minchan Kim]

On Tue, May 23, 2017 at 10:38:57PM -0700, Nick Desaulniers wrote:
> is_first_page() is only called from the macro VM_BUG_ON_PAGE() which is
> only compiled in as a runtime check when CONFIG_DEBUG_VM is set,
> otherwise is checked at compile time and not actually compiled in.
> 
> Fixes the following warning, found with Clang:
> 
> mm/zsmalloc.c:472:12: warning: function 'is_first_page' is not needed and
> will not be emitted [-Wunneeded-internal-declaration]
> static int is_first_page(struct page *page)
>^
> 
> Signed-off-by: Nick Desaulniers 
Acked-by: Minchan Kim 

Thanks.

[PATCH] tpm, tpmrm: Mark tpmrm_write as static

[Peter Huewe]

sparse complains that tpmrm_write can be made static, and since it is
right we make it static.

Signed-off-by: Peter Huewe 
---
 drivers/char/tpm/tpmrm-dev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/char/tpm/tpmrm-dev.c b/drivers/char/tpm/tpmrm-dev.c
index c636e7f..1a0e97a 100644
--- a/drivers/char/tpm/tpmrm-dev.c
+++ b/drivers/char/tpm/tpmrm-dev.c
@@ -45,7 +45,7 @@ static int tpmrm_release(struct inode *inode, struct file 
*file)
return 0;
 }
 
-ssize_t tpmrm_write(struct file *file, const char __user *buf,
+static ssize_t tpmrm_write(struct file *file, const char __user *buf,
   size_t size, loff_t *off)
 {
struct file_priv *fpriv = file->private_data;
-- 
2.10.2

[PATCH] tpm, tpmrm: Mark tpmrm_write as static

[Peter Huewe]

sparse complains that tpmrm_write can be made static, and since it is
right we make it static.

Signed-off-by: Peter Huewe 
---
 drivers/char/tpm/tpmrm-dev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/char/tpm/tpmrm-dev.c b/drivers/char/tpm/tpmrm-dev.c
index c636e7f..1a0e97a 100644
--- a/drivers/char/tpm/tpmrm-dev.c
+++ b/drivers/char/tpm/tpmrm-dev.c
@@ -45,7 +45,7 @@ static int tpmrm_release(struct inode *inode, struct file 
*file)
return 0;
 }
 
-ssize_t tpmrm_write(struct file *file, const char __user *buf,
+static ssize_t tpmrm_write(struct file *file, const char __user *buf,
   size_t size, loff_t *off)
 {
struct file_priv *fpriv = file->private_data;
-- 
2.10.2

Aw: Re: [PATCH] tpm: remove struct tpm_pcrextend_in

[Peter Huewe]

> Removed struct tpm_pcrextend_in as it is not used for anything anymore.
>
> Signed-off-by: Jarkko Sakkinen 
LGTM.
Reviewed-by: Peter Huewe 

> ---
> drivers/char/tpm/tpm.h | 6 --
> 1 file changed, 6 deletions(-)
>
> diff --git a/drivers/char/tpm/tpm.h b/drivers/char/tpm/tpm.h
> index dd1173427fb2..af05c1403c6e 100644
> --- a/drivers/char/tpm/tpm.h
> +++ b/drivers/char/tpm/tpm.h
> @@ -363,11 +363,6 @@ struct tpm_pcrread_in {
> __be32 pcr_idx;
> } __packed;
>
> -struct tpm_pcrextend_in {
> - __be32 pcr_idx;
> - u8 hash[TPM_DIGEST_SIZE];
> -} __packed;
> -
> /* 128 bytes is an arbitrary cap. This could be as large as TPM_BUFSIZE - 18
> * bytes, but 128 is still a relatively large number of random bytes and
> * anything much bigger causes users of struct tpm_cmd_t to start getting
> @@ -392,7 +387,6 @@ typedef union {
> u8 readpubek_out_buffer[sizeof(struct tpm_readpubek_params_out)];
> struct tpm_pcrread_in pcrread_in;
> struct tpm_pcrread_out pcrread_out;
> - struct tpm_pcrextend_in pcrextend_in;
> struct tpm_getrandom_in getrandom_in;
> struct tpm_getrandom_out getrandom_out;
> struct tpm_startup_in startup_in;
> --
> 2.11.0
>

Aw: Re: [PATCH] tpm: remove struct tpm_pcrextend_in

[Peter Huewe]

> Removed struct tpm_pcrextend_in as it is not used for anything anymore.
>
> Signed-off-by: Jarkko Sakkinen 
LGTM.
Reviewed-by: Peter Huewe 

> ---
> drivers/char/tpm/tpm.h | 6 --
> 1 file changed, 6 deletions(-)
>
> diff --git a/drivers/char/tpm/tpm.h b/drivers/char/tpm/tpm.h
> index dd1173427fb2..af05c1403c6e 100644
> --- a/drivers/char/tpm/tpm.h
> +++ b/drivers/char/tpm/tpm.h
> @@ -363,11 +363,6 @@ struct tpm_pcrread_in {
> __be32 pcr_idx;
> } __packed;
>
> -struct tpm_pcrextend_in {
> - __be32 pcr_idx;
> - u8 hash[TPM_DIGEST_SIZE];
> -} __packed;
> -
> /* 128 bytes is an arbitrary cap. This could be as large as TPM_BUFSIZE - 18
> * bytes, but 128 is still a relatively large number of random bytes and
> * anything much bigger causes users of struct tpm_cmd_t to start getting
> @@ -392,7 +387,6 @@ typedef union {
> u8 readpubek_out_buffer[sizeof(struct tpm_readpubek_params_out)];
> struct tpm_pcrread_in pcrread_in;
> struct tpm_pcrread_out pcrread_out;
> - struct tpm_pcrextend_in pcrextend_in;
> struct tpm_getrandom_in getrandom_in;
> struct tpm_getrandom_out getrandom_out;
> struct tpm_startup_in startup_in;
> --
> 2.11.0
>

Re: [PATCH v4 04/11] VAS: Define vas_init() and vas_exit()

[Sukadev Bhattiprolu]

Tyrel Datwyler [tyr...@linux.vnet.ibm.com] wrote:
> > +   vinst = _instances[0];
> > +   for_each_node_by_name(dn, "vas") {
> > +   rc = init_vas_instance(dn, vinst);
> > +   if (rc) {
> > +   pr_err("Error %d initializing VAS instance %ld\n", rc,
> > +   (vinst-_instances[0]));
> 
> You need a of_node_put(dn) here. The for_each_node_by_name() loop will 
> get/put the
> references of the device_node for you. However, if you bail out of the loop 
> you are
> responsible for the of_node_put() on the current *dn reference otherwise you 
> will leak a
> reference.

Thanks for the pointing it out.  Based on Ben's comments, I have modified this
code and no longer need to break out of the loop.

Sukadev

Re: [PATCH v4 04/11] VAS: Define vas_init() and vas_exit()

[Sukadev Bhattiprolu]

Tyrel Datwyler [tyr...@linux.vnet.ibm.com] wrote:
> > +   vinst = _instances[0];
> > +   for_each_node_by_name(dn, "vas") {
> > +   rc = init_vas_instance(dn, vinst);
> > +   if (rc) {
> > +   pr_err("Error %d initializing VAS instance %ld\n", rc,
> > +   (vinst-_instances[0]));
> 
> You need a of_node_put(dn) here. The for_each_node_by_name() loop will 
> get/put the
> references of the device_node for you. However, if you bail out of the loop 
> you are
> responsible for the of_node_put() on the current *dn reference otherwise you 
> will leak a
> reference.

Thanks for the pointing it out.  Based on Ben's comments, I have modified this
code and no longer need to break out of the loop.

Sukadev

Aw: Re: [PATCH] tpm, tpm_infineon: remove useless snprintf() calls

[Peter Huewe]

> The memory copy from rodata to stack is useless.
>
> Signed-off-by: Jarkko Sakkinen 

After review, yes that should work.
Reviewed-by: Peter Huewe 

> ---
> drivers/char/tpm/tpm_infineon.c | 8 
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/char/tpm/tpm_infineon.c b/drivers/char/tpm/tpm_infineon.c
> index e3cf9f3545c5..3b1b9f9322d5 100644
> --- a/drivers/char/tpm/tpm_infineon.c
> +++ b/drivers/char/tpm/tpm_infineon.c
> @@ -397,7 +397,7 @@ static int tpm_inf_pnp_probe(struct pnp_dev *dev,
> int vendorid[2];
> int version[2];
> int productid[2];
> - char chipname[20];
> + const char *chipname;
> struct tpm_chip *chip;
>
> /* read IO-ports through PnP */
> @@ -488,13 +488,13 @@ static int tpm_inf_pnp_probe(struct pnp_dev *dev,
>
> switch ((productid[0] << 8) | productid[1]) {
> case 6:
> - snprintf(chipname, sizeof(chipname), " (SLD 9630 TT 1.1)");
> + chipname = " (SLD 9630 TT 1.1)";
> break;
> case 11:
> - snprintf(chipname, sizeof(chipname), " (SLB 9635 TT 1.2)");
> + chipname = " (SLB 9635 TT 1.2)";
> break;
> default:
> - snprintf(chipname, sizeof(chipname), " (unknown chip)");
> + chipname = " (unknown chip)";
> break;
> }
>
> --
> 2.11.0
>

Aw: Re: [PATCH] tpm, tpm_infineon: remove useless snprintf() calls

[Peter Huewe]

> The memory copy from rodata to stack is useless.
>
> Signed-off-by: Jarkko Sakkinen 

After review, yes that should work.
Reviewed-by: Peter Huewe 

> ---
> drivers/char/tpm/tpm_infineon.c | 8 
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/char/tpm/tpm_infineon.c b/drivers/char/tpm/tpm_infineon.c
> index e3cf9f3545c5..3b1b9f9322d5 100644
> --- a/drivers/char/tpm/tpm_infineon.c
> +++ b/drivers/char/tpm/tpm_infineon.c
> @@ -397,7 +397,7 @@ static int tpm_inf_pnp_probe(struct pnp_dev *dev,
> int vendorid[2];
> int version[2];
> int productid[2];
> - char chipname[20];
> + const char *chipname;
> struct tpm_chip *chip;
>
> /* read IO-ports through PnP */
> @@ -488,13 +488,13 @@ static int tpm_inf_pnp_probe(struct pnp_dev *dev,
>
> switch ((productid[0] << 8) | productid[1]) {
> case 6:
> - snprintf(chipname, sizeof(chipname), " (SLD 9630 TT 1.1)");
> + chipname = " (SLD 9630 TT 1.1)";
> break;
> case 11:
> - snprintf(chipname, sizeof(chipname), " (SLB 9635 TT 1.2)");
> + chipname = " (SLB 9635 TT 1.2)";
> break;
> default:
> - snprintf(chipname, sizeof(chipname), " (unknown chip)");
> + chipname = " (unknown chip)";
> break;
> }
>
> --
> 2.11.0
>

[PATCH v2 2/3] rtmutex: update rt-mutex

[Alex Shi]

The rtmutex remove a pending owner bit in in rt_mutex::owner, in
commit 8161239a8bcc ("rtmutex: Simplify PI algorithm and make highest prio task 
get lock")
But the document was changed accordingly. Updating it to a meaningful
state.

BTW, as 'Steven Rostedt' mentioned:
There is still technically a "Pending Owner", it's just not called
that anymore. The pending owner happens to be the top_waiter of a lock
that has no owner and has been woken up to grab the lock.

Signed-off-by: Alex Shi 
Cc: Steven Rostedt 
Cc: Sebastian Siewior 
Cc: Mathieu Poirier 
Cc: Juri Lelli 
Cc: Thomas Gleixner 
To: linux-...@vger.kernel.org
To: linux-kernel@vger.kernel.org
To: Jonathan Corbet 
To: Ingo Molnar 
To: Peter Zijlstra 
---
 Documentation/locking/rt-mutex.txt | 58 +-
 1 file changed, 26 insertions(+), 32 deletions(-)

diff --git a/Documentation/locking/rt-mutex.txt 
b/Documentation/locking/rt-mutex.txt
index 243393d..35793e0 100644
--- a/Documentation/locking/rt-mutex.txt
+++ b/Documentation/locking/rt-mutex.txt
@@ -28,14 +28,13 @@ magic bullet for poorly designed applications, but it allows
 well-designed applications to use userspace locks in critical parts of
 an high priority thread, without losing determinism.
 
-The enqueueing of the waiters into the rtmutex waiter list is done in
+The enqueueing of the waiters into the rtmutex waiter tree is done in
 priority order. For same priorities FIFO order is chosen. For each
 rtmutex, only the top priority waiter is enqueued into the owner's
-priority waiters list. This list too queues in priority order. Whenever
+priority waiters tree. This tree too queues in priority order. Whenever
 the top priority waiter of a task changes (for example it timed out or
-got a signal), the priority of the owner task is readjusted. [The
-priority enqueueing is handled by "plists", see include/linux/plist.h
-for more details.]
+got a signal), the priority of the owner task is readjusted. The
+priority enqueueing is handled by "pi_waiters".
 
 RT-mutexes are optimized for fastpath operations and have no internal
 locking overhead when locking an uncontended mutex or unlocking a mutex
@@ -46,34 +45,29 @@ is used]
 The state of the rt-mutex is tracked via the owner field of the rt-mutex
 structure:
 
-rt_mutex->owner holds the task_struct pointer of the owner. Bit 0 and 1
-are used to keep track of the "owner is pending" and "rtmutex has
-waiters" state.
+lock->owner holds the task_struct pointer of the owner. Bit 0 is used to
+keep track of the "lock has waiters" state.
 
- owner bit1bit0
- NULL  0   0   mutex is free (fast acquire possible)
- NULL  0   1   invalid state
- NULL  1   0   Transitional state*
- NULL  1   1   invalid state
- taskpointer   0   0   mutex is held (fast release possible)
- taskpointer   0   1   task is pending owner
- taskpointer   1   0   mutex is held and has waiters
- taskpointer   1   1   task is pending owner and mutex has waiters
+ ownerbit0
+ NULL 0   lock is free (fast acquire possible)
+ NULL 1   lock is free and has waiters and the top waiter
+   is going to take the lock*
+ taskpointer  0   lock is held (fast release possible)
+ taskpointer  1   lock is held and has waiters**
 
-Pending-ownership handling is a performance optimization:
-pending-ownership is assigned to the first (highest priority) waiter of
-the mutex, when the mutex is released. The thread is woken up and once
-it starts executing it can acquire the mutex. Until the mutex is taken
-by it (bit 0 is cleared) a competing higher priority thread can "steal"
-the mutex which puts the woken up thread back on the waiters list.
+The fast atomic compare exchange based acquire and release is only
+possible when bit 0 of lock->owner is 0.
 
-The pending-ownership optimization is especially important for the
-uninterrupted workflow of high-prio tasks which repeatedly
-takes/releases locks that have lower-prio waiters. Without this
-optimization the higher-prio thread would ping-pong to the lower-prio
-task [because at unlock time we always assign a new owner].
+(*) It also can be a transitional state when grabbing the lock
+with ->wait_lock is held. To prevent any fast path cmpxchg to the lock,
+we need to set the bit0 before looking at the lock, and the owner may be
+NULL in this small time, hence this can be a transitional state.
 
-(*) The "mutex has waiters" bit gets set to take the lock. If the lock
-doesn't already have an owner, this bit is quickly cleared if there are
-no waiters.  So this is a transitional state to synchronize with looking
-at the owner field of the mutex and the mutex owner releasing the 

[PATCH v2 2/3] rtmutex: update rt-mutex

[Alex Shi]

The rtmutex remove a pending owner bit in in rt_mutex::owner, in
commit 8161239a8bcc ("rtmutex: Simplify PI algorithm and make highest prio task 
get lock")
But the document was changed accordingly. Updating it to a meaningful
state.

BTW, as 'Steven Rostedt' mentioned:
There is still technically a "Pending Owner", it's just not called
that anymore. The pending owner happens to be the top_waiter of a lock
that has no owner and has been woken up to grab the lock.

Signed-off-by: Alex Shi 
Cc: Steven Rostedt 
Cc: Sebastian Siewior 
Cc: Mathieu Poirier 
Cc: Juri Lelli 
Cc: Thomas Gleixner 
To: linux-...@vger.kernel.org
To: linux-kernel@vger.kernel.org
To: Jonathan Corbet 
To: Ingo Molnar 
To: Peter Zijlstra 
---
 Documentation/locking/rt-mutex.txt | 58 +-
 1 file changed, 26 insertions(+), 32 deletions(-)

diff --git a/Documentation/locking/rt-mutex.txt 
b/Documentation/locking/rt-mutex.txt
index 243393d..35793e0 100644
--- a/Documentation/locking/rt-mutex.txt
+++ b/Documentation/locking/rt-mutex.txt
@@ -28,14 +28,13 @@ magic bullet for poorly designed applications, but it allows
 well-designed applications to use userspace locks in critical parts of
 an high priority thread, without losing determinism.
 
-The enqueueing of the waiters into the rtmutex waiter list is done in
+The enqueueing of the waiters into the rtmutex waiter tree is done in
 priority order. For same priorities FIFO order is chosen. For each
 rtmutex, only the top priority waiter is enqueued into the owner's
-priority waiters list. This list too queues in priority order. Whenever
+priority waiters tree. This tree too queues in priority order. Whenever
 the top priority waiter of a task changes (for example it timed out or
-got a signal), the priority of the owner task is readjusted. [The
-priority enqueueing is handled by "plists", see include/linux/plist.h
-for more details.]
+got a signal), the priority of the owner task is readjusted. The
+priority enqueueing is handled by "pi_waiters".
 
 RT-mutexes are optimized for fastpath operations and have no internal
 locking overhead when locking an uncontended mutex or unlocking a mutex
@@ -46,34 +45,29 @@ is used]
 The state of the rt-mutex is tracked via the owner field of the rt-mutex
 structure:
 
-rt_mutex->owner holds the task_struct pointer of the owner. Bit 0 and 1
-are used to keep track of the "owner is pending" and "rtmutex has
-waiters" state.
+lock->owner holds the task_struct pointer of the owner. Bit 0 is used to
+keep track of the "lock has waiters" state.
 
- owner bit1bit0
- NULL  0   0   mutex is free (fast acquire possible)
- NULL  0   1   invalid state
- NULL  1   0   Transitional state*
- NULL  1   1   invalid state
- taskpointer   0   0   mutex is held (fast release possible)
- taskpointer   0   1   task is pending owner
- taskpointer   1   0   mutex is held and has waiters
- taskpointer   1   1   task is pending owner and mutex has waiters
+ ownerbit0
+ NULL 0   lock is free (fast acquire possible)
+ NULL 1   lock is free and has waiters and the top waiter
+   is going to take the lock*
+ taskpointer  0   lock is held (fast release possible)
+ taskpointer  1   lock is held and has waiters**
 
-Pending-ownership handling is a performance optimization:
-pending-ownership is assigned to the first (highest priority) waiter of
-the mutex, when the mutex is released. The thread is woken up and once
-it starts executing it can acquire the mutex. Until the mutex is taken
-by it (bit 0 is cleared) a competing higher priority thread can "steal"
-the mutex which puts the woken up thread back on the waiters list.
+The fast atomic compare exchange based acquire and release is only
+possible when bit 0 of lock->owner is 0.
 
-The pending-ownership optimization is especially important for the
-uninterrupted workflow of high-prio tasks which repeatedly
-takes/releases locks that have lower-prio waiters. Without this
-optimization the higher-prio thread would ping-pong to the lower-prio
-task [because at unlock time we always assign a new owner].
+(*) It also can be a transitional state when grabbing the lock
+with ->wait_lock is held. To prevent any fast path cmpxchg to the lock,
+we need to set the bit0 before looking at the lock, and the owner may be
+NULL in this small time, hence this can be a transitional state.
 
-(*) The "mutex has waiters" bit gets set to take the lock. If the lock
-doesn't already have an owner, this bit is quickly cleared if there are
-no waiters.  So this is a transitional state to synchronize with looking
-at the owner field of the mutex and the mutex owner releasing the lock.
+(**) There is a small time when bit 0 is set but there are no
+waiters. This can happen when grabbing the lock in the slow path.
+To prevent a cmpxchg of the owner releasing the 

[PATCH 3/3] rtmutex: remove unnecessary adjust prio

[Alex Shi]

We don't need to adjust prio before new pi_waiter adding. The prio
only need update after pi_waiter change or task priority change.

Signed-off-by: Alex Shi 
Cc: Steven Rostedt 
Cc: Sebastian Siewior 
Cc: Mathieu Poirier 
Cc: Juri Lelli 
Cc: Thomas Gleixner 
To: linux-kernel@vger.kernel.org
To: Ingo Molnar 
To: Peter Zijlstra 
---
 kernel/locking/rtmutex.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/kernel/locking/rtmutex.c b/kernel/locking/rtmutex.c
index b955094..b659ba0 100644
--- a/kernel/locking/rtmutex.c
+++ b/kernel/locking/rtmutex.c
@@ -963,7 +963,6 @@ static int task_blocks_on_rt_mutex(struct rt_mutex *lock,
return -EDEADLK;
 
raw_spin_lock(>pi_lock);
-   rt_mutex_adjust_prio(task);
waiter->task = task;
waiter->lock = lock;
waiter->prio = task->prio;
-- 
1.9.1

[PATCH 3/3] rtmutex: remove unnecessary adjust prio

[Alex Shi]

We don't need to adjust prio before new pi_waiter adding. The prio
only need update after pi_waiter change or task priority change.

Signed-off-by: Alex Shi 
Cc: Steven Rostedt 
Cc: Sebastian Siewior 
Cc: Mathieu Poirier 
Cc: Juri Lelli 
Cc: Thomas Gleixner 
To: linux-kernel@vger.kernel.org
To: Ingo Molnar 
To: Peter Zijlstra 
---
 kernel/locking/rtmutex.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/kernel/locking/rtmutex.c b/kernel/locking/rtmutex.c
index b955094..b659ba0 100644
--- a/kernel/locking/rtmutex.c
+++ b/kernel/locking/rtmutex.c
@@ -963,7 +963,6 @@ static int task_blocks_on_rt_mutex(struct rt_mutex *lock,
return -EDEADLK;
 
raw_spin_lock(>pi_lock);
-   rt_mutex_adjust_prio(task);
waiter->task = task;
waiter->lock = lock;
waiter->prio = task->prio;
-- 
1.9.1

[PATCH v3 1/3] rtmutex: update rt-mutex-design

[Alex Shi]

The rt-mutex-design documents didn't gotten meaningful update from its
first version. Even after owner's pending bit was removed in commit 8161239a8bcc
("rtmutex: Simplify PI algorithm and make highest prio task get lock")
and priority list 'plist' changed to rbtree. And Peter Zijlstra did some
clean up and fix for deadline task changes on tip tree.

So update it to latest code and make it meaningful.

Signed-off-by: Alex Shi 
Cc: Steven Rostedt 
Cc: Sebastian Siewior 
Cc: Mathieu Poirier 
Cc: Juri Lelli 
Cc: Thomas Gleixner 
To: linux-...@vger.kernel.org
To: linux-kernel@vger.kernel.org
To: Jonathan Corbet 
To: Ingo Molnar 
To: Peter Zijlstra 
---
 Documentation/locking/rt-mutex-design.txt | 418 +++---
 1 file changed, 97 insertions(+), 321 deletions(-)

diff --git a/Documentation/locking/rt-mutex-design.txt 
b/Documentation/locking/rt-mutex-design.txt
index 8666070..1a0da32 100644
--- a/Documentation/locking/rt-mutex-design.txt
+++ b/Documentation/locking/rt-mutex-design.txt
@@ -97,9 +97,9 @@ waiter   - A waiter is a struct that is stored on the stack 
of a blocked
a process being blocked on the mutex, it is fine to allocate
the waiter on the process's stack (local variable).  This
structure holds a pointer to the task, as well as the mutex that
-   the task is blocked on.  It also has the plist node structures to
-   place the task in the waiter_list of a mutex as well as the
-   pi_list of a mutex owner task (described below).
+   the task is blocked on.  It also has a rbtree node structures to
+   place the task in waiters rbtree of a mutex as well as the
+   pi_waiters rbtree of a mutex owner task (described below).
 
waiter is sometimes used in reference to the task that is waiting
on a mutex. This is the same as waiter->task.
@@ -179,53 +179,35 @@ again.
  |
F->L5-+
 
-
-Plist
--
-
-Before I go further and talk about how the PI chain is stored through lists
-on both mutexes and processes, I'll explain the plist.  This is similar to
-the struct list_head functionality that is already in the kernel.
-The implementation of plist is out of scope for this document, but it is
-very important to understand what it does.
-
-There are a few differences between plist and list, the most important one
-being that plist is a priority sorted linked list.  This means that the
-priorities of the plist are sorted, such that it takes O(1) to retrieve the
-highest priority item in the list.  Obviously this is useful to store processes
-based on their priorities.
-
-Another difference, which is important for implementation, is that, unlike
-list, the head of the list is a different element than the nodes of a list.
-So the head of the list is declared as struct plist_head and nodes that will
-be added to the list are declared as struct plist_node.
-
+If process G has the highest priority in the chain, then all the tasks up
+the chain (A and B in this example), must have their priorities increased
+to that of G.
 
 Mutex Waiter List
 -
 
 Every mutex keeps track of all the waiters that are blocked on itself. The 
mutex
-has a plist to store these waiters by priority.  This list is protected by
+has a rbtree to store these waiters by priority.  This tree is protected by
 a spin lock that is located in the struct of the mutex. This lock is called
-wait_lock.  Since the modification of the waiter list is never done in
+wait_lock.  Since the modification of the waiter tree is never done in
 interrupt context, the wait_lock can be taken without disabling interrupts.
 
 
-Task PI List
+Task PI Tree
 
 
-To keep track of the PI chains, each process has its own PI list.  This is
-a list of all top waiters of the mutexes that are owned by the process.
-Note that this list only holds the top waiters and not all waiters that are
+To keep track of the PI chains, each process has its own PI rbtree.  This is
+a tree of all top waiters of the mutexes that are owned by the process.
+Note that this tree only holds the top waiters and not all waiters that are
 blocked on mutexes owned by the process.
 
-The top of the task's PI list is always the highest priority task that
+The top of the task's PI tree is always the highest priority task that
 is waiting on a mutex that is owned by the task.  So if the task has
 inherited a priority, it will always be the priority of the task that is
-at the top of this list.
+at the top of this tree.
 
-This list is stored in the task structure of a process as a plist called
-pi_list.  This list is protected by a spin lock also in the task structure,
+This tree is stored in the task structure of a process as a 

[PATCH v3 1/3] rtmutex: update rt-mutex-design

[Alex Shi]

The rt-mutex-design documents didn't gotten meaningful update from its
first version. Even after owner's pending bit was removed in commit 8161239a8bcc
("rtmutex: Simplify PI algorithm and make highest prio task get lock")
and priority list 'plist' changed to rbtree. And Peter Zijlstra did some
clean up and fix for deadline task changes on tip tree.

So update it to latest code and make it meaningful.

Signed-off-by: Alex Shi 
Cc: Steven Rostedt 
Cc: Sebastian Siewior 
Cc: Mathieu Poirier 
Cc: Juri Lelli 
Cc: Thomas Gleixner 
To: linux-...@vger.kernel.org
To: linux-kernel@vger.kernel.org
To: Jonathan Corbet 
To: Ingo Molnar 
To: Peter Zijlstra 
---
 Documentation/locking/rt-mutex-design.txt | 418 +++---
 1 file changed, 97 insertions(+), 321 deletions(-)

diff --git a/Documentation/locking/rt-mutex-design.txt 
b/Documentation/locking/rt-mutex-design.txt
index 8666070..1a0da32 100644
--- a/Documentation/locking/rt-mutex-design.txt
+++ b/Documentation/locking/rt-mutex-design.txt
@@ -97,9 +97,9 @@ waiter   - A waiter is a struct that is stored on the stack 
of a blocked
a process being blocked on the mutex, it is fine to allocate
the waiter on the process's stack (local variable).  This
structure holds a pointer to the task, as well as the mutex that
-   the task is blocked on.  It also has the plist node structures to
-   place the task in the waiter_list of a mutex as well as the
-   pi_list of a mutex owner task (described below).
+   the task is blocked on.  It also has a rbtree node structures to
+   place the task in waiters rbtree of a mutex as well as the
+   pi_waiters rbtree of a mutex owner task (described below).
 
waiter is sometimes used in reference to the task that is waiting
on a mutex. This is the same as waiter->task.
@@ -179,53 +179,35 @@ again.
  |
F->L5-+
 
-
-Plist
--
-
-Before I go further and talk about how the PI chain is stored through lists
-on both mutexes and processes, I'll explain the plist.  This is similar to
-the struct list_head functionality that is already in the kernel.
-The implementation of plist is out of scope for this document, but it is
-very important to understand what it does.
-
-There are a few differences between plist and list, the most important one
-being that plist is a priority sorted linked list.  This means that the
-priorities of the plist are sorted, such that it takes O(1) to retrieve the
-highest priority item in the list.  Obviously this is useful to store processes
-based on their priorities.
-
-Another difference, which is important for implementation, is that, unlike
-list, the head of the list is a different element than the nodes of a list.
-So the head of the list is declared as struct plist_head and nodes that will
-be added to the list are declared as struct plist_node.
-
+If process G has the highest priority in the chain, then all the tasks up
+the chain (A and B in this example), must have their priorities increased
+to that of G.
 
 Mutex Waiter List
 -
 
 Every mutex keeps track of all the waiters that are blocked on itself. The 
mutex
-has a plist to store these waiters by priority.  This list is protected by
+has a rbtree to store these waiters by priority.  This tree is protected by
 a spin lock that is located in the struct of the mutex. This lock is called
-wait_lock.  Since the modification of the waiter list is never done in
+wait_lock.  Since the modification of the waiter tree is never done in
 interrupt context, the wait_lock can be taken without disabling interrupts.
 
 
-Task PI List
+Task PI Tree
 
 
-To keep track of the PI chains, each process has its own PI list.  This is
-a list of all top waiters of the mutexes that are owned by the process.
-Note that this list only holds the top waiters and not all waiters that are
+To keep track of the PI chains, each process has its own PI rbtree.  This is
+a tree of all top waiters of the mutexes that are owned by the process.
+Note that this tree only holds the top waiters and not all waiters that are
 blocked on mutexes owned by the process.
 
-The top of the task's PI list is always the highest priority task that
+The top of the task's PI tree is always the highest priority task that
 is waiting on a mutex that is owned by the task.  So if the task has
 inherited a priority, it will always be the priority of the task that is
-at the top of this list.
+at the top of this tree.
 
-This list is stored in the task structure of a process as a plist called
-pi_list.  This list is protected by a spin lock also in the task structure,
+This tree is stored in the task structure of a process as a rbtree called
+pi_waiters.  It is protected by a spin lock also in the task structure,
 called pi_lock.  This lock may also be taken in interrupt context, so when
 locking the pi_lock, 

Re: [PATCH] Staging: bcm2835-audio: bcm2835-ctl.c: Fixed a comment coding style issue.

[srishti sharma]

On Thu, May 25, 2017 at 4:58 AM, Tobin C. Harding  wrote:
> On Wed, May 24, 2017 at 08:03:14PM +0530, srishti sharma wrote:
>
> This driver is not in Greg KH's staging tree. You may like to work off
> of that tree when doing staging patches.
>
> https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git/
>
> To aid you future patches here are a couple of minor comments for you.
>
>> fixed a trailing */ issue
>
> You may like to be more explicit here using the format described in
> Documentation/process/submitting-patches.rst (Section 2 Describe your
> changes). This goes for your subject line as well.
>
>> Signed-off-by: srishti sharma 
>> ---
>>  drivers/staging/bcm2835-audio/bcm2835-ctl.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/staging/bcm2835-audio/bcm2835-ctl.c 
>> b/drivers/staging/bcm2835-audio/bcm2835-ctl.c
>> index a4ffa1b..38fabab 100644
>> --- a/drivers/staging/bcm2835-audio/bcm2835-ctl.c
>> +++ b/drivers/staging/bcm2835-audio/bcm2835-ctl.c
>> @@ -247,8 +247,8 @@ static int snd_bcm2835_spdif_mask_get(struct 
>> snd_kcontrol *kcontrol,
>>   struct snd_ctl_elem_value *ucontrol)
>>  {
>>   /* bcm2835 supports only consumer mode and sets all other format flags
>> -  * automatically. So the only thing left is signalling non-audio
>> -  * content */
>> +  * automatically. So the only thing left is signalling non-audio 
>> content
>> +  */
>
> And for completeness this is the block comment style in networking
> code, the rest of the kernel uses the format
>
> /*
>  * block comment blah blah
>  * on multiple lines
>  */
>
> Good luck,
> Tobin.




Okay, Thanks a lot .

Regards ,
Srishti

Re: [PATCH] Staging: bcm2835-audio: bcm2835-ctl.c: Fixed a comment coding style issue.

[srishti sharma]

On Thu, May 25, 2017 at 4:58 AM, Tobin C. Harding  wrote:
> On Wed, May 24, 2017 at 08:03:14PM +0530, srishti sharma wrote:
>
> This driver is not in Greg KH's staging tree. You may like to work off
> of that tree when doing staging patches.
>
> https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git/
>
> To aid you future patches here are a couple of minor comments for you.
>
>> fixed a trailing */ issue
>
> You may like to be more explicit here using the format described in
> Documentation/process/submitting-patches.rst (Section 2 Describe your
> changes). This goes for your subject line as well.
>
>> Signed-off-by: srishti sharma 
>> ---
>>  drivers/staging/bcm2835-audio/bcm2835-ctl.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/staging/bcm2835-audio/bcm2835-ctl.c 
>> b/drivers/staging/bcm2835-audio/bcm2835-ctl.c
>> index a4ffa1b..38fabab 100644
>> --- a/drivers/staging/bcm2835-audio/bcm2835-ctl.c
>> +++ b/drivers/staging/bcm2835-audio/bcm2835-ctl.c
>> @@ -247,8 +247,8 @@ static int snd_bcm2835_spdif_mask_get(struct 
>> snd_kcontrol *kcontrol,
>>   struct snd_ctl_elem_value *ucontrol)
>>  {
>>   /* bcm2835 supports only consumer mode and sets all other format flags
>> -  * automatically. So the only thing left is signalling non-audio
>> -  * content */
>> +  * automatically. So the only thing left is signalling non-audio 
>> content
>> +  */
>
> And for completeness this is the block comment style in networking
> code, the rest of the kernel uses the format
>
> /*
>  * block comment blah blah
>  * on multiple lines
>  */
>
> Good luck,
> Tobin.




Okay, Thanks a lot .

Regards ,
Srishti

[PATCH] mtd: nand: check ecc->total sanity in nand_scan_tail

[Masahiro Yamada]

Drivers are supposed to set correct ecc->{size,strength,bytes} before
calling nand_scan_tail(), but it does not complain about ecc->total
bigger than oobsize.

In this case, chip->scan_bbt() crashes due to memory corruption, but
it is hard to debug.  It would be kind to fail it earlier with a clear
message.

Signed-off-by: Masahiro Yamada 
---

I was actually hit by this case.

I wasted half a day until I figured out my coding mistake in my
Denali driver.  It will be helpful to check this in NAND core.


 drivers/mtd/nand/nand_base.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index f4d686192717..14d6a5aa3ee8 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4970,6 +4970,11 @@ int nand_scan_tail(struct mtd_info *mtd)
goto err_free;
}
ecc->total = ecc->steps * ecc->bytes;
+   if (ecc->total > mtd->oobsize) {
+   WARN(1, "Total number of ECC bytes exceeded oobsize\n");
+   ret = -EINVAL;
+   goto err_free;
+   }
 
/*
 * The number of bytes available for a client to place data into
-- 
2.7.4

[PATCH] mtd: nand: check ecc->total sanity in nand_scan_tail

[Masahiro Yamada]

Drivers are supposed to set correct ecc->{size,strength,bytes} before
calling nand_scan_tail(), but it does not complain about ecc->total
bigger than oobsize.

In this case, chip->scan_bbt() crashes due to memory corruption, but
it is hard to debug.  It would be kind to fail it earlier with a clear
message.

Signed-off-by: Masahiro Yamada 
---

I was actually hit by this case.

I wasted half a day until I figured out my coding mistake in my
Denali driver.  It will be helpful to check this in NAND core.


 drivers/mtd/nand/nand_base.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index f4d686192717..14d6a5aa3ee8 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -4970,6 +4970,11 @@ int nand_scan_tail(struct mtd_info *mtd)
goto err_free;
}
ecc->total = ecc->steps * ecc->bytes;
+   if (ecc->total > mtd->oobsize) {
+   WARN(1, "Total number of ECC bytes exceeded oobsize\n");
+   ret = -EINVAL;
+   goto err_free;
+   }
 
/*
 * The number of bytes available for a client to place data into
-- 
2.7.4

[PATCH v3 1/2] phy: add PCIe PHY driver for Mediatek SoCs

[Ryder Lee]

This patch adds a generic PCIe PHY driver for Mediatek SoCs.

Signed-off-by: Ryder Lee 
---
 drivers/phy/Kconfig |   8 ++
 drivers/phy/Makefile|   1 +
 drivers/phy/phy-mediatek-pcie.c | 290 
 3 files changed, 299 insertions(+)
 create mode 100644 drivers/phy/phy-mediatek-pcie.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index afaf7b6..220f12f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -241,6 +241,14 @@ config PHY_MT65XX_USB3
  Say 'Y' here to add support for Mediatek USB3.0 PHY driver,
  it supports multiple usb2.0 and usb3.0 ports.
 
+config PHY_MEDIATEK_PCIE
+   tristate "Mediatek PCIe PHY driver"
+   depends on ARCH_MEDIATEK && OF
+   select GENERIC_PHY
+   select MFD_SYSCON
+   help
+ Say 'Y' here to add support for generic Mediatek PCIe PHY driver.
+
 config PHY_HI6220_USB
tristate "hi6220 USB PHY support"
depends on (ARCH_HISI && ARM64) || COMPILE_TEST
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f8047b4..b337ae9 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_PHY_EXYNOS5250_SATA) += phy-exynos5250-sata.o
 obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o
 obj-$(CONFIG_PHY_HI6220_USB)   += phy-hi6220-usb.o
 obj-$(CONFIG_PHY_MT65XX_USB3)  += phy-mt65xx-usb3.o
+obj-$(CONFIG_PHY_MEDIATEK_PCIE)+= phy-mediatek-pcie.o
 obj-$(CONFIG_PHY_SUN4I_USB)+= phy-sun4i-usb.o
 obj-$(CONFIG_PHY_SUN9I_USB)+= phy-sun9i-usb.o
 obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
diff --git a/drivers/phy/phy-mediatek-pcie.c b/drivers/phy/phy-mediatek-pcie.c
new file mode 100644
index 000..7c6f5aa
--- /dev/null
+++ b/drivers/phy/phy-mediatek-pcie.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Ryder Lee 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Offsets of sub-segment in each port registers */
+#define PCIE_SIFSLV_PHYD_BANK2_BASE0xa00
+#define SSUSB_SIFSLV_PHYA_BASE 0xb00
+#define SSUSB_SIFSLV_PHYA_DA_BASE  0xc00
+
+/*
+ * RX detection stable - 1 scale represent 8 reference cycles
+ * cover reference clock from 1M~100MHz, 7us~40us
+ */
+#define B2_PHYD_RXDET1 (PCIE_SIFSLV_PHYD_BANK2_BASE + 0x28)
+#define RG_SSUSB_RXDET_STB2GENMASK(17, 9)
+#define RG_SSUSB_RXDET_STB2_VAL(x) ((0x1ff & (x)) << 9)
+
+#define B2_PHYD_RXDET2 (PCIE_SIFSLV_PHYD_BANK2_BASE + 0x2c)
+#define RG_SSUSB_RXDET_STB2_P3 GENMASK(8, 0)
+#define RG_SSUSB_RXDET_STB2_P3_VAL(x)  (0x1ff & (x))
+
+#define U3_PHYA_REG0   (SSUSB_SIFSLV_PHYA_BASE + 0x00)
+#define RG_PCIE_CLKDRV_OFFSET  GENMASK(3, 1)
+#define RG_PCIE_CLKDRV_OFFSET_VAL(x)   ((0x3 & (x)) << 2)
+
+#define U3_PHYA_REG1   (SSUSB_SIFSLV_PHYA_BASE + 0x04)
+#define RG_PCIE_CLKDRV_AMP GENMASK(31, 29)
+#define RG_PCIE_CLKDRV_AMP_VAL(x)  ((0x7 & (x)) << 29)
+
+#define DA_SSUSB_CDR_REFCK_SEL (SSUSB_SIFSLV_PHYA_DA_BASE + 0x00)
+#define RG_SSUSB_XTAL_EXT_PE1H GENMASK(13, 12)
+#define RG_SSUSB_XTAL_EXT_PE1H_VAL(x)  ((0x3 & (x)) << 12)
+#define RG_SSUSB_XTAL_EXT_PE2H GENMASK(17, 16)
+#define RG_SSUSB_XTAL_EXT_PE2H_VAL(x)  ((0x3 & (x)) << 16)
+
+#define DA_SSUSB_PLL_IC(SSUSB_SIFSLV_PHYA_DA_BASE + 
0x0c)
+#define RG_SSUSB_PLL_IC_PE2H   GENMASK(15, 12)
+#define RG_SSUSB_PLL_IC_PE2H_VAL(x)((0xf & (x)) << 12)
+#define RG_SSUSB_PLL_BR_PE2H   GENMASK(29, 28)
+#define RG_SSUSB_PLL_BR_PE2H_VAL(x)((0x3 & (x)) << 28)
+
+#define DA_SSUSB_PLL_BC(SSUSB_SIFSLV_PHYA_DA_BASE + 
0x08)
+#define RG_SSUSB_PLL_DIVEN_PE2HGENMASK(21, 19)
+#define RG_SSUSB_PLL_BC_PE2H   GENMASK(7, 6)
+#define RG_SSUSB_PLL_BC_PE2H_VAL(x)((0x3 & (x)) << 6)
+
+#define DA_SSUSB_PLL_IR(SSUSB_SIFSLV_PHYA_DA_BASE + 
0x10)
+#define RG_SSUSB_PLL_IR_PE2H   GENMASK(19, 16)
+#define RG_SSUSB_PLL_IR_PE2H_VAL(x)((0xf & (x)) << 16)
+
+#define DA_SSUSB_PLL_BP(SSUSB_SIFSLV_PHYA_DA_BASE + 
0x14)
+#define RG_SSUSB_PLL_BP_PE2H   GENMASK(19, 16)
+#define RG_SSUSB_PLL_BP_PE2H_VAL(x)((0xf & (x)) << 16)
+
+#define DA_SSUSB_PLL_SSC_DELTA1_REG20  

[PATCH v3 1/2] phy: add PCIe PHY driver for Mediatek SoCs

[Ryder Lee]

This patch adds a generic PCIe PHY driver for Mediatek SoCs.

Signed-off-by: Ryder Lee 
---
 drivers/phy/Kconfig |   8 ++
 drivers/phy/Makefile|   1 +
 drivers/phy/phy-mediatek-pcie.c | 290 
 3 files changed, 299 insertions(+)
 create mode 100644 drivers/phy/phy-mediatek-pcie.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index afaf7b6..220f12f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -241,6 +241,14 @@ config PHY_MT65XX_USB3
  Say 'Y' here to add support for Mediatek USB3.0 PHY driver,
  it supports multiple usb2.0 and usb3.0 ports.
 
+config PHY_MEDIATEK_PCIE
+   tristate "Mediatek PCIe PHY driver"
+   depends on ARCH_MEDIATEK && OF
+   select GENERIC_PHY
+   select MFD_SYSCON
+   help
+ Say 'Y' here to add support for generic Mediatek PCIe PHY driver.
+
 config PHY_HI6220_USB
tristate "hi6220 USB PHY support"
depends on (ARCH_HISI && ARM64) || COMPILE_TEST
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f8047b4..b337ae9 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_PHY_EXYNOS5250_SATA) += phy-exynos5250-sata.o
 obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o
 obj-$(CONFIG_PHY_HI6220_USB)   += phy-hi6220-usb.o
 obj-$(CONFIG_PHY_MT65XX_USB3)  += phy-mt65xx-usb3.o
+obj-$(CONFIG_PHY_MEDIATEK_PCIE)+= phy-mediatek-pcie.o
 obj-$(CONFIG_PHY_SUN4I_USB)+= phy-sun4i-usb.o
 obj-$(CONFIG_PHY_SUN9I_USB)+= phy-sun9i-usb.o
 obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
diff --git a/drivers/phy/phy-mediatek-pcie.c b/drivers/phy/phy-mediatek-pcie.c
new file mode 100644
index 000..7c6f5aa
--- /dev/null
+++ b/drivers/phy/phy-mediatek-pcie.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Ryder Lee 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Offsets of sub-segment in each port registers */
+#define PCIE_SIFSLV_PHYD_BANK2_BASE0xa00
+#define SSUSB_SIFSLV_PHYA_BASE 0xb00
+#define SSUSB_SIFSLV_PHYA_DA_BASE  0xc00
+
+/*
+ * RX detection stable - 1 scale represent 8 reference cycles
+ * cover reference clock from 1M~100MHz, 7us~40us
+ */
+#define B2_PHYD_RXDET1 (PCIE_SIFSLV_PHYD_BANK2_BASE + 0x28)
+#define RG_SSUSB_RXDET_STB2GENMASK(17, 9)
+#define RG_SSUSB_RXDET_STB2_VAL(x) ((0x1ff & (x)) << 9)
+
+#define B2_PHYD_RXDET2 (PCIE_SIFSLV_PHYD_BANK2_BASE + 0x2c)
+#define RG_SSUSB_RXDET_STB2_P3 GENMASK(8, 0)
+#define RG_SSUSB_RXDET_STB2_P3_VAL(x)  (0x1ff & (x))
+
+#define U3_PHYA_REG0   (SSUSB_SIFSLV_PHYA_BASE + 0x00)
+#define RG_PCIE_CLKDRV_OFFSET  GENMASK(3, 1)
+#define RG_PCIE_CLKDRV_OFFSET_VAL(x)   ((0x3 & (x)) << 2)
+
+#define U3_PHYA_REG1   (SSUSB_SIFSLV_PHYA_BASE + 0x04)
+#define RG_PCIE_CLKDRV_AMP GENMASK(31, 29)
+#define RG_PCIE_CLKDRV_AMP_VAL(x)  ((0x7 & (x)) << 29)
+
+#define DA_SSUSB_CDR_REFCK_SEL (SSUSB_SIFSLV_PHYA_DA_BASE + 0x00)
+#define RG_SSUSB_XTAL_EXT_PE1H GENMASK(13, 12)
+#define RG_SSUSB_XTAL_EXT_PE1H_VAL(x)  ((0x3 & (x)) << 12)
+#define RG_SSUSB_XTAL_EXT_PE2H GENMASK(17, 16)
+#define RG_SSUSB_XTAL_EXT_PE2H_VAL(x)  ((0x3 & (x)) << 16)
+
+#define DA_SSUSB_PLL_IC(SSUSB_SIFSLV_PHYA_DA_BASE + 
0x0c)
+#define RG_SSUSB_PLL_IC_PE2H   GENMASK(15, 12)
+#define RG_SSUSB_PLL_IC_PE2H_VAL(x)((0xf & (x)) << 12)
+#define RG_SSUSB_PLL_BR_PE2H   GENMASK(29, 28)
+#define RG_SSUSB_PLL_BR_PE2H_VAL(x)((0x3 & (x)) << 28)
+
+#define DA_SSUSB_PLL_BC(SSUSB_SIFSLV_PHYA_DA_BASE + 
0x08)
+#define RG_SSUSB_PLL_DIVEN_PE2HGENMASK(21, 19)
+#define RG_SSUSB_PLL_BC_PE2H   GENMASK(7, 6)
+#define RG_SSUSB_PLL_BC_PE2H_VAL(x)((0x3 & (x)) << 6)
+
+#define DA_SSUSB_PLL_IR(SSUSB_SIFSLV_PHYA_DA_BASE + 
0x10)
+#define RG_SSUSB_PLL_IR_PE2H   GENMASK(19, 16)
+#define RG_SSUSB_PLL_IR_PE2H_VAL(x)((0xf & (x)) << 16)
+
+#define DA_SSUSB_PLL_BP(SSUSB_SIFSLV_PHYA_DA_BASE + 
0x14)
+#define RG_SSUSB_PLL_BP_PE2H   GENMASK(19, 16)
+#define RG_SSUSB_PLL_BP_PE2H_VAL(x)((0xf & (x)) << 16)
+
+#define DA_SSUSB_PLL_SSC_DELTA1_REG20  (SSUSB_SIFSLV_PHYA_DA_BASE + 0x3c)
+#define 

[PATCH v3 0/2] Add PCIe phy driver for some Mediatek SoCs

[Ryder Lee]

Hi,

This patch series add PCIe phy driver and related dt-binding file for
Mediatek SoCs.

The PICe host driver has been applied to pci/host-mediatek for v4.13.

Changes since v3:
- rename both the driver and the binding document to make it more generic
  so that we could reuse the driver if needed in the future.
- correct some anotations.

Changes since v2:
- rebase to v4.12-rc1

Changes since v1:
- revise binding document:
  drop 'status' properties.
  add a description to 'phy-switch' property and add vendor prefix.

Ryder Lee (2):
  phy: add PCIe PHY driver for Mediatek SoCs
  dt-bindings: phy: Add documentation for Mediatek PCIe PHY

 .../devicetree/bindings/phy/phy-mediatek-pcie.txt  |  64 +
 drivers/phy/Kconfig|   8 +
 drivers/phy/Makefile   |   1 +
 drivers/phy/phy-mediatek-pcie.c| 290 +
 4 files changed, 363 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-mediatek-pcie.txt
 create mode 100644 drivers/phy/phy-mediatek-pcie.c

-- 
1.9.1

[PATCH v3 0/2] Add PCIe phy driver for some Mediatek SoCs

[Ryder Lee]

Hi,

This patch series add PCIe phy driver and related dt-binding file for
Mediatek SoCs.

The PICe host driver has been applied to pci/host-mediatek for v4.13.

Changes since v3:
- rename both the driver and the binding document to make it more generic
  so that we could reuse the driver if needed in the future.
- correct some anotations.

Changes since v2:
- rebase to v4.12-rc1

Changes since v1:
- revise binding document:
  drop 'status' properties.
  add a description to 'phy-switch' property and add vendor prefix.

Ryder Lee (2):
  phy: add PCIe PHY driver for Mediatek SoCs
  dt-bindings: phy: Add documentation for Mediatek PCIe PHY

 .../devicetree/bindings/phy/phy-mediatek-pcie.txt  |  64 +
 drivers/phy/Kconfig|   8 +
 drivers/phy/Makefile   |   1 +
 drivers/phy/phy-mediatek-pcie.c| 290 +
 4 files changed, 363 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-mediatek-pcie.txt
 create mode 100644 drivers/phy/phy-mediatek-pcie.c

-- 
1.9.1

[PATCH v3 2/2] dt-bindings: phy: Add documentation for Mediatek PCIe PHY

[Ryder Lee]

Add dt-binding information for Mediatek PCIe PHY

Signed-off-by: Ryder Lee 
Acked-by: Rob Herring 
---
 .../devicetree/bindings/phy/phy-mediatek-pcie.txt  | 64 ++
 1 file changed, 64 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-mediatek-pcie.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-mediatek-pcie.txt 
b/Documentation/devicetree/bindings/phy/phy-mediatek-pcie.txt
new file mode 100644
index 000..a9cf0dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-mediatek-pcie.txt
@@ -0,0 +1,64 @@
+Mediatek PCIe PHY
+---
+
+Required properties:
+ - compatible: should be one of
+   "mediatek,mt7623-pcie-phy"
+   "mediatek,mt2701-pcie-phy"
+ - reg: Base address and length of the registers.
+ - clocks: Must contain an entry in clock-names.
+   See ../clocks/clock-bindings.txt for details.
+ - clock-names: Must be "pciephya_ref"
+ - #phy-cells: Must be 0.
+
+Optional properties:
+ - mediatek,phy-switch: A phandle to the system controller, used to
+   enable the PCIe PHY function if needed.
+
+Example:
+
+   pcie0_phy: pcie-phy@1a149000 {
+   compatible = "mediatek,mt7623-pcie-phy";
+   reg = <0 0x1a149000 0 0x1000>;
+   clocks = <>;
+   clock-names = "pciephya_ref";
+   #phy-cells = <0>;
+   };
+
+   pcie1_phy: pcie-phy@1a14a000 {
+   compatible = "mediatek,mt7623-pcie-phy";
+   reg = <0 0x1a14a000 0 0x1000>;
+   clocks = <>;
+   clock-names = "pciephya_ref";
+   #phy-cells = <0>;
+   };
+
+   pcie2_phy: pcie-phy@1a244000 {
+   compatible = "mediatek,mt7623-pcie-phy";
+   reg = <0 0x1a244000 0 0x1000>;
+   clocks = <>;
+   clock-names = "pciephya_ref";
+   #phy-cells = <0>;
+
+   mediatek,phy-switch = <>;
+   };
+
+Specifying phy control of devices
+-
+
+Device nodes should specify the configuration required in their "phys"
+property, containing a phandle to the phy node and phy-names.
+
+Example:
+
+#include 
+
+pcie: pcie@1a14 {
+   ...
+   pcie@0,0 {
+   ...
+   phys = <_phy>;
+   phy-names = "pcie-phy0";
+   }
+   ...
+};
-- 
1.9.1

[PATCH v3 2/2] dt-bindings: phy: Add documentation for Mediatek PCIe PHY

[Ryder Lee]

Add dt-binding information for Mediatek PCIe PHY

Signed-off-by: Ryder Lee 
Acked-by: Rob Herring 
---
 .../devicetree/bindings/phy/phy-mediatek-pcie.txt  | 64 ++
 1 file changed, 64 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/phy-mediatek-pcie.txt

diff --git a/Documentation/devicetree/bindings/phy/phy-mediatek-pcie.txt 
b/Documentation/devicetree/bindings/phy/phy-mediatek-pcie.txt
new file mode 100644
index 000..a9cf0dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-mediatek-pcie.txt
@@ -0,0 +1,64 @@
+Mediatek PCIe PHY
+---
+
+Required properties:
+ - compatible: should be one of
+   "mediatek,mt7623-pcie-phy"
+   "mediatek,mt2701-pcie-phy"
+ - reg: Base address and length of the registers.
+ - clocks: Must contain an entry in clock-names.
+   See ../clocks/clock-bindings.txt for details.
+ - clock-names: Must be "pciephya_ref"
+ - #phy-cells: Must be 0.
+
+Optional properties:
+ - mediatek,phy-switch: A phandle to the system controller, used to
+   enable the PCIe PHY function if needed.
+
+Example:
+
+   pcie0_phy: pcie-phy@1a149000 {
+   compatible = "mediatek,mt7623-pcie-phy";
+   reg = <0 0x1a149000 0 0x1000>;
+   clocks = <>;
+   clock-names = "pciephya_ref";
+   #phy-cells = <0>;
+   };
+
+   pcie1_phy: pcie-phy@1a14a000 {
+   compatible = "mediatek,mt7623-pcie-phy";
+   reg = <0 0x1a14a000 0 0x1000>;
+   clocks = <>;
+   clock-names = "pciephya_ref";
+   #phy-cells = <0>;
+   };
+
+   pcie2_phy: pcie-phy@1a244000 {
+   compatible = "mediatek,mt7623-pcie-phy";
+   reg = <0 0x1a244000 0 0x1000>;
+   clocks = <>;
+   clock-names = "pciephya_ref";
+   #phy-cells = <0>;
+
+   mediatek,phy-switch = <>;
+   };
+
+Specifying phy control of devices
+-
+
+Device nodes should specify the configuration required in their "phys"
+property, containing a phandle to the phy node and phy-names.
+
+Example:
+
+#include 
+
+pcie: pcie@1a14 {
+   ...
+   pcie@0,0 {
+   ...
+   phys = <_phy>;
+   phy-names = "pcie-phy0";
+   }
+   ...
+};
-- 
1.9.1

[RFC PATCH 3/5] ARM: imx: add gpiod_lookup_table for spi chip-selects

[Chris Packham]

This is a preparatory step which will allow the conversion of
spi-imx.c to gpiod.

Signed-off-by: Chris Packham 
---
 arch/arm/mach-imx/mach-mx27_3ds.c | 21 +
 arch/arm/mach-imx/mach-pca100.c   | 13 +
 2 files changed, 34 insertions(+)

diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c 
b/arch/arm/mach-imx/mach-mx27_3ds.c
index 45e16bd7e2f2..46d67be124f0 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -22,6 +22,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -313,6 +314,15 @@ static struct imx_ssi_platform_data mx27_3ds_ssi_pdata = {
 };
 
 /* SPI */
+static struct gpiod_lookup_table spi1_cs_gpio_table = {
+   .dev_id = "spi.0",
+   .table = {
+   GPIO_LOOKUP("gpio-mxc", SPI1_SS0,
+   "spi-cs", GPIO_ACTIVE_HIGH),
+   { },
+   },
+};
+
 static int spi1_chipselect[] = {SPI1_SS0};
 
 static const struct spi_imx_master spi1_pdata __initconst = {
@@ -320,6 +330,15 @@ static const struct spi_imx_master spi1_pdata __initconst 
= {
.num_chipselect = ARRAY_SIZE(spi1_chipselect),
 };
 
+static struct gpiod_lookup_table spi2_cs_gpio_table = {
+   .dev_id = "spi.1",
+   .table = {
+   GPIO_LOOKUP("gpio-mxc", SPI2_SS0,
+   "spi-cs", GPIO_ACTIVE_HIGH),
+   { },
+   },
+};
+
 static int spi2_chipselect[] = {SPI2_SS0};
 
 static const struct spi_imx_master spi2_pdata __initconst = {
@@ -398,7 +417,9 @@ static void __init mx27pdk_init(void)
imx27_add_imx_keypad(_3ds_keymap_data);
imx27_add_imx2_wdt();
 
+   gpiod_add_lookup_table(_cs_gpio_table);
imx27_add_spi_imx1(_pdata);
+   gpiod_add_lookup_table(_cs_gpio_table);
imx27_add_spi_imx0(_pdata);
 
imx27_add_imx_i2c(0, _3ds_i2c0_data);
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index ed675863655b..8a2b5860f327 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -202,6 +203,17 @@ static struct spi_board_info pca100_spi_board_info[] 
__initdata = {
},
 };
 
+static struct gpiod_lookup_table pca100_spi_cs_gpio_table = {
+   .dev_id = "spi.0",
+   .table = {
+   GPIO_LOOKUP_IDX("gpio-mxc", SPI1_SS0,
+   "spi-cs", 0, GPIO_ACTIVE_HIGH),
+   GPIO_LOOKUP_IDX("gpio-mxc", SPI1_SS1,
+   "spi-cs", 1, GPIO_ACTIVE_HIGH),
+   { },
+   },
+};
+
 static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1};
 
 static const struct spi_imx_master pca100_spi0_data __initconst = {
@@ -376,6 +388,7 @@ static void __init pca100_init(void)
mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
spi_register_board_info(pca100_spi_board_info,
ARRAY_SIZE(pca100_spi_board_info));
+   gpiod_add_lookup_table(_spi_cs_gpio_table);
imx27_add_spi_imx0(_spi0_data);
 
imx27_add_imx_fb(_fb_data);
-- 
2.13.0

[RFC PATCH 0/5] spi: moving to struct gpio_desc

[Chris Packham]

This is my attempt to move spi over to using struct gpio_desc. I've
stopped at converting struct spi_master to gather some feedback.

ep93xx wasn't as hard as I'd expected so I'm pretty happy with those
changes. imx on the other hand has an annoying habit of conflating the GPIO
and native chip-select so I'm pretty sure that's broken.

I've compile tested ep93xx_defconfig and multi_v5_defconfig.

Looking ahead to converting struct spi_device there are a number of drivers
that re-use cs_gpio to reference the native chip-select so that still poses
issues I don't have a plan to solve. Happily most of the changes are deleting
code that requests the GPIO since that's now taken care of in core.

Chris Packham (5):
  spi: use gpio_desc instead of numeric gpio
  ARM: ep93xx: add gpiod_lookup_table for spi chip-selects
  ARM: imx: add gpiod_lookup_table for spi chip-selects
  spi: core: convert spi_master to use gpio_desc
  ARM: ep93xx: remove chipselect from ep93xx_spi_info

 arch/arm/mach-ep93xx/edb93xx.c   | 15 +++
 arch/arm/mach-ep93xx/simone.c| 14 ++
 arch/arm/mach-ep93xx/vision_ep9307.c | 20 ++--
 arch/arm/mach-imx/mach-mx27_3ds.c| 21 +
 arch/arm/mach-imx/mach-pca100.c  | 13 +
 drivers/spi/spi-ep93xx.c | 18 --
 drivers/spi/spi-imx.c| 25 +
 drivers/spi/spi-mt65xx.c | 13 -
 drivers/spi/spi.c| 29 +
 include/linux/platform_data/spi-ep93xx.h |  4 +---
 include/linux/spi/spi.h  |  2 +-
 11 files changed, 109 insertions(+), 65 deletions(-)

-- 
2.13.0

[RFC PATCH 3/5] ARM: imx: add gpiod_lookup_table for spi chip-selects

[Chris Packham]

This is a preparatory step which will allow the conversion of
spi-imx.c to gpiod.

Signed-off-by: Chris Packham 
---
 arch/arm/mach-imx/mach-mx27_3ds.c | 21 +
 arch/arm/mach-imx/mach-pca100.c   | 13 +
 2 files changed, 34 insertions(+)

diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c 
b/arch/arm/mach-imx/mach-mx27_3ds.c
index 45e16bd7e2f2..46d67be124f0 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -22,6 +22,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -313,6 +314,15 @@ static struct imx_ssi_platform_data mx27_3ds_ssi_pdata = {
 };
 
 /* SPI */
+static struct gpiod_lookup_table spi1_cs_gpio_table = {
+   .dev_id = "spi.0",
+   .table = {
+   GPIO_LOOKUP("gpio-mxc", SPI1_SS0,
+   "spi-cs", GPIO_ACTIVE_HIGH),
+   { },
+   },
+};
+
 static int spi1_chipselect[] = {SPI1_SS0};
 
 static const struct spi_imx_master spi1_pdata __initconst = {
@@ -320,6 +330,15 @@ static const struct spi_imx_master spi1_pdata __initconst 
= {
.num_chipselect = ARRAY_SIZE(spi1_chipselect),
 };
 
+static struct gpiod_lookup_table spi2_cs_gpio_table = {
+   .dev_id = "spi.1",
+   .table = {
+   GPIO_LOOKUP("gpio-mxc", SPI2_SS0,
+   "spi-cs", GPIO_ACTIVE_HIGH),
+   { },
+   },
+};
+
 static int spi2_chipselect[] = {SPI2_SS0};
 
 static const struct spi_imx_master spi2_pdata __initconst = {
@@ -398,7 +417,9 @@ static void __init mx27pdk_init(void)
imx27_add_imx_keypad(_3ds_keymap_data);
imx27_add_imx2_wdt();
 
+   gpiod_add_lookup_table(_cs_gpio_table);
imx27_add_spi_imx1(_pdata);
+   gpiod_add_lookup_table(_cs_gpio_table);
imx27_add_spi_imx0(_pdata);
 
imx27_add_imx_i2c(0, _3ds_i2c0_data);
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index ed675863655b..8a2b5860f327 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -202,6 +203,17 @@ static struct spi_board_info pca100_spi_board_info[] 
__initdata = {
},
 };
 
+static struct gpiod_lookup_table pca100_spi_cs_gpio_table = {
+   .dev_id = "spi.0",
+   .table = {
+   GPIO_LOOKUP_IDX("gpio-mxc", SPI1_SS0,
+   "spi-cs", 0, GPIO_ACTIVE_HIGH),
+   GPIO_LOOKUP_IDX("gpio-mxc", SPI1_SS1,
+   "spi-cs", 1, GPIO_ACTIVE_HIGH),
+   { },
+   },
+};
+
 static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1};
 
 static const struct spi_imx_master pca100_spi0_data __initconst = {
@@ -376,6 +388,7 @@ static void __init pca100_init(void)
mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
spi_register_board_info(pca100_spi_board_info,
ARRAY_SIZE(pca100_spi_board_info));
+   gpiod_add_lookup_table(_spi_cs_gpio_table);
imx27_add_spi_imx0(_spi0_data);
 
imx27_add_imx_fb(_fb_data);
-- 
2.13.0

[RFC PATCH 0/5] spi: moving to struct gpio_desc

[Chris Packham]

This is my attempt to move spi over to using struct gpio_desc. I've
stopped at converting struct spi_master to gather some feedback.

ep93xx wasn't as hard as I'd expected so I'm pretty happy with those
changes. imx on the other hand has an annoying habit of conflating the GPIO
and native chip-select so I'm pretty sure that's broken.

I've compile tested ep93xx_defconfig and multi_v5_defconfig.

Looking ahead to converting struct spi_device there are a number of drivers
that re-use cs_gpio to reference the native chip-select so that still poses
issues I don't have a plan to solve. Happily most of the changes are deleting
code that requests the GPIO since that's now taken care of in core.

Chris Packham (5):
  spi: use gpio_desc instead of numeric gpio
  ARM: ep93xx: add gpiod_lookup_table for spi chip-selects
  ARM: imx: add gpiod_lookup_table for spi chip-selects
  spi: core: convert spi_master to use gpio_desc
  ARM: ep93xx: remove chipselect from ep93xx_spi_info

 arch/arm/mach-ep93xx/edb93xx.c   | 15 +++
 arch/arm/mach-ep93xx/simone.c| 14 ++
 arch/arm/mach-ep93xx/vision_ep9307.c | 20 ++--
 arch/arm/mach-imx/mach-mx27_3ds.c| 21 +
 arch/arm/mach-imx/mach-pca100.c  | 13 +
 drivers/spi/spi-ep93xx.c | 18 --
 drivers/spi/spi-imx.c| 25 +
 drivers/spi/spi-mt65xx.c | 13 -
 drivers/spi/spi.c| 29 +
 include/linux/platform_data/spi-ep93xx.h |  4 +---
 include/linux/spi/spi.h  |  2 +-
 11 files changed, 109 insertions(+), 65 deletions(-)

-- 
2.13.0

[RFC PATCH 5/5] ARM: ep93xx: remove chipselect from ep93xx_spi_info

[Chris Packham]

Now that the driver has been updated to use gpiod there is no need to
have platform data to define the SPI chipselects. We still need to
define the number of chipselects used.

Signed-off-by: Chris Packham 
---
 arch/arm/mach-ep93xx/edb93xx.c   | 7 +--
 arch/arm/mach-ep93xx/simone.c| 7 +--
 arch/arm/mach-ep93xx/vision_ep9307.c | 9 +
 include/linux/platform_data/spi-ep93xx.h | 4 +---
 4 files changed, 4 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 9042adfe03de..b8d354fc27f5 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -127,13 +127,8 @@ static struct gpiod_lookup_table edb93xx_gpios_table = {
},
 };
 
-static int edb93xx_spi_chipselects[] __initdata = {
-   EP93XX_GPIO_LINE_EGPIO6,
-};
-
 static struct ep93xx_spi_info edb93xx_spi_info __initdata = {
-   .chipselect = edb93xx_spi_chipselects,
-   .num_chipselect = ARRAY_SIZE(edb93xx_spi_chipselects),
+   .num_chipselect = 1,
 };
 
 static void __init edb93xx_register_spi(void)
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index f297a7a89ed9..cb6bc2e1670a 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -129,13 +129,8 @@ static struct gpiod_lookup_table simone_gpios_table = {
},
 };
 
-static int simone_spi_chipselects[] __initdata = {
-   EP93XX_GPIO_LINE_EGPIO1,
-};
-
 static struct ep93xx_spi_info simone_spi_info __initdata = {
-   .chipselect = simone_spi_chipselects,
-   .num_chipselect = ARRAY_SIZE(simone_spi_chipselects),
+   .num_chipselect = 1,
.use_dma = 1,
 };
 
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c 
b/arch/arm/mach-ep93xx/vision_ep9307.c
index 3d9c66bbf2af..494c55080472 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -256,15 +256,8 @@ static struct gpiod_lookup_table vision_gpios_table = {
},
 };
 
-static int vision_spi_chipselects[] __initdata = {
-   EP93XX_GPIO_LINE_EGPIO6,
-   EP93XX_GPIO_LINE_EGPIO7,
-   EP93XX_GPIO_LINE_G(2),
-};
-
 static struct ep93xx_spi_info vision_spi_master __initdata = {
-   .chipselect = vision_spi_chipselects,
-   .num_chipselect = ARRAY_SIZE(vision_spi_chipselects),
+   .num_chipselect = 3,
.use_dma= 1,
 };
 
diff --git a/include/linux/platform_data/spi-ep93xx.h 
b/include/linux/platform_data/spi-ep93xx.h
index 171a271c2cbd..efcf33eff851 100644
--- a/include/linux/platform_data/spi-ep93xx.h
+++ b/include/linux/platform_data/spi-ep93xx.h
@@ -5,12 +5,10 @@ struct spi_device;
 
 /**
  * struct ep93xx_spi_info - EP93xx specific SPI descriptor
- * @chipselect: array of gpio numbers to use as chip selects
- * @num_chipselect: ARRAY_SIZE(chipselect)
+ * @num_chipselect: number chip selects supported
  * @use_dma: use DMA for the transfers
  */
 struct ep93xx_spi_info {
-   int *chipselect;
int num_chipselect;
booluse_dma;
 };
-- 
2.13.0

[RFC PATCH 5/5] ARM: ep93xx: remove chipselect from ep93xx_spi_info

[Chris Packham]

Now that the driver has been updated to use gpiod there is no need to
have platform data to define the SPI chipselects. We still need to
define the number of chipselects used.

Signed-off-by: Chris Packham 
---
 arch/arm/mach-ep93xx/edb93xx.c   | 7 +--
 arch/arm/mach-ep93xx/simone.c| 7 +--
 arch/arm/mach-ep93xx/vision_ep9307.c | 9 +
 include/linux/platform_data/spi-ep93xx.h | 4 +---
 4 files changed, 4 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 9042adfe03de..b8d354fc27f5 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -127,13 +127,8 @@ static struct gpiod_lookup_table edb93xx_gpios_table = {
},
 };
 
-static int edb93xx_spi_chipselects[] __initdata = {
-   EP93XX_GPIO_LINE_EGPIO6,
-};
-
 static struct ep93xx_spi_info edb93xx_spi_info __initdata = {
-   .chipselect = edb93xx_spi_chipselects,
-   .num_chipselect = ARRAY_SIZE(edb93xx_spi_chipselects),
+   .num_chipselect = 1,
 };
 
 static void __init edb93xx_register_spi(void)
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index f297a7a89ed9..cb6bc2e1670a 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -129,13 +129,8 @@ static struct gpiod_lookup_table simone_gpios_table = {
},
 };
 
-static int simone_spi_chipselects[] __initdata = {
-   EP93XX_GPIO_LINE_EGPIO1,
-};
-
 static struct ep93xx_spi_info simone_spi_info __initdata = {
-   .chipselect = simone_spi_chipselects,
-   .num_chipselect = ARRAY_SIZE(simone_spi_chipselects),
+   .num_chipselect = 1,
.use_dma = 1,
 };
 
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c 
b/arch/arm/mach-ep93xx/vision_ep9307.c
index 3d9c66bbf2af..494c55080472 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -256,15 +256,8 @@ static struct gpiod_lookup_table vision_gpios_table = {
},
 };
 
-static int vision_spi_chipselects[] __initdata = {
-   EP93XX_GPIO_LINE_EGPIO6,
-   EP93XX_GPIO_LINE_EGPIO7,
-   EP93XX_GPIO_LINE_G(2),
-};
-
 static struct ep93xx_spi_info vision_spi_master __initdata = {
-   .chipselect = vision_spi_chipselects,
-   .num_chipselect = ARRAY_SIZE(vision_spi_chipselects),
+   .num_chipselect = 3,
.use_dma= 1,
 };
 
diff --git a/include/linux/platform_data/spi-ep93xx.h 
b/include/linux/platform_data/spi-ep93xx.h
index 171a271c2cbd..efcf33eff851 100644
--- a/include/linux/platform_data/spi-ep93xx.h
+++ b/include/linux/platform_data/spi-ep93xx.h
@@ -5,12 +5,10 @@ struct spi_device;
 
 /**
  * struct ep93xx_spi_info - EP93xx specific SPI descriptor
- * @chipselect: array of gpio numbers to use as chip selects
- * @num_chipselect: ARRAY_SIZE(chipselect)
+ * @num_chipselect: number chip selects supported
  * @use_dma: use DMA for the transfers
  */
 struct ep93xx_spi_info {
-   int *chipselect;
int num_chipselect;
booluse_dma;
 };
-- 
2.13.0

[RFC PATCH 4/5] spi: core: convert spi_master to use gpio_desc

[Chris Packham]

Instead of numeric gpios make struct spi_master hold an array of struct
gpio_desc. For now struct spi_device still maintains a numeric gpio
which will be updated in a subsequent change.

Signed-off-by: Chris Packham 
---
 drivers/spi/spi-ep93xx.c | 18 --
 drivers/spi/spi-imx.c| 25 +
 drivers/spi/spi-mt65xx.c | 13 -
 drivers/spi/spi.c| 24 +---
 include/linux/spi/spi.h  |  2 +-
 5 files changed, 35 insertions(+), 47 deletions(-)

diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c
index b5d766064b7b..8ff795e65b38 100644
--- a/drivers/spi/spi-ep93xx.c
+++ b/drivers/spi/spi-ep93xx.c
@@ -816,7 +816,7 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
 
master->num_chipselect = info->num_chipselect;
master->cs_gpios = devm_kzalloc(>dev,
-   sizeof(int) * master->num_chipselect,
+   sizeof(*master->cs_gpios) * 
master->num_chipselect,
GFP_KERNEL);
if (!master->cs_gpios) {
error = -ENOMEM;
@@ -824,19 +824,17 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
}
 
for (i = 0; i < master->num_chipselect; i++) {
-   master->cs_gpios[i] = info->chipselect[i];
+   struct gpio_desc *cs;
 
-   if (!gpio_is_valid(master->cs_gpios[i]))
-   continue;
-
-   error = devm_gpio_request_one(>dev, master->cs_gpios[i],
- GPIOF_OUT_INIT_HIGH,
- "ep93xx-spi");
-   if (error) {
+   cs = devm_gpiod_get_index(>dev, "spi-cs", i,
+ GPIOD_OUT_HIGH);
+   if (IS_ERR(cs)) {
dev_err(>dev, "could not request cs gpio %d\n",
-   master->cs_gpios[i]);
+   i);
+   error = PTR_ERR(cs);
goto fail_release_master;
}
+   master->cs_gpios[i] = cs;
}
 
platform_set_drvdata(pdev, master);
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 19b30cf7d2b7..efbf03ac7cf1 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -1360,12 +1360,18 @@ static int spi_imx_probe(struct platform_device *pdev)
if (mxc_platform_info) {
master->num_chipselect = mxc_platform_info->num_chipselect;
master->cs_gpios = devm_kzalloc(>dev,
-   sizeof(int) * master->num_chipselect, GFP_KERNEL);
+   sizeof(*master->cs_gpios) * master->num_chipselect, 
GFP_KERNEL);
if (!master->cs_gpios)
return -ENOMEM;
 
-   for (i = 0; i < master->num_chipselect; i++)
-   master->cs_gpios[i] = mxc_platform_info->chipselect[i];
+   for (i = 0; i < master->num_chipselect; i++) {
+   struct gpio_desc *cs;
+
+   cs = devm_gpiod_get_index(>dev, "spi-cs", i,
+ GPIOD_OUT_HIGH);
+   if (!IS_ERR(cs))
+   master->cs_gpios[i] = cs;
+   }
}
 
spi_imx->bitbang.chipselect = spi_imx_chipselect;
@@ -1456,19 +1462,6 @@ static int spi_imx_probe(struct platform_device *pdev)
goto out_clk_put;
}
 
-   for (i = 0; i < master->num_chipselect; i++) {
-   if (!gpio_is_valid(master->cs_gpios[i]))
-   continue;
-
-   ret = devm_gpio_request(>dev, master->cs_gpios[i],
-   DRIVER_NAME);
-   if (ret) {
-   dev_err(>dev, "Can't get CS GPIO %i\n",
-   master->cs_gpios[i]);
-   goto out_clk_put;
-   }
-   }
-
dev_info(>dev, "probed\n");
 
clk_disable(spi_imx->clk_ipg);
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 278867a31950..36e0d865fd02 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -681,19 +681,6 @@ static int mtk_spi_probe(struct platform_device *pdev)
ret = -EINVAL;
goto err_disable_runtime_pm;
}
-
-   if (master->cs_gpios) {
-   for (i = 0; i < master->num_chipselect; i++) {
-   ret = devm_gpio_request(>dev,
-   master->cs_gpios[i],
-   dev_name(>dev));
-   if (ret) {
-   dev_err(>dev,
- 

[RFC PATCH 1/5] spi: use gpio_desc instead of numeric gpio

[Chris Packham]

By using a gpio_desc and gpiod_set_value() instead of a numeric gpio and
gpio_set_value() the gpio flags are taken into account. This is useful
when using a gpio chip-select to supplement a controllers native
chip-select.

Signed-off-by: Chris Packham 
---
(I've included this in this series for context, ultimately it should not be
needed once everything is using gpio_desc)

My specific use-case is I have a board that uses the spi-orion driver but
only has one CS pin available. In order to access two spi slave devices the
board has a 1-of-2 decoder/demultiplexer which is driven via a gpio.

The problem is that for one of the 2 slave devices the gpio level required
is opposite to the chip-select so I can't simply specify "spi-cs-high".
With this change I can flag the gpio as active low and the gpio subsystem
takes care of the additional inversion required.

 drivers/spi/spi.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 6f87fec409b5..b39c0f9956dd 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -725,7 +725,10 @@ static void spi_set_cs(struct spi_device *spi, bool enable)
enable = !enable;
 
if (gpio_is_valid(spi->cs_gpio)) {
-   gpio_set_value(spi->cs_gpio, !enable);
+   struct gpio_desc *gpio = gpio_to_desc(spi->cs_gpio);
+
+   if (gpio)
+   gpiod_set_value(gpio, !enable);
/* Some SPI masters need both GPIO CS & slave_select */
if ((spi->master->flags & SPI_MASTER_GPIO_SS) &&
spi->master->set_cs)
-- 
2.13.0

[RFC PATCH 4/5] spi: core: convert spi_master to use gpio_desc

[Chris Packham]

Instead of numeric gpios make struct spi_master hold an array of struct
gpio_desc. For now struct spi_device still maintains a numeric gpio
which will be updated in a subsequent change.

Signed-off-by: Chris Packham 
---
 drivers/spi/spi-ep93xx.c | 18 --
 drivers/spi/spi-imx.c| 25 +
 drivers/spi/spi-mt65xx.c | 13 -
 drivers/spi/spi.c| 24 +---
 include/linux/spi/spi.h  |  2 +-
 5 files changed, 35 insertions(+), 47 deletions(-)

diff --git a/drivers/spi/spi-ep93xx.c b/drivers/spi/spi-ep93xx.c
index b5d766064b7b..8ff795e65b38 100644
--- a/drivers/spi/spi-ep93xx.c
+++ b/drivers/spi/spi-ep93xx.c
@@ -816,7 +816,7 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
 
master->num_chipselect = info->num_chipselect;
master->cs_gpios = devm_kzalloc(>dev,
-   sizeof(int) * master->num_chipselect,
+   sizeof(*master->cs_gpios) * 
master->num_chipselect,
GFP_KERNEL);
if (!master->cs_gpios) {
error = -ENOMEM;
@@ -824,19 +824,17 @@ static int ep93xx_spi_probe(struct platform_device *pdev)
}
 
for (i = 0; i < master->num_chipselect; i++) {
-   master->cs_gpios[i] = info->chipselect[i];
+   struct gpio_desc *cs;
 
-   if (!gpio_is_valid(master->cs_gpios[i]))
-   continue;
-
-   error = devm_gpio_request_one(>dev, master->cs_gpios[i],
- GPIOF_OUT_INIT_HIGH,
- "ep93xx-spi");
-   if (error) {
+   cs = devm_gpiod_get_index(>dev, "spi-cs", i,
+ GPIOD_OUT_HIGH);
+   if (IS_ERR(cs)) {
dev_err(>dev, "could not request cs gpio %d\n",
-   master->cs_gpios[i]);
+   i);
+   error = PTR_ERR(cs);
goto fail_release_master;
}
+   master->cs_gpios[i] = cs;
}
 
platform_set_drvdata(pdev, master);
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 19b30cf7d2b7..efbf03ac7cf1 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -1360,12 +1360,18 @@ static int spi_imx_probe(struct platform_device *pdev)
if (mxc_platform_info) {
master->num_chipselect = mxc_platform_info->num_chipselect;
master->cs_gpios = devm_kzalloc(>dev,
-   sizeof(int) * master->num_chipselect, GFP_KERNEL);
+   sizeof(*master->cs_gpios) * master->num_chipselect, 
GFP_KERNEL);
if (!master->cs_gpios)
return -ENOMEM;
 
-   for (i = 0; i < master->num_chipselect; i++)
-   master->cs_gpios[i] = mxc_platform_info->chipselect[i];
+   for (i = 0; i < master->num_chipselect; i++) {
+   struct gpio_desc *cs;
+
+   cs = devm_gpiod_get_index(>dev, "spi-cs", i,
+ GPIOD_OUT_HIGH);
+   if (!IS_ERR(cs))
+   master->cs_gpios[i] = cs;
+   }
}
 
spi_imx->bitbang.chipselect = spi_imx_chipselect;
@@ -1456,19 +1462,6 @@ static int spi_imx_probe(struct platform_device *pdev)
goto out_clk_put;
}
 
-   for (i = 0; i < master->num_chipselect; i++) {
-   if (!gpio_is_valid(master->cs_gpios[i]))
-   continue;
-
-   ret = devm_gpio_request(>dev, master->cs_gpios[i],
-   DRIVER_NAME);
-   if (ret) {
-   dev_err(>dev, "Can't get CS GPIO %i\n",
-   master->cs_gpios[i]);
-   goto out_clk_put;
-   }
-   }
-
dev_info(>dev, "probed\n");
 
clk_disable(spi_imx->clk_ipg);
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 278867a31950..36e0d865fd02 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -681,19 +681,6 @@ static int mtk_spi_probe(struct platform_device *pdev)
ret = -EINVAL;
goto err_disable_runtime_pm;
}
-
-   if (master->cs_gpios) {
-   for (i = 0; i < master->num_chipselect; i++) {
-   ret = devm_gpio_request(>dev,
-   master->cs_gpios[i],
-   dev_name(>dev));
-   if (ret) {
-   dev_err(>dev,
-   "can't get CS GPIO 

[RFC PATCH 1/5] spi: use gpio_desc instead of numeric gpio

[Chris Packham]

By using a gpio_desc and gpiod_set_value() instead of a numeric gpio and
gpio_set_value() the gpio flags are taken into account. This is useful
when using a gpio chip-select to supplement a controllers native
chip-select.

Signed-off-by: Chris Packham 
---
(I've included this in this series for context, ultimately it should not be
needed once everything is using gpio_desc)

My specific use-case is I have a board that uses the spi-orion driver but
only has one CS pin available. In order to access two spi slave devices the
board has a 1-of-2 decoder/demultiplexer which is driven via a gpio.

The problem is that for one of the 2 slave devices the gpio level required
is opposite to the chip-select so I can't simply specify "spi-cs-high".
With this change I can flag the gpio as active low and the gpio subsystem
takes care of the additional inversion required.

 drivers/spi/spi.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 6f87fec409b5..b39c0f9956dd 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -725,7 +725,10 @@ static void spi_set_cs(struct spi_device *spi, bool enable)
enable = !enable;
 
if (gpio_is_valid(spi->cs_gpio)) {
-   gpio_set_value(spi->cs_gpio, !enable);
+   struct gpio_desc *gpio = gpio_to_desc(spi->cs_gpio);
+
+   if (gpio)
+   gpiod_set_value(gpio, !enable);
/* Some SPI masters need both GPIO CS & slave_select */
if ((spi->master->flags & SPI_MASTER_GPIO_SS) &&
spi->master->set_cs)
-- 
2.13.0

[RFC PATCH 2/5] ARM: ep93xx: add gpiod_lookup_table for spi chip-selects

[Chris Packham]

This is a preparatory step which will allow the conversion of
spi-ep93xx.c to gpiod.

Signed-off-by: Chris Packham 
---
 arch/arm/mach-ep93xx/edb93xx.c   | 12 
 arch/arm/mach-ep93xx/simone.c| 11 +++
 arch/arm/mach-ep93xx/vision_ep9307.c | 15 +++
 3 files changed, 38 insertions(+)

diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 0ac176386789..9042adfe03de 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -27,6 +27,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -116,6 +118,15 @@ static struct spi_board_info edb93xx_spi_board_info[] 
__initdata = {
},
 };
 
+static struct gpiod_lookup_table edb93xx_gpios_table = {
+   .dev_id = "spi.0",
+   .table = {
+   GPIO_LOOKUP("gpio-ep93xx", EP93XX_GPIO_LINE_EGPIO6,
+   "spi-cs", GPIO_ACTIVE_HIGH),
+   {},
+   },
+};
+
 static int edb93xx_spi_chipselects[] __initdata = {
EP93XX_GPIO_LINE_EGPIO6,
 };
@@ -134,6 +145,7 @@ static void __init edb93xx_register_spi(void)
else if (machine_is_edb9315a())
edb93xx_cs4271_data.gpio_nreset = EP93XX_GPIO_LINE_EGPIO14;
 
+   gpiod_add_lookup_table(_gpios_table);
ep93xx_register_spi(_spi_info, edb93xx_spi_board_info,
ARRAY_SIZE(edb93xx_spi_board_info));
 }
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index c7a40f245892..f297a7a89ed9 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -119,6 +120,15 @@ static struct spi_board_info simone_spi_devices[] 
__initdata = {
  * low between multi-message command blocks. From v1.4, it uses a GPIO instead.
  * v1.3 parts will still work, since the signal on SFRMOUT is automatic.
  */
+static struct gpiod_lookup_table simone_gpios_table = {
+   .dev_id = "spi.0",
+   .table = {
+   GPIO_LOOKUP("gpio-ep93xx", EP93XX_GPIO_LINE_EGPIO1,
+   "spi-cs", GPIO_ACTIVE_HIGH),
+   {},
+   },
+};
+
 static int simone_spi_chipselects[] __initdata = {
EP93XX_GPIO_LINE_EGPIO1,
 };
@@ -163,6 +173,7 @@ static void __init simone_init_machine(void)
ep93xx_register_fb(_fb_info);
ep93xx_register_i2c(_i2c_gpio_data, simone_i2c_board_info,
ARRAY_SIZE(simone_i2c_board_info));
+   gpiod_add_lookup_table(_gpios_table);
ep93xx_register_spi(_spi_info, simone_spi_devices,
ARRAY_SIZE(simone_spi_devices));
simone_register_audio();
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c 
b/arch/arm/mach-ep93xx/vision_ep9307.c
index 1daf9441058c..3d9c66bbf2af 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -242,6 +243,19 @@ static struct spi_board_info vision_spi_board_info[] 
__initdata = {
},
 };
 
+static struct gpiod_lookup_table vision_gpios_table = {
+   .dev_id = "spi.0",
+   .table = {
+   GPIO_LOOKUP_IDX("gpio-ep93xx", EP93XX_GPIO_LINE_EGPIO6,
+   "spi-cs", 0, GPIO_ACTIVE_HIGH),
+   GPIO_LOOKUP_IDX("gpio-ep93xx", EP93XX_GPIO_LINE_EGPIO7,
+   "spi-cs", 1, GPIO_ACTIVE_HIGH),
+   GPIO_LOOKUP_IDX("gpio-ep93xx", EP93XX_GPIO_LINE_G(2),
+   "spi-cs", 2, GPIO_ACTIVE_HIGH),
+   {},
+   },
+};
+
 static int vision_spi_chipselects[] __initdata = {
EP93XX_GPIO_LINE_EGPIO6,
EP93XX_GPIO_LINE_EGPIO7,
@@ -291,6 +305,7 @@ static void __init vision_init_machine(void)
 
ep93xx_register_i2c(_i2c_gpio_data, vision_i2c_info,
ARRAY_SIZE(vision_i2c_info));
+   gpiod_add_lookup_table(_gpios_table);
ep93xx_register_spi(_spi_master, vision_spi_board_info,
ARRAY_SIZE(vision_spi_board_info));
vision_register_i2s();
-- 
2.13.0

[RFC PATCH 2/5] ARM: ep93xx: add gpiod_lookup_table for spi chip-selects

[Chris Packham]

This is a preparatory step which will allow the conversion of
spi-ep93xx.c to gpiod.

Signed-off-by: Chris Packham 
---
 arch/arm/mach-ep93xx/edb93xx.c   | 12 
 arch/arm/mach-ep93xx/simone.c| 11 +++
 arch/arm/mach-ep93xx/vision_ep9307.c | 15 +++
 3 files changed, 38 insertions(+)

diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 0ac176386789..9042adfe03de 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -27,6 +27,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
@@ -116,6 +118,15 @@ static struct spi_board_info edb93xx_spi_board_info[] 
__initdata = {
},
 };
 
+static struct gpiod_lookup_table edb93xx_gpios_table = {
+   .dev_id = "spi.0",
+   .table = {
+   GPIO_LOOKUP("gpio-ep93xx", EP93XX_GPIO_LINE_EGPIO6,
+   "spi-cs", GPIO_ACTIVE_HIGH),
+   {},
+   },
+};
+
 static int edb93xx_spi_chipselects[] __initdata = {
EP93XX_GPIO_LINE_EGPIO6,
 };
@@ -134,6 +145,7 @@ static void __init edb93xx_register_spi(void)
else if (machine_is_edb9315a())
edb93xx_cs4271_data.gpio_nreset = EP93XX_GPIO_LINE_EGPIO14;
 
+   gpiod_add_lookup_table(_gpios_table);
ep93xx_register_spi(_spi_info, edb93xx_spi_board_info,
ARRAY_SIZE(edb93xx_spi_board_info));
 }
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index c7a40f245892..f297a7a89ed9 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -119,6 +120,15 @@ static struct spi_board_info simone_spi_devices[] 
__initdata = {
  * low between multi-message command blocks. From v1.4, it uses a GPIO instead.
  * v1.3 parts will still work, since the signal on SFRMOUT is automatic.
  */
+static struct gpiod_lookup_table simone_gpios_table = {
+   .dev_id = "spi.0",
+   .table = {
+   GPIO_LOOKUP("gpio-ep93xx", EP93XX_GPIO_LINE_EGPIO1,
+   "spi-cs", GPIO_ACTIVE_HIGH),
+   {},
+   },
+};
+
 static int simone_spi_chipselects[] __initdata = {
EP93XX_GPIO_LINE_EGPIO1,
 };
@@ -163,6 +173,7 @@ static void __init simone_init_machine(void)
ep93xx_register_fb(_fb_info);
ep93xx_register_i2c(_i2c_gpio_data, simone_i2c_board_info,
ARRAY_SIZE(simone_i2c_board_info));
+   gpiod_add_lookup_table(_gpios_table);
ep93xx_register_spi(_spi_info, simone_spi_devices,
ARRAY_SIZE(simone_spi_devices));
simone_register_audio();
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c 
b/arch/arm/mach-ep93xx/vision_ep9307.c
index 1daf9441058c..3d9c66bbf2af 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -242,6 +243,19 @@ static struct spi_board_info vision_spi_board_info[] 
__initdata = {
},
 };
 
+static struct gpiod_lookup_table vision_gpios_table = {
+   .dev_id = "spi.0",
+   .table = {
+   GPIO_LOOKUP_IDX("gpio-ep93xx", EP93XX_GPIO_LINE_EGPIO6,
+   "spi-cs", 0, GPIO_ACTIVE_HIGH),
+   GPIO_LOOKUP_IDX("gpio-ep93xx", EP93XX_GPIO_LINE_EGPIO7,
+   "spi-cs", 1, GPIO_ACTIVE_HIGH),
+   GPIO_LOOKUP_IDX("gpio-ep93xx", EP93XX_GPIO_LINE_G(2),
+   "spi-cs", 2, GPIO_ACTIVE_HIGH),
+   {},
+   },
+};
+
 static int vision_spi_chipselects[] __initdata = {
EP93XX_GPIO_LINE_EGPIO6,
EP93XX_GPIO_LINE_EGPIO7,
@@ -291,6 +305,7 @@ static void __init vision_init_machine(void)
 
ep93xx_register_i2c(_i2c_gpio_data, vision_i2c_info,
ARRAY_SIZE(vision_i2c_info));
+   gpiod_add_lookup_table(_gpios_table);
ep93xx_register_spi(_spi_master, vision_spi_board_info,
ARRAY_SIZE(vision_spi_board_info));
vision_register_i2s();
-- 
2.13.0

Re: [PATCH v2] firmware: fix sending -ERESTARTSYS due to signal on fallback

[Andy Lutomirski]

On Wed, May 24, 2017 at 3:38 PM, Luis R. Rodriguez  wrote:
> On Wed, May 24, 2017 at 3:00 PM, Andy Lutomirski  wrote:
>> On Wed, May 24, 2017 at 2:40 PM, Luis R. Rodriguez  wrote:
>>> From: Martin Fuzzey 
>>>
>>> Commit 0cb64249ca500 ("firmware_loader: abort request if wait_for_completion
>>> is interrupted") added via 4.0 added support to abort the fallback mechanism
>>> when a signal was detected and wait_for_completion_interruptible() returned
>>> -ERESTARTSYS. Although the abort was effective we were unfortunately never
>>> really propagating this error though and as such userspace could not know
>>> why the abort happened.
>>
>> Can you give a simple example of what's going on and why it matters?
>>
>> ERESTARTSYS and friends are highly magical, and I'm not convinced that
>> allowing _request_firmware_load to return -ERESTARTSYS is actually a
>> good idea.  What if there are system calls that can't handle this
>> style of restart that start being restarted as a result?
>
> This seems to be a linux-api question, so Cc'ing them and Michael.
>
> For those not familiar it is worth explaining first the user interface.
>
> This describes the fallback mechanism of the Linux firmware API if
> direct filesystem lookup fails.

...

> While we wait we can get a
> -ERESTARTSYS since swait_event_interruptible_timeout() uses
> __swait_event_interruptible_timeout() under the hood and this in turn
> ___swait_event() which can prepare_to_swait_event() which can return
> -ERESTARTSYS on signal_pending_state().

This is too much kernel detail and too little ABI detail.

User code does some syscall.  Kernel requests firmware and that
request gets interrupted.  What syscall is this?  read(2)?  open(2)?
Something else?

mutex_lock_interruptible() returns -EINTR if interrupted.  It seems
odd to be that requesting firmware would be different.

>
> The issue discovered was that Android could issue SIGCHLD and the
> waiter gets a signal but the reason for the exact reason for the
> failure is not propagated. The proposed patch propagates -ERESTARTSYS
> when that is returned on signal_pending_state() as we wait.

Maybe SIGCHLD shouldn't interrupt firmware loading?

Re: [PATCH v2] firmware: fix sending -ERESTARTSYS due to signal on fallback

[Andy Lutomirski]

On Wed, May 24, 2017 at 3:38 PM, Luis R. Rodriguez  wrote:
> On Wed, May 24, 2017 at 3:00 PM, Andy Lutomirski  wrote:
>> On Wed, May 24, 2017 at 2:40 PM, Luis R. Rodriguez  wrote:
>>> From: Martin Fuzzey 
>>>
>>> Commit 0cb64249ca500 ("firmware_loader: abort request if wait_for_completion
>>> is interrupted") added via 4.0 added support to abort the fallback mechanism
>>> when a signal was detected and wait_for_completion_interruptible() returned
>>> -ERESTARTSYS. Although the abort was effective we were unfortunately never
>>> really propagating this error though and as such userspace could not know
>>> why the abort happened.
>>
>> Can you give a simple example of what's going on and why it matters?
>>
>> ERESTARTSYS and friends are highly magical, and I'm not convinced that
>> allowing _request_firmware_load to return -ERESTARTSYS is actually a
>> good idea.  What if there are system calls that can't handle this
>> style of restart that start being restarted as a result?
>
> This seems to be a linux-api question, so Cc'ing them and Michael.
>
> For those not familiar it is worth explaining first the user interface.
>
> This describes the fallback mechanism of the Linux firmware API if
> direct filesystem lookup fails.

...

> While we wait we can get a
> -ERESTARTSYS since swait_event_interruptible_timeout() uses
> __swait_event_interruptible_timeout() under the hood and this in turn
> ___swait_event() which can prepare_to_swait_event() which can return
> -ERESTARTSYS on signal_pending_state().

This is too much kernel detail and too little ABI detail.

User code does some syscall.  Kernel requests firmware and that
request gets interrupted.  What syscall is this?  read(2)?  open(2)?
Something else?

mutex_lock_interruptible() returns -EINTR if interrupted.  It seems
odd to be that requesting firmware would be different.

>
> The issue discovered was that Android could issue SIGCHLD and the
> waiter gets a signal but the reason for the exact reason for the
> failure is not propagated. The proposed patch propagates -ERESTARTSYS
> when that is returned on signal_pending_state() as we wait.

Maybe SIGCHLD shouldn't interrupt firmware loading?

Re: [PATCH] sparc64: Add 16GB hugepage support

[Nitin Gupta]

On 5/24/17 8:45 PM, David Miller wrote:
> From: Paul Gortmaker 
> Date: Wed, 24 May 2017 23:34:42 -0400
> 
>> [[PATCH] sparc64: Add 16GB hugepage support] On 24/05/2017 (Wed 17:29) Nitin 
>> Gupta wrote:
>>
>>> Orabug: 25362942
>>>
>>> Signed-off-by: Nitin Gupta 
>>
>> If this wasn't an accidental git send-email misfire, then there should
>> be a long log indicating the use case, the perforamnce increase, the
>> testing that was done, etc. etc. 
>>
>> Normally I'd not notice but since I was Cc'd I figured it was worth a
>> mention -- for example the vendor ID above doesn't mean a thing to
>> all the rest of us, hence why I suspect it was a git send-email misfire;
>> sadly, I think we've all accidentally done that at least once
> 
> Agreed.
> 
> No commit message whatsoever is basically unacceptable for something
> like this.
>

Ok, I will include usage, testing notes, performance numbers etc., in
v2 patch. Still, I do try to include "Orabug" for better tracking of
bugs internally; I hope that's okay.

Thanks,
Nitin

Re: [PATCH] sparc64: Add 16GB hugepage support

[Nitin Gupta]

On 5/24/17 8:45 PM, David Miller wrote:
> From: Paul Gortmaker 
> Date: Wed, 24 May 2017 23:34:42 -0400
> 
>> [[PATCH] sparc64: Add 16GB hugepage support] On 24/05/2017 (Wed 17:29) Nitin 
>> Gupta wrote:
>>
>>> Orabug: 25362942
>>>
>>> Signed-off-by: Nitin Gupta 
>>
>> If this wasn't an accidental git send-email misfire, then there should
>> be a long log indicating the use case, the perforamnce increase, the
>> testing that was done, etc. etc. 
>>
>> Normally I'd not notice but since I was Cc'd I figured it was worth a
>> mention -- for example the vendor ID above doesn't mean a thing to
>> all the rest of us, hence why I suspect it was a git send-email misfire;
>> sadly, I think we've all accidentally done that at least once
> 
> Agreed.
> 
> No commit message whatsoever is basically unacceptable for something
> like this.
>

Ok, I will include usage, testing notes, performance numbers etc., in
v2 patch. Still, I do try to include "Orabug" for better tracking of
bugs internally; I hope that's okay.

Thanks,
Nitin

[PATCH v4 2/9] dt-bindings: arm: mediatek: add bindings for mediatek MT7623a SoC Platform

[sean.wang]

From: Sean Wang 

This adds DT binding documentation for Mediatek MT7623a

Signed-off-by: Sean Wang 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/arm/mediatek.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index 0924b62..412c6bd 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -13,6 +13,7 @@ compatible: Must contain one of
"mediatek,mt6755"
"mediatek,mt6795"
"mediatek,mt7623" which is referred to MT7623N SoC
+   "mediatek,mt7623a"
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
-- 
2.7.4

[PATCH v4 2/9] dt-bindings: arm: mediatek: add bindings for mediatek MT7623a SoC Platform

[sean.wang]

From: Sean Wang 

This adds DT binding documentation for Mediatek MT7623a

Signed-off-by: Sean Wang 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/arm/mediatek.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index 0924b62..412c6bd 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -13,6 +13,7 @@ compatible: Must contain one of
"mediatek,mt6755"
"mediatek,mt6795"
"mediatek,mt7623" which is referred to MT7623N SoC
+   "mediatek,mt7623a"
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
-- 
2.7.4

[PATCH v4 0/9] arm: dts: extend mt7623 support

[sean.wang]

From: Sean Wang 

Changes since v3:
- explain in the commit message why this binding is changed
- patches for dt-binding is reordered at the beginning of patch list
- be concise wigh using SPDX-License-Identifier in new dts file

Changes since v2:
- exclude those patch are already queued into v4.11-next/dts32
- exclude those patches already sent in separation
- add mt7623a SoC basic support
- update binding SoC for mt7623n and relevant boards

Changes since v1:
Continue the upstream journey based on the previous John Crispin's good work.
- add fixes for the v1 suggestion
- fix typo in the commit log
- add missing pinctrl bindings for mt7623
- reuse pinctrl driver for mt7623
- enhance existing nodes since the way for binding is changed e.g USB
- add more nodes which already gets support from the latest tree e.g MT7530 DSA
- add the dts file for Bananapi R2 (BPI-R2) board

John Crispin (4):
  arm: dts: mt7623: add mt7623-mt6323.dtsi file
  arm: dts: mt7623: cleanup the mt7623n rfb uart nodes
  arm: dts: mt7623: enable the usb device on the mt7623n rfb
  arm: dts: mt7623: enable the nand device on the mt7623n nand rfb

Sean Wang (5):
  dt-bindings: arm: mediatek: update for MT7623n SoC and relevant boards
  dt-bindings: arm: mediatek: add bindings for mediatek MT7623a SoC
Platform
  arm: dts: mt7623: rename mt7623-evb.dts to
arch/arm/boot/dts/mt7623n-rfb.dtsi
  ARM: mediatek: add MT7623a smp bringup code
  arm: dts: mt7623: add dts file for Bananapi R2 (BPI-R2) board

 Documentation/devicetree/bindings/arm/mediatek.txt |  11 +-
 arch/arm/boot/dts/Makefile |   3 +-
 arch/arm/boot/dts/mt7623-evb.dts   |  33 --
 arch/arm/boot/dts/mt7623-mt6323.dtsi   | 269 +
 arch/arm/boot/dts/mt7623.dtsi  |   8 +-
 arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts  | 440 +
 arch/arm/boot/dts/mt7623n-rfb-nand.dts | 109 +
 arch/arm/boot/dts/mt7623n-rfb.dtsi |  61 +++
 arch/arm/mach-mediatek/mediatek.c  |   2 +
 arch/arm/mach-mediatek/platsmp.c   |   1 +
 10 files changed, 895 insertions(+), 42 deletions(-)
 delete mode 100644 arch/arm/boot/dts/mt7623-evb.dts
 create mode 100644 arch/arm/boot/dts/mt7623-mt6323.dtsi
 create mode 100644 arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
 create mode 100644 arch/arm/boot/dts/mt7623n-rfb-nand.dts
 create mode 100644 arch/arm/boot/dts/mt7623n-rfb.dtsi

-- 
2.7.4

[PATCH v4 1/9] dt-bindings: arm: mediatek: update for MT7623n SoC and relevant boards

[sean.wang]

From: Sean Wang 

Because there are two versions of MT7623 SoC that is MT7623a and MT7623n
respectively. So update the part of MT7623n bindings to allow that people
tend to differentiate which MT7623 SoC the boards applies.

And "mediatek,mt7623-evb" can be safely changed to
"mediatek,mt7623n-rfb-nand" because mt7623-evb is a kind of debug board
internally in Mediatek which real users can't get. So instead we should
indicate which variants it belongs to with more specific postfix as the
adding here to let people easily know what board they use.

Signed-off-by: John Crispin 
Signed-off-by: Sean Wang 
---
 Documentation/devicetree/bindings/arm/mediatek.txt | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..0924b62 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -1,6 +1,6 @@
 MediaTek mt65xx, mt67xx & mt81xx Platforms Device Tree Bindings
 
-Boards with a MediaTek mt65xx/mt67xx/mt81xx SoC shall have the
+Boards with a MediaTek mt65xx/mt67xx/mt762x/mt81xx SoC shall have the
 following property:
 
 Required root node property:
@@ -12,7 +12,7 @@ compatible: Must contain one of
"mediatek,mt6592"
"mediatek,mt6755"
"mediatek,mt6795"
-   "mediatek,mt7623"
+   "mediatek,mt7623" which is referred to MT7623N SoC
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
@@ -38,9 +38,9 @@ Supported boards:
 - Evaluation board for MT6795(Helio X10):
 Required root node properties:
   - compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
-- Evaluation board for MT7623:
+- Reference  board for MT7623n with NAND:
 Required root node properties:
-  - compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
+  - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
 - MTK mt8127 tablet moose EVB:
 Required root node properties:
   - compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
-- 
2.7.4

[PATCH v4 1/9] dt-bindings: arm: mediatek: update for MT7623n SoC and relevant boards

[sean.wang]

From: Sean Wang 

Because there are two versions of MT7623 SoC that is MT7623a and MT7623n
respectively. So update the part of MT7623n bindings to allow that people
tend to differentiate which MT7623 SoC the boards applies.

And "mediatek,mt7623-evb" can be safely changed to
"mediatek,mt7623n-rfb-nand" because mt7623-evb is a kind of debug board
internally in Mediatek which real users can't get. So instead we should
indicate which variants it belongs to with more specific postfix as the
adding here to let people easily know what board they use.

Signed-off-by: John Crispin 
Signed-off-by: Sean Wang 
---
 Documentation/devicetree/bindings/arm/mediatek.txt | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index c860b24..0924b62 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -1,6 +1,6 @@
 MediaTek mt65xx, mt67xx & mt81xx Platforms Device Tree Bindings
 
-Boards with a MediaTek mt65xx/mt67xx/mt81xx SoC shall have the
+Boards with a MediaTek mt65xx/mt67xx/mt762x/mt81xx SoC shall have the
 following property:
 
 Required root node property:
@@ -12,7 +12,7 @@ compatible: Must contain one of
"mediatek,mt6592"
"mediatek,mt6755"
"mediatek,mt6795"
-   "mediatek,mt7623"
+   "mediatek,mt7623" which is referred to MT7623N SoC
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
@@ -38,9 +38,9 @@ Supported boards:
 - Evaluation board for MT6795(Helio X10):
 Required root node properties:
   - compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
-- Evaluation board for MT7623:
+- Reference  board for MT7623n with NAND:
 Required root node properties:
-  - compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
+  - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
 - MTK mt8127 tablet moose EVB:
 Required root node properties:
   - compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
-- 
2.7.4

[PATCH v4 0/9] arm: dts: extend mt7623 support

[sean.wang]

From: Sean Wang 

Changes since v3:
- explain in the commit message why this binding is changed
- patches for dt-binding is reordered at the beginning of patch list
- be concise wigh using SPDX-License-Identifier in new dts file

Changes since v2:
- exclude those patch are already queued into v4.11-next/dts32
- exclude those patches already sent in separation
- add mt7623a SoC basic support
- update binding SoC for mt7623n and relevant boards

Changes since v1:
Continue the upstream journey based on the previous John Crispin's good work.
- add fixes for the v1 suggestion
- fix typo in the commit log
- add missing pinctrl bindings for mt7623
- reuse pinctrl driver for mt7623
- enhance existing nodes since the way for binding is changed e.g USB
- add more nodes which already gets support from the latest tree e.g MT7530 DSA
- add the dts file for Bananapi R2 (BPI-R2) board

John Crispin (4):
  arm: dts: mt7623: add mt7623-mt6323.dtsi file
  arm: dts: mt7623: cleanup the mt7623n rfb uart nodes
  arm: dts: mt7623: enable the usb device on the mt7623n rfb
  arm: dts: mt7623: enable the nand device on the mt7623n nand rfb

Sean Wang (5):
  dt-bindings: arm: mediatek: update for MT7623n SoC and relevant boards
  dt-bindings: arm: mediatek: add bindings for mediatek MT7623a SoC
Platform
  arm: dts: mt7623: rename mt7623-evb.dts to
arch/arm/boot/dts/mt7623n-rfb.dtsi
  ARM: mediatek: add MT7623a smp bringup code
  arm: dts: mt7623: add dts file for Bananapi R2 (BPI-R2) board

 Documentation/devicetree/bindings/arm/mediatek.txt |  11 +-
 arch/arm/boot/dts/Makefile |   3 +-
 arch/arm/boot/dts/mt7623-evb.dts   |  33 --
 arch/arm/boot/dts/mt7623-mt6323.dtsi   | 269 +
 arch/arm/boot/dts/mt7623.dtsi  |   8 +-
 arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts  | 440 +
 arch/arm/boot/dts/mt7623n-rfb-nand.dts | 109 +
 arch/arm/boot/dts/mt7623n-rfb.dtsi |  61 +++
 arch/arm/mach-mediatek/mediatek.c  |   2 +
 arch/arm/mach-mediatek/platsmp.c   |   1 +
 10 files changed, 895 insertions(+), 42 deletions(-)
 delete mode 100644 arch/arm/boot/dts/mt7623-evb.dts
 create mode 100644 arch/arm/boot/dts/mt7623-mt6323.dtsi
 create mode 100644 arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
 create mode 100644 arch/arm/boot/dts/mt7623n-rfb-nand.dts
 create mode 100644 arch/arm/boot/dts/mt7623n-rfb.dtsi

-- 
2.7.4

[PATCH] spi: st-ssc4: whitespace cleanup

[Chris Packham]

Remove stray single spaces after a leading hard-tab.

Signed-off-by: Chris Packham 
---
 drivers/spi/spi-st-ssc4.c | 38 +++---
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/spi/spi-st-ssc4.c b/drivers/spi/spi-st-ssc4.c
index e54b59638458..a4e43fc19ece 100644
--- a/drivers/spi/spi-st-ssc4.c
+++ b/drivers/spi/spi-st-ssc4.c
@@ -229,42 +229,42 @@ static int spi_st_setup(struct spi_device *spi)
"setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n",
hz, spi_st->baud, sscbrg);
 
-/* Set SSC_CTL and enable SSC */
-var = readl_relaxed(spi_st->base + SSC_CTL);
-var |= SSC_CTL_MS;
+   /* Set SSC_CTL and enable SSC */
+   var = readl_relaxed(spi_st->base + SSC_CTL);
+   var |= SSC_CTL_MS;
 
-if (spi->mode & SPI_CPOL)
+   if (spi->mode & SPI_CPOL)
var |= SSC_CTL_PO;
-else
+   else
var &= ~SSC_CTL_PO;
 
-if (spi->mode & SPI_CPHA)
+   if (spi->mode & SPI_CPHA)
var |= SSC_CTL_PH;
-else
+   else
var &= ~SSC_CTL_PH;
 
-if ((spi->mode & SPI_LSB_FIRST) == 0)
+   if ((spi->mode & SPI_LSB_FIRST) == 0)
var |= SSC_CTL_HB;
-else
+   else
var &= ~SSC_CTL_HB;
 
-if (spi->mode & SPI_LOOP)
+   if (spi->mode & SPI_LOOP)
var |= SSC_CTL_LPB;
-else
+   else
var &= ~SSC_CTL_LPB;
 
-var &= ~SSC_CTL_DATA_WIDTH_MSK;
-var |= (spi->bits_per_word - 1);
+   var &= ~SSC_CTL_DATA_WIDTH_MSK;
+   var |= (spi->bits_per_word - 1);
 
-var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;
-var |= SSC_CTL_EN;
+   var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;
+   var |= SSC_CTL_EN;
 
-writel_relaxed(var, spi_st->base + SSC_CTL);
+   writel_relaxed(var, spi_st->base + SSC_CTL);
 
-/* Clear the status register */
-readl_relaxed(spi_st->base + SSC_RBUF);
+   /* Clear the status register */
+   readl_relaxed(spi_st->base + SSC_RBUF);
 
-return 0;
+   return 0;
 
 out_free_gpio:
gpio_free(cs);
-- 
2.13.0

[PATCH] spi: st-ssc4: whitespace cleanup

[Chris Packham]

Remove stray single spaces after a leading hard-tab.

Signed-off-by: Chris Packham 
---
 drivers/spi/spi-st-ssc4.c | 38 +++---
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/spi/spi-st-ssc4.c b/drivers/spi/spi-st-ssc4.c
index e54b59638458..a4e43fc19ece 100644
--- a/drivers/spi/spi-st-ssc4.c
+++ b/drivers/spi/spi-st-ssc4.c
@@ -229,42 +229,42 @@ static int spi_st_setup(struct spi_device *spi)
"setting baudrate:target= %u hz, actual= %u hz, sscbrg= %u\n",
hz, spi_st->baud, sscbrg);
 
-/* Set SSC_CTL and enable SSC */
-var = readl_relaxed(spi_st->base + SSC_CTL);
-var |= SSC_CTL_MS;
+   /* Set SSC_CTL and enable SSC */
+   var = readl_relaxed(spi_st->base + SSC_CTL);
+   var |= SSC_CTL_MS;
 
-if (spi->mode & SPI_CPOL)
+   if (spi->mode & SPI_CPOL)
var |= SSC_CTL_PO;
-else
+   else
var &= ~SSC_CTL_PO;
 
-if (spi->mode & SPI_CPHA)
+   if (spi->mode & SPI_CPHA)
var |= SSC_CTL_PH;
-else
+   else
var &= ~SSC_CTL_PH;
 
-if ((spi->mode & SPI_LSB_FIRST) == 0)
+   if ((spi->mode & SPI_LSB_FIRST) == 0)
var |= SSC_CTL_HB;
-else
+   else
var &= ~SSC_CTL_HB;
 
-if (spi->mode & SPI_LOOP)
+   if (spi->mode & SPI_LOOP)
var |= SSC_CTL_LPB;
-else
+   else
var &= ~SSC_CTL_LPB;
 
-var &= ~SSC_CTL_DATA_WIDTH_MSK;
-var |= (spi->bits_per_word - 1);
+   var &= ~SSC_CTL_DATA_WIDTH_MSK;
+   var |= (spi->bits_per_word - 1);
 
-var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;
-var |= SSC_CTL_EN;
+   var |= SSC_CTL_EN_TX_FIFO | SSC_CTL_EN_RX_FIFO;
+   var |= SSC_CTL_EN;
 
-writel_relaxed(var, spi_st->base + SSC_CTL);
+   writel_relaxed(var, spi_st->base + SSC_CTL);
 
-/* Clear the status register */
-readl_relaxed(spi_st->base + SSC_RBUF);
+   /* Clear the status register */
+   readl_relaxed(spi_st->base + SSC_RBUF);
 
-return 0;
+   return 0;
 
 out_free_gpio:
gpio_free(cs);
-- 
2.13.0

[PATCH v4 9/9] arm: dts: mt7623: add dts file for Bananapi R2 (BPI-R2) board

[sean.wang]

From: Sean Wang 

Add support for the Bananapi R2 (BPI-R2) development board from
BIPAI KEJI. Detailed hardware information for BPI-R2 which could be
found on http://www.banana-pi.org/r2.html

The patch currently only adds Mediatek GMAC, MT7530 Switch, the crypto
engine, USB, IR, I2S, I2C, UART, SPI, PWM, GPIO keys, GPIO LEDs and
PMIC LEDs. As to the other missing hardware and peripherals, they would
be added and integrated continuously.

Signed-off-by: Sean Wang 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/arm/mediatek.txt |   2 +
 arch/arm/boot/dts/Makefile |   1 +
 arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts  | 440 +
 3 files changed, 443 insertions(+)
 create mode 100644 arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index 412c6bd..7b289bd 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -42,6 +42,8 @@ Supported boards:
 - Reference  board for MT7623n with NAND:
 Required root node properties:
   - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
+- Bananapi BPI-R2 board:
+  - compatible = "bananapi,bpi-r2", "mediatek,mt7623";
 - MTK mt8127 tablet moose EVB:
 Required root node properties:
   - compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 20a7c9d..34eb03f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1035,6 +1035,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt6589-aquaris5.dtb \
mt6592-evb.dtb \
mt7623n-rfb-nand.dtb \
+   mt7623n-bananapi-bpi-r2.dtb \
mt8127-moose.dtb \
mt8135-evbp1.dtb
 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts 
b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
new file mode 100644
index 000..72c7984
--- /dev/null
+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
@@ -0,0 +1,440 @@
+/*
+ * Copyright 2017 Sean Wang 
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+#include 
+#include "mt7623-mt6323.dtsi"
+
+/ {
+   model = "Bananapi BPI-R2";
+   compatible = "bananapi,bpi-r2", "mediatek,mt7623";
+
+   aliases {
+   serial2 = 
+   };
+
+   chosen {
+   stdout-path = "serial2:115200n8";
+   };
+
+   gpio_keys {
+   compatible = "gpio-keys";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+
+   factory {
+   label = "factory";
+   linux,code = ;
+   gpios = < 256 GPIO_ACTIVE_LOW>;
+   };
+
+   wps {
+   label = "wps";
+   linux,code = ;
+   gpios = < 257 GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+
+   red {
+   label = "bpi-r2:pio:red";
+   gpios = < 239 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+
+   green {
+   label = "bpi-r2:pio:green";
+   gpios = < 240 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+
+   blue {
+   label = "bpi-r2:pio:blue";
+   gpios = < 241 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+   };
+
+   memory@8000 {
+   reg = <0 0x8000 0 0x4000>;
+   };
+
+   sound:sound {
+   compatible = "mediatek,mt2701-wm8960-machine";
+   mediatek,platform = <>;
+   audio-routing =
+   "Headphone", "HP_L",
+   "Headphone", "HP_R",
+   "LINPUT1", "AMIC",
+   "RINPUT1", "AMIC";
+   mediatek,audio-codec = <>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   };
+};
+
+ {
+   cir_pins_a:cir@0 {
+   pins_cir {
+   pinmux = ;
+   bias-disable;
+   };
+   };
+
+   i2c0_pins_a: i2c@0 {
+   pins_i2c0 {
+   pinmux = ,
+;
+   bias-disable;
+   };
+   };
+
+   i2c1_pins_a: i2c@1 {
+   pin_i2c1 {
+   pinmux = ,
+;
+   bias-disable;
+   };
+ 

[PATCH v4 7/9] arm: dts: mt7623: enable the usb device on the mt7623n rfb

[sean.wang]

From: John Crispin 

All versions of the mt7623n RFB have an USB port so enable the device.
There is a gpio that gets used to power up the port supply. Add support
for this gpio using the fixed-regulator driver.

Signed-off-by: John Crispin 
Signed-off-by: Sean Wang 
---
 arch/arm/boot/dts/mt7623n-rfb.dtsi | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/mt7623n-rfb.dtsi 
b/arch/arm/boot/dts/mt7623n-rfb.dtsi
index 4963e6a..2964b4c 100644
--- a/arch/arm/boot/dts/mt7623n-rfb.dtsi
+++ b/arch/arm/boot/dts/mt7623n-rfb.dtsi
@@ -28,6 +28,15 @@
serial1 = 
serial2 = 
};
+
+   usb_p1_vbus: regulator@0 {
+   compatible = "regulator-fixed";
+   regulator-name = "usb_vbus";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   gpio = < 135 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
 };
 
  {
@@ -41,3 +50,12 @@
  {
status = "okay";
 };
+
+ {
+   vbus-supply = <_p1_vbus>;
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
-- 
2.7.4

[PATCH v4 9/9] arm: dts: mt7623: add dts file for Bananapi R2 (BPI-R2) board

[sean.wang]

From: Sean Wang 

Add support for the Bananapi R2 (BPI-R2) development board from
BIPAI KEJI. Detailed hardware information for BPI-R2 which could be
found on http://www.banana-pi.org/r2.html

The patch currently only adds Mediatek GMAC, MT7530 Switch, the crypto
engine, USB, IR, I2S, I2C, UART, SPI, PWM, GPIO keys, GPIO LEDs and
PMIC LEDs. As to the other missing hardware and peripherals, they would
be added and integrated continuously.

Signed-off-by: Sean Wang 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/arm/mediatek.txt |   2 +
 arch/arm/boot/dts/Makefile |   1 +
 arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts  | 440 +
 3 files changed, 443 insertions(+)
 create mode 100644 arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts

diff --git a/Documentation/devicetree/bindings/arm/mediatek.txt 
b/Documentation/devicetree/bindings/arm/mediatek.txt
index 412c6bd..7b289bd 100644
--- a/Documentation/devicetree/bindings/arm/mediatek.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek.txt
@@ -42,6 +42,8 @@ Supported boards:
 - Reference  board for MT7623n with NAND:
 Required root node properties:
   - compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
+- Bananapi BPI-R2 board:
+  - compatible = "bananapi,bpi-r2", "mediatek,mt7623";
 - MTK mt8127 tablet moose EVB:
 Required root node properties:
   - compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 20a7c9d..34eb03f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1035,6 +1035,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt6589-aquaris5.dtb \
mt6592-evb.dtb \
mt7623n-rfb-nand.dtb \
+   mt7623n-bananapi-bpi-r2.dtb \
mt8127-moose.dtb \
mt8135-evbp1.dtb
 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts 
b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
new file mode 100644
index 000..72c7984
--- /dev/null
+++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
@@ -0,0 +1,440 @@
+/*
+ * Copyright 2017 Sean Wang 
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+#include 
+#include "mt7623-mt6323.dtsi"
+
+/ {
+   model = "Bananapi BPI-R2";
+   compatible = "bananapi,bpi-r2", "mediatek,mt7623";
+
+   aliases {
+   serial2 = 
+   };
+
+   chosen {
+   stdout-path = "serial2:115200n8";
+   };
+
+   gpio_keys {
+   compatible = "gpio-keys";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+
+   factory {
+   label = "factory";
+   linux,code = ;
+   gpios = < 256 GPIO_ACTIVE_LOW>;
+   };
+
+   wps {
+   label = "wps";
+   linux,code = ;
+   gpios = < 257 GPIO_ACTIVE_HIGH>;
+   };
+   };
+
+   leds {
+   compatible = "gpio-leds";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+
+   red {
+   label = "bpi-r2:pio:red";
+   gpios = < 239 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+
+   green {
+   label = "bpi-r2:pio:green";
+   gpios = < 240 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+
+   blue {
+   label = "bpi-r2:pio:blue";
+   gpios = < 241 GPIO_ACTIVE_HIGH>;
+   default-state = "off";
+   };
+   };
+
+   memory@8000 {
+   reg = <0 0x8000 0 0x4000>;
+   };
+
+   sound:sound {
+   compatible = "mediatek,mt2701-wm8960-machine";
+   mediatek,platform = <>;
+   audio-routing =
+   "Headphone", "HP_L",
+   "Headphone", "HP_R",
+   "LINPUT1", "AMIC",
+   "RINPUT1", "AMIC";
+   mediatek,audio-codec = <>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   };
+};
+
+ {
+   cir_pins_a:cir@0 {
+   pins_cir {
+   pinmux = ;
+   bias-disable;
+   };
+   };
+
+   i2c0_pins_a: i2c@0 {
+   pins_i2c0 {
+   pinmux = ,
+;
+   bias-disable;
+   };
+   };
+
+   i2c1_pins_a: i2c@1 {
+   pin_i2c1 {
+   pinmux = ,
+;
+   bias-disable;
+   };
+   };
+
+   i2s0_pins_a: i2s@0 {
+   pin_i2s0 {
+   

[PATCH v4 7/9] arm: dts: mt7623: enable the usb device on the mt7623n rfb

[sean.wang]

From: John Crispin 

All versions of the mt7623n RFB have an USB port so enable the device.
There is a gpio that gets used to power up the port supply. Add support
for this gpio using the fixed-regulator driver.

Signed-off-by: John Crispin 
Signed-off-by: Sean Wang 
---
 arch/arm/boot/dts/mt7623n-rfb.dtsi | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/mt7623n-rfb.dtsi 
b/arch/arm/boot/dts/mt7623n-rfb.dtsi
index 4963e6a..2964b4c 100644
--- a/arch/arm/boot/dts/mt7623n-rfb.dtsi
+++ b/arch/arm/boot/dts/mt7623n-rfb.dtsi
@@ -28,6 +28,15 @@
serial1 = 
serial2 = 
};
+
+   usb_p1_vbus: regulator@0 {
+   compatible = "regulator-fixed";
+   regulator-name = "usb_vbus";
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   gpio = < 135 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
 };
 
  {
@@ -41,3 +50,12 @@
  {
status = "okay";
 };
+
+ {
+   vbus-supply = <_p1_vbus>;
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
-- 
2.7.4

[PATCH v4 5/9] ARM: mediatek: add MT7623a smp bringup code

[sean.wang]

From: Sean Wang 

Add support for booting secondary CPUs on MT7623a.

Signed-off-by: Sean Wang 
---
 arch/arm/mach-mediatek/mediatek.c | 2 ++
 arch/arm/mach-mediatek/platsmp.c  | 1 +
 2 files changed, 3 insertions(+)

diff --git a/arch/arm/mach-mediatek/mediatek.c 
b/arch/arm/mach-mediatek/mediatek.c
index a6e3c98..1b52011 100644
--- a/arch/arm/mach-mediatek/mediatek.c
+++ b/arch/arm/mach-mediatek/mediatek.c
@@ -30,6 +30,7 @@ static void __init mediatek_timer_init(void)
 
if (of_machine_is_compatible("mediatek,mt6589") ||
of_machine_is_compatible("mediatek,mt7623") ||
+   of_machine_is_compatible("mediatek,mt7623a") ||
of_machine_is_compatible("mediatek,mt8135") ||
of_machine_is_compatible("mediatek,mt8127")) {
/* turn on GPT6 which ungates arch timer clocks */
@@ -49,6 +50,7 @@ static const char * const mediatek_board_dt_compat[] = {
"mediatek,mt6589",
"mediatek,mt6592",
"mediatek,mt7623",
+   "mediatek,mt7623a",
"mediatek,mt8127",
"mediatek,mt8135",
NULL,
diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
index 726eb69..27d78c9 100644
--- a/arch/arm/mach-mediatek/platsmp.c
+++ b/arch/arm/mach-mediatek/platsmp.c
@@ -59,6 +59,7 @@ static const struct of_device_id mtk_tz_smp_boot_infos[] 
__initconst = {
 static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
{ .compatible   = "mediatek,mt6589", .data = _mt6589_boot },
{ .compatible   = "mediatek,mt7623", .data = _mt7623_boot },
+   { .compatible   = "mediatek,mt7623a", .data = _mt7623_boot },
 };
 
 static void __iomem *mtk_smp_base;
-- 
2.7.4

[PATCH v4 8/9] arm: dts: mt7623: enable the nand device on the mt7623n nand rfb

[sean.wang]

From: John Crispin 

Enable the nand device and setup pinmux on the mt7632m rfb with nand
support.

Signed-off-by: John Crispin 
Signed-off-by: Sean Wang 
---
 arch/arm/boot/dts/mt7623n-rfb-nand.dts | 88 ++
 1 file changed, 88 insertions(+)

diff --git a/arch/arm/boot/dts/mt7623n-rfb-nand.dts 
b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
index 436d51c..9356095 100644
--- a/arch/arm/boot/dts/mt7623n-rfb-nand.dts
+++ b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
@@ -19,3 +19,91 @@
model = "MediaTek MT7623N NAND reference board";
compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
 };
+
+ {
+   nand_pins_default: nanddefault {
+   pins_dat {
+   pinmux = ,
+,
+,
+,
+,
+,
+,
+,
+;
+   input-enable;
+   drive-strength = ;
+   bias-pull-up;
+   };
+
+   pins_we {
+   pinmux = ;
+   drive-strength = ;
+   bias-pull-up = ;
+   };
+
+   pins_ale {
+   pinmux = ;
+   drive-strength = ;
+   bias-pull-down = ;
+   };
+   };
+};
+
+ {
+   status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_default>;
+   nand@0 {
+   reg = <0>;
+   spare_per_sector = <64>;
+   nand-ecc-mode = "hw";
+   nand-ecc-strength = <12>;
+   nand-ecc-step-size = <1024>;
+   partitions {
+   compatible = "fixed-partitions";
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   partition@0 {
+   label = "preloader";
+   reg = <0x0 0x4>;
+   };
+
+   partition@4 {
+   label = "uboot";
+   reg = <0x4 0x8>;
+   };
+
+   partition@C {
+   label = "uboot-env";
+   reg = <0xC 0x4>;
+   };
+
+   partition@14 {
+   label = "bootimg";
+   reg = <0x14 0x200>;
+   };
+
+   partition@214 {
+   label = "recovery";
+   reg = <0x214 0x200>;
+   };
+
+   partition@414 {
+   label = "rootfs";
+   reg = <0x414 0x100>;
+   };
+
+   partition@514 {
+   label = "usrdata";
+   reg = <0x514 0x100>;
+   };
+   };
+   };
+};
+
+ {
+   status = "okay";
+};
-- 
2.7.4

[PATCH v4 6/9] arm: dts: mt7623: cleanup the mt7623n rfb uart nodes

[sean.wang]

From: John Crispin 

This patch does a cleanup of the uart nodes in the dts file of the RFB. It
adds aliases, enables 2 more uarts and explicitly sets the uart mode of the
console.

Signed-off-by: John Crispin 
Signed-off-by: Sean Wang 
---
 arch/arm/boot/dts/mt7623n-rfb.dtsi | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/mt7623n-rfb.dtsi 
b/arch/arm/boot/dts/mt7623n-rfb.dtsi
index c526116..4963e6a 100644
--- a/arch/arm/boot/dts/mt7623n-rfb.dtsi
+++ b/arch/arm/boot/dts/mt7623n-rfb.dtsi
@@ -16,12 +16,26 @@
 
 / {
chosen {
-   stdout-path = 
+   stdout-path = "serial2:115200n8";
};
 
memory@8000 {
reg = <0 0x8000 0 0x4000>;
};
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
 };
 
  {
-- 
2.7.4

[PATCH v4 5/9] ARM: mediatek: add MT7623a smp bringup code

[sean.wang]

From: Sean Wang 

Add support for booting secondary CPUs on MT7623a.

Signed-off-by: Sean Wang 
---
 arch/arm/mach-mediatek/mediatek.c | 2 ++
 arch/arm/mach-mediatek/platsmp.c  | 1 +
 2 files changed, 3 insertions(+)

diff --git a/arch/arm/mach-mediatek/mediatek.c 
b/arch/arm/mach-mediatek/mediatek.c
index a6e3c98..1b52011 100644
--- a/arch/arm/mach-mediatek/mediatek.c
+++ b/arch/arm/mach-mediatek/mediatek.c
@@ -30,6 +30,7 @@ static void __init mediatek_timer_init(void)
 
if (of_machine_is_compatible("mediatek,mt6589") ||
of_machine_is_compatible("mediatek,mt7623") ||
+   of_machine_is_compatible("mediatek,mt7623a") ||
of_machine_is_compatible("mediatek,mt8135") ||
of_machine_is_compatible("mediatek,mt8127")) {
/* turn on GPT6 which ungates arch timer clocks */
@@ -49,6 +50,7 @@ static const char * const mediatek_board_dt_compat[] = {
"mediatek,mt6589",
"mediatek,mt6592",
"mediatek,mt7623",
+   "mediatek,mt7623a",
"mediatek,mt8127",
"mediatek,mt8135",
NULL,
diff --git a/arch/arm/mach-mediatek/platsmp.c b/arch/arm/mach-mediatek/platsmp.c
index 726eb69..27d78c9 100644
--- a/arch/arm/mach-mediatek/platsmp.c
+++ b/arch/arm/mach-mediatek/platsmp.c
@@ -59,6 +59,7 @@ static const struct of_device_id mtk_tz_smp_boot_infos[] 
__initconst = {
 static const struct of_device_id mtk_smp_boot_infos[] __initconst = {
{ .compatible   = "mediatek,mt6589", .data = _mt6589_boot },
{ .compatible   = "mediatek,mt7623", .data = _mt7623_boot },
+   { .compatible   = "mediatek,mt7623a", .data = _mt7623_boot },
 };
 
 static void __iomem *mtk_smp_base;
-- 
2.7.4

[PATCH v4 8/9] arm: dts: mt7623: enable the nand device on the mt7623n nand rfb

[sean.wang]

From: John Crispin 

Enable the nand device and setup pinmux on the mt7632m rfb with nand
support.

Signed-off-by: John Crispin 
Signed-off-by: Sean Wang 
---
 arch/arm/boot/dts/mt7623n-rfb-nand.dts | 88 ++
 1 file changed, 88 insertions(+)

diff --git a/arch/arm/boot/dts/mt7623n-rfb-nand.dts 
b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
index 436d51c..9356095 100644
--- a/arch/arm/boot/dts/mt7623n-rfb-nand.dts
+++ b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
@@ -19,3 +19,91 @@
model = "MediaTek MT7623N NAND reference board";
compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
 };
+
+ {
+   nand_pins_default: nanddefault {
+   pins_dat {
+   pinmux = ,
+,
+,
+,
+,
+,
+,
+,
+;
+   input-enable;
+   drive-strength = ;
+   bias-pull-up;
+   };
+
+   pins_we {
+   pinmux = ;
+   drive-strength = ;
+   bias-pull-up = ;
+   };
+
+   pins_ale {
+   pinmux = ;
+   drive-strength = ;
+   bias-pull-down = ;
+   };
+   };
+};
+
+ {
+   status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_default>;
+   nand@0 {
+   reg = <0>;
+   spare_per_sector = <64>;
+   nand-ecc-mode = "hw";
+   nand-ecc-strength = <12>;
+   nand-ecc-step-size = <1024>;
+   partitions {
+   compatible = "fixed-partitions";
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   partition@0 {
+   label = "preloader";
+   reg = <0x0 0x4>;
+   };
+
+   partition@4 {
+   label = "uboot";
+   reg = <0x4 0x8>;
+   };
+
+   partition@C {
+   label = "uboot-env";
+   reg = <0xC 0x4>;
+   };
+
+   partition@14 {
+   label = "bootimg";
+   reg = <0x14 0x200>;
+   };
+
+   partition@214 {
+   label = "recovery";
+   reg = <0x214 0x200>;
+   };
+
+   partition@414 {
+   label = "rootfs";
+   reg = <0x414 0x100>;
+   };
+
+   partition@514 {
+   label = "usrdata";
+   reg = <0x514 0x100>;
+   };
+   };
+   };
+};
+
+ {
+   status = "okay";
+};
-- 
2.7.4

[PATCH v4 6/9] arm: dts: mt7623: cleanup the mt7623n rfb uart nodes

[sean.wang]

From: John Crispin 

This patch does a cleanup of the uart nodes in the dts file of the RFB. It
adds aliases, enables 2 more uarts and explicitly sets the uart mode of the
console.

Signed-off-by: John Crispin 
Signed-off-by: Sean Wang 
---
 arch/arm/boot/dts/mt7623n-rfb.dtsi | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/mt7623n-rfb.dtsi 
b/arch/arm/boot/dts/mt7623n-rfb.dtsi
index c526116..4963e6a 100644
--- a/arch/arm/boot/dts/mt7623n-rfb.dtsi
+++ b/arch/arm/boot/dts/mt7623n-rfb.dtsi
@@ -16,12 +16,26 @@
 
 / {
chosen {
-   stdout-path = 
+   stdout-path = "serial2:115200n8";
};
 
memory@8000 {
reg = <0 0x8000 0 0x4000>;
};
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   };
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
 };
 
  {
-- 
2.7.4

Re: [linux-sunxi] [PATCH v3 3/9] ASoC: sun8i-codec-analog: add support for V3s SoC

[Chen-Yu Tsai]

On Wed, May 24, 2017 at 6:06 PM, Icenowy Zheng  wrote:
> From: Icenowy Zheng 
>
> The V3s SoC features an analog codec with headphone support but without
> mic2 and linein.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng 

Reviewed-by: Chen-Yu Tsai 

Mark, please hold off on applying this patch until the comments from the
previous patch have been addressed. They should be applied in order.

> ---
>  Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt | 1 +
>  sound/soc/sunxi/sun8i-codec-analog.c   | 9 +

Also, is there a preference for splitting out device tree binding
changes from driver changes?

Thanks
ChenYu

[PATCH v4 3/9] arm: dts: mt7623: add mt7623-mt6323.dtsi file

[sean.wang]

From: John Crispin 

MediaTek produces various PMICs. Which one is used depends on the actual
circuit design. Instead of adding the correct PMIC node to every dts file
we instead add a new intermediate dtsi file which adds the PMIC node.
Additionally we also add the phandles for the regulators to various nodes.

Signed-off-by: John Crispin 
Signed-off-by: Sean Wang 
---
 arch/arm/boot/dts/mt7623-evb.dts |   2 +-
 arch/arm/boot/dts/mt7623-mt6323.dtsi | 269 +++
 arch/arm/boot/dts/mt7623.dtsi|   8 +-
 3 files changed, 274 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/boot/dts/mt7623-mt6323.dtsi

diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
index b60b41c..a769149 100644
--- a/arch/arm/boot/dts/mt7623-evb.dts
+++ b/arch/arm/boot/dts/mt7623-evb.dts
@@ -13,7 +13,7 @@
  */
 
 /dts-v1/;
-#include "mt7623.dtsi"
+#include "mt7623-mt6323.dtsi"
 
 / {
model = "MediaTek MT7623 evaluation board";
diff --git a/arch/arm/boot/dts/mt7623-mt6323.dtsi 
b/arch/arm/boot/dts/mt7623-mt6323.dtsi
new file mode 100644
index 000..93d3f71
--- /dev/null
+++ b/arch/arm/boot/dts/mt7623-mt6323.dtsi
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: John Crispin 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "mt7623.dtsi"
+
+ {
+   proc-supply = <_vproc_reg>;
+};
+
+ {
+   proc-supply = <_vproc_reg>;
+};
+
+ {
+   proc-supply = <_vproc_reg>;
+};
+
+ {
+   proc-supply = <_vproc_reg>;
+};
+
+ {
+   pmic: mt6323 {
+   compatible = "mediatek,mt6323";
+   interrupt-parent = <>;
+   interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+
+   mt6323regulator: mt6323regulator{
+   compatible = "mediatek,mt6323-regulator";
+
+   mt6323_vproc_reg: buck_vproc{
+   regulator-name = "vproc";
+   regulator-min-microvolt = < 70>;
+   regulator-max-microvolt = <135>;
+   regulator-ramp-delay = <12500>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   mt6323_vsys_reg: buck_vsys{
+   regulator-name = "vsys";
+   regulator-min-microvolt = <140>;
+   regulator-max-microvolt = <2987500>;
+   regulator-ramp-delay = <25000>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   mt6323_vpa_reg: buck_vpa{
+   regulator-name = "vpa";
+   regulator-min-microvolt = < 50>;
+   regulator-max-microvolt = <365>;
+   };
+
+   mt6323_vtcxo_reg: ldo_vtcxo{
+   regulator-name = "vtcxo";
+   regulator-min-microvolt = <280>;
+   regulator-max-microvolt = <280>;
+   regulator-enable-ramp-delay = <90>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   mt6323_vcn28_reg: ldo_vcn28{
+   regulator-name = "vcn28";
+   regulator-min-microvolt = <280>;
+   regulator-max-microvolt = <280>;
+   regulator-enable-ramp-delay = <185>;
+   };
+
+   mt6323_vcn33_bt_reg: ldo_vcn33_bt{
+   regulator-name = "vcn33_bt";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <360>;
+   regulator-enable-ramp-delay = <185>;
+   };
+
+   mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
+   regulator-name = "vcn33_wifi";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <360>;
+   

[PATCH v4 4/9] arm: dts: mt7623: rename mt7623-evb.dts to arch/arm/boot/dts/mt7623n-rfb.dtsi

[sean.wang]

From: Sean Wang 

There are 2 versions of the MT7623 SoC, the one is MT7623n and the other
is MT7623a.  MT7623n is almost identical to MT7623a but has some
additional multimedia features. The reference boards are available as
NAND or MMC and might have a different ethernet setup. In order to reduce
the duplication of devicetree code we add an intermediate dtsi file for
these reference boards. Additionally Mediatek pointed out, that the EVB
is yet another board and the board in question is infact the RFB. Take
this into account while renaming the files.

Signed-off-by: John Crispin 
Signed-off-by: Sean Wang 
---
 arch/arm/boot/dts/Makefile  |  2 +-
 arch/arm/boot/dts/mt7623n-rfb-nand.dts  | 21 +
 .../boot/dts/{mt7623-evb.dts => mt7623n-rfb.dtsi}   |  8 ++--
 3 files changed, 24 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/boot/dts/mt7623n-rfb-nand.dts
 rename arch/arm/boot/dts/{mt7623-evb.dts => mt7623n-rfb.dtsi} (79%)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9c5e1d9..20a7c9d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1034,7 +1034,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt6580-evbp1.dtb \
mt6589-aquaris5.dtb \
mt6592-evb.dtb \
-   mt7623-evb.dtb \
+   mt7623n-rfb-nand.dtb \
mt8127-moose.dtb \
mt8135-evbp1.dtb
 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
diff --git a/arch/arm/boot/dts/mt7623n-rfb-nand.dts 
b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
new file mode 100644
index 000..436d51c
--- /dev/null
+++ b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: John Crispin 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "mt7623n-rfb.dtsi"
+
+/ {
+   model = "MediaTek MT7623N NAND reference board";
+   compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
+};
diff --git a/arch/arm/boot/dts/mt7623-evb.dts 
b/arch/arm/boot/dts/mt7623n-rfb.dtsi
similarity index 79%
rename from arch/arm/boot/dts/mt7623-evb.dts
rename to arch/arm/boot/dts/mt7623n-rfb.dtsi
index a769149..c526116 100644
--- a/arch/arm/boot/dts/mt7623-evb.dts
+++ b/arch/arm/boot/dts/mt7623n-rfb.dtsi
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016 MediaTek Inc.
- * Author: John Crispin 
+ * Author: John Crispin 
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,18 +12,14 @@
  * GNU General Public License for more details.
  */
 
-/dts-v1/;
 #include "mt7623-mt6323.dtsi"
 
 / {
-   model = "MediaTek MT7623 evaluation board";
-   compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
-
chosen {
stdout-path = 
};
 
-   memory {
+   memory@8000 {
reg = <0 0x8000 0 0x4000>;
};
 };
-- 
2.7.4

Re: [linux-sunxi] [PATCH v3 3/9] ASoC: sun8i-codec-analog: add support for V3s SoC

[Chen-Yu Tsai]

On Wed, May 24, 2017 at 6:06 PM, Icenowy Zheng  wrote:
> From: Icenowy Zheng 
>
> The V3s SoC features an analog codec with headphone support but without
> mic2 and linein.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng 

Reviewed-by: Chen-Yu Tsai 

Mark, please hold off on applying this patch until the comments from the
previous patch have been addressed. They should be applied in order.

> ---
>  Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt | 1 +
>  sound/soc/sunxi/sun8i-codec-analog.c   | 9 +

Also, is there a preference for splitting out device tree binding
changes from driver changes?

Thanks
ChenYu

[PATCH v4 3/9] arm: dts: mt7623: add mt7623-mt6323.dtsi file

[sean.wang]

From: John Crispin 

MediaTek produces various PMICs. Which one is used depends on the actual
circuit design. Instead of adding the correct PMIC node to every dts file
we instead add a new intermediate dtsi file which adds the PMIC node.
Additionally we also add the phandles for the regulators to various nodes.

Signed-off-by: John Crispin 
Signed-off-by: Sean Wang 
---
 arch/arm/boot/dts/mt7623-evb.dts |   2 +-
 arch/arm/boot/dts/mt7623-mt6323.dtsi | 269 +++
 arch/arm/boot/dts/mt7623.dtsi|   8 +-
 3 files changed, 274 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/boot/dts/mt7623-mt6323.dtsi

diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
index b60b41c..a769149 100644
--- a/arch/arm/boot/dts/mt7623-evb.dts
+++ b/arch/arm/boot/dts/mt7623-evb.dts
@@ -13,7 +13,7 @@
  */
 
 /dts-v1/;
-#include "mt7623.dtsi"
+#include "mt7623-mt6323.dtsi"
 
 / {
model = "MediaTek MT7623 evaluation board";
diff --git a/arch/arm/boot/dts/mt7623-mt6323.dtsi 
b/arch/arm/boot/dts/mt7623-mt6323.dtsi
new file mode 100644
index 000..93d3f71
--- /dev/null
+++ b/arch/arm/boot/dts/mt7623-mt6323.dtsi
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: John Crispin 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "mt7623.dtsi"
+
+ {
+   proc-supply = <_vproc_reg>;
+};
+
+ {
+   proc-supply = <_vproc_reg>;
+};
+
+ {
+   proc-supply = <_vproc_reg>;
+};
+
+ {
+   proc-supply = <_vproc_reg>;
+};
+
+ {
+   pmic: mt6323 {
+   compatible = "mediatek,mt6323";
+   interrupt-parent = <>;
+   interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+
+   mt6323regulator: mt6323regulator{
+   compatible = "mediatek,mt6323-regulator";
+
+   mt6323_vproc_reg: buck_vproc{
+   regulator-name = "vproc";
+   regulator-min-microvolt = < 70>;
+   regulator-max-microvolt = <135>;
+   regulator-ramp-delay = <12500>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   mt6323_vsys_reg: buck_vsys{
+   regulator-name = "vsys";
+   regulator-min-microvolt = <140>;
+   regulator-max-microvolt = <2987500>;
+   regulator-ramp-delay = <25000>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   mt6323_vpa_reg: buck_vpa{
+   regulator-name = "vpa";
+   regulator-min-microvolt = < 50>;
+   regulator-max-microvolt = <365>;
+   };
+
+   mt6323_vtcxo_reg: ldo_vtcxo{
+   regulator-name = "vtcxo";
+   regulator-min-microvolt = <280>;
+   regulator-max-microvolt = <280>;
+   regulator-enable-ramp-delay = <90>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   mt6323_vcn28_reg: ldo_vcn28{
+   regulator-name = "vcn28";
+   regulator-min-microvolt = <280>;
+   regulator-max-microvolt = <280>;
+   regulator-enable-ramp-delay = <185>;
+   };
+
+   mt6323_vcn33_bt_reg: ldo_vcn33_bt{
+   regulator-name = "vcn33_bt";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <360>;
+   regulator-enable-ramp-delay = <185>;
+   };
+
+   mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
+   regulator-name = "vcn33_wifi";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <360>;
+   regulator-enable-ramp-delay = <185>;
+   };
+
+  

[PATCH v4 4/9] arm: dts: mt7623: rename mt7623-evb.dts to arch/arm/boot/dts/mt7623n-rfb.dtsi

[sean.wang]

From: Sean Wang 

There are 2 versions of the MT7623 SoC, the one is MT7623n and the other
is MT7623a.  MT7623n is almost identical to MT7623a but has some
additional multimedia features. The reference boards are available as
NAND or MMC and might have a different ethernet setup. In order to reduce
the duplication of devicetree code we add an intermediate dtsi file for
these reference boards. Additionally Mediatek pointed out, that the EVB
is yet another board and the board in question is infact the RFB. Take
this into account while renaming the files.

Signed-off-by: John Crispin 
Signed-off-by: Sean Wang 
---
 arch/arm/boot/dts/Makefile  |  2 +-
 arch/arm/boot/dts/mt7623n-rfb-nand.dts  | 21 +
 .../boot/dts/{mt7623-evb.dts => mt7623n-rfb.dtsi}   |  8 ++--
 3 files changed, 24 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/boot/dts/mt7623n-rfb-nand.dts
 rename arch/arm/boot/dts/{mt7623-evb.dts => mt7623n-rfb.dtsi} (79%)

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9c5e1d9..20a7c9d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1034,7 +1034,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt6580-evbp1.dtb \
mt6589-aquaris5.dtb \
mt6592-evb.dtb \
-   mt7623-evb.dtb \
+   mt7623n-rfb-nand.dtb \
mt8127-moose.dtb \
mt8135-evbp1.dtb
 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
diff --git a/arch/arm/boot/dts/mt7623n-rfb-nand.dts 
b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
new file mode 100644
index 000..436d51c
--- /dev/null
+++ b/arch/arm/boot/dts/mt7623n-rfb-nand.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2016 MediaTek Inc.
+ * Author: John Crispin 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "mt7623n-rfb.dtsi"
+
+/ {
+   model = "MediaTek MT7623N NAND reference board";
+   compatible = "mediatek,mt7623n-rfb-nand", "mediatek,mt7623";
+};
diff --git a/arch/arm/boot/dts/mt7623-evb.dts 
b/arch/arm/boot/dts/mt7623n-rfb.dtsi
similarity index 79%
rename from arch/arm/boot/dts/mt7623-evb.dts
rename to arch/arm/boot/dts/mt7623n-rfb.dtsi
index a769149..c526116 100644
--- a/arch/arm/boot/dts/mt7623-evb.dts
+++ b/arch/arm/boot/dts/mt7623n-rfb.dtsi
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016 MediaTek Inc.
- * Author: John Crispin 
+ * Author: John Crispin 
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -12,18 +12,14 @@
  * GNU General Public License for more details.
  */
 
-/dts-v1/;
 #include "mt7623-mt6323.dtsi"
 
 / {
-   model = "MediaTek MT7623 evaluation board";
-   compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
-
chosen {
stdout-path = 
};
 
-   memory {
+   memory@8000 {
reg = <0 0x8000 0 0x4000>;
};
 };
-- 
2.7.4