Re: [PATCH v5 3/3] gpiolib: Show correct direction from the beginning
Hi,
On Thursday 11 October 2018 07:12 PM, Ricardo Ribalda Delgado wrote:
> Hi Vignesh
>
> Ups, it does not look too good :S . Can you check if this change fixes it:
>
Below diff works for me. I no longer see crash and gpio-hog seems to be
working. Thanks!
Regards
Vignesh
> diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
> index e016b22658ff..bcd0ef49ce97 100644
> --- a/drivers/gpio/gpiolib.c
> +++ b/drivers/gpio/gpiolib.c
> @@ -1349,6 +1349,9 @@ int gpiochip_add_data_with_key(struct gpio_chip
> *chip, void *data,
>
> spin_unlock_irqrestore(_lock, flags);
>
> + for (i = 0; i < chip->ngpio; i++)
> + gdev->descs[i].gdev = gdev;
> +
> #ifdef CONFIG_PINCTRL
> INIT_LIST_HEAD(>pin_ranges);
> #endif
> @@ -1380,8 +1383,6 @@ int gpiochip_add_data_with_key(struct gpio_chip
> *chip, void *data,
> for (i = 0; i < chip->ngpio; i++) {
> struct gpio_desc *desc = >descs[i];
>
> - desc->gdev = gdev;
> -
> if (chip->get_direction && gpiochip_line_is_valid(chip, i))
> desc->flags = !chip->get_direction(chip, i) ?
> (1 << FLAG_IS_OUT) : 0;
>
>
> Thanks!
> On Thu, Oct 11, 2018 at 2:18 PM Vignesh R wrote:
>>
>> Hi,
>>
>> On Friday 05 October 2018 12:23 PM, Ricardo Ribalda Delgado wrote:
>>> Current code assumes that the direction is input if direction_input
>>> function is set.
>>> This might not be the case on GPIOs with programmable direction.
>>>
>>> Signed-off-by: Ricardo Ribalda Delgado
>>> Tested-by: Jeffrey Hugo
>>
>> This patch causes oops on TI's AM335x-ICEv2 board on next-20181011:
>>
>> [0.563797] OMAP GPIO hardware version 0.1
>> [0.577589] Unable to handle kernel NULL pointer dereference at virtual
>> address 02b8
>> [0.586127] pgd = (ptrval)
>> [0.588934] [02b8] *pgd=
>> [0.592732] Internal error: Oops: 5 [#1] SMP ARM
>> [0.597499] Modules linked in:
>> [0.600668] CPU: 0 PID: 1 Comm: swapper/0 Not tainted
>> 4.19.0-rc7-next-20181011 #70
>> [0.608466] Hardware name: Generic AM33XX (Flattened Device Tree)
>> [0.614770] PC is at gpiod_hog+0x30/0x154
>> [0.618913] LR is at of_gpiochip_add+0x2fc/0x4e4
>> [0.623671] pc : []lr : []psr: 6013
>> [0.630130] sp : ce09bba0 ip : cdf08095 fp :
>> [0.635516] r10: c0bfcf24 r9 : r8 : 0007
>> [0.640902] r7 : cdf08088 r6 : r5 : r4 : ce191e40
>> [0.647630] r3 : r2 : r1 : cdf08088 r0 : ce191e40
>> [0.654361] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment
>> none
>> [0.661718] Control: 10c5387d Table: 80004019 DAC: 0051
>> [0.667642] Process swapper/0 (pid: 1, stack limit = 0x(ptrval))
>> [...]
>> [0.973593] [] (gpiod_hog) from []
>> (of_gpiochip_add+0x2fc/0x4e4)
>> [0.981588] [] (of_gpiochip_add) from []
>> (gpiochip_add_data_with_key+
>> 0x5a0/0x990)
>> [0.991102] [] (gpiochip_add_data_with_key) from []
>> (omap_gpio_probe+
>> 0x37c/0x75c)
>> [1.000613] [] (omap_gpio_probe) from []
>> (platform_drv_probe+0x48/0x9
>> 8)
>> [1.009237] [] (platform_drv_probe) from []
>> (really_probe+0x220/0x2d4
>> )
>> [1.017764] [] (really_probe) from []
>> (driver_probe_device+0x5c/0x164
>> )
>> [1.026293] [] (driver_probe_device) from []
>> (bus_for_each_drv+0x54/0
>> xb8)
>> [1.035090] [] (bus_for_each_drv) from []
>> (__device_attach+0xcc/0x13c
>> )
>> [1.043615] [] (__device_attach) from []
>> (bus_probe_device+0x88/0x90)
>> [1.052051] [] (bus_probe_device) from []
>> (device_add+0x3d8/0x608)
>> [1.060223] [] (device_add) from []
>> (of_platform_device_create_pdata+
>> 0x8c/0xc0)
>> [1.069552] [] (of_platform_device_create_pdata) from
>> [] (of_platform
>> _bus_create+0x190/0x228)
>> [1.080134] [] (of_platform_bus_create) from []
>> (of_platform_bus_crea
>> te+0x1dc/0x228)
>> [1.089909] [] (of_platform_bus_create) from []
>> (of_platform_populate
>> +0x5c/0xac)
>> [1.099333] [] (of_platform_populate) from []
>> (pdata_quirks_init+0x6c
>> /0x90)
>> [1.108306] [] (pdata_quirks_init) from []
>> (omap_generic_init+0xc/0x1
>> 8)
>> [1.116933] [] (omap_generic_init) from []
>> (customize_machine+0x1c/0x
Re: [PATCH v5 3/3] gpiolib: Show correct direction from the beginning
Hi,
On Thursday 11 October 2018 07:12 PM, Ricardo Ribalda Delgado wrote:
> Hi Vignesh
>
> Ups, it does not look too good :S . Can you check if this change fixes it:
>
Below diff works for me. I no longer see crash and gpio-hog seems to be
working. Thanks!
Regards
Vignesh
> diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
> index e016b22658ff..bcd0ef49ce97 100644
> --- a/drivers/gpio/gpiolib.c
> +++ b/drivers/gpio/gpiolib.c
> @@ -1349,6 +1349,9 @@ int gpiochip_add_data_with_key(struct gpio_chip
> *chip, void *data,
>
> spin_unlock_irqrestore(_lock, flags);
>
> + for (i = 0; i < chip->ngpio; i++)
> + gdev->descs[i].gdev = gdev;
> +
> #ifdef CONFIG_PINCTRL
> INIT_LIST_HEAD(>pin_ranges);
> #endif
> @@ -1380,8 +1383,6 @@ int gpiochip_add_data_with_key(struct gpio_chip
> *chip, void *data,
> for (i = 0; i < chip->ngpio; i++) {
> struct gpio_desc *desc = >descs[i];
>
> - desc->gdev = gdev;
> -
> if (chip->get_direction && gpiochip_line_is_valid(chip, i))
> desc->flags = !chip->get_direction(chip, i) ?
> (1 << FLAG_IS_OUT) : 0;
>
>
> Thanks!
> On Thu, Oct 11, 2018 at 2:18 PM Vignesh R wrote:
>>
>> Hi,
>>
>> On Friday 05 October 2018 12:23 PM, Ricardo Ribalda Delgado wrote:
>>> Current code assumes that the direction is input if direction_input
>>> function is set.
>>> This might not be the case on GPIOs with programmable direction.
>>>
>>> Signed-off-by: Ricardo Ribalda Delgado
>>> Tested-by: Jeffrey Hugo
>>
>> This patch causes oops on TI's AM335x-ICEv2 board on next-20181011:
>>
>> [0.563797] OMAP GPIO hardware version 0.1
>> [0.577589] Unable to handle kernel NULL pointer dereference at virtual
>> address 02b8
>> [0.586127] pgd = (ptrval)
>> [0.588934] [02b8] *pgd=
>> [0.592732] Internal error: Oops: 5 [#1] SMP ARM
>> [0.597499] Modules linked in:
>> [0.600668] CPU: 0 PID: 1 Comm: swapper/0 Not tainted
>> 4.19.0-rc7-next-20181011 #70
>> [0.608466] Hardware name: Generic AM33XX (Flattened Device Tree)
>> [0.614770] PC is at gpiod_hog+0x30/0x154
>> [0.618913] LR is at of_gpiochip_add+0x2fc/0x4e4
>> [0.623671] pc : []lr : []psr: 6013
>> [0.630130] sp : ce09bba0 ip : cdf08095 fp :
>> [0.635516] r10: c0bfcf24 r9 : r8 : 0007
>> [0.640902] r7 : cdf08088 r6 : r5 : r4 : ce191e40
>> [0.647630] r3 : r2 : r1 : cdf08088 r0 : ce191e40
>> [0.654361] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment
>> none
>> [0.661718] Control: 10c5387d Table: 80004019 DAC: 0051
>> [0.667642] Process swapper/0 (pid: 1, stack limit = 0x(ptrval))
>> [...]
>> [0.973593] [] (gpiod_hog) from []
>> (of_gpiochip_add+0x2fc/0x4e4)
>> [0.981588] [] (of_gpiochip_add) from []
>> (gpiochip_add_data_with_key+
>> 0x5a0/0x990)
>> [0.991102] [] (gpiochip_add_data_with_key) from []
>> (omap_gpio_probe+
>> 0x37c/0x75c)
>> [1.000613] [] (omap_gpio_probe) from []
>> (platform_drv_probe+0x48/0x9
>> 8)
>> [1.009237] [] (platform_drv_probe) from []
>> (really_probe+0x220/0x2d4
>> )
>> [1.017764] [] (really_probe) from []
>> (driver_probe_device+0x5c/0x164
>> )
>> [1.026293] [] (driver_probe_device) from []
>> (bus_for_each_drv+0x54/0
>> xb8)
>> [1.035090] [] (bus_for_each_drv) from []
>> (__device_attach+0xcc/0x13c
>> )
>> [1.043615] [] (__device_attach) from []
>> (bus_probe_device+0x88/0x90)
>> [1.052051] [] (bus_probe_device) from []
>> (device_add+0x3d8/0x608)
>> [1.060223] [] (device_add) from []
>> (of_platform_device_create_pdata+
>> 0x8c/0xc0)
>> [1.069552] [] (of_platform_device_create_pdata) from
>> [] (of_platform
>> _bus_create+0x190/0x228)
>> [1.080134] [] (of_platform_bus_create) from []
>> (of_platform_bus_crea
>> te+0x1dc/0x228)
>> [1.089909] [] (of_platform_bus_create) from []
>> (of_platform_populate
>> +0x5c/0xac)
>> [1.099333] [] (of_platform_populate) from []
>> (pdata_quirks_init+0x6c
>> /0x90)
>> [1.108306] [] (pdata_quirks_init) from []
>> (omap_generic_init+0xc/0x1
>> 8)
>> [1.116933] [] (omap_generic_init) from []
>> (customize_machine+0x1c/0x
Re: [PATCH v1] phy: qcom-qusb2: Fix HSTX_TRIM tuning with fused value for SDM845
Hi,
On 2018-10-11 04:06, Doug Anderson wrote:
Hi,
On Fri, Oct 5, 2018 at 2:09 AM Manu Gautam
wrote:
Tune1 register on sdm845 is used to update HSTX_TRIM with fused
setting. Enable same by specifying update_tune1_with_efuse flag
for sdm845, otherwise driver ends up programming tune2 register.
While at it, also fix HSTX_TRIM tuning logic which instead of
using fused value as HSTX_TRIM, incorrectly performs bitwise OR
operation with existing default value.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
It's a little weird that the old code wasn't causing more problems.
Any idea why? On SDM845 it looks like the old code was clobbering the
"fstx slew rate control" bits.
Thanks for reviewing it.
I am assuming changing 'fstx slew rc' didn't have major impact other
than
some interoperability or electrical compliance issues.
In any case, this looks like it fixes several commits:
1. The bitwise OR vs. setting the bits w/ mask fixes the original
driver at commit ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2
PHY on Qcom chips"). It'll be slightly annoying to backport past
commit c71dabf27c3a ("phy: qcom-qusb2: Add support for different
register layouts") but you should still tag "Fixes" with the original
commit in case anyone wants to do it.
2. On sdm845 it was updating the wrong register (tune2 instead of
tune1). This fixes commit ef17f6e212ca ("phy: qcom-qusb2: Add QUSB2
PHYs support for sdm845").
...because of the above I'd suggest splitting this into two commits:
one that fixes the qusb2_write_mask() and one that fixes sdm845. Then
add the "Fixes:" tag. This will really help in the backports to
linux-stable.
Sure, will split in two.
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index e70e425f26f5..defeb0b7cfa0 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -231,6 +231,7 @@ static const struct qusb2_phy_cfg sdm845_phy_cfg =
{
.mask_core_ready = CORE_READY_STATUS,
.has_pll_override = true,
.autoresume_en= BIT(0),
+ .update_tune1_with_efuse = true,
};
static const char * const qusb2_phy_vreg_names[] = {
@@ -415,12 +416,13 @@ static void qusb2_phy_set_tune2_param(struct
qusb2_phy *qphy)
/* Fused TUNE1/2 value is the higher nibble only */
if (cfg->update_tune1_with_efuse)
- qusb2_setbits(qphy->base,
cfg->regs[QUSB2PHY_PORT_TUNE1],
- val[0] << 0x4);
+ qusb2_write_mask(qphy->base,
cfg->regs[QUSB2PHY_PORT_TUNE1],
+val[0] << HSTX_TRIM_SHIFT,
+HSTX_TRIM_MASK);
else
- qusb2_setbits(qphy->base,
cfg->regs[QUSB2PHY_PORT_TUNE2],
- val[0] << 0x4);
-
+ qusb2_write_mask(qphy->base,
cfg->regs[QUSB2PHY_PORT_TUNE2],
+val[0] << HSTX_TRIM_SHIFT,
+HSTX_TRIM_MASK);
In general your patch seems like something we should take. ...but it
made me look a bit more at the code and I think your patch will tickle
another bug that we probably need to fix first.
Specifically there are two ways to set HSTX_TRIM. One is in
qusb2_phy_set_tune2_param() and the other is in
qusb2_phy_override_phy_params(). At the moment we first call
qusb2_phy_override_phy_params() and then we call
qusb2_phy_set_tune2_param(). That means that (now that we've fixed
qusb2_phy_set_tune2_param()) we'll _always_ set the tuning based on
qusb2_phy_set_tune2_param() assuming that the nvmem is specified (and
non-zero). ...and it's specified in sdm845.dtsi so that means that on
SDM845 it's _always_ specified.
Said another way: the 'qcom,hstx-trim-value' in sdm845-mtp.dts is
totally useless because it will always be overridden by the fuse which
is specified in sdm845.dtsi.
I have no idea how the fused value vs. the device tree value are
supposed to interact, but that doesn't seem right. ...or is the fused
value really supposed to override and it'll be 0 if it's not supposed
to?
Fused value is supposed to always override. If value is not fused for
some
parts (which I believe is case with some early samples), then driver
will
read it is '0' from nvmem and should use hstx-trim value passed from DT.
-Manu
Re: [PATCH v1] phy: qcom-qusb2: Fix HSTX_TRIM tuning with fused value for SDM845
Hi,
On 2018-10-11 04:06, Doug Anderson wrote:
Hi,
On Fri, Oct 5, 2018 at 2:09 AM Manu Gautam
wrote:
Tune1 register on sdm845 is used to update HSTX_TRIM with fused
setting. Enable same by specifying update_tune1_with_efuse flag
for sdm845, otherwise driver ends up programming tune2 register.
While at it, also fix HSTX_TRIM tuning logic which instead of
using fused value as HSTX_TRIM, incorrectly performs bitwise OR
operation with existing default value.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
It's a little weird that the old code wasn't causing more problems.
Any idea why? On SDM845 it looks like the old code was clobbering the
"fstx slew rate control" bits.
Thanks for reviewing it.
I am assuming changing 'fstx slew rc' didn't have major impact other
than
some interoperability or electrical compliance issues.
In any case, this looks like it fixes several commits:
1. The bitwise OR vs. setting the bits w/ mask fixes the original
driver at commit ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2
PHY on Qcom chips"). It'll be slightly annoying to backport past
commit c71dabf27c3a ("phy: qcom-qusb2: Add support for different
register layouts") but you should still tag "Fixes" with the original
commit in case anyone wants to do it.
2. On sdm845 it was updating the wrong register (tune2 instead of
tune1). This fixes commit ef17f6e212ca ("phy: qcom-qusb2: Add QUSB2
PHYs support for sdm845").
...because of the above I'd suggest splitting this into two commits:
one that fixes the qusb2_write_mask() and one that fixes sdm845. Then
add the "Fixes:" tag. This will really help in the backports to
linux-stable.
Sure, will split in two.
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index e70e425f26f5..defeb0b7cfa0 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -231,6 +231,7 @@ static const struct qusb2_phy_cfg sdm845_phy_cfg =
{
.mask_core_ready = CORE_READY_STATUS,
.has_pll_override = true,
.autoresume_en= BIT(0),
+ .update_tune1_with_efuse = true,
};
static const char * const qusb2_phy_vreg_names[] = {
@@ -415,12 +416,13 @@ static void qusb2_phy_set_tune2_param(struct
qusb2_phy *qphy)
/* Fused TUNE1/2 value is the higher nibble only */
if (cfg->update_tune1_with_efuse)
- qusb2_setbits(qphy->base,
cfg->regs[QUSB2PHY_PORT_TUNE1],
- val[0] << 0x4);
+ qusb2_write_mask(qphy->base,
cfg->regs[QUSB2PHY_PORT_TUNE1],
+val[0] << HSTX_TRIM_SHIFT,
+HSTX_TRIM_MASK);
else
- qusb2_setbits(qphy->base,
cfg->regs[QUSB2PHY_PORT_TUNE2],
- val[0] << 0x4);
-
+ qusb2_write_mask(qphy->base,
cfg->regs[QUSB2PHY_PORT_TUNE2],
+val[0] << HSTX_TRIM_SHIFT,
+HSTX_TRIM_MASK);
In general your patch seems like something we should take. ...but it
made me look a bit more at the code and I think your patch will tickle
another bug that we probably need to fix first.
Specifically there are two ways to set HSTX_TRIM. One is in
qusb2_phy_set_tune2_param() and the other is in
qusb2_phy_override_phy_params(). At the moment we first call
qusb2_phy_override_phy_params() and then we call
qusb2_phy_set_tune2_param(). That means that (now that we've fixed
qusb2_phy_set_tune2_param()) we'll _always_ set the tuning based on
qusb2_phy_set_tune2_param() assuming that the nvmem is specified (and
non-zero). ...and it's specified in sdm845.dtsi so that means that on
SDM845 it's _always_ specified.
Said another way: the 'qcom,hstx-trim-value' in sdm845-mtp.dts is
totally useless because it will always be overridden by the fuse which
is specified in sdm845.dtsi.
I have no idea how the fused value vs. the device tree value are
supposed to interact, but that doesn't seem right. ...or is the fused
value really supposed to override and it'll be 0 if it's not supposed
to?
Fused value is supposed to always override. If value is not fused for
some
parts (which I believe is case with some early samples), then driver
will
read it is '0' from nvmem and should use hstx-trim value passed from DT.
-Manu
linux-next: manual merge of the xarray tree with the nnvdimm-fixes tree
Hi all,
Today's linux-next merge of the xarray tree got a conflict in:
fs/dax.c
between commit:
d7782145e1ad ("filesystem-dax: Fix dax_layout_busy_page() livelock")
from the nvdimm-fixes tree and commit:
0995344c1493 ("dax: Convert dax_layout_busy_page to XArray")
from the xarray tree.
I fixed it up (I just used the latter - please let me know if more id
needed) and can carry the fix as necessary. This is now fixed as far as
linux-next is concerned, but any non trivial conflicts should be mentioned
to your upstream maintainer when your tree is submitted for merging.
You may also want to consider cooperating with the maintainer of the
conflicting tree to minimise any particularly complex conflicts.
--
Cheers,
Stephen Rothwell
pgp9T82pJJ1kz.pgp
Description: OpenPGP digital signature
linux-next: manual merge of the xarray tree with the nnvdimm-fixes tree
Hi all,
Today's linux-next merge of the xarray tree got a conflict in:
fs/dax.c
between commit:
d7782145e1ad ("filesystem-dax: Fix dax_layout_busy_page() livelock")
from the nvdimm-fixes tree and commit:
0995344c1493 ("dax: Convert dax_layout_busy_page to XArray")
from the xarray tree.
I fixed it up (I just used the latter - please let me know if more id
needed) and can carry the fix as necessary. This is now fixed as far as
linux-next is concerned, but any non trivial conflicts should be mentioned
to your upstream maintainer when your tree is submitted for merging.
You may also want to consider cooperating with the maintainer of the
conflicting tree to minimise any particularly complex conflicts.
--
Cheers,
Stephen Rothwell
pgp9T82pJJ1kz.pgp
Description: OpenPGP digital signature
Re: Insanely high baud rates
On 10/11/18 2:40 PM, Theodore Y. Ts'o wrote: > On Thu, Oct 11, 2018 at 07:14:30AM -0700, h...@zytor.com wrote: >>> >>> I mean - what is the baud rate of a pty ? >> >> Whatever the master wants it to be... > > I think Alan's point is that it is highly unlikely you would be able > to push the equivalent of 4 gbps through a PTY layer. The TTY later > was never engineered for those speeds, and the real question is --- > what's the point? That's what Ethernet is for. > I like to consider the far future; I think things like the Y2038 problem is a good example. Or, as I like to put it, "numbers are cheap, running out of numbers is expensive." Sounds like we have enough of a plan that we aren't completely stuck should it ever become an issue. It might never, of course. -hpa
Re: Insanely high baud rates
On 10/11/18 2:40 PM, Theodore Y. Ts'o wrote: > On Thu, Oct 11, 2018 at 07:14:30AM -0700, h...@zytor.com wrote: >>> >>> I mean - what is the baud rate of a pty ? >> >> Whatever the master wants it to be... > > I think Alan's point is that it is highly unlikely you would be able > to push the equivalent of 4 gbps through a PTY layer. The TTY later > was never engineered for those speeds, and the real question is --- > what's the point? That's what Ethernet is for. > I like to consider the far future; I think things like the Y2038 problem is a good example. Or, as I like to put it, "numbers are cheap, running out of numbers is expensive." Sounds like we have enough of a plan that we aren't completely stuck should it ever become an issue. It might never, of course. -hpa
[PATCH] perf: Align cpu map events properly.
The size of the resulting cpu map can be smaller than a multiple
of sizeof(u64), resulting in SIGBUS on cpus like Sparc as the
next event will not be aligned properly.
Fixes: 6c872901af07 ("perf cpu_map: Add cpu_map event synthesize function")
Signed-off-by: David S. Miller
diff --git a/tools/perf/util/event.c b/tools/perf/util/event.c
index 0cd42150f712..0988eb3b844b 100644
--- a/tools/perf/util/event.c
+++ b/tools/perf/util/event.c
@@ -1081,6 +1081,7 @@ void *cpu_map_data__alloc(struct cpu_map *map, size_t
*size, u16 *type, int *max
}
*size += sizeof(struct cpu_map_data);
+ *size = PERF_ALIGN(*size, sizeof(u64));
return zalloc(*size);
}
[PATCH] perf: Align cpu map events properly.
The size of the resulting cpu map can be smaller than a multiple
of sizeof(u64), resulting in SIGBUS on cpus like Sparc as the
next event will not be aligned properly.
Fixes: 6c872901af07 ("perf cpu_map: Add cpu_map event synthesize function")
Signed-off-by: David S. Miller
diff --git a/tools/perf/util/event.c b/tools/perf/util/event.c
index 0cd42150f712..0988eb3b844b 100644
--- a/tools/perf/util/event.c
+++ b/tools/perf/util/event.c
@@ -1081,6 +1081,7 @@ void *cpu_map_data__alloc(struct cpu_map *map, size_t
*size, u16 *type, int *max
}
*size += sizeof(struct cpu_map_data);
+ *size = PERF_ALIGN(*size, sizeof(u64));
return zalloc(*size);
}
[PATCH v2] of: base: Change logic in of_alias_get_alias_list()
Check compatible string first before setting up bit in bitmap to also
cover cases that allocated bitfield is not big enough.
Show warning about it but let driver to continue to work with allocated
bitfield to keep at least some devices (included console which
is commonly close to serial0) to work.
Fixes: b1078c355d76 ("of: base: Introduce of_alias_get_alias_list() to check
alias IDs")
Fixes: ae1cca3fa347 ("serial: uartps: Change uart ID port allocation")
Signed-off-by: Michal Simek
---
Changes in v2:
- Use EOVERFLOW instead of EINVAL - Rob
I have looked at it and I don't think there should be necessary to
report error immediately back with partially initialized bitfield.
The reason is that still there could be a console device which is most
likely below that max limit and it is worth to return at least that nbits
properly filled.
It will also enable cases that you can still continue to use aliases
higher then fields prepared for devices without alias.
To be fixed patches are present in tty-next branch.
And this patch depends on
"of: base: Fix english spelling in of_alias_get_alias_list()"
---
drivers/of/base.c | 22 --
drivers/tty/serial/xilinx_uartps.c | 2 +-
2 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 908de45f966b..6418205a05f5 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -1953,13 +1953,15 @@ int of_alias_get_id(struct device_node *np, const char
*stem)
* The function travels the lookup table to record alias ids for the given
* device match structures and alias stem.
*
- * Return: 0 or -ENOSYS when !CONFIG_OF
+ * Return: 0 or -ENOSYS when !CONFIG_OF or
+ * -EOVERFLOW if alias ID is greater then allocated nbits
*/
int of_alias_get_alias_list(const struct of_device_id *matches,
const char *stem, unsigned long *bitmap,
unsigned int nbits)
{
struct alias_prop *app;
+ int ret = 0;
/* Zero bitmap field to make sure that all the time it is clean */
bitmap_zero(bitmap, nbits);
@@ -1976,21 +1978,21 @@ int of_alias_get_alias_list(const struct of_device_id
*matches,
continue;
}
- if (app->id >= nbits) {
- pr_debug("%s: ID %d greater then bitmap field %d\n",
- __func__, app->id, nbits);
- continue;
- }
-
if (of_match_node(matches, app->np)) {
pr_debug("%s: Allocated ID %d\n", __func__, app->id);
- set_bit(app->id, bitmap);
+
+ if (app->id >= nbits) {
+ pr_warn("%s: ID %d >= than bitmap field %d\n",
+ __func__, app->id, nbits);
+ ret = -EOVERFLOW;
+ } else {
+ set_bit(app->id, bitmap);
+ }
}
- /* Alias exists but is not compatible with matches */
}
mutex_unlock(_mutex);
- return 0;
+ return ret;
}
EXPORT_SYMBOL_GPL(of_alias_get_alias_list);
diff --git a/drivers/tty/serial/xilinx_uartps.c
b/drivers/tty/serial/xilinx_uartps.c
index d452dceb0cb3..b8f8abc96631 100644
--- a/drivers/tty/serial/xilinx_uartps.c
+++ b/drivers/tty/serial/xilinx_uartps.c
@@ -1393,7 +1393,7 @@ static int cdns_get_id(struct platform_device *pdev)
if (!alias_bitmap_initialized) {
ret = of_alias_get_alias_list(cdns_uart_of_match, "serial",
alias_bitmap, MAX_UART_INSTANCES);
- if (ret) {
+ if (ret && ret != -EOVERFLOW) {
mutex_unlock(_lock);
return ret;
}
--
1.9.1
[PATCH v2] of: base: Change logic in of_alias_get_alias_list()
Check compatible string first before setting up bit in bitmap to also
cover cases that allocated bitfield is not big enough.
Show warning about it but let driver to continue to work with allocated
bitfield to keep at least some devices (included console which
is commonly close to serial0) to work.
Fixes: b1078c355d76 ("of: base: Introduce of_alias_get_alias_list() to check
alias IDs")
Fixes: ae1cca3fa347 ("serial: uartps: Change uart ID port allocation")
Signed-off-by: Michal Simek
---
Changes in v2:
- Use EOVERFLOW instead of EINVAL - Rob
I have looked at it and I don't think there should be necessary to
report error immediately back with partially initialized bitfield.
The reason is that still there could be a console device which is most
likely below that max limit and it is worth to return at least that nbits
properly filled.
It will also enable cases that you can still continue to use aliases
higher then fields prepared for devices without alias.
To be fixed patches are present in tty-next branch.
And this patch depends on
"of: base: Fix english spelling in of_alias_get_alias_list()"
---
drivers/of/base.c | 22 --
drivers/tty/serial/xilinx_uartps.c | 2 +-
2 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 908de45f966b..6418205a05f5 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -1953,13 +1953,15 @@ int of_alias_get_id(struct device_node *np, const char
*stem)
* The function travels the lookup table to record alias ids for the given
* device match structures and alias stem.
*
- * Return: 0 or -ENOSYS when !CONFIG_OF
+ * Return: 0 or -ENOSYS when !CONFIG_OF or
+ * -EOVERFLOW if alias ID is greater then allocated nbits
*/
int of_alias_get_alias_list(const struct of_device_id *matches,
const char *stem, unsigned long *bitmap,
unsigned int nbits)
{
struct alias_prop *app;
+ int ret = 0;
/* Zero bitmap field to make sure that all the time it is clean */
bitmap_zero(bitmap, nbits);
@@ -1976,21 +1978,21 @@ int of_alias_get_alias_list(const struct of_device_id
*matches,
continue;
}
- if (app->id >= nbits) {
- pr_debug("%s: ID %d greater then bitmap field %d\n",
- __func__, app->id, nbits);
- continue;
- }
-
if (of_match_node(matches, app->np)) {
pr_debug("%s: Allocated ID %d\n", __func__, app->id);
- set_bit(app->id, bitmap);
+
+ if (app->id >= nbits) {
+ pr_warn("%s: ID %d >= than bitmap field %d\n",
+ __func__, app->id, nbits);
+ ret = -EOVERFLOW;
+ } else {
+ set_bit(app->id, bitmap);
+ }
}
- /* Alias exists but is not compatible with matches */
}
mutex_unlock(_mutex);
- return 0;
+ return ret;
}
EXPORT_SYMBOL_GPL(of_alias_get_alias_list);
diff --git a/drivers/tty/serial/xilinx_uartps.c
b/drivers/tty/serial/xilinx_uartps.c
index d452dceb0cb3..b8f8abc96631 100644
--- a/drivers/tty/serial/xilinx_uartps.c
+++ b/drivers/tty/serial/xilinx_uartps.c
@@ -1393,7 +1393,7 @@ static int cdns_get_id(struct platform_device *pdev)
if (!alias_bitmap_initialized) {
ret = of_alias_get_alias_list(cdns_uart_of_match, "serial",
alias_bitmap, MAX_UART_INSTANCES);
- if (ret) {
+ if (ret && ret != -EOVERFLOW) {
mutex_unlock(_lock);
return ret;
}
--
1.9.1
RE: [PATCH] stm class: increase pos if no free channels found
Hi Alexander,
Any comments about this patch?
BRs
Zhi Jin
> -Original Message-
> From: Jin, Zhi
> Sent: Thursday, September 06, 2018 3:22 PM
> To: alexander.shish...@linux.intel.com
> Cc: linux-kernel@vger.kernel.org; Jin, Zhi
> Subject: [PATCH] stm class: increase pos if no free channels found
>
> Considering this case in find_free_channels():
>
> bitmap:
>+--+-+-+-+-+-+-+-+-+-+-+
>| .. |0|0|0|0|0|0|0|1|0|0|
>+--+-+-+-+-+-+-+-+-+-+-+
>
> 1. Channel #2 has been occupied, so bit #2 is 1, and the others
>are all 0.
> 2. Another thread tries to find 4 free channels from #0.
> 3. In the 1st loop, pos starts from 0, and then it checks if the
>following 4 bits are all 0, but fails, as bit#2 is 1.
> 4. In the 2st loop, pos is not updated, and still starts from 0,
>so nothing changes against loop #1.
> 5. Dead loop ...
>
> This patch is to update the pos in step #3 to avoid the issue.
>
> Fixes: 7bd1d4093c2f ("stm class: Introduce an abstraction for System
> Trace Module devices")
> Signed-off-by: Zhi Jin
> ---
> drivers/hwtracing/stm/core.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/hwtracing/stm/core.c b/drivers/hwtracing/stm/core.c
> index 10bcb5d73f90..c86a979b9bd7 100644
> --- a/drivers/hwtracing/stm/core.c
> +++ b/drivers/hwtracing/stm/core.c
> @@ -244,6 +244,8 @@ static int find_free_channels(unsigned long *bitmap,
> unsigned int start,
> ;
> if (i == width)
> return pos;
> +
> + pos += i;
> }
>
> return -1;
> --
> 2.7.4
RE: [PATCH] stm class: increase pos if no free channels found
Hi Alexander,
Any comments about this patch?
BRs
Zhi Jin
> -Original Message-
> From: Jin, Zhi
> Sent: Thursday, September 06, 2018 3:22 PM
> To: alexander.shish...@linux.intel.com
> Cc: linux-kernel@vger.kernel.org; Jin, Zhi
> Subject: [PATCH] stm class: increase pos if no free channels found
>
> Considering this case in find_free_channels():
>
> bitmap:
>+--+-+-+-+-+-+-+-+-+-+-+
>| .. |0|0|0|0|0|0|0|1|0|0|
>+--+-+-+-+-+-+-+-+-+-+-+
>
> 1. Channel #2 has been occupied, so bit #2 is 1, and the others
>are all 0.
> 2. Another thread tries to find 4 free channels from #0.
> 3. In the 1st loop, pos starts from 0, and then it checks if the
>following 4 bits are all 0, but fails, as bit#2 is 1.
> 4. In the 2st loop, pos is not updated, and still starts from 0,
>so nothing changes against loop #1.
> 5. Dead loop ...
>
> This patch is to update the pos in step #3 to avoid the issue.
>
> Fixes: 7bd1d4093c2f ("stm class: Introduce an abstraction for System
> Trace Module devices")
> Signed-off-by: Zhi Jin
> ---
> drivers/hwtracing/stm/core.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/hwtracing/stm/core.c b/drivers/hwtracing/stm/core.c
> index 10bcb5d73f90..c86a979b9bd7 100644
> --- a/drivers/hwtracing/stm/core.c
> +++ b/drivers/hwtracing/stm/core.c
> @@ -244,6 +244,8 @@ static int find_free_channels(unsigned long *bitmap,
> unsigned int start,
> ;
> if (i == width)
> return pos;
> +
> + pos += i;
> }
>
> return -1;
> --
> 2.7.4
Re: [PATCH] mm: Speed up mremap on large regions
On Fri, Oct 12, 2018 at 7:29 AM Juergen Gross wrote:
> On 12/10/2018 05:21, Jann Horn wrote:
> > +cc xen maintainers and kvm folks
> >
> > On Fri, Oct 12, 2018 at 4:40 AM Joel Fernandes (Google)
> > wrote:
> >> Android needs to mremap large regions of memory during memory management
> >> related operations. The mremap system call can be really slow if THP is
> >> not enabled. The bottleneck is move_page_tables, which is copying each
> >> pte at a time, and can be really slow across a large map. Turning on THP
> >> may not be a viable option, and is not for us. This patch speeds up the
> >> performance for non-THP system by copying at the PMD level when possible.
> > [...]
> >> +bool move_normal_pmd(struct vm_area_struct *vma, unsigned long old_addr,
> >> + unsigned long new_addr, unsigned long old_end,
> >> + pmd_t *old_pmd, pmd_t *new_pmd, bool *need_flush)
> >> +{
> > [...]
> >> + /*
> >> +* We don't have to worry about the ordering of src and dst
> >> +* ptlocks because exclusive mmap_sem prevents deadlock.
> >> +*/
> >> + old_ptl = pmd_lock(vma->vm_mm, old_pmd);
> >> + if (old_ptl) {
> >> + pmd_t pmd;
> >> +
> >> + new_ptl = pmd_lockptr(mm, new_pmd);
> >> + if (new_ptl != old_ptl)
> >> + spin_lock_nested(new_ptl, SINGLE_DEPTH_NESTING);
> >> +
> >> + /* Clear the pmd */
> >> + pmd = *old_pmd;
> >> + pmd_clear(old_pmd);
> >> +
> >> + VM_BUG_ON(!pmd_none(*new_pmd));
> >> +
> >> + /* Set the new pmd */
> >> + set_pmd_at(mm, new_addr, new_pmd, pmd);
> >> + if (new_ptl != old_ptl)
> >> + spin_unlock(new_ptl);
> >> + spin_unlock(old_ptl);
> >
> > How does this interact with Xen PV? From a quick look at the Xen PV
> > integration code in xen_alloc_ptpage(), it looks to me as if, in a
> > config that doesn't use split ptlocks, this is going to temporarily
> > drop Xen's type count for the page to zero, causing Xen to de-validate
> > and then re-validate the L1 pagetable; if you first set the new pmd
> > before clearing the old one, that wouldn't happen. I don't know how
> > this interacts with shadow paging implementations.
>
> No, this isn't an issue. As the L1 pagetable isn't being released it
> will stay pinned, so there will be no need to revalidate it.
Where exactly is the L1 pagetable pinned? xen_alloc_ptpage() does:
if (static_branch_likely(_struct_pages_ready))
SetPagePinned(page);
if (!PageHighMem(page)) {
xen_mc_batch();
__set_pfn_prot(pfn, PAGE_KERNEL_RO);
if (level == PT_PTE && USE_SPLIT_PTE_PTLOCKS)
__pin_pagetable_pfn(MMUEXT_PIN_L1_TABLE, pfn);
xen_mc_issue(PARAVIRT_LAZY_MMU);
} else {
/* make sure there are no stray mappings of
this page */
kmap_flush_unused();
}
which means that if USE_SPLIT_PTE_PTLOCKS is false, the table doesn't
get pinned and only stays typed as long as it is referenced by an L2
table, right?
Re: [PATCH] mm: Speed up mremap on large regions
On Fri, Oct 12, 2018 at 7:29 AM Juergen Gross wrote:
> On 12/10/2018 05:21, Jann Horn wrote:
> > +cc xen maintainers and kvm folks
> >
> > On Fri, Oct 12, 2018 at 4:40 AM Joel Fernandes (Google)
> > wrote:
> >> Android needs to mremap large regions of memory during memory management
> >> related operations. The mremap system call can be really slow if THP is
> >> not enabled. The bottleneck is move_page_tables, which is copying each
> >> pte at a time, and can be really slow across a large map. Turning on THP
> >> may not be a viable option, and is not for us. This patch speeds up the
> >> performance for non-THP system by copying at the PMD level when possible.
> > [...]
> >> +bool move_normal_pmd(struct vm_area_struct *vma, unsigned long old_addr,
> >> + unsigned long new_addr, unsigned long old_end,
> >> + pmd_t *old_pmd, pmd_t *new_pmd, bool *need_flush)
> >> +{
> > [...]
> >> + /*
> >> +* We don't have to worry about the ordering of src and dst
> >> +* ptlocks because exclusive mmap_sem prevents deadlock.
> >> +*/
> >> + old_ptl = pmd_lock(vma->vm_mm, old_pmd);
> >> + if (old_ptl) {
> >> + pmd_t pmd;
> >> +
> >> + new_ptl = pmd_lockptr(mm, new_pmd);
> >> + if (new_ptl != old_ptl)
> >> + spin_lock_nested(new_ptl, SINGLE_DEPTH_NESTING);
> >> +
> >> + /* Clear the pmd */
> >> + pmd = *old_pmd;
> >> + pmd_clear(old_pmd);
> >> +
> >> + VM_BUG_ON(!pmd_none(*new_pmd));
> >> +
> >> + /* Set the new pmd */
> >> + set_pmd_at(mm, new_addr, new_pmd, pmd);
> >> + if (new_ptl != old_ptl)
> >> + spin_unlock(new_ptl);
> >> + spin_unlock(old_ptl);
> >
> > How does this interact with Xen PV? From a quick look at the Xen PV
> > integration code in xen_alloc_ptpage(), it looks to me as if, in a
> > config that doesn't use split ptlocks, this is going to temporarily
> > drop Xen's type count for the page to zero, causing Xen to de-validate
> > and then re-validate the L1 pagetable; if you first set the new pmd
> > before clearing the old one, that wouldn't happen. I don't know how
> > this interacts with shadow paging implementations.
>
> No, this isn't an issue. As the L1 pagetable isn't being released it
> will stay pinned, so there will be no need to revalidate it.
Where exactly is the L1 pagetable pinned? xen_alloc_ptpage() does:
if (static_branch_likely(_struct_pages_ready))
SetPagePinned(page);
if (!PageHighMem(page)) {
xen_mc_batch();
__set_pfn_prot(pfn, PAGE_KERNEL_RO);
if (level == PT_PTE && USE_SPLIT_PTE_PTLOCKS)
__pin_pagetable_pfn(MMUEXT_PIN_L1_TABLE, pfn);
xen_mc_issue(PARAVIRT_LAZY_MMU);
} else {
/* make sure there are no stray mappings of
this page */
kmap_flush_unused();
}
which means that if USE_SPLIT_PTE_PTLOCKS is false, the table doesn't
get pinned and only stays typed as long as it is referenced by an L2
table, right?
Re: [PATCH] mm: Speed up mremap on large regions
On 12/10/2018 05:21, Jann Horn wrote:
> +cc xen maintainers and kvm folks
>
> On Fri, Oct 12, 2018 at 4:40 AM Joel Fernandes (Google)
> wrote:
>> Android needs to mremap large regions of memory during memory management
>> related operations. The mremap system call can be really slow if THP is
>> not enabled. The bottleneck is move_page_tables, which is copying each
>> pte at a time, and can be really slow across a large map. Turning on THP
>> may not be a viable option, and is not for us. This patch speeds up the
>> performance for non-THP system by copying at the PMD level when possible.
> [...]
>> +bool move_normal_pmd(struct vm_area_struct *vma, unsigned long old_addr,
>> + unsigned long new_addr, unsigned long old_end,
>> + pmd_t *old_pmd, pmd_t *new_pmd, bool *need_flush)
>> +{
> [...]
>> + /*
>> +* We don't have to worry about the ordering of src and dst
>> +* ptlocks because exclusive mmap_sem prevents deadlock.
>> +*/
>> + old_ptl = pmd_lock(vma->vm_mm, old_pmd);
>> + if (old_ptl) {
>> + pmd_t pmd;
>> +
>> + new_ptl = pmd_lockptr(mm, new_pmd);
>> + if (new_ptl != old_ptl)
>> + spin_lock_nested(new_ptl, SINGLE_DEPTH_NESTING);
>> +
>> + /* Clear the pmd */
>> + pmd = *old_pmd;
>> + pmd_clear(old_pmd);
>> +
>> + VM_BUG_ON(!pmd_none(*new_pmd));
>> +
>> + /* Set the new pmd */
>> + set_pmd_at(mm, new_addr, new_pmd, pmd);
>> + if (new_ptl != old_ptl)
>> + spin_unlock(new_ptl);
>> + spin_unlock(old_ptl);
>
> How does this interact with Xen PV? From a quick look at the Xen PV
> integration code in xen_alloc_ptpage(), it looks to me as if, in a
> config that doesn't use split ptlocks, this is going to temporarily
> drop Xen's type count for the page to zero, causing Xen to de-validate
> and then re-validate the L1 pagetable; if you first set the new pmd
> before clearing the old one, that wouldn't happen. I don't know how
> this interacts with shadow paging implementations.
No, this isn't an issue. As the L1 pagetable isn't being released it
will stay pinned, so there will be no need to revalidate it.
For Xen in shadow mode I'm quite sure it just doesn't matter. In the
case another thread of the process is accessing the memory in parallel
it might even be better to not having a L1 pagetable with 2 references
at the same time, but this is an academic problem which doesn't need to
be tuned for performance IMO.
Juergen
Re: [PATCH] mm: Speed up mremap on large regions
On 12/10/2018 05:21, Jann Horn wrote:
> +cc xen maintainers and kvm folks
>
> On Fri, Oct 12, 2018 at 4:40 AM Joel Fernandes (Google)
> wrote:
>> Android needs to mremap large regions of memory during memory management
>> related operations. The mremap system call can be really slow if THP is
>> not enabled. The bottleneck is move_page_tables, which is copying each
>> pte at a time, and can be really slow across a large map. Turning on THP
>> may not be a viable option, and is not for us. This patch speeds up the
>> performance for non-THP system by copying at the PMD level when possible.
> [...]
>> +bool move_normal_pmd(struct vm_area_struct *vma, unsigned long old_addr,
>> + unsigned long new_addr, unsigned long old_end,
>> + pmd_t *old_pmd, pmd_t *new_pmd, bool *need_flush)
>> +{
> [...]
>> + /*
>> +* We don't have to worry about the ordering of src and dst
>> +* ptlocks because exclusive mmap_sem prevents deadlock.
>> +*/
>> + old_ptl = pmd_lock(vma->vm_mm, old_pmd);
>> + if (old_ptl) {
>> + pmd_t pmd;
>> +
>> + new_ptl = pmd_lockptr(mm, new_pmd);
>> + if (new_ptl != old_ptl)
>> + spin_lock_nested(new_ptl, SINGLE_DEPTH_NESTING);
>> +
>> + /* Clear the pmd */
>> + pmd = *old_pmd;
>> + pmd_clear(old_pmd);
>> +
>> + VM_BUG_ON(!pmd_none(*new_pmd));
>> +
>> + /* Set the new pmd */
>> + set_pmd_at(mm, new_addr, new_pmd, pmd);
>> + if (new_ptl != old_ptl)
>> + spin_unlock(new_ptl);
>> + spin_unlock(old_ptl);
>
> How does this interact with Xen PV? From a quick look at the Xen PV
> integration code in xen_alloc_ptpage(), it looks to me as if, in a
> config that doesn't use split ptlocks, this is going to temporarily
> drop Xen's type count for the page to zero, causing Xen to de-validate
> and then re-validate the L1 pagetable; if you first set the new pmd
> before clearing the old one, that wouldn't happen. I don't know how
> this interacts with shadow paging implementations.
No, this isn't an issue. As the L1 pagetable isn't being released it
will stay pinned, so there will be no need to revalidate it.
For Xen in shadow mode I'm quite sure it just doesn't matter. In the
case another thread of the process is accessing the memory in parallel
it might even be better to not having a L1 pagetable with 2 references
at the same time, but this is an academic problem which doesn't need to
be tuned for performance IMO.
Juergen
linux-next: build warning after merge of the scsi-mkp tree
Hi all,
After merging the scsi-mkp tree, today's linux-next build (x86_64
allmodconfig) produced this warning:
./usr/include/scsi/scsi_bsg_ufs.h:45: found __[us]{8,16,32,64} type without
#include
Introduced by commits
a851b2bd3632 ("scsi: uapi: ufs: Make utp_upiu_req visible to user space")
e77044c5a842 ("scsi: ufs-bsg: Add support for uic commands in
ufs_bsg_request()")
--
Cheers,
Stephen Rothwell
pgpJbxIvcQKDS.pgp
Description: OpenPGP digital signature
linux-next: build warning after merge of the scsi-mkp tree
Hi all,
After merging the scsi-mkp tree, today's linux-next build (x86_64
allmodconfig) produced this warning:
./usr/include/scsi/scsi_bsg_ufs.h:45: found __[us]{8,16,32,64} type without
#include
Introduced by commits
a851b2bd3632 ("scsi: uapi: ufs: Make utp_upiu_req visible to user space")
e77044c5a842 ("scsi: ufs-bsg: Add support for uic commands in
ufs_bsg_request()")
--
Cheers,
Stephen Rothwell
pgpJbxIvcQKDS.pgp
Description: OpenPGP digital signature
[PATCH V8 15/21] csky: Debug and Ptrace GDB
This patch adds arch ptrace implementation, stack dump and bug.h.
Signed-off-by: Guo Ren
---
arch/csky/include/asm/bug.h | 26 +++
arch/csky/include/uapi/asm/ptrace.h | 104
arch/csky/kernel/dumpstack.c| 66
arch/csky/kernel/ptrace.c | 314
4 files changed, 510 insertions(+)
create mode 100644 arch/csky/include/asm/bug.h
create mode 100644 arch/csky/include/uapi/asm/ptrace.h
create mode 100644 arch/csky/kernel/dumpstack.c
create mode 100644 arch/csky/kernel/ptrace.c
diff --git a/arch/csky/include/asm/bug.h b/arch/csky/include/asm/bug.h
new file mode 100644
index 000..bd7b323
--- /dev/null
+++ b/arch/csky/include/asm/bug.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_BUG_H
+#define __ASM_CSKY_BUG_H
+
+#include
+#include
+#include
+
+#define BUG() \
+do { \
+ asm volatile ("bkpt\n");\
+ unreachable(); \
+} while (0)
+
+#define HAVE_ARCH_BUG
+
+#include
+
+struct pt_regs;
+
+void die_if_kernel(char *str, struct pt_regs *regs, int nr);
+void show_regs(struct pt_regs *regs);
+
+#endif /* __ASM_CSKY_BUG_H */
diff --git a/arch/csky/include/uapi/asm/ptrace.h
b/arch/csky/include/uapi/asm/ptrace.h
new file mode 100644
index 000..f10d02c
--- /dev/null
+++ b/arch/csky/include/uapi/asm/ptrace.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef _CSKY_PTRACE_H
+#define _CSKY_PTRACE_H
+
+#ifndef __ASSEMBLY__
+
+struct pt_regs {
+ unsigned long tls;
+ unsigned long lr;
+ unsigned long pc;
+ unsigned long sr;
+ unsigned long usp;
+
+ /*
+* a0, a1, a2, a3:
+* abiv1: r2, r3, r4, r5
+* abiv2: r0, r1, r2, r3
+*/
+ unsigned long orig_a0;
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+
+ /*
+* ABIV2: r4 ~ r13
+* ABIV1: r6 ~ r14, r1
+*/
+ unsigned long regs[10];
+
+#if defined(__CSKYABIV2__)
+ /* r16 ~ r30 */
+ unsigned long exregs[15];
+
+ unsigned long rhi;
+ unsigned long rlo;
+ unsigned long pad; /* reserved */
+#endif
+};
+
+struct user_fp {
+ unsigned long vr[96];
+ unsigned long fcr;
+ unsigned long fesr;
+ unsigned long fid;
+ unsigned long reserved;
+};
+
+/*
+ * Switch stack for switch_to after push pt_regs.
+ *
+ * ABI_CSKYV2: r4 ~ r11, r15 ~ r17, r26 ~ r30;
+ * ABI_CSKYV1: r8 ~ r14, r15;
+ */
+struct switch_stack {
+#if defined(__CSKYABIV2__)
+ unsigned long r4;
+ unsigned long r5;
+ unsigned long r6;
+ unsigned long r7;
+ unsigned long r8;
+ unsigned long r9;
+ unsigned long r10;
+ unsigned long r11;
+#else
+ unsigned long r8;
+ unsigned long r9;
+ unsigned long r10;
+ unsigned long r11;
+ unsigned long r12;
+ unsigned long r13;
+ unsigned long r14;
+#endif
+ unsigned long r15;
+#if defined(__CSKYABIV2__)
+ unsigned long r16;
+ unsigned long r17;
+ unsigned long r26;
+ unsigned long r27;
+ unsigned long r28;
+ unsigned long r29;
+ unsigned long r30;
+#endif
+};
+
+#ifdef __KERNEL__
+
+#define PS_S 0x8000 /* Supervisor Mode */
+
+#define arch_has_single_step() (1)
+#define current_pt_regs() \
+({ (struct pt_regs *)((char *)current_thread_info() + THREAD_SIZE) - 1; })
+
+#define user_stack_pointer(regs) ((regs)->usp)
+
+#define user_mode(regs) (!((regs)->sr & PS_S))
+#define instruction_pointer(regs) ((regs)->pc)
+#define profile_pc(regs) instruction_pointer(regs)
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+#endif /* _CSKY_PTRACE_H */
diff --git a/arch/csky/kernel/dumpstack.c b/arch/csky/kernel/dumpstack.c
new file mode 100644
index 000..a9a03ac
--- /dev/null
+++ b/arch/csky/kernel/dumpstack.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+
+int kstack_depth_to_print = 48;
+
+void show_trace(unsigned long *stack)
+{
+ unsigned long *endstack;
+ unsigned long addr;
+ int i;
+
+ pr_info("Call Trace:\n");
+ addr = (unsigned long)stack + THREAD_SIZE - 1;
+ endstack = (unsigned long *)(addr & -THREAD_SIZE);
+ i = 0;
+ while (stack + 1 <= endstack) {
+ addr = *stack++;
+ /*
+* If the address is either in the text segment of the
+* kernel, or in the region which contains vmalloc'ed
+* memory, it *may* be the address of a calling
+* routine; if so, print it so that someone
[PATCH V8 15/21] csky: Debug and Ptrace GDB
This patch adds arch ptrace implementation, stack dump and bug.h.
Signed-off-by: Guo Ren
---
arch/csky/include/asm/bug.h | 26 +++
arch/csky/include/uapi/asm/ptrace.h | 104
arch/csky/kernel/dumpstack.c| 66
arch/csky/kernel/ptrace.c | 314
4 files changed, 510 insertions(+)
create mode 100644 arch/csky/include/asm/bug.h
create mode 100644 arch/csky/include/uapi/asm/ptrace.h
create mode 100644 arch/csky/kernel/dumpstack.c
create mode 100644 arch/csky/kernel/ptrace.c
diff --git a/arch/csky/include/asm/bug.h b/arch/csky/include/asm/bug.h
new file mode 100644
index 000..bd7b323
--- /dev/null
+++ b/arch/csky/include/asm/bug.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_BUG_H
+#define __ASM_CSKY_BUG_H
+
+#include
+#include
+#include
+
+#define BUG() \
+do { \
+ asm volatile ("bkpt\n");\
+ unreachable(); \
+} while (0)
+
+#define HAVE_ARCH_BUG
+
+#include
+
+struct pt_regs;
+
+void die_if_kernel(char *str, struct pt_regs *regs, int nr);
+void show_regs(struct pt_regs *regs);
+
+#endif /* __ASM_CSKY_BUG_H */
diff --git a/arch/csky/include/uapi/asm/ptrace.h
b/arch/csky/include/uapi/asm/ptrace.h
new file mode 100644
index 000..f10d02c
--- /dev/null
+++ b/arch/csky/include/uapi/asm/ptrace.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef _CSKY_PTRACE_H
+#define _CSKY_PTRACE_H
+
+#ifndef __ASSEMBLY__
+
+struct pt_regs {
+ unsigned long tls;
+ unsigned long lr;
+ unsigned long pc;
+ unsigned long sr;
+ unsigned long usp;
+
+ /*
+* a0, a1, a2, a3:
+* abiv1: r2, r3, r4, r5
+* abiv2: r0, r1, r2, r3
+*/
+ unsigned long orig_a0;
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+
+ /*
+* ABIV2: r4 ~ r13
+* ABIV1: r6 ~ r14, r1
+*/
+ unsigned long regs[10];
+
+#if defined(__CSKYABIV2__)
+ /* r16 ~ r30 */
+ unsigned long exregs[15];
+
+ unsigned long rhi;
+ unsigned long rlo;
+ unsigned long pad; /* reserved */
+#endif
+};
+
+struct user_fp {
+ unsigned long vr[96];
+ unsigned long fcr;
+ unsigned long fesr;
+ unsigned long fid;
+ unsigned long reserved;
+};
+
+/*
+ * Switch stack for switch_to after push pt_regs.
+ *
+ * ABI_CSKYV2: r4 ~ r11, r15 ~ r17, r26 ~ r30;
+ * ABI_CSKYV1: r8 ~ r14, r15;
+ */
+struct switch_stack {
+#if defined(__CSKYABIV2__)
+ unsigned long r4;
+ unsigned long r5;
+ unsigned long r6;
+ unsigned long r7;
+ unsigned long r8;
+ unsigned long r9;
+ unsigned long r10;
+ unsigned long r11;
+#else
+ unsigned long r8;
+ unsigned long r9;
+ unsigned long r10;
+ unsigned long r11;
+ unsigned long r12;
+ unsigned long r13;
+ unsigned long r14;
+#endif
+ unsigned long r15;
+#if defined(__CSKYABIV2__)
+ unsigned long r16;
+ unsigned long r17;
+ unsigned long r26;
+ unsigned long r27;
+ unsigned long r28;
+ unsigned long r29;
+ unsigned long r30;
+#endif
+};
+
+#ifdef __KERNEL__
+
+#define PS_S 0x8000 /* Supervisor Mode */
+
+#define arch_has_single_step() (1)
+#define current_pt_regs() \
+({ (struct pt_regs *)((char *)current_thread_info() + THREAD_SIZE) - 1; })
+
+#define user_stack_pointer(regs) ((regs)->usp)
+
+#define user_mode(regs) (!((regs)->sr & PS_S))
+#define instruction_pointer(regs) ((regs)->pc)
+#define profile_pc(regs) instruction_pointer(regs)
+
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+#endif /* _CSKY_PTRACE_H */
diff --git a/arch/csky/kernel/dumpstack.c b/arch/csky/kernel/dumpstack.c
new file mode 100644
index 000..a9a03ac
--- /dev/null
+++ b/arch/csky/kernel/dumpstack.c
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+
+int kstack_depth_to_print = 48;
+
+void show_trace(unsigned long *stack)
+{
+ unsigned long *endstack;
+ unsigned long addr;
+ int i;
+
+ pr_info("Call Trace:\n");
+ addr = (unsigned long)stack + THREAD_SIZE - 1;
+ endstack = (unsigned long *)(addr & -THREAD_SIZE);
+ i = 0;
+ while (stack + 1 <= endstack) {
+ addr = *stack++;
+ /*
+* If the address is either in the text segment of the
+* kernel, or in the region which contains vmalloc'ed
+* memory, it *may* be the address of a calling
+* routine; if so, print it so that someone
[PATCH V8 16/21] csky: SMP support
This patch adds boot, ipi, hotplug code for SMP.
Changelog:
- remove set_ipi_irq_mapping callback.
- Convert the cpumask to an interrupt-controller specific representation
in driver's code, and not the SMP code's.
- csky: remove irq_mapping from smp.c
There are some feedbacks from irqchip, and we need to adjust
"smp.c & smp.h" to match the csky_mp_intc modification.
- Move IPI_IRQ define into drivers/irqchip/csky_mpintc.c, because it's a
interrupt controller specific.
- Bugfix request_irq with IPI_IRQ, we must use irq_mapping return value
not directly use IPI_IRQ. The modification also involves csky_mp_intc.
Signed-off-by: Guo Ren
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: Peter Zijlstra
---
arch/csky/include/asm/smp.h | 28 ++
arch/csky/kernel/smp.c | 237
2 files changed, 265 insertions(+)
create mode 100644 arch/csky/include/asm/smp.h
create mode 100644 arch/csky/kernel/smp.c
diff --git a/arch/csky/include/asm/smp.h b/arch/csky/include/asm/smp.h
new file mode 100644
index 000..31f7b94
--- /dev/null
+++ b/arch/csky/include/asm/smp.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASM_CSKY_SMP_H
+#define __ASM_CSKY_SMP_H
+
+#include
+#include
+#include
+
+#ifdef CONFIG_SMP
+
+void __init setup_smp(void);
+
+void __init setup_smp_ipi(void);
+
+void __init enable_smp_ipi(void);
+
+void arch_send_call_function_ipi_mask(struct cpumask *mask);
+
+void arch_send_call_function_single_ipi(int cpu);
+
+void __init set_send_ipi(void (*func)(const struct cpumask *mask), int irq);
+
+#define raw_smp_processor_id() (current_thread_info()->cpu)
+
+#endif /* CONFIG_SMP */
+
+#endif /* __ASM_CSKY_SMP_H */
diff --git a/arch/csky/kernel/smp.c b/arch/csky/kernel/smp.c
new file mode 100644
index 000..5ea9516
--- /dev/null
+++ b/arch/csky/kernel/smp.c
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct {
+ unsigned long bits cacheline_aligned;
+} ipi_data[NR_CPUS] __cacheline_aligned;
+
+enum ipi_message_type {
+ IPI_EMPTY,
+ IPI_RESCHEDULE,
+ IPI_CALL_FUNC,
+ IPI_MAX
+};
+
+static irqreturn_t handle_ipi(int irq, void *dev)
+{
+ unsigned long *pending_ipis = _data[smp_processor_id()].bits;
+
+ while (true) {
+ unsigned long ops;
+
+ ops = xchg(pending_ipis, 0);
+ if (ops == 0)
+ return IRQ_HANDLED;
+
+ if (ops & (1 << IPI_RESCHEDULE))
+ scheduler_ipi();
+
+ if (ops & (1 << IPI_CALL_FUNC))
+ generic_smp_call_function_interrupt();
+
+ BUG_ON((ops >> IPI_MAX) != 0);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void (*send_arch_ipi)(const struct cpumask *mask);
+
+static int ipi_irq;
+void __init set_send_ipi(void (*func)(const struct cpumask *mask), int irq)
+{
+ if (send_arch_ipi)
+ return;
+
+ send_arch_ipi = func;
+ ipi_irq = irq;
+}
+
+static void
+send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type
operation)
+{
+ int i;
+
+ for_each_cpu(i, to_whom)
+ set_bit(operation, _data[i].bits);
+
+ smp_mb();
+ send_arch_ipi(to_whom);
+}
+
+void arch_send_call_function_ipi_mask(struct cpumask *mask)
+{
+ send_ipi_message(mask, IPI_CALL_FUNC);
+}
+
+void arch_send_call_function_single_ipi(int cpu)
+{
+ send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
+}
+
+static void ipi_stop(void *unused)
+{
+ while (1);
+}
+
+void smp_send_stop(void)
+{
+ on_each_cpu(ipi_stop, NULL, 1);
+}
+
+void smp_send_reschedule(int cpu)
+{
+ send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
+}
+
+void *__cpu_up_stack_pointer[NR_CPUS];
+void *__cpu_up_task_pointer[NR_CPUS];
+
+void __init smp_prepare_boot_cpu(void)
+{
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+}
+
+void __init enable_smp_ipi(void)
+{
+ enable_percpu_irq(ipi_irq, 0);
+}
+
+static int ipi_dummy_dev;
+void __init setup_smp_ipi(void)
+{
+ int rc;
+
+ if (ipi_irq == 0)
+ panic("%s IRQ mapping failed\n", __func__);
+
+ rc = request_percpu_irq(ipi_irq, handle_ipi, "IPI Interrupt",
+ _dummy_dev);
+ if (rc)
+ panic("%s IRQ request failed\n", __func__);
+
+ enable_smp_ipi();
+}
+
+void __init setup_smp(void)
+{
+ struct device_node *node = NULL;
+ int cpu;
+
+ while ((node = of_find_node_by_type(node, "cpu"))) {
+ if (!of_device_is_available(node))
+ continue;
+
+ if (of_property_read_u32(node, "reg", ))
+ continue;
+
+
[PATCH V8 16/21] csky: SMP support
This patch adds boot, ipi, hotplug code for SMP.
Changelog:
- remove set_ipi_irq_mapping callback.
- Convert the cpumask to an interrupt-controller specific representation
in driver's code, and not the SMP code's.
- csky: remove irq_mapping from smp.c
There are some feedbacks from irqchip, and we need to adjust
"smp.c & smp.h" to match the csky_mp_intc modification.
- Move IPI_IRQ define into drivers/irqchip/csky_mpintc.c, because it's a
interrupt controller specific.
- Bugfix request_irq with IPI_IRQ, we must use irq_mapping return value
not directly use IPI_IRQ. The modification also involves csky_mp_intc.
Signed-off-by: Guo Ren
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: Peter Zijlstra
---
arch/csky/include/asm/smp.h | 28 ++
arch/csky/kernel/smp.c | 237
2 files changed, 265 insertions(+)
create mode 100644 arch/csky/include/asm/smp.h
create mode 100644 arch/csky/kernel/smp.c
diff --git a/arch/csky/include/asm/smp.h b/arch/csky/include/asm/smp.h
new file mode 100644
index 000..31f7b94
--- /dev/null
+++ b/arch/csky/include/asm/smp.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASM_CSKY_SMP_H
+#define __ASM_CSKY_SMP_H
+
+#include
+#include
+#include
+
+#ifdef CONFIG_SMP
+
+void __init setup_smp(void);
+
+void __init setup_smp_ipi(void);
+
+void __init enable_smp_ipi(void);
+
+void arch_send_call_function_ipi_mask(struct cpumask *mask);
+
+void arch_send_call_function_single_ipi(int cpu);
+
+void __init set_send_ipi(void (*func)(const struct cpumask *mask), int irq);
+
+#define raw_smp_processor_id() (current_thread_info()->cpu)
+
+#endif /* CONFIG_SMP */
+
+#endif /* __ASM_CSKY_SMP_H */
diff --git a/arch/csky/kernel/smp.c b/arch/csky/kernel/smp.c
new file mode 100644
index 000..5ea9516
--- /dev/null
+++ b/arch/csky/kernel/smp.c
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct {
+ unsigned long bits cacheline_aligned;
+} ipi_data[NR_CPUS] __cacheline_aligned;
+
+enum ipi_message_type {
+ IPI_EMPTY,
+ IPI_RESCHEDULE,
+ IPI_CALL_FUNC,
+ IPI_MAX
+};
+
+static irqreturn_t handle_ipi(int irq, void *dev)
+{
+ unsigned long *pending_ipis = _data[smp_processor_id()].bits;
+
+ while (true) {
+ unsigned long ops;
+
+ ops = xchg(pending_ipis, 0);
+ if (ops == 0)
+ return IRQ_HANDLED;
+
+ if (ops & (1 << IPI_RESCHEDULE))
+ scheduler_ipi();
+
+ if (ops & (1 << IPI_CALL_FUNC))
+ generic_smp_call_function_interrupt();
+
+ BUG_ON((ops >> IPI_MAX) != 0);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void (*send_arch_ipi)(const struct cpumask *mask);
+
+static int ipi_irq;
+void __init set_send_ipi(void (*func)(const struct cpumask *mask), int irq)
+{
+ if (send_arch_ipi)
+ return;
+
+ send_arch_ipi = func;
+ ipi_irq = irq;
+}
+
+static void
+send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type
operation)
+{
+ int i;
+
+ for_each_cpu(i, to_whom)
+ set_bit(operation, _data[i].bits);
+
+ smp_mb();
+ send_arch_ipi(to_whom);
+}
+
+void arch_send_call_function_ipi_mask(struct cpumask *mask)
+{
+ send_ipi_message(mask, IPI_CALL_FUNC);
+}
+
+void arch_send_call_function_single_ipi(int cpu)
+{
+ send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC);
+}
+
+static void ipi_stop(void *unused)
+{
+ while (1);
+}
+
+void smp_send_stop(void)
+{
+ on_each_cpu(ipi_stop, NULL, 1);
+}
+
+void smp_send_reschedule(int cpu)
+{
+ send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
+}
+
+void *__cpu_up_stack_pointer[NR_CPUS];
+void *__cpu_up_task_pointer[NR_CPUS];
+
+void __init smp_prepare_boot_cpu(void)
+{
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+}
+
+void __init enable_smp_ipi(void)
+{
+ enable_percpu_irq(ipi_irq, 0);
+}
+
+static int ipi_dummy_dev;
+void __init setup_smp_ipi(void)
+{
+ int rc;
+
+ if (ipi_irq == 0)
+ panic("%s IRQ mapping failed\n", __func__);
+
+ rc = request_percpu_irq(ipi_irq, handle_ipi, "IPI Interrupt",
+ _dummy_dev);
+ if (rc)
+ panic("%s IRQ request failed\n", __func__);
+
+ enable_smp_ipi();
+}
+
+void __init setup_smp(void)
+{
+ struct device_node *node = NULL;
+ int cpu;
+
+ while ((node = of_find_node_by_type(node, "cpu"))) {
+ if (!of_device_is_available(node))
+ continue;
+
+ if (of_property_read_u32(node, "reg", ))
+ continue;
+
+
[PATCH V8 14/21] csky: User access
This patch adds "user access from kernel" codes.
Signed-off-by: Guo Ren
---
arch/csky/include/asm/uaccess.h | 416
arch/csky/lib/usercopy.c| 262 +
2 files changed, 678 insertions(+)
create mode 100644 arch/csky/include/asm/uaccess.h
create mode 100644 arch/csky/lib/usercopy.c
diff --git a/arch/csky/include/asm/uaccess.h b/arch/csky/include/asm/uaccess.h
new file mode 100644
index 000..acaf0e210
--- /dev/null
+++ b/arch/csky/include/asm/uaccess.h
@@ -0,0 +1,416 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_UACCESS_H
+#define __ASM_CSKY_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define VERIFY_READ0
+#define VERIFY_WRITE 1
+
+static inline int access_ok(int type, const void *addr, unsigned long size)
+{
+ unsigned long limit = current_thread_info()->addr_limit.seg;
+
+ return (((unsigned long)addr < limit) &&
+ ((unsigned long)(addr + size) < limit));
+}
+
+static inline int verify_area(int type, const void *addr, unsigned long size)
+{
+ return access_ok(type, addr, size) ? 0 : -EFAULT;
+}
+
+#define __addr_ok(addr) (access_ok(VERIFY_READ, addr, 0))
+
+extern int __put_user_bad(void);
+
+/*
+ * Tell gcc we read from memory instead of writing: this is because
+ * we do not write to any memory gcc knows about, so there are no
+ * aliasing issues.
+ */
+
+/*
+ * These are the main single-value transfer routines. They automatically
+ * use the right size if we just have the right pointer type.
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the ugliness from the user.
+ *
+ * The "__xxx" versions of the user access functions are versions that
+ * do not verify the address space, that must have been done previously
+ * with a separate "access_ok()" call (this is used when we do multiple
+ * accesses to the same area of user memory).
+ *
+ * As we use the same address space for kernel and user data on
+ * Ckcore, we can just do these as direct assignments. (Of course, the
+ * exception handling means that it's no longer "just"...)
+ */
+
+#define put_user(x, ptr) \
+ __put_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user(x, ptr) \
+ __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+#define __ptr(x) ((unsigned long *)(x))
+
+#define get_user(x, ptr) \
+ __get_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __get_user(x, ptr) \
+ __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user_nocheck(x, ptr, size) \
+({ \
+ long __pu_err = 0; \
+ typeof(*(ptr)) *__pu_addr = (ptr); \
+ typeof(*(ptr)) __pu_val = (typeof(*(ptr)))(x); \
+ if (__pu_addr) \
+ __put_user_size(__pu_val, (__pu_addr), (size), \
+ __pu_err); \
+ __pu_err; \
+})
+
+#define __put_user_check(x, ptr, size) \
+({ \
+ long __pu_err = -EFAULT;\
+ typeof(*(ptr)) *__pu_addr = (ptr); \
+ typeof(*(ptr)) __pu_val = (typeof(*(ptr)))(x); \
+ if (access_ok(VERIFY_WRITE, __pu_addr, size) && __pu_addr) \
+ __put_user_size(__pu_val, __pu_addr, (size), __pu_err); \
+ __pu_err; \
+})
+
+#define __put_user_size(x, ptr, size, retval) \
+do { \
+ retval = 0; \
+ switch (size) { \
+ case 1: \
+ __put_user_asm_b(x, ptr, retval); \
+ break; \
+ case 2: \
+ __put_user_asm_h(x, ptr, retval); \
+ break; \
+ case 4: \
+ __put_user_asm_w(x, ptr, retval); \
+ break; \
+ case 8: \
+ __put_user_asm_64(x, ptr, retval); \
+
[PATCH V8 14/21] csky: User access
This patch adds "user access from kernel" codes.
Signed-off-by: Guo Ren
---
arch/csky/include/asm/uaccess.h | 416
arch/csky/lib/usercopy.c| 262 +
2 files changed, 678 insertions(+)
create mode 100644 arch/csky/include/asm/uaccess.h
create mode 100644 arch/csky/lib/usercopy.c
diff --git a/arch/csky/include/asm/uaccess.h b/arch/csky/include/asm/uaccess.h
new file mode 100644
index 000..acaf0e210
--- /dev/null
+++ b/arch/csky/include/asm/uaccess.h
@@ -0,0 +1,416 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_UACCESS_H
+#define __ASM_CSKY_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define VERIFY_READ0
+#define VERIFY_WRITE 1
+
+static inline int access_ok(int type, const void *addr, unsigned long size)
+{
+ unsigned long limit = current_thread_info()->addr_limit.seg;
+
+ return (((unsigned long)addr < limit) &&
+ ((unsigned long)(addr + size) < limit));
+}
+
+static inline int verify_area(int type, const void *addr, unsigned long size)
+{
+ return access_ok(type, addr, size) ? 0 : -EFAULT;
+}
+
+#define __addr_ok(addr) (access_ok(VERIFY_READ, addr, 0))
+
+extern int __put_user_bad(void);
+
+/*
+ * Tell gcc we read from memory instead of writing: this is because
+ * we do not write to any memory gcc knows about, so there are no
+ * aliasing issues.
+ */
+
+/*
+ * These are the main single-value transfer routines. They automatically
+ * use the right size if we just have the right pointer type.
+ *
+ * This gets kind of ugly. We want to return _two_ values in "get_user()"
+ * and yet we don't want to do any pointers, because that is too much
+ * of a performance impact. Thus we have a few rather ugly macros here,
+ * and hide all the ugliness from the user.
+ *
+ * The "__xxx" versions of the user access functions are versions that
+ * do not verify the address space, that must have been done previously
+ * with a separate "access_ok()" call (this is used when we do multiple
+ * accesses to the same area of user memory).
+ *
+ * As we use the same address space for kernel and user data on
+ * Ckcore, we can just do these as direct assignments. (Of course, the
+ * exception handling means that it's no longer "just"...)
+ */
+
+#define put_user(x, ptr) \
+ __put_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user(x, ptr) \
+ __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+#define __ptr(x) ((unsigned long *)(x))
+
+#define get_user(x, ptr) \
+ __get_user_check((x), (ptr), sizeof(*(ptr)))
+
+#define __get_user(x, ptr) \
+ __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+#define __put_user_nocheck(x, ptr, size) \
+({ \
+ long __pu_err = 0; \
+ typeof(*(ptr)) *__pu_addr = (ptr); \
+ typeof(*(ptr)) __pu_val = (typeof(*(ptr)))(x); \
+ if (__pu_addr) \
+ __put_user_size(__pu_val, (__pu_addr), (size), \
+ __pu_err); \
+ __pu_err; \
+})
+
+#define __put_user_check(x, ptr, size) \
+({ \
+ long __pu_err = -EFAULT;\
+ typeof(*(ptr)) *__pu_addr = (ptr); \
+ typeof(*(ptr)) __pu_val = (typeof(*(ptr)))(x); \
+ if (access_ok(VERIFY_WRITE, __pu_addr, size) && __pu_addr) \
+ __put_user_size(__pu_val, __pu_addr, (size), __pu_err); \
+ __pu_err; \
+})
+
+#define __put_user_size(x, ptr, size, retval) \
+do { \
+ retval = 0; \
+ switch (size) { \
+ case 1: \
+ __put_user_asm_b(x, ptr, retval); \
+ break; \
+ case 2: \
+ __put_user_asm_h(x, ptr, retval); \
+ break; \
+ case 4: \
+ __put_user_asm_w(x, ptr, retval); \
+ break; \
+ case 8: \
+ __put_user_asm_64(x, ptr, retval); \
+
[PATCH V8 12/21] csky: ELF and module probe
This patch adds ELF definition and module relocate codes.
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/elf.h | 26
arch/csky/abiv2/inc/abi/elf.h | 43
arch/csky/include/asm/elf.h | 85 +++
arch/csky/kernel/module.c | 92 +++
4 files changed, 246 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/elf.h
create mode 100644 arch/csky/abiv2/inc/abi/elf.h
create mode 100644 arch/csky/include/asm/elf.h
create mode 100644 arch/csky/kernel/module.c
diff --git a/arch/csky/abiv1/inc/abi/elf.h b/arch/csky/abiv1/inc/abi/elf.h
new file mode 100644
index 000..3058cc0
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/elf.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ABI_CSKY_ELF_H
+#define __ABI_CSKY_ELF_H
+
+#define ELF_CORE_COPY_REGS(pr_reg, regs) do { \
+ pr_reg[0] = regs->pc; \
+ pr_reg[1] = regs->regs[9]; \
+ pr_reg[2] = regs->usp; \
+ pr_reg[3] = regs->sr; \
+ pr_reg[4] = regs->a0; \
+ pr_reg[5] = regs->a1; \
+ pr_reg[6] = regs->a2; \
+ pr_reg[7] = regs->a3; \
+ pr_reg[8] = regs->regs[0]; \
+ pr_reg[9] = regs->regs[1]; \
+ pr_reg[10] = regs->regs[2]; \
+ pr_reg[11] = regs->regs[3]; \
+ pr_reg[12] = regs->regs[4]; \
+ pr_reg[13] = regs->regs[5]; \
+ pr_reg[14] = regs->regs[6]; \
+ pr_reg[15] = regs->regs[7]; \
+ pr_reg[16] = regs->regs[8]; \
+ pr_reg[17] = regs->lr; \
+} while (0);
+#endif /* __ABI_CSKY_ELF_H */
diff --git a/arch/csky/abiv2/inc/abi/elf.h b/arch/csky/abiv2/inc/abi/elf.h
new file mode 100644
index 000..290f49e
--- /dev/null
+++ b/arch/csky/abiv2/inc/abi/elf.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ABI_CSKY_ELF_H
+#define __ABI_CSKY_ELF_H
+
+/* The member sort in array pr_reg[x] is defined by GDB. */
+#define ELF_CORE_COPY_REGS(pr_reg, regs) do { \
+ pr_reg[0] = regs->pc; \
+ pr_reg[1] = regs->a1; \
+ pr_reg[2] = regs->a0; \
+ pr_reg[3] = regs->sr; \
+ pr_reg[4] = regs->a2; \
+ pr_reg[5] = regs->a3; \
+ pr_reg[6] = regs->regs[0]; \
+ pr_reg[7] = regs->regs[1]; \
+ pr_reg[8] = regs->regs[2]; \
+ pr_reg[9] = regs->regs[3]; \
+ pr_reg[10] = regs->regs[4]; \
+ pr_reg[11] = regs->regs[5]; \
+ pr_reg[12] = regs->regs[6]; \
+ pr_reg[13] = regs->regs[7]; \
+ pr_reg[14] = regs->regs[8]; \
+ pr_reg[15] = regs->regs[9]; \
+ pr_reg[16] = regs->usp; \
+ pr_reg[17] = regs->lr; \
+ pr_reg[18] = regs->exregs[0]; \
+ pr_reg[19] = regs->exregs[1]; \
+ pr_reg[20] = regs->exregs[2]; \
+ pr_reg[21] = regs->exregs[3]; \
+ pr_reg[22] = regs->exregs[4]; \
+ pr_reg[23] = regs->exregs[5]; \
+ pr_reg[24] = regs->exregs[6]; \
+ pr_reg[25] = regs->exregs[7]; \
+ pr_reg[26] = regs->exregs[8]; \
+ pr_reg[27] = regs->exregs[9]; \
+ pr_reg[28] = regs->exregs[10]; \
+ pr_reg[29] = regs->exregs[11]; \
+ pr_reg[30] = regs->exregs[12]; \
+ pr_reg[31] = regs->exregs[13]; \
+ pr_reg[32] = regs->exregs[14]; \
+ pr_reg[33] = regs->tls; \
+} while (0);
+#endif /* __ABI_CSKY_ELF_H */
diff --git a/arch/csky/include/asm/elf.h b/arch/csky/include/asm/elf.h
new file mode 100644
index 000..773b133
--- /dev/null
+++ b/arch/csky/include/asm/elf.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_ELF_H
+#define __ASM_CSKY_ELF_H
+
+#include
+#include
+
+#define ELF_ARCH 252
+
+/* CSKY Relocations */
+#define R_CSKY_NONE 0
+#define R_CSKY_32 1
+#define R_CSKY_PCIMM8BY4 2
+#define R_CSKY_PCIMM11BY2 3
+#define R_CSKY_PCIMM4BY2 4
+#define R_CSKY_PC32 5
+#define R_CSKY_PCRELJSR_IMM11BY2 6
+#define R_CSKY_GNU_VTINHERIT 7
+#define R_CSKY_GNU_VTENTRY8
+#define R_CSKY_RELATIVE 9
+#define R_CSKY_COPY 10
+#define R_CSKY_GLOB_DAT 11
+#define R_CSKY_JUMP_SLOT 12
+#define R_CSKY_ADDR_HI16 24
+#define R_CSKY_ADDR_LO16 25
+#define R_CSKY_PCRELJSR_IMM26BY2
[PATCH V8 12/21] csky: ELF and module probe
This patch adds ELF definition and module relocate codes.
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/elf.h | 26
arch/csky/abiv2/inc/abi/elf.h | 43
arch/csky/include/asm/elf.h | 85 +++
arch/csky/kernel/module.c | 92 +++
4 files changed, 246 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/elf.h
create mode 100644 arch/csky/abiv2/inc/abi/elf.h
create mode 100644 arch/csky/include/asm/elf.h
create mode 100644 arch/csky/kernel/module.c
diff --git a/arch/csky/abiv1/inc/abi/elf.h b/arch/csky/abiv1/inc/abi/elf.h
new file mode 100644
index 000..3058cc0
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/elf.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ABI_CSKY_ELF_H
+#define __ABI_CSKY_ELF_H
+
+#define ELF_CORE_COPY_REGS(pr_reg, regs) do { \
+ pr_reg[0] = regs->pc; \
+ pr_reg[1] = regs->regs[9]; \
+ pr_reg[2] = regs->usp; \
+ pr_reg[3] = regs->sr; \
+ pr_reg[4] = regs->a0; \
+ pr_reg[5] = regs->a1; \
+ pr_reg[6] = regs->a2; \
+ pr_reg[7] = regs->a3; \
+ pr_reg[8] = regs->regs[0]; \
+ pr_reg[9] = regs->regs[1]; \
+ pr_reg[10] = regs->regs[2]; \
+ pr_reg[11] = regs->regs[3]; \
+ pr_reg[12] = regs->regs[4]; \
+ pr_reg[13] = regs->regs[5]; \
+ pr_reg[14] = regs->regs[6]; \
+ pr_reg[15] = regs->regs[7]; \
+ pr_reg[16] = regs->regs[8]; \
+ pr_reg[17] = regs->lr; \
+} while (0);
+#endif /* __ABI_CSKY_ELF_H */
diff --git a/arch/csky/abiv2/inc/abi/elf.h b/arch/csky/abiv2/inc/abi/elf.h
new file mode 100644
index 000..290f49e
--- /dev/null
+++ b/arch/csky/abiv2/inc/abi/elf.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ABI_CSKY_ELF_H
+#define __ABI_CSKY_ELF_H
+
+/* The member sort in array pr_reg[x] is defined by GDB. */
+#define ELF_CORE_COPY_REGS(pr_reg, regs) do { \
+ pr_reg[0] = regs->pc; \
+ pr_reg[1] = regs->a1; \
+ pr_reg[2] = regs->a0; \
+ pr_reg[3] = regs->sr; \
+ pr_reg[4] = regs->a2; \
+ pr_reg[5] = regs->a3; \
+ pr_reg[6] = regs->regs[0]; \
+ pr_reg[7] = regs->regs[1]; \
+ pr_reg[8] = regs->regs[2]; \
+ pr_reg[9] = regs->regs[3]; \
+ pr_reg[10] = regs->regs[4]; \
+ pr_reg[11] = regs->regs[5]; \
+ pr_reg[12] = regs->regs[6]; \
+ pr_reg[13] = regs->regs[7]; \
+ pr_reg[14] = regs->regs[8]; \
+ pr_reg[15] = regs->regs[9]; \
+ pr_reg[16] = regs->usp; \
+ pr_reg[17] = regs->lr; \
+ pr_reg[18] = regs->exregs[0]; \
+ pr_reg[19] = regs->exregs[1]; \
+ pr_reg[20] = regs->exregs[2]; \
+ pr_reg[21] = regs->exregs[3]; \
+ pr_reg[22] = regs->exregs[4]; \
+ pr_reg[23] = regs->exregs[5]; \
+ pr_reg[24] = regs->exregs[6]; \
+ pr_reg[25] = regs->exregs[7]; \
+ pr_reg[26] = regs->exregs[8]; \
+ pr_reg[27] = regs->exregs[9]; \
+ pr_reg[28] = regs->exregs[10]; \
+ pr_reg[29] = regs->exregs[11]; \
+ pr_reg[30] = regs->exregs[12]; \
+ pr_reg[31] = regs->exregs[13]; \
+ pr_reg[32] = regs->exregs[14]; \
+ pr_reg[33] = regs->tls; \
+} while (0);
+#endif /* __ABI_CSKY_ELF_H */
diff --git a/arch/csky/include/asm/elf.h b/arch/csky/include/asm/elf.h
new file mode 100644
index 000..773b133
--- /dev/null
+++ b/arch/csky/include/asm/elf.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_ELF_H
+#define __ASM_CSKY_ELF_H
+
+#include
+#include
+
+#define ELF_ARCH 252
+
+/* CSKY Relocations */
+#define R_CSKY_NONE 0
+#define R_CSKY_32 1
+#define R_CSKY_PCIMM8BY4 2
+#define R_CSKY_PCIMM11BY2 3
+#define R_CSKY_PCIMM4BY2 4
+#define R_CSKY_PC32 5
+#define R_CSKY_PCRELJSR_IMM11BY2 6
+#define R_CSKY_GNU_VTINHERIT 7
+#define R_CSKY_GNU_VTENTRY8
+#define R_CSKY_RELATIVE 9
+#define R_CSKY_COPY 10
+#define R_CSKY_GLOB_DAT 11
+#define R_CSKY_JUMP_SLOT 12
+#define R_CSKY_ADDR_HI16 24
+#define R_CSKY_ADDR_LO16 25
+#define R_CSKY_PCRELJSR_IMM26BY2
[PATCH V8 08/21] csky: Process management and Signal
This patch adds files related to task_switch, sigcontext, signal.
Changelog:
- abiv2/fpu.c: Userspace should never be sent NSIGXXX as a si_code.
Use FPE_FLTUNK instead.
- abiv2/fpu.c: Use force_sig_fault instead.
Signed-off-by: Guo Ren
---
arch/csky/abiv2/fpu.c | 275 +
arch/csky/abiv2/inc/abi/fpu.h | 66 ++
arch/csky/include/asm/mmu_context.h | 150 ++
arch/csky/include/asm/processor.h | 121 +++
arch/csky/include/asm/switch_to.h | 36
arch/csky/include/asm/thread_info.h | 75 +++
arch/csky/include/uapi/asm/sigcontext.h | 14 ++
arch/csky/kernel/process.c | 136
arch/csky/kernel/signal.c | 355
arch/csky/kernel/time.c | 11 +
10 files changed, 1239 insertions(+)
create mode 100644 arch/csky/abiv2/fpu.c
create mode 100644 arch/csky/abiv2/inc/abi/fpu.h
create mode 100644 arch/csky/include/asm/mmu_context.h
create mode 100644 arch/csky/include/asm/processor.h
create mode 100644 arch/csky/include/asm/switch_to.h
create mode 100644 arch/csky/include/asm/thread_info.h
create mode 100644 arch/csky/include/uapi/asm/sigcontext.h
create mode 100644 arch/csky/kernel/process.c
create mode 100644 arch/csky/kernel/signal.c
create mode 100644 arch/csky/kernel/time.c
diff --git a/arch/csky/abiv2/fpu.c b/arch/csky/abiv2/fpu.c
new file mode 100644
index 000..e7e1134
--- /dev/null
+++ b/arch/csky/abiv2/fpu.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+
+#define MTCR_MASK 0xFC00FFE0
+#define MFCR_MASK 0xFC00FFE0
+#define MTCR_DIST 0xC0006420
+#define MFCR_DIST 0xC0006020
+
+void __init init_fpu(void)
+{
+ mtcr("cr<1, 2>", 0);
+}
+
+/*
+ * fpu_libc_helper() is to help libc to excute:
+ * - mfcr %a, cr<1, 2>
+ * - mfcr %a, cr<2, 2>
+ * - mtcr %a, cr<1, 2>
+ * - mtcr %a, cr<2, 2>
+ */
+int fpu_libc_helper(struct pt_regs *regs)
+{
+ int fault;
+ unsigned long instrptr, regx = 0;
+ unsigned long index = 0, tmp = 0;
+ unsigned long tinstr = 0;
+ u16 instr_hi, instr_low;
+
+ instrptr = instruction_pointer(regs);
+ if (instrptr & 1)
+ return 0;
+
+ fault = __get_user(instr_low, (u16 *)instrptr);
+ if (fault)
+ return 0;
+
+ fault = __get_user(instr_hi, (u16 *)(instrptr + 2));
+ if (fault)
+ return 0;
+
+ tinstr = instr_hi | ((unsigned long)instr_low << 16);
+
+ if (((tinstr >> 21) & 0x1F) != 2)
+ return 0;
+
+ if ((tinstr & MTCR_MASK) == MTCR_DIST) {
+ index = (tinstr >> 16) & 0x1F;
+ if (index > 13)
+ return 0;
+
+ tmp = tinstr & 0x1F;
+ if (tmp > 2)
+ return 0;
+
+ regx = *(>a0 + index);
+
+ if (tmp == 1)
+ mtcr("cr<1, 2>", regx);
+ else if (tmp == 2)
+ mtcr("cr<2, 2>", regx);
+ else
+ return 0;
+
+ regs->pc += 4;
+ return 1;
+ }
+
+ if ((tinstr & MFCR_MASK) == MFCR_DIST) {
+ index = tinstr & 0x1F;
+ if (index > 13)
+ return 0;
+
+ tmp = ((tinstr >> 16) & 0x1F);
+ if (tmp > 2)
+ return 0;
+
+ if (tmp == 1)
+ regx = mfcr("cr<1, 2>");
+ else if (tmp == 2)
+ regx = mfcr("cr<2, 2>");
+ else
+ return 0;
+
+ *(>a0 + index) = regx;
+
+ regs->pc += 4;
+ return 1;
+ }
+
+ return 0;
+}
+
+void fpu_fpe(struct pt_regs *regs)
+{
+ int sig, code;
+ unsigned int fesr;
+
+ fesr = mfcr("cr<2, 2>");
+
+ sig = SIGFPE;
+ code = FPE_FLTUNK;
+
+ if (fesr & FPE_ILLE) {
+ sig = SIGILL;
+ code = ILL_ILLOPC;
+ } else if (fesr & FPE_IDC) {
+ sig = SIGILL;
+ code = ILL_ILLOPN;
+ } else if (fesr & FPE_FEC) {
+ sig = SIGFPE;
+ if (fesr & FPE_IOC)
+ code = FPE_FLTINV;
+ else if (fesr & FPE_DZC)
+ code = FPE_FLTDIV;
+ else if (fesr & FPE_UFC)
+ code = FPE_FLTUND;
+ else if (fesr & FPE_OFC)
+ code = FPE_FLTOVF;
+ else if (fesr & FPE_IXC)
+ code = FPE_FLTRES;
+ }
+
+ force_sig_fault(sig, code, (void __user *)regs->pc, current);
+}
+
+#define FMFVR_FPU_REGS(vrx, vry) \
+ "fmfvrl %0, "#vrx"\n" \
+ "fmfvrh %1, "#vrx"\n"
[PATCH V8 08/21] csky: Process management and Signal
This patch adds files related to task_switch, sigcontext, signal.
Changelog:
- abiv2/fpu.c: Userspace should never be sent NSIGXXX as a si_code.
Use FPE_FLTUNK instead.
- abiv2/fpu.c: Use force_sig_fault instead.
Signed-off-by: Guo Ren
---
arch/csky/abiv2/fpu.c | 275 +
arch/csky/abiv2/inc/abi/fpu.h | 66 ++
arch/csky/include/asm/mmu_context.h | 150 ++
arch/csky/include/asm/processor.h | 121 +++
arch/csky/include/asm/switch_to.h | 36
arch/csky/include/asm/thread_info.h | 75 +++
arch/csky/include/uapi/asm/sigcontext.h | 14 ++
arch/csky/kernel/process.c | 136
arch/csky/kernel/signal.c | 355
arch/csky/kernel/time.c | 11 +
10 files changed, 1239 insertions(+)
create mode 100644 arch/csky/abiv2/fpu.c
create mode 100644 arch/csky/abiv2/inc/abi/fpu.h
create mode 100644 arch/csky/include/asm/mmu_context.h
create mode 100644 arch/csky/include/asm/processor.h
create mode 100644 arch/csky/include/asm/switch_to.h
create mode 100644 arch/csky/include/asm/thread_info.h
create mode 100644 arch/csky/include/uapi/asm/sigcontext.h
create mode 100644 arch/csky/kernel/process.c
create mode 100644 arch/csky/kernel/signal.c
create mode 100644 arch/csky/kernel/time.c
diff --git a/arch/csky/abiv2/fpu.c b/arch/csky/abiv2/fpu.c
new file mode 100644
index 000..e7e1134
--- /dev/null
+++ b/arch/csky/abiv2/fpu.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+
+#define MTCR_MASK 0xFC00FFE0
+#define MFCR_MASK 0xFC00FFE0
+#define MTCR_DIST 0xC0006420
+#define MFCR_DIST 0xC0006020
+
+void __init init_fpu(void)
+{
+ mtcr("cr<1, 2>", 0);
+}
+
+/*
+ * fpu_libc_helper() is to help libc to excute:
+ * - mfcr %a, cr<1, 2>
+ * - mfcr %a, cr<2, 2>
+ * - mtcr %a, cr<1, 2>
+ * - mtcr %a, cr<2, 2>
+ */
+int fpu_libc_helper(struct pt_regs *regs)
+{
+ int fault;
+ unsigned long instrptr, regx = 0;
+ unsigned long index = 0, tmp = 0;
+ unsigned long tinstr = 0;
+ u16 instr_hi, instr_low;
+
+ instrptr = instruction_pointer(regs);
+ if (instrptr & 1)
+ return 0;
+
+ fault = __get_user(instr_low, (u16 *)instrptr);
+ if (fault)
+ return 0;
+
+ fault = __get_user(instr_hi, (u16 *)(instrptr + 2));
+ if (fault)
+ return 0;
+
+ tinstr = instr_hi | ((unsigned long)instr_low << 16);
+
+ if (((tinstr >> 21) & 0x1F) != 2)
+ return 0;
+
+ if ((tinstr & MTCR_MASK) == MTCR_DIST) {
+ index = (tinstr >> 16) & 0x1F;
+ if (index > 13)
+ return 0;
+
+ tmp = tinstr & 0x1F;
+ if (tmp > 2)
+ return 0;
+
+ regx = *(>a0 + index);
+
+ if (tmp == 1)
+ mtcr("cr<1, 2>", regx);
+ else if (tmp == 2)
+ mtcr("cr<2, 2>", regx);
+ else
+ return 0;
+
+ regs->pc += 4;
+ return 1;
+ }
+
+ if ((tinstr & MFCR_MASK) == MFCR_DIST) {
+ index = tinstr & 0x1F;
+ if (index > 13)
+ return 0;
+
+ tmp = ((tinstr >> 16) & 0x1F);
+ if (tmp > 2)
+ return 0;
+
+ if (tmp == 1)
+ regx = mfcr("cr<1, 2>");
+ else if (tmp == 2)
+ regx = mfcr("cr<2, 2>");
+ else
+ return 0;
+
+ *(>a0 + index) = regx;
+
+ regs->pc += 4;
+ return 1;
+ }
+
+ return 0;
+}
+
+void fpu_fpe(struct pt_regs *regs)
+{
+ int sig, code;
+ unsigned int fesr;
+
+ fesr = mfcr("cr<2, 2>");
+
+ sig = SIGFPE;
+ code = FPE_FLTUNK;
+
+ if (fesr & FPE_ILLE) {
+ sig = SIGILL;
+ code = ILL_ILLOPC;
+ } else if (fesr & FPE_IDC) {
+ sig = SIGILL;
+ code = ILL_ILLOPN;
+ } else if (fesr & FPE_FEC) {
+ sig = SIGFPE;
+ if (fesr & FPE_IOC)
+ code = FPE_FLTINV;
+ else if (fesr & FPE_DZC)
+ code = FPE_FLTDIV;
+ else if (fesr & FPE_UFC)
+ code = FPE_FLTUND;
+ else if (fesr & FPE_OFC)
+ code = FPE_FLTOVF;
+ else if (fesr & FPE_IXC)
+ code = FPE_FLTRES;
+ }
+
+ force_sig_fault(sig, code, (void __user *)regs->pc, current);
+}
+
+#define FMFVR_FPU_REGS(vrx, vry) \
+ "fmfvrl %0, "#vrx"\n" \
+ "fmfvrh %1, "#vrx"\n"
[PATCH V8 06/21] csky: Cache and TLB routines
This patch adds cache and tlb sync codes for abiv1 & abiv2.
Changelog:
- fixup module compile error for EXPORT_SYMBOL(cache_wbinv_range).
- tlb.h & cacheflush.h:
fix flush_cache_range and tlb_start_vma of abiv1 in
flush_cache_range(vma, ...). cache_wbinv_range() couldn't deal with
vma->mm's asid for cache_flush_line and we use cache_wbinv_all() first.
Wwe'll improve with cache_flush(vma, start, end) in future.
For tlb_start_vma, we make it the same as other arch.
- remove the abi/tlb.h
Signed-off-by: Guo Ren
---
arch/csky/abiv1/cacheflush.c | 52
arch/csky/abiv1/inc/abi/cacheflush.h | 49
arch/csky/abiv2/cacheflush.c | 60 ++
arch/csky/abiv2/inc/abi/cacheflush.h | 46 +++
arch/csky/include/asm/barrier.h | 49
arch/csky/include/asm/cache.h | 30 +
arch/csky/include/asm/cacheflush.h| 9 ++
arch/csky/include/asm/io.h| 24
arch/csky/include/asm/tlb.h | 25
arch/csky/include/asm/tlbflush.h | 25
arch/csky/include/uapi/asm/cachectl.h | 13 ++
arch/csky/mm/cachev1.c| 126 +++
arch/csky/mm/cachev2.c| 79
arch/csky/mm/syscache.c | 32 +
arch/csky/mm/tlb.c| 219 ++
15 files changed, 838 insertions(+)
create mode 100644 arch/csky/abiv1/cacheflush.c
create mode 100644 arch/csky/abiv1/inc/abi/cacheflush.h
create mode 100644 arch/csky/abiv2/cacheflush.c
create mode 100644 arch/csky/abiv2/inc/abi/cacheflush.h
create mode 100644 arch/csky/include/asm/barrier.h
create mode 100644 arch/csky/include/asm/cache.h
create mode 100644 arch/csky/include/asm/cacheflush.h
create mode 100644 arch/csky/include/asm/io.h
create mode 100644 arch/csky/include/asm/tlb.h
create mode 100644 arch/csky/include/asm/tlbflush.h
create mode 100644 arch/csky/include/uapi/asm/cachectl.h
create mode 100644 arch/csky/mm/cachev1.c
create mode 100644 arch/csky/mm/cachev2.c
create mode 100644 arch/csky/mm/syscache.c
create mode 100644 arch/csky/mm/tlb.c
diff --git a/arch/csky/abiv1/cacheflush.c b/arch/csky/abiv1/cacheflush.c
new file mode 100644
index 000..10af8b6
--- /dev/null
+++ b/arch/csky/abiv1/cacheflush.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+void flush_dcache_page(struct page *page)
+{
+ struct address_space *mapping = page_mapping(page);
+ unsigned long addr;
+
+ if (mapping && !mapping_mapped(mapping)) {
+ set_bit(PG_arch_1, &(page)->flags);
+ return;
+ }
+
+ /*
+* We could delay the flush for the !page_mapping case too. But that
+* case is for exec env/arg pages and those are %99 certainly going to
+* get faulted into the tlb (and thus flushed) anyways.
+*/
+ addr = (unsigned long) page_address(page);
+ dcache_wb_range(addr, addr + PAGE_SIZE);
+}
+
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
+ pte_t *pte)
+{
+ unsigned long addr;
+ struct page *page;
+ unsigned long pfn;
+
+ pfn = pte_pfn(*pte);
+ if (unlikely(!pfn_valid(pfn)))
+ return;
+
+ page = pfn_to_page(pfn);
+ addr = (unsigned long) page_address(page);
+
+ if (vma->vm_flags & VM_EXEC ||
+ pages_do_alias(addr, address & PAGE_MASK))
+ cache_wbinv_all();
+
+ clear_bit(PG_arch_1, &(page)->flags);
+}
diff --git a/arch/csky/abiv1/inc/abi/cacheflush.h
b/arch/csky/abiv1/inc/abi/cacheflush.h
new file mode 100644
index 000..5f663ae
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/cacheflush.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ABI_CSKY_CACHEFLUSH_H
+#define __ABI_CSKY_CACHEFLUSH_H
+
+#include
+#include
+#include
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+extern void flush_dcache_page(struct page *);
+
+#define flush_cache_mm(mm) cache_wbinv_all()
+#define flush_cache_page(vma, page, pfn) cache_wbinv_all()
+#define flush_cache_dup_mm(mm) cache_wbinv_all()
+
+/*
+ * if (current_mm != vma->mm) cache_wbinv_range(start, end) will be broken.
+ * Use cache_wbinv_all() here and need to be improved in future.
+ */
+#define flush_cache_range(vma, start, end) cache_wbinv_all()
+#define flush_cache_vmap(start, end) cache_wbinv_range(start, end)
+#define flush_cache_vunmap(start, end) cache_wbinv_range(start, end)
+
+#define flush_icache_page(vma, page) cache_wbinv_all()
+#define flush_icache_range(start, end) cache_wbinv_range(start, end)
+
+#define flush_icache_user_range(vma, pg, adr, len) \
+
[PATCH V8 11/21] csky: Atomic operations
This patch adds atomic, cmpxchg, spinlock files.
Changlog:
- SMP supported
- ticklock supported
- queue-rwlock supported
Signed-off-by: Guo Ren
Cc: Peter Zijlstra
Cc: Andrea Parri
---
arch/csky/include/asm/atomic.h | 212 +
arch/csky/include/asm/cmpxchg.h| 73 +
arch/csky/include/asm/spinlock.h | 274 +
arch/csky/include/asm/spinlock_types.h | 37 +
arch/csky/kernel/atomic.S | 87 +++
5 files changed, 683 insertions(+)
create mode 100644 arch/csky/include/asm/atomic.h
create mode 100644 arch/csky/include/asm/cmpxchg.h
create mode 100644 arch/csky/include/asm/spinlock.h
create mode 100644 arch/csky/include/asm/spinlock_types.h
create mode 100644 arch/csky/kernel/atomic.S
diff --git a/arch/csky/include/asm/atomic.h b/arch/csky/include/asm/atomic.h
new file mode 100644
index 000..e369d73
--- /dev/null
+++ b/arch/csky/include/asm/atomic.h
@@ -0,0 +1,212 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASM_CSKY_ATOMIC_H
+#define __ASM_CSKY_ATOMIC_H
+
+#include
+#include
+#include
+
+#ifdef CONFIG_CPU_HAS_LDSTEX
+
+#define __atomic_add_unless __atomic_add_unless
+static inline int __atomic_add_unless(atomic_t *v, int a, int u)
+{
+ unsigned long tmp, ret;
+
+ smp_mb();
+
+ asm volatile (
+ "1: ldex.w %0, (%3) \n"
+ " mov %1, %0 \n"
+ " cmpne %0, %4 \n"
+ " bf 2f \n"
+ " add %0, %2 \n"
+ " stex.w %0, (%3) \n"
+ " bez %0, 1b \n"
+ "2: \n"
+ : "=" (tmp), "=" (ret)
+ : "r" (a), "r"(>counter), "r"(u)
+ : "memory");
+
+ if (ret != u)
+ smp_mb();
+
+ return ret;
+}
+
+#define ATOMIC_OP(op, c_op)\
+static inline void atomic_##op(int i, atomic_t *v) \
+{ \
+ unsigned long tmp; \
+ \
+ asm volatile ( \
+ "1: ldex.w %0, (%2) \n"\
+ " " #op " %0, %1 \n"\
+ " stex.w %0, (%2) \n"\
+ " bez %0, 1b \n"\
+ : "=" (tmp) \
+ : "r" (i), "r"(>counter) \
+ : "memory");\
+}
+
+#define ATOMIC_OP_RETURN(op, c_op) \
+static inline int atomic_##op##_return(int i, atomic_t *v) \
+{ \
+ unsigned long tmp, ret; \
+ \
+ smp_mb(); \
+ asm volatile ( \
+ "1: ldex.w %0, (%3) \n"\
+ " " #op " %0, %2 \n"\
+ " mov %1, %0 \n"\
+ " stex.w %0, (%3) \n"\
+ " bez %0, 1b \n"\
+ : "=" (tmp), "=" (ret) \
+ : "r" (i), "r"(>counter) \
+ : "memory");\
+ smp_mb(); \
+ \
+ return ret; \
+}
+
+#define ATOMIC_FETCH_OP(op, c_op) \
+static inline int atomic_fetch_##op(int i, atomic_t *v)
\
+{ \
+ unsigned long tmp, ret; \
+ \
+ smp_mb(); \
+ asm volatile ( \
+ "1: ldex.w %0, (%3) \n"\
+ " mov %1, %0 \n"\
+ " " #op " %0, %2 \n"\
+ " stex.w %0, (%3)
[PATCH V8 10/21] csky: IRQ handling
This patch adds IRQ handling files.
Changelog:
- Use CONFIG_GENERIC_IRQ_MULTI_HANDLER
Signed-off-by: Guo Ren
Cc: Thomas Gleixner
---
arch/csky/include/asm/irqflags.h | 49
arch/csky/kernel/irq.c | 22 ++
2 files changed, 71 insertions(+)
create mode 100644 arch/csky/include/asm/irqflags.h
create mode 100644 arch/csky/kernel/irq.c
diff --git a/arch/csky/include/asm/irqflags.h b/arch/csky/include/asm/irqflags.h
new file mode 100644
index 000..9e3a569
--- /dev/null
+++ b/arch/csky/include/asm/irqflags.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASM_CSKY_IRQFLAGS_H
+#define __ASM_CSKY_IRQFLAGS_H
+#include
+
+static inline unsigned long arch_local_irq_save(void)
+{
+ unsigned long flags;
+
+ flags = mfcr("psr");
+ asm volatile("psrclr ie\n":::"memory");
+ return flags;
+}
+#define arch_local_irq_save arch_local_irq_save
+
+static inline void arch_local_irq_enable(void)
+{
+ asm volatile("psrset ee, ie\n":::"memory");
+}
+#define arch_local_irq_enable arch_local_irq_enable
+
+static inline void arch_local_irq_disable(void)
+{
+ asm volatile("psrclr ie\n":::"memory");
+}
+#define arch_local_irq_disable arch_local_irq_disable
+
+static inline unsigned long arch_local_save_flags(void)
+{
+ return mfcr("psr");
+}
+#define arch_local_save_flags arch_local_save_flags
+
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+ mtcr("psr", flags);
+}
+#define arch_local_irq_restore arch_local_irq_restore
+
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+ return !(flags & (1<<6));
+}
+#define arch_irqs_disabled_flags arch_irqs_disabled_flags
+
+#include
+
+#endif /* __ASM_CSKY_IRQFLAGS_H */
diff --git a/arch/csky/kernel/irq.c b/arch/csky/kernel/irq.c
new file mode 100644
index 000..03a1930
--- /dev/null
+++ b/arch/csky/kernel/irq.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+void __init init_IRQ(void)
+{
+ irqchip_init();
+#ifdef CONFIG_SMP
+ setup_smp_ipi();
+#endif
+}
+
+asmlinkage void __irq_entry csky_do_IRQ(struct pt_regs *regs)
+{
+ handle_arch_irq(regs);
+}
--
2.7.4
[PATCH V8 06/21] csky: Cache and TLB routines
This patch adds cache and tlb sync codes for abiv1 & abiv2.
Changelog:
- fixup module compile error for EXPORT_SYMBOL(cache_wbinv_range).
- tlb.h & cacheflush.h:
fix flush_cache_range and tlb_start_vma of abiv1 in
flush_cache_range(vma, ...). cache_wbinv_range() couldn't deal with
vma->mm's asid for cache_flush_line and we use cache_wbinv_all() first.
Wwe'll improve with cache_flush(vma, start, end) in future.
For tlb_start_vma, we make it the same as other arch.
- remove the abi/tlb.h
Signed-off-by: Guo Ren
---
arch/csky/abiv1/cacheflush.c | 52
arch/csky/abiv1/inc/abi/cacheflush.h | 49
arch/csky/abiv2/cacheflush.c | 60 ++
arch/csky/abiv2/inc/abi/cacheflush.h | 46 +++
arch/csky/include/asm/barrier.h | 49
arch/csky/include/asm/cache.h | 30 +
arch/csky/include/asm/cacheflush.h| 9 ++
arch/csky/include/asm/io.h| 24
arch/csky/include/asm/tlb.h | 25
arch/csky/include/asm/tlbflush.h | 25
arch/csky/include/uapi/asm/cachectl.h | 13 ++
arch/csky/mm/cachev1.c| 126 +++
arch/csky/mm/cachev2.c| 79
arch/csky/mm/syscache.c | 32 +
arch/csky/mm/tlb.c| 219 ++
15 files changed, 838 insertions(+)
create mode 100644 arch/csky/abiv1/cacheflush.c
create mode 100644 arch/csky/abiv1/inc/abi/cacheflush.h
create mode 100644 arch/csky/abiv2/cacheflush.c
create mode 100644 arch/csky/abiv2/inc/abi/cacheflush.h
create mode 100644 arch/csky/include/asm/barrier.h
create mode 100644 arch/csky/include/asm/cache.h
create mode 100644 arch/csky/include/asm/cacheflush.h
create mode 100644 arch/csky/include/asm/io.h
create mode 100644 arch/csky/include/asm/tlb.h
create mode 100644 arch/csky/include/asm/tlbflush.h
create mode 100644 arch/csky/include/uapi/asm/cachectl.h
create mode 100644 arch/csky/mm/cachev1.c
create mode 100644 arch/csky/mm/cachev2.c
create mode 100644 arch/csky/mm/syscache.c
create mode 100644 arch/csky/mm/tlb.c
diff --git a/arch/csky/abiv1/cacheflush.c b/arch/csky/abiv1/cacheflush.c
new file mode 100644
index 000..10af8b6
--- /dev/null
+++ b/arch/csky/abiv1/cacheflush.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+void flush_dcache_page(struct page *page)
+{
+ struct address_space *mapping = page_mapping(page);
+ unsigned long addr;
+
+ if (mapping && !mapping_mapped(mapping)) {
+ set_bit(PG_arch_1, &(page)->flags);
+ return;
+ }
+
+ /*
+* We could delay the flush for the !page_mapping case too. But that
+* case is for exec env/arg pages and those are %99 certainly going to
+* get faulted into the tlb (and thus flushed) anyways.
+*/
+ addr = (unsigned long) page_address(page);
+ dcache_wb_range(addr, addr + PAGE_SIZE);
+}
+
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
+ pte_t *pte)
+{
+ unsigned long addr;
+ struct page *page;
+ unsigned long pfn;
+
+ pfn = pte_pfn(*pte);
+ if (unlikely(!pfn_valid(pfn)))
+ return;
+
+ page = pfn_to_page(pfn);
+ addr = (unsigned long) page_address(page);
+
+ if (vma->vm_flags & VM_EXEC ||
+ pages_do_alias(addr, address & PAGE_MASK))
+ cache_wbinv_all();
+
+ clear_bit(PG_arch_1, &(page)->flags);
+}
diff --git a/arch/csky/abiv1/inc/abi/cacheflush.h
b/arch/csky/abiv1/inc/abi/cacheflush.h
new file mode 100644
index 000..5f663ae
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/cacheflush.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ABI_CSKY_CACHEFLUSH_H
+#define __ABI_CSKY_CACHEFLUSH_H
+
+#include
+#include
+#include
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+extern void flush_dcache_page(struct page *);
+
+#define flush_cache_mm(mm) cache_wbinv_all()
+#define flush_cache_page(vma, page, pfn) cache_wbinv_all()
+#define flush_cache_dup_mm(mm) cache_wbinv_all()
+
+/*
+ * if (current_mm != vma->mm) cache_wbinv_range(start, end) will be broken.
+ * Use cache_wbinv_all() here and need to be improved in future.
+ */
+#define flush_cache_range(vma, start, end) cache_wbinv_all()
+#define flush_cache_vmap(start, end) cache_wbinv_range(start, end)
+#define flush_cache_vunmap(start, end) cache_wbinv_range(start, end)
+
+#define flush_icache_page(vma, page) cache_wbinv_all()
+#define flush_icache_range(start, end) cache_wbinv_range(start, end)
+
+#define flush_icache_user_range(vma, pg, adr, len) \
+
[PATCH V8 11/21] csky: Atomic operations
This patch adds atomic, cmpxchg, spinlock files.
Changlog:
- SMP supported
- ticklock supported
- queue-rwlock supported
Signed-off-by: Guo Ren
Cc: Peter Zijlstra
Cc: Andrea Parri
---
arch/csky/include/asm/atomic.h | 212 +
arch/csky/include/asm/cmpxchg.h| 73 +
arch/csky/include/asm/spinlock.h | 274 +
arch/csky/include/asm/spinlock_types.h | 37 +
arch/csky/kernel/atomic.S | 87 +++
5 files changed, 683 insertions(+)
create mode 100644 arch/csky/include/asm/atomic.h
create mode 100644 arch/csky/include/asm/cmpxchg.h
create mode 100644 arch/csky/include/asm/spinlock.h
create mode 100644 arch/csky/include/asm/spinlock_types.h
create mode 100644 arch/csky/kernel/atomic.S
diff --git a/arch/csky/include/asm/atomic.h b/arch/csky/include/asm/atomic.h
new file mode 100644
index 000..e369d73
--- /dev/null
+++ b/arch/csky/include/asm/atomic.h
@@ -0,0 +1,212 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASM_CSKY_ATOMIC_H
+#define __ASM_CSKY_ATOMIC_H
+
+#include
+#include
+#include
+
+#ifdef CONFIG_CPU_HAS_LDSTEX
+
+#define __atomic_add_unless __atomic_add_unless
+static inline int __atomic_add_unless(atomic_t *v, int a, int u)
+{
+ unsigned long tmp, ret;
+
+ smp_mb();
+
+ asm volatile (
+ "1: ldex.w %0, (%3) \n"
+ " mov %1, %0 \n"
+ " cmpne %0, %4 \n"
+ " bf 2f \n"
+ " add %0, %2 \n"
+ " stex.w %0, (%3) \n"
+ " bez %0, 1b \n"
+ "2: \n"
+ : "=" (tmp), "=" (ret)
+ : "r" (a), "r"(>counter), "r"(u)
+ : "memory");
+
+ if (ret != u)
+ smp_mb();
+
+ return ret;
+}
+
+#define ATOMIC_OP(op, c_op)\
+static inline void atomic_##op(int i, atomic_t *v) \
+{ \
+ unsigned long tmp; \
+ \
+ asm volatile ( \
+ "1: ldex.w %0, (%2) \n"\
+ " " #op " %0, %1 \n"\
+ " stex.w %0, (%2) \n"\
+ " bez %0, 1b \n"\
+ : "=" (tmp) \
+ : "r" (i), "r"(>counter) \
+ : "memory");\
+}
+
+#define ATOMIC_OP_RETURN(op, c_op) \
+static inline int atomic_##op##_return(int i, atomic_t *v) \
+{ \
+ unsigned long tmp, ret; \
+ \
+ smp_mb(); \
+ asm volatile ( \
+ "1: ldex.w %0, (%3) \n"\
+ " " #op " %0, %2 \n"\
+ " mov %1, %0 \n"\
+ " stex.w %0, (%3) \n"\
+ " bez %0, 1b \n"\
+ : "=" (tmp), "=" (ret) \
+ : "r" (i), "r"(>counter) \
+ : "memory");\
+ smp_mb(); \
+ \
+ return ret; \
+}
+
+#define ATOMIC_FETCH_OP(op, c_op) \
+static inline int atomic_fetch_##op(int i, atomic_t *v)
\
+{ \
+ unsigned long tmp, ret; \
+ \
+ smp_mb(); \
+ asm volatile ( \
+ "1: ldex.w %0, (%3) \n"\
+ " mov %1, %0 \n"\
+ " " #op " %0, %2 \n"\
+ " stex.w %0, (%3)
[PATCH V8 10/21] csky: IRQ handling
This patch adds IRQ handling files.
Changelog:
- Use CONFIG_GENERIC_IRQ_MULTI_HANDLER
Signed-off-by: Guo Ren
Cc: Thomas Gleixner
---
arch/csky/include/asm/irqflags.h | 49
arch/csky/kernel/irq.c | 22 ++
2 files changed, 71 insertions(+)
create mode 100644 arch/csky/include/asm/irqflags.h
create mode 100644 arch/csky/kernel/irq.c
diff --git a/arch/csky/include/asm/irqflags.h b/arch/csky/include/asm/irqflags.h
new file mode 100644
index 000..9e3a569
--- /dev/null
+++ b/arch/csky/include/asm/irqflags.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASM_CSKY_IRQFLAGS_H
+#define __ASM_CSKY_IRQFLAGS_H
+#include
+
+static inline unsigned long arch_local_irq_save(void)
+{
+ unsigned long flags;
+
+ flags = mfcr("psr");
+ asm volatile("psrclr ie\n":::"memory");
+ return flags;
+}
+#define arch_local_irq_save arch_local_irq_save
+
+static inline void arch_local_irq_enable(void)
+{
+ asm volatile("psrset ee, ie\n":::"memory");
+}
+#define arch_local_irq_enable arch_local_irq_enable
+
+static inline void arch_local_irq_disable(void)
+{
+ asm volatile("psrclr ie\n":::"memory");
+}
+#define arch_local_irq_disable arch_local_irq_disable
+
+static inline unsigned long arch_local_save_flags(void)
+{
+ return mfcr("psr");
+}
+#define arch_local_save_flags arch_local_save_flags
+
+static inline void arch_local_irq_restore(unsigned long flags)
+{
+ mtcr("psr", flags);
+}
+#define arch_local_irq_restore arch_local_irq_restore
+
+static inline int arch_irqs_disabled_flags(unsigned long flags)
+{
+ return !(flags & (1<<6));
+}
+#define arch_irqs_disabled_flags arch_irqs_disabled_flags
+
+#include
+
+#endif /* __ASM_CSKY_IRQFLAGS_H */
diff --git a/arch/csky/kernel/irq.c b/arch/csky/kernel/irq.c
new file mode 100644
index 000..03a1930
--- /dev/null
+++ b/arch/csky/kernel/irq.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+void __init init_IRQ(void)
+{
+ irqchip_init();
+#ifdef CONFIG_SMP
+ setup_smp_ipi();
+#endif
+}
+
+asmlinkage void __irq_entry csky_do_IRQ(struct pt_regs *regs)
+{
+ handle_arch_irq(regs);
+}
--
2.7.4
[PATCH V8 09/21] csky: VDSO and rt_sigreturn
This patch adds files related to VDSO and our VDSO only support
rt_sigreturn.
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/vdso.h | 17 +
arch/csky/abiv2/inc/abi/vdso.h | 23 +++
arch/csky/include/asm/vdso.h | 12 ++
arch/csky/kernel/vdso.c| 86 ++
4 files changed, 138 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/vdso.h
create mode 100644 arch/csky/abiv2/inc/abi/vdso.h
create mode 100644 arch/csky/include/asm/vdso.h
create mode 100644 arch/csky/kernel/vdso.c
diff --git a/arch/csky/abiv1/inc/abi/vdso.h b/arch/csky/abiv1/inc/abi/vdso.h
new file mode 100644
index 000..14352f5
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/vdso.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#include
+
+static inline int setup_vdso_page(unsigned short *ptr)
+{
+ int err = 0;
+
+ /* movi r1, 127 */
+ err |= __put_user(0x67f1, ptr + 0);
+ /* addi r1, (139 - 127) */
+ err |= __put_user(0x20b1, ptr + 1);
+ /* trap 0 */
+ err |= __put_user(0x0008, ptr + 2);
+
+ return err;
+}
diff --git a/arch/csky/abiv2/inc/abi/vdso.h b/arch/csky/abiv2/inc/abi/vdso.h
new file mode 100644
index 000..b60d4a0
--- /dev/null
+++ b/arch/csky/abiv2/inc/abi/vdso.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ABI_CSKY_VDSO_H
+#define __ABI_CSKY_VDSO_H
+
+#include
+
+static inline int setup_vdso_page(unsigned short *ptr)
+{
+ int err = 0;
+
+ /* movi r7, 173 */
+ err |= __put_user(0xea07, ptr);
+ err |= __put_user(0x008b, ptr+1);
+
+ /* trap 0 */
+ err |= __put_user(0xc000, ptr+2);
+ err |= __put_user(0x2020, ptr+3);
+
+ return err;
+}
+
+#endif /* __ABI_CSKY_STRING_H */
diff --git a/arch/csky/include/asm/vdso.h b/arch/csky/include/asm/vdso.h
new file mode 100644
index 000..d963d69
--- /dev/null
+++ b/arch/csky/include/asm/vdso.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASM_CSKY_VDSO_H
+#define __ASM_CSKY_VDSO_H
+
+#include
+
+struct csky_vdso {
+ unsigned short rt_signal_retcode[4];
+};
+
+#endif /* __ASM_CSKY_VDSO_H */
diff --git a/arch/csky/kernel/vdso.c b/arch/csky/kernel/vdso.c
new file mode 100644
index 000..60ff7ad
--- /dev/null
+++ b/arch/csky/kernel/vdso.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+static struct page *vdso_page;
+
+static int __init init_vdso(void)
+{
+ struct csky_vdso *vdso;
+ int err = 0;
+
+ vdso_page = alloc_page(GFP_KERNEL);
+ if (!vdso_page)
+ panic("Cannot allocate vdso");
+
+ vdso = vmap(_page, 1, 0, PAGE_KERNEL);
+ if (!vdso)
+ panic("Cannot map vdso");
+
+ clear_page(vdso);
+
+ err = setup_vdso_page(vdso->rt_signal_retcode);
+ if (err)
+ panic("Cannot set signal return code, err: %x.", err);
+
+ dcache_wb_range((unsigned long)vdso, (unsigned long)vdso + 16);
+
+ vunmap(vdso);
+
+ return 0;
+}
+subsys_initcall(init_vdso);
+
+int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
+{
+ int ret;
+ unsigned long addr;
+ struct mm_struct *mm = current->mm;
+
+ down_write(>mmap_sem);
+
+ addr = get_unmapped_area(NULL, STACK_TOP, PAGE_SIZE, 0, 0);
+ if (IS_ERR_VALUE(addr)) {
+ ret = addr;
+ goto up_fail;
+ }
+
+ ret = install_special_mapping(
+ mm,
+ addr,
+ PAGE_SIZE,
+ VM_READ|VM_EXEC|VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
+ _page);
+ if (ret)
+ goto up_fail;
+
+ mm->context.vdso = (void *)addr;
+
+up_fail:
+ up_write(>mmap_sem);
+ return ret;
+}
+
+const char *arch_vma_name(struct vm_area_struct *vma)
+{
+ if (vma->vm_mm == NULL)
+ return NULL;
+
+ if (vma->vm_start == (long)vma->vm_mm->context.vdso)
+ return "[vdso]";
+ else
+ return NULL;
+}
--
2.7.4
[PATCH V8 07/21] csky: MMU and page table management
This patch adds files related to memory management and here is our
memory-layout:
Fixmap : 0xffc02000 – 0xf000 (4 MB - 12KB)
Pkmap: 0xff80 – 0xffc0 (4 MB)
Vmalloc : 0xf020 – 0xff00 (238 MB)
Lowmem : 0x8000 – 0xc000 (1GB)
abiv1 CPU (CK610) is VIPT cache and it doesn't support highmem.
abiv2 CPUs are all PIPT cache and they could support highmem.
Lowmem is directly mapped by msa0 & msa1 reg, and we needn't setup
memory page table for it.
Changelog:
- fixup pfn_valid(pfn) compile error for modules.
- fixup compile warning for CONFIG_DEBUG_HIGHMEM.
- fixup module compile error for EXPORT_SYMBOL(empty_zero_page).
- dma-mapping: fix up dma_mapping error
The arch_sync_dma_for_cpu()/arch_sync_dma_for_device() implementation is
broken for some combinations that end up in a BUG() instead of performing
the necessary flushes.
- Fixup arch_sync_dma() broken when size is larger than PAGE_SIZE.
Ignore the DMA_ATTR_NON_CONSISTENT, remove the BUG() and use return NULL
instead.
The implementation of arch should follow the following rules:
map for_cpu for_device unmap
TO_DEV writeback nonewriteback none
TO_CPU invalidate invalidate* invalidate invalidate*
BIDIR writeback invalidate writeback invalidate
Link:https://lore.kernel.org/lkml/20180518215548.gh17...@n2100.armlinux.org.uk/
Signed-off-by: Guo Ren
Cc: Christoph Hellwig
---
arch/csky/abiv1/inc/abi/ckmmu.h| 75
arch/csky/abiv1/inc/abi/page.h | 27 +++
arch/csky/abiv1/inc/abi/pgtable-bits.h | 37
arch/csky/abiv1/mmap.c | 66 +++
arch/csky/abiv2/inc/abi/ckmmu.h| 87 ++
arch/csky/abiv2/inc/abi/page.h | 14 ++
arch/csky/abiv2/inc/abi/pgtable-bits.h | 37
arch/csky/include/asm/addrspace.h | 10 ++
arch/csky/include/asm/fixmap.h | 27 +++
arch/csky/include/asm/highmem.h| 51 ++
arch/csky/include/asm/mmu.h| 12 ++
arch/csky/include/asm/page.h | 104 +++
arch/csky/include/asm/pgalloc.h| 115 +
arch/csky/include/asm/pgtable.h| 306 +
arch/csky/include/asm/segment.h| 19 ++
arch/csky/include/asm/shmparam.h | 11 ++
arch/csky/mm/dma-mapping.c | 254 +++
arch/csky/mm/highmem.c | 198 +
arch/csky/mm/init.c| 122 +
arch/csky/mm/ioremap.c | 48 ++
20 files changed, 1620 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/ckmmu.h
create mode 100644 arch/csky/abiv1/inc/abi/page.h
create mode 100644 arch/csky/abiv1/inc/abi/pgtable-bits.h
create mode 100644 arch/csky/abiv1/mmap.c
create mode 100644 arch/csky/abiv2/inc/abi/ckmmu.h
create mode 100644 arch/csky/abiv2/inc/abi/page.h
create mode 100644 arch/csky/abiv2/inc/abi/pgtable-bits.h
create mode 100644 arch/csky/include/asm/addrspace.h
create mode 100644 arch/csky/include/asm/fixmap.h
create mode 100644 arch/csky/include/asm/highmem.h
create mode 100644 arch/csky/include/asm/mmu.h
create mode 100644 arch/csky/include/asm/page.h
create mode 100644 arch/csky/include/asm/pgalloc.h
create mode 100644 arch/csky/include/asm/pgtable.h
create mode 100644 arch/csky/include/asm/segment.h
create mode 100644 arch/csky/include/asm/shmparam.h
create mode 100644 arch/csky/mm/dma-mapping.c
create mode 100644 arch/csky/mm/highmem.c
create mode 100644 arch/csky/mm/init.c
create mode 100644 arch/csky/mm/ioremap.c
diff --git a/arch/csky/abiv1/inc/abi/ckmmu.h b/arch/csky/abiv1/inc/abi/ckmmu.h
new file mode 100644
index 000..3a00201
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/ckmmu.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_CKMMUV1_H
+#define __ASM_CSKY_CKMMUV1_H
+#include
+
+static inline int read_mmu_index(void)
+{
+ return cprcr("cpcr0");
+}
+
+static inline void write_mmu_index(int value)
+{
+ cpwcr("cpcr0", value);
+}
+
+static inline int read_mmu_entrylo0(void)
+{
+ return cprcr("cpcr2") << 6;
+}
+
+static inline int read_mmu_entrylo1(void)
+{
+ return cprcr("cpcr3") << 6;
+}
+
+static inline void write_mmu_pagemask(int value)
+{
+ cpwcr("cpcr6", value);
+}
+
+static inline int read_mmu_entryhi(void)
+{
+ return cprcr("cpcr4");
+}
+
+static inline void write_mmu_entryhi(int value)
+{
+ cpwcr("cpcr4", value);
+}
+
+/*
+ * TLB operations.
+ */
+static inline void tlb_probe(void)
+{
+ cpwcr("cpcr8", 0x8000);
+}
+
+static inline void tlb_read(void)
+{
+ cpwcr("cpcr8", 0x4000);
+}
+
+static inline void tlb_invalid_all(void)
+{
+ cpwcr("cpcr8", 0x0400);
+}
+
+static inline void
[PATCH V8 13/21] csky: Library functions
This patch adds string optimize codes and some auxiliary code.
Changelog:
- Use bt instead of jbt in asm, jbt will cause relocation problem.
- remove kernel/platform.c
Signed-off-by: Chen Linfei
Signed-off-by: Mao Han
Signed-off-by: Guo Ren
---
arch/csky/abiv1/bswapdi.c| 12 ++
arch/csky/abiv1/bswapsi.c| 12 ++
arch/csky/abiv1/inc/abi/string.h | 13 ++
arch/csky/abiv1/memcpy.S | 347 +++
arch/csky/abiv1/memset.c | 37 +
arch/csky/abiv1/strksyms.c | 7 +
arch/csky/abiv2/inc/abi/string.h | 27 +++
arch/csky/abiv2/memcmp.S | 152 +
arch/csky/abiv2/memcpy.S | 110 +
arch/csky/abiv2/memmove.S| 108
arch/csky/abiv2/memset.S | 83 ++
arch/csky/abiv2/strcmp.S | 168 +++
arch/csky/abiv2/strcpy.S | 123 ++
arch/csky/abiv2/strksyms.c | 12 ++
arch/csky/abiv2/strlen.S | 97 +++
arch/csky/abiv2/sysdep.h | 30
arch/csky/include/asm/string.h | 13 ++
arch/csky/kernel/power.c | 30
arch/csky/lib/delay.c| 39 +
19 files changed, 1420 insertions(+)
create mode 100644 arch/csky/abiv1/bswapdi.c
create mode 100644 arch/csky/abiv1/bswapsi.c
create mode 100644 arch/csky/abiv1/inc/abi/string.h
create mode 100644 arch/csky/abiv1/memcpy.S
create mode 100644 arch/csky/abiv1/memset.c
create mode 100644 arch/csky/abiv1/strksyms.c
create mode 100644 arch/csky/abiv2/inc/abi/string.h
create mode 100644 arch/csky/abiv2/memcmp.S
create mode 100644 arch/csky/abiv2/memcpy.S
create mode 100644 arch/csky/abiv2/memmove.S
create mode 100644 arch/csky/abiv2/memset.S
create mode 100644 arch/csky/abiv2/strcmp.S
create mode 100644 arch/csky/abiv2/strcpy.S
create mode 100644 arch/csky/abiv2/strksyms.c
create mode 100644 arch/csky/abiv2/strlen.S
create mode 100644 arch/csky/abiv2/sysdep.h
create mode 100644 arch/csky/include/asm/string.h
create mode 100644 arch/csky/kernel/power.c
create mode 100644 arch/csky/lib/delay.c
diff --git a/arch/csky/abiv1/bswapdi.c b/arch/csky/abiv1/bswapdi.c
new file mode 100644
index 000..f50a1d6
--- /dev/null
+++ b/arch/csky/abiv1/bswapdi.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+
+unsigned long long notrace __bswapdi2(unsigned long long u)
+{
+ return ___constant_swab64(u);
+}
+EXPORT_SYMBOL(__bswapdi2);
diff --git a/arch/csky/abiv1/bswapsi.c b/arch/csky/abiv1/bswapsi.c
new file mode 100644
index 000..0f79182
--- /dev/null
+++ b/arch/csky/abiv1/bswapsi.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+
+unsigned int notrace __bswapsi2(unsigned int u)
+{
+ return ___constant_swab32(u);
+}
+EXPORT_SYMBOL(__bswapsi2);
diff --git a/arch/csky/abiv1/inc/abi/string.h b/arch/csky/abiv1/inc/abi/string.h
new file mode 100644
index 000..5abe80b
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/string.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ABI_CSKY_STRING_H
+#define __ABI_CSKY_STRING_H
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#endif /* __ABI_CSKY_STRING_H */
diff --git a/arch/csky/abiv1/memcpy.S b/arch/csky/abiv1/memcpy.S
new file mode 100644
index 000..5078eb5
--- /dev/null
+++ b/arch/csky/abiv1/memcpy.S
@@ -0,0 +1,347 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+
+.macro GET_FRONT_BITS rx y
+#ifdef __cskyLE__
+ lsri\rx, \y
+#else
+ lsli\rx, \y
+#endif
+.endm
+
+.macro GET_AFTER_BITS rx y
+#ifdef __cskyLE__
+ lsli\rx, \y
+#else
+ lsri\rx, \y
+#endif
+.endm
+
+/* void *memcpy(void *dest, const void *src, size_t n); */
+ENTRY(memcpy)
+ mov r7, r2
+ cmplti r4, 4
+ bt .L_copy_by_byte
+ mov r6, r2
+ andir6, 3
+ cmpnei r6, 0
+ jbt .L_dest_not_aligned
+ mov r6, r3
+ andir6, 3
+ cmpnei r6, 0
+ jbt .L_dest_aligned_but_src_not_aligned
+.L0:
+ cmplti r4, 16
+ jbt .L_aligned_and_len_less_16bytes
+ subisp, 8
+ stw r8, (sp, 0)
+.L_aligned_and_len_larger_16bytes:
+ ldw r1, (r3, 0)
+ ldw r5, (r3, 4)
+ ldw r8, (r3, 8)
+ stw r1, (r7, 0)
+ ldw r1, (r3, 12)
+ stw r5, (r7, 4)
+ stw r8, (r7, 8)
+ stw r1, (r7, 12)
+ subir4, 16
+ addir3, 16
+ addir7, 16
+ cmplti r4, 16
+ jbf .L_aligned_and_len_larger_16bytes
+ ldw
[PATCH V8 09/21] csky: VDSO and rt_sigreturn
This patch adds files related to VDSO and our VDSO only support
rt_sigreturn.
Signed-off-by: Guo Ren
---
arch/csky/abiv1/inc/abi/vdso.h | 17 +
arch/csky/abiv2/inc/abi/vdso.h | 23 +++
arch/csky/include/asm/vdso.h | 12 ++
arch/csky/kernel/vdso.c| 86 ++
4 files changed, 138 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/vdso.h
create mode 100644 arch/csky/abiv2/inc/abi/vdso.h
create mode 100644 arch/csky/include/asm/vdso.h
create mode 100644 arch/csky/kernel/vdso.c
diff --git a/arch/csky/abiv1/inc/abi/vdso.h b/arch/csky/abiv1/inc/abi/vdso.h
new file mode 100644
index 000..14352f5
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/vdso.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#include
+
+static inline int setup_vdso_page(unsigned short *ptr)
+{
+ int err = 0;
+
+ /* movi r1, 127 */
+ err |= __put_user(0x67f1, ptr + 0);
+ /* addi r1, (139 - 127) */
+ err |= __put_user(0x20b1, ptr + 1);
+ /* trap 0 */
+ err |= __put_user(0x0008, ptr + 2);
+
+ return err;
+}
diff --git a/arch/csky/abiv2/inc/abi/vdso.h b/arch/csky/abiv2/inc/abi/vdso.h
new file mode 100644
index 000..b60d4a0
--- /dev/null
+++ b/arch/csky/abiv2/inc/abi/vdso.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ABI_CSKY_VDSO_H
+#define __ABI_CSKY_VDSO_H
+
+#include
+
+static inline int setup_vdso_page(unsigned short *ptr)
+{
+ int err = 0;
+
+ /* movi r7, 173 */
+ err |= __put_user(0xea07, ptr);
+ err |= __put_user(0x008b, ptr+1);
+
+ /* trap 0 */
+ err |= __put_user(0xc000, ptr+2);
+ err |= __put_user(0x2020, ptr+3);
+
+ return err;
+}
+
+#endif /* __ABI_CSKY_STRING_H */
diff --git a/arch/csky/include/asm/vdso.h b/arch/csky/include/asm/vdso.h
new file mode 100644
index 000..d963d69
--- /dev/null
+++ b/arch/csky/include/asm/vdso.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASM_CSKY_VDSO_H
+#define __ASM_CSKY_VDSO_H
+
+#include
+
+struct csky_vdso {
+ unsigned short rt_signal_retcode[4];
+};
+
+#endif /* __ASM_CSKY_VDSO_H */
diff --git a/arch/csky/kernel/vdso.c b/arch/csky/kernel/vdso.c
new file mode 100644
index 000..60ff7ad
--- /dev/null
+++ b/arch/csky/kernel/vdso.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+static struct page *vdso_page;
+
+static int __init init_vdso(void)
+{
+ struct csky_vdso *vdso;
+ int err = 0;
+
+ vdso_page = alloc_page(GFP_KERNEL);
+ if (!vdso_page)
+ panic("Cannot allocate vdso");
+
+ vdso = vmap(_page, 1, 0, PAGE_KERNEL);
+ if (!vdso)
+ panic("Cannot map vdso");
+
+ clear_page(vdso);
+
+ err = setup_vdso_page(vdso->rt_signal_retcode);
+ if (err)
+ panic("Cannot set signal return code, err: %x.", err);
+
+ dcache_wb_range((unsigned long)vdso, (unsigned long)vdso + 16);
+
+ vunmap(vdso);
+
+ return 0;
+}
+subsys_initcall(init_vdso);
+
+int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp)
+{
+ int ret;
+ unsigned long addr;
+ struct mm_struct *mm = current->mm;
+
+ down_write(>mmap_sem);
+
+ addr = get_unmapped_area(NULL, STACK_TOP, PAGE_SIZE, 0, 0);
+ if (IS_ERR_VALUE(addr)) {
+ ret = addr;
+ goto up_fail;
+ }
+
+ ret = install_special_mapping(
+ mm,
+ addr,
+ PAGE_SIZE,
+ VM_READ|VM_EXEC|VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC,
+ _page);
+ if (ret)
+ goto up_fail;
+
+ mm->context.vdso = (void *)addr;
+
+up_fail:
+ up_write(>mmap_sem);
+ return ret;
+}
+
+const char *arch_vma_name(struct vm_area_struct *vma)
+{
+ if (vma->vm_mm == NULL)
+ return NULL;
+
+ if (vma->vm_start == (long)vma->vm_mm->context.vdso)
+ return "[vdso]";
+ else
+ return NULL;
+}
--
2.7.4
[PATCH V8 07/21] csky: MMU and page table management
This patch adds files related to memory management and here is our
memory-layout:
Fixmap : 0xffc02000 – 0xf000 (4 MB - 12KB)
Pkmap: 0xff80 – 0xffc0 (4 MB)
Vmalloc : 0xf020 – 0xff00 (238 MB)
Lowmem : 0x8000 – 0xc000 (1GB)
abiv1 CPU (CK610) is VIPT cache and it doesn't support highmem.
abiv2 CPUs are all PIPT cache and they could support highmem.
Lowmem is directly mapped by msa0 & msa1 reg, and we needn't setup
memory page table for it.
Changelog:
- fixup pfn_valid(pfn) compile error for modules.
- fixup compile warning for CONFIG_DEBUG_HIGHMEM.
- fixup module compile error for EXPORT_SYMBOL(empty_zero_page).
- dma-mapping: fix up dma_mapping error
The arch_sync_dma_for_cpu()/arch_sync_dma_for_device() implementation is
broken for some combinations that end up in a BUG() instead of performing
the necessary flushes.
- Fixup arch_sync_dma() broken when size is larger than PAGE_SIZE.
Ignore the DMA_ATTR_NON_CONSISTENT, remove the BUG() and use return NULL
instead.
The implementation of arch should follow the following rules:
map for_cpu for_device unmap
TO_DEV writeback nonewriteback none
TO_CPU invalidate invalidate* invalidate invalidate*
BIDIR writeback invalidate writeback invalidate
Link:https://lore.kernel.org/lkml/20180518215548.gh17...@n2100.armlinux.org.uk/
Signed-off-by: Guo Ren
Cc: Christoph Hellwig
---
arch/csky/abiv1/inc/abi/ckmmu.h| 75
arch/csky/abiv1/inc/abi/page.h | 27 +++
arch/csky/abiv1/inc/abi/pgtable-bits.h | 37
arch/csky/abiv1/mmap.c | 66 +++
arch/csky/abiv2/inc/abi/ckmmu.h| 87 ++
arch/csky/abiv2/inc/abi/page.h | 14 ++
arch/csky/abiv2/inc/abi/pgtable-bits.h | 37
arch/csky/include/asm/addrspace.h | 10 ++
arch/csky/include/asm/fixmap.h | 27 +++
arch/csky/include/asm/highmem.h| 51 ++
arch/csky/include/asm/mmu.h| 12 ++
arch/csky/include/asm/page.h | 104 +++
arch/csky/include/asm/pgalloc.h| 115 +
arch/csky/include/asm/pgtable.h| 306 +
arch/csky/include/asm/segment.h| 19 ++
arch/csky/include/asm/shmparam.h | 11 ++
arch/csky/mm/dma-mapping.c | 254 +++
arch/csky/mm/highmem.c | 198 +
arch/csky/mm/init.c| 122 +
arch/csky/mm/ioremap.c | 48 ++
20 files changed, 1620 insertions(+)
create mode 100644 arch/csky/abiv1/inc/abi/ckmmu.h
create mode 100644 arch/csky/abiv1/inc/abi/page.h
create mode 100644 arch/csky/abiv1/inc/abi/pgtable-bits.h
create mode 100644 arch/csky/abiv1/mmap.c
create mode 100644 arch/csky/abiv2/inc/abi/ckmmu.h
create mode 100644 arch/csky/abiv2/inc/abi/page.h
create mode 100644 arch/csky/abiv2/inc/abi/pgtable-bits.h
create mode 100644 arch/csky/include/asm/addrspace.h
create mode 100644 arch/csky/include/asm/fixmap.h
create mode 100644 arch/csky/include/asm/highmem.h
create mode 100644 arch/csky/include/asm/mmu.h
create mode 100644 arch/csky/include/asm/page.h
create mode 100644 arch/csky/include/asm/pgalloc.h
create mode 100644 arch/csky/include/asm/pgtable.h
create mode 100644 arch/csky/include/asm/segment.h
create mode 100644 arch/csky/include/asm/shmparam.h
create mode 100644 arch/csky/mm/dma-mapping.c
create mode 100644 arch/csky/mm/highmem.c
create mode 100644 arch/csky/mm/init.c
create mode 100644 arch/csky/mm/ioremap.c
diff --git a/arch/csky/abiv1/inc/abi/ckmmu.h b/arch/csky/abiv1/inc/abi/ckmmu.h
new file mode 100644
index 000..3a00201
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/ckmmu.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_CKMMUV1_H
+#define __ASM_CSKY_CKMMUV1_H
+#include
+
+static inline int read_mmu_index(void)
+{
+ return cprcr("cpcr0");
+}
+
+static inline void write_mmu_index(int value)
+{
+ cpwcr("cpcr0", value);
+}
+
+static inline int read_mmu_entrylo0(void)
+{
+ return cprcr("cpcr2") << 6;
+}
+
+static inline int read_mmu_entrylo1(void)
+{
+ return cprcr("cpcr3") << 6;
+}
+
+static inline void write_mmu_pagemask(int value)
+{
+ cpwcr("cpcr6", value);
+}
+
+static inline int read_mmu_entryhi(void)
+{
+ return cprcr("cpcr4");
+}
+
+static inline void write_mmu_entryhi(int value)
+{
+ cpwcr("cpcr4", value);
+}
+
+/*
+ * TLB operations.
+ */
+static inline void tlb_probe(void)
+{
+ cpwcr("cpcr8", 0x8000);
+}
+
+static inline void tlb_read(void)
+{
+ cpwcr("cpcr8", 0x4000);
+}
+
+static inline void tlb_invalid_all(void)
+{
+ cpwcr("cpcr8", 0x0400);
+}
+
+static inline void
[PATCH V8 13/21] csky: Library functions
This patch adds string optimize codes and some auxiliary code.
Changelog:
- Use bt instead of jbt in asm, jbt will cause relocation problem.
- remove kernel/platform.c
Signed-off-by: Chen Linfei
Signed-off-by: Mao Han
Signed-off-by: Guo Ren
---
arch/csky/abiv1/bswapdi.c| 12 ++
arch/csky/abiv1/bswapsi.c| 12 ++
arch/csky/abiv1/inc/abi/string.h | 13 ++
arch/csky/abiv1/memcpy.S | 347 +++
arch/csky/abiv1/memset.c | 37 +
arch/csky/abiv1/strksyms.c | 7 +
arch/csky/abiv2/inc/abi/string.h | 27 +++
arch/csky/abiv2/memcmp.S | 152 +
arch/csky/abiv2/memcpy.S | 110 +
arch/csky/abiv2/memmove.S| 108
arch/csky/abiv2/memset.S | 83 ++
arch/csky/abiv2/strcmp.S | 168 +++
arch/csky/abiv2/strcpy.S | 123 ++
arch/csky/abiv2/strksyms.c | 12 ++
arch/csky/abiv2/strlen.S | 97 +++
arch/csky/abiv2/sysdep.h | 30
arch/csky/include/asm/string.h | 13 ++
arch/csky/kernel/power.c | 30
arch/csky/lib/delay.c| 39 +
19 files changed, 1420 insertions(+)
create mode 100644 arch/csky/abiv1/bswapdi.c
create mode 100644 arch/csky/abiv1/bswapsi.c
create mode 100644 arch/csky/abiv1/inc/abi/string.h
create mode 100644 arch/csky/abiv1/memcpy.S
create mode 100644 arch/csky/abiv1/memset.c
create mode 100644 arch/csky/abiv1/strksyms.c
create mode 100644 arch/csky/abiv2/inc/abi/string.h
create mode 100644 arch/csky/abiv2/memcmp.S
create mode 100644 arch/csky/abiv2/memcpy.S
create mode 100644 arch/csky/abiv2/memmove.S
create mode 100644 arch/csky/abiv2/memset.S
create mode 100644 arch/csky/abiv2/strcmp.S
create mode 100644 arch/csky/abiv2/strcpy.S
create mode 100644 arch/csky/abiv2/strksyms.c
create mode 100644 arch/csky/abiv2/strlen.S
create mode 100644 arch/csky/abiv2/sysdep.h
create mode 100644 arch/csky/include/asm/string.h
create mode 100644 arch/csky/kernel/power.c
create mode 100644 arch/csky/lib/delay.c
diff --git a/arch/csky/abiv1/bswapdi.c b/arch/csky/abiv1/bswapdi.c
new file mode 100644
index 000..f50a1d6
--- /dev/null
+++ b/arch/csky/abiv1/bswapdi.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+
+unsigned long long notrace __bswapdi2(unsigned long long u)
+{
+ return ___constant_swab64(u);
+}
+EXPORT_SYMBOL(__bswapdi2);
diff --git a/arch/csky/abiv1/bswapsi.c b/arch/csky/abiv1/bswapsi.c
new file mode 100644
index 000..0f79182
--- /dev/null
+++ b/arch/csky/abiv1/bswapsi.c
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+
+unsigned int notrace __bswapsi2(unsigned int u)
+{
+ return ___constant_swab32(u);
+}
+EXPORT_SYMBOL(__bswapsi2);
diff --git a/arch/csky/abiv1/inc/abi/string.h b/arch/csky/abiv1/inc/abi/string.h
new file mode 100644
index 000..5abe80b
--- /dev/null
+++ b/arch/csky/abiv1/inc/abi/string.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ABI_CSKY_STRING_H
+#define __ABI_CSKY_STRING_H
+
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *, int, __kernel_size_t);
+
+#endif /* __ABI_CSKY_STRING_H */
diff --git a/arch/csky/abiv1/memcpy.S b/arch/csky/abiv1/memcpy.S
new file mode 100644
index 000..5078eb5
--- /dev/null
+++ b/arch/csky/abiv1/memcpy.S
@@ -0,0 +1,347 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+
+.macro GET_FRONT_BITS rx y
+#ifdef __cskyLE__
+ lsri\rx, \y
+#else
+ lsli\rx, \y
+#endif
+.endm
+
+.macro GET_AFTER_BITS rx y
+#ifdef __cskyLE__
+ lsli\rx, \y
+#else
+ lsri\rx, \y
+#endif
+.endm
+
+/* void *memcpy(void *dest, const void *src, size_t n); */
+ENTRY(memcpy)
+ mov r7, r2
+ cmplti r4, 4
+ bt .L_copy_by_byte
+ mov r6, r2
+ andir6, 3
+ cmpnei r6, 0
+ jbt .L_dest_not_aligned
+ mov r6, r3
+ andir6, 3
+ cmpnei r6, 0
+ jbt .L_dest_aligned_but_src_not_aligned
+.L0:
+ cmplti r4, 16
+ jbt .L_aligned_and_len_less_16bytes
+ subisp, 8
+ stw r8, (sp, 0)
+.L_aligned_and_len_larger_16bytes:
+ ldw r1, (r3, 0)
+ ldw r5, (r3, 4)
+ ldw r8, (r3, 8)
+ stw r1, (r7, 0)
+ ldw r1, (r3, 12)
+ stw r5, (r7, 4)
+ stw r8, (r7, 8)
+ stw r1, (r7, 12)
+ subir4, 16
+ addir3, 16
+ addir7, 16
+ cmplti r4, 16
+ jbf .L_aligned_and_len_larger_16bytes
+ ldw
[PATCH V8 04/21] csky: Exception handling and mm-fault
This patch adds exception handling code, cpuinfo and mm-fault code.
Signed-off-by: Guo Ren
---
arch/csky/abiv1/alignment.c | 323
arch/csky/abiv1/inc/abi/entry.h | 160
arch/csky/abiv2/inc/abi/entry.h | 156
arch/csky/include/asm/traps.h | 44 +
arch/csky/include/asm/unistd.h | 4 +
arch/csky/kernel/cpu-probe.c| 79
arch/csky/kernel/entry.S| 396
arch/csky/kernel/traps.c| 172 +
arch/csky/mm/fault.c| 220 ++
9 files changed, 1554 insertions(+)
create mode 100644 arch/csky/abiv1/alignment.c
create mode 100644 arch/csky/abiv1/inc/abi/entry.h
create mode 100644 arch/csky/abiv2/inc/abi/entry.h
create mode 100644 arch/csky/include/asm/traps.h
create mode 100644 arch/csky/include/asm/unistd.h
create mode 100644 arch/csky/kernel/cpu-probe.c
create mode 100644 arch/csky/kernel/entry.S
create mode 100644 arch/csky/kernel/traps.c
create mode 100644 arch/csky/mm/fault.c
diff --git a/arch/csky/abiv1/alignment.c b/arch/csky/abiv1/alignment.c
new file mode 100644
index 000..8ec7400
--- /dev/null
+++ b/arch/csky/abiv1/alignment.c
@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+
+static int align_enable = 1;
+static int align_count;
+
+static inline uint32_t get_ptreg(struct pt_regs *regs, uint32_t rx)
+{
+ return *((int *)&(regs->a0) - 2 + rx);
+}
+
+static inline void put_ptreg(struct pt_regs *regs, uint32_t rx, uint32_t val)
+{
+ *((int *)&(regs->a0) - 2 + rx) = val;
+}
+
+/*
+ * Get byte-value from addr and set it to *valp.
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int ldb_asm(uint32_t addr, uint32_t *valp)
+{
+ uint32_t val;
+ int err;
+
+ if (!access_ok(VERIFY_READ, (void *)addr, 1))
+ return 1;
+
+ asm volatile (
+ "movi %0, 0\n"
+ "1:\n"
+ "ldb%1, (%2)\n"
+ "br 3f\n"
+ "2:\n"
+ "movi %0, 1\n"
+ "br 3f\n"
+ ".section __ex_table,\"a\"\n"
+ ".align 2\n"
+ ".long 1b, 2b\n"
+ ".previous\n"
+ "3:\n"
+ : "="(err), "=r"(val)
+ : "r" (addr)
+ );
+
+ *valp = val;
+
+ return err;
+}
+
+/*
+ * Put byte-value to addr.
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int stb_asm(uint32_t addr, uint32_t val)
+{
+ int err;
+
+ if (!access_ok(VERIFY_WRITE, (void *)addr, 1))
+ return 1;
+
+ asm volatile (
+ "movi %0, 0\n"
+ "1:\n"
+ "stb%1, (%2)\n"
+ "br 3f\n"
+ "2:\n"
+ "movi %0, 1\n"
+ "br 3f\n"
+ ".section __ex_table,\"a\"\n"
+ ".align 2\n"
+ ".long 1b, 2b\n"
+ ".previous\n"
+ "3:\n"
+ : "="(err)
+ : "r"(val), "r" (addr)
+ );
+
+ return err;
+}
+
+/*
+ * Get half-word from [rx + imm]
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int ldh_c(struct pt_regs *regs, uint32_t rz, uint32_t addr)
+{
+ uint32_t byte0, byte1;
+
+ if (ldb_asm(addr, ))
+ return 1;
+ addr += 1;
+ if (ldb_asm(addr, ))
+ return 1;
+
+ byte0 |= byte1 << 8;
+ put_ptreg(regs, rz, byte0);
+
+ return 0;
+}
+
+/*
+ * Store half-word to [rx + imm]
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int sth_c(struct pt_regs *regs, uint32_t rz, uint32_t addr)
+{
+ uint32_t byte0, byte1;
+
+ byte0 = byte1 = get_ptreg(regs, rz);
+
+ byte0 &= 0xff;
+
+ if (stb_asm(addr, byte0))
+ return 1;
+
+ addr += 1;
+ byte1 = (byte1 >> 8) & 0xff;
+ if (stb_asm(addr, byte1))
+ return 1;
+
+ return 0;
+}
+
+/*
+ * Get word from [rx + imm]
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int ldw_c(struct pt_regs *regs, uint32_t rz, uint32_t addr)
+{
+ uint32_t byte0, byte1, byte2, byte3;
+
+ if (ldb_asm(addr, ))
+ return 1;
+
+ addr += 1;
+ if (ldb_asm(addr, ))
+ return 1;
+
+ addr += 1;
+ if (ldb_asm(addr, ))
+ return 1;
+
+ addr += 1;
+ if (ldb_asm(addr, ))
+ return 1;
+
+ byte0 |= byte1 << 8;
+ byte0 |= byte2 << 16;
+ byte0 |= byte3 << 24;
+
+ put_ptreg(regs, rz, byte0);
+
+ return 0;
+}
+
+/*
+ * Store word to [rx + imm]
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int stw_c(struct pt_regs *regs, uint32_t rz, uint32_t addr)
+{
+ uint32_t byte0, byte1, byte2, byte3;
+
+
[PATCH V8 05/21] csky: System Call
This patch adds files related to syscall.
Signed-off-by: Guo Ren
---
arch/csky/include/asm/syscall.h | 71 +
arch/csky/include/asm/syscalls.h| 15
arch/csky/include/uapi/asm/unistd.h | 10 ++
arch/csky/kernel/syscall.c | 43 ++
arch/csky/kernel/syscall_table.c| 14
5 files changed, 153 insertions(+)
create mode 100644 arch/csky/include/asm/syscall.h
create mode 100644 arch/csky/include/asm/syscalls.h
create mode 100644 arch/csky/include/uapi/asm/unistd.h
create mode 100644 arch/csky/kernel/syscall.c
create mode 100644 arch/csky/kernel/syscall_table.c
diff --git a/arch/csky/include/asm/syscall.h b/arch/csky/include/asm/syscall.h
new file mode 100644
index 000..926a64a
--- /dev/null
+++ b/arch/csky/include/asm/syscall.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASM_SYSCALL_H
+#define __ASM_SYSCALL_H
+
+#include
+#include
+#include
+
+static inline int
+syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
+{
+ return regs_syscallid(regs);
+}
+
+static inline void
+syscall_rollback(struct task_struct *task, struct pt_regs *regs)
+{
+ regs->a0 = regs->orig_a0;
+}
+
+static inline long
+syscall_get_error(struct task_struct *task, struct pt_regs *regs)
+{
+ unsigned long error = regs->a0;
+
+ return IS_ERR_VALUE(error) ? error : 0;
+}
+
+static inline long
+syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
+{
+ return regs->a0;
+}
+
+static inline void
+syscall_set_return_value(struct task_struct *task, struct pt_regs *regs,
+ int error, long val)
+{
+ regs->a0 = (long) error ?: val;
+}
+
+static inline void
+syscall_get_arguments(struct task_struct *task, struct pt_regs *regs,
+ unsigned int i, unsigned int n, unsigned long *args)
+{
+ BUG_ON(i + n > 6);
+ if (i == 0) {
+ args[0] = regs->orig_a0;
+ args++;
+ i++;
+ n--;
+ }
+ memcpy(args, >a1 + i * sizeof(regs->a1), n * sizeof(args[0]));
+}
+
+static inline void
+syscall_set_arguments(struct task_struct *task, struct pt_regs *regs,
+ unsigned int i, unsigned int n, const unsigned long *args)
+{
+ BUG_ON(i + n > 6);
+ if (i == 0) {
+ regs->orig_a0 = args[0];
+ args++;
+ i++;
+ n--;
+ }
+ memcpy(>a1 + i * sizeof(regs->a1), args, n * sizeof(regs->a0));
+}
+
+#endif /* __ASM_SYSCALL_H */
diff --git a/arch/csky/include/asm/syscalls.h b/arch/csky/include/asm/syscalls.h
new file mode 100644
index 000..5d48e5e
--- /dev/null
+++ b/arch/csky/include/asm/syscalls.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_SYSCALLS_H
+#define __ASM_CSKY_SYSCALLS_H
+
+#include
+
+long sys_cacheflush(void __user *, unsigned long, int);
+
+long sys_set_thread_area(unsigned long addr);
+
+long sys_csky_fadvise64_64(int fd, int advice, loff_t offset, loff_t len);
+
+#endif /* __ASM_CSKY_SYSCALLS_H */
diff --git a/arch/csky/include/uapi/asm/unistd.h
b/arch/csky/include/uapi/asm/unistd.h
new file mode 100644
index 000..16ed71e
--- /dev/null
+++ b/arch/csky/include/uapi/asm/unistd.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#define __ARCH_WANT_SYS_CLONE
+#include
+
+#define __NR_set_thread_area (__NR_arch_specific_syscall + 0)
+__SYSCALL(__NR_set_thread_area, sys_set_thread_area)
+#define __NR_cacheflush(__NR_arch_specific_syscall + 4)
+__SYSCALL(__NR_cacheflush, sys_cacheflush)
diff --git a/arch/csky/kernel/syscall.c b/arch/csky/kernel/syscall.c
new file mode 100644
index 000..3d30e58
--- /dev/null
+++ b/arch/csky/kernel/syscall.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+
+SYSCALL_DEFINE1(set_thread_area, unsigned long, addr)
+{
+ struct thread_info *ti = task_thread_info(current);
+ struct pt_regs *reg = current_pt_regs();
+
+ reg->tls = addr;
+ ti->tp_value = addr;
+
+ return 0;
+}
+
+SYSCALL_DEFINE6(mmap2,
+ unsigned long, addr,
+ unsigned long, len,
+ unsigned long, prot,
+ unsigned long, flags,
+ unsigned long, fd,
+ off_t, offset)
+{
+ if (unlikely(offset & (~PAGE_MASK >> 12)))
+ return -EINVAL;
+
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd,
+ offset >> (PAGE_SHIFT - 12));
+}
+
+/*
+ * for abiv1 the 64bits args should be even th, So we need mov the advice
+ * forward.
+ */
+SYSCALL_DEFINE4(csky_fadvise64_64,
+ int, fd,
+ int, advice,
+ loff_t, offset,
+ loff_t, len)
+{
+ return ksys_fadvise64_64(fd, offset, len, advice);
+}
[PATCH V8 05/21] csky: System Call
This patch adds files related to syscall.
Signed-off-by: Guo Ren
---
arch/csky/include/asm/syscall.h | 71 +
arch/csky/include/asm/syscalls.h| 15
arch/csky/include/uapi/asm/unistd.h | 10 ++
arch/csky/kernel/syscall.c | 43 ++
arch/csky/kernel/syscall_table.c| 14
5 files changed, 153 insertions(+)
create mode 100644 arch/csky/include/asm/syscall.h
create mode 100644 arch/csky/include/asm/syscalls.h
create mode 100644 arch/csky/include/uapi/asm/unistd.h
create mode 100644 arch/csky/kernel/syscall.c
create mode 100644 arch/csky/kernel/syscall_table.c
diff --git a/arch/csky/include/asm/syscall.h b/arch/csky/include/asm/syscall.h
new file mode 100644
index 000..926a64a
--- /dev/null
+++ b/arch/csky/include/asm/syscall.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __ASM_SYSCALL_H
+#define __ASM_SYSCALL_H
+
+#include
+#include
+#include
+
+static inline int
+syscall_get_nr(struct task_struct *task, struct pt_regs *regs)
+{
+ return regs_syscallid(regs);
+}
+
+static inline void
+syscall_rollback(struct task_struct *task, struct pt_regs *regs)
+{
+ regs->a0 = regs->orig_a0;
+}
+
+static inline long
+syscall_get_error(struct task_struct *task, struct pt_regs *regs)
+{
+ unsigned long error = regs->a0;
+
+ return IS_ERR_VALUE(error) ? error : 0;
+}
+
+static inline long
+syscall_get_return_value(struct task_struct *task, struct pt_regs *regs)
+{
+ return regs->a0;
+}
+
+static inline void
+syscall_set_return_value(struct task_struct *task, struct pt_regs *regs,
+ int error, long val)
+{
+ regs->a0 = (long) error ?: val;
+}
+
+static inline void
+syscall_get_arguments(struct task_struct *task, struct pt_regs *regs,
+ unsigned int i, unsigned int n, unsigned long *args)
+{
+ BUG_ON(i + n > 6);
+ if (i == 0) {
+ args[0] = regs->orig_a0;
+ args++;
+ i++;
+ n--;
+ }
+ memcpy(args, >a1 + i * sizeof(regs->a1), n * sizeof(args[0]));
+}
+
+static inline void
+syscall_set_arguments(struct task_struct *task, struct pt_regs *regs,
+ unsigned int i, unsigned int n, const unsigned long *args)
+{
+ BUG_ON(i + n > 6);
+ if (i == 0) {
+ regs->orig_a0 = args[0];
+ args++;
+ i++;
+ n--;
+ }
+ memcpy(>a1 + i * sizeof(regs->a1), args, n * sizeof(regs->a0));
+}
+
+#endif /* __ASM_SYSCALL_H */
diff --git a/arch/csky/include/asm/syscalls.h b/arch/csky/include/asm/syscalls.h
new file mode 100644
index 000..5d48e5e
--- /dev/null
+++ b/arch/csky/include/asm/syscalls.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#ifndef __ASM_CSKY_SYSCALLS_H
+#define __ASM_CSKY_SYSCALLS_H
+
+#include
+
+long sys_cacheflush(void __user *, unsigned long, int);
+
+long sys_set_thread_area(unsigned long addr);
+
+long sys_csky_fadvise64_64(int fd, int advice, loff_t offset, loff_t len);
+
+#endif /* __ASM_CSKY_SYSCALLS_H */
diff --git a/arch/csky/include/uapi/asm/unistd.h
b/arch/csky/include/uapi/asm/unistd.h
new file mode 100644
index 000..16ed71e
--- /dev/null
+++ b/arch/csky/include/uapi/asm/unistd.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#define __ARCH_WANT_SYS_CLONE
+#include
+
+#define __NR_set_thread_area (__NR_arch_specific_syscall + 0)
+__SYSCALL(__NR_set_thread_area, sys_set_thread_area)
+#define __NR_cacheflush(__NR_arch_specific_syscall + 4)
+__SYSCALL(__NR_cacheflush, sys_cacheflush)
diff --git a/arch/csky/kernel/syscall.c b/arch/csky/kernel/syscall.c
new file mode 100644
index 000..3d30e58
--- /dev/null
+++ b/arch/csky/kernel/syscall.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+
+SYSCALL_DEFINE1(set_thread_area, unsigned long, addr)
+{
+ struct thread_info *ti = task_thread_info(current);
+ struct pt_regs *reg = current_pt_regs();
+
+ reg->tls = addr;
+ ti->tp_value = addr;
+
+ return 0;
+}
+
+SYSCALL_DEFINE6(mmap2,
+ unsigned long, addr,
+ unsigned long, len,
+ unsigned long, prot,
+ unsigned long, flags,
+ unsigned long, fd,
+ off_t, offset)
+{
+ if (unlikely(offset & (~PAGE_MASK >> 12)))
+ return -EINVAL;
+
+ return ksys_mmap_pgoff(addr, len, prot, flags, fd,
+ offset >> (PAGE_SHIFT - 12));
+}
+
+/*
+ * for abiv1 the 64bits args should be even th, So we need mov the advice
+ * forward.
+ */
+SYSCALL_DEFINE4(csky_fadvise64_64,
+ int, fd,
+ int, advice,
+ loff_t, offset,
+ loff_t, len)
+{
+ return ksys_fadvise64_64(fd, offset, len, advice);
+}
[PATCH V8 04/21] csky: Exception handling and mm-fault
This patch adds exception handling code, cpuinfo and mm-fault code.
Signed-off-by: Guo Ren
---
arch/csky/abiv1/alignment.c | 323
arch/csky/abiv1/inc/abi/entry.h | 160
arch/csky/abiv2/inc/abi/entry.h | 156
arch/csky/include/asm/traps.h | 44 +
arch/csky/include/asm/unistd.h | 4 +
arch/csky/kernel/cpu-probe.c| 79
arch/csky/kernel/entry.S| 396
arch/csky/kernel/traps.c| 172 +
arch/csky/mm/fault.c| 220 ++
9 files changed, 1554 insertions(+)
create mode 100644 arch/csky/abiv1/alignment.c
create mode 100644 arch/csky/abiv1/inc/abi/entry.h
create mode 100644 arch/csky/abiv2/inc/abi/entry.h
create mode 100644 arch/csky/include/asm/traps.h
create mode 100644 arch/csky/include/asm/unistd.h
create mode 100644 arch/csky/kernel/cpu-probe.c
create mode 100644 arch/csky/kernel/entry.S
create mode 100644 arch/csky/kernel/traps.c
create mode 100644 arch/csky/mm/fault.c
diff --git a/arch/csky/abiv1/alignment.c b/arch/csky/abiv1/alignment.c
new file mode 100644
index 000..8ec7400
--- /dev/null
+++ b/arch/csky/abiv1/alignment.c
@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+
+static int align_enable = 1;
+static int align_count;
+
+static inline uint32_t get_ptreg(struct pt_regs *regs, uint32_t rx)
+{
+ return *((int *)&(regs->a0) - 2 + rx);
+}
+
+static inline void put_ptreg(struct pt_regs *regs, uint32_t rx, uint32_t val)
+{
+ *((int *)&(regs->a0) - 2 + rx) = val;
+}
+
+/*
+ * Get byte-value from addr and set it to *valp.
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int ldb_asm(uint32_t addr, uint32_t *valp)
+{
+ uint32_t val;
+ int err;
+
+ if (!access_ok(VERIFY_READ, (void *)addr, 1))
+ return 1;
+
+ asm volatile (
+ "movi %0, 0\n"
+ "1:\n"
+ "ldb%1, (%2)\n"
+ "br 3f\n"
+ "2:\n"
+ "movi %0, 1\n"
+ "br 3f\n"
+ ".section __ex_table,\"a\"\n"
+ ".align 2\n"
+ ".long 1b, 2b\n"
+ ".previous\n"
+ "3:\n"
+ : "="(err), "=r"(val)
+ : "r" (addr)
+ );
+
+ *valp = val;
+
+ return err;
+}
+
+/*
+ * Put byte-value to addr.
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int stb_asm(uint32_t addr, uint32_t val)
+{
+ int err;
+
+ if (!access_ok(VERIFY_WRITE, (void *)addr, 1))
+ return 1;
+
+ asm volatile (
+ "movi %0, 0\n"
+ "1:\n"
+ "stb%1, (%2)\n"
+ "br 3f\n"
+ "2:\n"
+ "movi %0, 1\n"
+ "br 3f\n"
+ ".section __ex_table,\"a\"\n"
+ ".align 2\n"
+ ".long 1b, 2b\n"
+ ".previous\n"
+ "3:\n"
+ : "="(err)
+ : "r"(val), "r" (addr)
+ );
+
+ return err;
+}
+
+/*
+ * Get half-word from [rx + imm]
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int ldh_c(struct pt_regs *regs, uint32_t rz, uint32_t addr)
+{
+ uint32_t byte0, byte1;
+
+ if (ldb_asm(addr, ))
+ return 1;
+ addr += 1;
+ if (ldb_asm(addr, ))
+ return 1;
+
+ byte0 |= byte1 << 8;
+ put_ptreg(regs, rz, byte0);
+
+ return 0;
+}
+
+/*
+ * Store half-word to [rx + imm]
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int sth_c(struct pt_regs *regs, uint32_t rz, uint32_t addr)
+{
+ uint32_t byte0, byte1;
+
+ byte0 = byte1 = get_ptreg(regs, rz);
+
+ byte0 &= 0xff;
+
+ if (stb_asm(addr, byte0))
+ return 1;
+
+ addr += 1;
+ byte1 = (byte1 >> 8) & 0xff;
+ if (stb_asm(addr, byte1))
+ return 1;
+
+ return 0;
+}
+
+/*
+ * Get word from [rx + imm]
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int ldw_c(struct pt_regs *regs, uint32_t rz, uint32_t addr)
+{
+ uint32_t byte0, byte1, byte2, byte3;
+
+ if (ldb_asm(addr, ))
+ return 1;
+
+ addr += 1;
+ if (ldb_asm(addr, ))
+ return 1;
+
+ addr += 1;
+ if (ldb_asm(addr, ))
+ return 1;
+
+ addr += 1;
+ if (ldb_asm(addr, ))
+ return 1;
+
+ byte0 |= byte1 << 8;
+ byte0 |= byte2 << 16;
+ byte0 |= byte3 << 24;
+
+ put_ptreg(regs, rz, byte0);
+
+ return 0;
+}
+
+/*
+ * Store word to [rx + imm]
+ *
+ * Success: return 0
+ * Failure: return 1
+ */
+static int stw_c(struct pt_regs *regs, uint32_t rz, uint32_t addr)
+{
+ uint32_t byte0, byte1, byte2, byte3;
+
+
[PATCH V8 03/21] csky: Kernel booting
This patch add boot code. Thx boot params is all in dtb and it's
the only way to let kernel get bootloader param information.
Changelog:
- Use built-in dtb when dtb param is NULL.
- Add dummy console for allmodconfig.
Signed-off-by: Guo Ren
---
arch/csky/kernel/head.S| 77
arch/csky/kernel/setup.c | 162 +
arch/csky/kernel/vmlinux.lds.S | 66 +
3 files changed, 305 insertions(+)
create mode 100644 arch/csky/kernel/head.S
create mode 100644 arch/csky/kernel/setup.c
create mode 100644 arch/csky/kernel/vmlinux.lds.S
diff --git a/arch/csky/kernel/head.S b/arch/csky/kernel/head.S
new file mode 100644
index 000..9c4ec47
--- /dev/null
+++ b/arch/csky/kernel/head.S
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#include
+#include
+#include
+#include
+
+__HEAD
+ENTRY(_start)
+ /* set super user mode */
+ lrw a3, DEFAULT_PSR_VALUE
+ mtcra3, psr
+ psrset ee
+
+ SETUP_MMU a3
+
+ /* set stack point */
+ lrw a3, init_thread_union + THREAD_SIZE
+ mov sp, a3
+
+ jmpicsky_start
+END(_start)
+
+#ifdef CONFIG_SMP
+.align 10
+ENTRY(_start_smp_secondary)
+ /* Invalid I/Dcache BTB BHT */
+ movia3, 7
+ lslia3, 16
+ addia3, (1<<4) | 3
+ mtcra3, cr17
+
+ tlbi.alls
+
+ /* setup PAGEMASK */
+ movia3, 0
+ mtcra3, cr<6, 15>
+
+ /* setup MEL0/MEL1 */
+ grs a0, _start_smp_pc
+_start_smp_pc:
+ bmaski a1, 13
+ andna0, a1
+ movia1, 0x0006
+ movia2, 0x1006
+ or a1, a0
+ or a2, a0
+ mtcra1, cr<2, 15>
+ mtcra2, cr<3, 15>
+
+ /* setup MEH */
+ mtcra0, cr<4, 15>
+
+ /* write TLB */
+ bgeni a3, 28
+ mtcra3, cr<8, 15>
+
+ SETUP_MMU a3
+
+ /* enable MMU */
+ movia3, 1
+ mtcra3, cr18
+
+ jmpi_goto_mmu_on
+_goto_mmu_on:
+ lrw a3, DEFAULT_PSR_VALUE
+ mtcra3, psr
+ psrset ee
+
+ /* set stack point */
+ lrw a3, secondary_stack
+ ld.wa3, (a3, 0)
+ mov sp, a3
+
+ jmpicsky_start_secondary
+END(_start_smp_secondary)
+#endif
diff --git a/arch/csky/kernel/setup.c b/arch/csky/kernel/setup.c
new file mode 100644
index 000..a5e3ab1
--- /dev/null
+++ b/arch/csky/kernel/setup.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#ifdef CONFIG_DUMMY_CONSOLE
+struct screen_info screen_info = {
+ .orig_video_lines = 30,
+ .orig_video_cols= 80,
+ .orig_video_mode= 0,
+ .orig_video_ega_bx = 0,
+ .orig_video_isVGA = 1,
+ .orig_video_points = 8
+};
+#endif
+
+phys_addr_t __init_memblock memblock_end_of_REG0(void)
+{
+ return (memblock.memory.regions[0].base +
+ memblock.memory.regions[0].size);
+}
+
+phys_addr_t __init_memblock memblock_start_of_REG1(void)
+{
+ return memblock.memory.regions[1].base;
+}
+
+size_t __init_memblock memblock_size_of_REG1(void)
+{
+ return memblock.memory.regions[1].size;
+}
+
+static void __init csky_memblock_init(void)
+{
+ unsigned long zone_size[MAX_NR_ZONES];
+ unsigned long zhole_size[MAX_NR_ZONES];
+ signed long size;
+
+ memblock_reserve(__pa(_stext), _end - _stext);
+#ifdef CONFIG_BLK_DEV_INITRD
+ memblock_reserve(__pa(initrd_start), initrd_end - initrd_start);
+#endif
+
+ early_init_fdt_reserve_self();
+ early_init_fdt_scan_reserved_mem();
+
+ memblock_dump_all();
+
+ memset(zone_size, 0, sizeof(zone_size));
+ memset(zhole_size, 0, sizeof(zhole_size));
+
+ min_low_pfn = PFN_UP(memblock_start_of_DRAM());
+ max_pfn = PFN_DOWN(memblock_end_of_DRAM());
+
+ max_low_pfn = PFN_UP(memblock_end_of_REG0());
+ if (max_low_pfn == 0)
+ max_low_pfn = max_pfn;
+
+ size = max_pfn - min_low_pfn;
+
+ if (memblock.memory.cnt > 1) {
+ zone_size[ZONE_NORMAL] =
+ PFN_DOWN(memblock_start_of_REG1()) - min_low_pfn;
+ zhole_size[ZONE_NORMAL] =
+ PFN_DOWN(memblock_start_of_REG1()) - max_low_pfn;
+ } else {
+ if (size <= PFN_DOWN(LOWMEM_LIMIT - PHYS_OFFSET_OFFSET))
+ zone_size[ZONE_NORMAL] = max_pfn - min_low_pfn;
+ else {
+ zone_size[ZONE_NORMAL] =
+ PFN_DOWN(LOWMEM_LIMIT - PHYS_OFFSET_OFFSET);
+ max_low_pfn = min_low_pfn + zone_size[ZONE_NORMAL];
+ }
+ }
+
+#ifdef CONFIG_HIGHMEM
+ size = 0;
[PATCH V8 03/21] csky: Kernel booting
This patch add boot code. Thx boot params is all in dtb and it's
the only way to let kernel get bootloader param information.
Changelog:
- Use built-in dtb when dtb param is NULL.
- Add dummy console for allmodconfig.
Signed-off-by: Guo Ren
---
arch/csky/kernel/head.S| 77
arch/csky/kernel/setup.c | 162 +
arch/csky/kernel/vmlinux.lds.S | 66 +
3 files changed, 305 insertions(+)
create mode 100644 arch/csky/kernel/head.S
create mode 100644 arch/csky/kernel/setup.c
create mode 100644 arch/csky/kernel/vmlinux.lds.S
diff --git a/arch/csky/kernel/head.S b/arch/csky/kernel/head.S
new file mode 100644
index 000..9c4ec47
--- /dev/null
+++ b/arch/csky/kernel/head.S
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#include
+#include
+#include
+#include
+
+__HEAD
+ENTRY(_start)
+ /* set super user mode */
+ lrw a3, DEFAULT_PSR_VALUE
+ mtcra3, psr
+ psrset ee
+
+ SETUP_MMU a3
+
+ /* set stack point */
+ lrw a3, init_thread_union + THREAD_SIZE
+ mov sp, a3
+
+ jmpicsky_start
+END(_start)
+
+#ifdef CONFIG_SMP
+.align 10
+ENTRY(_start_smp_secondary)
+ /* Invalid I/Dcache BTB BHT */
+ movia3, 7
+ lslia3, 16
+ addia3, (1<<4) | 3
+ mtcra3, cr17
+
+ tlbi.alls
+
+ /* setup PAGEMASK */
+ movia3, 0
+ mtcra3, cr<6, 15>
+
+ /* setup MEL0/MEL1 */
+ grs a0, _start_smp_pc
+_start_smp_pc:
+ bmaski a1, 13
+ andna0, a1
+ movia1, 0x0006
+ movia2, 0x1006
+ or a1, a0
+ or a2, a0
+ mtcra1, cr<2, 15>
+ mtcra2, cr<3, 15>
+
+ /* setup MEH */
+ mtcra0, cr<4, 15>
+
+ /* write TLB */
+ bgeni a3, 28
+ mtcra3, cr<8, 15>
+
+ SETUP_MMU a3
+
+ /* enable MMU */
+ movia3, 1
+ mtcra3, cr18
+
+ jmpi_goto_mmu_on
+_goto_mmu_on:
+ lrw a3, DEFAULT_PSR_VALUE
+ mtcra3, psr
+ psrset ee
+
+ /* set stack point */
+ lrw a3, secondary_stack
+ ld.wa3, (a3, 0)
+ mov sp, a3
+
+ jmpicsky_start_secondary
+END(_start_smp_secondary)
+#endif
diff --git a/arch/csky/kernel/setup.c b/arch/csky/kernel/setup.c
new file mode 100644
index 000..a5e3ab1
--- /dev/null
+++ b/arch/csky/kernel/setup.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#ifdef CONFIG_DUMMY_CONSOLE
+struct screen_info screen_info = {
+ .orig_video_lines = 30,
+ .orig_video_cols= 80,
+ .orig_video_mode= 0,
+ .orig_video_ega_bx = 0,
+ .orig_video_isVGA = 1,
+ .orig_video_points = 8
+};
+#endif
+
+phys_addr_t __init_memblock memblock_end_of_REG0(void)
+{
+ return (memblock.memory.regions[0].base +
+ memblock.memory.regions[0].size);
+}
+
+phys_addr_t __init_memblock memblock_start_of_REG1(void)
+{
+ return memblock.memory.regions[1].base;
+}
+
+size_t __init_memblock memblock_size_of_REG1(void)
+{
+ return memblock.memory.regions[1].size;
+}
+
+static void __init csky_memblock_init(void)
+{
+ unsigned long zone_size[MAX_NR_ZONES];
+ unsigned long zhole_size[MAX_NR_ZONES];
+ signed long size;
+
+ memblock_reserve(__pa(_stext), _end - _stext);
+#ifdef CONFIG_BLK_DEV_INITRD
+ memblock_reserve(__pa(initrd_start), initrd_end - initrd_start);
+#endif
+
+ early_init_fdt_reserve_self();
+ early_init_fdt_scan_reserved_mem();
+
+ memblock_dump_all();
+
+ memset(zone_size, 0, sizeof(zone_size));
+ memset(zhole_size, 0, sizeof(zhole_size));
+
+ min_low_pfn = PFN_UP(memblock_start_of_DRAM());
+ max_pfn = PFN_DOWN(memblock_end_of_DRAM());
+
+ max_low_pfn = PFN_UP(memblock_end_of_REG0());
+ if (max_low_pfn == 0)
+ max_low_pfn = max_pfn;
+
+ size = max_pfn - min_low_pfn;
+
+ if (memblock.memory.cnt > 1) {
+ zone_size[ZONE_NORMAL] =
+ PFN_DOWN(memblock_start_of_REG1()) - min_low_pfn;
+ zhole_size[ZONE_NORMAL] =
+ PFN_DOWN(memblock_start_of_REG1()) - max_low_pfn;
+ } else {
+ if (size <= PFN_DOWN(LOWMEM_LIMIT - PHYS_OFFSET_OFFSET))
+ zone_size[ZONE_NORMAL] = max_pfn - min_low_pfn;
+ else {
+ zone_size[ZONE_NORMAL] =
+ PFN_DOWN(LOWMEM_LIMIT - PHYS_OFFSET_OFFSET);
+ max_low_pfn = min_low_pfn + zone_size[ZONE_NORMAL];
+ }
+ }
+
+#ifdef CONFIG_HIGHMEM
+ size = 0;
[PATCH V8 00/21] C-SKY(csky) Linux Kernel Port
This is the 8th version patchset to add the Linux kernel port for C-SKY(csky) based on linux-4.19-rc3. In this patchset, we fixup make allmodconfig and remove one callback in smp.c with irqchip's feedback. Here is the LTP test report for this patchset: (and add "V12 C-SKY(csky) Linux Kernel Driver" patchset) --- Total Tests: 1298 Total Skipped Tests: 280 Total Failures: 11 Kernel Version: 4.19.0-rc3+ Machine Architecture: csky Hostname: buildroot --- This patchset adds architecture support to Linux for C-SKY's 32-bit embedded There are two ABI versions with several CPU cores in this patchset: ABIv1: ck610 (16-bit instruction, 32-bit data path, VIPT Cache ...) ABIv2: ck807 ck810 ck860 (16/32-bit variable length instruction, PIPT Cache, SMP ...) More information: http://en.c-sky.com The development repo: https://github.com/c-sky/csky-linux ABI Documentation: https://github.com/c-sky/csky-doc Here is the pre-built cross compiler for fast test from our CI: https://gitlab.com/c-sky/buildroot/-/jobs/101608095/artifacts/file/output/images/csky_toolchain_qemu_csky_ck807f_4.18_glibc_defconfig_482b221e52908be1c9b2ccb444255e1562bb7025.tar.xz We use buildroot as our CI-test enviornment. "LTP, Lmbench ..." will be tested for every commit. See here for more details: https://gitlab.com/c-sky/buildroot/pipelines Any feedback is welcome. Changes in v8: - Pass make allmodconfig. - Implement abiv1 get_user_dword(). - Remove set_irq_mapping() used by driver in smp.c. Changes in v7: - Use checkpatch.pl to check all patches and fixup as possible. - Remove github.com/c-sky print in bootup. - Give a return in DMA_ATTR_NON_CONSISTENT in csky_dma_alloc_atomic(). - Remove the NSIGXXX in fpu.c and use force_sig_fault() in fpu.c. - Remove irq.h and add it in asm/Kbuild. - Use byteswap helpers in abiv1/bswapXi.c. - Fixup arch_sync_dma() only with one page problem. Changes in v6: - use asm-generic/bitops/atomic.h for all in asm/bitops.h - fix flush_cache_range and tlb_start_vma - fix compile error with include linux/bug.h in cmpxchg.h - improve the comment Changes in v5: - remove redundant smp_mb operations in spinlock.h - add commit message for dt-bindings docs - add CPUHP_AP_CSKY_TIMER_STARTING in hotplug.h for csky_mptimer - add COMPILE_TEST for timer-gx6605s Kconfig - seperate csky two interrupt controllers with 2 patches - add MAINTAINERS patch for csky - move IPI_IRQ into csky_mptimer, fixup irq_mapping problem - coding convension Changes in v4: - cleanup defconfig - use ksys_ in syscall.c - remove wrong comment in vdso.c - Use GENERIC_IRQ_MULTI_HANDLER - optimize the memset.c - fixup dts warnings - remove big-endian in byteorder.h Changes in v3: dc560f1 csky: change to EM_CSKY 252 for elf.h 2ac3ddf csky: remove gx6605s.dts af00b8c csky: add defconfig and qemu.dts 6c87efb csky: remove the deprecate name. f6dda39 csky: add dt-bindings doc. d9f02a8 csky: remove KERNEL_VERSION in upstream branch 7bd663c csky: Use kernel/dma/noncoherent.c 1544c09 csky: bugfix emmc hang up LINS-976 e963271 csky: cleanup include/asm/Kbuild cd267ba csky: remove CSKY_DEBUG_INFO 78950da csky: remove dcache invalid. 13fe51d csky: remove csum_ipv6_magic(), use generic one. a7372db csky: bugfix CK810 access twice error. 1bb7c69 csky: bugfix add gcc asm memory for barrier. 5ea3257 csky: add -msoft-float instead of -mfloat-abi=soft. 38b037d csky: bugfix losing cache flush range. ab5e8c4 csky: Add ticket-spinlock and qrwlock support. c9aaec5 csky: rename cskyksyms.c to libgcc_ksyms.c 28c5e48 csky: avoid the MB on failure: trylock f929c97 csky: bugfix idly4 may cause exception. 09dc496 csky: Use GENERIC_ASHLDI3/ASHRDI3 etc 6ecc99d csky: optimize smp boot code. 16f50df csky: asm/bug.h simple implement. 0ba532a csky: csky asm/atomic.h added. df66947 csky: asm/compat.h added 275a06f csky: String operations optimization 4c021dd csky: ck860 SMP memory barrier optimize fc39c66 csky: Add wait/doze/stop d005144 csky: add GENERIC_ALLOCATOR 4a10074 csky: bugfix cma failed for highmem. 9f2ca70 csky: CMA supported :) 53791f4 csky: optimize csky_dma_alloc_nonatomic 974676e csky: optimize the cpuinfo printf. 2538669 csky: bugfix make headers_install error. 1158d0c csky: prevent hard-float and vdsp instructions. dc3c856 csky: increase Normal Memory to 1GB 6ee5932 csky: bugfix qemu mmu couldn't support 0xe000 1d7dfb8 csky: csky_dma_alloc_atomic added. caf6610 csky: restruct the fixmap memory layout. 5a17eaa csky: use -Wa,-mcpu=ckxxxfv to the as. 4d51829 csky: use Kconfig.hz. f3f88fa csky: BUGFIX add -mcpu=ck860f support 6192fd1 csky: support ck860 fpu. 7aa5e01 csky: BUGFIX add smp_mb before ldex. 15758e2 csky: BUGFIX tlbi couldn't handle ASID in another CPU core. d69640d csky: enable tlbi.vas to flush one tlb entry Changes in v2: a29bfc8 csky: add pre_mmu_init, move misc mmu setup to mm/init.c 4eab702 csky: no need kmap for
[PATCH V8 02/21] csky: defconfig
This patch adds csky defconfig. Signed-off-by: Guo Ren --- arch/csky/configs/defconfig | 61 + 1 file changed, 61 insertions(+) create mode 100644 arch/csky/configs/defconfig diff --git a/arch/csky/configs/defconfig b/arch/csky/configs/defconfig new file mode 100644 index 000..7ef4289 --- /dev/null +++ b/arch/csky/configs/defconfig @@ -0,0 +1,61 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_DEFAULT_HOSTNAME="csky" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_CPU_CK807=y +CONFIG_CPU_HAS_FPU=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_TTY_PRINTK=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_CSKY_MPTIMER=y +CONFIG_GX6605S_TIMER=y +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_GENERIC_PHY=y +CONFIG_EXT4_FS=y +CONFIG_FANOTIFY=y +CONFIG_QUOTA=y +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_NTFS_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +CONFIG_CRAMFS=y +CONFIG_ROMFS_FS=y +CONFIG_NFS_FS=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y -- 2.7.4
[PATCH V8 00/21] C-SKY(csky) Linux Kernel Port
This is the 8th version patchset to add the Linux kernel port for C-SKY(csky) based on linux-4.19-rc3. In this patchset, we fixup make allmodconfig and remove one callback in smp.c with irqchip's feedback. Here is the LTP test report for this patchset: (and add "V12 C-SKY(csky) Linux Kernel Driver" patchset) --- Total Tests: 1298 Total Skipped Tests: 280 Total Failures: 11 Kernel Version: 4.19.0-rc3+ Machine Architecture: csky Hostname: buildroot --- This patchset adds architecture support to Linux for C-SKY's 32-bit embedded There are two ABI versions with several CPU cores in this patchset: ABIv1: ck610 (16-bit instruction, 32-bit data path, VIPT Cache ...) ABIv2: ck807 ck810 ck860 (16/32-bit variable length instruction, PIPT Cache, SMP ...) More information: http://en.c-sky.com The development repo: https://github.com/c-sky/csky-linux ABI Documentation: https://github.com/c-sky/csky-doc Here is the pre-built cross compiler for fast test from our CI: https://gitlab.com/c-sky/buildroot/-/jobs/101608095/artifacts/file/output/images/csky_toolchain_qemu_csky_ck807f_4.18_glibc_defconfig_482b221e52908be1c9b2ccb444255e1562bb7025.tar.xz We use buildroot as our CI-test enviornment. "LTP, Lmbench ..." will be tested for every commit. See here for more details: https://gitlab.com/c-sky/buildroot/pipelines Any feedback is welcome. Changes in v8: - Pass make allmodconfig. - Implement abiv1 get_user_dword(). - Remove set_irq_mapping() used by driver in smp.c. Changes in v7: - Use checkpatch.pl to check all patches and fixup as possible. - Remove github.com/c-sky print in bootup. - Give a return in DMA_ATTR_NON_CONSISTENT in csky_dma_alloc_atomic(). - Remove the NSIGXXX in fpu.c and use force_sig_fault() in fpu.c. - Remove irq.h and add it in asm/Kbuild. - Use byteswap helpers in abiv1/bswapXi.c. - Fixup arch_sync_dma() only with one page problem. Changes in v6: - use asm-generic/bitops/atomic.h for all in asm/bitops.h - fix flush_cache_range and tlb_start_vma - fix compile error with include linux/bug.h in cmpxchg.h - improve the comment Changes in v5: - remove redundant smp_mb operations in spinlock.h - add commit message for dt-bindings docs - add CPUHP_AP_CSKY_TIMER_STARTING in hotplug.h for csky_mptimer - add COMPILE_TEST for timer-gx6605s Kconfig - seperate csky two interrupt controllers with 2 patches - add MAINTAINERS patch for csky - move IPI_IRQ into csky_mptimer, fixup irq_mapping problem - coding convension Changes in v4: - cleanup defconfig - use ksys_ in syscall.c - remove wrong comment in vdso.c - Use GENERIC_IRQ_MULTI_HANDLER - optimize the memset.c - fixup dts warnings - remove big-endian in byteorder.h Changes in v3: dc560f1 csky: change to EM_CSKY 252 for elf.h 2ac3ddf csky: remove gx6605s.dts af00b8c csky: add defconfig and qemu.dts 6c87efb csky: remove the deprecate name. f6dda39 csky: add dt-bindings doc. d9f02a8 csky: remove KERNEL_VERSION in upstream branch 7bd663c csky: Use kernel/dma/noncoherent.c 1544c09 csky: bugfix emmc hang up LINS-976 e963271 csky: cleanup include/asm/Kbuild cd267ba csky: remove CSKY_DEBUG_INFO 78950da csky: remove dcache invalid. 13fe51d csky: remove csum_ipv6_magic(), use generic one. a7372db csky: bugfix CK810 access twice error. 1bb7c69 csky: bugfix add gcc asm memory for barrier. 5ea3257 csky: add -msoft-float instead of -mfloat-abi=soft. 38b037d csky: bugfix losing cache flush range. ab5e8c4 csky: Add ticket-spinlock and qrwlock support. c9aaec5 csky: rename cskyksyms.c to libgcc_ksyms.c 28c5e48 csky: avoid the MB on failure: trylock f929c97 csky: bugfix idly4 may cause exception. 09dc496 csky: Use GENERIC_ASHLDI3/ASHRDI3 etc 6ecc99d csky: optimize smp boot code. 16f50df csky: asm/bug.h simple implement. 0ba532a csky: csky asm/atomic.h added. df66947 csky: asm/compat.h added 275a06f csky: String operations optimization 4c021dd csky: ck860 SMP memory barrier optimize fc39c66 csky: Add wait/doze/stop d005144 csky: add GENERIC_ALLOCATOR 4a10074 csky: bugfix cma failed for highmem. 9f2ca70 csky: CMA supported :) 53791f4 csky: optimize csky_dma_alloc_nonatomic 974676e csky: optimize the cpuinfo printf. 2538669 csky: bugfix make headers_install error. 1158d0c csky: prevent hard-float and vdsp instructions. dc3c856 csky: increase Normal Memory to 1GB 6ee5932 csky: bugfix qemu mmu couldn't support 0xe000 1d7dfb8 csky: csky_dma_alloc_atomic added. caf6610 csky: restruct the fixmap memory layout. 5a17eaa csky: use -Wa,-mcpu=ckxxxfv to the as. 4d51829 csky: use Kconfig.hz. f3f88fa csky: BUGFIX add -mcpu=ck860f support 6192fd1 csky: support ck860 fpu. 7aa5e01 csky: BUGFIX add smp_mb before ldex. 15758e2 csky: BUGFIX tlbi couldn't handle ASID in another CPU core. d69640d csky: enable tlbi.vas to flush one tlb entry Changes in v2: a29bfc8 csky: add pre_mmu_init, move misc mmu setup to mm/init.c 4eab702 csky: no need kmap for
[PATCH V8 02/21] csky: defconfig
This patch adds csky defconfig. Signed-off-by: Guo Ren --- arch/csky/configs/defconfig | 61 + 1 file changed, 61 insertions(+) create mode 100644 arch/csky/configs/defconfig diff --git a/arch/csky/configs/defconfig b/arch/csky/configs/defconfig new file mode 100644 index 000..7ef4289 --- /dev/null +++ b/arch/csky/configs/defconfig @@ -0,0 +1,61 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_DEFAULT_HOSTNAME="csky" +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_CPU_CK807=y +CONFIG_CPU_HAS_FPU=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_TTY_PRINTK=y +# CONFIG_VGA_CONSOLE is not set +CONFIG_CSKY_MPTIMER=y +CONFIG_GX6605S_TIMER=y +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_GENERIC_PHY=y +CONFIG_EXT4_FS=y +CONFIG_FANOTIFY=y +CONFIG_QUOTA=y +CONFIG_FSCACHE=m +CONFIG_FSCACHE_STATS=y +CONFIG_CACHEFILES=m +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_NTFS_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_CHILDREN=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CONFIGFS_FS=y +CONFIG_CRAMFS=y +CONFIG_ROMFS_FS=y +CONFIG_NFS_FS=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y -- 2.7.4
[PATCH V8 01/21] csky: Build infrastructure
This patch adds Makefile, Kconfig for build infrastructure. Changelog: - make allmodconfig is OK. - Use BUILTIN_DTB as string, remove bool define for compile. - Add xor.h in asm/Kbuild - Add compat.h in asm/Kbuild. - Add select DMA_DIRECT_OPS in Kconfig. - remove kernel/platform.c in Makefile. Signed-off-by: Guo Ren --- arch/csky/Kconfig | 205 + arch/csky/Kconfig.debug| 9 ++ arch/csky/Makefile | 93 +++ arch/csky/abiv1/Makefile | 8 ++ arch/csky/abiv2/Makefile | 10 ++ arch/csky/boot/Makefile| 24 arch/csky/boot/dts/Makefile| 13 +++ arch/csky/boot/dts/include/dt-bindings | 1 + arch/csky/include/asm/Kbuild | 72 arch/csky/include/uapi/asm/Kbuild | 33 ++ arch/csky/kernel/Makefile | 8 ++ arch/csky/lib/Makefile | 1 + arch/csky/mm/Makefile | 13 +++ 13 files changed, 490 insertions(+) create mode 100644 arch/csky/Kconfig create mode 100644 arch/csky/Kconfig.debug create mode 100644 arch/csky/Makefile create mode 100644 arch/csky/abiv1/Makefile create mode 100644 arch/csky/abiv2/Makefile create mode 100644 arch/csky/boot/Makefile create mode 100644 arch/csky/boot/dts/Makefile create mode 12 arch/csky/boot/dts/include/dt-bindings create mode 100644 arch/csky/include/asm/Kbuild create mode 100644 arch/csky/include/uapi/asm/Kbuild create mode 100644 arch/csky/kernel/Makefile create mode 100644 arch/csky/lib/Makefile create mode 100644 arch/csky/mm/Makefile diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig new file mode 100644 index 000..0a05585 --- /dev/null +++ b/arch/csky/Kconfig @@ -0,0 +1,205 @@ +config CSKY + def_bool y + select ARCH_HAS_SYNC_DMA_FOR_CPU + select ARCH_HAS_SYNC_DMA_FOR_DEVICE + select ARCH_USE_BUILTIN_BSWAP + select ARCH_USE_QUEUED_RWLOCKS if NR_CPUS>2 + select COMMON_CLK + select CLKSRC_MMIO + select CLKSRC_OF + select DMA_DIRECT_OPS + select DMA_NONCOHERENT_OPS + select IRQ_DOMAIN + select HANDLE_DOMAIN_IRQ + select DW_APB_TIMER_OF + select GENERIC_LIB_ASHLDI3 + select GENERIC_LIB_ASHRDI3 + select GENERIC_LIB_LSHRDI3 + select GENERIC_LIB_MULDI3 + select GENERIC_LIB_CMPDI2 + select GENERIC_LIB_UCMPDI2 + select GENERIC_ALLOCATOR + select GENERIC_ATOMIC64 + select GENERIC_CLOCKEVENTS + select GENERIC_CPU_DEVICES + select GENERIC_IRQ_CHIP + select GENERIC_IRQ_PROBE + select GENERIC_IRQ_SHOW + select GENERIC_IRQ_MULTI_HANDLER + select GENERIC_SCHED_CLOCK + select GENERIC_SMP_IDLE_THREAD + select HAVE_ARCH_TRACEHOOK + select HAVE_GENERIC_DMA_COHERENT + select HAVE_KERNEL_GZIP + select HAVE_KERNEL_LZO + select HAVE_KERNEL_LZMA + select HAVE_C_RECORDMCOUNT + select HAVE_DMA_API_DEBUG + select HAVE_DMA_CONTIGUOUS + select HAVE_MEMBLOCK + select MAY_HAVE_SPARSE_IRQ + select MODULES_USE_ELF_RELA if MODULES + select NO_BOOTMEM + select OF + select OF_EARLY_FLATTREE + select OF_RESERVED_MEM + select PERF_USE_VMALLOC + select RTC_LIB + select TIMER_OF + select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI + +config CPU_HAS_CACHEV2 + bool + +config CPU_HAS_FPUV2 + bool + +config CPU_HAS_HILO + bool + +config CPU_HAS_TLBI + bool + +config CPU_HAS_LDSTEX + bool + help + For SMP, CPU needs "ldex" instrcutions to atomic operations. + +config CPU_NEED_TLBSYNC + bool + +config CPU_NEED_SOFTALIGN + bool + +config CPU_NO_USER_BKPT + bool + help + For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, because + abiv2 is 16/32bit instruction set and "trap 1" is 32bit. + So we need a 16bit instruction as user space bkpt, and it will cause an illegal + instruction exception. + In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not. + +config GENERIC_CALIBRATE_DELAY + def_bool y + +config GENERIC_CSUM + def_bool y + +config GENERIC_HWEIGHT + def_bool y + +config MMU + def_bool y + +config RWSEM_GENERIC_SPINLOCK + def_bool y + +config TIME_LOW_RES + def_bool y + +config TRACE_IRQFLAGS_SUPPORT + def_bool y + +config CPU_TLB_SIZE + int + default "128" if (CPU_CK610 || CPU_CK807 || CPU_CK810) + default "1024" if (CPU_CK860) + +config CPU_ASID_BITS + int + default "8" if (CPU_CK610 || CPU_CK807 || CPU_CK810) + default "12"if (CPU_CK860) + +config L1_CACHE_SHIFT + int + default "4" if (CPU_CK610) + default "5" if (CPU_CK807 || CPU_CK810) + default "6" if (CPU_CK860) + +menu
[PATCH V8 01/21] csky: Build infrastructure
This patch adds Makefile, Kconfig for build infrastructure. Changelog: - make allmodconfig is OK. - Use BUILTIN_DTB as string, remove bool define for compile. - Add xor.h in asm/Kbuild - Add compat.h in asm/Kbuild. - Add select DMA_DIRECT_OPS in Kconfig. - remove kernel/platform.c in Makefile. Signed-off-by: Guo Ren --- arch/csky/Kconfig | 205 + arch/csky/Kconfig.debug| 9 ++ arch/csky/Makefile | 93 +++ arch/csky/abiv1/Makefile | 8 ++ arch/csky/abiv2/Makefile | 10 ++ arch/csky/boot/Makefile| 24 arch/csky/boot/dts/Makefile| 13 +++ arch/csky/boot/dts/include/dt-bindings | 1 + arch/csky/include/asm/Kbuild | 72 arch/csky/include/uapi/asm/Kbuild | 33 ++ arch/csky/kernel/Makefile | 8 ++ arch/csky/lib/Makefile | 1 + arch/csky/mm/Makefile | 13 +++ 13 files changed, 490 insertions(+) create mode 100644 arch/csky/Kconfig create mode 100644 arch/csky/Kconfig.debug create mode 100644 arch/csky/Makefile create mode 100644 arch/csky/abiv1/Makefile create mode 100644 arch/csky/abiv2/Makefile create mode 100644 arch/csky/boot/Makefile create mode 100644 arch/csky/boot/dts/Makefile create mode 12 arch/csky/boot/dts/include/dt-bindings create mode 100644 arch/csky/include/asm/Kbuild create mode 100644 arch/csky/include/uapi/asm/Kbuild create mode 100644 arch/csky/kernel/Makefile create mode 100644 arch/csky/lib/Makefile create mode 100644 arch/csky/mm/Makefile diff --git a/arch/csky/Kconfig b/arch/csky/Kconfig new file mode 100644 index 000..0a05585 --- /dev/null +++ b/arch/csky/Kconfig @@ -0,0 +1,205 @@ +config CSKY + def_bool y + select ARCH_HAS_SYNC_DMA_FOR_CPU + select ARCH_HAS_SYNC_DMA_FOR_DEVICE + select ARCH_USE_BUILTIN_BSWAP + select ARCH_USE_QUEUED_RWLOCKS if NR_CPUS>2 + select COMMON_CLK + select CLKSRC_MMIO + select CLKSRC_OF + select DMA_DIRECT_OPS + select DMA_NONCOHERENT_OPS + select IRQ_DOMAIN + select HANDLE_DOMAIN_IRQ + select DW_APB_TIMER_OF + select GENERIC_LIB_ASHLDI3 + select GENERIC_LIB_ASHRDI3 + select GENERIC_LIB_LSHRDI3 + select GENERIC_LIB_MULDI3 + select GENERIC_LIB_CMPDI2 + select GENERIC_LIB_UCMPDI2 + select GENERIC_ALLOCATOR + select GENERIC_ATOMIC64 + select GENERIC_CLOCKEVENTS + select GENERIC_CPU_DEVICES + select GENERIC_IRQ_CHIP + select GENERIC_IRQ_PROBE + select GENERIC_IRQ_SHOW + select GENERIC_IRQ_MULTI_HANDLER + select GENERIC_SCHED_CLOCK + select GENERIC_SMP_IDLE_THREAD + select HAVE_ARCH_TRACEHOOK + select HAVE_GENERIC_DMA_COHERENT + select HAVE_KERNEL_GZIP + select HAVE_KERNEL_LZO + select HAVE_KERNEL_LZMA + select HAVE_C_RECORDMCOUNT + select HAVE_DMA_API_DEBUG + select HAVE_DMA_CONTIGUOUS + select HAVE_MEMBLOCK + select MAY_HAVE_SPARSE_IRQ + select MODULES_USE_ELF_RELA if MODULES + select NO_BOOTMEM + select OF + select OF_EARLY_FLATTREE + select OF_RESERVED_MEM + select PERF_USE_VMALLOC + select RTC_LIB + select TIMER_OF + select USB_ARCH_HAS_EHCI + select USB_ARCH_HAS_OHCI + +config CPU_HAS_CACHEV2 + bool + +config CPU_HAS_FPUV2 + bool + +config CPU_HAS_HILO + bool + +config CPU_HAS_TLBI + bool + +config CPU_HAS_LDSTEX + bool + help + For SMP, CPU needs "ldex" instrcutions to atomic operations. + +config CPU_NEED_TLBSYNC + bool + +config CPU_NEED_SOFTALIGN + bool + +config CPU_NO_USER_BKPT + bool + help + For abiv2 we couldn't use "trap 1" as user space bkpt in gdbserver, because + abiv2 is 16/32bit instruction set and "trap 1" is 32bit. + So we need a 16bit instruction as user space bkpt, and it will cause an illegal + instruction exception. + In kernel we parse the *regs->pc to determine whether to send SIGTRAP or not. + +config GENERIC_CALIBRATE_DELAY + def_bool y + +config GENERIC_CSUM + def_bool y + +config GENERIC_HWEIGHT + def_bool y + +config MMU + def_bool y + +config RWSEM_GENERIC_SPINLOCK + def_bool y + +config TIME_LOW_RES + def_bool y + +config TRACE_IRQFLAGS_SUPPORT + def_bool y + +config CPU_TLB_SIZE + int + default "128" if (CPU_CK610 || CPU_CK807 || CPU_CK810) + default "1024" if (CPU_CK860) + +config CPU_ASID_BITS + int + default "8" if (CPU_CK610 || CPU_CK807 || CPU_CK810) + default "12"if (CPU_CK860) + +config L1_CACHE_SHIFT + int + default "4" if (CPU_CK610) + default "5" if (CPU_CK807 || CPU_CK810) + default "6" if (CPU_CK860) + +menu
Re: [PATCH 4.4 00/27] 4.4.161-stable review
On Thu, 11 Oct 2018 at 21:12, Greg Kroah-Hartman wrote: > > This is the start of the stable review cycle for the 4.4.161 release. > There are 27 patches in this series, all will be posted as a response > to this one. If anyone has any issues with these being applied, please > let me know. > > Responses should be made by Sat Oct 13 15:25:23 UTC 2018. > Anything received after that time might be too late. > > The whole patch series can be found in one patch at: > > https://www.kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.4.161-rc1.gz > or in the git tree and branch at: > > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git > linux-4.4.y > and the diffstat can be found below. > > thanks, > > greg k-h Results from Linaro’s test farm. No regressions on arm64, arm, x86_64, and i386. Summary kernel: 4.4.161-rc1 git repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git git branch: linux-4.4.y git commit: b3522afcec59a6a8030ebf4397f5b285b3e804d2 git describe: v4.4.160-28-gb3522afcec59 Test details: https://qa-reports.linaro.org/lkft/linux-stable-rc-4.4-oe/build/v4.4.160-28-gb3522afcec59 No regressions (compared to build v4.4.160) No fixes (compared to build v4.4.160) Ran 16805 total tests in the following environments and test suites. Environments -- - i386 - juno-r2 - arm64 - qemu_arm - qemu_i386 - qemu_x86_64 - x15 - arm - x86_64 Test Suites --- * boot * kselftest * libhugetlbfs * ltp-cap_bounds-tests * ltp-containers-tests * ltp-cve-tests * ltp-fcntl-locktests-tests * ltp-filecaps-tests * ltp-fs-tests * ltp-fs_bind-tests * ltp-fs_perms_simple-tests * ltp-fsx-tests * ltp-hugetlb-tests * ltp-io-tests * ltp-ipc-tests * ltp-math-tests * ltp-nptl-tests * ltp-open-posix-tests * ltp-pty-tests * ltp-sched-tests * ltp-securebits-tests * ltp-syscalls-tests * ltp-timers-tests * kselftest-vsyscall-mode-native * kselftest-vsyscall-mode-none Summary kernel: 4.4.161-rc1 git repo: https://git.linaro.org/lkft/arm64-stable-rc.git git branch: 4.4.161-rc1-hikey-20181011-301 git commit: d3ba9c3a1b2509d2b14941baee1cd504d5ab0a07 git describe: 4.4.161-rc1-hikey-20181011-301 Test details: https://qa-reports.linaro.org/lkft/linaro-hikey-stable-rc-4.4-oe/build/4.4.161-rc1-hikey-20181011-301 No regressions (compared to build 4.4.160-rc1-hikey-20181009-299) No fixes (compared to build 4.4.160-rc1-hikey-20181009-299) Ran 2688 total tests in the following environments and test suites. Environments -- - hi6220-hikey - arm64 - qemu_arm64 Test Suites --- * boot * kselftest * libhugetlbfs * ltp-cap_bounds-tests * ltp-containers-tests * ltp-cve-tests * ltp-fcntl-locktests-tests * ltp-filecaps-tests * ltp-fs-tests * ltp-fs_bind-tests * ltp-fs_perms_simple-tests * ltp-fsx-tests * ltp-hugetlb-tests * ltp-io-tests * ltp-ipc-tests * ltp-math-tests * ltp-nptl-tests * ltp-pty-tests * ltp-sched-tests * ltp-securebits-tests * ltp-syscalls-tests * ltp-timers-tests -- Linaro LKFT https://lkft.linaro.org
Re: [PATCH 4.4 00/27] 4.4.161-stable review
On Thu, 11 Oct 2018 at 21:12, Greg Kroah-Hartman wrote: > > This is the start of the stable review cycle for the 4.4.161 release. > There are 27 patches in this series, all will be posted as a response > to this one. If anyone has any issues with these being applied, please > let me know. > > Responses should be made by Sat Oct 13 15:25:23 UTC 2018. > Anything received after that time might be too late. > > The whole patch series can be found in one patch at: > > https://www.kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.4.161-rc1.gz > or in the git tree and branch at: > > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git > linux-4.4.y > and the diffstat can be found below. > > thanks, > > greg k-h Results from Linaro’s test farm. No regressions on arm64, arm, x86_64, and i386. Summary kernel: 4.4.161-rc1 git repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git git branch: linux-4.4.y git commit: b3522afcec59a6a8030ebf4397f5b285b3e804d2 git describe: v4.4.160-28-gb3522afcec59 Test details: https://qa-reports.linaro.org/lkft/linux-stable-rc-4.4-oe/build/v4.4.160-28-gb3522afcec59 No regressions (compared to build v4.4.160) No fixes (compared to build v4.4.160) Ran 16805 total tests in the following environments and test suites. Environments -- - i386 - juno-r2 - arm64 - qemu_arm - qemu_i386 - qemu_x86_64 - x15 - arm - x86_64 Test Suites --- * boot * kselftest * libhugetlbfs * ltp-cap_bounds-tests * ltp-containers-tests * ltp-cve-tests * ltp-fcntl-locktests-tests * ltp-filecaps-tests * ltp-fs-tests * ltp-fs_bind-tests * ltp-fs_perms_simple-tests * ltp-fsx-tests * ltp-hugetlb-tests * ltp-io-tests * ltp-ipc-tests * ltp-math-tests * ltp-nptl-tests * ltp-open-posix-tests * ltp-pty-tests * ltp-sched-tests * ltp-securebits-tests * ltp-syscalls-tests * ltp-timers-tests * kselftest-vsyscall-mode-native * kselftest-vsyscall-mode-none Summary kernel: 4.4.161-rc1 git repo: https://git.linaro.org/lkft/arm64-stable-rc.git git branch: 4.4.161-rc1-hikey-20181011-301 git commit: d3ba9c3a1b2509d2b14941baee1cd504d5ab0a07 git describe: 4.4.161-rc1-hikey-20181011-301 Test details: https://qa-reports.linaro.org/lkft/linaro-hikey-stable-rc-4.4-oe/build/4.4.161-rc1-hikey-20181011-301 No regressions (compared to build 4.4.160-rc1-hikey-20181009-299) No fixes (compared to build 4.4.160-rc1-hikey-20181009-299) Ran 2688 total tests in the following environments and test suites. Environments -- - hi6220-hikey - arm64 - qemu_arm64 Test Suites --- * boot * kselftest * libhugetlbfs * ltp-cap_bounds-tests * ltp-containers-tests * ltp-cve-tests * ltp-fcntl-locktests-tests * ltp-filecaps-tests * ltp-fs-tests * ltp-fs_bind-tests * ltp-fs_perms_simple-tests * ltp-fsx-tests * ltp-hugetlb-tests * ltp-io-tests * ltp-ipc-tests * ltp-math-tests * ltp-nptl-tests * ltp-pty-tests * ltp-sched-tests * ltp-securebits-tests * ltp-syscalls-tests * ltp-timers-tests -- Linaro LKFT https://lkft.linaro.org
Re: [PATCH 4.9 00/35] 4.9.133-stable review
On Thu, 11 Oct 2018 at 21:14, Greg Kroah-Hartman wrote: > > This is the start of the stable review cycle for the 4.9.133 release. > There are 35 patches in this series, all will be posted as a response > to this one. If anyone has any issues with these being applied, please > let me know. > > Responses should be made by Sat Oct 13 15:25:09 UTC 2018. > Anything received after that time might be too late. > > The whole patch series can be found in one patch at: > > https://www.kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.9.133-rc1.gz > or in the git tree and branch at: > > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git > linux-4.9.y > and the diffstat can be found below. > > thanks, > > greg k-h Results from Linaro’s test farm. No regressions on arm64, arm, x86_64, and i386. Summary kernel: 4.9.133-rc1 git repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git git branch: linux-4.9.y git commit: c26947f9eb18b1c3de2b4d76a981b0b468b390f2 git describe: v4.9.132-36-gc26947f9eb18 Test details: https://qa-reports.linaro.org/lkft/linux-stable-rc-4.9-oe/build/v4.9.132-36-gc26947f9eb18 No regressions (compared to build v4.9.132) Ran 20946 total tests in the following environments and test suites. Environments -- - dragonboard-410c - arm64 - hi6220-hikey - arm64 - i386 - juno-r2 - arm64 - qemu_arm - qemu_arm64 - qemu_i386 - qemu_x86_64 - x15 - arm - x86_64 Test Suites --- * boot * kselftest * libhugetlbfs * ltp-cap_bounds-tests * ltp-containers-tests * ltp-cve-tests * ltp-fcntl-locktests-tests * ltp-filecaps-tests * ltp-fs-tests * ltp-fs_bind-tests * ltp-fs_perms_simple-tests * ltp-fsx-tests * ltp-hugetlb-tests * ltp-io-tests * ltp-ipc-tests * ltp-math-tests * ltp-nptl-tests * ltp-pty-tests * ltp-sched-tests * ltp-securebits-tests * ltp-syscalls-tests * ltp-timers-tests * ltp-open-posix-tests * kselftest-vsyscall-mode-native * kselftest-vsyscall-mode-none -- Linaro LKFT https://lkft.linaro.org
Re: [PATCH 4.9 00/35] 4.9.133-stable review
On Thu, 11 Oct 2018 at 21:14, Greg Kroah-Hartman wrote: > > This is the start of the stable review cycle for the 4.9.133 release. > There are 35 patches in this series, all will be posted as a response > to this one. If anyone has any issues with these being applied, please > let me know. > > Responses should be made by Sat Oct 13 15:25:09 UTC 2018. > Anything received after that time might be too late. > > The whole patch series can be found in one patch at: > > https://www.kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.9.133-rc1.gz > or in the git tree and branch at: > > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git > linux-4.9.y > and the diffstat can be found below. > > thanks, > > greg k-h Results from Linaro’s test farm. No regressions on arm64, arm, x86_64, and i386. Summary kernel: 4.9.133-rc1 git repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git git branch: linux-4.9.y git commit: c26947f9eb18b1c3de2b4d76a981b0b468b390f2 git describe: v4.9.132-36-gc26947f9eb18 Test details: https://qa-reports.linaro.org/lkft/linux-stable-rc-4.9-oe/build/v4.9.132-36-gc26947f9eb18 No regressions (compared to build v4.9.132) Ran 20946 total tests in the following environments and test suites. Environments -- - dragonboard-410c - arm64 - hi6220-hikey - arm64 - i386 - juno-r2 - arm64 - qemu_arm - qemu_arm64 - qemu_i386 - qemu_x86_64 - x15 - arm - x86_64 Test Suites --- * boot * kselftest * libhugetlbfs * ltp-cap_bounds-tests * ltp-containers-tests * ltp-cve-tests * ltp-fcntl-locktests-tests * ltp-filecaps-tests * ltp-fs-tests * ltp-fs_bind-tests * ltp-fs_perms_simple-tests * ltp-fsx-tests * ltp-hugetlb-tests * ltp-io-tests * ltp-ipc-tests * ltp-math-tests * ltp-nptl-tests * ltp-pty-tests * ltp-sched-tests * ltp-securebits-tests * ltp-syscalls-tests * ltp-timers-tests * ltp-open-posix-tests * kselftest-vsyscall-mode-native * kselftest-vsyscall-mode-none -- Linaro LKFT https://lkft.linaro.org
Re: [PATCH 4.14 00/45] 4.14.76-stable review
On Thu, 11 Oct 2018 at 21:16, Greg Kroah-Hartman wrote: > > This is the start of the stable review cycle for the 4.14.76 release. > There are 45 patches in this series, all will be posted as a response > to this one. If anyone has any issues with these being applied, please > let me know. > > Responses should be made by Sat Oct 13 15:24:53 UTC 2018. > Anything received after that time might be too late. > > The whole patch series can be found in one patch at: > > https://www.kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.14.76-rc1.gz > or in the git tree and branch at: > > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git > linux-4.14.y > and the diffstat can be found below. > > thanks, > > greg k-h > Results from Linaro’s test farm. No regressions on arm64, arm, x86_64, and i386. Summary kernel: 4.14.76-rc1 git repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git git branch: linux-4.14.y git commit: c0c2a4359275ed099acb465f0c929abd22647d64 git describe: v4.14.75-46-gc0c2a4359275 Test details: https://qa-reports.linaro.org/lkft/linux-stable-rc-4.14-oe/build/v4.14.75-46-gc0c2a4359275 No regressions (compared to build v4.14.75) No fixes (compared to build v4.14.75) Ran 18438 total tests in the following environments and test suites. Environments -- - dragonboard-410c - arm64 - hi6220-hikey - arm64 - i386 - juno-r2 - arm64 - qemu_arm - qemu_arm64 - qemu_i386 - qemu_x86_64 - x15 - arm - x86_64 Test Suites --- * boot * kselftest * libhugetlbfs * ltp-cap_bounds-tests * ltp-containers-tests * ltp-cve-tests * ltp-fcntl-locktests-tests * ltp-filecaps-tests * ltp-fs-tests * ltp-fs_bind-tests * ltp-fs_perms_simple-tests * ltp-fsx-tests * ltp-hugetlb-tests * ltp-io-tests * ltp-ipc-tests * ltp-math-tests * ltp-nptl-tests * ltp-pty-tests * ltp-sched-tests * ltp-securebits-tests * ltp-syscalls-tests * ltp-timers-tests * ltp-open-posix-tests * kselftest-vsyscall-mode-native * kselftest-vsyscall-mode-none -- Linaro LKFT https://lkft.linaro.org
Re: [PATCH 4.14 00/45] 4.14.76-stable review
On Thu, 11 Oct 2018 at 21:16, Greg Kroah-Hartman wrote: > > This is the start of the stable review cycle for the 4.14.76 release. > There are 45 patches in this series, all will be posted as a response > to this one. If anyone has any issues with these being applied, please > let me know. > > Responses should be made by Sat Oct 13 15:24:53 UTC 2018. > Anything received after that time might be too late. > > The whole patch series can be found in one patch at: > > https://www.kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.14.76-rc1.gz > or in the git tree and branch at: > > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git > linux-4.14.y > and the diffstat can be found below. > > thanks, > > greg k-h > Results from Linaro’s test farm. No regressions on arm64, arm, x86_64, and i386. Summary kernel: 4.14.76-rc1 git repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git git branch: linux-4.14.y git commit: c0c2a4359275ed099acb465f0c929abd22647d64 git describe: v4.14.75-46-gc0c2a4359275 Test details: https://qa-reports.linaro.org/lkft/linux-stable-rc-4.14-oe/build/v4.14.75-46-gc0c2a4359275 No regressions (compared to build v4.14.75) No fixes (compared to build v4.14.75) Ran 18438 total tests in the following environments and test suites. Environments -- - dragonboard-410c - arm64 - hi6220-hikey - arm64 - i386 - juno-r2 - arm64 - qemu_arm - qemu_arm64 - qemu_i386 - qemu_x86_64 - x15 - arm - x86_64 Test Suites --- * boot * kselftest * libhugetlbfs * ltp-cap_bounds-tests * ltp-containers-tests * ltp-cve-tests * ltp-fcntl-locktests-tests * ltp-filecaps-tests * ltp-fs-tests * ltp-fs_bind-tests * ltp-fs_perms_simple-tests * ltp-fsx-tests * ltp-hugetlb-tests * ltp-io-tests * ltp-ipc-tests * ltp-math-tests * ltp-nptl-tests * ltp-pty-tests * ltp-sched-tests * ltp-securebits-tests * ltp-syscalls-tests * ltp-timers-tests * ltp-open-posix-tests * kselftest-vsyscall-mode-native * kselftest-vsyscall-mode-none -- Linaro LKFT https://lkft.linaro.org
[PATCH v2 2/2] dt-bindings: uniphier: move cache-uniphier.txt to vendor directory
Now, the Socionext vendor directory is available at
Documentation/devicetree/bindings/arm/socionext/
Move cache-uniphier.txt over to it.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- New patch
.../devicetree/bindings/arm/{uniphier => socionext}/cache-uniphier.txt| 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/arm/{uniphier =>
socionext}/cache-uniphier.txt (100%)
diff --git a/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt
b/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt
rename to Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt
--
2.7.4
[PATCH v2 1/2] dt-bindings: uniphier: add bindings for UniPhier SoC family
Document the list of SoCs and boards of UniPhier platform.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
Changes suggested by Rob.
- Move the file to
Documentation/devicetree/bindings/arm/socionext/uniphier.txt
- Group boards by each SoC
Previous posts:
v1: https://patchwork.ozlabs.org/patch/842010/
.../devicetree/bindings/arm/socionext/uniphier.txt | 47 ++
MAINTAINERS| 1 +
2 files changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/socionext/uniphier.txt
diff --git a/Documentation/devicetree/bindings/arm/socionext/uniphier.txt
b/Documentation/devicetree/bindings/arm/socionext/uniphier.txt
new file mode 100644
index 000..dafc466
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/socionext/uniphier.txt
@@ -0,0 +1,47 @@
+Socionext UniPhier SoC family
+-
+
+Required properties in the root node:
+ - compatible: should contain board and SoC compatible strings
+
+SoC and board compatible strings:
+ (sorted chronologically)
+
+ - LD4 SoC: "socionext,uniphier-ld4"
+ - Reference board: "socionext,uniphier-ld4-ref"
+
+ - Pro4 SoC: "socionext,uniphier-pro4"
+ - Reference Board: "socionext,uniphier-pro4-ref"
+ - Ace Board: "socionext,uniphier-pro4-ace"
+ - Sanji Board: "socionext,uniphier-pro4-sanji"
+
+ - sLD8 SoC: "socionext,uniphier-sld8"
+ - Reference Board: "socionext,uniphier-sld8-ref"
+
+ - PXs2 SoC: "socionext,uniphier-pxs2"
+ - Gentil Board:"socionext,uniphier-pxs2-gentil"
+ - Vodka Board: "socionext,uniphier-pxs2-vodka"
+
+ - LD6b SoC: "socionext,uniphier-ld6b"
+ - Reference Board: "socionext,uniphier-ld6b-ref"
+
+ - LD11 SoC: "socionext,uniphier-ld11"
+ - Reference Board: "socionext,uniphier-ld11-ref"
+ - Global Board:"socionext,uniphier-ld11-global"
+
+ - LD20 SoC: "socionext,uniphier-ld20"
+ - Reference Board: "socionext,uniphier-ld20-ref"
+ - Global Board:"socionext,uniphier-ld20-global"
+
+ - PXs3 SoC: "socionext,uniphier-pxs3"
+ - Reference Board: "socionext,uniphier-pxs3-ref"
+
+Example:
+
+/dts-v1/;
+
+/ {
+ compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
+
+ ...
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index a5c951c..c0c2abb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2183,6 +2183,7 @@ M:Masahiro Yamada
L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
T: git
git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git
S: Maintained
+F: Documentation/devicetree/bindings/arm/socionext/uniphier.txt
F: Documentation/devicetree/bindings/gpio/gpio-uniphier.txt
F: Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt
F: arch/arm/boot/dts/uniphier*
--
2.7.4
[PATCH v2 2/2] dt-bindings: uniphier: move cache-uniphier.txt to vendor directory
Now, the Socionext vendor directory is available at
Documentation/devicetree/bindings/arm/socionext/
Move cache-uniphier.txt over to it.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
- New patch
.../devicetree/bindings/arm/{uniphier => socionext}/cache-uniphier.txt| 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/arm/{uniphier =>
socionext}/cache-uniphier.txt (100%)
diff --git a/Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt
b/Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt
rename to Documentation/devicetree/bindings/arm/socionext/cache-uniphier.txt
--
2.7.4
[PATCH v2 1/2] dt-bindings: uniphier: add bindings for UniPhier SoC family
Document the list of SoCs and boards of UniPhier platform.
Signed-off-by: Masahiro Yamada
---
Changes in v2:
Changes suggested by Rob.
- Move the file to
Documentation/devicetree/bindings/arm/socionext/uniphier.txt
- Group boards by each SoC
Previous posts:
v1: https://patchwork.ozlabs.org/patch/842010/
.../devicetree/bindings/arm/socionext/uniphier.txt | 47 ++
MAINTAINERS| 1 +
2 files changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/socionext/uniphier.txt
diff --git a/Documentation/devicetree/bindings/arm/socionext/uniphier.txt
b/Documentation/devicetree/bindings/arm/socionext/uniphier.txt
new file mode 100644
index 000..dafc466
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/socionext/uniphier.txt
@@ -0,0 +1,47 @@
+Socionext UniPhier SoC family
+-
+
+Required properties in the root node:
+ - compatible: should contain board and SoC compatible strings
+
+SoC and board compatible strings:
+ (sorted chronologically)
+
+ - LD4 SoC: "socionext,uniphier-ld4"
+ - Reference board: "socionext,uniphier-ld4-ref"
+
+ - Pro4 SoC: "socionext,uniphier-pro4"
+ - Reference Board: "socionext,uniphier-pro4-ref"
+ - Ace Board: "socionext,uniphier-pro4-ace"
+ - Sanji Board: "socionext,uniphier-pro4-sanji"
+
+ - sLD8 SoC: "socionext,uniphier-sld8"
+ - Reference Board: "socionext,uniphier-sld8-ref"
+
+ - PXs2 SoC: "socionext,uniphier-pxs2"
+ - Gentil Board:"socionext,uniphier-pxs2-gentil"
+ - Vodka Board: "socionext,uniphier-pxs2-vodka"
+
+ - LD6b SoC: "socionext,uniphier-ld6b"
+ - Reference Board: "socionext,uniphier-ld6b-ref"
+
+ - LD11 SoC: "socionext,uniphier-ld11"
+ - Reference Board: "socionext,uniphier-ld11-ref"
+ - Global Board:"socionext,uniphier-ld11-global"
+
+ - LD20 SoC: "socionext,uniphier-ld20"
+ - Reference Board: "socionext,uniphier-ld20-ref"
+ - Global Board:"socionext,uniphier-ld20-global"
+
+ - PXs3 SoC: "socionext,uniphier-pxs3"
+ - Reference Board: "socionext,uniphier-pxs3-ref"
+
+Example:
+
+/dts-v1/;
+
+/ {
+ compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
+
+ ...
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index a5c951c..c0c2abb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2183,6 +2183,7 @@ M:Masahiro Yamada
L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
T: git
git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier.git
S: Maintained
+F: Documentation/devicetree/bindings/arm/socionext/uniphier.txt
F: Documentation/devicetree/bindings/gpio/gpio-uniphier.txt
F: Documentation/devicetree/bindings/pinctrl/socionext,uniphier-pinctrl.txt
F: arch/arm/boot/dts/uniphier*
--
2.7.4
Re: [PATCH 4.18 00/44] 4.18.14-stable review
On Thu, 11 Oct 2018 at 21:18, Greg Kroah-Hartman wrote: > > This is the start of the stable review cycle for the 4.18.14 release. > There are 44 patches in this series, all will be posted as a response > to this one. If anyone has any issues with these being applied, please > let me know. > > Responses should be made by Sat Oct 13 15:24:36 UTC 2018. > Anything received after that time might be too late. > > The whole patch series can be found in one patch at: > > https://www.kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.18.14-rc1.gz > or in the git tree and branch at: > > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git > linux-4.18.y > and the diffstat can be found below. > > thanks, > > greg k-h > Results from Linaro’s test farm. No regressions on arm64, arm, x86_64, and i386. Summary kernel: 4.18.14-rc1 git repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git git branch: linux-4.18.y git commit: 32f54e007e34d795186f0073a5f9f7eafb7a1cf2 git describe: v4.18.13-45-g32f54e007e34 Test details: https://qa-reports.linaro.org/lkft/linux-stable-rc-4.18-oe/build/v4.18.13-45-g32f54e007e34 No regressions (compared to build v4.18.13) No fixes (compared to build v4.18.13) Ran 21191 total tests in the following environments and test suites. Environments -- - dragonboard-410c - arm64 - hi6220-hikey - arm64 - i386 - juno-r2 - arm64 - qemu_arm - qemu_arm64 - qemu_i386 - qemu_x86_64 - x15 - arm - x86_64 Test Suites --- * boot * kselftest * libhugetlbfs * ltp-cap_bounds-tests * ltp-containers-tests * ltp-cve-tests * ltp-fcntl-locktests-tests * ltp-filecaps-tests * ltp-fs-tests * ltp-fs_bind-tests * ltp-fs_perms_simple-tests * ltp-fsx-tests * ltp-hugetlb-tests * ltp-io-tests * ltp-ipc-tests * ltp-math-tests * ltp-nptl-tests * ltp-pty-tests * ltp-sched-tests * ltp-securebits-tests * ltp-syscalls-tests * ltp-timers-tests * ltp-open-posix-tests * kselftest-vsyscall-mode-native * kselftest-vsyscall-mode-none -- Linaro LKFT https://lkft.linaro.org
Re: [PATCH 4.18 00/44] 4.18.14-stable review
On Thu, 11 Oct 2018 at 21:18, Greg Kroah-Hartman wrote: > > This is the start of the stable review cycle for the 4.18.14 release. > There are 44 patches in this series, all will be posted as a response > to this one. If anyone has any issues with these being applied, please > let me know. > > Responses should be made by Sat Oct 13 15:24:36 UTC 2018. > Anything received after that time might be too late. > > The whole patch series can be found in one patch at: > > https://www.kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.18.14-rc1.gz > or in the git tree and branch at: > > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git > linux-4.18.y > and the diffstat can be found below. > > thanks, > > greg k-h > Results from Linaro’s test farm. No regressions on arm64, arm, x86_64, and i386. Summary kernel: 4.18.14-rc1 git repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git git branch: linux-4.18.y git commit: 32f54e007e34d795186f0073a5f9f7eafb7a1cf2 git describe: v4.18.13-45-g32f54e007e34 Test details: https://qa-reports.linaro.org/lkft/linux-stable-rc-4.18-oe/build/v4.18.13-45-g32f54e007e34 No regressions (compared to build v4.18.13) No fixes (compared to build v4.18.13) Ran 21191 total tests in the following environments and test suites. Environments -- - dragonboard-410c - arm64 - hi6220-hikey - arm64 - i386 - juno-r2 - arm64 - qemu_arm - qemu_arm64 - qemu_i386 - qemu_x86_64 - x15 - arm - x86_64 Test Suites --- * boot * kselftest * libhugetlbfs * ltp-cap_bounds-tests * ltp-containers-tests * ltp-cve-tests * ltp-fcntl-locktests-tests * ltp-filecaps-tests * ltp-fs-tests * ltp-fs_bind-tests * ltp-fs_perms_simple-tests * ltp-fsx-tests * ltp-hugetlb-tests * ltp-io-tests * ltp-ipc-tests * ltp-math-tests * ltp-nptl-tests * ltp-pty-tests * ltp-sched-tests * ltp-securebits-tests * ltp-syscalls-tests * ltp-timers-tests * ltp-open-posix-tests * kselftest-vsyscall-mode-native * kselftest-vsyscall-mode-none -- Linaro LKFT https://lkft.linaro.org
[PATCH V2 4/5] arm64/mm: Enable HugeTLB migration
Let arm64 subscribe to generic HugeTLB page migration framework. Right now this only works on the following PMD and PUD level HugeTLB page sizes with various kernel base page size combinations. CONT PTEPMDCONT PMDPUD ------ 4K: NA 2M NA 1G 16K:NA32M NA 64K:NA 512M NA Signed-off-by: Anshuman Khandual --- arch/arm64/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 1b1a0e9..e54350f 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1305,6 +1305,10 @@ config SYSVIPC_COMPAT def_bool y depends on COMPAT && SYSVIPC +config ARCH_ENABLE_HUGEPAGE_MIGRATION + def_bool y + depends on HUGETLB_PAGE && MIGRATION + menu "Power management options" source "kernel/power/Kconfig" -- 2.7.4
[PATCH V2 2/5] mm/hugetlb: Distinguish between migratability and movability
During huge page allocation it's migratability is checked to determine if
it should be placed under movable zones with GFP_HIGHUSER_MOVABLE. But the
movability aspect of the huge page could depend on other factors than just
migratability. Movability in itself is a distinct property which should not
be tied with migratability alone.
This differentiates these two and implements an enhanced movability check
which also considers huge page size to determine if it is feasible to be
placed under a movable zone. At present it just checks for gigantic pages
but going forward it can incorporate other enhanced checks.
Suggested-by: Michal Hocko
Signed-off-by: Anshuman Khandual
---
include/linux/hugetlb.h | 30 ++
mm/hugetlb.c| 2 +-
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index 9c1b77f..456cb60 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -493,6 +493,31 @@ static inline bool hugepage_migration_supported(struct
hstate *h)
#endif
}
+/*
+ * Movability check is different as compared to migration check.
+ * It determines whether or not a huge page should be placed on
+ * movable zone or not. Movability of any huge page should be
+ * required only if huge page size is supported for migration.
+ * There wont be any reason for the huge page to be movable if
+ * it is not migratable to start with. Also the size of the huge
+ * page should be large enough to be placed under a movable zone
+ * and still feasible enough to be migratable. Just the presence
+ * in movable zone does not make the migration feasible.
+ *
+ * So even though large huge page sizes like the gigantic ones
+ * are migratable they should not be movable because its not
+ * feasible to migrate them from movable zone.
+ */
+static inline bool hugepage_movable_supported(struct hstate *h)
+{
+ if (!hugepage_migration_supported(h))
+ return false;
+
+ if (hstate_is_gigantic(h))
+ return false;
+ return true;
+}
+
static inline spinlock_t *huge_pte_lockptr(struct hstate *h,
struct mm_struct *mm, pte_t *pte)
{
@@ -589,6 +614,11 @@ static inline bool hugepage_migration_supported(struct
hstate *h)
return false;
}
+static inline bool hugepage_movable_supported(struct hstate *h)
+{
+ return false;
+}
+
static inline spinlock_t *huge_pte_lockptr(struct hstate *h,
struct mm_struct *mm, pte_t *pte)
{
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index 3c21775..a5a111d 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -919,7 +919,7 @@ static struct page *dequeue_huge_page_nodemask(struct
hstate *h, gfp_t gfp_mask,
/* Movability of hugepages depends on migration support. */
static inline gfp_t htlb_alloc_mask(struct hstate *h)
{
- if (hugepage_migration_supported(h))
+ if (hugepage_movable_supported(h))
return GFP_HIGHUSER_MOVABLE;
else
return GFP_HIGHUSER;
--
2.7.4
[PATCH V2 3/5] mm/hugetlb: Enable arch specific huge page size support for migration
Architectures like arm64 have HugeTLB page sizes which are different than
generic sizes at PMD, PUD, PGD level and implemented via contiguous bits.
At present these special size HugeTLB pages cannot be identified through
macros like (PMD|PUD|PGDIR)_SHIFT and hence chosen not be migrated.
Enabling migration support for these special HugeTLB page sizes along with
the generic ones (PMD|PUD|PGD) would require identifying all of them on a
given platform. A platform specific hook can precisely enumerate all huge
page sizes supported for migration. Instead of comparing against standard
huge page orders let hugetlb_migration_support() function call a platform
hook arch_hugetlb_migration_support(). Default definition for the platform
hook maintains existing semantics which checks standard huge page order.
But an architecture can choose to override the default and provide support
for a comprehensive set of huge page sizes.
Signed-off-by: Anshuman Khandual
---
include/linux/hugetlb.h | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index 456cb60..97a2fdb 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -479,18 +479,29 @@ static inline pgoff_t basepage_index(struct page *page)
extern int dissolve_free_huge_page(struct page *page);
extern int dissolve_free_huge_pages(unsigned long start_pfn,
unsigned long end_pfn);
-static inline bool hugepage_migration_supported(struct hstate *h)
-{
+
#ifdef CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION
+#ifndef arch_hugetlb_migration_supported
+static inline bool arch_hugetlb_migration_supported(struct hstate *h)
+{
if ((huge_page_shift(h) == PMD_SHIFT) ||
(huge_page_shift(h) == PUD_SHIFT) ||
(huge_page_shift(h) == PGDIR_SHIFT))
return true;
else
return false;
+}
+#endif
#else
+static inline bool arch_hugetlb_migration_supported(struct hstate *h)
+{
return false;
+}
#endif
+
+static inline bool hugepage_migration_supported(struct hstate *h)
+{
+ return arch_hugetlb_migration_supported(h);
}
/*
--
2.7.4
[PATCH V2 5/5] arm64/mm: Enable HugeTLB migration for contiguous bit HugeTLB pages
Let arm64 subscribe to the previously added framework in which architecture
can inform whether a given huge page size is supported for migration. This
just overrides the default function arch_hugetlb_migration_supported() and
enables migration for all possible HugeTLB page sizes on arm64. With this,
HugeTLB migration support on arm64 now covers all possible HugeTLB options.
CONT PTEPMDCONT PMDPUD
------
4K:64K 2M32M 1G
16K:2M 32M 1G
64K:2M512M16G
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/hugetlb.h | 5 +
arch/arm64/mm/hugetlbpage.c | 20
2 files changed, 25 insertions(+)
diff --git a/arch/arm64/include/asm/hugetlb.h b/arch/arm64/include/asm/hugetlb.h
index e73f685..656f70e 100644
--- a/arch/arm64/include/asm/hugetlb.h
+++ b/arch/arm64/include/asm/hugetlb.h
@@ -20,6 +20,11 @@
#include
+#ifdef CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION
+#define arch_hugetlb_migration_supported arch_hugetlb_migration_supported
+extern bool arch_hugetlb_migration_supported(struct hstate *h);
+#endif
+
static inline pte_t huge_ptep_get(pte_t *ptep)
{
return READ_ONCE(*ptep);
diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
index 4eafd9f..28f4795 100644
--- a/arch/arm64/mm/hugetlbpage.c
+++ b/arch/arm64/mm/hugetlbpage.c
@@ -27,6 +27,26 @@
#include
#include
+#ifdef CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION
+bool arch_hugetlb_migration_supported(struct hstate *h)
+{
+ size_t pagesize = huge_page_size(h);
+
+ switch (pagesize) {
+#ifdef CONFIG_ARM64_4K_PAGES
+ case PUD_SIZE:
+#endif
+ case PMD_SIZE:
+ case CONT_PMD_SIZE:
+ case CONT_PTE_SIZE:
+ return true;
+ }
+ pr_warn("%s: unrecognized huge page size 0x%lx\n",
+ __func__, pagesize);
+ return false;
+}
+#endif
+
int pmd_huge(pmd_t pmd)
{
return pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
--
2.7.4
[PATCH V2 4/5] arm64/mm: Enable HugeTLB migration
Let arm64 subscribe to generic HugeTLB page migration framework. Right now this only works on the following PMD and PUD level HugeTLB page sizes with various kernel base page size combinations. CONT PTEPMDCONT PMDPUD ------ 4K: NA 2M NA 1G 16K:NA32M NA 64K:NA 512M NA Signed-off-by: Anshuman Khandual --- arch/arm64/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 1b1a0e9..e54350f 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1305,6 +1305,10 @@ config SYSVIPC_COMPAT def_bool y depends on COMPAT && SYSVIPC +config ARCH_ENABLE_HUGEPAGE_MIGRATION + def_bool y + depends on HUGETLB_PAGE && MIGRATION + menu "Power management options" source "kernel/power/Kconfig" -- 2.7.4
[PATCH V2 2/5] mm/hugetlb: Distinguish between migratability and movability
During huge page allocation it's migratability is checked to determine if
it should be placed under movable zones with GFP_HIGHUSER_MOVABLE. But the
movability aspect of the huge page could depend on other factors than just
migratability. Movability in itself is a distinct property which should not
be tied with migratability alone.
This differentiates these two and implements an enhanced movability check
which also considers huge page size to determine if it is feasible to be
placed under a movable zone. At present it just checks for gigantic pages
but going forward it can incorporate other enhanced checks.
Suggested-by: Michal Hocko
Signed-off-by: Anshuman Khandual
---
include/linux/hugetlb.h | 30 ++
mm/hugetlb.c| 2 +-
2 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index 9c1b77f..456cb60 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -493,6 +493,31 @@ static inline bool hugepage_migration_supported(struct
hstate *h)
#endif
}
+/*
+ * Movability check is different as compared to migration check.
+ * It determines whether or not a huge page should be placed on
+ * movable zone or not. Movability of any huge page should be
+ * required only if huge page size is supported for migration.
+ * There wont be any reason for the huge page to be movable if
+ * it is not migratable to start with. Also the size of the huge
+ * page should be large enough to be placed under a movable zone
+ * and still feasible enough to be migratable. Just the presence
+ * in movable zone does not make the migration feasible.
+ *
+ * So even though large huge page sizes like the gigantic ones
+ * are migratable they should not be movable because its not
+ * feasible to migrate them from movable zone.
+ */
+static inline bool hugepage_movable_supported(struct hstate *h)
+{
+ if (!hugepage_migration_supported(h))
+ return false;
+
+ if (hstate_is_gigantic(h))
+ return false;
+ return true;
+}
+
static inline spinlock_t *huge_pte_lockptr(struct hstate *h,
struct mm_struct *mm, pte_t *pte)
{
@@ -589,6 +614,11 @@ static inline bool hugepage_migration_supported(struct
hstate *h)
return false;
}
+static inline bool hugepage_movable_supported(struct hstate *h)
+{
+ return false;
+}
+
static inline spinlock_t *huge_pte_lockptr(struct hstate *h,
struct mm_struct *mm, pte_t *pte)
{
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index 3c21775..a5a111d 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -919,7 +919,7 @@ static struct page *dequeue_huge_page_nodemask(struct
hstate *h, gfp_t gfp_mask,
/* Movability of hugepages depends on migration support. */
static inline gfp_t htlb_alloc_mask(struct hstate *h)
{
- if (hugepage_migration_supported(h))
+ if (hugepage_movable_supported(h))
return GFP_HIGHUSER_MOVABLE;
else
return GFP_HIGHUSER;
--
2.7.4
[PATCH V2 3/5] mm/hugetlb: Enable arch specific huge page size support for migration
Architectures like arm64 have HugeTLB page sizes which are different than
generic sizes at PMD, PUD, PGD level and implemented via contiguous bits.
At present these special size HugeTLB pages cannot be identified through
macros like (PMD|PUD|PGDIR)_SHIFT and hence chosen not be migrated.
Enabling migration support for these special HugeTLB page sizes along with
the generic ones (PMD|PUD|PGD) would require identifying all of them on a
given platform. A platform specific hook can precisely enumerate all huge
page sizes supported for migration. Instead of comparing against standard
huge page orders let hugetlb_migration_support() function call a platform
hook arch_hugetlb_migration_support(). Default definition for the platform
hook maintains existing semantics which checks standard huge page order.
But an architecture can choose to override the default and provide support
for a comprehensive set of huge page sizes.
Signed-off-by: Anshuman Khandual
---
include/linux/hugetlb.h | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index 456cb60..97a2fdb 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -479,18 +479,29 @@ static inline pgoff_t basepage_index(struct page *page)
extern int dissolve_free_huge_page(struct page *page);
extern int dissolve_free_huge_pages(unsigned long start_pfn,
unsigned long end_pfn);
-static inline bool hugepage_migration_supported(struct hstate *h)
-{
+
#ifdef CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION
+#ifndef arch_hugetlb_migration_supported
+static inline bool arch_hugetlb_migration_supported(struct hstate *h)
+{
if ((huge_page_shift(h) == PMD_SHIFT) ||
(huge_page_shift(h) == PUD_SHIFT) ||
(huge_page_shift(h) == PGDIR_SHIFT))
return true;
else
return false;
+}
+#endif
#else
+static inline bool arch_hugetlb_migration_supported(struct hstate *h)
+{
return false;
+}
#endif
+
+static inline bool hugepage_migration_supported(struct hstate *h)
+{
+ return arch_hugetlb_migration_supported(h);
}
/*
--
2.7.4
[PATCH V2 5/5] arm64/mm: Enable HugeTLB migration for contiguous bit HugeTLB pages
Let arm64 subscribe to the previously added framework in which architecture
can inform whether a given huge page size is supported for migration. This
just overrides the default function arch_hugetlb_migration_supported() and
enables migration for all possible HugeTLB page sizes on arm64. With this,
HugeTLB migration support on arm64 now covers all possible HugeTLB options.
CONT PTEPMDCONT PMDPUD
------
4K:64K 2M32M 1G
16K:2M 32M 1G
64K:2M512M16G
Signed-off-by: Anshuman Khandual
---
arch/arm64/include/asm/hugetlb.h | 5 +
arch/arm64/mm/hugetlbpage.c | 20
2 files changed, 25 insertions(+)
diff --git a/arch/arm64/include/asm/hugetlb.h b/arch/arm64/include/asm/hugetlb.h
index e73f685..656f70e 100644
--- a/arch/arm64/include/asm/hugetlb.h
+++ b/arch/arm64/include/asm/hugetlb.h
@@ -20,6 +20,11 @@
#include
+#ifdef CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION
+#define arch_hugetlb_migration_supported arch_hugetlb_migration_supported
+extern bool arch_hugetlb_migration_supported(struct hstate *h);
+#endif
+
static inline pte_t huge_ptep_get(pte_t *ptep)
{
return READ_ONCE(*ptep);
diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
index 4eafd9f..28f4795 100644
--- a/arch/arm64/mm/hugetlbpage.c
+++ b/arch/arm64/mm/hugetlbpage.c
@@ -27,6 +27,26 @@
#include
#include
+#ifdef CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION
+bool arch_hugetlb_migration_supported(struct hstate *h)
+{
+ size_t pagesize = huge_page_size(h);
+
+ switch (pagesize) {
+#ifdef CONFIG_ARM64_4K_PAGES
+ case PUD_SIZE:
+#endif
+ case PMD_SIZE:
+ case CONT_PMD_SIZE:
+ case CONT_PTE_SIZE:
+ return true;
+ }
+ pr_warn("%s: unrecognized huge page size 0x%lx\n",
+ __func__, pagesize);
+ return false;
+}
+#endif
+
int pmd_huge(pmd_t pmd)
{
return pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
--
2.7.4
[PATCH V2 0/5] arm64/mm: Enable HugeTLB migration
This patch series enables HugeTLB migration support for all supported huge page sizes at all levels including contiguous bit implementation. Following HugeTLB migration support matrix has been enabled with this patch series. All permutations have been tested except for the 16GB. CONT PTEPMDCONT PMDPUD ------ 4K: 64K 2M 32M 1G 16K: 2M32M 1G 64K: 2M 512M 16G First the series adds migration support for PUD based huge pages. It then adds a platform specific hook to query an architecture if a given huge page size is supported for migration while also providing a default fallback option preserving the existing semantics which just checks for (PMD|PUD|PGDIR)_SHIFT macros. The last two patches enables HugeTLB migration on arm64 and subscribe to this new platform specific hook by defining an override. The second patch differentiates between movability and migratability aspects of huge pages and implements hugepage_movable_supported() which can then be used during allocation to decide whether to place the huge page in movable zone or not. Changes in V2: - Added a new patch which differentiates migratability and movability of huge pages and implements hugepage_movable_supported() function as suggested by Michal Hocko. Anshuman Khandual (5): mm/hugetlb: Enable PUD level huge page migration mm/hugetlb: Distinguish between migratability and movability mm/hugetlb: Enable arch specific huge page size support for migration arm64/mm: Enable HugeTLB migration arm64/mm: Enable HugeTLB migration for contiguous bit HugeTLB pages arch/arm64/Kconfig | 4 arch/arm64/include/asm/hugetlb.h | 5 + arch/arm64/mm/hugetlbpage.c | 20 + include/linux/hugetlb.h | 48 +--- mm/hugetlb.c | 2 +- 5 files changed, 75 insertions(+), 4 deletions(-) -- 2.7.4
[PATCH V2 0/5] arm64/mm: Enable HugeTLB migration
This patch series enables HugeTLB migration support for all supported huge page sizes at all levels including contiguous bit implementation. Following HugeTLB migration support matrix has been enabled with this patch series. All permutations have been tested except for the 16GB. CONT PTEPMDCONT PMDPUD ------ 4K: 64K 2M 32M 1G 16K: 2M32M 1G 64K: 2M 512M 16G First the series adds migration support for PUD based huge pages. It then adds a platform specific hook to query an architecture if a given huge page size is supported for migration while also providing a default fallback option preserving the existing semantics which just checks for (PMD|PUD|PGDIR)_SHIFT macros. The last two patches enables HugeTLB migration on arm64 and subscribe to this new platform specific hook by defining an override. The second patch differentiates between movability and migratability aspects of huge pages and implements hugepage_movable_supported() which can then be used during allocation to decide whether to place the huge page in movable zone or not. Changes in V2: - Added a new patch which differentiates migratability and movability of huge pages and implements hugepage_movable_supported() function as suggested by Michal Hocko. Anshuman Khandual (5): mm/hugetlb: Enable PUD level huge page migration mm/hugetlb: Distinguish between migratability and movability mm/hugetlb: Enable arch specific huge page size support for migration arm64/mm: Enable HugeTLB migration arm64/mm: Enable HugeTLB migration for contiguous bit HugeTLB pages arch/arm64/Kconfig | 4 arch/arm64/include/asm/hugetlb.h | 5 + arch/arm64/mm/hugetlbpage.c | 20 + include/linux/hugetlb.h | 48 +--- mm/hugetlb.c | 2 +- 5 files changed, 75 insertions(+), 4 deletions(-) -- 2.7.4
[PATCH V2 1/5] mm/hugetlb: Enable PUD level huge page migration
Architectures like arm64 have PUD level HugeTLB pages for certain configs
(1GB huge page is PUD based on ARM64_4K_PAGES base page size) that can be
enabled for migration. It can be achieved through checking for PUD_SHIFT
order based HugeTLB pages during migration.
Signed-off-by: Anshuman Khandual
---
include/linux/hugetlb.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index 6b68e34..9c1b77f 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -483,7 +483,8 @@ static inline bool hugepage_migration_supported(struct
hstate *h)
{
#ifdef CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION
if ((huge_page_shift(h) == PMD_SHIFT) ||
- (huge_page_shift(h) == PGDIR_SHIFT))
+ (huge_page_shift(h) == PUD_SHIFT) ||
+ (huge_page_shift(h) == PGDIR_SHIFT))
return true;
else
return false;
--
2.7.4
[PATCH V2 1/5] mm/hugetlb: Enable PUD level huge page migration
Architectures like arm64 have PUD level HugeTLB pages for certain configs
(1GB huge page is PUD based on ARM64_4K_PAGES base page size) that can be
enabled for migration. It can be achieved through checking for PUD_SHIFT
order based HugeTLB pages during migration.
Signed-off-by: Anshuman Khandual
---
include/linux/hugetlb.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index 6b68e34..9c1b77f 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -483,7 +483,8 @@ static inline bool hugepage_migration_supported(struct
hstate *h)
{
#ifdef CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION
if ((huge_page_shift(h) == PMD_SHIFT) ||
- (huge_page_shift(h) == PGDIR_SHIFT))
+ (huge_page_shift(h) == PUD_SHIFT) ||
+ (huge_page_shift(h) == PGDIR_SHIFT))
return true;
else
return false;
--
2.7.4
Re: [PATCH v4 2/3] mm: introduce put_user_page*(), placeholder versions
On 10/11/18 6:23 PM, John Hubbard wrote: > On 10/11/18 6:20 AM, Jason Gunthorpe wrote: >> On Thu, Oct 11, 2018 at 10:49:29AM +0200, Jan Kara wrote: >> This is a real worry. If someone uses a mistaken put_page() then how will that bug manifest at runtime? Under what set of circumstances will the kernel trigger the bug? >>> >>> At runtime such bug will manifest as a page that can never be evicted from >>> memory. We could warn in put_page() if page reference count drops below >>> bare minimum for given user pin count which would be able to catch some >>> issues but it won't be 100% reliable. So at this point I'm more leaning >>> towards making get_user_pages() return a different type than just >>> struct page * to make it much harder for refcount to go wrong... >> >> At least for the infiniband code being used as an example here we take >> the struct page from get_user_pages, then stick it in a sgl, and at >> put_page time we get the page back out of the sgl via sg_page() >> >> So type safety will not help this case... I wonder how many other >> users are similar? I think this is a pretty reasonable flow for DMA >> with user pages. >> > > That is true. The infiniband code, fortunately, never mixes the two page > types into the same pool (or sg list), so it's actually an easier example > than some other subsystems. But, yes, type safety doesn't help there. I can > take a moment to look around at the other areas, to quantify how much a type > safety change might help. > > Back to page flags again, out of desperation: > > How much do we know about the page types that all of these subsystems > use? In other words, can we, for example, use bit 1 of page->lru.next (see [1] > for context) as the "dma-pinned" page flag, while tracking pages within parts > of the kernel that call a mix of alloc_pages, get_user_pages, and other > allocators? > In order for that to work, page->index, page->private, and bit 1 of > page->mapping > must not be used. I doubt that this is always going to hold, but...does it? > Oops, pardon me, please ignore that nonsense about page->index and page->private and page->mapping, that's actually fine (I was seeing "union", where "struct" was written--too much staring at this code). So actually, I think maybe we can just use bit 1 in page->lru.next to sort out which pages are dma-pinned, in the calling code, just like we're going to do in writeback situations. This should also allow run-time checking that Andrew was hoping for: put_user_page(): assert that the page is dma-pinned put_page(): assert that the page is *not* dma-pinned ...both of which depend on that bit being, essentially, available as sort of a general page flag. And in fact, if it's not, then the whole approach is dead anyway. Am I missing anything? This avoids the need to change the get_user_pages interface. thanks, -- John Hubbard NVIDIA
Re: [PATCH v4 2/3] mm: introduce put_user_page*(), placeholder versions
On 10/11/18 6:23 PM, John Hubbard wrote: > On 10/11/18 6:20 AM, Jason Gunthorpe wrote: >> On Thu, Oct 11, 2018 at 10:49:29AM +0200, Jan Kara wrote: >> This is a real worry. If someone uses a mistaken put_page() then how will that bug manifest at runtime? Under what set of circumstances will the kernel trigger the bug? >>> >>> At runtime such bug will manifest as a page that can never be evicted from >>> memory. We could warn in put_page() if page reference count drops below >>> bare minimum for given user pin count which would be able to catch some >>> issues but it won't be 100% reliable. So at this point I'm more leaning >>> towards making get_user_pages() return a different type than just >>> struct page * to make it much harder for refcount to go wrong... >> >> At least for the infiniband code being used as an example here we take >> the struct page from get_user_pages, then stick it in a sgl, and at >> put_page time we get the page back out of the sgl via sg_page() >> >> So type safety will not help this case... I wonder how many other >> users are similar? I think this is a pretty reasonable flow for DMA >> with user pages. >> > > That is true. The infiniband code, fortunately, never mixes the two page > types into the same pool (or sg list), so it's actually an easier example > than some other subsystems. But, yes, type safety doesn't help there. I can > take a moment to look around at the other areas, to quantify how much a type > safety change might help. > > Back to page flags again, out of desperation: > > How much do we know about the page types that all of these subsystems > use? In other words, can we, for example, use bit 1 of page->lru.next (see [1] > for context) as the "dma-pinned" page flag, while tracking pages within parts > of the kernel that call a mix of alloc_pages, get_user_pages, and other > allocators? > In order for that to work, page->index, page->private, and bit 1 of > page->mapping > must not be used. I doubt that this is always going to hold, but...does it? > Oops, pardon me, please ignore that nonsense about page->index and page->private and page->mapping, that's actually fine (I was seeing "union", where "struct" was written--too much staring at this code). So actually, I think maybe we can just use bit 1 in page->lru.next to sort out which pages are dma-pinned, in the calling code, just like we're going to do in writeback situations. This should also allow run-time checking that Andrew was hoping for: put_user_page(): assert that the page is dma-pinned put_page(): assert that the page is *not* dma-pinned ...both of which depend on that bit being, essentially, available as sort of a general page flag. And in fact, if it's not, then the whole approach is dead anyway. Am I missing anything? This avoids the need to change the get_user_pages interface. thanks, -- John Hubbard NVIDIA
Re: [PATCH 0/4] Add clock support for Hi3670 SoC
On Thu, Sep 20, 2018 at 11:00:59PM -0700, Manivannan Sadhasivam wrote: > This patchset adds clock support for Hi3670 SoC from HiSilicon utilizing > the HiSi common clock code. While adding clock support, let's remove the > fixed clock for UART and source SoC clock on HiKey970 board. > > This patchset has been verified on HiKey970 board. > Hi, Any update on this series? Thanks, Mani > Thanks, > Mani > > Manivannan Sadhasivam (4): > dt-bindings: clk: hisilicon: Add bindings for Hi3670 clk > arm64: dts: hisilicon: Add clock nodes for Hi3670 SoC > arm64: dts: hisilicon: Source SoC clock for UART6 > clk: hisilicon: Add clock driver for Hi3670 SoC > > .../bindings/clock/hi3670-clock.txt | 43 + > arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 48 +- > drivers/clk/hisilicon/Kconfig |7 + > drivers/clk/hisilicon/Makefile|1 + > drivers/clk/hisilicon/clk-hi3670.c| 1016 + > include/dt-bindings/clock/hi3670-clock.h | 348 ++ > 6 files changed, 1458 insertions(+), 5 deletions(-) > create mode 100644 Documentation/devicetree/bindings/clock/hi3670-clock.txt > create mode 100644 drivers/clk/hisilicon/clk-hi3670.c > create mode 100644 include/dt-bindings/clock/hi3670-clock.h > > -- > 2.17.1 >
Re: [PATCH 0/4] Add clock support for Hi3670 SoC
On Thu, Sep 20, 2018 at 11:00:59PM -0700, Manivannan Sadhasivam wrote: > This patchset adds clock support for Hi3670 SoC from HiSilicon utilizing > the HiSi common clock code. While adding clock support, let's remove the > fixed clock for UART and source SoC clock on HiKey970 board. > > This patchset has been verified on HiKey970 board. > Hi, Any update on this series? Thanks, Mani > Thanks, > Mani > > Manivannan Sadhasivam (4): > dt-bindings: clk: hisilicon: Add bindings for Hi3670 clk > arm64: dts: hisilicon: Add clock nodes for Hi3670 SoC > arm64: dts: hisilicon: Source SoC clock for UART6 > clk: hisilicon: Add clock driver for Hi3670 SoC > > .../bindings/clock/hi3670-clock.txt | 43 + > arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 48 +- > drivers/clk/hisilicon/Kconfig |7 + > drivers/clk/hisilicon/Makefile|1 + > drivers/clk/hisilicon/clk-hi3670.c| 1016 + > include/dt-bindings/clock/hi3670-clock.h | 348 ++ > 6 files changed, 1458 insertions(+), 5 deletions(-) > create mode 100644 Documentation/devicetree/bindings/clock/hi3670-clock.txt > create mode 100644 drivers/clk/hisilicon/clk-hi3670.c > create mode 100644 include/dt-bindings/clock/hi3670-clock.h > > -- > 2.17.1 >
Re: [PATCH] mm: Speed up mremap on large regions
+cc xen maintainers and kvm folks
On Fri, Oct 12, 2018 at 4:40 AM Joel Fernandes (Google)
wrote:
> Android needs to mremap large regions of memory during memory management
> related operations. The mremap system call can be really slow if THP is
> not enabled. The bottleneck is move_page_tables, which is copying each
> pte at a time, and can be really slow across a large map. Turning on THP
> may not be a viable option, and is not for us. This patch speeds up the
> performance for non-THP system by copying at the PMD level when possible.
[...]
> +bool move_normal_pmd(struct vm_area_struct *vma, unsigned long old_addr,
> + unsigned long new_addr, unsigned long old_end,
> + pmd_t *old_pmd, pmd_t *new_pmd, bool *need_flush)
> +{
[...]
> + /*
> +* We don't have to worry about the ordering of src and dst
> +* ptlocks because exclusive mmap_sem prevents deadlock.
> +*/
> + old_ptl = pmd_lock(vma->vm_mm, old_pmd);
> + if (old_ptl) {
> + pmd_t pmd;
> +
> + new_ptl = pmd_lockptr(mm, new_pmd);
> + if (new_ptl != old_ptl)
> + spin_lock_nested(new_ptl, SINGLE_DEPTH_NESTING);
> +
> + /* Clear the pmd */
> + pmd = *old_pmd;
> + pmd_clear(old_pmd);
> +
> + VM_BUG_ON(!pmd_none(*new_pmd));
> +
> + /* Set the new pmd */
> + set_pmd_at(mm, new_addr, new_pmd, pmd);
> + if (new_ptl != old_ptl)
> + spin_unlock(new_ptl);
> + spin_unlock(old_ptl);
How does this interact with Xen PV? From a quick look at the Xen PV
integration code in xen_alloc_ptpage(), it looks to me as if, in a
config that doesn't use split ptlocks, this is going to temporarily
drop Xen's type count for the page to zero, causing Xen to de-validate
and then re-validate the L1 pagetable; if you first set the new pmd
before clearing the old one, that wouldn't happen. I don't know how
this interacts with shadow paging implementations.
> + *need_flush = true;
> + return true;
> + }
> + return false;
> +}
Re: [PATCH] mm: Speed up mremap on large regions
+cc xen maintainers and kvm folks
On Fri, Oct 12, 2018 at 4:40 AM Joel Fernandes (Google)
wrote:
> Android needs to mremap large regions of memory during memory management
> related operations. The mremap system call can be really slow if THP is
> not enabled. The bottleneck is move_page_tables, which is copying each
> pte at a time, and can be really slow across a large map. Turning on THP
> may not be a viable option, and is not for us. This patch speeds up the
> performance for non-THP system by copying at the PMD level when possible.
[...]
> +bool move_normal_pmd(struct vm_area_struct *vma, unsigned long old_addr,
> + unsigned long new_addr, unsigned long old_end,
> + pmd_t *old_pmd, pmd_t *new_pmd, bool *need_flush)
> +{
[...]
> + /*
> +* We don't have to worry about the ordering of src and dst
> +* ptlocks because exclusive mmap_sem prevents deadlock.
> +*/
> + old_ptl = pmd_lock(vma->vm_mm, old_pmd);
> + if (old_ptl) {
> + pmd_t pmd;
> +
> + new_ptl = pmd_lockptr(mm, new_pmd);
> + if (new_ptl != old_ptl)
> + spin_lock_nested(new_ptl, SINGLE_DEPTH_NESTING);
> +
> + /* Clear the pmd */
> + pmd = *old_pmd;
> + pmd_clear(old_pmd);
> +
> + VM_BUG_ON(!pmd_none(*new_pmd));
> +
> + /* Set the new pmd */
> + set_pmd_at(mm, new_addr, new_pmd, pmd);
> + if (new_ptl != old_ptl)
> + spin_unlock(new_ptl);
> + spin_unlock(old_ptl);
How does this interact with Xen PV? From a quick look at the Xen PV
integration code in xen_alloc_ptpage(), it looks to me as if, in a
config that doesn't use split ptlocks, this is going to temporarily
drop Xen's type count for the page to zero, causing Xen to de-validate
and then re-validate the L1 pagetable; if you first set the new pmd
before clearing the old one, that wouldn't happen. I don't know how
this interacts with shadow paging implementations.
> + *need_flush = true;
> + return true;
> + }
> + return false;
> +}
Re: [PATCH V11 1/8] irqchip: add C-SKY SMP interrupt controller
Hi Marc,
On Tue, Oct 09, 2018 at 04:11:05PM +0100, Marc Zyngier wrote:
> On 09/10/18 15:41, Guo Ren wrote:
> > - Irq-csky-mpintc is C-SKY smp system interrupt controller and it
> >could support 16 soft irqs, 16 private irqs, and 992 max common
> >irqs.
> >
> >Changelog:
> > - Convert the cpumask to an interrupt-controller specific representation
> >in driver's code, and not the SMP code's.
> > - pass checkpatch.pl
> > - Move IPI_IRQ into the driver
> > - Remove irq_set_default_host() and use set_ipi_irq_mapping()
> > - Change name with upstream feed-back
> > - Change irq map, reserve soft_irq & private_irq space
> > - Add License and Copyright
> > - Support set_affinity for irq balance in SMP
> >
> >Signed-off-by: Guo Ren
> >Cc: Marc Zyngier
>
> [...]
>
> >+/* C-SKY multi processor interrupt controller */
> >+static int __init
> >+csky_mpintc_init(struct device_node *node, struct device_node *parent)
> >+{
> >+unsigned int cpu, nr_irq;
> >+int ret;
> >+
> >+if (parent)
> >+return 0;
> >+
> >+ret = of_property_read_u32(node, "csky,num-irqs", _irq);
> >+if (ret < 0)
> >+nr_irq = INTC_IRQS;
> >+
> >+if (INTCG_base == NULL) {
> >+INTCG_base = ioremap(mfcr("cr<31, 14>"),
> >+ INTCL_SIZE*nr_cpu_ids + INTCG_SIZE);
> >+if (INTCG_base == NULL)
> >+return -EIO;
> >+
> >+INTCL_base = INTCG_base + INTCG_SIZE;
> >+
> >+writel_relaxed(BIT(0), INTCG_base + INTCG_ICTLR);
> >+}
> >+
> >+root_domain = irq_domain_add_linear(node, nr_irq, _irqdomain_ops,
> >+NULL);
> >+if (!root_domain)
> >+return -ENXIO;
> >+
> >+/* for every cpu */
> >+for_each_present_cpu(cpu) {
> >+per_cpu(intcl_reg, cpu) = INTCL_base + (INTCL_SIZE * cpu);
> >+writel_relaxed(BIT(0), per_cpu(intcl_reg, cpu) + INTCL_PICTLR);
> >+}
> >+
> >+set_handle_irq(_mpintc_handler);
> >+
> >+#ifdef CONFIG_SMP
> >+set_send_ipi(_mpintc_send_ipi);
> >+
> >+set_ipi_irq_mapping(_mpintc_ipi_irq_mapping);
>
> Same remark as before.
>
> You do not need this second callback, and you should redefine set_send_ipi
> to take an irq number:
>
> ipi_irq = irq_create_mapping(root_domain, IPI_IRQ);
> if (!ipi_irq)
> [handle error]
>
> set_send_ipi(csky_mpintc_send_ipi, ipi_irq);
>
> and you can then delete both set_ipi_irq_mapping and csky_mpintc_handler,
> none of which serve any purpose.
>
> In your SMP code:
>
> void __init set_send_ipi(void (*func)(const struct cpumask *), int irq)
> {
> if (send_arch_ipi)
> return;
>
> send_arch_ipi = func;
> ipi_irq = irq;
> }
>
> and simplify setup_smp_ipi.
Ok, remove the set_ipi_irq_mapping. See my next version patch.
Best Regards
Guo Ren
Re: [PATCH V11 1/8] irqchip: add C-SKY SMP interrupt controller
Hi Marc,
On Tue, Oct 09, 2018 at 04:11:05PM +0100, Marc Zyngier wrote:
> On 09/10/18 15:41, Guo Ren wrote:
> > - Irq-csky-mpintc is C-SKY smp system interrupt controller and it
> >could support 16 soft irqs, 16 private irqs, and 992 max common
> >irqs.
> >
> >Changelog:
> > - Convert the cpumask to an interrupt-controller specific representation
> >in driver's code, and not the SMP code's.
> > - pass checkpatch.pl
> > - Move IPI_IRQ into the driver
> > - Remove irq_set_default_host() and use set_ipi_irq_mapping()
> > - Change name with upstream feed-back
> > - Change irq map, reserve soft_irq & private_irq space
> > - Add License and Copyright
> > - Support set_affinity for irq balance in SMP
> >
> >Signed-off-by: Guo Ren
> >Cc: Marc Zyngier
>
> [...]
>
> >+/* C-SKY multi processor interrupt controller */
> >+static int __init
> >+csky_mpintc_init(struct device_node *node, struct device_node *parent)
> >+{
> >+unsigned int cpu, nr_irq;
> >+int ret;
> >+
> >+if (parent)
> >+return 0;
> >+
> >+ret = of_property_read_u32(node, "csky,num-irqs", _irq);
> >+if (ret < 0)
> >+nr_irq = INTC_IRQS;
> >+
> >+if (INTCG_base == NULL) {
> >+INTCG_base = ioremap(mfcr("cr<31, 14>"),
> >+ INTCL_SIZE*nr_cpu_ids + INTCG_SIZE);
> >+if (INTCG_base == NULL)
> >+return -EIO;
> >+
> >+INTCL_base = INTCG_base + INTCG_SIZE;
> >+
> >+writel_relaxed(BIT(0), INTCG_base + INTCG_ICTLR);
> >+}
> >+
> >+root_domain = irq_domain_add_linear(node, nr_irq, _irqdomain_ops,
> >+NULL);
> >+if (!root_domain)
> >+return -ENXIO;
> >+
> >+/* for every cpu */
> >+for_each_present_cpu(cpu) {
> >+per_cpu(intcl_reg, cpu) = INTCL_base + (INTCL_SIZE * cpu);
> >+writel_relaxed(BIT(0), per_cpu(intcl_reg, cpu) + INTCL_PICTLR);
> >+}
> >+
> >+set_handle_irq(_mpintc_handler);
> >+
> >+#ifdef CONFIG_SMP
> >+set_send_ipi(_mpintc_send_ipi);
> >+
> >+set_ipi_irq_mapping(_mpintc_ipi_irq_mapping);
>
> Same remark as before.
>
> You do not need this second callback, and you should redefine set_send_ipi
> to take an irq number:
>
> ipi_irq = irq_create_mapping(root_domain, IPI_IRQ);
> if (!ipi_irq)
> [handle error]
>
> set_send_ipi(csky_mpintc_send_ipi, ipi_irq);
>
> and you can then delete both set_ipi_irq_mapping and csky_mpintc_handler,
> none of which serve any purpose.
>
> In your SMP code:
>
> void __init set_send_ipi(void (*func)(const struct cpumask *), int irq)
> {
> if (send_arch_ipi)
> return;
>
> send_arch_ipi = func;
> ipi_irq = irq;
> }
>
> and simplify setup_smp_ipi.
Ok, remove the set_ipi_irq_mapping. See my next version patch.
Best Regards
Guo Ren
[PATCH -next] misc: mic: scif: remove set but not used variables 'src_dma_addr, dst_dma_addr'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/misc/mic/scif/scif_dma.c: In function 'scif_rma_list_dma_copy_wrapper':
drivers/misc/mic/scif/scif_dma.c:1558:27: warning:
variable 'dst_dma_addr' set but not used [-Wunused-but-set-variable]
drivers/misc/mic/scif/scif_dma.c:1558:13: warning:
variable 'src_dma_addr' set but not used [-Wunused-but-set-variable]
They never used since introduction in
commit 7cc31cd27752 ("misc: mic: SCIF DMA and CPU copy interface")
Signed-off-by: YueHaibing
---
drivers/misc/mic/scif/scif_dma.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/misc/mic/scif/scif_dma.c b/drivers/misc/mic/scif/scif_dma.c
index 03af8b5..2babbac 100644
--- a/drivers/misc/mic/scif/scif_dma.c
+++ b/drivers/misc/mic/scif/scif_dma.c
@@ -1555,7 +1555,6 @@ static int scif_rma_list_dma_copy_wrapper(struct
scif_endpt *epd,
u8 *temp = NULL;
bool src_local = true;
struct scif_dma_comp_cb *comp_cb;
- dma_addr_t src_dma_addr, dst_dma_addr;
int err;
if (is_dma_copy_aligned(chan->device, 1, 1, 1))
@@ -1569,8 +1568,6 @@ static int scif_rma_list_dma_copy_wrapper(struct
scif_endpt *epd,
if (work->loopback)
return scif_rma_list_cpu_copy(work);
- src_dma_addr = __scif_off_to_dma_addr(work->src_window, src_offset);
- dst_dma_addr = __scif_off_to_dma_addr(work->dst_window, dst_offset);
src_local = work->src_window->type == SCIF_WINDOW_SELF;
/* Allocate dma_completion cb */
[PATCH -next] misc: mic: scif: remove set but not used variables 'src_dma_addr, dst_dma_addr'
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/misc/mic/scif/scif_dma.c: In function 'scif_rma_list_dma_copy_wrapper':
drivers/misc/mic/scif/scif_dma.c:1558:27: warning:
variable 'dst_dma_addr' set but not used [-Wunused-but-set-variable]
drivers/misc/mic/scif/scif_dma.c:1558:13: warning:
variable 'src_dma_addr' set but not used [-Wunused-but-set-variable]
They never used since introduction in
commit 7cc31cd27752 ("misc: mic: SCIF DMA and CPU copy interface")
Signed-off-by: YueHaibing
---
drivers/misc/mic/scif/scif_dma.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/misc/mic/scif/scif_dma.c b/drivers/misc/mic/scif/scif_dma.c
index 03af8b5..2babbac 100644
--- a/drivers/misc/mic/scif/scif_dma.c
+++ b/drivers/misc/mic/scif/scif_dma.c
@@ -1555,7 +1555,6 @@ static int scif_rma_list_dma_copy_wrapper(struct
scif_endpt *epd,
u8 *temp = NULL;
bool src_local = true;
struct scif_dma_comp_cb *comp_cb;
- dma_addr_t src_dma_addr, dst_dma_addr;
int err;
if (is_dma_copy_aligned(chan->device, 1, 1, 1))
@@ -1569,8 +1568,6 @@ static int scif_rma_list_dma_copy_wrapper(struct
scif_endpt *epd,
if (work->loopback)
return scif_rma_list_cpu_copy(work);
- src_dma_addr = __scif_off_to_dma_addr(work->src_window, src_offset);
- dst_dma_addr = __scif_off_to_dma_addr(work->dst_window, dst_offset);
src_local = work->src_window->type == SCIF_WINDOW_SELF;
/* Allocate dma_completion cb */
Re: [RFC][PATCH] x86: ptrace: Add function argument access API
On Thu, 11 Oct 2018 23:00:21 -0400 Steven Rostedt wrote: > A while ago I posted an RFC patchset for dynamic function based > events. But Masami pointed out that this could be done with kprobes > with minimal changes. He posted a patch set back in March > http://lkml.kernel.org/r/152049860385.7289.14079393589900496424.stgit@devbox > I've pulled this in locally, but haven't had the time until recently > to look at it seriously. I even plan to talk about these changes in > my talk at Open Source Summit in Edinburgh less than two weeks away > (talk about conference driven development!). > Anyway, the one patch that really needs external approval is the one > that creates a new architecture dependent API to retrieve function > arguments from pt_regs if the ip is at the start of the function call > (via a breakpoint or ftrace fentry). That's this patch. > > Anyone have any issues with it? If not, I'm going to start doing some > serious testing of this code and try to get it into the next merge > window. You can also play with the full repo here: git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace.git branch: ftrace/kprobes -- Steve
Re: [RFC][PATCH] x86: ptrace: Add function argument access API
On Thu, 11 Oct 2018 23:00:21 -0400 Steven Rostedt wrote: > A while ago I posted an RFC patchset for dynamic function based > events. But Masami pointed out that this could be done with kprobes > with minimal changes. He posted a patch set back in March > http://lkml.kernel.org/r/152049860385.7289.14079393589900496424.stgit@devbox > I've pulled this in locally, but haven't had the time until recently > to look at it seriously. I even plan to talk about these changes in > my talk at Open Source Summit in Edinburgh less than two weeks away > (talk about conference driven development!). > Anyway, the one patch that really needs external approval is the one > that creates a new architecture dependent API to retrieve function > arguments from pt_regs if the ip is at the start of the function call > (via a breakpoint or ftrace fentry). That's this patch. > > Anyone have any issues with it? If not, I'm going to start doing some > serious testing of this code and try to get it into the next merge > window. You can also play with the full repo here: git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace.git branch: ftrace/kprobes -- Steve
[RFC][PATCH] x86: ptrace: Add function argument access API
[
A while ago I posted an RFC patchset for dynamic function based
events. But Masami pointed out that this could be done with kprobes
with minimal changes. He posted a patch set back in March
http://lkml.kernel.org/r/152049860385.7289.14079393589900496424.stgit@devbox
I've pulled this in locally, but haven't had the time until recently
to look at it seriously. I even plan to talk about these changes in
my talk at Open Source Summit in Edinburgh less than two weeks away
(talk about conference driven development!).
Anyway, the one patch that really needs external approval is the one
that creates a new architecture dependent API to retrieve function
arguments from pt_regs if the ip is at the start of the function call
(via a breakpoint or ftrace fentry). That's this patch.
Anyone have any issues with it? If not, I'm going to start doing some
serious testing of this code and try to get it into the next merge
window.
Thanks!
-- Steve
]
From: Masami Hiramatsu
Add regs_get_argument() which returns N th argument of the
function call.
Note that this chooses most probably assignment, in some case
it can be incorrect (e.g. passing data structure or floating
point etc.)
This is expected to be called from kprobes or ftrace with regs
where the top of stack is the return address.
Link:
http://lkml.kernel.org/r/152465885737.26224.2822487520472783854.stgit@devbox
Signed-off-by: Masami Hiramatsu
Signed-off-by: Steven Rostedt (VMware)
---
arch/Kconfig | 7 +++
arch/x86/Kconfig | 1 +
arch/x86/include/asm/ptrace.h | 38 +++
3 files changed, 46 insertions(+)
diff --git a/arch/Kconfig b/arch/Kconfig
index 6801123932a5..facace0c90fc 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -290,6 +290,13 @@ config HAVE_RSEQ
This symbol should be selected by an architecture if it
supports an implementation of restartable sequences.
+config HAVE_FUNCTION_ARG_ACCESS_API
+ bool
+ help
+ This symbol should be selected by an architecure if it supports
+ the API needed to access function arguments from pt_regs,
+ declared in asm/ptrace.h
+
config HAVE_CLK
bool
help
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 1a0be022f91d..972973851779 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -184,6 +184,7 @@ config X86
select HAVE_RCU_TABLE_INVALIDATEif HAVE_RCU_TABLE_FREE
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_RELIABLE_STACKTRACE if X86_64 &&
(UNWINDER_FRAME_POINTER || UNWINDER_ORC) && STACK_VALIDATION
+ select HAVE_FUNCTION_ARG_ACCESS_API
select HAVE_STACKPROTECTOR if CC_HAS_SANE_STACKPROTECTOR
select HAVE_STACK_VALIDATIONif X86_64
select HAVE_RSEQ
diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h
index 6de1fd3d0097..c2304b25e2fd 100644
--- a/arch/x86/include/asm/ptrace.h
+++ b/arch/x86/include/asm/ptrace.h
@@ -256,6 +256,44 @@ static inline unsigned long
regs_get_kernel_stack_nth(struct pt_regs *regs,
return 0;
}
+/**
+ * regs_get_kernel_argument() - get Nth function argument in kernel
+ * @regs: pt_regs of that context
+ * @n: function argument number (start from 0)
+ *
+ * regs_get_argument() returns @n th argument of the function call.
+ * Note that this chooses most probably assignment, in some case
+ * it can be incorrect.
+ * This is expected to be called from kprobes or ftrace with regs
+ * where the top of stack is the return address.
+ */
+static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs,
+unsigned int n)
+{
+ static const unsigned int argument_offs[] = {
+#ifdef __i386__
+ offsetof(struct pt_regs, ax),
+ offsetof(struct pt_regs, cx),
+ offsetof(struct pt_regs, dx),
+#define NR_REG_ARGUMENTS 3
+#else
+ offsetof(struct pt_regs, di),
+ offsetof(struct pt_regs, si),
+ offsetof(struct pt_regs, dx),
+ offsetof(struct pt_regs, cx),
+ offsetof(struct pt_regs, r8),
+ offsetof(struct pt_regs, r9),
+#define NR_REG_ARGUMENTS 6
+#endif
+ };
+
+ if (n >= NR_REG_ARGUMENTS) {
+ n -= NR_REG_ARGUMENTS - 1;
+ return regs_get_kernel_stack_nth(regs, n);
+ } else
+ return regs_get_register(regs, argument_offs[n]);
+}
+
#define arch_has_single_step() (1)
#ifdef CONFIG_X86_DEBUGCTLMSR
#define arch_has_block_step() (1)
--
2.19.0
[RFC][PATCH] x86: ptrace: Add function argument access API
[
A while ago I posted an RFC patchset for dynamic function based
events. But Masami pointed out that this could be done with kprobes
with minimal changes. He posted a patch set back in March
http://lkml.kernel.org/r/152049860385.7289.14079393589900496424.stgit@devbox
I've pulled this in locally, but haven't had the time until recently
to look at it seriously. I even plan to talk about these changes in
my talk at Open Source Summit in Edinburgh less than two weeks away
(talk about conference driven development!).
Anyway, the one patch that really needs external approval is the one
that creates a new architecture dependent API to retrieve function
arguments from pt_regs if the ip is at the start of the function call
(via a breakpoint or ftrace fentry). That's this patch.
Anyone have any issues with it? If not, I'm going to start doing some
serious testing of this code and try to get it into the next merge
window.
Thanks!
-- Steve
]
From: Masami Hiramatsu
Add regs_get_argument() which returns N th argument of the
function call.
Note that this chooses most probably assignment, in some case
it can be incorrect (e.g. passing data structure or floating
point etc.)
This is expected to be called from kprobes or ftrace with regs
where the top of stack is the return address.
Link:
http://lkml.kernel.org/r/152465885737.26224.2822487520472783854.stgit@devbox
Signed-off-by: Masami Hiramatsu
Signed-off-by: Steven Rostedt (VMware)
---
arch/Kconfig | 7 +++
arch/x86/Kconfig | 1 +
arch/x86/include/asm/ptrace.h | 38 +++
3 files changed, 46 insertions(+)
diff --git a/arch/Kconfig b/arch/Kconfig
index 6801123932a5..facace0c90fc 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -290,6 +290,13 @@ config HAVE_RSEQ
This symbol should be selected by an architecture if it
supports an implementation of restartable sequences.
+config HAVE_FUNCTION_ARG_ACCESS_API
+ bool
+ help
+ This symbol should be selected by an architecure if it supports
+ the API needed to access function arguments from pt_regs,
+ declared in asm/ptrace.h
+
config HAVE_CLK
bool
help
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 1a0be022f91d..972973851779 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -184,6 +184,7 @@ config X86
select HAVE_RCU_TABLE_INVALIDATEif HAVE_RCU_TABLE_FREE
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_RELIABLE_STACKTRACE if X86_64 &&
(UNWINDER_FRAME_POINTER || UNWINDER_ORC) && STACK_VALIDATION
+ select HAVE_FUNCTION_ARG_ACCESS_API
select HAVE_STACKPROTECTOR if CC_HAS_SANE_STACKPROTECTOR
select HAVE_STACK_VALIDATIONif X86_64
select HAVE_RSEQ
diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h
index 6de1fd3d0097..c2304b25e2fd 100644
--- a/arch/x86/include/asm/ptrace.h
+++ b/arch/x86/include/asm/ptrace.h
@@ -256,6 +256,44 @@ static inline unsigned long
regs_get_kernel_stack_nth(struct pt_regs *regs,
return 0;
}
+/**
+ * regs_get_kernel_argument() - get Nth function argument in kernel
+ * @regs: pt_regs of that context
+ * @n: function argument number (start from 0)
+ *
+ * regs_get_argument() returns @n th argument of the function call.
+ * Note that this chooses most probably assignment, in some case
+ * it can be incorrect.
+ * This is expected to be called from kprobes or ftrace with regs
+ * where the top of stack is the return address.
+ */
+static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs,
+unsigned int n)
+{
+ static const unsigned int argument_offs[] = {
+#ifdef __i386__
+ offsetof(struct pt_regs, ax),
+ offsetof(struct pt_regs, cx),
+ offsetof(struct pt_regs, dx),
+#define NR_REG_ARGUMENTS 3
+#else
+ offsetof(struct pt_regs, di),
+ offsetof(struct pt_regs, si),
+ offsetof(struct pt_regs, dx),
+ offsetof(struct pt_regs, cx),
+ offsetof(struct pt_regs, r8),
+ offsetof(struct pt_regs, r9),
+#define NR_REG_ARGUMENTS 6
+#endif
+ };
+
+ if (n >= NR_REG_ARGUMENTS) {
+ n -= NR_REG_ARGUMENTS - 1;
+ return regs_get_kernel_stack_nth(regs, n);
+ } else
+ return regs_get_register(regs, argument_offs[n]);
+}
+
#define arch_has_single_step() (1)
#ifdef CONFIG_X86_DEBUGCTLMSR
#define arch_has_block_step() (1)
--
2.19.0
Re: [PATCH] mtd: spi-nor: Add support for SPI boot flash access for AMD Family 16h
Hi Brett,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on mtd/spi-nor/next]
[also build test WARNING on v4.19-rc7 next-20181011]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Brett-Grandbois/mtd-spi-nor-Add-support-for-SPI-boot-flash-access-for-AMD-Family-16h/20181012-085348
base: git://git.infradead.org/linux-mtd.git spi-nor/next
config: x86_64-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All warnings (new ones prefixed by >>):
>> drivers/mtd/spi-nor/amd-spirom.c:355:22: warning: incorrect type in
>> assignment (different base types)
drivers/mtd/spi-nor/amd-spirom.c:355:22:expected unsigned int [unsigned]
[usertype] addr
drivers/mtd/spi-nor/amd-spirom.c:355:22:got restricted __be32 [usertype]
drivers/mtd/spi-nor/amd-spirom.c:396:14: warning: incorrect type in
assignment (different base types)
drivers/mtd/spi-nor/amd-spirom.c:396:14:expected unsigned int [unsigned]
[usertype] addr
drivers/mtd/spi-nor/amd-spirom.c:396:14:got restricted __be32 [usertype]
vim +355 drivers/mtd/spi-nor/amd-spirom.c
296
297 /*
298 * fallback read op based on explicit read command
299 * ideally the HW io will be used but this needs to be available if
it's not
300 * strapped, can't get the resources, etc.
301 * spi_nor_read() will loop on the actual bytes read so we can just
limit
302 * ourselves to the 64-byte FIFO size.
303 */
304 static ssize_t amd_spirom_read(struct spi_nor *nor, loff_t from,
305 size_t len, u_char *read_buf)
306 {
307 struct amd_spirom *spirom = nor->priv;
308 u32 *pbuf32;
309 size_t head;
310 size_t tail;
311 size_t left;
312 ssize_t rc;
313 size_t cur;
314 u8 *p_addr;
315 u8 rd_len;
316 size_t i;
317 u32 addr;
318
319 dev_dbg(nor->dev, "read: from: %lld len: %zu\n", from, len);
320
321 /*
322 * We only allow READ in the HWCAPS so most read operations
should come
323 * with that opcode. However, the SPI-NOR layer can swap out
the read
324 * opcode with something else (i.e. Read SFDP) which must be
handled via
325 * alt command and not the ROM IO
326 */
327 if (spirom->rom && (nor->read_opcode == SPINOR_OP_READ)) {
328 /*
329 * no need for status/busy as the HW controller will
deal with
330 * that, but memcpy_fromio can make out-of-order
fetches so need
331 * to do this explicitly
332 */
333 left = len;
334 head = from & 3;
335 left -= head;
336 tail = left & 3;
337 left -= tail;
338 cur = 0;
339
340 for (i = 0; i < head; i++, cur++)
341 read_buf[cur] = ioread8(spirom->rom + from +
cur);
342
343 pbuf32 = (u32 *)(read_buf + cur);
344 left /= 4;
345
346 for (i = 0; i < left; i++, cur += 4, pbuf32++)
347 *pbuf32 = ioread32(spirom->rom + from + cur);
348
349 for (i = 0; i < tail; i++, cur++)
350 read_buf[cur] = ioread8(spirom->rom + from +
cur);
351
352 rc = (ssize_t)len;
353 } else {
354
> 355 addr = cpu_to_be32((u32)(from));
356 p_addr = (u8 *)();
357
358 rd_len = len > 64 ? 64 : (u8)len;
359
360 if (nor->addr_width == 3)
361 p_addr++;
362
363 rc = amd_spirom_reg_xfer(spirom, nor->read_opcode,
rd_len,
364 nor->addr_width, read_buf,
p_addr);
365
366 if (!rc)
367 rc = (ssize_t)rd_len;
368 }
369
370 return rc;
371 }
372
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
Re: [PATCH] mtd: spi-nor: Add support for SPI boot flash access for AMD Family 16h
Hi Brett,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on mtd/spi-nor/next]
[also build test WARNING on v4.19-rc7 next-20181011]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Brett-Grandbois/mtd-spi-nor-Add-support-for-SPI-boot-flash-access-for-AMD-Family-16h/20181012-085348
base: git://git.infradead.org/linux-mtd.git spi-nor/next
config: x86_64-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All warnings (new ones prefixed by >>):
>> drivers/mtd/spi-nor/amd-spirom.c:355:22: warning: incorrect type in
>> assignment (different base types)
drivers/mtd/spi-nor/amd-spirom.c:355:22:expected unsigned int [unsigned]
[usertype] addr
drivers/mtd/spi-nor/amd-spirom.c:355:22:got restricted __be32 [usertype]
drivers/mtd/spi-nor/amd-spirom.c:396:14: warning: incorrect type in
assignment (different base types)
drivers/mtd/spi-nor/amd-spirom.c:396:14:expected unsigned int [unsigned]
[usertype] addr
drivers/mtd/spi-nor/amd-spirom.c:396:14:got restricted __be32 [usertype]
vim +355 drivers/mtd/spi-nor/amd-spirom.c
296
297 /*
298 * fallback read op based on explicit read command
299 * ideally the HW io will be used but this needs to be available if
it's not
300 * strapped, can't get the resources, etc.
301 * spi_nor_read() will loop on the actual bytes read so we can just
limit
302 * ourselves to the 64-byte FIFO size.
303 */
304 static ssize_t amd_spirom_read(struct spi_nor *nor, loff_t from,
305 size_t len, u_char *read_buf)
306 {
307 struct amd_spirom *spirom = nor->priv;
308 u32 *pbuf32;
309 size_t head;
310 size_t tail;
311 size_t left;
312 ssize_t rc;
313 size_t cur;
314 u8 *p_addr;
315 u8 rd_len;
316 size_t i;
317 u32 addr;
318
319 dev_dbg(nor->dev, "read: from: %lld len: %zu\n", from, len);
320
321 /*
322 * We only allow READ in the HWCAPS so most read operations
should come
323 * with that opcode. However, the SPI-NOR layer can swap out
the read
324 * opcode with something else (i.e. Read SFDP) which must be
handled via
325 * alt command and not the ROM IO
326 */
327 if (spirom->rom && (nor->read_opcode == SPINOR_OP_READ)) {
328 /*
329 * no need for status/busy as the HW controller will
deal with
330 * that, but memcpy_fromio can make out-of-order
fetches so need
331 * to do this explicitly
332 */
333 left = len;
334 head = from & 3;
335 left -= head;
336 tail = left & 3;
337 left -= tail;
338 cur = 0;
339
340 for (i = 0; i < head; i++, cur++)
341 read_buf[cur] = ioread8(spirom->rom + from +
cur);
342
343 pbuf32 = (u32 *)(read_buf + cur);
344 left /= 4;
345
346 for (i = 0; i < left; i++, cur += 4, pbuf32++)
347 *pbuf32 = ioread32(spirom->rom + from + cur);
348
349 for (i = 0; i < tail; i++, cur++)
350 read_buf[cur] = ioread8(spirom->rom + from +
cur);
351
352 rc = (ssize_t)len;
353 } else {
354
> 355 addr = cpu_to_be32((u32)(from));
356 p_addr = (u8 *)();
357
358 rd_len = len > 64 ? 64 : (u8)len;
359
360 if (nor->addr_width == 3)
361 p_addr++;
362
363 rc = amd_spirom_reg_xfer(spirom, nor->read_opcode,
rd_len,
364 nor->addr_width, read_buf,
p_addr);
365
366 if (!rc)
367 rc = (ssize_t)rd_len;
368 }
369
370 return rc;
371 }
372
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
[for-next][PATCH] trace_uprobe: support reference counter in fd-based uprobe
Added for the 4.20/5.0 queue.
-- Steve
git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace.git
for-next
Head SHA1: a6ca88b241d5e929e6e60b12ad8cd288f0ffa256
Song Liu (1):
trace_uprobe: support reference counter in fd-based uprobe
include/linux/trace_events.h| 3 ++-
kernel/events/core.c| 49 -
kernel/trace/trace_event_perf.c | 7 +++---
kernel/trace/trace_probe.h | 3 ++-
kernel/trace/trace_uprobe.c | 4 +++-
5 files changed, 50 insertions(+), 16 deletions(-)
---
commit a6ca88b241d5e929e6e60b12ad8cd288f0ffa256
Author: Song Liu
Date: Mon Oct 1 22:36:36 2018 -0700
trace_uprobe: support reference counter in fd-based uprobe
This patch enables uprobes with reference counter in fd-based uprobe.
Highest 32 bits of perf_event_attr.config is used to stored offset
of the reference count (semaphore).
Format information in /sys/bus/event_source/devices/uprobe/format/ is
updated to reflect this new feature.
Link:
http://lkml.kernel.org/r/20181002053636.1896903-1-songliubrav...@fb.com
Cc: Oleg Nesterov
Acked-by: Peter Zijlstra (Intel)
Reviewed-and-tested-by: Ravi Bangoria
Signed-off-by: Song Liu
Signed-off-by: Steven Rostedt (VMware)
diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h
index 78a010e19ed4..4130a5497d40 100644
--- a/include/linux/trace_events.h
+++ b/include/linux/trace_events.h
@@ -575,7 +575,8 @@ extern int bpf_get_kprobe_info(const struct perf_event
*event,
bool perf_type_tracepoint);
#endif
#ifdef CONFIG_UPROBE_EVENTS
-extern int perf_uprobe_init(struct perf_event *event, bool is_retprobe);
+extern int perf_uprobe_init(struct perf_event *event,
+unsigned long ref_ctr_offset, bool is_retprobe);
extern void perf_uprobe_destroy(struct perf_event *event);
extern int bpf_get_uprobe_info(const struct perf_event *event,
u32 *fd_type, const char **filename,
diff --git a/kernel/events/core.c b/kernel/events/core.c
index c80549bf82c6..65b30773af3e 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -8368,30 +8368,39 @@ static struct pmu perf_tracepoint = {
*
* PERF_PROBE_CONFIG_IS_RETPROBE if set, create kretprobe/uretprobe
* if not set, create kprobe/uprobe
+ *
+ * The following values specify a reference counter (or semaphore in the
+ * terminology of tools like dtrace, systemtap, etc.) Userspace Statically
+ * Defined Tracepoints (USDT). Currently, we use 40 bit for the offset.
+ *
+ * PERF_UPROBE_REF_CTR_OFFSET_BITS # of bits in config as th offset
+ * PERF_UPROBE_REF_CTR_OFFSET_SHIFT# of bits to shift left
*/
enum perf_probe_config {
PERF_PROBE_CONFIG_IS_RETPROBE = 1U << 0, /* [k,u]retprobe */
+ PERF_UPROBE_REF_CTR_OFFSET_BITS = 32,
+ PERF_UPROBE_REF_CTR_OFFSET_SHIFT = 64 - PERF_UPROBE_REF_CTR_OFFSET_BITS,
};
PMU_FORMAT_ATTR(retprobe, "config:0");
+#endif
-static struct attribute *probe_attrs[] = {
+#ifdef CONFIG_KPROBE_EVENTS
+static struct attribute *kprobe_attrs[] = {
_attr_retprobe.attr,
NULL,
};
-static struct attribute_group probe_format_group = {
+static struct attribute_group kprobe_format_group = {
.name = "format",
- .attrs = probe_attrs,
+ .attrs = kprobe_attrs,
};
-static const struct attribute_group *probe_attr_groups[] = {
- _format_group,
+static const struct attribute_group *kprobe_attr_groups[] = {
+ _format_group,
NULL,
};
-#endif
-#ifdef CONFIG_KPROBE_EVENTS
static int perf_kprobe_event_init(struct perf_event *event);
static struct pmu perf_kprobe = {
.task_ctx_nr= perf_sw_context,
@@ -8401,7 +8410,7 @@ static struct pmu perf_kprobe = {
.start = perf_swevent_start,
.stop = perf_swevent_stop,
.read = perf_swevent_read,
- .attr_groups= probe_attr_groups,
+ .attr_groups= kprobe_attr_groups,
};
static int perf_kprobe_event_init(struct perf_event *event)
@@ -8433,6 +8442,24 @@ static int perf_kprobe_event_init(struct perf_event
*event)
#endif /* CONFIG_KPROBE_EVENTS */
#ifdef CONFIG_UPROBE_EVENTS
+PMU_FORMAT_ATTR(ref_ctr_offset, "config:32-63");
+
+static struct attribute *uprobe_attrs[] = {
+ _attr_retprobe.attr,
+ _attr_ref_ctr_offset.attr,
+ NULL,
+};
+
+static struct attribute_group uprobe_format_group = {
+ .name = "format",
+ .attrs = uprobe_attrs,
+};
+
+static const struct attribute_group *uprobe_attr_groups[] = {
+ _format_group,
+ NULL,
+};
+
static int perf_uprobe_event_init(struct perf_event *event);
static struct pmu perf_uprobe = {
.task_ctx_nr= perf_sw_context,
@@ -8442,12 +8469,13 @@ static struct pmu perf_uprobe = {
.start =
[for-next][PATCH] trace_uprobe: support reference counter in fd-based uprobe
Added for the 4.20/5.0 queue.
-- Steve
git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace.git
for-next
Head SHA1: a6ca88b241d5e929e6e60b12ad8cd288f0ffa256
Song Liu (1):
trace_uprobe: support reference counter in fd-based uprobe
include/linux/trace_events.h| 3 ++-
kernel/events/core.c| 49 -
kernel/trace/trace_event_perf.c | 7 +++---
kernel/trace/trace_probe.h | 3 ++-
kernel/trace/trace_uprobe.c | 4 +++-
5 files changed, 50 insertions(+), 16 deletions(-)
---
commit a6ca88b241d5e929e6e60b12ad8cd288f0ffa256
Author: Song Liu
Date: Mon Oct 1 22:36:36 2018 -0700
trace_uprobe: support reference counter in fd-based uprobe
This patch enables uprobes with reference counter in fd-based uprobe.
Highest 32 bits of perf_event_attr.config is used to stored offset
of the reference count (semaphore).
Format information in /sys/bus/event_source/devices/uprobe/format/ is
updated to reflect this new feature.
Link:
http://lkml.kernel.org/r/20181002053636.1896903-1-songliubrav...@fb.com
Cc: Oleg Nesterov
Acked-by: Peter Zijlstra (Intel)
Reviewed-and-tested-by: Ravi Bangoria
Signed-off-by: Song Liu
Signed-off-by: Steven Rostedt (VMware)
diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h
index 78a010e19ed4..4130a5497d40 100644
--- a/include/linux/trace_events.h
+++ b/include/linux/trace_events.h
@@ -575,7 +575,8 @@ extern int bpf_get_kprobe_info(const struct perf_event
*event,
bool perf_type_tracepoint);
#endif
#ifdef CONFIG_UPROBE_EVENTS
-extern int perf_uprobe_init(struct perf_event *event, bool is_retprobe);
+extern int perf_uprobe_init(struct perf_event *event,
+unsigned long ref_ctr_offset, bool is_retprobe);
extern void perf_uprobe_destroy(struct perf_event *event);
extern int bpf_get_uprobe_info(const struct perf_event *event,
u32 *fd_type, const char **filename,
diff --git a/kernel/events/core.c b/kernel/events/core.c
index c80549bf82c6..65b30773af3e 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -8368,30 +8368,39 @@ static struct pmu perf_tracepoint = {
*
* PERF_PROBE_CONFIG_IS_RETPROBE if set, create kretprobe/uretprobe
* if not set, create kprobe/uprobe
+ *
+ * The following values specify a reference counter (or semaphore in the
+ * terminology of tools like dtrace, systemtap, etc.) Userspace Statically
+ * Defined Tracepoints (USDT). Currently, we use 40 bit for the offset.
+ *
+ * PERF_UPROBE_REF_CTR_OFFSET_BITS # of bits in config as th offset
+ * PERF_UPROBE_REF_CTR_OFFSET_SHIFT# of bits to shift left
*/
enum perf_probe_config {
PERF_PROBE_CONFIG_IS_RETPROBE = 1U << 0, /* [k,u]retprobe */
+ PERF_UPROBE_REF_CTR_OFFSET_BITS = 32,
+ PERF_UPROBE_REF_CTR_OFFSET_SHIFT = 64 - PERF_UPROBE_REF_CTR_OFFSET_BITS,
};
PMU_FORMAT_ATTR(retprobe, "config:0");
+#endif
-static struct attribute *probe_attrs[] = {
+#ifdef CONFIG_KPROBE_EVENTS
+static struct attribute *kprobe_attrs[] = {
_attr_retprobe.attr,
NULL,
};
-static struct attribute_group probe_format_group = {
+static struct attribute_group kprobe_format_group = {
.name = "format",
- .attrs = probe_attrs,
+ .attrs = kprobe_attrs,
};
-static const struct attribute_group *probe_attr_groups[] = {
- _format_group,
+static const struct attribute_group *kprobe_attr_groups[] = {
+ _format_group,
NULL,
};
-#endif
-#ifdef CONFIG_KPROBE_EVENTS
static int perf_kprobe_event_init(struct perf_event *event);
static struct pmu perf_kprobe = {
.task_ctx_nr= perf_sw_context,
@@ -8401,7 +8410,7 @@ static struct pmu perf_kprobe = {
.start = perf_swevent_start,
.stop = perf_swevent_stop,
.read = perf_swevent_read,
- .attr_groups= probe_attr_groups,
+ .attr_groups= kprobe_attr_groups,
};
static int perf_kprobe_event_init(struct perf_event *event)
@@ -8433,6 +8442,24 @@ static int perf_kprobe_event_init(struct perf_event
*event)
#endif /* CONFIG_KPROBE_EVENTS */
#ifdef CONFIG_UPROBE_EVENTS
+PMU_FORMAT_ATTR(ref_ctr_offset, "config:32-63");
+
+static struct attribute *uprobe_attrs[] = {
+ _attr_retprobe.attr,
+ _attr_ref_ctr_offset.attr,
+ NULL,
+};
+
+static struct attribute_group uprobe_format_group = {
+ .name = "format",
+ .attrs = uprobe_attrs,
+};
+
+static const struct attribute_group *uprobe_attr_groups[] = {
+ _format_group,
+ NULL,
+};
+
static int perf_uprobe_event_init(struct perf_event *event);
static struct pmu perf_uprobe = {
.task_ctx_nr= perf_sw_context,
@@ -8442,12 +8469,13 @@ static struct pmu perf_uprobe = {
.start =
RE: [PATCH v2 2/2] mtd: spi-nor: add entry for mt35xu512aba flash
Hi Tudor,
> -Original Message-
> From: Tudor Ambarus [mailto:tudor.amba...@microchip.com]
> Sent: Thursday, October 11, 2018 9:33 PM
> To: Yogesh Narayan Gaur ; linux-
> m...@lists.infradead.org; linux-...@vger.kernel.org
> Cc: marek.va...@gmail.com; cyrille.pitc...@wedev4u.fr;
> boris.brezil...@bootlin.com; computersforpe...@gmail.com;
> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v2 2/2] mtd: spi-nor: add entry for mt35xu512aba flash
>
>
>
> On 10/11/2018 11:15 AM, Yogesh Narayan Gaur wrote:
> > Add entry for mt35xu512aba Micron NOR flash.
> > This flash is having uniform sector erase size of 128KB, have support
> > of FSR(flag status register), flash size is 64MB and supports 4-byte
> > commands.
> >
> > Signed-off-by: Yogesh Gaur
> > ---
> > Changes for v2:
> > - Removed checkpatch warning, 80 character limit.
> >
> > drivers/mtd/spi-nor/spi-nor.c | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > b/drivers/mtd/spi-nor/spi-nor.c index b8b494f..e0d95ac 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -1405,6 +1405,10 @@ static const struct flash_info spi_nor_ids[] = {
> > { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR
> | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> > { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> >
> > + /* Micron */
> > + { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
> > + SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) },
> > +
>
> The style is slightly different from what Brian proposed back in
> 9648388fc7737365be7a8092e77df78ccc2cd1a4. For consistency reasons, I think
> we should use the same style in all entries.
>
Ok, I have send the next version of the patches with the style changes as
proposed by Brian.
--
Regards
Yogesh Gaur.
> Since I verified the correctness of the patch and my comment targets just a
> cosmetic change, I'll let the maintainers decide:
>
> Reviewed-by: Tudor Ambarus
RE: [PATCH v2 2/2] mtd: spi-nor: add entry for mt35xu512aba flash
Hi Tudor,
> -Original Message-
> From: Tudor Ambarus [mailto:tudor.amba...@microchip.com]
> Sent: Thursday, October 11, 2018 9:33 PM
> To: Yogesh Narayan Gaur ; linux-
> m...@lists.infradead.org; linux-...@vger.kernel.org
> Cc: marek.va...@gmail.com; cyrille.pitc...@wedev4u.fr;
> boris.brezil...@bootlin.com; computersforpe...@gmail.com;
> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v2 2/2] mtd: spi-nor: add entry for mt35xu512aba flash
>
>
>
> On 10/11/2018 11:15 AM, Yogesh Narayan Gaur wrote:
> > Add entry for mt35xu512aba Micron NOR flash.
> > This flash is having uniform sector erase size of 128KB, have support
> > of FSR(flag status register), flash size is 64MB and supports 4-byte
> > commands.
> >
> > Signed-off-by: Yogesh Gaur
> > ---
> > Changes for v2:
> > - Removed checkpatch warning, 80 character limit.
> >
> > drivers/mtd/spi-nor/spi-nor.c | 4
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > b/drivers/mtd/spi-nor/spi-nor.c index b8b494f..e0d95ac 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -1405,6 +1405,10 @@ static const struct flash_info spi_nor_ids[] = {
> > { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR
> | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> > { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> >
> > + /* Micron */
> > + { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
> > + SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) },
> > +
>
> The style is slightly different from what Brian proposed back in
> 9648388fc7737365be7a8092e77df78ccc2cd1a4. For consistency reasons, I think
> we should use the same style in all entries.
>
Ok, I have send the next version of the patches with the style changes as
proposed by Brian.
--
Regards
Yogesh Gaur.
> Since I verified the correctness of the patch and my comment targets just a
> cosmetic change, I'll let the maintainers decide:
>
> Reviewed-by: Tudor Ambarus
[PATCH v3 2/2] mtd: spi-nor: add entry for mt35xu512aba flash
Add entry for mt35xu512aba Micron NOR flash.
This flash is having uniform sector erase size of 128KB, have
support of FSR(flag status register), flash size is 64MB and
supports 4-byte commands.
Signed-off-by: Yogesh Gaur
Reviewed-by: Tudor Ambarus
---
Changes for v3:
- Modified flash node style as suggested by Tudor.
Changes for v2:
- Removed checkpatch warning, 80 character limit.
drivers/mtd/spi-nor/spi-nor.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index b8b494f..0b8a6e0 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1405,6 +1405,12 @@ static int spi_nor_is_locked(struct mtd_info *mtd,
loff_t ofs, uint64_t len)
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR |
SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR |
SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
+ /* Micron */
+ {
+ "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
+ SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES)
+ },
+
/* PMC */
{ "pm25lv512", INFO(0,0, 32 * 1024,2, SECT_4K_PMC) },
{ "pm25lv010", INFO(0,0, 32 * 1024,4, SECT_4K_PMC) },
--
1.9.1
[PATCH v3 1/2] mtd: spi-nor: add macros related to MICRON flash
Some MICRON related macros in spi-nor domain were ST.
Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.
Added entry of MFR Id for Micron flashes, 0x002C.
Signed-off-by: Yogesh Gaur
Reviewed-by: Tudor Ambarus
---
Changes for v3:
- None
Changes for v2:
- None
drivers/mtd/spi-nor/spi-nor.c | 9 ++---
include/linux/mtd/cfi.h | 1 +
include/linux/mtd/spi-nor.h | 3 ++-
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 9407ca5..b8b494f 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -284,6 +284,7 @@ static inline int set_4byte(struct spi_nor *nor, const
struct flash_info *info,
u8 cmd;
switch (JEDEC_MFR(info)) {
+ case SNOR_MFR_ST:
case SNOR_MFR_MICRON:
/* Some Micron need WREN command; all will accept it */
need_wren = true;
@@ -1388,7 +1389,7 @@ static int spi_nor_is_locked(struct mtd_info *mtd, loff_t
ofs, uint64_t len)
{ "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ)
},
- /* Micron */
+ /* Micron <--> ST Micro */
{ "n25q016a",INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K |
SPI_NOR_QUAD_READ) },
{ "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ)
},
{ "n25q032a",INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ)
},
@@ -3223,6 +3224,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
params->quad_enable = macronix_quad_enable;
break;
+ case SNOR_MFR_ST:
case SNOR_MFR_MICRON:
break;
@@ -3671,8 +3673,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
mtd->_resume = spi_nor_resume;
/* NOR protection support for STmicro/Micron chips and similar */
- if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
- info->flags & SPI_NOR_HAS_LOCK) {
+ if (JEDEC_MFR(info) == SNOR_MFR_ST ||
+ JEDEC_MFR(info) == SNOR_MFR_MICRON ||
+ info->flags & SPI_NOR_HAS_LOCK) {
nor->flash_lock = stm_lock;
nor->flash_unlock = stm_unlock;
nor->flash_is_locked = stm_is_locked;
diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h
index 9b57a9b..cbf7716 100644
--- a/include/linux/mtd/cfi.h
+++ b/include/linux/mtd/cfi.h
@@ -377,6 +377,7 @@ struct cfi_fixup {
#define CFI_MFR_SHARP 0x00B0
#define CFI_MFR_SST0x00BF
#define CFI_MFR_ST 0x0020 /* STMicroelectronics */
+#define CFI_MFR_MICRON 0x002C /* Micron */
#define CFI_MFR_TOSHIBA0x0098
#define CFI_MFR_WINBOND0x00DA
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 7f0c730..8b1acf6 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -23,7 +23,8 @@
#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
#define SNOR_MFR_GIGADEVICE0xc8
#define SNOR_MFR_INTEL CFI_MFR_INTEL
-#define SNOR_MFR_MICRONCFI_MFR_ST /* ST Micro <--> Micron */
+#define SNOR_MFR_STCFI_MFR_ST /* ST Micro */
+#define SNOR_MFR_MICRONCFI_MFR_MICRON /* Micron */
#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
#define SNOR_MFR_SPANSION CFI_MFR_AMD
#define SNOR_MFR_SST CFI_MFR_SST
--
1.9.1
