[PATCH v3] mailbox: sti: fix struct description warnings
Fix formating of struct description to avoid warning highlighted
by W=1 compilation.
warning: cannot understand function prototype: 'struct sti_mbox_device '
warning: cannot understand function prototype: 'struct sti_mbox_pdata '
warning: cannot understand function prototype: 'struct sti_channel '
Signed-off-by: Alain Volmat
Reviewed-by: Lee Jones
---
drivers/mailbox/mailbox-sti.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mailbox/mailbox-sti.c b/drivers/mailbox/mailbox-sti.c
index 2baf69a0b81c..0f2bc09c364d 100644
--- a/drivers/mailbox/mailbox-sti.c
+++ b/drivers/mailbox/mailbox-sti.c
@@ -36,7 +36,7 @@
#define MBOX_BASE(mdev, inst) ((mdev)->base + ((inst) * 4))
/**
- * STi Mailbox device data
+ * struct sti_mbox_device - STi Mailbox device data
*
* An IP Mailbox is currently composed of 4 instances
* Each instance is currently composed of 32 channels
@@ -60,7 +60,7 @@ struct sti_mbox_device {
};
/**
- * STi Mailbox platform specific configuration
+ * struct sti_mbox_pdata - STi Mailbox platform specific configuration
*
* @num_inst: Maximum number of instances in one HW Mailbox
* @num_chan: Maximum number of channel per instance
@@ -71,7 +71,7 @@ struct sti_mbox_pdata {
};
/**
- * STi Mailbox allocated channel information
+ * struct sti_channel - STi Mailbox allocated channel information
*
* @mdev: Pointer to parent Mailbox device
* @instance: Instance number channel resides in
--
2.17.1
[PATCH v4 4/7] clk: st: clkgen-pll: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
Reviewed-by: Patrice Chotard
---
v3: avoid CLK_IS_CRITICAL. PLL are enabled whenever necessary thanks to
child clock
v2: clk-s-a0-pll-odf-0 don't need to be CLK_IS_CRITICAL
mark several clock as CLK_IS_CRITICAL
drivers/clk/st/clkgen-pll.c | 120 +++-
1 file changed, 106 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index f6c56ca90c7d..b36e4d803636 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -57,6 +57,17 @@ struct clkgen_pll_data {
const struct clk_ops *ops;
};
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
+struct clkgen_pll_data_clks {
+ struct clkgen_pll_data *data;
+ const struct clkgen_clk_out *outputs;
+};
+
+
static const struct clk_ops stm_pll3200c32_ops;
static const struct clk_ops stm_pll3200c32_a9_ops;
static const struct clk_ops stm_pll4600c28_ops;
@@ -74,6 +85,28 @@ static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
.ops= _pll3200c32_ops,
};
+static const struct clkgen_pll_data_clks st_pll3200c32_cx_0_legacy_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_0,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_ax_0_clks[] = {
+ { .name = "clk-s-a0-pll-odf-0", },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_a0_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_0,
+ .outputs= st_pll3200c32_ax_0_clks,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_cx_0_clks[] = {
+ { .name = "clk-s-c0-pll0-odf-0", },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_c0_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_0,
+ .outputs= st_pll3200c32_cx_0_clks,
+};
+
static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
/* 407 C0 PLL1 */
.pdn_status = CLKGEN_FIELD(0x2c8, 0x1,8),
@@ -87,6 +120,19 @@ static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
.ops= _pll3200c32_ops,
};
+static const struct clkgen_pll_data_clks st_pll3200c32_cx_1_legacy_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_1,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_cx_1_clks[] = {
+ { .name = "clk-s-c0-pll1-odf-0", },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_c1_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_1,
+ .outputs= st_pll3200c32_cx_1_clks,
+};
+
static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
/* 407 A9 */
.pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
@@ -104,6 +150,15 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 =
{
.ops= _pll3200c32_a9_ops,
};
+static const struct clkgen_clk_out st_pll3200c32_407_a9_clks[] = {
+ { .name = "clockgen-a9-pll-odf", },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_407_a9_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_407_a9,
+ .outputs= st_pll3200c32_407_a9_clks,
+};
+
static struct clkgen_pll_data st_pll4600c28_418_a9 = {
/* 418 A9 */
.pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
@@ -120,6 +175,15 @@ static struct clkgen_pll_data st_pll4600c28_418_a9 = {
.ops= _pll4600c28_ops,
};
+static const struct clkgen_clk_out st_pll4600c28_418_a9_clks[] = {
+ { .name = "clockgen-a9-pll-odf", },
+};
+
+static const struct clkgen_pll_data_clks st_pll4600c28_418_a9_data = {
+ .data = (struct clkgen_pll_data *)_pll4600c28_418_a9,
+ .outputs= st_pll4600c28_418_a9_clks,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -684,7 +748,7 @@ static struct clk * __init clkgen_odf_register(const char
*parent_name,
static void __init clkgen_c32_pll_setup(struct device_node *np,
- struct clkgen_pll_data *data)
+ struct clkgen_pll_data_clks *datac)
{
struct clk *clk;
const char *parent_name, *pll_name;
@@ -704,14 +768,14 @@ static void __init clkgen_c32_pll_setup(struct
device_node *np,
of_clk_detect_critical(np, 0, _flags);
- clk = clkgen_pll_register(parent_name, data, pll_base, pll_flags,
-
[PATCH v3 13/13] ARM: dts: sti: Introduce 4KOpen (stih418-b2264) board
4KOpen (B2264) is a board based on the STMicroelectronics STiH418 soc:
- 2GB DDR
- HDMI
- Ethernet 1000-BaseT
- PCIe (mini PCIe connector)
- MicroSD slot
- USB2 and USB3 connectors
- Sata
- 40 pins GPIO header
Signed-off-by: Alain Volmat
---
v3: add 300MHz opp, add led, add ethernet pinctrl
v2: fix bootargs (removal of console=)
removal of rng11 node, moved into stih418.dtsi
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/stih418-b2264.dts | 151
2 files changed, 153 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/stih418-b2264.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8e5d4ab4e75e..3c1877627e91 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1061,7 +1061,8 @@ dtb-$(CONFIG_ARCH_STI) += \
stih407-b2120.dtb \
stih410-b2120.dtb \
stih410-b2260.dtb \
- stih418-b2199.dtb
+ stih418-b2199.dtb \
+ stih418-b2264.dtb
dtb-$(CONFIG_ARCH_STM32) += \
stm32f429-disco.dtb \
stm32f469-disco.dtb \
diff --git a/arch/arm/boot/dts/stih418-b2264.dts
b/arch/arm/boot/dts/stih418-b2264.dts
new file mode 100644
index ..a99604bebf8c
--- /dev/null
+++ b/arch/arm/boot/dts/stih418-b2264.dts
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2021 STMicroelectronics
+ * Author: Alain Volmat
+ */
+/dts-v1/;
+#include "stih418.dtsi"
+#include
+/ {
+ model = "STiH418 B2264";
+ compatible = "st,stih418-b2264", "st,stih418";
+
+ chosen {
+ stdout-path = _serial0;
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x4000 0xc000>;
+ };
+
+ cpus {
+ cpu@0 {
+ operating-points-v2 = <_opp_table>;
+ /* u-boot puts hpen in SBC dmem at 0xb8 offset */
+ cpu-release-addr = <0x94100b8>;
+ };
+ cpu@1 {
+ operating-points-v2 = <_opp_table>;
+ /* u-boot puts hpen in SBC dmem at 0xb8 offset */
+ cpu-release-addr = <0x94100b8>;
+ };
+ cpu@2 {
+ operating-points-v2 = <_opp_table>;
+ /* u-boot puts hpen in SBC dmem at 0xb8 offset */
+ cpu-release-addr = <0x94100b8>;
+ };
+ cpu@3 {
+ operating-points-v2 = <_opp_table>;
+ /* u-boot puts hpen in SBC dmem at 0xb8 offset */
+ cpu-release-addr = <0x94100b8>;
+ };
+ };
+
+ cpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <3>;
+ opp-microvolt = <784000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <5>;
+ opp-microvolt = <784000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <8>;
+ opp-microvolt = <784000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <784000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <15>;
+ opp-microvolt = <784000>;
+ };
+ };
+
+ aliases {
+ ttyAS0 = _serial0;
+ ethernet0 =
+ };
+
+ soc {
+ leds {
+ compatible = "gpio-leds";
+ green {
+ gpios = < 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ pin-controller-sbc@961f080 {
+ gmac1 {
+ rgmii1-0 {
+ st,pins {
+ rxd0 = < 4 ALT1 IN DE_IO
300 CLK_A>;
+ rxd1 = < 5 ALT1 IN DE_IO
300 CLK_A>;
+ rxd2 = < 6 ALT1 IN DE_IO
300 CLK_A>;
+ rxd3 = < 7 ALT1 IN DE_IO
300 CLK_A>;
+ rxdv = < 0 ALT1 IN DE_IO
300 CLK_A>;
+ };
+ };
+ };
+ };
+
+ };
+};
+
+ {
+ status = "
[PATCH v3 11/13] ARM: dts: sti: disable rng11 on the stih418 platform
The rng11 is not available on the STiH418 hence is disabled in the
stih418.dtsi
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi
index a05e2278b448..39a249983496 100644
--- a/arch/arm/boot/dts/stih418.dtsi
+++ b/arch/arm/boot/dts/stih418.dtsi
@@ -27,6 +27,10 @@
};
soc {
+ rng11: rng@8a8a000 {
+ status = "disabled";
+ };
+
usb2_picophy1: phy2@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
--
2.17.1
[PATCH v3 12/13] ARM: dts: sti: add the thermal sensor node within stih418
The STiH418 embedded the same sensor as the STiH410.
This commit adds the corresponding node, relying on the st_thermal
driver.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi
index 39a249983496..97eda4392fbe 100644
--- a/arch/arm/boot/dts/stih418.dtsi
+++ b/arch/arm/boot/dts/stih418.dtsi
@@ -108,5 +108,13 @@
assigned-clock-parents = <_s_c0_pll1 0>;
assigned-clock-rates = <2>;
};
+
+ thermal@91a {
+ compatible = "st,stih407-thermal";
+ reg = <0x91a 0x28>;
+ clock-names = "thermal";
+ clocks = <_sysin>;
+ interrupts = ;
+ };
};
};
--
2.17.1
[PATCH v3 10/13] ARM: dts: sti: add the spinor controller node within stih407-family
The STiH407 family (and further versions STiH410/STiH418) embedded
a serial flash controller allowing fast access to SPI-NOR.
This commit adds the corresponding node, relying on the st-spi-fsm
drivers.
Signed-off-by: Alain Volmat
---
v2: commit log improvement
arch/arm/boot/dts/stih407-family.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-family.dtsi
b/arch/arm/boot/dts/stih407-family.dtsi
index 23a1746f3baa..21f3347a91d6 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -616,6 +616,21 @@
st,lpc-mode = ;
};
+ spifsm: spifsm@9022000{
+ compatible = "st,spi-fsm";
+ reg = <0x9022000 0x1000>;
+ reg-names = "spi-fsm";
+ clocks = <_s_c0_flexgen CLK_FLASH_PROMIP>;
+ clock-names = "emi_clk";
+ pinctrl-names = "default";
+ pinctrl-0 = <_fsm>;
+ st,syscfg = <_core>;
+ st,boot-device-reg = <0x8c4>;
+ st,boot-device-spi = <0x68>;
+
+ status = "disabled";
+ };
+
sata0: sata@9b2 {
compatible = "st,ahci";
reg = <0x9b2 0x1000>;
--
2.17.1
[PATCH v3 09/13] ARM: dts: sti: update clkgen-fsyn entries in stih418-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418-clock.dtsi | 26 +++---
1 file changed, 3 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index d628e656458d..e84c476b83ed 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -94,11 +94,6 @@
reg = <0x9103000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
-"clk-s-c0-fs0-ch1",
-"clk-s-c0-fs0-ch2",
-"clk-s-c0-fs0-ch3";
};
clk_s_c0: clockgen-c@9103000 {
@@ -150,15 +145,10 @@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
-"clk-s-d0-fs0-ch1",
-"clk-s-d0-fs0-ch2",
-"clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
@@ -179,15 +169,10 @@
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
-"clk-s-d2-fs0-ch1",
-"clk-s-d2-fs0-ch2",
-"clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
@@ -210,15 +195,10 @@
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
-"clk-s-d3-fs0-ch1",
-"clk-s-d3-fs0-ch2",
-"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
--
2.17.1
[PATCH v3 08/13] ARM: dts: sti: update clkgen-fsyn entries in stih410-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih410-clock.dtsi | 27 +++
1 file changed, 3 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index 3aeabdd6e305..6b0e6d4477a3 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -93,12 +93,6 @@
reg = <0x9103000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
-"clk-s-c0-fs0-ch1",
-"clk-s-c0-fs0-ch2",
-"clk-s-c0-fs0-ch3";
- clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
clk_s_c0: clockgen-c@9103000 {
@@ -150,15 +144,10 @@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
-"clk-s-d0-fs0-ch1",
-"clk-s-d0-fs0-ch2",
-"clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
@@ -179,15 +168,10 @@
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
-"clk-s-d2-fs0-ch1",
-"clk-s-d2-fs0-ch2",
-"clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
@@ -210,15 +194,10 @@
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
-"clk-s-d3-fs0-ch1",
-"clk-s-d3-fs0-ch2",
-"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
--
2.17.1
[PATCH v3 07/13] ARM: dts: sti: update clkgen-fsyn entries in stih407-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih407-clock.dtsi | 27 +++
1 file changed, 3 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi
b/arch/arm/boot/dts/stih407-clock.dtsi
index 2603226a6ca8..9cce9541e26b 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -93,12 +93,6 @@
reg = <0x9103000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
-"clk-s-c0-fs0-ch1",
-"clk-s-c0-fs0-ch2",
-"clk-s-c0-fs0-ch3";
- clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
clk_s_c0: clockgen-c@9103000 {
@@ -150,15 +144,10 @@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
-"clk-s-d0-fs0-ch1",
-"clk-s-d0-fs0-ch2",
-"clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
@@ -179,15 +168,10 @@
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
-"clk-s-d2-fs0-ch1",
-"clk-s-d2-fs0-ch2",
-"clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
@@ -210,15 +194,10 @@
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
-"clk-s-d3-fs0-ch1",
-"clk-s-d3-fs0-ch2",
-"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
--
2.17.1
[PATCH v3 06/13] ARM: dts: sti: update clkgen-pll entries in stih418-clock
The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418-clock.dtsi | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 35d12979cdf4..d628e656458d 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -39,8 +39,6 @@
compatible = "st,stih418-clkgen-plla9";
clocks = <_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -75,11 +73,9 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -111,20 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
--
2.17.1
[PATCH v3 04/13] ARM: dts: sti: update clkgen-pll entries in stih407-clock
The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih407-clock.dtsi | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi
b/arch/arm/boot/dts/stih407-clock.dtsi
index ecd568777e5f..2603226a6ca8 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -36,8 +36,6 @@
compatible = "st,stih407-clkgen-plla9";
clocks = <_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -74,12 +72,9 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
- clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -112,21 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
- clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
--
2.17.1
[PATCH v3 05/13] ARM: dts: sti: update clkgen-pll entries in stih410-clock
The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih410-clock.dtsi | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index 04b0d7080353..3aeabdd6e305 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -39,8 +39,6 @@
compatible = "st,stih407-clkgen-plla9";
clocks = <_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -74,12 +72,9 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
- clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -112,21 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
- clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
--
2.17.1
[PATCH v3 03/13] ARM: dts: sti: update flexgen compatible within stih410-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih410-clock.dtsi | 95 ++--
1 file changed, 6 insertions(+), 89 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index 81a8c25d7ba5..04b0d7080353 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -83,16 +83,12 @@
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih410-a0";
#clock-cells = <1>;
clocks = <_s_a0_pll 0>,
<_sysin>;
-
- clock-output-names = "clk-ic-lmi0",
-"clk-ic-lmi1";
- clock-critical = ;
};
};
@@ -135,7 +131,7 @@
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih410-c0";
clocks = <_s_c0_pll0 0>,
<_s_c0_pll1 0>,
@@ -145,52 +141,6 @@
<_s_c0_quadfs 3>,
<_sysin>;
- clock-output-names = "clk-icn-gpu",
-"clk-fdma",
-"clk-nand",
-"clk-hva",
-"clk-proc-stfe",
-"clk-proc-tp",
-"clk-rx-icn-dmu",
-"clk-rx-icn-hva",
-"clk-icn-cpu",
-"clk-tx-icn-dmu",
-"clk-mmc-0",
-"clk-mmc-1",
-"clk-jpegdec",
-"clk-ext2fa9",
-"clk-ic-bdisp-0",
-"clk-ic-bdisp-1",
-"clk-pp-dmu",
-"clk-vid-dmu",
-"clk-dss-lpc",
-"clk-st231-aud-0",
-"clk-st231-gp-1",
-"clk-st231-dmu",
-"clk-icn-lmi",
-"clk-tx-icn-disp-1",
-"clk-icn-sbc",
-"clk-stfe-frc2",
-"clk-eth-phy",
-"clk-eth-ref-phyclk",
-"clk-flash-promip",
-"clk-main-disp",
-"clk-aux-disp",
-"clk-compo-dvp",
-"clk-tx-icn-hades",
-"clk-rx-icn-hades",
-"clk-icn-reg-16",
-"clk-pp-hades",
-"clk-clust-hades",
-"clk-hwpe-hades",
-"clk-fc-hades";
-
[PATCH v3 01/13] ARM: dts: sti: update flexgen compatible within stih418-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418-clock.dtsi | 96 ++--
1 file changed, 5 insertions(+), 91 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 8fa092462102..35d12979cdf4 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -83,15 +83,12 @@
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih410-a0";
#clock-cells = <1>;
clocks = <_s_a0_pll 0>,
<_sysin>;
-
- clock-output-names = "clk-ic-lmi0",
-"clk-ic-lmi1";
};
};
@@ -132,7 +129,7 @@
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih418-c0";
clocks = <_s_c0_pll0 0>,
<_s_c0_pll1 0>,
@@ -142,49 +139,6 @@
<_s_c0_quadfs 3>,
<_sysin>;
- clock-output-names = "clk-icn-gpu",
-"clk-fdma",
-"clk-nand",
-"clk-hva",
-"clk-proc-stfe",
-"clk-tp",
-"clk-rx-icn-dmu",
-"clk-rx-icn-hva",
-"clk-icn-cpu",
-"clk-tx-icn-dmu",
-"clk-mmc-0",
-"clk-mmc-1",
-"clk-jpegdec",
-"clk-icn-reg",
-"clk-proc-bdisp-0",
-"clk-proc-bdisp-1",
-"clk-pp-dmu",
-"clk-vid-dmu",
-"clk-dss-lpc",
-"clk-st231-aud-0",
-"clk-st231-gp-1",
-"clk-st231-dmu",
-"clk-icn-lmi",
-"clk-tx-icn-1",
-"clk-icn-sbc",
-"clk-stfe-frc2",
-"clk-eth-phyref",
-"clk-eth-ref-phyclk",
-"clk-flash-promip",
-"clk-main-disp",
-"clk-aux-disp",
-"clk-compo-dvp",
-"clk-tx-icn-hades",
-"clk-rx-icn-hades",
-"clk-icn-reg-16",
-"clk-pp-hevc",
-"clk-clust-hevc",
-"clk-hwpe-hevc",
-"clk-fc-hevc",
-
[PATCH v3 02/13] ARM: dts: sti: update flexgen compatible within stih407-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih407-clock.dtsi | 85 ++--
1 file changed, 6 insertions(+), 79 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi
b/arch/arm/boot/dts/stih407-clock.dtsi
index 1ab40db7c91a..ecd568777e5f 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -83,15 +83,12 @@
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih407-a0";
#clock-cells = <1>;
clocks = <_s_a0_pll 0>,
<_sysin>;
-
- clock-output-names = "clk-ic-lmi0";
- clock-critical = ;
};
};
@@ -134,7 +131,7 @@
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih407-c0";
clocks = <_s_c0_pll0 0>,
<_s_c0_pll1 0>,
@@ -144,45 +141,6 @@
<_s_c0_quadfs 3>,
<_sysin>;
- clock-output-names = "clk-icn-gpu",
-"clk-fdma",
-"clk-nand",
-"clk-hva",
-"clk-proc-stfe",
-"clk-proc-tp",
-"clk-rx-icn-dmu",
-"clk-rx-icn-hva",
-"clk-icn-cpu",
-"clk-tx-icn-dmu",
-"clk-mmc-0",
-"clk-mmc-1",
-"clk-jpegdec",
-"clk-ext2fa9",
-"clk-ic-bdisp-0",
-"clk-ic-bdisp-1",
-"clk-pp-dmu",
-"clk-vid-dmu",
-"clk-dss-lpc",
-"clk-st231-aud-0",
-"clk-st231-gp-1",
-"clk-st231-dmu",
-"clk-icn-lmi",
-"clk-tx-icn-disp-1",
-"clk-icn-sbc",
-"clk-stfe-frc2",
-"clk-eth-phy",
-"clk-eth-ref-phyclk",
-"clk-flash-promip",
-"clk-main-disp",
-"clk-aux-disp",
-"clk-compo-dvp";
- clock-critical = ,
-,
-,
-,
-,
-;
-
/*
* ARM Peripheral clock for timers
*/
@@ -219,18 +177,13 @@
clk_s_d0_flexgen: clk-s-d0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen-audio",
[PATCH v3 00/13] Introduction of STiH418 based 4KOpen board
This serie introduces the 4KOpen (stih418-b2264) board based on a stih418 soc. Since it is the first board to use the spi-fsm SPI NOR controller available since stih407, the controller is also added within the stih407-family DT. It also contains a fix within the stih418 DT since the rng11 is not available on this platform and is thus disabled. sti dts updates related to clocks are also added within the serie in order to use new sti clock driver compatible to avoid having to declare clock output names within the device-tree. Those 9 patches were initially pushed together with the clock driver updates but have been pulled out of that serie to only push the driver updates via the clock tree. [1] For that reason, this serie should be applied on top of the serie [clk: st: embed clock outputs within drivers]. [1] https://lore.kernel.org/linux-clk/161706966003.3012082.13602640109563561...@swboyd.mtv.corp.google.com/ Alain Volmat (13): ARM: dts: sti: update flexgen compatible within stih418-clock ARM: dts: sti: update flexgen compatible within stih407-clock ARM: dts: sti: update flexgen compatible within stih410-clock ARM: dts: sti: update clkgen-pll entries in stih407-clock ARM: dts: sti: update clkgen-pll entries in stih410-clock ARM: dts: sti: update clkgen-pll entries in stih418-clock ARM: dts: sti: update clkgen-fsyn entries in stih407-clock ARM: dts: sti: update clkgen-fsyn entries in stih410-clock ARM: dts: sti: update clkgen-fsyn entries in stih418-clock ARM: dts: sti: add the spinor controller node within stih407-family ARM: dts: sti: disable rng11 on the stih418 platform ARM: dts: sti: add the thermal sensor node within stih418 ARM: dts: sti: Introduce 4KOpen (stih418-b2264) board v3: update of the stih418-b2264 dts addition of stih407/stih410/stih418 clock updates arch/arm/boot/dts/Makefile| 3 +- arch/arm/boot/dts/stih407-clock.dtsi | 128 ++ arch/arm/boot/dts/stih407-family.dtsi | 15 +++ arch/arm/boot/dts/stih410-clock.dtsi | 138 ++- arch/arm/boot/dts/stih418-b2264.dts | 151 ++ arch/arm/boot/dts/stih418-clock.dtsi | 136 ++- arch/arm/boot/dts/stih418.dtsi| 12 ++ 7 files changed, 215 insertions(+), 368 deletions(-) create mode 100644 arch/arm/boot/dts/stih418-b2264.dts -- 2.17.1
[PATCH v4 5/7] dt-bindings: clock: st: clkgen-pll: add new introduced compatible
New compatible are added, supporting various kind of clkgen-pll used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat Acked-by: Rob Herring --- Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt index f207053e0550..d0fa1e02d06d 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt @@ -10,7 +10,10 @@ Required properties: - compatible : shall be: "st,clkgen-pll0" + "st,clkgen-pll0-a0" + "st,clkgen-pll0-c0" "st,clkgen-pll1" + "st,clkgen-pll1-c0" "st,stih407-clkgen-plla9" "st,stih418-clkgen-plla9" -- 2.17.1
[PATCH v4 6/7] clk: st: clkgen-fsyn: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
Reviewed-by: Patrice Chotard
---
v2: clk-s-c0-fs0-ch0 do not need to be CLK_IS_CRITICAL
drivers/clk/st/clkgen-fsyn.c | 113 +++
1 file changed, 101 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index dd6062e043e0..164285d6be97 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -66,6 +66,16 @@ struct clkgen_quadfs_data {
unsigned long *);
};
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
+struct clkgen_quadfs_data_clks {
+ struct clkgen_quadfs_data *data;
+ const struct clkgen_clk_out *outputs;
+};
+
static const struct clk_ops st_quadfs_pll_c32_ops;
static int clk_fs660c32_dig_get_params(unsigned long input,
@@ -115,6 +125,18 @@ static const struct clkgen_quadfs_data st_fs660c32_C = {
.get_rate = clk_fs660c32_dig_get_rate,
};
+static const struct clkgen_clk_out st_fs660c32_C_clks[] = {
+ { .name = "clk-s-c0-fs0-ch0", },
+ { .name = "clk-s-c0-fs0-ch1", },
+ { .name = "clk-s-c0-fs0-ch2", },
+ { .name = "clk-s-c0-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_C_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_C,
+ .outputs= st_fs660c32_C_clks,
+};
+
static const struct clkgen_quadfs_data st_fs660c32_D = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
@@ -156,6 +178,46 @@ static const struct clkgen_quadfs_data st_fs660c32_D = {
.get_params = clk_fs660c32_dig_get_params,
.get_rate = clk_fs660c32_dig_get_rate,};
+static const struct clkgen_quadfs_data_clks st_fs660c32_D_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_D,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D0_clks[] = {
+ { .name = "clk-s-d0-fs0-ch0", },
+ { .name = "clk-s-d0-fs0-ch1", },
+ { .name = "clk-s-d0-fs0-ch2", },
+ { .name = "clk-s-d0-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D0_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_D,
+ .outputs= st_fs660c32_D0_clks,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D2_clks[] = {
+ { .name = "clk-s-d2-fs0-ch0", },
+ { .name = "clk-s-d2-fs0-ch1", },
+ { .name = "clk-s-d2-fs0-ch2", },
+ { .name = "clk-s-d2-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D2_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_D,
+ .outputs= st_fs660c32_D2_clks,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D3_clks[] = {
+ { .name = "clk-s-d3-fs0-ch0", },
+ { .name = "clk-s-d3-fs0-ch1", },
+ { .name = "clk-s-d3-fs0-ch2", },
+ { .name = "clk-s-d3-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D3_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_D,
+ .outputs= st_fs660c32_D3_clks,
+};
+
/**
* DOC: A Frequency Synthesizer that multiples its input clock by a fixed
factor
*
@@ -857,7 +919,7 @@ static struct clk * __init st_clk_register_quadfs_fsynth(
static void __init st_of_create_quadfs_fsynths(
struct device_node *np, const char *pll_name,
- struct clkgen_quadfs_data *quadfs, void __iomem *reg,
+ struct clkgen_quadfs_data_clks *quadfs, void __iomem *reg,
spinlock_t *lock)
{
struct clk_onecell_data *clk_data;
@@ -881,9 +943,15 @@ static void __init st_of_create_quadfs_fsynths(
const char *clk_name;
unsigned long flags = 0;
- if (of_property_read_string_index(np, "clock-output-names",
- fschan, _name)) {
- break;
+ if (quadfs->outputs) {
+ clk_name = quadfs->outputs[fschan].name;
+ flags = quadfs->outputs[fschan].flags;
+ } else {
+ if (of_property_read_string_index(np,
+ "clock-output-names",
+ fschan
[PATCH v4 7/7] dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible
New compatible are added, supporting various kind of clkgen-fsyn used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat --- Documentation/devicetree/bindings/clock/st/st,quadfs.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt index d93d49342e60..c4ba2adb0b4f 100644 --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt +++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt @@ -12,6 +12,9 @@ This binding uses the common clock binding[1]. Required properties: - compatible : shall be: "st,quadfs" + "st,quadfs-d0" + "st,quadfs-d2" + "st,quadfs-d3" "st,quadfs-pll" -- 2.17.1
[PATCH v4 3/7] dt-bindings: clock: st: flexgen: add new introduced compatible
New compatible are added, supporting various kind of flexgen in STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat Acked-by: Rob Herring --- .../devicetree/bindings/clock/st/st,flexgen.txt| 10 ++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt index 7ff77fc57dff..55a18939bddd 100644 --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt @@ -64,6 +64,16 @@ Required properties: audio use case) "st,flexgen-video", "st,flexgen" (enable clock propagation on parent and activate synchronous mode) + "st,flexgen-stih407-a0" + "st,flexgen-stih410-a0" + "st,flexgen-stih407-c0" + "st,flexgen-stih410-c0" + "st,flexgen-stih418-c0" + "st,flexgen-stih407-d0" + "st,flexgen-stih410-d0" + "st,flexgen-stih407-d2" + "st,flexgen-stih418-d2" + "st,flexgen-stih407-d3" - #clock-cells : from common clock binding; shall be set to 1 (multiple clock outputs). -- 2.17.1
[PATCH v4 2/7] clk: st: flexgen: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
Reviewed-by: Patrice Chotard
---
v4: for stih410, set the clk-icn-reg-16 as critical
v3: add comments about CLK_IS_CRITICAL reason
don't put clk-proc-stfe as CLK_IS_CRITICAL
v2: add some missing clock as CLK_IS_CRITICAL
drivers/clk/st/clk-flexgen.c | 367 +--
1 file changed, 353 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 55873d4b7603..7ae4f656191e 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -16,9 +16,16 @@
#include
#include
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
struct clkgen_data {
unsigned long flags;
bool mode;
+ const struct clkgen_clk_out *outputs;
+ const unsigned int outputs_nb;
};
struct flexgen {
@@ -295,6 +302,290 @@ static const struct clkgen_data clkgen_video = {
.mode = 1,
};
+static const struct clkgen_clk_out clkgen_stih407_a0_clk_out[] = {
+ /* This clk needs to be on so that memory interface is accessible */
+ { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_data clkgen_stih407_a0 = {
+ .outputs = clkgen_stih407_a0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih407_a0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih410_a0_clk_out[] = {
+ /* Those clks need to be on so that memory interface is accessible */
+ { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-lmi1", .flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_data clkgen_stih410_a0 = {
+ .outputs = clkgen_stih410_a0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih410_a0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih407_c0_clk_out[] = {
+ { .name = "clk-icn-gpu", },
+ { .name = "clk-fdma", },
+ { .name = "clk-nand", },
+ { .name = "clk-hva", },
+ { .name = "clk-proc-stfe", },
+ { .name = "clk-proc-tp", },
+ { .name = "clk-rx-icn-dmu", },
+ { .name = "clk-rx-icn-hva", },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-mmc-0", },
+ { .name = "clk-mmc-1", },
+ { .name = "clk-jpegdec", },
+ /* This clk needs to be on to keep A9 running */
+ { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-bdisp-0", },
+ { .name = "clk-ic-bdisp-1", },
+ { .name = "clk-pp-dmu", },
+ { .name = "clk-vid-dmu", },
+ { .name = "clk-dss-lpc", },
+ { .name = "clk-st231-aud-0", },
+ { .name = "clk-st231-gp-1", },
+ { .name = "clk-st231-dmu", },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-tx-icn-disp-1", },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-stfe-frc2", },
+ { .name = "clk-eth-phy", },
+ { .name = "clk-eth-ref-phyclk", },
+ { .name = "clk-flash-promip", },
+ { .name = "clk-main-disp", },
+ { .name = "clk-aux-disp", },
+ { .name = "clk-compo-dvp", },
+};
+
+static const struct clkgen_data clkgen_stih407_c0 = {
+ .outputs = clkgen_stih407_c0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih407_c0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih410_c0_clk_out[] = {
+ { .name = "clk-icn-gpu", },
+ { .name = "clk-fdma", },
+ { .name = "clk-nand", },
+ { .name = "clk-hva", },
+ { .name = "clk-proc-stfe", },
+ { .name = "clk-proc-tp", },
+ { .name = "clk-rx-icn-dmu", },
+ { .name = "clk-rx-icn-hva", },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = &
[PATCH v4 1/7] clk: st: clkgen-pll: remove unused variable of struct clkgen_pll
ODF field within the struct clkgen_pll is never used by the driver
and can thus be removed.
Signed-off-by: Alain Volmat
Reviewed-by: Patrice Chotard
---
v3: s/used/unused within the subject
drivers/clk/st/clkgen-pll.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 119c5b33080c..f6c56ca90c7d 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -146,7 +146,6 @@ struct clkgen_pll {
u32 ndiv;
u32 idf;
- u32 odf;
u32 cp;
};
--
2.17.1
[PATCH v4 0/7] clk: st: embed clock outputs within drivers
Most of ST clock drivers used by STi platform are updated in order to introduce clock outputs informations within each drivers and thus allow to avoid having to rely on clock-output-names properties within DT clock nodes. For that purpose, drivers are updated to allow handling both modes (with or without clock-output-names). Once all DT will have been updated, the legacy mode could be removed from the drivers. This will also allow, once all STi DT will be corrected, to remove the of_clk_detect_critical API from clk core code since STi clock drivers are the only drivers using this API. Alain Volmat (7): clk: st: clkgen-pll: remove unused variable of struct clkgen_pll clk: st: flexgen: embed soc clock outputs within compatible data dt-bindings: clock: st: flexgen: add new introduced compatible clk: st: clkgen-pll: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-pll: add new introduced compatible clk: st: clkgen-fsyn: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible .../bindings/clock/st/st,clkgen-pll.txt | 3 + .../bindings/clock/st/st,flexgen.txt | 10 + .../bindings/clock/st/st,quadfs.txt | 3 + drivers/clk/st/clk-flexgen.c | 367 +- drivers/clk/st/clkgen-fsyn.c | 113 +- drivers/clk/st/clkgen-pll.c | 121 +- 6 files changed, 576 insertions(+), 41 deletions(-) --- v4: - add an additional CLK_IS_CRITICAL within flexgen driver v3: - removal some useless CLK_IS_CRITICAL and add some comments - only keep clk drivers/binding patches within the serie -- 2.17.1
[PATCH v3 7/7] dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible
New compatible are added, supporting various kind of clkgen-fsyn used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat --- Documentation/devicetree/bindings/clock/st/st,quadfs.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt index d93d49342e60..c4ba2adb0b4f 100644 --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt +++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt @@ -12,6 +12,9 @@ This binding uses the common clock binding[1]. Required properties: - compatible : shall be: "st,quadfs" + "st,quadfs-d0" + "st,quadfs-d2" + "st,quadfs-d3" "st,quadfs-pll" -- 2.17.1
[PATCH v3 6/7] clk: st: clkgen-fsyn: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
v2: clk-s-c0-fs0-ch0 do not need to be CLK_IS_CRITICAL
drivers/clk/st/clkgen-fsyn.c | 113 +++
1 file changed, 101 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index dd6062e043e0..164285d6be97 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -66,6 +66,16 @@ struct clkgen_quadfs_data {
unsigned long *);
};
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
+struct clkgen_quadfs_data_clks {
+ struct clkgen_quadfs_data *data;
+ const struct clkgen_clk_out *outputs;
+};
+
static const struct clk_ops st_quadfs_pll_c32_ops;
static int clk_fs660c32_dig_get_params(unsigned long input,
@@ -115,6 +125,18 @@ static const struct clkgen_quadfs_data st_fs660c32_C = {
.get_rate = clk_fs660c32_dig_get_rate,
};
+static const struct clkgen_clk_out st_fs660c32_C_clks[] = {
+ { .name = "clk-s-c0-fs0-ch0", },
+ { .name = "clk-s-c0-fs0-ch1", },
+ { .name = "clk-s-c0-fs0-ch2", },
+ { .name = "clk-s-c0-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_C_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_C,
+ .outputs= st_fs660c32_C_clks,
+};
+
static const struct clkgen_quadfs_data st_fs660c32_D = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
@@ -156,6 +178,46 @@ static const struct clkgen_quadfs_data st_fs660c32_D = {
.get_params = clk_fs660c32_dig_get_params,
.get_rate = clk_fs660c32_dig_get_rate,};
+static const struct clkgen_quadfs_data_clks st_fs660c32_D_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_D,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D0_clks[] = {
+ { .name = "clk-s-d0-fs0-ch0", },
+ { .name = "clk-s-d0-fs0-ch1", },
+ { .name = "clk-s-d0-fs0-ch2", },
+ { .name = "clk-s-d0-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D0_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_D,
+ .outputs= st_fs660c32_D0_clks,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D2_clks[] = {
+ { .name = "clk-s-d2-fs0-ch0", },
+ { .name = "clk-s-d2-fs0-ch1", },
+ { .name = "clk-s-d2-fs0-ch2", },
+ { .name = "clk-s-d2-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D2_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_D,
+ .outputs= st_fs660c32_D2_clks,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D3_clks[] = {
+ { .name = "clk-s-d3-fs0-ch0", },
+ { .name = "clk-s-d3-fs0-ch1", },
+ { .name = "clk-s-d3-fs0-ch2", },
+ { .name = "clk-s-d3-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D3_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_D,
+ .outputs= st_fs660c32_D3_clks,
+};
+
/**
* DOC: A Frequency Synthesizer that multiples its input clock by a fixed
factor
*
@@ -857,7 +919,7 @@ static struct clk * __init st_clk_register_quadfs_fsynth(
static void __init st_of_create_quadfs_fsynths(
struct device_node *np, const char *pll_name,
- struct clkgen_quadfs_data *quadfs, void __iomem *reg,
+ struct clkgen_quadfs_data_clks *quadfs, void __iomem *reg,
spinlock_t *lock)
{
struct clk_onecell_data *clk_data;
@@ -881,9 +943,15 @@ static void __init st_of_create_quadfs_fsynths(
const char *clk_name;
unsigned long flags = 0;
- if (of_property_read_string_index(np, "clock-output-names",
- fschan, _name)) {
- break;
+ if (quadfs->outputs) {
+ clk_name = quadfs->outputs[fschan].name;
+ flags = quadfs->outputs[fschan].flags;
+ } else {
+ if (of_property_read_string_index(np,
+ "clock-output-names",
+ fschan, _name))
+
[PATCH v3 5/7] dt-bindings: clock: st: clkgen-pll: add new introduced compatible
New compatible are added, supporting various kind of clkgen-pll used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat Acked-by: Rob Herring --- Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt index f207053e0550..d0fa1e02d06d 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt @@ -10,7 +10,10 @@ Required properties: - compatible : shall be: "st,clkgen-pll0" + "st,clkgen-pll0-a0" + "st,clkgen-pll0-c0" "st,clkgen-pll1" + "st,clkgen-pll1-c0" "st,stih407-clkgen-plla9" "st,stih418-clkgen-plla9" -- 2.17.1
[PATCH v3 3/7] dt-bindings: clock: st: flexgen: add new introduced compatible
New compatible are added, supporting various kind of flexgen in STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat Acked-by: Rob Herring --- .../devicetree/bindings/clock/st/st,flexgen.txt| 10 ++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt index 7ff77fc57dff..55a18939bddd 100644 --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt @@ -64,6 +64,16 @@ Required properties: audio use case) "st,flexgen-video", "st,flexgen" (enable clock propagation on parent and activate synchronous mode) + "st,flexgen-stih407-a0" + "st,flexgen-stih410-a0" + "st,flexgen-stih407-c0" + "st,flexgen-stih410-c0" + "st,flexgen-stih418-c0" + "st,flexgen-stih407-d0" + "st,flexgen-stih410-d0" + "st,flexgen-stih407-d2" + "st,flexgen-stih418-d2" + "st,flexgen-stih407-d3" - #clock-cells : from common clock binding; shall be set to 1 (multiple clock outputs). -- 2.17.1
[PATCH v3 4/7] clk: st: clkgen-pll: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
v3: avoid CLK_IS_CRITICAL. PLL are enabled whenever necessary thanks to
child clock
v2: clk-s-a0-pll-odf-0 don't need to be CLK_IS_CRITICAL
mark several clock as CLK_IS_CRITICAL
drivers/clk/st/clkgen-pll.c | 120 +++-
1 file changed, 106 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index f6c56ca90c7d..b36e4d803636 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -57,6 +57,17 @@ struct clkgen_pll_data {
const struct clk_ops *ops;
};
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
+struct clkgen_pll_data_clks {
+ struct clkgen_pll_data *data;
+ const struct clkgen_clk_out *outputs;
+};
+
+
static const struct clk_ops stm_pll3200c32_ops;
static const struct clk_ops stm_pll3200c32_a9_ops;
static const struct clk_ops stm_pll4600c28_ops;
@@ -74,6 +85,28 @@ static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
.ops= _pll3200c32_ops,
};
+static const struct clkgen_pll_data_clks st_pll3200c32_cx_0_legacy_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_0,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_ax_0_clks[] = {
+ { .name = "clk-s-a0-pll-odf-0", },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_a0_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_0,
+ .outputs= st_pll3200c32_ax_0_clks,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_cx_0_clks[] = {
+ { .name = "clk-s-c0-pll0-odf-0", },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_c0_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_0,
+ .outputs= st_pll3200c32_cx_0_clks,
+};
+
static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
/* 407 C0 PLL1 */
.pdn_status = CLKGEN_FIELD(0x2c8, 0x1,8),
@@ -87,6 +120,19 @@ static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
.ops= _pll3200c32_ops,
};
+static const struct clkgen_pll_data_clks st_pll3200c32_cx_1_legacy_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_1,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_cx_1_clks[] = {
+ { .name = "clk-s-c0-pll1-odf-0", },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_c1_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_1,
+ .outputs= st_pll3200c32_cx_1_clks,
+};
+
static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
/* 407 A9 */
.pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
@@ -104,6 +150,15 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 =
{
.ops= _pll3200c32_a9_ops,
};
+static const struct clkgen_clk_out st_pll3200c32_407_a9_clks[] = {
+ { .name = "clockgen-a9-pll-odf", },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_407_a9_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_407_a9,
+ .outputs= st_pll3200c32_407_a9_clks,
+};
+
static struct clkgen_pll_data st_pll4600c28_418_a9 = {
/* 418 A9 */
.pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
@@ -120,6 +175,15 @@ static struct clkgen_pll_data st_pll4600c28_418_a9 = {
.ops= _pll4600c28_ops,
};
+static const struct clkgen_clk_out st_pll4600c28_418_a9_clks[] = {
+ { .name = "clockgen-a9-pll-odf", },
+};
+
+static const struct clkgen_pll_data_clks st_pll4600c28_418_a9_data = {
+ .data = (struct clkgen_pll_data *)_pll4600c28_418_a9,
+ .outputs= st_pll4600c28_418_a9_clks,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -684,7 +748,7 @@ static struct clk * __init clkgen_odf_register(const char
*parent_name,
static void __init clkgen_c32_pll_setup(struct device_node *np,
- struct clkgen_pll_data *data)
+ struct clkgen_pll_data_clks *datac)
{
struct clk *clk;
const char *parent_name, *pll_name;
@@ -704,14 +768,14 @@ static void __init clkgen_c32_pll_setup(struct
device_node *np,
of_clk_detect_critical(np, 0, _flags);
- clk = clkgen_pll_register(parent_name, data, pll_base, pll_flags,
- np->name, data->loc
[PATCH v3 2/7] clk: st: flexgen: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
v3: add comments about CLK_IS_CRITICAL reason
don't put clk-proc-stfe as CLK_IS_CRITICAL
v2: add some missing clock as CLK_IS_CRITICAL
drivers/clk/st/clk-flexgen.c | 366 +--
1 file changed, 352 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 55873d4b7603..69711c6c47a4 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -16,9 +16,16 @@
#include
#include
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
struct clkgen_data {
unsigned long flags;
bool mode;
+ const struct clkgen_clk_out *outputs;
+ const unsigned int outputs_nb;
};
struct flexgen {
@@ -295,6 +302,289 @@ static const struct clkgen_data clkgen_video = {
.mode = 1,
};
+static const struct clkgen_clk_out clkgen_stih407_a0_clk_out[] = {
+ /* This clk needs to be on so that memory interface is accessible */
+ { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_data clkgen_stih407_a0 = {
+ .outputs = clkgen_stih407_a0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih407_a0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih410_a0_clk_out[] = {
+ /* Those clks need to be on so that memory interface is accessible */
+ { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-lmi1", .flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_data clkgen_stih410_a0 = {
+ .outputs = clkgen_stih410_a0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih410_a0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih407_c0_clk_out[] = {
+ { .name = "clk-icn-gpu", },
+ { .name = "clk-fdma", },
+ { .name = "clk-nand", },
+ { .name = "clk-hva", },
+ { .name = "clk-proc-stfe", },
+ { .name = "clk-proc-tp", },
+ { .name = "clk-rx-icn-dmu", },
+ { .name = "clk-rx-icn-hva", },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-mmc-0", },
+ { .name = "clk-mmc-1", },
+ { .name = "clk-jpegdec", },
+ /* This clk needs to be on to keep A9 running */
+ { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-bdisp-0", },
+ { .name = "clk-ic-bdisp-1", },
+ { .name = "clk-pp-dmu", },
+ { .name = "clk-vid-dmu", },
+ { .name = "clk-dss-lpc", },
+ { .name = "clk-st231-aud-0", },
+ { .name = "clk-st231-gp-1", },
+ { .name = "clk-st231-dmu", },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-tx-icn-disp-1", },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-stfe-frc2", },
+ { .name = "clk-eth-phy", },
+ { .name = "clk-eth-ref-phyclk", },
+ { .name = "clk-flash-promip", },
+ { .name = "clk-main-disp", },
+ { .name = "clk-aux-disp", },
+ { .name = "clk-compo-dvp", },
+};
+
+static const struct clkgen_data clkgen_stih407_c0 = {
+ .outputs = clkgen_stih407_c0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih407_c0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih410_c0_clk_out[] = {
+ { .name = "clk-icn-gpu", },
+ { .name = "clk-fdma", },
+ { .name = "clk-nand", },
+ { .name = "clk-hva", },
+ { .name = "clk-proc-stfe", },
+ { .name = "clk-proc-tp", },
+ { .name = "clk-rx-icn-dmu", },
+ { .name = "clk-rx-icn-hva", },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
+ /* This clk ne
[PATCH v3 1/7] clk: st: clkgen-pll: remove unused variable of struct clkgen_pll
ODF field within the struct clkgen_pll is never used by the driver
and can thus be removed.
Signed-off-by: Alain Volmat
---
v3: s/used/unused within the subject
drivers/clk/st/clkgen-pll.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 119c5b33080c..f6c56ca90c7d 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -146,7 +146,6 @@ struct clkgen_pll {
u32 ndiv;
u32 idf;
- u32 odf;
u32 cp;
};
--
2.17.1
[PATCH v3 0/7] clk: st: embed clock outputs within drivers
Most of ST clock drivers used by STi platform are updated in order to introduce clock outputs informations within each drivers and thus allow to avoid having to rely on clock-output-names properties within DT clock nodes. For that purpose, drivers are updated to allow handling both modes (with or without clock-output-names). Once all DT will have been updated, the legacy mode could be removed from the drivers. This will also allow, once all STi DT will be corrected, to remove the of_clk_detect_critical API from clk core code since STi clock drivers are the only drivers using this API. This serie also contains modifications within STi DTS in order to use the newly introduced compatible and remove clock-output-names properties. Alain Volmat (7): clk: st: clkgen-pll: remove used variable of struct clkgen_pll clk: st: flexgen: embed soc clock outputs within compatible data dt-bindings: clock: st: flexgen: add new introduced compatible clk: st: clkgen-pll: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-pll: add new introduced compatible clk: st: clkgen-fsyn: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible .../bindings/clock/st/st,clkgen-pll.txt | 3 + .../bindings/clock/st/st,flexgen.txt | 10 + .../bindings/clock/st/st,quadfs.txt | 3 + drivers/clk/st/clk-flexgen.c | 366 +- drivers/clk/st/clkgen-fsyn.c | 113 +- drivers/clk/st/clkgen-pll.c | 121 +- 6 files changed, 575 insertions(+), 41 deletions(-) --- v3: - removal some useless CLK_IS_CRITICAL and add some comments - only keep clk drivers/binding patches within the serie v2: fix drivers to update some clocks as CLK_IS_CRITICAL -- 2.17.1
[PATCH v3 2/2] i2c: stm32f7: add SMBus-Alert support
Add support for the SMBus-Alert protocol to the STM32F7 that has
dedicated control and status logic.
If SMBus-Alert is used, the SMBALERT# pin must be configured as alternate
function for I2C Alert.
Signed-off-by: Alain Volmat
Reviewed-by: Pierre-Yves MORDRET
---
v2: - rely on st,smbus-alert binding instead of smbus
---
drivers/i2c/busses/i2c-stm32f7.c | 73
1 file changed, 73 insertions(+)
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index c62c815b88eb..bd840cd2b9e4 100644
--- a/drivers/i2c/busses/i2c-stm32f7.c
+++ b/drivers/i2c/busses/i2c-stm32f7.c
@@ -51,6 +51,7 @@
/* STM32F7 I2C control 1 */
#define STM32F7_I2C_CR1_PECEN BIT(23)
+#define STM32F7_I2C_CR1_ALERTENBIT(22)
#define STM32F7_I2C_CR1_SMBHEN BIT(20)
#define STM32F7_I2C_CR1_WUPEN BIT(18)
#define STM32F7_I2C_CR1_SBCBIT(16)
@@ -125,6 +126,7 @@
(((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
#define STM32F7_I2C_ISR_DIRBIT(16)
#define STM32F7_I2C_ISR_BUSY BIT(15)
+#define STM32F7_I2C_ISR_ALERT BIT(13)
#define STM32F7_I2C_ISR_PECERR BIT(11)
#define STM32F7_I2C_ISR_ARLO BIT(9)
#define STM32F7_I2C_ISR_BERR BIT(8)
@@ -138,6 +140,7 @@
#define STM32F7_I2C_ISR_TXEBIT(0)
/* STM32F7 I2C Interrupt Clear */
+#define STM32F7_I2C_ICR_ALERTCFBIT(13)
#define STM32F7_I2C_ICR_PECCF BIT(11)
#define STM32F7_I2C_ICR_ARLOCF BIT(9)
#define STM32F7_I2C_ICR_BERRCF BIT(8)
@@ -283,6 +286,17 @@ struct stm32f7_i2c_msg {
u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
};
+/**
+ * struct stm32f7_i2c_alert - SMBus alert specific data
+ * @setup: platform data for the smbus_alert i2c client
+ * @ara: I2C slave device used to respond to the SMBus Alert with Alert
+ * Response Address
+ */
+struct stm32f7_i2c_alert {
+ struct i2c_smbus_alert_setup setup;
+ struct i2c_client *ara;
+};
+
/**
* struct stm32f7_i2c_dev - private data of the controller
* @adap: I2C adapter for this controller
@@ -312,6 +326,7 @@ struct stm32f7_i2c_msg {
* @wakeup_src: boolean to know if the device is a wakeup source
* @smbus_mode: states that the controller is configured in SMBus mode
* @host_notify_client: SMBus host-notify client
+ * @alert: SMBus alert specific data
*/
struct stm32f7_i2c_dev {
struct i2c_adapter adap;
@@ -340,6 +355,7 @@ struct stm32f7_i2c_dev {
bool wakeup_src;
bool smbus_mode;
struct i2c_client *host_notify_client;
+ struct stm32f7_i2c_alert *alert;
};
/*
@@ -1616,6 +1632,13 @@ static irqreturn_t stm32f7_i2c_isr_error(int irq, void
*data)
f7_msg->result = -EINVAL;
}
+ if (status & STM32F7_I2C_ISR_ALERT) {
+ dev_dbg(dev, "<%s>: SMBus alert received\n", __func__);
+ writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);
+ i2c_handle_smbus_alert(i2c_dev->alert->ara);
+ return IRQ_HANDLED;
+ }
+
if (!i2c_dev->slave_running) {
u32 mask;
/* Disable interrupts */
@@ -1982,6 +2005,42 @@ static void stm32f7_i2c_disable_smbus_host(struct
stm32f7_i2c_dev *i2c_dev)
}
}
+static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
+{
+ struct stm32f7_i2c_alert *alert;
+ struct i2c_adapter *adap = _dev->adap;
+ struct device *dev = i2c_dev->dev;
+ void __iomem *base = i2c_dev->base;
+
+ alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL);
+ if (!alert)
+ return -ENOMEM;
+
+ alert->ara = i2c_new_smbus_alert_device(adap, >setup);
+ if (IS_ERR(alert->ara))
+ return PTR_ERR(alert->ara);
+
+ i2c_dev->alert = alert;
+
+ /* Enable SMBus Alert */
+ stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);
+
+ return 0;
+}
+
+static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
+{
+ struct stm32f7_i2c_alert *alert = i2c_dev->alert;
+ void __iomem *base = i2c_dev->base;
+
+ if (alert) {
+ /* Disable SMBus Alert */
+ stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
+STM32F7_I2C_CR1_ALERTEN);
+ i2c_unregister_device(alert->ara);
+ }
+}
+
static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
{
struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
@@ -2169,6 +2228,16 @@ static int stm32f7_i2c_probe(struct platform_device
*pdev)
}
}
+ if (of_property_read_bool(pdev->dev.of_node, &qu
[PATCH v3 1/2] dt-bindings: i2c: stm32f7: add st,smbus-alert binding for SMBus Alert
Based on the SMBus specification, SMBus Alert active state is low. As often on SoC, the SMBus Alert pin is not only dedicated to this feature and can also be used for another purpose (by configuring it as alternate function for other functions via pinctrl). "smbus" dt-binding has been introduced recently [1], however it is also used to indicate usage of host-notify feature. Relying on 'smbus' binding for SMBus-Alert as well as it was discussed previously [2] would lead to requiring the SMBALERT# pin to be configured as alternate function for i2c/smbus controller even if only host-notify is needed. Indeed, not doing so would lead to spurious SMBus Alert interrupts since the i2c/smbus controller would see the (not configured) SMBA pin as low level. For that reason, SMBus-Alert needs to have its own binding in order to only be enabled whenever SMBALERT# pin is configured as alternate function for i2c/smbus controller. [1] https://lore.kernel.org/linux-i2c/20200721062217.GA1044@kunai/ [2] https://lore.kernel.org/linux-i2c/20200701143738.gf3...@gnbcxd0016.gnb.st.com/ Signed-off-by: Alain Volmat Reviewed-by: Rob Herring --- v3: use lore.kernel.org links v2: introduce st,smbus-alert property --- Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml index d747f4990ad8..0d45ead7d835 100644 --- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml @@ -36,6 +36,11 @@ allOf: minItems: 3 maxItems: 3 +st,smbus-alert: + description: Enable the SMBus-Alert via SMBA pin, note SMBA pin + must also be configured via pinctrl. + type: boolean + - if: properties: compatible: -- 2.17.1
[PATCH v3 0/2] i2c: stm32f7: add SMBus-Alert support
This serie adds support for SMBus Alert on the STM32F7. A new binding st,smbus-alert is added in order to differenciate with the existing smbus binding. SMBA alert control and status logic must be enabled along with SMBALERT# pin configured via pinctrl in the device tree. This is the rational for adding "st,smbus-alert" property. --- v3: use lore.kernel.org links instead of marc.info v2: When SMBUS alert isn't available on the board (SMBA unused), this logic musn't be enabled. Enabling it unconditionally wrongly lead to get SMBA interrupts. So, add "st,smbus-alert" dedicated binding to have a smbus alert with a consistent pin configuration in DT. Alain Volmat (2): dt-bindings: i2c: stm32f7: add st,smbus-alert binding for SMBus Alert i2c: stm32f7: add SMBus-Alert support .../devicetree/bindings/i2c/st,stm32-i2c.yaml | 5 ++ drivers/i2c/busses/i2c-stm32f7.c | 73 +++ 2 files changed, 78 insertions(+) -- 2.17.1
Re: [PATCH] i2c-stm32f4: Mundane typo fix
On Wed, Mar 24, 2021 at 07:36:10PM +0530, Bhaskar Chowdhury wrote: > > s/postion/position/ > > Signed-off-by: Bhaskar Chowdhury > --- > drivers/i2c/busses/i2c-stm32f4.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/i2c/busses/i2c-stm32f4.c > b/drivers/i2c/busses/i2c-stm32f4.c > index 937c2c8fd349..4933fc8ce3fd 100644 > --- a/drivers/i2c/busses/i2c-stm32f4.c > +++ b/drivers/i2c/busses/i2c-stm32f4.c > @@ -534,7 +534,7 @@ static void stm32f4_i2c_handle_rx_addr(struct > stm32f4_i2c_dev *i2c_dev) > default: > /* >* N-byte reception: > - * Enable ACK, reset POS (ACK postion) and clear ADDR flag. > + * Enable ACK, reset POS (ACK position) and clear ADDR flag. >* In that way, ACK will be sent as soon as the current byte >* will be received in the shift register >*/ Reviewed-by: Alain Volmat > -- > 2.30.1 >
[PATCH v2 16/16] ARM: dts: sti: update clkgen-fsyn entries in stih418-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418-clock.dtsi | 26 +++---
1 file changed, 3 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index d628e656458d..e84c476b83ed 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -94,11 +94,6 @@
reg = <0x9103000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
-"clk-s-c0-fs0-ch1",
-"clk-s-c0-fs0-ch2",
-"clk-s-c0-fs0-ch3";
};
clk_s_c0: clockgen-c@9103000 {
@@ -150,15 +145,10 @@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
-"clk-s-d0-fs0-ch1",
-"clk-s-d0-fs0-ch2",
-"clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
@@ -179,15 +169,10 @@
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
-"clk-s-d2-fs0-ch1",
-"clk-s-d2-fs0-ch2",
-"clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
@@ -210,15 +195,10 @@
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
-"clk-s-d3-fs0-ch1",
-"clk-s-d3-fs0-ch2",
-"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
--
2.17.1
[PATCH v2 15/16] ARM: dts: sti: update clkgen-fsyn entries in stih410-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih410-clock.dtsi | 27 +++
1 file changed, 3 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index 3aeabdd6e305..6b0e6d4477a3 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -93,12 +93,6 @@
reg = <0x9103000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
-"clk-s-c0-fs0-ch1",
-"clk-s-c0-fs0-ch2",
-"clk-s-c0-fs0-ch3";
- clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
clk_s_c0: clockgen-c@9103000 {
@@ -150,15 +144,10 @@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
-"clk-s-d0-fs0-ch1",
-"clk-s-d0-fs0-ch2",
-"clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
@@ -179,15 +168,10 @@
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
-"clk-s-d2-fs0-ch1",
-"clk-s-d2-fs0-ch2",
-"clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
@@ -210,15 +194,10 @@
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
-"clk-s-d3-fs0-ch1",
-"clk-s-d3-fs0-ch2",
-"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
--
2.17.1
[PATCH v2 14/16] ARM: dts: sti: update clkgen-fsyn entries in stih407-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih407-clock.dtsi | 27 +++
1 file changed, 3 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi
b/arch/arm/boot/dts/stih407-clock.dtsi
index 2603226a6ca8..9cce9541e26b 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -93,12 +93,6 @@
reg = <0x9103000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
-"clk-s-c0-fs0-ch1",
-"clk-s-c0-fs0-ch2",
-"clk-s-c0-fs0-ch3";
- clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
clk_s_c0: clockgen-c@9103000 {
@@ -150,15 +144,10 @@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
-"clk-s-d0-fs0-ch1",
-"clk-s-d0-fs0-ch2",
-"clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
@@ -179,15 +168,10 @@
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
-"clk-s-d2-fs0-ch1",
-"clk-s-d2-fs0-ch2",
-"clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
@@ -210,15 +194,10 @@
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
-"clk-s-d3-fs0-ch1",
-"clk-s-d3-fs0-ch2",
-"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
--
2.17.1
[PATCH v2 12/16] ARM: dts: sti: update clkgen-pll entries in stih410-clock
The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih410-clock.dtsi | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index 04b0d7080353..3aeabdd6e305 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -39,8 +39,6 @@
compatible = "st,stih407-clkgen-plla9";
clocks = <_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -74,12 +72,9 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
- clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -112,21 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
- clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
--
2.17.1
[PATCH v2 13/16] ARM: dts: sti: update clkgen-pll entries in stih418-clock
The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418-clock.dtsi | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 35d12979cdf4..d628e656458d 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -39,8 +39,6 @@
compatible = "st,stih418-clkgen-plla9";
clocks = <_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -75,11 +73,9 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -111,20 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
--
2.17.1
[PATCH v2 11/16] ARM: dts: sti: update clkgen-pll entries in stih407-clock
The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih407-clock.dtsi | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi
b/arch/arm/boot/dts/stih407-clock.dtsi
index ecd568777e5f..2603226a6ca8 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -36,8 +36,6 @@
compatible = "st,stih407-clkgen-plla9";
clocks = <_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -74,12 +72,9 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
- clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -112,21 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
- clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
--
2.17.1
[PATCH v2 10/16] ARM: dts: sti: update flexgen compatible within stih410-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih410-clock.dtsi | 95 ++--
1 file changed, 6 insertions(+), 89 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index 81a8c25d7ba5..04b0d7080353 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -83,16 +83,12 @@
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih410-a0";
#clock-cells = <1>;
clocks = <_s_a0_pll 0>,
<_sysin>;
-
- clock-output-names = "clk-ic-lmi0",
-"clk-ic-lmi1";
- clock-critical = ;
};
};
@@ -135,7 +131,7 @@
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih410-c0";
clocks = <_s_c0_pll0 0>,
<_s_c0_pll1 0>,
@@ -145,52 +141,6 @@
<_s_c0_quadfs 3>,
<_sysin>;
- clock-output-names = "clk-icn-gpu",
-"clk-fdma",
-"clk-nand",
-"clk-hva",
-"clk-proc-stfe",
-"clk-proc-tp",
-"clk-rx-icn-dmu",
-"clk-rx-icn-hva",
-"clk-icn-cpu",
-"clk-tx-icn-dmu",
-"clk-mmc-0",
-"clk-mmc-1",
-"clk-jpegdec",
-"clk-ext2fa9",
-"clk-ic-bdisp-0",
-"clk-ic-bdisp-1",
-"clk-pp-dmu",
-"clk-vid-dmu",
-"clk-dss-lpc",
-"clk-st231-aud-0",
-"clk-st231-gp-1",
-"clk-st231-dmu",
-"clk-icn-lmi",
-"clk-tx-icn-disp-1",
-"clk-icn-sbc",
-"clk-stfe-frc2",
-"clk-eth-phy",
-"clk-eth-ref-phyclk",
-"clk-flash-promip",
-"clk-main-disp",
-"clk-aux-disp",
-"clk-compo-dvp",
-"clk-tx-icn-hades",
-"clk-rx-icn-hades",
-"clk-icn-reg-16",
-"clk-pp-hades",
-"clk-clust-hades",
-"clk-hwpe-hades",
-"clk-fc-hades";
-
[PATCH v2 08/16] ARM: dts: sti: update flexgen compatible within stih418-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418-clock.dtsi | 96 ++--
1 file changed, 5 insertions(+), 91 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 8fa092462102..35d12979cdf4 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -83,15 +83,12 @@
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih410-a0";
#clock-cells = <1>;
clocks = <_s_a0_pll 0>,
<_sysin>;
-
- clock-output-names = "clk-ic-lmi0",
-"clk-ic-lmi1";
};
};
@@ -132,7 +129,7 @@
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih418-c0";
clocks = <_s_c0_pll0 0>,
<_s_c0_pll1 0>,
@@ -142,49 +139,6 @@
<_s_c0_quadfs 3>,
<_sysin>;
- clock-output-names = "clk-icn-gpu",
-"clk-fdma",
-"clk-nand",
-"clk-hva",
-"clk-proc-stfe",
-"clk-tp",
-"clk-rx-icn-dmu",
-"clk-rx-icn-hva",
-"clk-icn-cpu",
-"clk-tx-icn-dmu",
-"clk-mmc-0",
-"clk-mmc-1",
-"clk-jpegdec",
-"clk-icn-reg",
-"clk-proc-bdisp-0",
-"clk-proc-bdisp-1",
-"clk-pp-dmu",
-"clk-vid-dmu",
-"clk-dss-lpc",
-"clk-st231-aud-0",
-"clk-st231-gp-1",
-"clk-st231-dmu",
-"clk-icn-lmi",
-"clk-tx-icn-1",
-"clk-icn-sbc",
-"clk-stfe-frc2",
-"clk-eth-phyref",
-"clk-eth-ref-phyclk",
-"clk-flash-promip",
-"clk-main-disp",
-"clk-aux-disp",
-"clk-compo-dvp",
-"clk-tx-icn-hades",
-"clk-rx-icn-hades",
-"clk-icn-reg-16",
-"clk-pp-hevc",
-"clk-clust-hevc",
-"clk-hwpe-hevc",
-"clk-fc-hevc",
-
[PATCH v2 07/16] dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible
New compatible are added, supporting various kind of clkgen-fsyn used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat --- Documentation/devicetree/bindings/clock/st/st,quadfs.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt index d93d49342e60..c4ba2adb0b4f 100644 --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt +++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt @@ -12,6 +12,9 @@ This binding uses the common clock binding[1]. Required properties: - compatible : shall be: "st,quadfs" + "st,quadfs-d0" + "st,quadfs-d2" + "st,quadfs-d3" "st,quadfs-pll" -- 2.17.1
[PATCH v2 09/16] ARM: dts: sti: update flexgen compatible within stih407-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih407-clock.dtsi | 85 ++--
1 file changed, 6 insertions(+), 79 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi
b/arch/arm/boot/dts/stih407-clock.dtsi
index 1ab40db7c91a..ecd568777e5f 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -83,15 +83,12 @@
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih407-a0";
#clock-cells = <1>;
clocks = <_s_a0_pll 0>,
<_sysin>;
-
- clock-output-names = "clk-ic-lmi0";
- clock-critical = ;
};
};
@@ -134,7 +131,7 @@
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih407-c0";
clocks = <_s_c0_pll0 0>,
<_s_c0_pll1 0>,
@@ -144,45 +141,6 @@
<_s_c0_quadfs 3>,
<_sysin>;
- clock-output-names = "clk-icn-gpu",
-"clk-fdma",
-"clk-nand",
-"clk-hva",
-"clk-proc-stfe",
-"clk-proc-tp",
-"clk-rx-icn-dmu",
-"clk-rx-icn-hva",
-"clk-icn-cpu",
-"clk-tx-icn-dmu",
-"clk-mmc-0",
-"clk-mmc-1",
-"clk-jpegdec",
-"clk-ext2fa9",
-"clk-ic-bdisp-0",
-"clk-ic-bdisp-1",
-"clk-pp-dmu",
-"clk-vid-dmu",
-"clk-dss-lpc",
-"clk-st231-aud-0",
-"clk-st231-gp-1",
-"clk-st231-dmu",
-"clk-icn-lmi",
-"clk-tx-icn-disp-1",
-"clk-icn-sbc",
-"clk-stfe-frc2",
-"clk-eth-phy",
-"clk-eth-ref-phyclk",
-"clk-flash-promip",
-"clk-main-disp",
-"clk-aux-disp",
-"clk-compo-dvp";
- clock-critical = ,
-,
-,
-,
-,
-;
-
/*
* ARM Peripheral clock for timers
*/
@@ -219,18 +177,13 @@
clk_s_d0_flexgen: clk-s-d0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen-audio",
[PATCH v2 04/16] clk: st: clkgen-pll: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
v2: clk-s-a0-pll-odf-0 don't need to be CLK_IS_CRITICAL
mark several clock as CLK_IS_CRITICAL
drivers/clk/st/clkgen-pll.c | 120 +++-
1 file changed, 106 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index f6c56ca90c7d..8c6215b3c808 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -57,6 +57,17 @@ struct clkgen_pll_data {
const struct clk_ops *ops;
};
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
+struct clkgen_pll_data_clks {
+ struct clkgen_pll_data *data;
+ const struct clkgen_clk_out *outputs;
+};
+
+
static const struct clk_ops stm_pll3200c32_ops;
static const struct clk_ops stm_pll3200c32_a9_ops;
static const struct clk_ops stm_pll4600c28_ops;
@@ -74,6 +85,28 @@ static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
.ops= _pll3200c32_ops,
};
+static const struct clkgen_pll_data_clks st_pll3200c32_cx_0_legacy_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_0,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_ax_0_clks[] = {
+ { .name = "clk-s-a0-pll-odf-0", },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_a0_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_0,
+ .outputs= st_pll3200c32_ax_0_clks,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_cx_0_clks[] = {
+ { .name = "clk-s-c0-pll0-odf-0",.flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_c0_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_0,
+ .outputs= st_pll3200c32_cx_0_clks,
+};
+
static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
/* 407 C0 PLL1 */
.pdn_status = CLKGEN_FIELD(0x2c8, 0x1,8),
@@ -87,6 +120,19 @@ static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
.ops= _pll3200c32_ops,
};
+static const struct clkgen_pll_data_clks st_pll3200c32_cx_1_legacy_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_1,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_cx_1_clks[] = {
+ { .name = "clk-s-c0-pll1-odf-0",.flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_c1_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_1,
+ .outputs= st_pll3200c32_cx_1_clks,
+};
+
static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
/* 407 A9 */
.pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
@@ -104,6 +150,15 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 =
{
.ops= _pll3200c32_a9_ops,
};
+static const struct clkgen_clk_out st_pll3200c32_407_a9_clks[] = {
+ { .name = "clockgen-a9-pll-odf",.flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_407_a9_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_407_a9,
+ .outputs= st_pll3200c32_407_a9_clks,
+};
+
static struct clkgen_pll_data st_pll4600c28_418_a9 = {
/* 418 A9 */
.pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
@@ -120,6 +175,15 @@ static struct clkgen_pll_data st_pll4600c28_418_a9 = {
.ops= _pll4600c28_ops,
};
+static const struct clkgen_clk_out st_pll4600c28_418_a9_clks[] = {
+ { .name = "clockgen-a9-pll-odf", },
+};
+
+static const struct clkgen_pll_data_clks st_pll4600c28_418_a9_data = {
+ .data = (struct clkgen_pll_data *)_pll4600c28_418_a9,
+ .outputs= st_pll4600c28_418_a9_clks,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -684,7 +748,7 @@ static struct clk * __init clkgen_odf_register(const char
*parent_name,
static void __init clkgen_c32_pll_setup(struct device_node *np,
- struct clkgen_pll_data *data)
+ struct clkgen_pll_data_clks *datac)
{
struct clk *clk;
const char *parent_name, *pll_name;
@@ -704,14 +768,14 @@ static void __init clkgen_c32_pll_setup(struct
device_node *np,
of_clk_detect_critical(np, 0, _flags);
- clk = clkgen_pll_register(parent_name, data, pll_base, pll_flags,
- np->name, data-
[PATCH v2 05/16] dt-bindings: clock: st: clkgen-pll: add new introduced compatible
New compatible are added, supporting various kind of clkgen-pll used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat --- Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt index f207053e0550..d0fa1e02d06d 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt @@ -10,7 +10,10 @@ Required properties: - compatible : shall be: "st,clkgen-pll0" + "st,clkgen-pll0-a0" + "st,clkgen-pll0-c0" "st,clkgen-pll1" + "st,clkgen-pll1-c0" "st,stih407-clkgen-plla9" "st,stih418-clkgen-plla9" -- 2.17.1
[PATCH v2 06/16] clk: st: clkgen-fsyn: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
v2: clk-s-c0-fs0-ch0 do not need to be CLK_IS_CRITICAL
drivers/clk/st/clkgen-fsyn.c | 113 +++
1 file changed, 101 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index dd6062e043e0..164285d6be97 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -66,6 +66,16 @@ struct clkgen_quadfs_data {
unsigned long *);
};
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
+struct clkgen_quadfs_data_clks {
+ struct clkgen_quadfs_data *data;
+ const struct clkgen_clk_out *outputs;
+};
+
static const struct clk_ops st_quadfs_pll_c32_ops;
static int clk_fs660c32_dig_get_params(unsigned long input,
@@ -115,6 +125,18 @@ static const struct clkgen_quadfs_data st_fs660c32_C = {
.get_rate = clk_fs660c32_dig_get_rate,
};
+static const struct clkgen_clk_out st_fs660c32_C_clks[] = {
+ { .name = "clk-s-c0-fs0-ch0", },
+ { .name = "clk-s-c0-fs0-ch1", },
+ { .name = "clk-s-c0-fs0-ch2", },
+ { .name = "clk-s-c0-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_C_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_C,
+ .outputs= st_fs660c32_C_clks,
+};
+
static const struct clkgen_quadfs_data st_fs660c32_D = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
@@ -156,6 +178,46 @@ static const struct clkgen_quadfs_data st_fs660c32_D = {
.get_params = clk_fs660c32_dig_get_params,
.get_rate = clk_fs660c32_dig_get_rate,};
+static const struct clkgen_quadfs_data_clks st_fs660c32_D_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_D,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D0_clks[] = {
+ { .name = "clk-s-d0-fs0-ch0", },
+ { .name = "clk-s-d0-fs0-ch1", },
+ { .name = "clk-s-d0-fs0-ch2", },
+ { .name = "clk-s-d0-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D0_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_D,
+ .outputs= st_fs660c32_D0_clks,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D2_clks[] = {
+ { .name = "clk-s-d2-fs0-ch0", },
+ { .name = "clk-s-d2-fs0-ch1", },
+ { .name = "clk-s-d2-fs0-ch2", },
+ { .name = "clk-s-d2-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D2_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_D,
+ .outputs= st_fs660c32_D2_clks,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D3_clks[] = {
+ { .name = "clk-s-d3-fs0-ch0", },
+ { .name = "clk-s-d3-fs0-ch1", },
+ { .name = "clk-s-d3-fs0-ch2", },
+ { .name = "clk-s-d3-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D3_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_D,
+ .outputs= st_fs660c32_D3_clks,
+};
+
/**
* DOC: A Frequency Synthesizer that multiples its input clock by a fixed
factor
*
@@ -857,7 +919,7 @@ static struct clk * __init st_clk_register_quadfs_fsynth(
static void __init st_of_create_quadfs_fsynths(
struct device_node *np, const char *pll_name,
- struct clkgen_quadfs_data *quadfs, void __iomem *reg,
+ struct clkgen_quadfs_data_clks *quadfs, void __iomem *reg,
spinlock_t *lock)
{
struct clk_onecell_data *clk_data;
@@ -881,9 +943,15 @@ static void __init st_of_create_quadfs_fsynths(
const char *clk_name;
unsigned long flags = 0;
- if (of_property_read_string_index(np, "clock-output-names",
- fschan, _name)) {
- break;
+ if (quadfs->outputs) {
+ clk_name = quadfs->outputs[fschan].name;
+ flags = quadfs->outputs[fschan].flags;
+ } else {
+ if (of_property_read_string_index(np,
+ "clock-output-names",
+ fschan, _name))
+
[PATCH v2 02/16] clk: st: flexgen: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
v2: add some missing clock as CLK_IS_CRITICAL
drivers/clk/st/clk-flexgen.c | 344 +--
1 file changed, 330 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 55873d4b7603..24dd0c7dc6c3 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -16,9 +16,16 @@
#include
#include
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
struct clkgen_data {
unsigned long flags;
bool mode;
+ const struct clkgen_clk_out *outputs;
+ const unsigned int outputs_nb;
};
struct flexgen {
@@ -295,6 +302,267 @@ static const struct clkgen_data clkgen_video = {
.mode = 1,
};
+static const struct clkgen_clk_out clkgen_stih407_a0_clk_out[] = {
+ { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_data clkgen_stih407_a0 = {
+ .outputs = clkgen_stih407_a0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih407_a0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih410_a0_clk_out[] = {
+ { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-lmi1", .flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_data clkgen_stih410_a0 = {
+ .outputs = clkgen_stih410_a0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih410_a0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih407_c0_clk_out[] = {
+ { .name = "clk-icn-gpu", },
+ { .name = "clk-fdma", },
+ { .name = "clk-nand", },
+ { .name = "clk-hva", },
+ { .name = "clk-proc-stfe", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-proc-tp", },
+ { .name = "clk-rx-icn-dmu", },
+ { .name = "clk-rx-icn-hva", },
+ { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-mmc-0", },
+ { .name = "clk-mmc-1", },
+ { .name = "clk-jpegdec", },
+ { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-bdisp-0", },
+ { .name = "clk-ic-bdisp-1", },
+ { .name = "clk-pp-dmu", },
+ { .name = "clk-vid-dmu", },
+ { .name = "clk-dss-lpc", },
+ { .name = "clk-st231-aud-0", },
+ { .name = "clk-st231-gp-1", },
+ { .name = "clk-st231-dmu", },
+ { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-tx-icn-disp-1", },
+ { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-stfe-frc2", },
+ { .name = "clk-eth-phy", },
+ { .name = "clk-eth-ref-phyclk", },
+ { .name = "clk-flash-promip", },
+ { .name = "clk-main-disp", },
+ { .name = "clk-aux-disp", },
+ { .name = "clk-compo-dvp", },
+};
+
+static const struct clkgen_data clkgen_stih407_c0 = {
+ .outputs = clkgen_stih407_c0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih407_c0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih410_c0_clk_out[] = {
+ { .name = "clk-icn-gpu", },
+ { .name = "clk-fdma", },
+ { .name = "clk-nand", },
+ { .name = "clk-hva", },
+ { .name = "clk-proc-stfe", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-proc-tp", },
+ { .name = "clk-rx-icn-dmu", },
+ { .name = "clk-rx-icn-hva", },
+ { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-mmc-0", },
+ { .name = "clk-mmc-1", },
+ { .name = "clk-jpegdec", },
+ { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-bdisp-0", },
+ { .name = "clk-ic-bdisp-1", },
+ { .name = "clk-pp-dmu", },
+ { .name = "clk-vid-dmu", },
+ { .name = "clk-dss-lpc", },
+ { .name = "clk-st231-aud-0", },
+ { .name = "clk-st231-gp-1", },
+ { .name = &qu
[PATCH v2 03/16] dt-bindings: clock: st: flexgen: add new introduced compatible
New compatible are added, supporting various kind of flexgen in STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat --- .../devicetree/bindings/clock/st/st,flexgen.txt| 10 ++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt index 7ff77fc57dff..55a18939bddd 100644 --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt @@ -64,6 +64,16 @@ Required properties: audio use case) "st,flexgen-video", "st,flexgen" (enable clock propagation on parent and activate synchronous mode) + "st,flexgen-stih407-a0" + "st,flexgen-stih410-a0" + "st,flexgen-stih407-c0" + "st,flexgen-stih410-c0" + "st,flexgen-stih418-c0" + "st,flexgen-stih407-d0" + "st,flexgen-stih410-d0" + "st,flexgen-stih407-d2" + "st,flexgen-stih418-d2" + "st,flexgen-stih407-d3" - #clock-cells : from common clock binding; shall be set to 1 (multiple clock outputs). -- 2.17.1
[PATCH v2 01/16] clk: st: clkgen-pll: remove used variable of struct clkgen_pll
ODF field within the struct clkgen_pll is never used by the driver
and can thus be removed.
Signed-off-by: Alain Volmat
---
drivers/clk/st/clkgen-pll.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 119c5b33080c..f6c56ca90c7d 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -146,7 +146,6 @@ struct clkgen_pll {
u32 ndiv;
u32 idf;
- u32 odf;
u32 cp;
};
--
2.17.1
[PATCH v2 00/16] clk: st: embed clock outputs within drivers
Most of ST clock drivers used by STi platform are updated in order to introduce clock outputs informations within each drivers and thus allow to avoid having to rely on clock-output-names properties within DT clock nodes. For that purpose, drivers are updated to allow handling both modes (with or without clock-output-names). Once all DT will have been updated, the legacy mode could be removed from the drivers. This will also allow, once all STi DT will be corrected, to remove the of_clk_detect_critical API from clk core code since STi clock drivers are the only drivers using this API. This serie also contains modifications within STi DTS in order to use the newly introduced compatible and remove clock-output-names properties. Alain Volmat (16): clk: st: clkgen-pll: remove used variable of struct clkgen_pll clk: st: flexgen: embed soc clock outputs within compatible data dt-bindings: clock: st: flexgen: add new introduced compatible clk: st: clkgen-pll: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-pll: add new introduced compatible clk: st: clkgen-fsyn: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible ARM: dts: sti: update flexgen compatible within stih418-clock ARM: dts: sti: update flexgen compatible within stih407-clock ARM: dts: sti: update flexgen compatible within stih410-clock ARM: dts: sti: update clkgen-pll entries in stih407-clock ARM: dts: sti: update clkgen-pll entries in stih410-clock ARM: dts: sti: update clkgen-pll entries in stih418-clock ARM: dts: sti: update clkgen-fsyn entries in stih407-clock ARM: dts: sti: update clkgen-fsyn entries in stih410-clock ARM: dts: sti: update clkgen-fsyn entries in stih418-clock .../bindings/clock/st/st,clkgen-pll.txt | 3 + .../bindings/clock/st/st,flexgen.txt | 10 + .../bindings/clock/st/st,quadfs.txt | 3 + arch/arm/boot/dts/stih407-clock.dtsi | 128 +-- arch/arm/boot/dts/stih410-clock.dtsi | 138 +-- arch/arm/boot/dts/stih418-clock.dtsi | 136 +-- drivers/clk/st/clk-flexgen.c | 344 +- drivers/clk/st/clkgen-fsyn.c | 113 +- drivers/clk/st/clkgen-pll.c | 121 +- 9 files changed, 588 insertions(+), 408 deletions(-) --- v2: fix drivers to update some clocks as CLK_IS_CRITICAL -- 2.17.1
Re: [PATCH 00/16] clk: st: embed clock outputs within drivers
Hello, it turns out that some CLK_IS_CRITICAL are missing in the patches I sent. (especially for the stih418). I will send a v2 soon. Alain On Sun, Mar 21, 2021 at 09:40:22PM +0100, Alain Volmat wrote: > Most of ST clock drivers used by STi platform are updated in > order to introduce clock outputs informations within each drivers > and thus allow to avoid having to rely on clock-output-names properties > within DT clock nodes. > For that purpose, drivers are updated to allow handling both modes > (with or without clock-output-names). > Once all DT will have been updated, the legacy mode could be removed > from the drivers. > This will also allow, once all STi DT will be corrected, to remove the > of_clk_detect_critical API from clk core code since STi clock drivers > are the only drivers using this API. > > This serie also contains modifications within STi DTS in order to use > the newly introduced compatible and remove clock-output-names > properties. > > Alain Volmat (16): > clk: st: clkgen-pll: remove used variable of struct clkgen_pll > clk: st: flexgen: embed soc clock outputs within compatible data > dt-bindings: clock: st: flexgen: add new introduced compatible > clk: st: clkgen-pll: embed soc clock outputs within compatible data > dt-bindings: clock: st: clkgen-pll: add new introduced compatible > clk: st: clkgen-fsyn: embed soc clock outputs within compatible data > dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible > ARM: dts: sti: update flexgen compatible within stih418-clock > ARM: dts: sti: update flexgen compatible within stih407-clock > ARM: dts: sti: update flexgen compatible within stih410-clock > ARM: dts: sti: update clkgen-pll entries in stih407-clock > ARM: dts: sti: update clkgen-pll entries in stih410-clock > ARM: dts: sti: update clkgen-pll entries in stih418-clock > ARM: dts: sti: update clkgen-fsyn entries in stih407-clock > ARM: dts: sti: update clkgen-fsyn entries in stih410-clock > ARM: dts: sti: update clkgen-fsyn entries in stih418-clock > > .../bindings/clock/st/st,clkgen-pll.txt | 3 + > .../bindings/clock/st/st,flexgen.txt | 10 + > .../bindings/clock/st/st,quadfs.txt | 3 + > arch/arm/boot/dts/stih407-clock.dtsi | 128 +-- > arch/arm/boot/dts/stih410-clock.dtsi | 138 +-- > arch/arm/boot/dts/stih418-clock.dtsi | 136 +-- > drivers/clk/st/clk-flexgen.c | 344 +- > drivers/clk/st/clkgen-fsyn.c | 113 +- > drivers/clk/st/clkgen-pll.c | 121 +- > 9 files changed, 588 insertions(+), 408 deletions(-) > > -- > 2.17.1 >
[PATCH 16/16] ARM: dts: sti: update clkgen-fsyn entries in stih418-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418-clock.dtsi | 26 +++---
1 file changed, 3 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index d628e656458d..e84c476b83ed 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -94,11 +94,6 @@
reg = <0x9103000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
-"clk-s-c0-fs0-ch1",
-"clk-s-c0-fs0-ch2",
-"clk-s-c0-fs0-ch3";
};
clk_s_c0: clockgen-c@9103000 {
@@ -150,15 +145,10 @@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
-"clk-s-d0-fs0-ch1",
-"clk-s-d0-fs0-ch2",
-"clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
@@ -179,15 +169,10 @@
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
-"clk-s-d2-fs0-ch1",
-"clk-s-d2-fs0-ch2",
-"clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
@@ -210,15 +195,10 @@
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
-"clk-s-d3-fs0-ch1",
-"clk-s-d3-fs0-ch2",
-"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
--
2.17.1
[PATCH 12/16] ARM: dts: sti: update clkgen-pll entries in stih410-clock
The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih410-clock.dtsi | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index 04b0d7080353..3aeabdd6e305 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -39,8 +39,6 @@
compatible = "st,stih407-clkgen-plla9";
clocks = <_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -74,12 +72,9 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
- clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -112,21 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
- clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
--
2.17.1
[PATCH 13/16] ARM: dts: sti: update clkgen-pll entries in stih418-clock
The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418-clock.dtsi | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 35d12979cdf4..d628e656458d 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -39,8 +39,6 @@
compatible = "st,stih418-clkgen-plla9";
clocks = <_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -75,11 +73,9 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -111,20 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
--
2.17.1
[PATCH 15/16] ARM: dts: sti: update clkgen-fsyn entries in stih410-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih410-clock.dtsi | 27 +++
1 file changed, 3 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index 3aeabdd6e305..6b0e6d4477a3 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -93,12 +93,6 @@
reg = <0x9103000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
-"clk-s-c0-fs0-ch1",
-"clk-s-c0-fs0-ch2",
-"clk-s-c0-fs0-ch3";
- clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
clk_s_c0: clockgen-c@9103000 {
@@ -150,15 +144,10 @@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
-"clk-s-d0-fs0-ch1",
-"clk-s-d0-fs0-ch2",
-"clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
@@ -179,15 +168,10 @@
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
-"clk-s-d2-fs0-ch1",
-"clk-s-d2-fs0-ch2",
-"clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
@@ -210,15 +194,10 @@
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
-"clk-s-d3-fs0-ch1",
-"clk-s-d3-fs0-ch2",
-"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
--
2.17.1
[PATCH 14/16] ARM: dts: sti: update clkgen-fsyn entries in stih407-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih407-clock.dtsi | 27 +++
1 file changed, 3 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi
b/arch/arm/boot/dts/stih407-clock.dtsi
index 2603226a6ca8..9cce9541e26b 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -93,12 +93,6 @@
reg = <0x9103000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
-"clk-s-c0-fs0-ch1",
-"clk-s-c0-fs0-ch2",
-"clk-s-c0-fs0-ch3";
- clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
clk_s_c0: clockgen-c@9103000 {
@@ -150,15 +144,10 @@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
-"clk-s-d0-fs0-ch1",
-"clk-s-d0-fs0-ch2",
-"clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
@@ -179,15 +168,10 @@
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
-"clk-s-d2-fs0-ch1",
-"clk-s-d2-fs0-ch2",
-"clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
@@ -210,15 +194,10 @@
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
-"clk-s-d3-fs0-ch1",
-"clk-s-d3-fs0-ch2",
-"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
--
2.17.1
[PATCH 11/16] ARM: dts: sti: update clkgen-pll entries in stih407-clock
The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih407-clock.dtsi | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi
b/arch/arm/boot/dts/stih407-clock.dtsi
index ecd568777e5f..2603226a6ca8 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -36,8 +36,6 @@
compatible = "st,stih407-clkgen-plla9";
clocks = <_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -74,12 +72,9 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
- clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -112,21 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
- clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
--
2.17.1
[PATCH 09/16] ARM: dts: sti: update flexgen compatible within stih407-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih407-clock.dtsi | 85 ++--
1 file changed, 6 insertions(+), 79 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi
b/arch/arm/boot/dts/stih407-clock.dtsi
index 1ab40db7c91a..ecd568777e5f 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -83,15 +83,12 @@
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih407-a0";
#clock-cells = <1>;
clocks = <_s_a0_pll 0>,
<_sysin>;
-
- clock-output-names = "clk-ic-lmi0";
- clock-critical = ;
};
};
@@ -134,7 +131,7 @@
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih407-c0";
clocks = <_s_c0_pll0 0>,
<_s_c0_pll1 0>,
@@ -144,45 +141,6 @@
<_s_c0_quadfs 3>,
<_sysin>;
- clock-output-names = "clk-icn-gpu",
-"clk-fdma",
-"clk-nand",
-"clk-hva",
-"clk-proc-stfe",
-"clk-proc-tp",
-"clk-rx-icn-dmu",
-"clk-rx-icn-hva",
-"clk-icn-cpu",
-"clk-tx-icn-dmu",
-"clk-mmc-0",
-"clk-mmc-1",
-"clk-jpegdec",
-"clk-ext2fa9",
-"clk-ic-bdisp-0",
-"clk-ic-bdisp-1",
-"clk-pp-dmu",
-"clk-vid-dmu",
-"clk-dss-lpc",
-"clk-st231-aud-0",
-"clk-st231-gp-1",
-"clk-st231-dmu",
-"clk-icn-lmi",
-"clk-tx-icn-disp-1",
-"clk-icn-sbc",
-"clk-stfe-frc2",
-"clk-eth-phy",
-"clk-eth-ref-phyclk",
-"clk-flash-promip",
-"clk-main-disp",
-"clk-aux-disp",
-"clk-compo-dvp";
- clock-critical = ,
-,
-,
-,
-,
-;
-
/*
* ARM Peripheral clock for timers
*/
@@ -219,18 +177,13 @@
clk_s_d0_flexgen: clk-s-d0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen-audio",
[PATCH 10/16] ARM: dts: sti: update flexgen compatible within stih410-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih410-clock.dtsi | 95 ++--
1 file changed, 6 insertions(+), 89 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index 81a8c25d7ba5..04b0d7080353 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -83,16 +83,12 @@
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih410-a0";
#clock-cells = <1>;
clocks = <_s_a0_pll 0>,
<_sysin>;
-
- clock-output-names = "clk-ic-lmi0",
-"clk-ic-lmi1";
- clock-critical = ;
};
};
@@ -135,7 +131,7 @@
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih410-c0";
clocks = <_s_c0_pll0 0>,
<_s_c0_pll1 0>,
@@ -145,52 +141,6 @@
<_s_c0_quadfs 3>,
<_sysin>;
- clock-output-names = "clk-icn-gpu",
-"clk-fdma",
-"clk-nand",
-"clk-hva",
-"clk-proc-stfe",
-"clk-proc-tp",
-"clk-rx-icn-dmu",
-"clk-rx-icn-hva",
-"clk-icn-cpu",
-"clk-tx-icn-dmu",
-"clk-mmc-0",
-"clk-mmc-1",
-"clk-jpegdec",
-"clk-ext2fa9",
-"clk-ic-bdisp-0",
-"clk-ic-bdisp-1",
-"clk-pp-dmu",
-"clk-vid-dmu",
-"clk-dss-lpc",
-"clk-st231-aud-0",
-"clk-st231-gp-1",
-"clk-st231-dmu",
-"clk-icn-lmi",
-"clk-tx-icn-disp-1",
-"clk-icn-sbc",
-"clk-stfe-frc2",
-"clk-eth-phy",
-"clk-eth-ref-phyclk",
-"clk-flash-promip",
-"clk-main-disp",
-"clk-aux-disp",
-"clk-compo-dvp",
-"clk-tx-icn-hades",
-"clk-rx-icn-hades",
-"clk-icn-reg-16",
-"clk-pp-hades",
-"clk-clust-hades",
-"clk-hwpe-hades",
-"clk-fc-hades";
-
[PATCH 06/16] clk: st: clkgen-fsyn: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
drivers/clk/st/clkgen-fsyn.c | 113 +++
1 file changed, 101 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index dd6062e043e0..c44a59ba4d85 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -66,6 +66,16 @@ struct clkgen_quadfs_data {
unsigned long *);
};
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
+struct clkgen_quadfs_data_clks {
+ struct clkgen_quadfs_data *data;
+ const struct clkgen_clk_out *outputs;
+};
+
static const struct clk_ops st_quadfs_pll_c32_ops;
static int clk_fs660c32_dig_get_params(unsigned long input,
@@ -115,6 +125,18 @@ static const struct clkgen_quadfs_data st_fs660c32_C = {
.get_rate = clk_fs660c32_dig_get_rate,
};
+static const struct clkgen_clk_out st_fs660c32_C_clks[] = {
+ { .name = "clk-s-c0-fs0-ch0", .flags = CLK_IS_CRITICAL, },
+ { .name = "clk-s-c0-fs0-ch1", },
+ { .name = "clk-s-c0-fs0-ch2", },
+ { .name = "clk-s-c0-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_C_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_C,
+ .outputs= st_fs660c32_C_clks,
+};
+
static const struct clkgen_quadfs_data st_fs660c32_D = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
@@ -156,6 +178,46 @@ static const struct clkgen_quadfs_data st_fs660c32_D = {
.get_params = clk_fs660c32_dig_get_params,
.get_rate = clk_fs660c32_dig_get_rate,};
+static const struct clkgen_quadfs_data_clks st_fs660c32_D_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_D,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D0_clks[] = {
+ { .name = "clk-s-d0-fs0-ch0", },
+ { .name = "clk-s-d0-fs0-ch1", },
+ { .name = "clk-s-d0-fs0-ch2", },
+ { .name = "clk-s-d0-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D0_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_D,
+ .outputs= st_fs660c32_D0_clks,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D2_clks[] = {
+ { .name = "clk-s-d2-fs0-ch0", },
+ { .name = "clk-s-d2-fs0-ch1", },
+ { .name = "clk-s-d2-fs0-ch2", },
+ { .name = "clk-s-d2-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D2_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_D,
+ .outputs= st_fs660c32_D2_clks,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D3_clks[] = {
+ { .name = "clk-s-d3-fs0-ch0", },
+ { .name = "clk-s-d3-fs0-ch1", },
+ { .name = "clk-s-d3-fs0-ch2", },
+ { .name = "clk-s-d3-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D3_data = {
+ .data = (struct clkgen_quadfs_data *)_fs660c32_D,
+ .outputs= st_fs660c32_D3_clks,
+};
+
/**
* DOC: A Frequency Synthesizer that multiples its input clock by a fixed
factor
*
@@ -857,7 +919,7 @@ static struct clk * __init st_clk_register_quadfs_fsynth(
static void __init st_of_create_quadfs_fsynths(
struct device_node *np, const char *pll_name,
- struct clkgen_quadfs_data *quadfs, void __iomem *reg,
+ struct clkgen_quadfs_data_clks *quadfs, void __iomem *reg,
spinlock_t *lock)
{
struct clk_onecell_data *clk_data;
@@ -881,9 +943,15 @@ static void __init st_of_create_quadfs_fsynths(
const char *clk_name;
unsigned long flags = 0;
- if (of_property_read_string_index(np, "clock-output-names",
- fschan, _name)) {
- break;
+ if (quadfs->outputs) {
+ clk_name = quadfs->outputs[fschan].name;
+ flags = quadfs->outputs[fschan].flags;
+ } else {
+ if (of_property_read_string_index(np,
+ "clock-output-names",
+ fschan, _name))
+ break;
+
[PATCH 03/16] dt-bindings: clock: st: flexgen: add new introduced compatible
New compatible are added, supporting various kind of flexgen in STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat --- .../devicetree/bindings/clock/st/st,flexgen.txt| 10 ++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt index 7ff77fc57dff..55a18939bddd 100644 --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt @@ -64,6 +64,16 @@ Required properties: audio use case) "st,flexgen-video", "st,flexgen" (enable clock propagation on parent and activate synchronous mode) + "st,flexgen-stih407-a0" + "st,flexgen-stih410-a0" + "st,flexgen-stih407-c0" + "st,flexgen-stih410-c0" + "st,flexgen-stih418-c0" + "st,flexgen-stih407-d0" + "st,flexgen-stih410-d0" + "st,flexgen-stih407-d2" + "st,flexgen-stih418-d2" + "st,flexgen-stih407-d3" - #clock-cells : from common clock binding; shall be set to 1 (multiple clock outputs). -- 2.17.1
[PATCH 04/16] clk: st: clkgen-pll: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
drivers/clk/st/clkgen-pll.c | 120 +++-
1 file changed, 106 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index f6c56ca90c7d..68863f79e1b5 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -57,6 +57,17 @@ struct clkgen_pll_data {
const struct clk_ops *ops;
};
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
+struct clkgen_pll_data_clks {
+ struct clkgen_pll_data *data;
+ const struct clkgen_clk_out *outputs;
+};
+
+
static const struct clk_ops stm_pll3200c32_ops;
static const struct clk_ops stm_pll3200c32_a9_ops;
static const struct clk_ops stm_pll4600c28_ops;
@@ -74,6 +85,28 @@ static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
.ops= _pll3200c32_ops,
};
+static const struct clkgen_pll_data_clks st_pll3200c32_cx_0_legacy_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_0,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_ax_0_clks[] = {
+ { .name = "clk-s-a0-pll-odf-0", .flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_a0_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_0,
+ .outputs= st_pll3200c32_ax_0_clks,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_cx_0_clks[] = {
+ { .name = "clk-s-c0-pll0-odf-0",.flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_c0_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_0,
+ .outputs= st_pll3200c32_cx_0_clks,
+};
+
static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
/* 407 C0 PLL1 */
.pdn_status = CLKGEN_FIELD(0x2c8, 0x1,8),
@@ -87,6 +120,19 @@ static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
.ops= _pll3200c32_ops,
};
+static const struct clkgen_pll_data_clks st_pll3200c32_cx_1_legacy_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_1,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_cx_1_clks[] = {
+ { .name = "clk-s-c0-pll1-odf-0",},
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_c1_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_cx_1,
+ .outputs= st_pll3200c32_cx_1_clks,
+};
+
static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
/* 407 A9 */
.pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
@@ -104,6 +150,15 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 =
{
.ops= _pll3200c32_a9_ops,
};
+static const struct clkgen_clk_out st_pll3200c32_407_a9_clks[] = {
+ { .name = "clockgen-a9-pll-odf", },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_407_a9_data = {
+ .data = (struct clkgen_pll_data *)_pll3200c32_407_a9,
+ .outputs= st_pll3200c32_407_a9_clks,
+};
+
static struct clkgen_pll_data st_pll4600c28_418_a9 = {
/* 418 A9 */
.pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
@@ -120,6 +175,15 @@ static struct clkgen_pll_data st_pll4600c28_418_a9 = {
.ops= _pll4600c28_ops,
};
+static const struct clkgen_clk_out st_pll4600c28_418_a9_clks[] = {
+ { .name = "clockgen-a9-pll-odf", },
+};
+
+static const struct clkgen_pll_data_clks st_pll4600c28_418_a9_data = {
+ .data = (struct clkgen_pll_data *)_pll4600c28_418_a9,
+ .outputs= st_pll4600c28_418_a9_clks,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -684,7 +748,7 @@ static struct clk * __init clkgen_odf_register(const char
*parent_name,
static void __init clkgen_c32_pll_setup(struct device_node *np,
- struct clkgen_pll_data *data)
+ struct clkgen_pll_data_clks *datac)
{
struct clk *clk;
const char *parent_name, *pll_name;
@@ -704,14 +768,14 @@ static void __init clkgen_c32_pll_setup(struct
device_node *np,
of_clk_detect_critical(np, 0, _flags);
- clk = clkgen_pll_register(parent_name, data, pll_base, pll_flags,
- np->name, data->lock);
+ clk = clkgen_pll_register(parent_name, datac->data, pll_base, pll_flags,
+
[PATCH 08/16] ARM: dts: sti: update flexgen compatible within stih418-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418-clock.dtsi | 96 ++--
1 file changed, 5 insertions(+), 91 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 8fa092462102..35d12979cdf4 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -83,15 +83,12 @@
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih410-a0";
#clock-cells = <1>;
clocks = <_s_a0_pll 0>,
<_sysin>;
-
- clock-output-names = "clk-ic-lmi0",
-"clk-ic-lmi1";
};
};
@@ -132,7 +129,7 @@
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih418-c0";
clocks = <_s_c0_pll0 0>,
<_s_c0_pll1 0>,
@@ -142,49 +139,6 @@
<_s_c0_quadfs 3>,
<_sysin>;
- clock-output-names = "clk-icn-gpu",
-"clk-fdma",
-"clk-nand",
-"clk-hva",
-"clk-proc-stfe",
-"clk-tp",
-"clk-rx-icn-dmu",
-"clk-rx-icn-hva",
-"clk-icn-cpu",
-"clk-tx-icn-dmu",
-"clk-mmc-0",
-"clk-mmc-1",
-"clk-jpegdec",
-"clk-icn-reg",
-"clk-proc-bdisp-0",
-"clk-proc-bdisp-1",
-"clk-pp-dmu",
-"clk-vid-dmu",
-"clk-dss-lpc",
-"clk-st231-aud-0",
-"clk-st231-gp-1",
-"clk-st231-dmu",
-"clk-icn-lmi",
-"clk-tx-icn-1",
-"clk-icn-sbc",
-"clk-stfe-frc2",
-"clk-eth-phyref",
-"clk-eth-ref-phyclk",
-"clk-flash-promip",
-"clk-main-disp",
-"clk-aux-disp",
-"clk-compo-dvp",
-"clk-tx-icn-hades",
-"clk-rx-icn-hades",
-"clk-icn-reg-16",
-"clk-pp-hevc",
-"clk-clust-hevc",
-"clk-hwpe-hevc",
-"clk-fc-hevc",
-
[PATCH 02/16] clk: st: flexgen: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
drivers/clk/st/clk-flexgen.c | 344 +--
1 file changed, 330 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 55873d4b7603..b2a205d014dc 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -16,9 +16,16 @@
#include
#include
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
struct clkgen_data {
unsigned long flags;
bool mode;
+ const struct clkgen_clk_out *outputs;
+ const unsigned int outputs_nb;
};
struct flexgen {
@@ -295,6 +302,267 @@ static const struct clkgen_data clkgen_video = {
.mode = 1,
};
+static const struct clkgen_clk_out clkgen_stih407_a0_clk_out[] = {
+ { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_data clkgen_stih407_a0 = {
+ .outputs = clkgen_stih407_a0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih407_a0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih410_a0_clk_out[] = {
+ { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-lmi1", },
+};
+
+static const struct clkgen_data clkgen_stih410_a0 = {
+ .outputs = clkgen_stih410_a0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih410_a0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih407_c0_clk_out[] = {
+ { .name = "clk-icn-gpu", },
+ { .name = "clk-fdma", },
+ { .name = "clk-nand", },
+ { .name = "clk-hva", },
+ { .name = "clk-proc-stfe", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-proc-tp", },
+ { .name = "clk-rx-icn-dmu", },
+ { .name = "clk-rx-icn-hva", },
+ { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-mmc-0", },
+ { .name = "clk-mmc-1", },
+ { .name = "clk-jpegdec", },
+ { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-bdisp-0", },
+ { .name = "clk-ic-bdisp-1", },
+ { .name = "clk-pp-dmu", },
+ { .name = "clk-vid-dmu", },
+ { .name = "clk-dss-lpc", },
+ { .name = "clk-st231-aud-0", },
+ { .name = "clk-st231-gp-1", },
+ { .name = "clk-st231-dmu", },
+ { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-tx-icn-disp-1", },
+ { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-stfe-frc2", },
+ { .name = "clk-eth-phy", },
+ { .name = "clk-eth-ref-phyclk", },
+ { .name = "clk-flash-promip", },
+ { .name = "clk-main-disp", },
+ { .name = "clk-aux-disp", },
+ { .name = "clk-compo-dvp", },
+};
+
+static const struct clkgen_data clkgen_stih407_c0 = {
+ .outputs = clkgen_stih407_c0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih407_c0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih410_c0_clk_out[] = {
+ { .name = "clk-icn-gpu", },
+ { .name = "clk-fdma", },
+ { .name = "clk-nand", },
+ { .name = "clk-hva", },
+ { .name = "clk-proc-stfe", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-proc-tp", },
+ { .name = "clk-rx-icn-dmu", },
+ { .name = "clk-rx-icn-hva", },
+ { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-mmc-0", },
+ { .name = "clk-mmc-1", },
+ { .name = "clk-jpegdec", },
+ { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-bdisp-0", },
+ { .name = "clk-ic-bdisp-1", },
+ { .name = "clk-pp-dmu", },
+ { .name = "clk-vid-dmu", },
+ { .name = "clk-dss-lpc", },
+ { .name = "clk-st231-aud-0", },
+ { .name = "clk-st231-gp-1", },
+ { .name = "clk-st231-dmu", },
+ { .name = "clk-icn-lmi", .f
[PATCH 07/16] dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible
New compatible are added, supporting various kind of clkgen-fsyn used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat --- Documentation/devicetree/bindings/clock/st/st,quadfs.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt index d93d49342e60..c4ba2adb0b4f 100644 --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt +++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt @@ -12,6 +12,9 @@ This binding uses the common clock binding[1]. Required properties: - compatible : shall be: "st,quadfs" + "st,quadfs-d0" + "st,quadfs-d2" + "st,quadfs-d3" "st,quadfs-pll" -- 2.17.1
[PATCH 05/16] dt-bindings: clock: st: clkgen-pll: add new introduced compatible
New compatible are added, supporting various kind of clkgen-pll used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat --- Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt index f207053e0550..d0fa1e02d06d 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt @@ -10,7 +10,10 @@ Required properties: - compatible : shall be: "st,clkgen-pll0" + "st,clkgen-pll0-a0" + "st,clkgen-pll0-c0" "st,clkgen-pll1" + "st,clkgen-pll1-c0" "st,stih407-clkgen-plla9" "st,stih418-clkgen-plla9" -- 2.17.1
[PATCH 00/16] clk: st: embed clock outputs within drivers
Most of ST clock drivers used by STi platform are updated in order to introduce clock outputs informations within each drivers and thus allow to avoid having to rely on clock-output-names properties within DT clock nodes. For that purpose, drivers are updated to allow handling both modes (with or without clock-output-names). Once all DT will have been updated, the legacy mode could be removed from the drivers. This will also allow, once all STi DT will be corrected, to remove the of_clk_detect_critical API from clk core code since STi clock drivers are the only drivers using this API. This serie also contains modifications within STi DTS in order to use the newly introduced compatible and remove clock-output-names properties. Alain Volmat (16): clk: st: clkgen-pll: remove used variable of struct clkgen_pll clk: st: flexgen: embed soc clock outputs within compatible data dt-bindings: clock: st: flexgen: add new introduced compatible clk: st: clkgen-pll: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-pll: add new introduced compatible clk: st: clkgen-fsyn: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible ARM: dts: sti: update flexgen compatible within stih418-clock ARM: dts: sti: update flexgen compatible within stih407-clock ARM: dts: sti: update flexgen compatible within stih410-clock ARM: dts: sti: update clkgen-pll entries in stih407-clock ARM: dts: sti: update clkgen-pll entries in stih410-clock ARM: dts: sti: update clkgen-pll entries in stih418-clock ARM: dts: sti: update clkgen-fsyn entries in stih407-clock ARM: dts: sti: update clkgen-fsyn entries in stih410-clock ARM: dts: sti: update clkgen-fsyn entries in stih418-clock .../bindings/clock/st/st,clkgen-pll.txt | 3 + .../bindings/clock/st/st,flexgen.txt | 10 + .../bindings/clock/st/st,quadfs.txt | 3 + arch/arm/boot/dts/stih407-clock.dtsi | 128 +-- arch/arm/boot/dts/stih410-clock.dtsi | 138 +-- arch/arm/boot/dts/stih418-clock.dtsi | 136 +-- drivers/clk/st/clk-flexgen.c | 344 +- drivers/clk/st/clkgen-fsyn.c | 113 +- drivers/clk/st/clkgen-pll.c | 121 +- 9 files changed, 588 insertions(+), 408 deletions(-) -- 2.17.1
[PATCH 01/16] clk: st: clkgen-pll: remove used variable of struct clkgen_pll
ODF field within the struct clkgen_pll is never used by the driver
and can thus be removed.
Signed-off-by: Alain Volmat
---
drivers/clk/st/clkgen-pll.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 119c5b33080c..f6c56ca90c7d 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -146,7 +146,6 @@ struct clkgen_pll {
u32 ndiv;
u32 idf;
- u32 odf;
u32 cp;
};
--
2.17.1
[PATCH v2 0/2] i2c: stm32f7: add SMBus-Alert support
This serie adds support for SMBus Alert on the STM32F7. A new binding st,smbus-alert is added in order to differenciate with the existing smbus binding. SMBA alert control and status logic must be enabled along with SMBALERT# pin configured via pinctrl in the device tree. This is the rational for adding "st,smbus-alert" property. --- v2: When SMBUS alert isn't available on the board (SMBA unused), this logic musn't be enabled. Enabling it unconditionally wrongly lead to get SMBA interrupts. So, add "st,smbus-alert" dedicated binding to have a smbus alert with a consistent pin configuration in DT. Alain Volmat (2): dt-bindings: i2c: stm32f7: add st,smbus-alert binding for SMBus Alert i2c: stm32f7: add SMBus-Alert support .../devicetree/bindings/i2c/st,stm32-i2c.yaml | 5 ++ drivers/i2c/busses/i2c-stm32f7.c | 73 +++ 2 files changed, 78 insertions(+) -- 2.17.1
[PATCH v2 2/2] i2c: stm32f7: add SMBus-Alert support
Add support for the SMBus-Alert protocol to the STM32F7 that has
dedicated control and status logic.
If SMBus-Alert is used, the SMBALERT# pin must be configured as alternate
function for I2C Alert.
Signed-off-by: Alain Volmat
---
v2: - rely on st,smbus-alert binding instead of smbus
---
drivers/i2c/busses/i2c-stm32f7.c | 73
1 file changed, 73 insertions(+)
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index c62c815b88eb..bd840cd2b9e4 100644
--- a/drivers/i2c/busses/i2c-stm32f7.c
+++ b/drivers/i2c/busses/i2c-stm32f7.c
@@ -51,6 +51,7 @@
/* STM32F7 I2C control 1 */
#define STM32F7_I2C_CR1_PECEN BIT(23)
+#define STM32F7_I2C_CR1_ALERTENBIT(22)
#define STM32F7_I2C_CR1_SMBHEN BIT(20)
#define STM32F7_I2C_CR1_WUPEN BIT(18)
#define STM32F7_I2C_CR1_SBCBIT(16)
@@ -125,6 +126,7 @@
(((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
#define STM32F7_I2C_ISR_DIRBIT(16)
#define STM32F7_I2C_ISR_BUSY BIT(15)
+#define STM32F7_I2C_ISR_ALERT BIT(13)
#define STM32F7_I2C_ISR_PECERR BIT(11)
#define STM32F7_I2C_ISR_ARLO BIT(9)
#define STM32F7_I2C_ISR_BERR BIT(8)
@@ -138,6 +140,7 @@
#define STM32F7_I2C_ISR_TXEBIT(0)
/* STM32F7 I2C Interrupt Clear */
+#define STM32F7_I2C_ICR_ALERTCFBIT(13)
#define STM32F7_I2C_ICR_PECCF BIT(11)
#define STM32F7_I2C_ICR_ARLOCF BIT(9)
#define STM32F7_I2C_ICR_BERRCF BIT(8)
@@ -283,6 +286,17 @@ struct stm32f7_i2c_msg {
u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
};
+/**
+ * struct stm32f7_i2c_alert - SMBus alert specific data
+ * @setup: platform data for the smbus_alert i2c client
+ * @ara: I2C slave device used to respond to the SMBus Alert with Alert
+ * Response Address
+ */
+struct stm32f7_i2c_alert {
+ struct i2c_smbus_alert_setup setup;
+ struct i2c_client *ara;
+};
+
/**
* struct stm32f7_i2c_dev - private data of the controller
* @adap: I2C adapter for this controller
@@ -312,6 +326,7 @@ struct stm32f7_i2c_msg {
* @wakeup_src: boolean to know if the device is a wakeup source
* @smbus_mode: states that the controller is configured in SMBus mode
* @host_notify_client: SMBus host-notify client
+ * @alert: SMBus alert specific data
*/
struct stm32f7_i2c_dev {
struct i2c_adapter adap;
@@ -340,6 +355,7 @@ struct stm32f7_i2c_dev {
bool wakeup_src;
bool smbus_mode;
struct i2c_client *host_notify_client;
+ struct stm32f7_i2c_alert *alert;
};
/*
@@ -1616,6 +1632,13 @@ static irqreturn_t stm32f7_i2c_isr_error(int irq, void
*data)
f7_msg->result = -EINVAL;
}
+ if (status & STM32F7_I2C_ISR_ALERT) {
+ dev_dbg(dev, "<%s>: SMBus alert received\n", __func__);
+ writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);
+ i2c_handle_smbus_alert(i2c_dev->alert->ara);
+ return IRQ_HANDLED;
+ }
+
if (!i2c_dev->slave_running) {
u32 mask;
/* Disable interrupts */
@@ -1982,6 +2005,42 @@ static void stm32f7_i2c_disable_smbus_host(struct
stm32f7_i2c_dev *i2c_dev)
}
}
+static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
+{
+ struct stm32f7_i2c_alert *alert;
+ struct i2c_adapter *adap = _dev->adap;
+ struct device *dev = i2c_dev->dev;
+ void __iomem *base = i2c_dev->base;
+
+ alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL);
+ if (!alert)
+ return -ENOMEM;
+
+ alert->ara = i2c_new_smbus_alert_device(adap, >setup);
+ if (IS_ERR(alert->ara))
+ return PTR_ERR(alert->ara);
+
+ i2c_dev->alert = alert;
+
+ /* Enable SMBus Alert */
+ stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);
+
+ return 0;
+}
+
+static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
+{
+ struct stm32f7_i2c_alert *alert = i2c_dev->alert;
+ void __iomem *base = i2c_dev->base;
+
+ if (alert) {
+ /* Disable SMBus Alert */
+ stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
+STM32F7_I2C_CR1_ALERTEN);
+ i2c_unregister_device(alert->ara);
+ }
+}
+
static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
{
struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
@@ -2169,6 +2228,16 @@ static int stm32f7_i2c_probe(struct platform_device
*pdev)
}
}
+ if (of_property_read_bool(pdev->dev.of_node, "st,smbus-alert"))
[PATCH v2 1/2] dt-bindings: i2c: stm32f7: add st,smbus-alert binding for SMBus Alert
Based on the SMBus specification, SMBus Alert active state is low. As often on SoC, the SMBus Alert pin is not only dedicated to this feature and can also be used for another purpose (by configuring it as alternate function for other functions via pinctrl). "smbus" dt-binding has been introduced recently [1], however it is also used to indicate usage of host-notify feature. Relying on 'smbus' binding for SMBus-Alert as well as it was discussed previously [2] would lead to requiring the SMBALERT# pin to be configured as alternate function for i2c/smbus controller even if only host-notify is needed. Indeed, not doing so would lead to spurious SMBus Alert interrupts since the i2c/smbus controller would see the (not configured) SMBA pin as low level. For that reason, SMBus-Alert needs to have its own binding in order to only be enabled whenever SMBALERT# pin is configured as alternate function for i2c/smbus controller. [1] https://marc.info/?l=linux-i2c=159531254413805=2 [2] https://marc.info/?l=linux-renesas-soc=159361426409817=2 Signed-off-by: Alain Volmat --- v2: introduce st,smbus-alert property --- Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml index d747f4990ad8..0d45ead7d835 100644 --- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml @@ -36,6 +36,11 @@ allOf: minItems: 3 maxItems: 3 +st,smbus-alert: + description: Enable the SMBus-Alert via SMBA pin, note SMBA pin + must also be configured via pinctrl. + type: boolean + - if: properties: compatible: -- 2.17.1
[PATCH] spi: stm32: Fix use-after-free on unbind
stm32_spi_remove() accesses the driver's private data after calling
spi_unregister_master() even though that function releases the last
reference on the spi_master and thereby frees the private data.
Fix by switching over to the new devm_spi_alloc_master() helper which
keeps the private data accessible until the driver has unbound.
Fixes: 8d559a64f00b ("spi: stm32: drop devres version of spi_register_master")
Reported-by: Lukas Wunner
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 97cf3a2d4180..7f0244a246e9 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1803,7 +1803,7 @@ static int stm32_spi_probe(struct platform_device *pdev)
struct reset_control *rst;
int ret;
- master = spi_alloc_master(>dev, sizeof(struct stm32_spi));
+ master = devm_spi_alloc_master(>dev, sizeof(struct stm32_spi));
if (!master) {
dev_err(>dev, "spi master allocation failed\n");
return -ENOMEM;
@@ -1821,18 +1821,16 @@ static int stm32_spi_probe(struct platform_device *pdev)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
spi->base = devm_ioremap_resource(>dev, res);
- if (IS_ERR(spi->base)) {
- ret = PTR_ERR(spi->base);
- goto err_master_put;
- }
+ if (IS_ERR(spi->base))
+ return PTR_ERR(spi->base);
spi->phys_addr = (dma_addr_t)res->start;
spi->irq = platform_get_irq(pdev, 0);
- if (spi->irq <= 0) {
- ret = dev_err_probe(>dev, spi->irq, "failed to get
irq\n");
- goto err_master_put;
- }
+ if (spi->irq <= 0)
+ return dev_err_probe(>dev, spi->irq,
+"failed to get irq\n");
+
ret = devm_request_threaded_irq(>dev, spi->irq,
spi->cfg->irq_handler_event,
spi->cfg->irq_handler_thread,
@@ -1840,20 +1838,20 @@ static int stm32_spi_probe(struct platform_device *pdev)
if (ret) {
dev_err(>dev, "irq%d request failed: %d\n", spi->irq,
ret);
- goto err_master_put;
+ return ret;
}
spi->clk = devm_clk_get(>dev, NULL);
if (IS_ERR(spi->clk)) {
ret = PTR_ERR(spi->clk);
dev_err(>dev, "clk get failed: %d\n", ret);
- goto err_master_put;
+ return ret;
}
ret = clk_prepare_enable(spi->clk);
if (ret) {
dev_err(>dev, "clk enable failed: %d\n", ret);
- goto err_master_put;
+ return ret;
}
spi->clk_rate = clk_get_rate(spi->clk);
if (!spi->clk_rate) {
@@ -1949,8 +1947,6 @@ static int stm32_spi_probe(struct platform_device *pdev)
dma_release_channel(spi->dma_rx);
err_clk_disable:
clk_disable_unprepare(spi->clk);
-err_master_put:
- spi_master_put(master);
return ret;
}
--
2.17.1
Re: [PATCH] spi: stm32: drop devres version of spi_register_master
Hi Lukas, On Tue, Mar 16, 2021 at 10:17:44PM +0100, Lukas Wunner wrote: > On Fri, Mar 12, 2021 at 11:34:46AM +0100, Alain Volmat wrote: > > --- a/drivers/spi/spi-stm32.c > > +++ b/drivers/spi/spi-stm32.c > > @@ -1960,6 +1960,7 @@ static int stm32_spi_remove(struct platform_device > > *pdev) > > struct spi_master *master = platform_get_drvdata(pdev); > > struct stm32_spi *spi = spi_master_get_devdata(master); > > > > + spi_unregister_master(master); > > spi->cfg->disable(spi); > > > > if (master->dma_tx) > > This introduces a use-after-free because spi_unregister_master() > drops the last reference on the spi_master allocation (which includes > the struct stm32_spi), causing it to be freed, yet the stm32_spi > struct is accessed afterwards. Indeed. Thanks. I've fixed that and will post it. > You need to convert the driver to devm_spi_alloc_master() to > fix the use-after-free. See commit 6cfd39e212de for an example. > > Thanks, > > Lukas
Re: [PATCH] dt-bindings: Clean-up undocumented compatible strings
On Tue, Mar 16, 2021 at 01:49:18PM -0600, Rob Herring wrote:
> Adding checks for undocumented compatible strings reveals a bunch of
> warnings in the DT binding examples. Fix the cases which are typos, just
> a mismatch between the schema and the example, or aren't documented at all.
> In a couple of cases, fixing the compatible revealed some schema errors
> which are fixed.
>
> There's a bunch of others remaining after this which have bindings, but
> those aren't converted to schema yet.
>
> Cc: Stephen Boyd
> Cc: Maxime Ripard
> Cc: Thierry Reding
> Cc: Sam Ravnborg
> Cc: Vinod Koul
> Cc: Alexandre Belloni
> Cc: Jonathan Cameron
> Cc: Pavel Machek
> Cc: Kishon Vijay Abraham I
> Cc: Sebastian Reichel
> Cc: Mark Brown
> Cc: Greg Kroah-Hartman
> Cc: linux-...@vger.kernel.org
> Cc: dmaeng...@vger.kernel.org
> Cc: linux-...@lists.infradead.org
> Cc: linux-...@vger.kernel.org
> Cc: linux-l...@vger.kernel.org
> Cc: linux...@vger.kernel.org
> Cc: linux-ser...@vger.kernel.org
> Cc: linux-...@vger.kernel.org
> Signed-off-by: Rob Herring
> ---
> .../clock/allwinner,sun4i-a10-pll1-clk.yaml | 2 +-
> .../bindings/clock/milbeaut-clock.yaml| 12 +
> .../bindings/display/brcm,bcm2835-dsi0.yaml | 6 -
> .../bindings/display/panel/panel-dpi.yaml | 2 +-
> .../devicetree/bindings/dma/qcom,gpi.yaml | 2 +-
> .../devicetree/bindings/i3c/i3c.yaml | 7 ++---
> .../iio/adc/brcm,iproc-static-adc.yaml| 5
> .../iio/gyroscope/nxp,fxas21002c.yaml | 2 +-
> .../bindings/iio/light/upisemi,us5182.yaml| 4 +--
> .../interrupt-controller/loongson,htpic.yaml | 2 +-
> .../devicetree/bindings/leds/leds-lgm.yaml| 26 ---
> .../bindings/phy/ti,phy-j721e-wiz.yaml| 2 +-
> .../bindings/power/supply/cw2015_battery.yaml | 2 +-
> .../bindings/power/supply/power-supply.yaml | 22
> .../devicetree/bindings/serial/serial.yaml| 2 +-
> .../bindings/spi/amlogic,meson-gx-spicc.yaml | 4 +--
> .../bindings/spi/spi-controller.yaml | 21 ---
> .../devicetree/bindings/spi/spi-mux.yaml | 8 ++
> .../devicetree/bindings/spi/st,stm32-spi.yaml | 6 -
Acked-by: Alain Volmat
> 19 files changed, 58 insertions(+), 79 deletions(-)
>
> diff --git
> a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml
> b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml
> index e9c4cf834aa7..e5d9d45dab8a 100644
> ---
> a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml
> +++
> b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll1-clk.yaml
> @@ -44,7 +44,7 @@ examples:
>- |
> clk@1c2 {
> #clock-cells = <0>;
> -compatible = "allwinner,sun4i-a10-pll1";
> +compatible = "allwinner,sun4i-a10-pll1-clk";
> reg = <0x01c2 0x4>;
> clocks = <>;
> clock-output-names = "osc24M";
> diff --git a/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml
> b/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml
> index 0e8b07710451..6d39344d2b70 100644
> --- a/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/milbeaut-clock.yaml
> @@ -18,10 +18,12 @@ description: |
>
> properties:
>compatible:
> -oneOf:
> - - items:
> - - enum:
> - - socionext,milbeaut-m10v-ccu
> +enum:
> + - socionext,milbeaut-m10v-ccu
> +
> + reg:
> +maxItems: 1
> +
>clocks:
> maxItems: 1
> description: external clock
> @@ -41,7 +43,7 @@ examples:
># Clock controller node:
>- |
> m10v-clk-ctrl@1d021000 {
> -compatible = "socionext,milbeaut-m10v-clk-ccu";
> +compatible = "socionext,milbeaut-m10v-ccu";
> reg = <0x1d021000 0x4000>;
> #clock-cells = <1>;
> clocks = <>;
> diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml
> b/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml
> index 55c60919991f..32608578a352 100644
> --- a/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml
> +++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml
> @@ -77,12 +77,6 @@ examples:
>
> clock-output-names = "dsi1_byte", "dsi1_ddr2", "dsi1_ddr";
>
> -pitouchscreen: panel@0 {
> -compatible = "raspberrypi,touchscreen";
> -reg = <0>;
> -
&
[PATCH] i2c: stm32f7: avoid ifdef CONFIG_PM_SLEEP for pm callbacks
Avoid CONFIG_PM preprocessor check for pm suspend/resume
callbacks and identify the functions with __maybe_unused.
Signed-off-by: Alain Volmat
---
drivers/i2c/busses/i2c-stm32f7.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index c62c815b88eb..4c2f1b16c5ce 100644
--- a/drivers/i2c/busses/i2c-stm32f7.c
+++ b/drivers/i2c/busses/i2c-stm32f7.c
@@ -2267,8 +2267,7 @@ static int __maybe_unused
stm32f7_i2c_runtime_resume(struct device *dev)
return 0;
}
-#ifdef CONFIG_PM_SLEEP
-static int stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
+static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev
*i2c_dev)
{
int ret;
struct stm32f7_i2c_regs *backup_regs = _dev->backup_regs;
@@ -2289,7 +2288,7 @@ static int stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev
*i2c_dev)
return ret;
}
-static int stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
+static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev
*i2c_dev)
{
u32 cr1;
int ret;
@@ -2320,7 +2319,7 @@ static int stm32f7_i2c_regs_restore(struct
stm32f7_i2c_dev *i2c_dev)
return ret;
}
-static int stm32f7_i2c_suspend(struct device *dev)
+static int __maybe_unused stm32f7_i2c_suspend(struct device *dev)
{
struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
int ret;
@@ -2341,7 +2340,7 @@ static int stm32f7_i2c_suspend(struct device *dev)
return 0;
}
-static int stm32f7_i2c_resume(struct device *dev)
+static int __maybe_unused stm32f7_i2c_resume(struct device *dev)
{
struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
int ret;
@@ -2361,7 +2360,6 @@ static int stm32f7_i2c_resume(struct device *dev)
return 0;
}
-#endif
static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
--
2.17.1
[PATCH] spi: stm32: avoid ifdef CONFIG_PM for pm callbacks
Avoid CONFIG_PM preprocessor check for pm suspend/resume
callbacks and identify the functions with __maybe_unused.
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 25c076461011..3cc978e477a2 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1976,8 +1976,7 @@ static int stm32_spi_remove(struct platform_device *pdev)
return 0;
}
-#ifdef CONFIG_PM
-static int stm32_spi_runtime_suspend(struct device *dev)
+static int __maybe_unused stm32_spi_runtime_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct stm32_spi *spi = spi_master_get_devdata(master);
@@ -1987,7 +1986,7 @@ static int stm32_spi_runtime_suspend(struct device *dev)
return pinctrl_pm_select_sleep_state(dev);
}
-static int stm32_spi_runtime_resume(struct device *dev)
+static int __maybe_unused stm32_spi_runtime_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct stm32_spi *spi = spi_master_get_devdata(master);
@@ -1999,10 +1998,8 @@ static int stm32_spi_runtime_resume(struct device *dev)
return clk_prepare_enable(spi->clk);
}
-#endif
-#ifdef CONFIG_PM_SLEEP
-static int stm32_spi_suspend(struct device *dev)
+static int __maybe_unused stm32_spi_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
int ret;
@@ -2014,7 +2011,7 @@ static int stm32_spi_suspend(struct device *dev)
return pm_runtime_force_suspend(dev);
}
-static int stm32_spi_resume(struct device *dev)
+static int __maybe_unused stm32_spi_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct stm32_spi *spi = spi_master_get_devdata(master);
@@ -2044,7 +2041,6 @@ static int stm32_spi_resume(struct device *dev)
return 0;
}
-#endif
static const struct dev_pm_ops stm32_spi_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume)
--
2.17.1
[PATCH] spi: stm32: drop devres version of spi_register_master
From: Antonio Borneo
A call to spi_unregister_master() triggers calling remove()
for all the spi devices binded to the spi master.
Some spi device driver requires to "talk" with the spi device
during the remove(), e.g.:
- a LCD panel like drivers/gpu/drm/panel/panel-lg-lg4573.c
will turn off the backlighting sending a command over spi.
This implies that the spi master must be fully functional when
spi_unregister_master() is called, either if it is called
explicitly in the master's remove() code or implicitly by the
devres framework.
Devres calls devres_release_all() to release all the resources
"after" the remove() of the spi master driver (check code of
__device_release_driver() in drivers/base/dd.c).
If the spi master driver has an empty remove() then there would
be no issue; the devres_release_all() will release everything
in reverse order w.r.t. probe().
But if code in spi master driver remove() disables the spi or
makes it not functional (like in this spi-stm32), then devres
cannot be used safely for unregistering the spi master and the
binded spi devices.
Replace devm_spi_register_master() with spi_register_master()
and add spi_unregister_master() as first action in remove().
Fixes: dcbe0d84dfa5 ("spi: add driver for STM32 SPI controller")
Signed-off-by: Antonio Borneo
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 25c076461011..97cf3a2d4180 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1929,7 +1929,7 @@ static int stm32_spi_probe(struct platform_device *pdev)
pm_runtime_set_active(>dev);
pm_runtime_enable(>dev);
- ret = devm_spi_register_master(>dev, master);
+ ret = spi_register_master(master);
if (ret) {
dev_err(>dev, "spi master registration failed: %d\n",
ret);
@@ -1960,6 +1960,7 @@ static int stm32_spi_remove(struct platform_device *pdev)
struct spi_master *master = platform_get_drvdata(pdev);
struct stm32_spi *spi = spi_master_get_devdata(master);
+ spi_unregister_master(master);
spi->cfg->disable(spi);
if (master->dma_tx)
--
2.17.1
Re: linux-next: manual merge of the arm-soc tree with the arm tree
Hi Stephen,
sorry for the delay, is there anything I should do concerning this issue
?
Cheers,
Alain
On Mon, Feb 15, 2021 at 09:14:44AM +1100, Stephen Rothwell wrote:
> Hi all,
>
> On Tue, 2 Feb 2021 09:01:35 +1100 Stephen Rothwell
> wrote:
> >
> > Today's linux-next merge of the arm-soc tree got a conflict in:
> >
> > arch/arm/Kconfig.debug
> >
> > between commits:
> >
> > 9ca4efec0aba ("ARM: 9040/1: use DEBUG_UART_PHYS and DEBUG_UART_VIRT for
> > sti LL_UART")
> > 6e959ad8bb90 ("ARM: 9041/1: sti LL_UART: add STiH418 SBC UART0 support")
> >
> > from the arm tree and commits:
> >
> > f3a732843acc ("ARM: remove sirf prima2/atlas platforms")
> > 89d4f98ae90d ("ARM: remove zte zx platform")
> >
> > from the arm-soc tree.
> >
> > I fixed it up (see below) and can carry the fix as necessary. This
> > is now fixed as far as linux-next is concerned, but any non trivial
> > conflicts should be mentioned to your upstream maintainer when your tree
> > is submitted for merging. You may also want to consider cooperating
> > with the maintainer of the conflicting tree to minimise any particularly
> > complex conflicts.
> >
> > diff --cc arch/arm/Kconfig.debug
> > index 7a8697a97c98,c36c5d4c6e9c..
> > --- a/arch/arm/Kconfig.debug
> > +++ b/arch/arm/Kconfig.debug
> > @@@ -1623,10 -1546,7 +1550,9 @@@ config DEBUG_LL_INCLUD
> > default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4
> > default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART || DEBUG_S3C64XX_UART
> > default "debug/s5pv210.S" if DEBUG_S5PV210_UART
> > - default "debug/sirf.S" if DEBUG_SIRFSOC_UART
> > - default "debug/sti.S" if DEBUG_STI_UART
> > + default "debug/sti.S" if DEBUG_STIH41X_ASC2
> > + default "debug/sti.S" if DEBUG_STIH41X_SBC_ASC1
> > + default "debug/sti.S" if DEBUG_STIH418_SBC_ASC0
> > default "debug/stm32.S" if DEBUG_STM32_UART
> > default "debug/tegra.S" if DEBUG_TEGRA_UART
> > default "debug/ux500.S" if DEBUG_UX500_UART
> > @@@ -1659,8 -1579,6 +1585,7 @@@ config DEBUG_UART_PHY
> > default 0x02531000 if DEBUG_KEYSTONE_UART1
> > default 0x03010fe0 if ARCH_RPC
> > default 0x0700 if DEBUG_SUN9I_UART0
> > - default 0x09405000 if DEBUG_ZTE_ZX
> > + default 0x0953 if DEBUG_STIH418_SBC_ASC0
> > default 0x10009000 if DEBUG_REALVIEW_STD_PORT || \
> > DEBUG_VEXPRESS_UART0_CA9
> > default 0x1010c000 if DEBUG_REALVIEW_PB1176_PORT
> > @@@ -1789,10 -1698,8 +1707,10 @@@
> > DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \
> > DEBUG_S3C64XX_UART || \
> > DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
> > - DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \
> > + DEBUG_DIGICOLOR_UA0 || \
> > - DEBUG_AT91_UART || DEBUG_STM32_UART
> > + DEBUG_AT91_UART || DEBUG_STM32_UART || \
> > + DEBUG_STIH41X_ASC2 || DEBUG_STIH41X_SBC_ASC1 || \
> > + DEBUG_STIH418_SBC_ASC0
> >
> > config DEBUG_UART_VIRT
> > hex "Virtual base address of debug UART"
> > @@@ -1854,12 -1760,9 +1772,11 @@@
> > default 0xfb02 if DEBUG_OMAP3UART3
> > default 0xfb042000 if DEBUG_OMAP3UART4
> > default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
> > - default 0xfc705000 if DEBUG_ZTE_ZX
> > default 0xfcfe8600 if DEBUG_BCM63XX_UART
> > default 0xfd00 if DEBUG_SPEAR3XX || DEBUG_SPEAR13XX
> > + default 0xfd531000 if DEBUG_STIH41X_SBC_ASC1
> > default 0xfd883000 if DEBUG_ALPINE_UART0
> > + default 0xfdd32000 if DEBUG_STIH41X_ASC2
> > default 0xfe01 if STM32MP1_DEBUG_UART
> > default 0xfe017000 if DEBUG_MMP_UART2
> > default 0xfe018000 if DEBUG_MMP_UART3
> > @@@ -1904,10 -1802,8 +1816,10 @@@
> > DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \
> > DEBUG_S3C64XX_UART || \
> > DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \
> > - DEBUG_SIRFSOC_UART || DEBUG_DIGICOLOR_UA0 || \
> > + DEBUG_DIGICOLOR_UA0 || \
> > - DEBUG_AT91_UART || DEBUG_STM32_UART
> > + DEBUG_AT91_UART || DEBUG_STM32_UART || \
> > + DEBUG_STIH41X_ASC2 || DEBUG_STIH41X_SBC_ASC1 || \
> > + DEBUG_STIH418_SBC_ASC0
> >
> > config DEBUG_UART_8250_SHIFT
> > int "Register offset shift for the 8250 debug UART"
>
> With the merge window about to open, this is a reminder that this
> conflict still exists.
>
> --
> Cheers,
> Stephen Rothwell
[PATCH v2 5/8] spi: stm32: driver uses reset controller only at init
From: Etienne Carriere
Remove reset controller device reference from the device private
structure since it is used only at probe time and can be discarded
once used to reset the SPI device.
Signed-off-by: Etienne Carriere
Signed-off-by: Alain Volmat
---
v2: reordered within the serie
drivers/spi/spi-stm32.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 8e4db219b95d..561234829110 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -263,7 +263,6 @@ struct stm32_spi_cfg {
* @base: virtual memory area
* @clk: hw kernel clock feeding the SPI clock generator
* @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
- * @rst: SPI controller reset line
* @lock: prevent I/O concurrent access
* @irq: SPI controller interrupt line
* @fifo_size: size of the embedded fifo in bytes
@@ -289,7 +288,6 @@ struct stm32_spi {
void __iomem *base;
struct clk *clk;
u32 clk_rate;
- struct reset_control *rst;
spinlock_t lock; /* prevent I/O concurrent access */
int irq;
unsigned int fifo_size;
@@ -1811,6 +1809,7 @@ static int stm32_spi_probe(struct platform_device *pdev)
struct spi_master *master;
struct stm32_spi *spi;
struct resource *res;
+ struct reset_control *rst;
int ret;
master = spi_alloc_master(>dev, sizeof(struct stm32_spi));
@@ -1872,11 +1871,11 @@ static int stm32_spi_probe(struct platform_device *pdev)
goto err_clk_disable;
}
- spi->rst = devm_reset_control_get_exclusive(>dev, NULL);
- if (!IS_ERR(spi->rst)) {
- reset_control_assert(spi->rst);
+ rst = devm_reset_control_get_exclusive(>dev, NULL);
+ if (!IS_ERR(rst)) {
+ reset_control_assert(rst);
udelay(2);
- reset_control_deassert(spi->rst);
+ reset_control_deassert(rst);
}
if (spi->cfg->has_fifo)
--
2.17.1
[PATCH v2 7/8] spi: stm32h7: replace private SPI_1HZ_NS with NSEC_PER_SEC
From: Amelie Delaunay
Replace SPI_1HZ_NS private constant with NSEC_PER_SEC, which is easier
to read and understand.
Signed-off-by: Amelie Delaunay
Signed-off-by: Alain Volmat
---
v2: identical to v1
drivers/spi/spi-stm32.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 54196cecfe2e..f3a4ff60ac4b 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -162,8 +162,6 @@
#define SPI_3WIRE_TX 3
#define SPI_3WIRE_RX 4
-#define SPI_1HZ_NS 10
-
/*
* use PIO for small transfers, avoiding DMA setup/teardown overhead for
drivers
* without fifo buffers.
@@ -1525,7 +1523,7 @@ static void stm32h7_spi_data_idleness(struct stm32_spi
*spi, u32 len)
cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
if ((len > 1) && (spi->cur_midi > 0)) {
- u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
+ u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed);
u32 midi = min_t(u32,
DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
FIELD_GET(STM32H7_SPI_CFG2_MIDI,
--
2.17.1
[PATCH v2 8/8] spi: stm32: make spurious and overrun interrupts visible
We do not expect to receive spurious interrupts so rise a warning
if it happens.
RX overrun is an error condition that signals a corrupted RX
stream both in dma and in irq modes. Report the error and
abort the transfer in either cases.
Signed-off-by: Alain Volmat
---
v2: identical to v1
drivers/spi/spi-stm32.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index f3a4ff60ac4b..25c076461011 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -895,8 +895,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void
*dev_id)
mask |= STM32H7_SPI_SR_RXP;
if (!(sr & mask)) {
- dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
- sr, ier);
+ dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
+sr, ier);
spin_unlock_irqrestore(>lock, flags);
return IRQ_NONE;
}
@@ -923,15 +923,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void
*dev_id)
}
if (sr & STM32H7_SPI_SR_OVR) {
- dev_warn(spi->dev, "Overrun: received value discarded\n");
- if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
- stm32h7_spi_read_rxfifo(spi, false);
- /*
-* If overrun is detected while using DMA, it means that
-* something went wrong, so stop the current transfer
-*/
- if (spi->cur_usedma)
- end = true;
+ dev_err(spi->dev, "Overrun: RX data lost\n");
+ end = true;
}
if (sr & STM32H7_SPI_SR_EOT) {
--
2.17.1
[PATCH v2 4/8] spi: stm32h7: ensure message are smaller than max size
Ensure that messages given to transfer_one handler can actually be
handled by it. For that purpose rely on the SPI framework
spi_split_transfers_maxsize function to split messages whenever necessary.
Signed-off-by: Alain Volmat
---
v2: reordered within the serie
drivers/spi/spi-stm32.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index a46132e81533..8e4db219b95d 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1004,6 +1004,20 @@ static int stm32_spi_prepare_msg(struct spi_master
*master,
!!(spi_dev->mode & SPI_LSB_FIRST),
!!(spi_dev->mode & SPI_CS_HIGH));
+ /* On STM32H7, messages should not exceed a maximum size setted
+* afterward via the set_number_of_data function. In order to
+* ensure that, split large messages into several messages
+*/
+ if (spi->cfg->set_number_of_data) {
+ int ret;
+
+ ret = spi_split_transfers_maxsize(master, msg,
+ STM32H7_SPI_TSIZE_MAX,
+ GFP_KERNEL | GFP_DMA);
+ if (ret)
+ return ret;
+ }
+
spin_lock_irqsave(>lock, flags);
/* CPOL, CPHA and LSB FIRST bits have common register */
--
2.17.1
[PATCH v2 0/8] spi: stm32: fix and enhancements for spi-stm32
The serie provides a fix for the spi-stm32 driver, allowing to properly handle 0 byte transfer (and thus being able to run spi-loopback-test). In addition to that, important enhancements are implemented, among them, supporting transfer larger that what the IP can setup in one go or allowing to use the SPI bus without cs_gpio. v2: Fix within patch 'spi: stm32: properly handle 0 byte transfer' Reorder patches to avoid compilation issue Alain Volmat (5): spi: stm32: properly handle 0 byte transfer spi: stm32: do not mandate cs_gpio spi: stm32h7: ensure message are smaller than max size spi: stm32: defer probe for reset spi: stm32: make spurious and overrun interrupts visible Amelie Delaunay (2): spi: stm32: use bitfield macros spi: stm32h7: replace private SPI_1HZ_NS with NSEC_PER_SEC Etienne Carriere (1): spi: stm32: driver uses reset controller only at init drivers/spi/spi-stm32.c | 114 ++-- 1 file changed, 52 insertions(+), 62 deletions(-) -- 2.17.1
[PATCH v2 2/8] spi: stm32: do not mandate cs_gpio
CS gpios is not mandatory, the driver should allow working
even when CS are not given.
Signed-off-by: Alain Volmat
---
v2: identical to v1
drivers/spi/spi-stm32.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 6cdecd1c5ec7..2b4ea4cba00b 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1944,12 +1944,6 @@ static int stm32_spi_probe(struct platform_device *pdev)
goto err_pm_disable;
}
- if (!master->cs_gpiods) {
- dev_err(>dev, "no CS gpios available\n");
- ret = -EINVAL;
- goto err_pm_disable;
- }
-
dev_info(>dev, "driver initialized\n");
return 0;
--
2.17.1
[PATCH v2 3/8] spi: stm32: use bitfield macros
From: Amelie Delaunay
To avoid defining shift and mask separately and hand-coding the bit
manipulation, use the bitfield macros.
Signed-off-by: Amelie Delaunay
Signed-off-by: Alain Volmat
---
v2: reordered within the serie
drivers/spi/spi-stm32.c | 54 ++---
1 file changed, 18 insertions(+), 36 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 2b4ea4cba00b..a46132e81533 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -5,6 +5,7 @@
// Copyright (C) 2017, STMicroelectronics - All Rights Reserved
// Author(s): Amelie Delaunay for STMicroelectronics.
+#include
#include
#include
#include
@@ -94,27 +95,22 @@
#define STM32H7_SPI_CR1_SSIBIT(12)
/* STM32H7_SPI_CR2 bit fields */
-#define STM32H7_SPI_CR2_TSIZE_SHIFT0
#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
+#define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0)
/* STM32H7_SPI_CFG1 bit fields */
-#define STM32H7_SPI_CFG1_DSIZE_SHIFT 0
#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
-#define STM32H7_SPI_CFG1_FTHLV_SHIFT 5
#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
#define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
#define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
-#define STM32H7_SPI_CFG1_MBR_SHIFT 28
#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
+#define STM32H7_SPI_CFG1_MBR_SHIFT 28
#define STM32H7_SPI_CFG1_MBR_MIN 0
#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
/* STM32H7_SPI_CFG2 bit fields */
-#define STM32H7_SPI_CFG2_MIDI_SHIFT4
#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
-#define STM32H7_SPI_CFG2_COMM_SHIFT17
#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
-#define STM32H7_SPI_CFG2_SP_SHIFT 19
#define STM32H7_SPI_CFG2_SPGENMASK(21, 19)
#define STM32H7_SPI_CFG2_MASTERBIT(22)
#define STM32H7_SPI_CFG2_LSBFRST BIT(23)
@@ -140,7 +136,6 @@
#define STM32H7_SPI_SR_OVR BIT(6)
#define STM32H7_SPI_SR_MODFBIT(9)
#define STM32H7_SPI_SR_SUSPBIT(11)
-#define STM32H7_SPI_SR_RXPLVL_SHIFT13
#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
#define STM32H7_SPI_SR_RXWNE BIT(15)
@@ -417,9 +412,7 @@ static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
- max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
- STM32H7_SPI_CFG1_DSIZE_SHIFT;
- max_bpw += 1;
+ max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1;
spin_unlock_irqrestore(>lock, flags);
@@ -587,8 +580,7 @@ static void stm32f4_spi_read_rx(struct stm32_spi *spi)
static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
{
u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
- u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
-STM32H7_SPI_SR_RXPLVL_SHIFT;
+ u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
while ((spi->rx_len > 0) &&
((sr & STM32H7_SPI_SR_RXP) ||
@@ -615,8 +607,7 @@ static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi,
bool flush)
}
sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
- rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
-STM32H7_SPI_SR_RXPLVL_SHIFT;
+ rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
}
dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
@@ -1385,15 +1376,13 @@ static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
bpw = spi->cur_bpw - 1;
cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
- cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
-STM32H7_SPI_CFG1_DSIZE;
+ cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw);
spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
fthlv = spi->cur_fthlv - 1;
cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
- cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
-STM32H7_SPI_CFG1_FTHLV;
+ cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv);
writel_relaxed(
(readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
@@ -1411,8 +1400,7 @@ static void stm32_spi_set_mbr(struct stm32_spi *spi, u32
mbrdiv)
u32 clrb = 0, setb = 0;
clrb |= spi->cfg->regs->br.mask;
- setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) &
- spi->cfg->regs->br.mask;
+ setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask;
writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
[PATCH v2 6/8] spi: stm32: defer probe for reset
Defer the probe operation when a reset controller device is expected
but have not yet been probed.
This change replaces use of devm_reset_control_get_exclusive() with
devm_reset_control_get_optional_exclusive() as reset controller is
optional which is now explicitly stated.
Signed-off-by: Alain Volmat
---
v2: reordered within the serie
drivers/spi/spi-stm32.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 561234829110..54196cecfe2e 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1871,8 +1871,14 @@ static int stm32_spi_probe(struct platform_device *pdev)
goto err_clk_disable;
}
- rst = devm_reset_control_get_exclusive(>dev, NULL);
- if (!IS_ERR(rst)) {
+ rst = devm_reset_control_get_optional_exclusive(>dev, NULL);
+ if (rst) {
+ if (IS_ERR(rst)) {
+ ret = dev_err_probe(>dev, PTR_ERR(rst),
+ "failed to get reset\n");
+ goto err_clk_disable;
+ }
+
reset_control_assert(rst);
udelay(2);
reset_control_deassert(rst);
--
2.17.1
[PATCH v2 1/8] spi: stm32: properly handle 0 byte transfer
On 0 byte transfer request, return straight from the
xfer function after finalizing the transfer.
Fixes: dcbe0d84dfa5 ("spi: add driver for STM32 SPI controller")
Signed-off-by: Alain Volmat
---
v2: remove useless spi_finalize_current_transfer
drivers/spi/spi-stm32.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index db3e305d9ec4..6cdecd1c5ec7 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1657,6 +1657,10 @@ static int stm32_spi_transfer_one(struct spi_master
*master,
struct stm32_spi *spi = spi_master_get_devdata(master);
int ret;
+ /* Don't do anything on 0 bytes transfers */
+ if (transfer->len == 0)
+ return 0;
+
spi->tx_buf = transfer->tx_buf;
spi->rx_buf = transfer->rx_buf;
spi->tx_len = spi->tx_buf ? transfer->len : 0;
--
2.17.1
Re: [PATCH 5/8] spi: stm32: defer probe for reset
Hi Mark, sorry about that, I've just noticed the issue. This is probably due to modification of patches ordering I did. STM32H7_SPI_TSIZE_MAX is introduced in the PATCH 6/8 and this is the reason why PATCH 5/8 doesn't build properly. I'll rework that to ensure that all patches compile properly. Sorry again, Alain On Fri, Feb 05, 2021 at 04:41:54PM +, Mark Brown wrote: > On Fri, Feb 05, 2021 at 12:08:59PM +0100, Alain Volmat wrote: > > Defer the probe operation when a reset controller device is expected > > but have not yet been probed. > > > > This change replaces use of devm_reset_control_get_exclusive() with > > devm_reset_control_get_optional_exclusive() as reset controller is > > optional which is now explicitly stated. > > This has trouble building an x86 allmodconfig build: > > /mnt/kernel/drivers/spi/spi-stm32.c: In function 'stm32_spi_prepare_msg': > /mnt/kernel/drivers/spi/spi-stm32.c:1022:9: error: 'STM32H7_SPI_TSIZE_MAX' > undeclared (first use in this function); did you mean 'STM32H7_SPI_CR1_MASRX'? > STM32H7_SPI_TSIZE_MAX, > ^ > STM32H7_SPI_CR1_MASRX > /mnt/kernel/drivers/spi/spi-stm32.c:1022:9: note: each undeclared identifier > is reported only once for each function it appears in > > This may be due to an earlier patch in the series, my script is working > back through the patch series.
[PATCH 5/8] spi: stm32: defer probe for reset
Defer the probe operation when a reset controller device is expected
but have not yet been probed.
This change replaces use of devm_reset_control_get_exclusive() with
devm_reset_control_get_optional_exclusive() as reset controller is
optional which is now explicitly stated.
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 22bd3d1c8d69..c40cea0640e6 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1891,8 +1891,14 @@ static int stm32_spi_probe(struct platform_device *pdev)
goto err_clk_disable;
}
- rst = devm_reset_control_get_exclusive(>dev, NULL);
- if (!IS_ERR(rst)) {
+ rst = devm_reset_control_get_optional_exclusive(>dev, NULL);
+ if (rst) {
+ if (IS_ERR(rst)) {
+ ret = dev_err_probe(>dev, PTR_ERR(rst),
+ "failed to get reset\n");
+ goto err_clk_disable;
+ }
+
reset_control_assert(rst);
udelay(2);
reset_control_deassert(rst);
--
2.17.1
[PATCH 1/8] spi: stm32: properly handle 0 byte transfer
On 0 byte transfer request, return straight from the
xfer function after finalizing the transfer.
Fixes: dcbe0d84dfa5 ("spi: add driver for STM32 SPI controller")
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index db3e305d9ec4..137213633e6d 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1657,6 +1657,12 @@ static int stm32_spi_transfer_one(struct spi_master
*master,
struct stm32_spi *spi = spi_master_get_devdata(master);
int ret;
+ /* Don't do anything on 0 bytes transfers */
+ if (transfer->len == 0) {
+ spi_finalize_current_transfer(master);
+ return 0;
+ }
+
spi->tx_buf = transfer->tx_buf;
spi->rx_buf = transfer->rx_buf;
spi->tx_len = spi->tx_buf ? transfer->len : 0;
--
2.17.1
[PATCH 3/8] spi: stm32h7: ensure message are smaller than max size
Ensure that messages given to transfer_one handler can actually be
handled by it. For that purpose rely on the SPI framework
spi_split_transfers_maxsize function to split messages whenever necessary.
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 8c6af3aa0dc3..417a2aa2b98d 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1013,6 +1013,20 @@ static int stm32_spi_prepare_msg(struct spi_master
*master,
!!(spi_dev->mode & SPI_LSB_FIRST),
!!(spi_dev->mode & SPI_CS_HIGH));
+ /* On STM32H7, messages should not exceed a maximum size setted
+* afterward via the set_number_of_data function. In order to
+* ensure that, split large messages into several messages
+*/
+ if (spi->cfg->set_number_of_data) {
+ int ret;
+
+ ret = spi_split_transfers_maxsize(master, msg,
+ STM32H7_SPI_TSIZE_MAX,
+ GFP_KERNEL | GFP_DMA);
+ if (ret)
+ return ret;
+ }
+
spin_lock_irqsave(>lock, flags);
/* CPOL, CPHA and LSB FIRST bits have common register */
--
2.17.1
[PATCH 2/8] spi: stm32: do not mandate cs_gpio
CS gpios is not mandatory, the driver should allow working
even when CS are not given.
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 137213633e6d..8c6af3aa0dc3 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1946,12 +1946,6 @@ static int stm32_spi_probe(struct platform_device *pdev)
goto err_pm_disable;
}
- if (!master->cs_gpiods) {
- dev_err(>dev, "no CS gpios available\n");
- ret = -EINVAL;
- goto err_pm_disable;
- }
-
dev_info(>dev, "driver initialized\n");
return 0;
--
2.17.1
[PATCH 7/8] spi: stm32h7: replace private SPI_1HZ_NS with NSEC_PER_SEC
From: Amelie Delaunay
Replace SPI_1HZ_NS private constant with NSEC_PER_SEC, which is easier
to read and understand.
Signed-off-by: Amelie Delaunay
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index cacd5b4b6823..7692e2778df5 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -162,8 +162,6 @@
#define SPI_3WIRE_TX 3
#define SPI_3WIRE_RX 4
-#define SPI_1HZ_NS 10
-
/*
* use PIO for small transfers, avoiding DMA setup/teardown overhead for
drivers
* without fifo buffers.
@@ -1525,7 +1523,7 @@ static void stm32h7_spi_data_idleness(struct stm32_spi
*spi, u32 len)
cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
if ((len > 1) && (spi->cur_midi > 0)) {
- u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
+ u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed);
u32 midi = min_t(u32,
DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
FIELD_GET(STM32H7_SPI_CFG2_MIDI,
--
2.17.1
[PATCH 0/8] spi: stm32: fix and enhancements for spi-stm32
The serie provides a fix for the spi-stm32 driver, allowing to properly handle 0 byte transfer (and thus being able to run spi-loopback-test). In addition to that, important enhancements are implemented, among them, supporting transfer larger that what the IP can setup in one go or allowing to use the SPI bus without cs_gpio. Alain Volmat (5): spi: stm32: properly handle 0 byte transfer spi: stm32: do not mandate cs_gpio spi: stm32h7: ensure message are smaller than max size spi: stm32: defer probe for reset spi: stm32: make spurious and overrun interrupts visible Amelie Delaunay (2): spi: stm32: use bitfield macros spi: stm32h7: replace private SPI_1HZ_NS with NSEC_PER_SEC Etienne Carriere (1): spi: stm32: driver uses reset controller only at init drivers/spi/spi-stm32.c | 116 +++- 1 file changed, 54 insertions(+), 62 deletions(-) -- 2.17.1
[PATCH 6/8] spi: stm32: use bitfield macros
From: Amelie Delaunay
To avoid defining shift and mask separately and hand-coding the bit
manipulation, use the bitfield macros.
Signed-off-by: Amelie Delaunay
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 54 ++---
1 file changed, 18 insertions(+), 36 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index c40cea0640e6..cacd5b4b6823 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -5,6 +5,7 @@
// Copyright (C) 2017, STMicroelectronics - All Rights Reserved
// Author(s): Amelie Delaunay for STMicroelectronics.
+#include
#include
#include
#include
@@ -94,27 +95,22 @@
#define STM32H7_SPI_CR1_SSIBIT(12)
/* STM32H7_SPI_CR2 bit fields */
-#define STM32H7_SPI_CR2_TSIZE_SHIFT0
#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
+#define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0)
/* STM32H7_SPI_CFG1 bit fields */
-#define STM32H7_SPI_CFG1_DSIZE_SHIFT 0
#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
-#define STM32H7_SPI_CFG1_FTHLV_SHIFT 5
#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
#define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
#define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
-#define STM32H7_SPI_CFG1_MBR_SHIFT 28
#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
+#define STM32H7_SPI_CFG1_MBR_SHIFT 28
#define STM32H7_SPI_CFG1_MBR_MIN 0
#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
/* STM32H7_SPI_CFG2 bit fields */
-#define STM32H7_SPI_CFG2_MIDI_SHIFT4
#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
-#define STM32H7_SPI_CFG2_COMM_SHIFT17
#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
-#define STM32H7_SPI_CFG2_SP_SHIFT 19
#define STM32H7_SPI_CFG2_SPGENMASK(21, 19)
#define STM32H7_SPI_CFG2_MASTERBIT(22)
#define STM32H7_SPI_CFG2_LSBFRST BIT(23)
@@ -140,7 +136,6 @@
#define STM32H7_SPI_SR_OVR BIT(6)
#define STM32H7_SPI_SR_MODFBIT(9)
#define STM32H7_SPI_SR_SUSPBIT(11)
-#define STM32H7_SPI_SR_RXPLVL_SHIFT13
#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
#define STM32H7_SPI_SR_RXWNE BIT(15)
@@ -415,9 +410,7 @@ static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
- max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
- STM32H7_SPI_CFG1_DSIZE_SHIFT;
- max_bpw += 1;
+ max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1;
spin_unlock_irqrestore(>lock, flags);
@@ -585,8 +578,7 @@ static void stm32f4_spi_read_rx(struct stm32_spi *spi)
static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
{
u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
- u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
-STM32H7_SPI_SR_RXPLVL_SHIFT;
+ u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
while ((spi->rx_len > 0) &&
((sr & STM32H7_SPI_SR_RXP) ||
@@ -613,8 +605,7 @@ static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi,
bool flush)
}
sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
- rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
-STM32H7_SPI_SR_RXPLVL_SHIFT;
+ rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
}
dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
@@ -1397,15 +1388,13 @@ static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
bpw = spi->cur_bpw - 1;
cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
- cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
-STM32H7_SPI_CFG1_DSIZE;
+ cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw);
spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
fthlv = spi->cur_fthlv - 1;
cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
- cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
-STM32H7_SPI_CFG1_FTHLV;
+ cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv);
writel_relaxed(
(readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
@@ -1423,8 +1412,7 @@ static void stm32_spi_set_mbr(struct stm32_spi *spi, u32
mbrdiv)
u32 clrb = 0, setb = 0;
clrb |= spi->cfg->regs->br.mask;
- setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) &
- spi->cfg->regs->br.mask;
+ setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask;
writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
~clrb) | setb,
@@ -1515,8 +1503
[PATCH 4/8] spi: stm32: driver uses reset controller only at init
From: Etienne Carriere
Remove reset controller device reference from the device private
structure since it is used only at probe time and can be discarded
once used to reset the SPI device.
Signed-off-by: Etienne Carriere
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 417a2aa2b98d..22bd3d1c8d69 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -268,7 +268,6 @@ struct stm32_spi_cfg {
* @base: virtual memory area
* @clk: hw kernel clock feeding the SPI clock generator
* @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
- * @rst: SPI controller reset line
* @lock: prevent I/O concurrent access
* @irq: SPI controller interrupt line
* @fifo_size: size of the embedded fifo in bytes
@@ -294,7 +293,6 @@ struct stm32_spi {
void __iomem *base;
struct clk *clk;
u32 clk_rate;
- struct reset_control *rst;
spinlock_t lock; /* prevent I/O concurrent access */
int irq;
unsigned int fifo_size;
@@ -1831,6 +1829,7 @@ static int stm32_spi_probe(struct platform_device *pdev)
struct spi_master *master;
struct stm32_spi *spi;
struct resource *res;
+ struct reset_control *rst;
int ret;
master = spi_alloc_master(>dev, sizeof(struct stm32_spi));
@@ -1892,11 +1891,11 @@ static int stm32_spi_probe(struct platform_device *pdev)
goto err_clk_disable;
}
- spi->rst = devm_reset_control_get_exclusive(>dev, NULL);
- if (!IS_ERR(spi->rst)) {
- reset_control_assert(spi->rst);
+ rst = devm_reset_control_get_exclusive(>dev, NULL);
+ if (!IS_ERR(rst)) {
+ reset_control_assert(rst);
udelay(2);
- reset_control_deassert(spi->rst);
+ reset_control_deassert(rst);
}
if (spi->cfg->has_fifo)
--
2.17.1
[PATCH 8/8] spi: stm32: make spurious and overrun interrupts visible
We do not expect to receive spurious interrupts so rise a warning
if it happens.
RX overrun is an error condition that signals a corrupted RX
stream both in dma and in irq modes. Report the error and
abort the transfer in either cases.
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 7692e2778df5..e7699758c609 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -895,8 +895,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void
*dev_id)
mask |= STM32H7_SPI_SR_RXP;
if (!(sr & mask)) {
- dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
- sr, ier);
+ dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
+sr, ier);
spin_unlock_irqrestore(>lock, flags);
return IRQ_NONE;
}
@@ -923,15 +923,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void
*dev_id)
}
if (sr & STM32H7_SPI_SR_OVR) {
- dev_warn(spi->dev, "Overrun: received value discarded\n");
- if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
- stm32h7_spi_read_rxfifo(spi, false);
- /*
-* If overrun is detected while using DMA, it means that
-* something went wrong, so stop the current transfer
-*/
- if (spi->cur_usedma)
- end = true;
+ dev_err(spi->dev, "Overrun: RX data lost\n");
+ end = true;
}
if (sr & STM32H7_SPI_SR_EOT) {
--
2.17.1
[PATCH 1/5] i2c: stm32f7: fix configuration of the digital filter
The digital filter related computation are present in the driver
however the programming of the filter within the IP is missing.
The maximum value for the DNF is wrong and should be 15 instead of 16.
Fixes: aeb068c57214 ("i2c: i2c-stm32f7: add driver")
Signed-off-by: Alain Volmat
---
drivers/i2c/busses/i2c-stm32f7.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index 9aa8e65b511e..473fbe144b7e 100644
--- a/drivers/i2c/busses/i2c-stm32f7.c
+++ b/drivers/i2c/busses/i2c-stm32f7.c
@@ -57,6 +57,8 @@
#define STM32F7_I2C_CR1_RXDMAENBIT(15)
#define STM32F7_I2C_CR1_TXDMAENBIT(14)
#define STM32F7_I2C_CR1_ANFOFF BIT(12)
+#define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)
+#define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
#define STM32F7_I2C_CR1_ERRIE BIT(7)
#define STM32F7_I2C_CR1_TCIE BIT(6)
#define STM32F7_I2C_CR1_STOPIE BIT(5)
@@ -160,7 +162,7 @@ enum {
};
#define STM32F7_I2C_DNF_DEFAULT0
-#define STM32F7_I2C_DNF_MAX16
+#define STM32F7_I2C_DNF_MAX15
#define STM32F7_I2C_ANALOG_FILTER_ENABLE 1
#define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN50 /* ns */
@@ -725,6 +727,13 @@ static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev
*i2c_dev)
else
stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
STM32F7_I2C_CR1_ANFOFF);
+
+ /* Program the Digital Filter */
+ stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
+STM32F7_I2C_CR1_DNF_MASK);
+ stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
+STM32F7_I2C_CR1_DNF(i2c_dev->setup.dnf));
+
stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
STM32F7_I2C_CR1_PE);
}
--
2.17.1
