Re: [PATCH 0/2] sunxi: Enforce consistent MMC numbering
On Mon, 19 Apr 2021 11:17:19 +0800 Chen-Yu Tsai wrote: Hi, > On Mon, Apr 19, 2021 at 10:52 AM Samuel Holland wrote: > > > > Dealing with the inconsistent numbering has been a major pain, and > > there is a solution with (as far as I can tell) no tangible downsides. > > So let's use it. Thanks Samuel for sending this! > > Yes, I know the kernel supports UUIDs for root=. But UUIDs do not help > > when referencing the whole, unpartitioned device, like is needed for > > updating the bootloader and firmware. So for the use case of "write a > > bootloader to the SD card, regardless of where the board is currently > > booted from", I know of two options: > > - Dig around in sysfs to find the mmc number from the MMIO address, > > which means I have to know the MMIO addresses for every SoC, or > > - Apply patches like these. > > > > Samuel Holland (2): > > ARM: dts: sunxi: h3/h5: Enforce consistent MMC numbering > > arm64: dts: allwinner: Enforce consistent MMC numbering > > > > arch/arm/boot/dts/sunxi-h3-h5.dtsi| 6 ++ > > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 6 ++ > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 6 ++ > > At least with Rockchip this is now done at the board level. IIRC it was > a request from other people to not do it at the SoC level. I don't recall > exactly who though. FWIW, I am very much in favour of these patches, at a SoC level: The *SoC* BootROM imposes an order, by probing the first (by MMIO address order) MMC controller first for boot devices. IIRC that's a different story for Rockchip? And if people really don't care about the order, then having a certain order doesn't hurt, so we could as well use the "natural" order, as it was before. Also UUIDs only help if you boot with an initramfs to resolve them, which proves to be extra pain if you don't compile kernels on the device, or not inside a distribution environment. One thing I was wondering about though is that U-Boot currently defines "mmc1 = ", so that the eMMC is always MMC device 1. This is also the BootROM probe order (MMC1 is never touched). I wonder if we should mimic this here, since MMC2 is clearly the device for eMMC (due to 8-bit bus width support)? So from a block device perspective we would have always have mmcblk0 and mmcblk1. Otherwise it would conflict with U-Boot's current fixup[1], so U-Boot's DT would either need to deviate or create boot script breakages there. Cheers, Andre [1] https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/dts/sunxi-u-boot.dtsi#L14-16
Re: linux-next: Signed-off-by missing for commit in the arm64 tree
On Wed, 24 Mar 2021 15:46:14 +
Catalin Marinas wrote:
> On Wed, Mar 24, 2021 at 08:14:45AM +1100, Stephen Rothwell wrote:
> > Commits
> >
> > b17f265bb4cc ("kselftest/arm64: mte: Fix MTE feature detection")
> > 4dfc9d30a8ab ("kselftest/arm64: mte: common: Fix write() warnings")
> >
> > are missing a Signed-off-by from their author.
>
> Thanks Stephen. Now fixed.
Thanks Catalin, and apologies for the blunder, that's what I get from
trying multitasking with just a single X chromosome ;-)
Cheers,
Andre
Re: [RFC PATCH] arm64: dts: allwinner: a64/h5: Add CPU idle states
On Mon, 22 Mar 2021 01:25:14 -0500 Samuel Holland wrote: Hi, > Powering off idle CPUs saves about 33 mW compared to using WFI only. > Additional power savings are possible by idling the L2 and downclocking > the cluster when all CPUs are idle. > > Entry and exit latency were measured using a logic analyzer, with GPIO > pins toggled in Linux after the calls to trace_cpu_idle() in > cpuidle_enter_state(), and in the power management firmware after CPU > power-off completes and immediately after detecting an interrupt. > > 800 us and 1500 us are worst-case values, largely driven by the fact > that the power management firmware is single threaded. It can only > handle commands to power off CPUs one at a time, and it cannot process > any commands while powering on a CPU in response to an interrupt. > > The cluster suspend process reliably takes 36 us; I rounded this up to > 50 us. If all CPUs enter the cluster idle state at the same time, exit > latency is actually reduced, because there is no contention in that > case. However, if only some CPUs enter the cluster idle state, behavior > is the same as for CPU idle. > > Polling delay for the power management firmware to detect a pending > interrupt is insignificant; it is less than 20 us. > > min-residency was chosen as the point where enabling the idle state > consumed no more average power than disabling the idle state at a > variety of interrupt rates. > > Signed-off-by: Samuel Holland > --- > > I'm sending this patch as an RFC because it raises questions about how > we handle firmware versioning. How far back does (or should) our support > for old TF-A and Crust versions go? > > cpuidle has a problem that without working firmware support, CPUs will > enter idle states and be unable to wake up. As a result, the system will > hang at some point during boot, usually before getting to userspace. > > For over a year[0], TF-A has exposed the PSCI CPU_SUSPEND function when > a SCPI implementation is present[1]. Implementing CPU_SUSPEND is > required for implementing SYSTEM_SUSPEND[2], even if CPU_SUSPEND is not > itself used for anything. > > However, there was no code to actually wake up a CPU once it called the > CPU_SUSPEND function, because I could not find the register providing > the necessary information. The fact that CPU_SUSPEND was broken affected > nobody, because nothing ever called it -- there were no idle states in > the DTS. In hindsight, what I should have done was always return failure > from sunxi_validate_power_state(), but that ship has long sailed. > > I finally found the elusive register and implemented the wakeup code > earlier this month[3]. So now, CPU_SUSPEND actually works, if all of > your firmware is up to date, and cpuidle works if you add the states in > your device tree. > > Unfortunately, there is currently nothing verifying that compatibility. > So you can get into four possible scenarios: > 1) No idle states in DTS, any firmware => Linux works, with baseline > power consumption. > 2) Idle states added to DTS, no Crust/SCPI => Linux works, but every > attempt to enter an idle state is rejected because CPU_SUSPEND is > not hooked up. So power consumption increases by a sizable amount. > 3) Idle states added to DTS, "old" Crust/SCPI (before [3]) => Linux > fails to boot, because CPUs never return from idle states. > 4) Idle states added to DTS, "new" Crust/SCPI (after [3]) => Linux > works, with improved power consumption compared to the baseline. > > Obviously, we want to prevent scenario 3 if possible. So I think the core of the problem is that the DT describes some firmware feature, but we have the DT bundled with the kernel, not the firmware. So is there any way we can detect an older crust version in U-Boot, then remove any potential idle states from the DT? Granted, this requires recent U-Boot as well, but at least we could try to mitigate the worst case a bit? A better solution could be to only *add* the idle states if the rest of the firmware is deemed worthy. So the mainline DTs would not carry the properties in the first place, and only U-Boot adds them, on detecting a capable firmware? Admittedly this changes the "flow" of the DT, where the kernel is the authority, but it might help to solve this problem? Or any other way, which involves U-Boot patching the DTB? (This would apply to the DTB passed to the kernel, regardless of where and when it's loaded from) Any opinions? Cheers, Andre > Enter the current patch: I chose the arm,psci-suspend-param values > specifically so they would be _rejected_ by the current TF-A code. This > makes scenario 3 behave like scenario 2. I then have some follow-up TF-A > patches (not yet submitted) to switch to the new parameter encoding[4]. > > This brings me back to my original question. Once the TF-A patches in > [4] are merged, scenario 3 (with an updated TF-A but an old Crust) would > fail to boot again. Do we care? > > Should I
Re: [PATCH v18 5/7] clocksource: Add clocksource id for arm arch counter
On Mon, 8 Feb 2021 13:40:27 +
Marc Zyngier wrote:
> From: Jianyong Wu
>
> Add clocksource id to the ARM generic counter so that it can be easily
> identified from callers such as ptp_kvm.
>
> Cc: Mark Rutland
> Signed-off-by: Jianyong Wu
> Signed-off-by: Marc Zyngier
> Link: https://lore.kernel.org/r/20201209060932.212364-6-jianyong...@arm.com
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> drivers/clocksource/arm_arch_timer.c | 2 ++
> include/linux/clocksource_ids.h | 1 +
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/clocksource/arm_arch_timer.c
> b/drivers/clocksource/arm_arch_timer.c
> index d0177824c518..8f12e223703f 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -16,6 +16,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -191,6 +192,7 @@ static u64 arch_counter_read_cc(const struct cyclecounter
> *cc)
>
> static struct clocksource clocksource_counter = {
> .name = "arch_sys_counter",
> + .id = CSID_ARM_ARCH_COUNTER,
> .rating = 400,
> .read = arch_counter_read,
> .mask = CLOCKSOURCE_MASK(56),
> diff --git a/include/linux/clocksource_ids.h b/include/linux/clocksource_ids.h
> index 4d8e19e05328..16775d7d8f8d 100644
> --- a/include/linux/clocksource_ids.h
> +++ b/include/linux/clocksource_ids.h
> @@ -5,6 +5,7 @@
> /* Enum to give clocksources a unique identifier */
> enum clocksource_ids {
> CSID_GENERIC= 0,
> + CSID_ARM_ARCH_COUNTER,
> CSID_MAX,
> };
>
Re: [PATCH v18 3/7] ptp: Reorganize ptp_kvm.c to make it arch-independent
On Mon, 8 Feb 2021 13:40:25 +
Marc Zyngier wrote:
> From: Jianyong Wu
>
> Currently, the ptp_kvm module contains a lot of x86-specific code.
> Let's move this code into a new arch-specific file in the same directory,
> and rename the arch-independent file to ptp_kvm_common.c.
>
> Signed-off-by: Jianyong Wu
> Signed-off-by: Marc Zyngier
> Link: https://lore.kernel.org/r/20201209060932.212364-4-jianyong...@arm.com
Verified that the code movements are correct. Test compiled for x86.
1.5 nits below, but regardless:
Reviewed-by: Andre Przywara
> ---
> drivers/ptp/Makefile| 1 +
> drivers/ptp/{ptp_kvm.c => ptp_kvm_common.c} | 84 +-
> drivers/ptp/ptp_kvm_x86.c | 97 +
> include/linux/ptp_kvm.h | 19
> 4 files changed, 139 insertions(+), 62 deletions(-)
> rename drivers/ptp/{ptp_kvm.c => ptp_kvm_common.c} (60%)
> create mode 100644 drivers/ptp/ptp_kvm_x86.c
> create mode 100644 include/linux/ptp_kvm.h
>
> diff --git a/drivers/ptp/Makefile b/drivers/ptp/Makefile
> index db5aef3bddc6..d11eeb5811d1 100644
> --- a/drivers/ptp/Makefile
> +++ b/drivers/ptp/Makefile
> @@ -4,6 +4,7 @@
> #
>
> ptp-y:= ptp_clock.o ptp_chardev.o
> ptp_sysfs.o
> +ptp_kvm-$(CONFIG_X86):= ptp_kvm_x86.o
> ptp_kvm_common.o
> obj-$(CONFIG_PTP_1588_CLOCK) += ptp.o
> obj-$(CONFIG_PTP_1588_CLOCK_DTE) += ptp_dte.o
> obj-$(CONFIG_PTP_1588_CLOCK_INES)+= ptp_ines.o
> diff --git a/drivers/ptp/ptp_kvm.c b/drivers/ptp/ptp_kvm_common.c
> similarity index 60%
> rename from drivers/ptp/ptp_kvm.c
> rename to drivers/ptp/ptp_kvm_common.c
> index 658d33fc3195..721ddcede5e1 100644
> --- a/drivers/ptp/ptp_kvm.c
> +++ b/drivers/ptp/ptp_kvm_common.c
> @@ -8,11 +8,11 @@
> #include
> #include
> #include
> +#include
> #include
> +#include
> #include
> #include
> -#include
> -#include
> #include
>
> #include
> @@ -24,56 +24,29 @@ struct kvm_ptp_clock {
>
> static DEFINE_SPINLOCK(kvm_ptp_lock);
>
> -static struct pvclock_vsyscall_time_info *hv_clock;
> -
> -static struct kvm_clock_pairing clock_pair;
> -static phys_addr_t clock_pair_gpa;
> -
> static int ptp_kvm_get_time_fn(ktime_t *device_time,
> struct system_counterval_t *system_counter,
> void *ctx)
> {
> - unsigned long ret;
> + long ret;
> + u64 cycle;
> struct timespec64 tspec;
> - unsigned version;
> - int cpu;
> - struct pvclock_vcpu_time_info *src;
> + struct clocksource *cs;
>
> spin_lock(_ptp_lock);
>
> preempt_disable_notrace();
> - cpu = smp_processor_id();
> - src = _clock[cpu].pvti;
> -
> - do {
> - /*
> - * We are using a TSC value read in the hosts
> - * kvm_hc_clock_pairing handling.
> - * So any changes to tsc_to_system_mul
> - * and tsc_shift or any other pvclock
> - * data invalidate that measurement.
> - */
> - version = pvclock_read_begin(src);
> -
> - ret = kvm_hypercall2(KVM_HC_CLOCK_PAIRING,
> - clock_pair_gpa,
> - KVM_CLOCK_PAIRING_WALLCLOCK);
> - if (ret != 0) {
> - pr_err_ratelimited("clock pairing hypercall ret %lu\n",
> ret);
> - spin_unlock(_ptp_lock);
> - preempt_enable_notrace();
> - return -EOPNOTSUPP;
> - }
> -
> - tspec.tv_sec = clock_pair.sec;
> - tspec.tv_nsec = clock_pair.nsec;
> - ret = __pvclock_read_cycles(src, clock_pair.tsc);
> - } while (pvclock_read_retry(src, version));
> + ret = kvm_arch_ptp_get_crosststamp(, , );
> + if (ret) {
> + spin_unlock(_ptp_lock);
> + preempt_enable_notrace();
> + return ret;
> + }
>
> preempt_enable_notrace();
>
> - system_counter->cycles = ret;
> - system_counter->cs = _clock;
> + system_counter->cycles = cycle;
> + system_counter->cs = cs;
>
> *device_time = timespec64_to_ktime(tspec);
>
> @@ -111,22 +84,17 @@ static int ptp_kvm_settime(struct ptp_clock_info *ptp,
>
> static int ptp_kvm_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
> {
> - unsigned long ret;
> + long ret;
> struct timespec64 tspec;
>
> spin_lock(_ptp_lock
Re: [PATCH] ARM: dts: zynq: Add address-cells property to interrupt controllers
On Wed, 3 Feb 2021 15:15:19 +0100
Michal Simek wrote:
> On 2/3/21 3:12 PM, Rob Herring wrote:
> > On Wed, Feb 3, 2021 at 1:01 AM Michal Simek
> > wrote:
> >>
> >>
> >>
> >> On 2/1/21 6:41 PM, Rob Herring wrote:
> >>> On Mon, Feb 1, 2021 at 8:27 AM Michal Simek
> >>> wrote:
>
> The commit 3eb619b2f7d8 ("scripts/dtc: Update to upstream version
> v1.6.0-11-g9d7888cbf19c") updated dtc version which also contained DTC
> commit
> "81e0919a3e21 checks: Add interrupt provider test"
> where reasons for this checking are mentioned as
> "A missing #address-cells property is less critical, but creates
> ambiguities when used in interrupt-map properties, so warn about this as
> well now."
>
> Add address-cells property to gic and gpio nodes to get rid of this
> warning.
> The similar change has been done for ZynqMP too.
> >>>
> >>> FYI, we're going to make this check dependent on having an
> >>> interrupt-map property. So adding these isn't necessary.
> >>
> >> Good to know. Is there going to be report if interrupt-map doesn't
> >> exist? Which can end up with reverting these changes?
> >
> > You mean a warning if '#address-cells' is present and interrupt-map is
> > not? No, that would cause lots of warnings.
>
> yep.
Why would we do that? That sounds dangerous and would be broken if the
IRQ controller is in a generic .dtsi (as it usually is), but the
interrupt map is only in *some* of the board .dts files.
What is the problem of just putting #address-cells = <0>; in the
IRQ controller node, after checking that there currently no interrupt
maps in use and no IRQ children? And be safe for good? That's 16 bytes
in the DTB, IIUC.
Because otherwise we have that lovely ambiguity between the
implicit default #address-cells = 2; and the assumed default of 0.
And that's why I think we also cannot *automatically* add an #ac = <0>;
property, because that would change behaviour.
Cheers,
Andre
> What's the timeline for this? I mean I want to get to state that
> all current warnings are gone that it will be much easier to add stuff
> which we have in soc tree.
>
> Thanks,
> Michal
>
Re: [linux-sunxi] [PATCH v5 04/20] dt-bindings: mfd: axp20x: Add AXP305 compatible (plus optional IRQ)
On Tue, 2 Feb 2021 15:55:50 +0800 Chen-Yu Tsai wrote: Hi, > On Thu, Jan 28, 2021 at 1:26 AM Andre Przywara wrote: > > > > The AXP305 PMIC used in AXP805 seems to be fully compatible to the > ^ > This statement doesn't quite make sense. I assume you wanted to mention > a board or the H616 SoC here? Argh, indeed! > > AXP805 PMIC, so add the proper chain of compatible strings. > > > > Also at least on one board (Orangepi Zero2) there is no interrupt line > > connected to the CPU, so make the "interrupts" property optional. > > > > Signed-off-by: Andre Przywara > > --- > > Documentation/devicetree/bindings/mfd/axp20x.txt | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt > > b/Documentation/devicetree/bindings/mfd/axp20x.txt > > index 4991a6415796..4fd748101e3c 100644 > > --- a/Documentation/devicetree/bindings/mfd/axp20x.txt > > +++ b/Documentation/devicetree/bindings/mfd/axp20x.txt > > @@ -26,10 +26,10 @@ Required properties: > > * "x-powers,axp803" > > * "x-powers,axp806" > > * "x-powers,axp805", "x-powers,axp806" > > +* "x-powers,axp803", "x-powers,axp805", "x-powers,axp806" > > axp305? axp803 is used with A64 IIRC. Oh, well spotted. This AXP naming already confused me when they were all called 80x, now using 30x gave me the rest ;-) Sorry for the blunder! Cheers, Andre > > ChenYu > > > * "x-powers,axp809" > > * "x-powers,axp813" > > - reg: The I2C slave address or RSB hardware address for the AXP chip > > -- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin > > - interrupt-controller: The PMIC has its own internal IRQs > > - #interrupt-cells: Should be set to 1 > > > > @@ -43,6 +43,7 @@ more information: > > AXP20x/LDO3: software-based implementation > > > > Optional properties: > > +- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin > > - x-powers,dcdc-freq: defines the work frequency of DC-DC in KHz > > AXP152/20X: range: 750-1875, Default: 1.5 MHz > > AXP22X/8XX: range: 1800-4050, Default: 3 MHz > > -- > > 2.17.5 > > > > -- > > You received this message because you are subscribed to the Google Groups > > "linux-sunxi" group. > > To unsubscribe from this group and stop receiving emails from it, send an > > email to linux-sunxi+unsubscr...@googlegroups.com. > > To view this discussion on the web, visit > > https://groups.google.com/d/msgid/linux-sunxi/20210127172500.13356-5-andre.przywara%40arm.com. > >
Re: [PATCH v5 12/20] dt-bindings: rtc: sun6i: Add H616 compatible string
On Sun, 31 Jan 2021 14:44:40 +0100 Jernej Škrabec wrote: Hi Jernej, > Dne sreda, 27. januar 2021 ob 18:24:52 CET je Andre Przywara napisal(a): > > Add the obvious compatible name to the existing RTC binding, and pair > > it with the existing H6 fallback compatible string, as the devices are > > compatible. > > After close lookup I would disagree with this observation. Major difference > is > that H616 doesn't support usage of external 32768 Hz oscillator. It uses 24 > MHz oscillator with divider for that case. Due to that change, whole logic > for > external oscillator should go out. Additionally, this logic overwrites > default > value in LOSC_CTRL register, which is not nice (there is no documentation for > those bits). Thanks for the heads up, and I wonder if there is more to that. From comparing the RTC documentation, I wonder if we should actually have incoming clocks in the bindings (the crystals / external clock sources with 32KHz, 16MHz, 24MHz). Then we could actually model which crystals the board provides. It seems like the H6 made the 32KHz OSC optional, and the H616 simply doesn't support it anymore - at the very least I don't see any X32K pins anymore. But more importantly: looking more closely (I only skimmed over the register summary back then) the actual RTC registers are different: the H616 encodes a linear day number (vs. a broken-down D-M-Y), also the time-of-day register is different. So we definitely need a driver update, and hence need to drop this patch. Cheers, Andre > Best regards, > Jernej > > > > > Signed-off-by: Andre Przywara > > Acked-by: Rob Herring > > --- > > .../devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31- > rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml > > index b1b0ee769b71..4193e5813344 100644 > > --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml > > +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml > > @@ -26,6 +26,9 @@ properties: > >- const: allwinner,sun50i-a64-rtc > >- const: allwinner,sun8i-h3-rtc > >- const: allwinner,sun50i-h6-rtc > > + - items: > > + - const: allwinner,sun50i-h616-rtc > > + - const: allwinner,sun50i-h6-rtc > > > >reg: > > maxItems: 1 > > -- > > 2.17.5 > > > > > >
Re: [PATCH v5 05/20] Input: axp20x-pek: Bail out if AXP has no interrupt line connected
On Thu, 28 Jan 2021 11:36:01 + Mark Brown wrote: > On Thu, Jan 28, 2021 at 11:11:28AM +0000, Andre Przywara wrote: > > Dmitry Torokhov wrote: > > > On Wed, Jan 27, 2021 at 05:24:45PM +0000, Andre Przywara wrote: > > > > > Check for the regmap_irqc member to be not NULL before proceeding with > > > > probe. This gets normally filled by the call to regmap_add_irq_chip(), > > > > which we allow to skip now, when the DT node lacks an interrupt > > > > property. > > It sounds like you're trying to register an IRQ chip with a somehow > bogus configuration? Quick background: Those AXP PMICs have an IRQ pin, that was always connected to the NMI pin on Allwinner SoCs. This was used for the power button GPIO interrupt. Now the H616 does not have this pin anymore, and the board does not use a GPIO either. I patched the AXP MFD driver [1] to skip the regmap-irq creation when no interrupts DT property was found, but this NULL pointer now understandably confuses the -pek driver, and leads to this crash: http://lists.infradead.org/pipermail/linux-arm-kernel/2021-January/634969.html Hence I wanted to plug this hole, which seems useful regardless of this particular issue. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2021-January/634971.html > > > No, the driver is not the right place to patch this; regmap should be > > > fixed so it does not crash instead. > > > I am not sure this is the right approach, those regmap functions look > > more like an internal interface to me, with lots of wrapper functions > > happily dereferencing pointers and reaching into structs. Moving > > NULL checks into those does not sound like the right thing. CC:ing Mark > > for more opinions on this. > > Without having seen the actual issue if you're trying to register an > interrupt controller with a known broken hardware configuration that > does seem like something the caller just shouldn't be doing, it's not > something that's going to transiently happen at runtime and we're very > much trusting that the caller got things right. > > > A more general solution would be to not instantiate this driver here > > at all, when we don't have an interrupt line. > > However at the moment the AXP MFD driver uses a const struct to hold > > all MFD cells, so there is no easy way of omitting the power key > > device dynamically. And even then it would hard code the requirement > > for an interrupt into the MFD driver, when this could be considered an > > implementation detail of the axp20x-pek driver. > > Another approach is to just register the optional device separately. I will have a look at how much this takes. Thanks, Andre
Re: [PATCH v5 05/20] Input: axp20x-pek: Bail out if AXP has no interrupt line connected
On Wed, 27 Jan 2021 11:42:15 -0800 Dmitry Torokhov wrote: Hi Dmitry, thanks for your feedback! > On Wed, Jan 27, 2021 at 05:24:45PM +0000, Andre Przywara wrote: > > On at least one board (Orangepi Zero2) the AXP305 PMIC does not have its > > interrupt line connected to the CPU (mostly because the H616 SoC does > > not feature an NMI pin anymore). > > After allowing the AXP driver to proceed without an "interrupts" > > property [1], the axp20x-pek driver crashes with a NULL pointer > > dereference (see below). > > > > Check for the regmap_irqc member to be not NULL before proceeding with > > probe. This gets normally filled by the call to regmap_add_irq_chip(), > > which we allow to skip now, when the DT node lacks an interrupt > > property. > > No, the driver is not the right place to patch this; regmap should be > fixed so it does not crash instead. I am not sure this is the right approach, those regmap functions look more like an internal interface to me, with lots of wrapper functions happily dereferencing pointers and reaching into structs. Moving NULL checks into those does not sound like the right thing. CC:ing Mark for more opinions on this. A more general solution would be to not instantiate this driver here at all, when we don't have an interrupt line. However at the moment the AXP MFD driver uses a const struct to hold all MFD cells, so there is no easy way of omitting the power key device dynamically. And even then it would hard code the requirement for an interrupt into the MFD driver, when this could be considered an implementation detail of the axp20x-pek driver. That's why I came up with this patch here, which was the easiest and cleanest: This driver *requires* a valid regmap_irqc, so it should verify this at probe time, kind of like a normal driver would bail out if no IRQ line could be reserved. Let me know what you think! Cheers, Andre
[PATCH v5 08/20] soc: sunxi: sram: Add support for more than one EMAC clock
The Allwinner H616 adds a second EMAC clock register at offset 0x34, for
controlling the second EMAC in this chip.
Allow to extend the regmap in this case, to cover more than the current
4 bytes exported.
Signed-off-by: Andre Przywara
---
drivers/soc/sunxi/sunxi_sram.c | 31 +++
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
index d4c7bd59429e..42833e33a96c 100644
--- a/drivers/soc/sunxi/sunxi_sram.c
+++ b/drivers/soc/sunxi/sunxi_sram.c
@@ -283,7 +283,7 @@ int sunxi_sram_release(struct device *dev)
EXPORT_SYMBOL(sunxi_sram_release);
struct sunxi_sramc_variant {
- bool has_emac_clock;
+ int num_emac_clocks;
};
static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
@@ -291,20 +291,31 @@ static const struct sunxi_sramc_variant
sun4i_a10_sramc_variant = {
};
static const struct sunxi_sramc_variant sun8i_h3_sramc_variant = {
- .has_emac_clock = true,
+ .num_emac_clocks = 1,
};
static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = {
- .has_emac_clock = true,
+ .num_emac_clocks = 1,
+};
+
+static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
+ .num_emac_clocks = 2,
};
#define SUNXI_SRAM_EMAC_CLOCK_REG 0x30
static bool sunxi_sram_regmap_accessible_reg(struct device *dev,
unsigned int reg)
{
- if (reg == SUNXI_SRAM_EMAC_CLOCK_REG)
- return true;
- return false;
+ const struct sunxi_sramc_variant *variant;
+
+ variant = of_device_get_match_data(dev);
+
+ if (reg < SUNXI_SRAM_EMAC_CLOCK_REG)
+ return false;
+ if (reg > SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
+ return false;
+
+ return true;
}
static struct regmap_config sunxi_sram_emac_clock_regmap = {
@@ -312,7 +323,7 @@ static struct regmap_config sunxi_sram_emac_clock_regmap = {
.val_bits = 32,
.reg_stride = 4,
/* last defined register */
- .max_register = SUNXI_SRAM_EMAC_CLOCK_REG,
+ .max_register = SUNXI_SRAM_EMAC_CLOCK_REG + 4,
/* other devices have no business accessing other registers */
.readable_reg = sunxi_sram_regmap_accessible_reg,
.writeable_reg = sunxi_sram_regmap_accessible_reg,
@@ -343,7 +354,7 @@ static int sunxi_sram_probe(struct platform_device *pdev)
if (!d)
return -ENOMEM;
- if (variant->has_emac_clock) {
+ if (variant->num_emac_clocks > 0) {
emac_clock = devm_regmap_init_mmio(>dev, base,
_sram_emac_clock_regmap);
@@ -387,6 +398,10 @@ static const struct of_device_id sunxi_sram_dt_match[] = {
.compatible = "allwinner,sun50i-h5-system-control",
.data = _a64_sramc_variant,
},
+ {
+ .compatible = "allwinner,sun50i-h616-system-control",
+ .data = _h616_sramc_variant,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
--
2.17.5
[PATCH v5 12/20] dt-bindings: rtc: sun6i: Add H616 compatible string
Add the obvious compatible name to the existing RTC binding, and pair it with the existing H6 fallback compatible string, as the devices are compatible. Signed-off-by: Andre Przywara Acked-by: Rob Herring --- .../devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml index b1b0ee769b71..4193e5813344 100644 --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -26,6 +26,9 @@ properties: - const: allwinner,sun50i-a64-rtc - const: allwinner,sun8i-h3-rtc - const: allwinner,sun50i-h6-rtc + - items: + - const: allwinner,sun50i-h616-rtc + - const: allwinner,sun50i-h6-rtc reg: maxItems: 1 -- 2.17.5
[PATCH v5 09/20] dt-bindings: watchdog: sun4i: Add H616 compatible string
Use enums to group all compatible devices together on the way. Signed-off-by: Andre Przywara Acked-by: Rob Herring Acked-by: Maxime Ripard Reviewed-by: Guenter Roeck --- .../bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 5ac607de8be4..9aa3c313c49f 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -19,13 +19,11 @@ properties: - const: allwinner,sun4i-a10-wdt - const: allwinner,sun6i-a31-wdt - items: - - const: allwinner,sun50i-a64-wdt - - const: allwinner,sun6i-a31-wdt - - items: - - const: allwinner,sun50i-a100-wdt - - const: allwinner,sun6i-a31-wdt - - items: - - const: allwinner,sun50i-h6-wdt + - enum: + - allwinner,sun50i-a64-wdt + - allwinner,sun50i-a100-wdt + - allwinner,sun50i-h6-wdt + - allwinner,sun50i-h616-wdt - const: allwinner,sun6i-a31-wdt - items: - const: allwinner,suniv-f1c100s-wdt -- 2.17.5
[PATCH v5 11/20] dt-bindings: media: IR: Add H616 IR compatible string
Add the obvious compatible name to the existing IR binding, and pair it with the existing A31 fallback compatible string, as the devices are compatible. On the way use enums to group all compatible devices together. Signed-off-by: Andre Przywara Acked-by: Rob Herring --- .../bindings/media/allwinner,sun4i-a10-ir.yaml | 16 ++-- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml index 5fa19d4aeaf3..6d8395d6bca0 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml @@ -20,16 +20,12 @@ properties: - const: allwinner,sun5i-a13-ir - const: allwinner,sun6i-a31-ir - items: - - const: allwinner,sun8i-a83t-ir - - const: allwinner,sun6i-a31-ir - - items: - - const: allwinner,sun8i-r40-ir - - const: allwinner,sun6i-a31-ir - - items: - - const: allwinner,sun50i-a64-ir - - const: allwinner,sun6i-a31-ir - - items: - - const: allwinner,sun50i-h6-ir + - enum: + - allwinner,sun8i-a83t-ir + - allwinner,sun8i-r40-ir + - allwinner,sun50i-a64-ir + - allwinner,sun50i-h6-ir + - allwinner,sun50i-h616-ir - const: allwinner,sun6i-a31-ir reg: -- 2.17.5
[PATCH v5 14/20] dt-bindings: bus: rsb: Add H616 compatible string
Add the obvious compatible name to the existing RSB binding, and pair it with the existing A23 fallback compatible string, as the devices are compatible. Signed-off-by: Andre Przywara --- .../devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml b/Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml index 32d33b983d66..3d719f468a5b 100644 --- a/Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml +++ b/Documentation/devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml @@ -21,7 +21,9 @@ properties: oneOf: - const: allwinner,sun8i-a23-rsb - items: - - const: allwinner,sun8i-a83t-rsb + - enum: + - allwinner,sun8i-a83t-rsb + - allwinner,sun50i-h616-rsb - const: allwinner,sun8i-a23-rsb reg: -- 2.17.5
[PATCH v5 13/20] dt-bindings: spi: sunxi: Add H616 compatible string
Add the obvious compatible name to the existing SPI binding, and pair it with the existing H3 fallback compatible string, as the devices are compatible. Signed-off-by: Andre Przywara Acked-by: Rob Herring --- .../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index 7866a655d81c..908248260afa 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -25,6 +25,7 @@ properties: - enum: - allwinner,sun8i-r40-spi - allwinner,sun50i-h6-spi + - allwinner,sun50i-h616-spi - const: allwinner,sun8i-h3-spi reg: -- 2.17.5
Re: (subset) [PATCH v4 00/21] arm64: sunxi: Initial Allwinner H616 SoC support
On Wed, 27 Jan 2021 17:15:30 + Mark Brown wrote: > On Mon, 25 Jan 2021 15:17:50 +0000, Andre Przywara wrote: > > an update from the v3 last week, to add support for the Allwinner H616 > > SoC. Still based on the (updated) sunxi/for-next branch. > > I am omitting the MMC and pinctrl patches now, as they have been taken > > by Ulf and LinusW already into their trees. > > > > I addressed the comments from the list, though not sure if the HOSC clock > > coming from the RTC is really a good idea (didn't change it). > > > > [...] > > Applied to > >https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next > > Thanks! > > [13/21] dt-bindings: spi: sunxi: Add H616 compatible string > commit: 6589daf8bb98c75ad1065edad87c099ffb9f5d87 Thanks for that. I just sent a v5, just before seeing your email, so this one still has this patch, but without any changes. So please ignore [PATCH v5 13/21]. Cheers, Andre > All being well this means that it will be integrated into the linux-next > tree (usually sometime in the next 24 hours) and sent to Linus during > the next merge window (or sooner if it is a bug fix), however if > problems are discovered then the patch may be dropped or reverted. > > You may get further e-mails resulting from automated or manual testing > and review of the tree, please engage with people reporting problems and > send followup patches addressing any issues that are reported if needed. > > If any updates are required or you are submitting further changes they > should be sent as incremental updates against current git, existing > patches will not be replaced. > > Please add any relevant lists and maintainers to the CCs when replying > to this mail. > > Thanks, > Mark
[PATCH v5 16/20] net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register
The Allwinner H616 SoC has two EMAC controllers, with the second one
being tied to the internal PHY, but also using a separate EMAC clock
register.
To tell the driver about which clock register to use, we add a parameter
to our syscon phandle. The driver will use this value as an index into
the regmap, so that we can address more than the first register, if
needed.
Signed-off-by: Andre Przywara
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 58e0511badba..c7951790ed98 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -1124,11 +1124,13 @@ static int sun8i_dwmac_probe(struct platform_device
*pdev)
struct stmmac_resources stmmac_res;
struct sunxi_priv_data *gmac;
struct device *dev = >dev;
+ struct reg_field syscon_field;
phy_interface_t interface;
int ret;
struct stmmac_priv *priv;
struct net_device *ndev;
struct regmap *regmap;
+ u32 syscon_idx = 0;
ret = stmmac_get_platform_resources(pdev, _res);
if (ret)
@@ -1190,8 +1192,12 @@ static int sun8i_dwmac_probe(struct platform_device
*pdev)
return ret;
}
- gmac->regmap_field = devm_regmap_field_alloc(dev, regmap,
-
*gmac->variant->syscon_field);
+ syscon_field = *gmac->variant->syscon_field;
+ ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1,
+_idx);
+ if (!ret)
+ syscon_field.reg += syscon_idx * sizeof(u32);
+ gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, syscon_field);
if (IS_ERR(gmac->regmap_field)) {
ret = PTR_ERR(gmac->regmap_field);
dev_err(dev, "Unable to map syscon register: %d\n", ret);
@@ -1263,6 +1269,8 @@ static const struct of_device_id sun8i_dwmac_match[] = {
.data = _variant_a64 },
{ .compatible = "allwinner,sun50i-h6-emac",
.data = _variant_h6 },
+ { .compatible = "allwinner,sun50i-h616-emac",
+ .data = _variant_h6 },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
--
2.17.5
[PATCH v5 15/20] dt-bindings: net: sun8i-emac: Add H616 compatible string
Add the obvious compatible name to the existing EMAC binding, and pair it with the existing A64 fallback compatible string, as the devices are compatible. On the way use enums to group the compatible devices together. Signed-off-by: Andre Przywara --- .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml| 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml index 7f2578d48e3f..0ccdab103f59 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -19,7 +19,9 @@ properties: - const: allwinner,sun8i-v3s-emac - const: allwinner,sun50i-a64-emac - items: - - const: allwinner,sun50i-h6-emac + - enum: + - allwinner,sun50i-h6-emac + - allwinner,sun50i-h616-emac - const: allwinner,sun50i-a64-emac reg: -- 2.17.5
[PATCH v5 19/20] dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding
Signed-off-by: Andre Przywara Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 08607c7ec1bf..aeb8771b14c4 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -932,4 +932,9 @@ properties: - const: xunlong,orangepi-zero-plus2-h3 - const: allwinner,sun8i-h3 + - description: Xunlong OrangePi Zero 2 +items: + - const: xunlong,orangepi-zero2 + - const: allwinner,sun50i-h616 + additionalProperties: true -- 2.17.5
[PATCH v5 20/20] arm64: dts: allwinner: Add OrangePi Zero 2 .dts
The OrangePi Zero 2 is a development board with the new H616 SoC.
It features the usual connectors used on those small boards, and comes
with the AXP305, which seems to be compatible with the AXP805.
For more details see: http://linux-sunxi.org/Xunlong_Orange_Pi_Zero2
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/allwinner/Makefile| 1 +
.../allwinner/sun50i-h616-orangepi-zero2.dts | 203 ++
2 files changed, 204 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile
b/arch/arm64/boot/dts/allwinner/Makefile
index 41ce680e5f8d..9ba4b5d92657 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -36,3 +36,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
new file mode 100644
index ..ca07cae698ce
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2020 Arm Ltd.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+
+#include
+#include
+#include
+
+/ {
+ model = "OrangePi Zero2";
+ compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
+
+ aliases {
+ ethernet0 =
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_POWER;
+ color = ;
+ gpios = < 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
+ default-state = "on";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = ;
+ gpios = < 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
+ };
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the USB-C socket */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <_rgmii_phy>;
+ phy-supply = <_dcdce>;
+ allwinner,rx-delay-ps = <3100>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
+ {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+ {
+ vmmc-supply = <_dcdce>;
+ cd-gpios = < 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+_rsb {
+ status = "okay";
+
+ axp305: pmic@745 {
+ compatible = "x-powers,axp305", "x-powers,axp805",
+"x-powers,axp806";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x745>;
+
+ x-powers,self-working-mode;
+ vina-supply = <_vcc5v>;
+ vinb-supply = <_vcc5v>;
+ vinc-supply = <_vcc5v>;
+ vind-supply = <_vcc5v>;
+ vine-supply = <_vcc5v>;
+ aldoin-supply = <_vcc5v>;
+ bldoin-supply = <_vcc5v>;
+ cldoin-supply = <_vcc5v>;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc-sys";
+ };
+
+ reg_aldo2: aldo2 { /* 3.3V on headers */
+ regulator-always-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc3v3-
[PATCH v5 17/20] phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling
As Icenowy pointed out, newer manuals (starting with H6) actually
document the register block at offset 0x800 as "HCI controller and PHY
interface", also describe the bits in our "PMU_UNK1" register.
Let's put proper names to those "unknown" variables and symbols.
While we are at it, generalise the existing code by allowing a bitmap
of bits to clear, to cover newer SoCs: The A100 and H616 use a different
bit for the SIDDQ control.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
drivers/phy/allwinner/phy-sun4i-usb.c | 29 +++
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 788dd5cdbb7d..539209fe3468 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -43,7 +43,7 @@
#define REG_PHYCTL_A33 0x10
#define REG_PHY_OTGCTL 0x20
-#define REG_PMU_UNK1 0x10
+#define REG_HCI_PHY_CTL0x10
#define PHYCTL_DATABIT(7)
@@ -115,9 +115,9 @@ struct sun4i_usb_phy_cfg {
int hsic_index;
enum sun4i_usb_phy_type type;
u32 disc_thresh;
+ u32 hci_phy_ctl_siddq;
u8 phyctl_offset;
bool dedicated_clocks;
- bool enable_pmu_unk1;
bool phy0_dual_route;
int missing_phys;
};
@@ -288,6 +288,12 @@ static int sun4i_usb_phy_init(struct phy *_phy)
return ret;
}
+ if (phy->pmu && data->cfg->hci_phy_ctl_siddq) {
+ val = readl(phy->pmu + REG_HCI_PHY_CTL);
+ val &= ~data->cfg->hci_phy_ctl_siddq;
+ writel(val, phy->pmu + REG_HCI_PHY_CTL);
+ }
+
if (data->cfg->type == sun8i_a83t_phy ||
data->cfg->type == sun50i_h6_phy) {
if (phy->index == 0) {
@@ -297,11 +303,6 @@ static int sun4i_usb_phy_init(struct phy *_phy)
writel(val, data->base + data->cfg->phyctl_offset);
}
} else {
- if (phy->pmu && data->cfg->enable_pmu_unk1) {
- val = readl(phy->pmu + REG_PMU_UNK1);
- writel(val & ~2, phy->pmu + REG_PMU_UNK1);
- }
-
/* Enable USB 45 Ohm resistor calibration */
if (phy->index == 0)
sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
@@ -863,7 +864,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
@@ -872,7 +872,6 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
.disc_thresh = 2,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
@@ -881,7 +880,6 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
@@ -890,7 +888,6 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
.disc_thresh = 2,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
@@ -899,7 +896,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
@@ -908,7 +904,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
@@ -925,7 +920,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
+ .hci_phy_ctl_siddq = BIT(1),
.phy0_dual_route = true,
};
@@ -935,7 +930,7 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
+ .hci_phy_ctl_siddq = BIT(1),
.phy0_dual_route = true,
};
@@ -945,7 +940,7 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1
[PATCH v5 18/20] arm64: dts: allwinner: Add Allwinner H616 .dtsi file
This (relatively) new SoC is similar to the H6, but drops the (broken)
PCIe support and the USB 3.0 controller. It also gets the management
controller removed, which in turn removes *some*, but not all of the
devices formerly dedicated to the ARISC (CPUS).
There does not seem to be an extra interrupt controller anymore, also
it lacks the corresponding NMI pin, so no interrupts for the PMIC.
Signed-off-by: Andre Przywara
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 573 ++
1 file changed, 573 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
new file mode 100644
index ..c277b53f94ea
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -0,0 +1,573 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Arm Ltd.
+// based on the H6 dtsi, which is:
+// Copyright (C) 2017 Icenowy Zheng
+
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 512KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@4000 {
+ reg = <0x0 0x4000 0x0 0x8>;
+ no-map;
+ };
+ };
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "osc24M";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = ,
+,
+,
+;
+ interrupt-affinity = <>, <>, <>, <>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ arm,no-tick-in-suspend;
+ interrupts = ,
+,
+,
+;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x4000>;
+
+ syscon: syscon@300 {
+ compatible = "allwinner,sun50i-h616-system-control";
+ reg = <0x0300 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_c: sram@28000 {
+ compatible = "mmio-sram";
+ reg = <0x00028000 0x3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00028000 0x3>;
+ };
+ };
+
+ ccu: clock@3001000 {
+ compatible = "allwinner,sun50i-h616-ccu";
+ reg = &
[PATCH v5 10/20] dt-bindings: i2c: mv64xxx: Add H616 compatible string
Add the obvious compatible name to the existing I2C binding, and pair it with the existing A31 fallback compatible string, as the devices are compatible. On the way use enums to group all compatible devices together. Signed-off-by: Andre Przywara Acked-by: Rob Herring Acked-by: Wolfram Sang --- .../bindings/i2c/marvell,mv64xxx-i2c.yaml | 21 +++ 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml index 5b5ae402f97a..eb72dd571def 100644 --- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml @@ -18,21 +18,14 @@ properties: - const: allwinner,sun4i-a10-i2c - const: allwinner,sun6i-a31-i2c - items: - - const: allwinner,sun8i-a23-i2c + - enum: + - allwinner,sun8i-a23-i2c + - allwinner,sun8i-a83t-i2c + - allwinner,sun50i-a64-i2c + - allwinner,sun50i-a100-i2c + - allwinner,sun50i-h6-i2c + - allwinner,sun50i-h616-i2c - const: allwinner,sun6i-a31-i2c - - items: - - const: allwinner,sun8i-a83t-i2c - - const: allwinner,sun6i-a31-i2c - - items: - - const: allwinner,sun50i-a64-i2c - - const: allwinner,sun6i-a31-i2c - - items: - - const: allwinner,sun50i-a100-i2c - - const: allwinner,sun6i-a31-i2c - - items: - - const: allwinner,sun50i-h6-i2c - - const: allwinner,sun6i-a31-i2c - - const: marvell,mv64xxx-i2c - const: marvell,mv78230-i2c - const: marvell,mv78230-a0-i2c -- 2.17.5
[PATCH v5 05/20] Input: axp20x-pek: Bail out if AXP has no interrupt line connected
On at least one board (Orangepi Zero2) the AXP305 PMIC does not have its interrupt line connected to the CPU (mostly because the H616 SoC does not feature an NMI pin anymore). After allowing the AXP driver to proceed without an "interrupts" property [1], the axp20x-pek driver crashes with a NULL pointer dereference (see below). Check for the regmap_irqc member to be not NULL before proceeding with probe. This gets normally filled by the call to regmap_add_irq_chip(), which we allow to skip now, when the DT node lacks an interrupt property. [3.843388] sunxi-rsb 7083000.rsb: RSB running at 300 Hz [3.849972] axp20x-rsb sunxi-rsb-745: AXP20x variant AXP806 found [3.857971] Unable to handle kernel NULL pointer dereference at virtual address 01b8 [3.866855] Mem abort info: [3.869691] ESR = 0x9604 [3.872749] EC = 0x25: DABT (current EL), IL = 32 bits [3.878092] SET = 0, FnV = 0 [3.881149] EA = 0, S1PTW = 0 [3.884309] Data abort info: [3.887210] ISV = 0, ISS = 0x0004 [3.891062] CM = 0, WnR = 0 [3.894049] [01b8] user address but active_mm is swapper [3.900590] Internal error: Oops: 9604 [#1] PREEMPT SMP [3.906166] Modules linked in: [3.909227] CPU: 2 PID: 34 Comm: kworker/2:1 Not tainted 5.11.0-rc1 [3.915925] Hardware name: OrangePi Zero2 (DT) [3.920367] Workqueue: events deferred_probe_work_func [3.925518] pstate: 4005 (nZcv daif -PAN -UAO -TCO BTYPE=--) [3.931522] pc : regmap_irq_get_virq+0x0/0x48 [3.935883] lr : axp20x_pek_probe+0x78/0x200 [3.940147] sp : 800012fdb450 [3.943459] x29: 800012fdb450 x28: 054af340 [3.948776] x27: 05534000 x26: 05534810 [3.954091] x25: 800012883028 x24: 0002 [3.959407] x23: 80001157eaf0 x22: 05534810 [3.964722] x21: 05534800 x20: 054b0580 [3.970037] x19: 000b x18: [3.975353] x17: 0001 x16: 0019 [3.980668] x15: 02ce4ea04ae6 x14: 014f [3.985983] x13: 0282 x12: 0030 [3.991298] x11: 0038 x10: 0101010101010101 [3.996613] x9 : x8 : 7f7f7f7f7f7f7f7f [4.001928] x7 : ff5141435e4a444f x6 : 0080 [4.007243] x5 : x4 : 8000 [4.012558] x3 : x2 : [4.017872] x1 : 000b x0 : [4.023188] Call trace: [4.025635] regmap_irq_get_virq+0x0/0x48 [4.029646] platform_probe+0x68/0xd8 [4.033312] really_probe+0xe4/0x3b0 [4.036889] driver_probe_device+0x58/0xb8 [4.040986] __device_attach_driver+0x84/0xc8 [4.045342] bus_for_each_drv+0x78/0xc8 [4.049178] __device_attach+0xf0/0x150 [4.053013] device_initial_probe+0x14/0x20 [4.057196] bus_probe_device+0x9c/0xa8 [4.061032] device_add+0x36c/0x7b8 [4.064525] platform_device_add+0x100/0x238 [4.068796] mfd_add_devices+0x494/0x718 [4.072721] axp20x_device_probe+0x70/0x158 [4.076904] axp20x_rsb_probe+0x94/0xd0 [4.080741] sunxi_rsb_device_probe+0x6c/0x88 [4.085102] really_probe+0xe4/0x3b0 [4.088679] driver_probe_device+0x58/0xb8 [4.092776] __device_attach_driver+0x84/0xc8 [4.097132] bus_for_each_drv+0x78/0xc8 [4.100967] __device_attach+0xf0/0x150 [4.104803] device_initial_probe+0x14/0x20 [4.108986] bus_probe_device+0x9c/0xa8 [4.112821] device_add+0x36c/0x7b8 [4.116313] device_register+0x20/0x30 [4.120065] sunxi_rsb_probe+0x4e4/0x608 [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2021-January/633392.html Signed-off-by: Andre Przywara --- drivers/input/misc/axp20x-pek.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/input/misc/axp20x-pek.c b/drivers/input/misc/axp20x-pek.c index 9c6386b2af33..abe52ef194ee 100644 --- a/drivers/input/misc/axp20x-pek.c +++ b/drivers/input/misc/axp20x-pek.c @@ -309,6 +309,10 @@ static int axp20x_pek_probe(struct platform_device *pdev) axp20x_pek->axp20x = dev_get_drvdata(pdev->dev.parent); + /* In case there is no interrupt line from the AXP towards the CPU. */ + if (!axp20x_pek->axp20x->regmap_irqc) + return -ENODEV; + axp20x_pek->irq_dbr = platform_get_irq_byname(pdev, "PEK_DBR"); if (axp20x_pek->irq_dbr < 0) return axp20x_pek->irq_dbr; -- 2.17.5
[PATCH v5 07/20] dt-bindings: sram: sunxi-sram: Add H616 compatible string
The H616 adds a second EMAC clock register. We don't know about the exact SRAM properties yet, so this gets omitted for now. Signed-off-by: Andre Przywara Acked-by: Rob Herring --- .../bindings/sram/allwinner,sun4i-a10-system-control.yaml| 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml index b66a07e21d1e..1c426c211e36 100644 --- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -49,6 +49,7 @@ properties: - items: - const: allwinner,suniv-f1c100s-system-control - const: allwinner,sun4i-a10-system-control + - const: allwinner,sun50i-h616-system-control reg: maxItems: 1 -- 2.17.5
[PATCH v5 06/20] mfd: axp20x: Allow AXP chips without interrupt lines
Currently the AXP chip requires to have its IRQ line connected to some
interrupt controller, and will fail probing when this is not the case.
On a new Allwinner SoC (H616) there is no NMI pin anymore, and at
least one board does not connect the AXP's IRQ pin to anything else,
so the interrupt functionality of the AXP chip is simply not available.
Check whether the interrupt line number returned by the platform code is
valid, before trying to register the irqchip. If not, we skip this
registration, to avoid the driver to bail out completely.
Signed-off-by: Andre Przywara
---
drivers/mfd/axp20x.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 3eae04e24ac8..00c163a1e20d 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -959,12 +959,17 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
}
- ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
- IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
- -1, axp20x->regmap_irq_chip, >regmap_irqc);
- if (ret) {
- dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret);
- return ret;
+ /* Only if there is an interrupt line connected towards the CPU. */
+ if (axp20x->irq > 0) {
+ ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
+ IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
+ -1, axp20x->regmap_irq_chip,
+ >regmap_irqc);
+ if (ret) {
+ dev_err(axp20x->dev, "failed to add irq chip: %d\n",
+ ret);
+ return ret;
+ }
}
ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
--
2.17.5
[PATCH v5 03/20] clk: sunxi-ng: Add support for the Allwinner H616 CCU
While the clocks are fairly similar to the H6, many differ in tiny
details, so a separate clock driver seems indicated.
Derived from the H6 clock driver, and adjusted according to the manual.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
drivers/clk/sunxi-ng/Kconfig|5 +
drivers/clk/sunxi-ng/Makefile |1 +
drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 1150 +++
drivers/clk/sunxi-ng/ccu-sun50i-h616.h | 56 +
include/dt-bindings/clock/sun50i-h616-ccu.h | 115 ++
include/dt-bindings/reset/sun50i-h616-ccu.h | 70 ++
6 files changed, 1397 insertions(+)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.h
create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index feeb8d2074ee..cd46d8853876 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -32,6 +32,11 @@ config SUN50I_H6_CCU
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+config SUN50I_H616_CCU
+ bool "Support for the Allwinner H616 CCU"
+ default ARM64 && ARCH_SUNXI
+ depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+
config SUN50I_H6_R_CCU
bool "Support for the Allwinner H6 and H616 PRCM CCU"
default ARM64 && ARCH_SUNXI
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 3eb5cff40eac..96c324306d97 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
obj-$(CONFIG_SUN50I_A100_CCU) += ccu-sun50i-a100.o
obj-$(CONFIG_SUN50I_A100_R_CCU)+= ccu-sun50i-a100-r.o
obj-$(CONFIG_SUN50I_H6_CCU)+= ccu-sun50i-h6.o
+obj-$(CONFIG_SUN50I_H616_CCU) += ccu-sun50i-h616.o
obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
obj-$(CONFIG_SUN4I_A10_CCU)+= ccu-sun4i-a10.o
obj-$(CONFIG_SUN5I_CCU)+= ccu-sun5i.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
new file mode 100644
index ..225307305880
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
@@ -0,0 +1,1150 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Arm Ltd.
+ * Based on the H6 CCU driver, which is:
+ * Copyright (c) 2017 Icenowy Zheng
+ */
+
+#include
+#include
+#include
+#include
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+
+#include "ccu-sun50i-h616.h"
+
+/*
+ * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
+ * P should only be used for output frequencies lower than 288 MHz.
+ *
+ * For now we can just model it as a multiplier clock, and force P to /1.
+ *
+ * The M factor is present in the register's description, but not in the
+ * frequency formula, and it's documented as "M is only used for backdoor
+ * testing", so it's not modelled and then force to 0.
+ */
+#define SUN50I_H616_PLL_CPUX_REG 0x000
+static struct ccu_mult pll_cpux_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .common = {
+ .reg= 0x000,
+ .hw.init= CLK_HW_INIT("pll-cpux", "osc24M",
+ _mult_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
+
+/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
+#define SUN50I_H616_PLL_DDR0_REG 0x010
+static struct ccu_nkmp pll_ddr0_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
+ .common = {
+ .reg= 0x010,
+ .hw.init= CLK_HW_INIT("pll-ddr0", "osc24M",
+ _nkmp_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
+
+#define SUN50I_H616_PLL_DDR1_REG 0x018
+static struct ccu_nkmp pll_ddr1_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .p = _SUNXI_CCU_DIV(
[PATCH v5 04/20] dt-bindings: mfd: axp20x: Add AXP305 compatible (plus optional IRQ)
The AXP305 PMIC used in AXP805 seems to be fully compatible to the AXP805 PMIC, so add the proper chain of compatible strings. Also at least on one board (Orangepi Zero2) there is no interrupt line connected to the CPU, so make the "interrupts" property optional. Signed-off-by: Andre Przywara --- Documentation/devicetree/bindings/mfd/axp20x.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt b/Documentation/devicetree/bindings/mfd/axp20x.txt index 4991a6415796..4fd748101e3c 100644 --- a/Documentation/devicetree/bindings/mfd/axp20x.txt +++ b/Documentation/devicetree/bindings/mfd/axp20x.txt @@ -26,10 +26,10 @@ Required properties: * "x-powers,axp803" * "x-powers,axp806" * "x-powers,axp805", "x-powers,axp806" +* "x-powers,axp803", "x-powers,axp805", "x-powers,axp806" * "x-powers,axp809" * "x-powers,axp813" - reg: The I2C slave address or RSB hardware address for the AXP chip -- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin - interrupt-controller: The PMIC has its own internal IRQs - #interrupt-cells: Should be set to 1 @@ -43,6 +43,7 @@ more information: AXP20x/LDO3: software-based implementation Optional properties: +- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin - x-powers,dcdc-freq: defines the work frequency of DC-DC in KHz AXP152/20X: range: 750-1875, Default: 1.5 MHz AXP22X/8XX: range: 1800-4050, Default: 3 MHz -- 2.17.5
[PATCH v5 02/20] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU
The clocks itself are identical to the H6 R-CCU, it's just that the H616
has not all of them implemented (or connected).
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
drivers/clk/sunxi-ng/Kconfig | 2 +-
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 48 ++
2 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index ce5f5847d5d3..feeb8d2074ee 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -33,7 +33,7 @@ config SUN50I_H6_CCU
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
config SUN50I_H6_R_CCU
- bool "Support for the Allwinner H6 PRCM CCU"
+ bool "Support for the Allwinner H6 and H616 PRCM CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index 56e351b513f3..f8909a7ed553 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -139,6 +139,16 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
_clk.common,
};
+static struct ccu_common *sun50i_h616_r_ccu_clks[] = {
+ _apb1_clk.common,
+ _apb2_clk.common,
+ _apb1_twd_clk.common,
+ _apb2_i2c_clk.common,
+ _apb2_rsb_clk.common,
+ _apb1_ir_clk.common,
+ _clk.common,
+};
+
static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
.hws= {
[CLK_AR100] = _clk.common.hw,
@@ -159,6 +169,20 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
.num= CLK_NUMBER,
};
+static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
+ .hws= {
+ [CLK_R_AHB] = _ahb_clk.hw,
+ [CLK_R_APB1]= _apb1_clk.common.hw,
+ [CLK_R_APB2]= _apb2_clk.common.hw,
+ [CLK_R_APB1_TWD]= _apb1_twd_clk.common.hw,
+ [CLK_R_APB2_I2C]= _apb2_i2c_clk.common.hw,
+ [CLK_R_APB2_RSB]= _apb2_rsb_clk.common.hw,
+ [CLK_R_APB1_IR] = _apb1_ir_clk.common.hw,
+ [CLK_IR]= _clk.common.hw,
+ },
+ .num= CLK_NUMBER,
+};
+
static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
[RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
[RST_R_APB1_TWD]= { 0x12c, BIT(16) },
@@ -170,6 +194,13 @@ static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
[RST_R_APB1_W1] = { 0x1ec, BIT(16) },
};
+static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
+ [RST_R_APB1_TWD]= { 0x12c, BIT(16) },
+ [RST_R_APB2_I2C]= { 0x19c, BIT(16) },
+ [RST_R_APB2_RSB]= { 0x1bc, BIT(16) },
+ [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
+};
+
static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
.ccu_clks = sun50i_h6_r_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
@@ -180,6 +211,16 @@ static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
.num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets),
};
+static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
+ .ccu_clks = sun50i_h616_r_ccu_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks),
+
+ .hw_clks= _h616_r_hw_clks,
+
+ .resets = sun50i_h616_r_ccu_resets,
+ .num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets),
+};
+
static void __init sunxi_r_ccu_init(struct device_node *node,
const struct sunxi_ccu_desc *desc)
{
@@ -200,3 +241,10 @@ static void __init sun50i_h6_r_ccu_setup(struct
device_node *node)
}
CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu",
sun50i_h6_r_ccu_setup);
+
+static void __init sun50i_h616_r_ccu_setup(struct device_node *node)
+{
+ sunxi_r_ccu_init(node, _h616_r_ccu_desc);
+}
+CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu",
+ sun50i_h616_r_ccu_setup);
--
2.17.5
[PATCH v5 00/20] arm64: sunxi: Initial Allwinner H616 SoC support
source - .dts: fix LED naming and swap pins - .dts: use 5V supply parent for USB supply - .dts: drop dummy IRQ for AXP - .dts: enable 3V3 header pin power rail - .dts: add SPI flash node - .dts: make USB-C port peripheral only - add IRQ-less AXP support - add two patches to support more than one EMAC clock - add patch to rework and extend USB PHY support - add DT binding documentation patches Andre Przywara (20): dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616 clk: sunxi-ng: Add support for the Allwinner H616 R-CCU clk: sunxi-ng: Add support for the Allwinner H616 CCU dt-bindings: mfd: axp20x: Add AXP305 compatible (plus optional IRQ) Input: axp20x-pek: Bail out if AXP has no interrupt line connected mfd: axp20x: Allow AXP chips without interrupt lines dt-bindings: sram: sunxi-sram: Add H616 compatible string soc: sunxi: sram: Add support for more than one EMAC clock dt-bindings: watchdog: sun4i: Add H616 compatible string dt-bindings: i2c: mv64xxx: Add H616 compatible string dt-bindings: media: IR: Add H616 IR compatible string dt-bindings: rtc: sun6i: Add H616 compatible string dt-bindings: spi: sunxi: Add H616 compatible string dt-bindings: bus: rsb: Add H616 compatible string dt-bindings: net: sun8i-emac: Add H616 compatible string net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling arm64: dts: allwinner: Add Allwinner H616 .dtsi file dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding arm64: dts: allwinner: Add OrangePi Zero 2 .dts .../devicetree/bindings/arm/sunxi.yaml|5 + .../bindings/bus/allwinner,sun8i-a23-rsb.yaml |4 +- .../clock/allwinner,sun4i-a10-ccu.yaml|4 + .../bindings/i2c/marvell,mv64xxx-i2c.yaml | 21 +- .../media/allwinner,sun4i-a10-ir.yaml | 16 +- .../devicetree/bindings/mfd/axp20x.txt|3 +- .../net/allwinner,sun8i-a83t-emac.yaml|4 +- .../bindings/rtc/allwinner,sun6i-a31-rtc.yaml |3 + .../bindings/spi/allwinner,sun6i-a31-spi.yaml |1 + .../allwinner,sun4i-a10-system-control.yaml |1 + .../watchdog/allwinner,sun4i-a10-wdt.yaml | 12 +- arch/arm64/boot/dts/allwinner/Makefile|1 + .../allwinner/sun50i-h616-orangepi-zero2.dts | 203 +++ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 573 drivers/clk/sunxi-ng/Kconfig |7 +- drivers/clk/sunxi-ng/Makefile |1 + drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c| 48 + drivers/clk/sunxi-ng/ccu-sun50i-h616.c| 1150 + drivers/clk/sunxi-ng/ccu-sun50i-h616.h| 56 + drivers/input/misc/axp20x-pek.c |4 + drivers/mfd/axp20x.c | 17 +- .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 12 +- drivers/phy/allwinner/phy-sun4i-usb.c | 29 +- drivers/soc/sunxi/sunxi_sram.c| 31 +- include/dt-bindings/clock/sun50i-h616-ccu.h | 115 ++ include/dt-bindings/reset/sun50i-h616-ccu.h | 70 + 26 files changed, 2323 insertions(+), 68 deletions(-) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.h create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h -- 2.17.5
[PATCH v5 01/20] dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616
Signed-off-by: Andre Przywara Acked-by: Rob Herring Acked-by: Maxime Ripard --- .../devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml| 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml index 3b45344ed758..a27025cd3909 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml @@ -41,6 +41,8 @@ properties: - allwinner,sun50i-h5-ccu - allwinner,sun50i-h6-ccu - allwinner,sun50i-h6-r-ccu + - allwinner,sun50i-h616-ccu + - allwinner,sun50i-h616-r-ccu - allwinner,suniv-f1c100s-ccu - nextthing,gr8-ccu @@ -82,6 +84,7 @@ if: - allwinner,sun50i-a64-r-ccu - allwinner,sun50i-a100-r-ccu - allwinner,sun50i-h6-r-ccu +- allwinner,sun50i-h616-r-ccu then: properties: @@ -100,6 +103,7 @@ else: enum: - allwinner,sun50i-a100-ccu - allwinner,sun50i-h6-ccu + - allwinner,sun50i-h616-ccu then: properties: -- 2.17.5
Re: [PATCH v2 2/4] arm64: dts: ti: k3: squelch warnings regarding no #address-cells for interrupt-controller
On Mon, 25 Jan 2021 18:01:08 -0600 Rob Herring wrote: Hi, > On Thu, Nov 19, 2020 at 01:17:36PM +0200, Grygorii Strashko wrote: > > > > > > On 18/11/2020 17:12, Nishanth Menon wrote: > > > On 13:38-20201118, Grygorii Strashko wrote: > > > > Hi Rob, > > > > > > > > On 17/11/2020 18:19, Sekhar Nori wrote: > > > > > With dtc 1.6.0, building TI device-tree files with W=2 results in > > > > > warnings > > > > > like below for all interrupt controllers. > > > > > > > > > > /bus@10/bus@3000/interrupt-controller1: Missing > > > > > #address-cells in interrupt provider > > > > > > > > > > Fix these by adding #address-cells = <0>; for all interrupt > > > > > controllers in > > > > > TI device-tree files. Any other #address-cells value is really only > > > > > needed > > > > > if interrupt-map property is being used (which is not the case for > > > > > existing > > > > > TI device-tree files) > > > > > > > > > > Signed-off-by: Sekhar Nori > > > > > --- > > > > >arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 + > > > > >arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi| 2 ++ > > > > >arch/arm64/boot/dts/ti/k3-am654-base-board.dts| 1 + > > > > >arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 3 +++ > > > > >arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 1 + > > > > >arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 1 + > > > > >arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 11 > > > > > +++ > > > > >arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 3 +++ > > > > >8 files changed, 27 insertions(+) > > > > > > > > > > diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > > > > > b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > > > > > index aa8725db0187..55aaa1404d7d 100644 > > > > > --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > > > > > +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > > > > > @@ -440,6 +440,7 @@ > > > > > interrupt-controller; > > > > > interrupt-parent = <>; > > > > > #interrupt-cells = <1>; > > > > > + #address-cells = <0>; > > > > Does it really required or mandatory to have #address-cells = <0>; > > > > defined for interrupt-controller DT nodes which > > > > do not have child nodes and no "interrupt-map"? > > > > > > Just to help clarify (I could be mistaken as well): is'nt the > > > interrupt map for user interrupt map nodes that refer to this > > > interrupt controller node to state they dont need a parent address > > > specifier - so are we claiming none of the users will have an > > > interrupt-map (now and never in the future as well) - we we might want > > > to explain why we think that is the case, and if we are expecting dtc > > > to deduce that (if so how?)? > > > > > > > The main reason I commented - is hope to get some clarification from DT > > maintainers. > > 90% of interrupt-controller nodes do not have #address-cells and I never > > seen in in GPIO nodes > > (most often is present in PCI and GIC nodes). > > and nobody seems fixing it. So, if we are going to move this direction it's > > reasonable to get clarification to be sure. > > > > And there is no "never" here - #address-cells always can be added if really > > required. > > Once required, how does one figure that out? It's not obvious and > requires booting. So we need something at build time. I'm okay with > loosening the check as long as it warns when a interrupt parent phandle > in an interrupt-map is missing '#address-cells'. So I think the rationale for requiring #address-cells is that the usage of an interrupt in an interrupt-map can be totally disconnected from the actual interrupt controller node. Typically the controller is in the .dtsi, but an interrupt map could be anywhere, down in some board .dts, or even some "common peripherals" intermediate .dts. Possibly even in an overlay (I2C IRQ lines?). So while not having this property works today, for your board, it might surprisingly break for someone else. And those things are hard to find (unless you know what you are looking for). Been there, done that with the VExpress DTs, and that was the reason I pushed for more tests. On top of that is the standard's default value of "2" for #address-cells, which Linux observes in this case. That leads to somewhat surprising results when interpreting interrupt-maps without an explicit #address-cells (cost me a few hours to figure out back then!) So given the already somewhat complicated nature of interrupt-maps I think it's comparably little to ask for explicit #address-cells properties, even though you might not immediately benefit from it. > Now that I look back at the dtc change, I'm now confused why this > check got applied. Both David and I wanted changes in regards to > #address-cells. Either a separate check or part of interrupt-map checks. > And the interrupt-map check never got applied. Andre?
[PATCH v4 19/21] arm64: dts: allwinner: Add Allwinner H616 .dtsi file
This (relatively) new SoC is similar to the H6, but drops the (broken)
PCIe support and the USB 3.0 controller. It also gets the management
controller removed, which in turn removes *some*, but not all of the
devices formerly dedicated to the ARISC (CPUS).
There does not seem to be an extra interrupt controller anymore, also
it lacks the corresponding NMI pin, so no interrupts for the PMIC.
Signed-off-by: Andre Przywara
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 750 ++
1 file changed, 750 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
new file mode 100644
index ..f74713e54a66
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -0,0 +1,750 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Arm Ltd.
+// based on the H6 dtsi, which is:
+// Copyright (C) 2017 Icenowy Zheng
+
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 512KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@4000 {
+ reg = <0x0 0x4000 0x0 0x8>;
+ no-map;
+ };
+ };
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "osc24M";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = ,
+,
+,
+;
+ interrupt-affinity = <>, <>, <>, <>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ arm,no-tick-in-suspend;
+ interrupts = ,
+,
+,
+;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x4000>;
+
+ syscon: syscon@300 {
+ compatible = "allwinner,sun50i-h616-system-control";
+ reg = <0x0300 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_c: sram@28000 {
+ compatible = "mmio-sram";
+ reg = <0x00028000 0x3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00028000 0x3>;
+ };
+ };
+
+ ccu: clock@3001000 {
+ compatible = "allwinner,sun50i-h616-ccu";
+ reg = &
[PATCH v4 18/21] phy: sun4i-usb: Add support for the H616 USB PHY
The USB PHY used in the Allwinner H616 SoC inherits some traits from its
various predecessors: it has four full PHYs like the H3, needs some
extra bits to be set like the H6, and clears a different bit in the
PMU_UNK1 register like the A100.
Name all those properties in a new config struct and assign a new
compatible name to it.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 539209fe3468..e71d6b8ccf16 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -964,6 +964,16 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
.missing_phys = BIT(1) | BIT(2),
};
+static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
+ .num_phys = 4,
+ .type = sun50i_h6_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A33,
+ .dedicated_clocks = true,
+ .phy0_dual_route = true,
+ .hci_phy_ctl_siddq = BIT(3),
+};
+
static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = _a10_cfg },
{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = _a13_cfg },
@@ -978,6 +988,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] =
{
{ .compatible = "allwinner,sun50i-a64-usb-phy",
.data = _a64_cfg},
{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = _h6_cfg },
+ { .compatible = "allwinner,sun50i-h616-usb-phy", .data =
_h616_cfg },
{ },
};
MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
--
2.17.5
Re: [PATCH v4 12/21] dt-bindings: rtc: sun6i: Add H616 compatible string
On Mon, 25 Jan 2021 23:51:01 +0100 Alexandre Belloni wrote: Hi Alexandre, > On 25/01/2021 15:18:02+0000, Andre Przywara wrote: > > Add the obvious compatible name to the existing RTC binding, and pair > > it with the existing H6 fallback compatible string, as the devices are > > compatible. > > > > Signed-off-by: Andre Przywara > > Acked-by: Rob Herring > > --- > > .../devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 3 +++ > > 1 file changed, 3 insertions(+) > > > > How do you expect that patch to be merged? I was thinking it would go > through Rob's tree. Yes, and that's why I originally combined all those trivial patches into one, but broonie asked for a split up. So I guess there is not much to do there, unless you want to object ;-) Cheers, Andre > > > diff --git > > a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml > > b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml > > index b1b0ee769b71..4193e5813344 100644 > > --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml > > +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml > > @@ -26,6 +26,9 @@ properties: > >- const: allwinner,sun50i-a64-rtc > >- const: allwinner,sun8i-h3-rtc > >- const: allwinner,sun50i-h6-rtc > > + - items: > > + - const: allwinner,sun50i-h616-rtc > > + - const: allwinner,sun50i-h6-rtc > > > >reg: > > maxItems: 1 > > -- > > 2.17.5 > > >
[PATCH v4 00/21] arm64: sunxi: Initial Allwinner H616 SoC support
able 3V3 header pin power rail - .dts: add SPI flash node - .dts: make USB-C port peripheral only - add IRQ-less AXP support - add two patches to support more than one EMAC clock - add patch to rework and extend USB PHY support - add DT binding documentation patches Andre Przywara (21): dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616 clk: sunxi-ng: Add support for the Allwinner H616 R-CCU clk: sunxi-ng: Add support for the Allwinner H616 CCU dt-bindings: mfd: axp20x: Add AXP305 compatible (plus optional IRQ) Input: axp20x-pek: Bail out if AXP has no interrupt line connected mfd: axp20x: Allow AXP chips without interrupt lines dt-bindings: sram: sunxi-sram: Add H616 compatible string soc: sunxi: sram: Add support for more than one EMAC clock dt-bindings: watchdog: sun4i: Add H616 compatible string dt-bindings: i2c: mv64xxx: Add H616 compatible string dt-bindings: media: IR: Add H616 IR compatible string dt-bindings: rtc: sun6i: Add H616 compatible string dt-bindings: spi: sunxi: Add H616 compatible string net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling dt-bindings: usb: Add H616 compatible string dt-bindings: usb: sunxi-musb: Add H616 compatible string phy: sun4i-usb: Add support for the H616 USB PHY arm64: dts: allwinner: Add Allwinner H616 .dtsi file dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding arm64: dts: allwinner: Add OrangePi Zero 2 .dts .../devicetree/bindings/arm/sunxi.yaml|5 + .../clock/allwinner,sun4i-a10-ccu.yaml|2 + .../bindings/i2c/marvell,mv64xxx-i2c.yaml | 21 +- .../media/allwinner,sun4i-a10-ir.yaml | 16 +- .../devicetree/bindings/mfd/axp20x.txt|3 +- .../phy/allwinner,sun8i-h3-usb-phy.yaml |4 +- .../bindings/rtc/allwinner,sun6i-a31-rtc.yaml |3 + .../bindings/spi/allwinner,sun6i-a31-spi.yaml |1 + .../allwinner,sun4i-a10-system-control.yaml |1 + .../usb/allwinner,sun4i-a10-musb.yaml |3 + .../watchdog/allwinner,sun4i-a10-wdt.yaml | 12 +- arch/arm64/boot/dts/allwinner/Makefile|1 + .../allwinner/sun50i-h616-orangepi-zero2.dts | 242 .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 750 +++ drivers/clk/sunxi-ng/Kconfig |7 +- drivers/clk/sunxi-ng/Makefile |1 + drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c| 48 + drivers/clk/sunxi-ng/ccu-sun50i-h616.c| 1150 + drivers/clk/sunxi-ng/ccu-sun50i-h616.h| 56 + drivers/input/misc/axp20x-pek.c |4 + drivers/mfd/axp20x.c | 17 +- .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 12 +- drivers/phy/allwinner/phy-sun4i-usb.c | 40 +- drivers/soc/sunxi/sunxi_sram.c| 31 +- include/dt-bindings/clock/sun50i-h616-ccu.h | 115 ++ include/dt-bindings/reset/sun50i-h616-ccu.h | 70 + 26 files changed, 2548 insertions(+), 67 deletions(-) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.h create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h -- 2.17.5
[PATCH v4 14/21] net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register
The Allwinner H616 SoC has two EMAC controllers, with the second one
being tied to the internal PHY, but also using a separate EMAC clock
register.
To tell the driver about which clock register to use, we add a parameter
to our syscon phandle. The driver will use this value as an index into
the regmap, so that we can address more than the first register, if
needed.
Signed-off-by: Andre Przywara
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 58e0511badba..c7951790ed98 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -1124,11 +1124,13 @@ static int sun8i_dwmac_probe(struct platform_device
*pdev)
struct stmmac_resources stmmac_res;
struct sunxi_priv_data *gmac;
struct device *dev = >dev;
+ struct reg_field syscon_field;
phy_interface_t interface;
int ret;
struct stmmac_priv *priv;
struct net_device *ndev;
struct regmap *regmap;
+ u32 syscon_idx = 0;
ret = stmmac_get_platform_resources(pdev, _res);
if (ret)
@@ -1190,8 +1192,12 @@ static int sun8i_dwmac_probe(struct platform_device
*pdev)
return ret;
}
- gmac->regmap_field = devm_regmap_field_alloc(dev, regmap,
-
*gmac->variant->syscon_field);
+ syscon_field = *gmac->variant->syscon_field;
+ ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1,
+_idx);
+ if (!ret)
+ syscon_field.reg += syscon_idx * sizeof(u32);
+ gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, syscon_field);
if (IS_ERR(gmac->regmap_field)) {
ret = PTR_ERR(gmac->regmap_field);
dev_err(dev, "Unable to map syscon register: %d\n", ret);
@@ -1263,6 +1269,8 @@ static const struct of_device_id sun8i_dwmac_match[] = {
.data = _variant_a64 },
{ .compatible = "allwinner,sun50i-h6-emac",
.data = _variant_h6 },
+ { .compatible = "allwinner,sun50i-h616-emac",
+ .data = _variant_h6 },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
--
2.17.5
[PATCH v4 11/21] dt-bindings: media: IR: Add H616 IR compatible string
Add the obvious compatible name to the existing IR binding, and pair it with the existing A31 fallback compatible string, as the devices are compatible. On the way use enums to group all compatible devices together. Signed-off-by: Andre Przywara Acked-by: Rob Herring --- .../bindings/media/allwinner,sun4i-a10-ir.yaml | 16 ++-- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml index 5fa19d4aeaf3..6d8395d6bca0 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml @@ -20,16 +20,12 @@ properties: - const: allwinner,sun5i-a13-ir - const: allwinner,sun6i-a31-ir - items: - - const: allwinner,sun8i-a83t-ir - - const: allwinner,sun6i-a31-ir - - items: - - const: allwinner,sun8i-r40-ir - - const: allwinner,sun6i-a31-ir - - items: - - const: allwinner,sun50i-a64-ir - - const: allwinner,sun6i-a31-ir - - items: - - const: allwinner,sun50i-h6-ir + - enum: + - allwinner,sun8i-a83t-ir + - allwinner,sun8i-r40-ir + - allwinner,sun50i-a64-ir + - allwinner,sun50i-h6-ir + - allwinner,sun50i-h616-ir - const: allwinner,sun6i-a31-ir reg: -- 2.17.5
[PATCH v4 09/21] dt-bindings: watchdog: sun4i: Add H616 compatible string
Use enums to group all compatible devices together on the way. Signed-off-by: Andre Przywara Acked-by: Rob Herring Acked-by: Maxime Ripard Reviewed-by: Guenter Roeck --- .../bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 5ac607de8be4..9aa3c313c49f 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -19,13 +19,11 @@ properties: - const: allwinner,sun4i-a10-wdt - const: allwinner,sun6i-a31-wdt - items: - - const: allwinner,sun50i-a64-wdt - - const: allwinner,sun6i-a31-wdt - - items: - - const: allwinner,sun50i-a100-wdt - - const: allwinner,sun6i-a31-wdt - - items: - - const: allwinner,sun50i-h6-wdt + - enum: + - allwinner,sun50i-a64-wdt + - allwinner,sun50i-a100-wdt + - allwinner,sun50i-h6-wdt + - allwinner,sun50i-h616-wdt - const: allwinner,sun6i-a31-wdt - items: - const: allwinner,suniv-f1c100s-wdt -- 2.17.5
[PATCH v4 12/21] dt-bindings: rtc: sun6i: Add H616 compatible string
Add the obvious compatible name to the existing RTC binding, and pair it with the existing H6 fallback compatible string, as the devices are compatible. Signed-off-by: Andre Przywara Acked-by: Rob Herring --- .../devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml index b1b0ee769b71..4193e5813344 100644 --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -26,6 +26,9 @@ properties: - const: allwinner,sun50i-a64-rtc - const: allwinner,sun8i-h3-rtc - const: allwinner,sun50i-h6-rtc + - items: + - const: allwinner,sun50i-h616-rtc + - const: allwinner,sun50i-h6-rtc reg: maxItems: 1 -- 2.17.5
[PATCH v4 20/21] dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding
Signed-off-by: Andre Przywara Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 08607c7ec1bf..aeb8771b14c4 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -932,4 +932,9 @@ properties: - const: xunlong,orangepi-zero-plus2-h3 - const: allwinner,sun8i-h3 + - description: Xunlong OrangePi Zero 2 +items: + - const: xunlong,orangepi-zero2 + - const: allwinner,sun50i-h616 + additionalProperties: true -- 2.17.5
[PATCH v4 16/21] dt-bindings: usb: Add H616 compatible string
The H616 has four PHYs as the H3, along with their respective clock gates and resets, so the property description is identical. However the PHYs itself need some special bits, so we need a new compatible string for it. Signed-off-by: Andre Przywara --- .../devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml index 60c344585276..b76a1803dc5f 100644 --- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml @@ -15,7 +15,9 @@ properties: const: 1 compatible: -const: allwinner,sun8i-h3-usb-phy +enum: + - allwinner,sun8i-h3-usb-phy + - allwinner,sun50i-h616-usb-phy reg: items: -- 2.17.5
[PATCH v4 21/21] arm64: dts: allwinner: Add OrangePi Zero 2 .dts
The OrangePi Zero 2 is a development board with the new H616 SoC.
It features the usual connectors used on those small boards, and comes
with the AXP305, which seems to be compatible with the AXP805.
For more details see: http://linux-sunxi.org/Xunlong_Orange_Pi_Zero2
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/allwinner/Makefile| 1 +
.../allwinner/sun50i-h616-orangepi-zero2.dts | 242 ++
2 files changed, 243 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile
b/arch/arm64/boot/dts/allwinner/Makefile
index 41ce680e5f8d..9ba4b5d92657 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -36,3 +36,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
new file mode 100644
index ..e6de49f89e39
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
@@ -0,0 +1,242 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2020 Arm Ltd.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+
+#include
+#include
+#include
+
+/ {
+ model = "OrangePi Zero2";
+ compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
+
+ aliases {
+ ethernet0 =
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_POWER;
+ color = ;
+ gpios = < 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
+ default-state = "on";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = ;
+ gpios = < 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
+ };
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the USB-C socket */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ };
+
+ reg_usb1_vbus: usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_vcc5v>;
+ enable-active-high;
+ gpio = < 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+ status = "okay";
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+/* USB 2 & 3 are on headers only. */
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <_rgmii_phy>;
+ phy-supply = <_dcdce>;
+ allwinner,rx-delay-ps = <3100>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
+ {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+ {
+ vmmc-supply = <_dcdce>;
+ cd-gpios = < 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+_rsb {
+ status = "okay";
+
+ axp305: pmic@745 {
+ compatible = "x-powers,axp305", "x-powers,axp805",
+"x-powers,axp806";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x745>;
+
+ x-powers,self-working-mode;
+ vina-supply = <_vcc5v>;
+ vinb-supply = <_vcc5v>;
+ vinc-supply = <_vcc5v>;
+ vind-supply = <_vcc5v>;
+ vine-supply = <_vcc5v>;
+ aldoin-supply = <_vcc5v>;
+ bldoin-supply = <_vcc5v>;
+ cldoin-supply = <_vcc5v>;
+
+ regulators {
+ r
[PATCH v4 10/21] dt-bindings: i2c: mv64xxx: Add H616 compatible string
Add the obvious compatible name to the existing I2C binding, and pair it with the existing A31 fallback compatible string, as the devices are compatible. On the way use enums to group all compatible devices together. Signed-off-by: Andre Przywara Acked-by: Rob Herring Acked-by: Wolfram Sang --- .../bindings/i2c/marvell,mv64xxx-i2c.yaml | 21 +++ 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml index 5b5ae402f97a..eb72dd571def 100644 --- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml @@ -18,21 +18,14 @@ properties: - const: allwinner,sun4i-a10-i2c - const: allwinner,sun6i-a31-i2c - items: - - const: allwinner,sun8i-a23-i2c + - enum: + - allwinner,sun8i-a23-i2c + - allwinner,sun8i-a83t-i2c + - allwinner,sun50i-a64-i2c + - allwinner,sun50i-a100-i2c + - allwinner,sun50i-h6-i2c + - allwinner,sun50i-h616-i2c - const: allwinner,sun6i-a31-i2c - - items: - - const: allwinner,sun8i-a83t-i2c - - const: allwinner,sun6i-a31-i2c - - items: - - const: allwinner,sun50i-a64-i2c - - const: allwinner,sun6i-a31-i2c - - items: - - const: allwinner,sun50i-a100-i2c - - const: allwinner,sun6i-a31-i2c - - items: - - const: allwinner,sun50i-h6-i2c - - const: allwinner,sun6i-a31-i2c - - const: marvell,mv64xxx-i2c - const: marvell,mv78230-i2c - const: marvell,mv78230-a0-i2c -- 2.17.5
[PATCH v4 01/21] dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616
Signed-off-by: Andre Przywara Acked-by: Rob Herring Acked-by: Maxime Ripard --- .../devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml index 3b45344ed758..b7e891803bb4 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml @@ -41,6 +41,8 @@ properties: - allwinner,sun50i-h5-ccu - allwinner,sun50i-h6-ccu - allwinner,sun50i-h6-r-ccu + - allwinner,sun50i-h616-ccu + - allwinner,sun50i-h616-r-ccu - allwinner,suniv-f1c100s-ccu - nextthing,gr8-ccu -- 2.17.5
[PATCH v4 15/21] phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling
As Icenowy pointed out, newer manuals (starting with H6) actually
document the register block at offset 0x800 as "HCI controller and PHY
interface", also describe the bits in our "PMU_UNK1" register.
Let's put proper names to those "unknown" variables and symbols.
While we are at it, generalise the existing code by allowing a bitmap
of bits to clear, to cover newer SoCs: The A100 and H616 use a different
bit for the SIDDQ control.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
drivers/phy/allwinner/phy-sun4i-usb.c | 29 +++
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 788dd5cdbb7d..539209fe3468 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -43,7 +43,7 @@
#define REG_PHYCTL_A33 0x10
#define REG_PHY_OTGCTL 0x20
-#define REG_PMU_UNK1 0x10
+#define REG_HCI_PHY_CTL0x10
#define PHYCTL_DATABIT(7)
@@ -115,9 +115,9 @@ struct sun4i_usb_phy_cfg {
int hsic_index;
enum sun4i_usb_phy_type type;
u32 disc_thresh;
+ u32 hci_phy_ctl_siddq;
u8 phyctl_offset;
bool dedicated_clocks;
- bool enable_pmu_unk1;
bool phy0_dual_route;
int missing_phys;
};
@@ -288,6 +288,12 @@ static int sun4i_usb_phy_init(struct phy *_phy)
return ret;
}
+ if (phy->pmu && data->cfg->hci_phy_ctl_siddq) {
+ val = readl(phy->pmu + REG_HCI_PHY_CTL);
+ val &= ~data->cfg->hci_phy_ctl_siddq;
+ writel(val, phy->pmu + REG_HCI_PHY_CTL);
+ }
+
if (data->cfg->type == sun8i_a83t_phy ||
data->cfg->type == sun50i_h6_phy) {
if (phy->index == 0) {
@@ -297,11 +303,6 @@ static int sun4i_usb_phy_init(struct phy *_phy)
writel(val, data->base + data->cfg->phyctl_offset);
}
} else {
- if (phy->pmu && data->cfg->enable_pmu_unk1) {
- val = readl(phy->pmu + REG_PMU_UNK1);
- writel(val & ~2, phy->pmu + REG_PMU_UNK1);
- }
-
/* Enable USB 45 Ohm resistor calibration */
if (phy->index == 0)
sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
@@ -863,7 +864,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
@@ -872,7 +872,6 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
.disc_thresh = 2,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
@@ -881,7 +880,6 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
@@ -890,7 +888,6 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
.disc_thresh = 2,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
@@ -899,7 +896,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
@@ -908,7 +904,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
@@ -925,7 +920,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
+ .hci_phy_ctl_siddq = BIT(1),
.phy0_dual_route = true,
};
@@ -935,7 +930,7 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
+ .hci_phy_ctl_siddq = BIT(1),
.phy0_dual_route = true,
};
@@ -945,7 +940,7 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1
[PATCH v4 04/21] dt-bindings: mfd: axp20x: Add AXP305 compatible (plus optional IRQ)
The AXP305 PMIC used in AXP805 seems to be fully compatible to the AXP805 PMIC, so add the proper chain of compatible strings. Also at least on one board (Orangepi Zero2) there is no interrupt line connected to the CPU, so make the "interrupts" property optional. Signed-off-by: Andre Przywara --- Documentation/devicetree/bindings/mfd/axp20x.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt b/Documentation/devicetree/bindings/mfd/axp20x.txt index 4991a6415796..4fd748101e3c 100644 --- a/Documentation/devicetree/bindings/mfd/axp20x.txt +++ b/Documentation/devicetree/bindings/mfd/axp20x.txt @@ -26,10 +26,10 @@ Required properties: * "x-powers,axp803" * "x-powers,axp806" * "x-powers,axp805", "x-powers,axp806" +* "x-powers,axp803", "x-powers,axp805", "x-powers,axp806" * "x-powers,axp809" * "x-powers,axp813" - reg: The I2C slave address or RSB hardware address for the AXP chip -- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin - interrupt-controller: The PMIC has its own internal IRQs - #interrupt-cells: Should be set to 1 @@ -43,6 +43,7 @@ more information: AXP20x/LDO3: software-based implementation Optional properties: +- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin - x-powers,dcdc-freq: defines the work frequency of DC-DC in KHz AXP152/20X: range: 750-1875, Default: 1.5 MHz AXP22X/8XX: range: 1800-4050, Default: 3 MHz -- 2.17.5
[PATCH v4 08/21] soc: sunxi: sram: Add support for more than one EMAC clock
The Allwinner H616 adds a second EMAC clock register at offset 0x34, for
controlling the second EMAC in this chip.
Allow to extend the regmap in this case, to cover more than the current
4 bytes exported.
Signed-off-by: Andre Przywara
---
drivers/soc/sunxi/sunxi_sram.c | 31 +++
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
index d4c7bd59429e..42833e33a96c 100644
--- a/drivers/soc/sunxi/sunxi_sram.c
+++ b/drivers/soc/sunxi/sunxi_sram.c
@@ -283,7 +283,7 @@ int sunxi_sram_release(struct device *dev)
EXPORT_SYMBOL(sunxi_sram_release);
struct sunxi_sramc_variant {
- bool has_emac_clock;
+ int num_emac_clocks;
};
static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
@@ -291,20 +291,31 @@ static const struct sunxi_sramc_variant
sun4i_a10_sramc_variant = {
};
static const struct sunxi_sramc_variant sun8i_h3_sramc_variant = {
- .has_emac_clock = true,
+ .num_emac_clocks = 1,
};
static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = {
- .has_emac_clock = true,
+ .num_emac_clocks = 1,
+};
+
+static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
+ .num_emac_clocks = 2,
};
#define SUNXI_SRAM_EMAC_CLOCK_REG 0x30
static bool sunxi_sram_regmap_accessible_reg(struct device *dev,
unsigned int reg)
{
- if (reg == SUNXI_SRAM_EMAC_CLOCK_REG)
- return true;
- return false;
+ const struct sunxi_sramc_variant *variant;
+
+ variant = of_device_get_match_data(dev);
+
+ if (reg < SUNXI_SRAM_EMAC_CLOCK_REG)
+ return false;
+ if (reg > SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
+ return false;
+
+ return true;
}
static struct regmap_config sunxi_sram_emac_clock_regmap = {
@@ -312,7 +323,7 @@ static struct regmap_config sunxi_sram_emac_clock_regmap = {
.val_bits = 32,
.reg_stride = 4,
/* last defined register */
- .max_register = SUNXI_SRAM_EMAC_CLOCK_REG,
+ .max_register = SUNXI_SRAM_EMAC_CLOCK_REG + 4,
/* other devices have no business accessing other registers */
.readable_reg = sunxi_sram_regmap_accessible_reg,
.writeable_reg = sunxi_sram_regmap_accessible_reg,
@@ -343,7 +354,7 @@ static int sunxi_sram_probe(struct platform_device *pdev)
if (!d)
return -ENOMEM;
- if (variant->has_emac_clock) {
+ if (variant->num_emac_clocks > 0) {
emac_clock = devm_regmap_init_mmio(>dev, base,
_sram_emac_clock_regmap);
@@ -387,6 +398,10 @@ static const struct of_device_id sunxi_sram_dt_match[] = {
.compatible = "allwinner,sun50i-h5-system-control",
.data = _a64_sramc_variant,
},
+ {
+ .compatible = "allwinner,sun50i-h616-system-control",
+ .data = _h616_sramc_variant,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
--
2.17.5
Re: [PATCH v3 18/21] dt-bindings: allwinner: Add H616 compatible strings
On Sun, 17 Jan 2021 22:28:47 -0600 Samuel Holland wrote: Hi, > On 1/17/21 8:08 PM, Andre Przywara wrote: > > Add simple "allwinner,sun50i-h616-xxx" compatible names to existing > > bindings, and pair them with an existing fallback compatible string, > > as the devices are compatible. > > This covers I2C, infrared, RTC and SPI. > > > > Use enums to group all compatible devices together. > > > > Signed-off-by: Andre Przywara > > Acked-by: Rob Herring > > Acked-by: Wolfram Sang # for I2C > > --- > > .../bindings/i2c/marvell,mv64xxx-i2c.yaml | 21 +++ > > .../media/allwinner,sun4i-a10-ir.yaml | 16 ++ > > .../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 3 +++ > > .../bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 + > > 4 files changed, 17 insertions(+), 24 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml > > b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml > > index 5b5ae402f97a..eb72dd571def 100644 > > --- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml > > +++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml > > @@ -18,21 +18,14 @@ properties: > >- const: allwinner,sun4i-a10-i2c > >- const: allwinner,sun6i-a31-i2c > >- items: > > - - const: allwinner,sun8i-a23-i2c > > + - enum: > > + - allwinner,sun8i-a23-i2c > > + - allwinner,sun8i-a83t-i2c > > + - allwinner,sun50i-a64-i2c > > + - allwinner,sun50i-a100-i2c > > + - allwinner,sun50i-h6-i2c > > + - allwinner,sun50i-h616-i2c > >- const: allwinner,sun6i-a31-i2c > > - - items: > > - - const: allwinner,sun8i-a83t-i2c > > - - const: allwinner,sun6i-a31-i2c > > - - items: > > - - const: allwinner,sun50i-a64-i2c > > - - const: allwinner,sun6i-a31-i2c > > - - items: > > - - const: allwinner,sun50i-a100-i2c > > - - const: allwinner,sun6i-a31-i2c > > - - items: > > - - const: allwinner,sun50i-h6-i2c > > - - const: allwinner,sun6i-a31-i2c > > - > >- const: marvell,mv64xxx-i2c > >- const: marvell,mv78230-i2c > >- const: marvell,mv78230-a0-i2c > > diff --git > > a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml > > b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml > > index 5fa19d4aeaf3..6d8395d6bca0 100644 > > --- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml > > +++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml > > @@ -20,16 +20,12 @@ properties: > >- const: allwinner,sun5i-a13-ir > >- const: allwinner,sun6i-a31-ir > >- items: > > - - const: allwinner,sun8i-a83t-ir > > - - const: allwinner,sun6i-a31-ir > > - - items: > > - - const: allwinner,sun8i-r40-ir > > - - const: allwinner,sun6i-a31-ir > > - - items: > > - - const: allwinner,sun50i-a64-ir > > - - const: allwinner,sun6i-a31-ir > > - - items: > > - - const: allwinner,sun50i-h6-ir > > + - enum: > > + - allwinner,sun8i-a83t-ir > > + - allwinner,sun8i-r40-ir > > + - allwinner,sun50i-a64-ir > > + - allwinner,sun50i-h6-ir > > + - allwinner,sun50i-h616-ir > >- const: allwinner,sun6i-a31-ir > > > >reg: > > diff --git > > a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml > > b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml > > index 37c2a601c3fa..97928efd2bc9 100644 > > --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml > > +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml > > @@ -26,6 +26,9 @@ properties: > >- const: allwinner,sun50i-a64-rtc > >- const: allwinner,sun8i-h3-rtc > >- const: allwinner,sun50i-h6-rtc > > + - items: > > + - const: allwinner,sun50i-h616-rtc > > + - const: allwinner,sun50i-h6-rtc > > Since H6, the RTC manages the 24 MHz DCXO, so it provides a fourth clock > output. If this is easy to change later, then it is fine for now, but > maybe it is better to get the H616 binding correct from the beginning? So
[PATCH v4 13/21] dt-bindings: spi: sunxi: Add H616 compatible string
Add the obvious compatible name to the existing SPI binding, and pair it with the existing H3 fallback compatible string, as the devices are compatible. Signed-off-by: Andre Przywara Acked-by: Rob Herring --- .../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index 7866a655d81c..908248260afa 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -25,6 +25,7 @@ properties: - enum: - allwinner,sun8i-r40-spi - allwinner,sun50i-h6-spi + - allwinner,sun50i-h616-spi - const: allwinner,sun8i-h3-spi reg: -- 2.17.5
[PATCH v4 06/21] mfd: axp20x: Allow AXP chips without interrupt lines
Currently the AXP chip requires to have its IRQ line connected to some
interrupt controller, and will fail probing when this is not the case.
On a new Allwinner SoC (H616) there is no NMI pin anymore, and at
least one board does not connect the AXP's IRQ pin to anything else,
so the interrupt functionality of the AXP chip is simply not available.
Check whether the interrupt line number returned by the platform code is
valid, before trying to register the irqchip. If not, we skip this
registration, to avoid the driver to bail out completely.
Signed-off-by: Andre Przywara
---
drivers/mfd/axp20x.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 3eae04e24ac8..00c163a1e20d 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -959,12 +959,17 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
}
- ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
- IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
- -1, axp20x->regmap_irq_chip, >regmap_irqc);
- if (ret) {
- dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret);
- return ret;
+ /* Only if there is an interrupt line connected towards the CPU. */
+ if (axp20x->irq > 0) {
+ ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
+ IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
+ -1, axp20x->regmap_irq_chip,
+ >regmap_irqc);
+ if (ret) {
+ dev_err(axp20x->dev, "failed to add irq chip: %d\n",
+ ret);
+ return ret;
+ }
}
ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
--
2.17.5
[PATCH v4 17/21] dt-bindings: usb: sunxi-musb: Add H616 compatible string
The H616 MUSB peripheral is presumably compatible to the H3 one. Signed-off-by: Andre Przywara Acked-by: Maxime Ripard --- .../devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml index d9207bf9d894..ad8983debeba 100644 --- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml +++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml @@ -22,6 +22,9 @@ properties: - allwinner,sun8i-a83t-musb - allwinner,sun50i-h6-musb - const: allwinner,sun8i-a33-musb + - items: + - const: allwinner,sun50i-h616-musb + - const: allwinner,sun8i-h3-musb reg: maxItems: 1 -- 2.17.5
[PATCH v4 02/21] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU
The clocks itself are identical to the H6 R-CCU, it's just that the H616
has not all of them implemented (or connected).
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
drivers/clk/sunxi-ng/Kconfig | 2 +-
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 48 ++
2 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index ce5f5847d5d3..feeb8d2074ee 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -33,7 +33,7 @@ config SUN50I_H6_CCU
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
config SUN50I_H6_R_CCU
- bool "Support for the Allwinner H6 PRCM CCU"
+ bool "Support for the Allwinner H6 and H616 PRCM CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index 56e351b513f3..f8909a7ed553 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -139,6 +139,16 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
_clk.common,
};
+static struct ccu_common *sun50i_h616_r_ccu_clks[] = {
+ _apb1_clk.common,
+ _apb2_clk.common,
+ _apb1_twd_clk.common,
+ _apb2_i2c_clk.common,
+ _apb2_rsb_clk.common,
+ _apb1_ir_clk.common,
+ _clk.common,
+};
+
static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
.hws= {
[CLK_AR100] = _clk.common.hw,
@@ -159,6 +169,20 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
.num= CLK_NUMBER,
};
+static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
+ .hws= {
+ [CLK_R_AHB] = _ahb_clk.hw,
+ [CLK_R_APB1]= _apb1_clk.common.hw,
+ [CLK_R_APB2]= _apb2_clk.common.hw,
+ [CLK_R_APB1_TWD]= _apb1_twd_clk.common.hw,
+ [CLK_R_APB2_I2C]= _apb2_i2c_clk.common.hw,
+ [CLK_R_APB2_RSB]= _apb2_rsb_clk.common.hw,
+ [CLK_R_APB1_IR] = _apb1_ir_clk.common.hw,
+ [CLK_IR]= _clk.common.hw,
+ },
+ .num= CLK_NUMBER,
+};
+
static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
[RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
[RST_R_APB1_TWD]= { 0x12c, BIT(16) },
@@ -170,6 +194,13 @@ static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
[RST_R_APB1_W1] = { 0x1ec, BIT(16) },
};
+static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
+ [RST_R_APB1_TWD]= { 0x12c, BIT(16) },
+ [RST_R_APB2_I2C]= { 0x19c, BIT(16) },
+ [RST_R_APB2_RSB]= { 0x1bc, BIT(16) },
+ [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
+};
+
static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
.ccu_clks = sun50i_h6_r_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
@@ -180,6 +211,16 @@ static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
.num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets),
};
+static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
+ .ccu_clks = sun50i_h616_r_ccu_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks),
+
+ .hw_clks= _h616_r_hw_clks,
+
+ .resets = sun50i_h616_r_ccu_resets,
+ .num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets),
+};
+
static void __init sunxi_r_ccu_init(struct device_node *node,
const struct sunxi_ccu_desc *desc)
{
@@ -200,3 +241,10 @@ static void __init sun50i_h6_r_ccu_setup(struct
device_node *node)
}
CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu",
sun50i_h6_r_ccu_setup);
+
+static void __init sun50i_h616_r_ccu_setup(struct device_node *node)
+{
+ sunxi_r_ccu_init(node, _h616_r_ccu_desc);
+}
+CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu",
+ sun50i_h616_r_ccu_setup);
--
2.17.5
[PATCH v4 03/21] clk: sunxi-ng: Add support for the Allwinner H616 CCU
While the clocks are fairly similar to the H6, many differ in tiny
details, so a separate clock driver seems indicated.
Derived from the H6 clock driver, and adjusted according to the manual.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
drivers/clk/sunxi-ng/Kconfig|5 +
drivers/clk/sunxi-ng/Makefile |1 +
drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 1150 +++
drivers/clk/sunxi-ng/ccu-sun50i-h616.h | 56 +
include/dt-bindings/clock/sun50i-h616-ccu.h | 115 ++
include/dt-bindings/reset/sun50i-h616-ccu.h | 70 ++
6 files changed, 1397 insertions(+)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.h
create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index feeb8d2074ee..cd46d8853876 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -32,6 +32,11 @@ config SUN50I_H6_CCU
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+config SUN50I_H616_CCU
+ bool "Support for the Allwinner H616 CCU"
+ default ARM64 && ARCH_SUNXI
+ depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+
config SUN50I_H6_R_CCU
bool "Support for the Allwinner H6 and H616 PRCM CCU"
default ARM64 && ARCH_SUNXI
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 3eb5cff40eac..96c324306d97 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
obj-$(CONFIG_SUN50I_A100_CCU) += ccu-sun50i-a100.o
obj-$(CONFIG_SUN50I_A100_R_CCU)+= ccu-sun50i-a100-r.o
obj-$(CONFIG_SUN50I_H6_CCU)+= ccu-sun50i-h6.o
+obj-$(CONFIG_SUN50I_H616_CCU) += ccu-sun50i-h616.o
obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
obj-$(CONFIG_SUN4I_A10_CCU)+= ccu-sun4i-a10.o
obj-$(CONFIG_SUN5I_CCU)+= ccu-sun5i.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
new file mode 100644
index ..225307305880
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
@@ -0,0 +1,1150 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Arm Ltd.
+ * Based on the H6 CCU driver, which is:
+ * Copyright (c) 2017 Icenowy Zheng
+ */
+
+#include
+#include
+#include
+#include
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+
+#include "ccu-sun50i-h616.h"
+
+/*
+ * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
+ * P should only be used for output frequencies lower than 288 MHz.
+ *
+ * For now we can just model it as a multiplier clock, and force P to /1.
+ *
+ * The M factor is present in the register's description, but not in the
+ * frequency formula, and it's documented as "M is only used for backdoor
+ * testing", so it's not modelled and then force to 0.
+ */
+#define SUN50I_H616_PLL_CPUX_REG 0x000
+static struct ccu_mult pll_cpux_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .common = {
+ .reg= 0x000,
+ .hw.init= CLK_HW_INIT("pll-cpux", "osc24M",
+ _mult_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
+
+/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
+#define SUN50I_H616_PLL_DDR0_REG 0x010
+static struct ccu_nkmp pll_ddr0_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
+ .common = {
+ .reg= 0x010,
+ .hw.init= CLK_HW_INIT("pll-ddr0", "osc24M",
+ _nkmp_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
+
+#define SUN50I_H616_PLL_DDR1_REG 0x018
+static struct ccu_nkmp pll_ddr1_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .p = _SUNXI_CCU_DIV(
[PATCH v4 07/21] dt-bindings: sram: sunxi-sram: Add H616 compatible string
The H616 adds a second EMAC clock register. We don't know about the exact SRAM properties yet, so this gets omitted for now. Signed-off-by: Andre Przywara Acked-by: Rob Herring --- .../bindings/sram/allwinner,sun4i-a10-system-control.yaml| 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml index b66a07e21d1e..1c426c211e36 100644 --- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -49,6 +49,7 @@ properties: - items: - const: allwinner,suniv-f1c100s-system-control - const: allwinner,sun4i-a10-system-control + - const: allwinner,sun50i-h616-system-control reg: maxItems: 1 -- 2.17.5
[PATCH v4 05/21] Input: axp20x-pek: Bail out if AXP has no interrupt line connected
On at least one board (Orangepi Zero2) the AXP305 PMIC does not have its interrupt line connected to the CPU (mostly because the H616 SoC does not feature an NMI pin anymore). After allowing the AXP driver to proceed without an "interrupts" property [1], the axp20x-pek driver crashes with a NULL pointer dereference (see below). Check for the regmap_irqc member to be not NULL before proceeding with probe. This gets normally filled by the call to regmap_add_irq_chip(), which we allow to skip now, when the DT node lacks an interrupt property. [3.843388] sunxi-rsb 7083000.rsb: RSB running at 300 Hz [3.849972] axp20x-rsb sunxi-rsb-745: AXP20x variant AXP806 found [3.857971] Unable to handle kernel NULL pointer dereference at virtual address 01b8 [3.866855] Mem abort info: [3.869691] ESR = 0x9604 [3.872749] EC = 0x25: DABT (current EL), IL = 32 bits [3.878092] SET = 0, FnV = 0 [3.881149] EA = 0, S1PTW = 0 [3.884309] Data abort info: [3.887210] ISV = 0, ISS = 0x0004 [3.891062] CM = 0, WnR = 0 [3.894049] [01b8] user address but active_mm is swapper [3.900590] Internal error: Oops: 9604 [#1] PREEMPT SMP [3.906166] Modules linked in: [3.909227] CPU: 2 PID: 34 Comm: kworker/2:1 Not tainted 5.11.0-rc1 [3.915925] Hardware name: OrangePi Zero2 (DT) [3.920367] Workqueue: events deferred_probe_work_func [3.925518] pstate: 4005 (nZcv daif -PAN -UAO -TCO BTYPE=--) [3.931522] pc : regmap_irq_get_virq+0x0/0x48 [3.935883] lr : axp20x_pek_probe+0x78/0x200 [3.940147] sp : 800012fdb450 [3.943459] x29: 800012fdb450 x28: 054af340 [3.948776] x27: 05534000 x26: 05534810 [3.954091] x25: 800012883028 x24: 0002 [3.959407] x23: 80001157eaf0 x22: 05534810 [3.964722] x21: 05534800 x20: 054b0580 [3.970037] x19: 000b x18: [3.975353] x17: 0001 x16: 0019 [3.980668] x15: 02ce4ea04ae6 x14: 014f [3.985983] x13: 0282 x12: 0030 [3.991298] x11: 0038 x10: 0101010101010101 [3.996613] x9 : x8 : 7f7f7f7f7f7f7f7f [4.001928] x7 : ff5141435e4a444f x6 : 0080 [4.007243] x5 : x4 : 8000 [4.012558] x3 : x2 : [4.017872] x1 : 000b x0 : [4.023188] Call trace: [4.025635] regmap_irq_get_virq+0x0/0x48 [4.029646] platform_probe+0x68/0xd8 [4.033312] really_probe+0xe4/0x3b0 [4.036889] driver_probe_device+0x58/0xb8 [4.040986] __device_attach_driver+0x84/0xc8 [4.045342] bus_for_each_drv+0x78/0xc8 [4.049178] __device_attach+0xf0/0x150 [4.053013] device_initial_probe+0x14/0x20 [4.057196] bus_probe_device+0x9c/0xa8 [4.061032] device_add+0x36c/0x7b8 [4.064525] platform_device_add+0x100/0x238 [4.068796] mfd_add_devices+0x494/0x718 [4.072721] axp20x_device_probe+0x70/0x158 [4.076904] axp20x_rsb_probe+0x94/0xd0 [4.080741] sunxi_rsb_device_probe+0x6c/0x88 [4.085102] really_probe+0xe4/0x3b0 [4.088679] driver_probe_device+0x58/0xb8 [4.092776] __device_attach_driver+0x84/0xc8 [4.097132] bus_for_each_drv+0x78/0xc8 [4.100967] __device_attach+0xf0/0x150 [4.104803] device_initial_probe+0x14/0x20 [4.108986] bus_probe_device+0x9c/0xa8 [4.112821] device_add+0x36c/0x7b8 [4.116313] device_register+0x20/0x30 [4.120065] sunxi_rsb_probe+0x4e4/0x608 [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2021-January/633392.html Signed-off-by: Andre Przywara --- drivers/input/misc/axp20x-pek.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/input/misc/axp20x-pek.c b/drivers/input/misc/axp20x-pek.c index 9c6386b2af33..abe52ef194ee 100644 --- a/drivers/input/misc/axp20x-pek.c +++ b/drivers/input/misc/axp20x-pek.c @@ -309,6 +309,10 @@ static int axp20x_pek_probe(struct platform_device *pdev) axp20x_pek->axp20x = dev_get_drvdata(pdev->dev.parent); + /* In case there is no interrupt line from the AXP towards the CPU. */ + if (!axp20x_pek->axp20x->regmap_irqc) + return -ENODEV; + axp20x_pek->irq_dbr = platform_get_irq_byname(pdev, "PEK_DBR"); if (axp20x_pek->irq_dbr < 0) return axp20x_pek->irq_dbr; -- 2.17.5
Re: [PATCH v3 09/21] mfd: axp20x: Allow AXP chips without interrupt lines
On Sun, 17 Jan 2021 21:37:22 -0600
Samuel Holland wrote:
Hi Samuel,
thanks for your input!
> On 1/17/21 8:08 PM, Andre Przywara wrote:
> > Currently the AXP chip requires to have its IRQ line connected to some
> > interrupt controller, and will fail probing when this is not the case.
> >
> > On a new Allwinner SoC (H616) there is no NMI pin anymore, so the
> > interrupt functionality of the AXP chip is simply not available.
> >
> > Check whether the DT describes the AXP chip as an interrupt controller
> > before trying to register the irqchip, to avoid probe failures on
> > setups without an interrupt.
>
> The AXP305 has an IRQ pin. It is still an interrupt controller, even if
> its output is not connected anywhere. And even though the NMI pin on the
> H616 is gone, the PMIC IRQ line could be connected to a GPIO. So it is
> not appropriate to remove "interrupt-controller".
That's a fair point.
> Per the binding, both "interrupts" and "interrupt-controller" are
> required properties. It would make more sense to make "interrupts"
> optional. Either way, you need to update the binding.
I agree.
So I will replace the explicit check for the interrupt-controller
property with a check for axp20x->irq being not 0 (which is apparently
the right check for this, according to my research).
And also adjust the binding to make "interrupts" optional.
> Though I'm concerned about how this may affect drivers for regmap cells
> which use interrupts (such as axp20x-pek). If the irqchip is not
> registered, requesting those interrupts will fail. While I don't
> currently know of any boards that have the AXP305 power key wired up, it
> prevents us from modelling the hardware correctly and supporting that
> configuration.
Good point! Indeed axp20x_pek_probe() crashes with a NULL pointer
dereference. I think this device is unconditionally tied to the AXP
drivers, and this is probably fine, as it looks trivial to check the
regmap_irqc pointer before passing it on to regmap_irq_get_virq(),
bailing out if this is NULL.
Will send the patch shortly, then update this patch here as well.
And I guess the outcome (power button input device not available) is
reasonable as well. The hardware power button feature (off after 6s)
would work nevertheless. If board vendors expect more functionality
from the button, they should connect the AXP IRQ pin to a GPIO.
Cheers,
Andre
>
> Cheers,
> Samuel
>
> > Signed-off-by: Andre Przywara
> > ---
> > drivers/mfd/axp20x.c | 17 +++--
> > 1 file changed, 11 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
> > index aa59496e4376..a52595c49d40 100644
> > --- a/drivers/mfd/axp20x.c
> > +++ b/drivers/mfd/axp20x.c
> > @@ -959,12 +959,17 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
> > AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
> > }
> >
> > - ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
> > - IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
> > - -1, axp20x->regmap_irq_chip, >regmap_irqc);
> > - if (ret) {
> > - dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret);
> > - return ret;
> > + if (!axp20x->dev->of_node ||
> > + of_property_read_bool(axp20x->dev->of_node,
> > "interrupt-controller")) {
> > + ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
> > + IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
> > + -1, axp20x->regmap_irq_chip,
> > + >regmap_irqc);
> > + if (ret) {
> > + dev_err(axp20x->dev, "failed to add irq chip: %d\n",
> > + ret);
> > + return ret;
> > + }
> > }
> >
> > ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
> >
>
Re: [PATCH v6 0/5] ARM: arm64: Add SMCCC TRNG entropy service
On Wed, 20 Jan 2021 13:26:26 + Marc Zyngier wrote: Hi, > On 2021-01-20 13:01, Will Deacon wrote: > > On Wed, 6 Jan 2021 10:34:48 +0000, Andre Przywara wrote: > >> a fix to v5, now *really* fixing the wrong priority of SMCCC vs. > >> RNDR in arch_get_random_seed_long_early(). Apologies for messing > >> this up in v5 and thanks to broonie for being on the watch! > >> > >> Will, Catalin: it would be much appreciated if you could consider > >> taking > >> patch 1/5. This contains the common definitions, and is a > >> prerequisite for every other patch, although they are somewhat > >> independent and likely > >> will need to go through different subsystems. > >> > >> [...] > > > > Applied the first patch only to arm64 (for-next/rng), thanks! > > > > [1/5] firmware: smccc: Add SMCCC TRNG function call IDs > > https://git.kernel.org/arm64/c/67c6bb56b649 > > I can't see how the rest of the patches can go via any other tree > if all the definitions are in the first one. > > Andre, can you explain what your plan is? Well, I don't really have a great solution for that, other than hoping that 1/5 makes it into Linus' master at some point. I see that it's a stretch, but pulling 1/5 into 5.11 now would prepare the stage for the others to go via any tree, into 5.12-rc1? Or you could maybe take both 1/5 and 5/5 into your kvm-arm tree, and would hope that a git rebase later would sort this out for you? But I think you are much more experienced in those kind of issues, so happy to hear about any other solutions. Thanks, Andre
Re: [PATCH v3 02/21] mmc: sunxi: add support for A100 mmc controller
On Mon, 18 Jan 2021 14:28:54 +0100 Maxime Ripard wrote: Hi Maxime, > On Mon, Jan 18, 2021 at 02:08:29AM +0000, Andre Przywara wrote: > > From: Yangtao Li > > > > This patch adds support for A100 MMC controller, which use word > > address for internal dma. > > > > Signed-off-by: Yangtao Li > > Signed-off-by: Andre Przywara > > We should also disable the timings setup in probe to derive them from > the DT. This is causing issues on some SoCs already, so it would be > best to not make the situation worse But only for those new SoCs, where we have the speed modes in the DT in every case (so only new ones)? And this disabling would be SoC/compatible string dependent? Happy to send a patch later if that is what you were thinking about. Also I was wondering about the voltage dependent speed modes: At the moment the driver declares both MMC_CAP_1_8V_DDR and MMC_CAP_3_3V_DDR, so I mimic this in the .dtsi. However in the eventual DTB this looks somewhat dodgy, since most boards only support one of those voltages. Do we ignore this, and rely on the vqmmc-supply to limit this choice? Cheers, Andre Btw: This patch is already in Ulf's -next tree, I just included it here for the sake of completeness. Is that a problem? I don't think it affects the build, so we don't care too much?
[PATCH v3 17/21] dt-bindings: watchdog: sun4i: Add H616 compatible string
Use enums to group all compatible devices together on the way. Signed-off-by: Andre Przywara Acked-by: Rob Herring --- .../bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 5ac607de8be4..9aa3c313c49f 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -19,13 +19,11 @@ properties: - const: allwinner,sun4i-a10-wdt - const: allwinner,sun6i-a31-wdt - items: - - const: allwinner,sun50i-a64-wdt - - const: allwinner,sun6i-a31-wdt - - items: - - const: allwinner,sun50i-a100-wdt - - const: allwinner,sun6i-a31-wdt - - items: - - const: allwinner,sun50i-h6-wdt + - enum: + - allwinner,sun50i-a64-wdt + - allwinner,sun50i-a100-wdt + - allwinner,sun50i-h6-wdt + - allwinner,sun50i-h616-wdt - const: allwinner,sun6i-a31-wdt - items: - const: allwinner,suniv-f1c100s-wdt -- 2.17.5
[PATCH v3 06/21] dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616
Signed-off-by: Andre Przywara Acked-by: Rob Herring --- .../devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml index 3b45344ed758..b7e891803bb4 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml @@ -41,6 +41,8 @@ properties: - allwinner,sun50i-h5-ccu - allwinner,sun50i-h6-ccu - allwinner,sun50i-h6-r-ccu + - allwinner,sun50i-h616-ccu + - allwinner,sun50i-h616-r-ccu - allwinner,suniv-f1c100s-ccu - nextthing,gr8-ccu -- 2.17.5
[PATCH v3 05/21] pinctrl: sunxi: Add support for the Allwinner H616-R pin controller
There are only two pins left now, used to connect to the PMIC via I2C.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
Reviewed-by: Jernej Skrabec
---
drivers/pinctrl/sunxi/Kconfig | 5 ++
drivers/pinctrl/sunxi/Makefile| 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c | 56 +++
3 files changed, 62 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 73e88ce71a48..33751a6a0757 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -124,4 +124,9 @@ config PINCTRL_SUN50I_H616
default ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_H616_R
+ bool "Support for the Allwinner H616 R-PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 5359327a3c8f..d3440c42b9d6 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -24,5 +24,6 @@ obj-$(CONFIG_PINCTRL_SUN50I_H5) +=
pinctrl-sun50i-h5.o
obj-$(CONFIG_PINCTRL_SUN50I_H6)+= pinctrl-sun50i-h6.o
obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o
obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o
+obj-$(CONFIG_PINCTRL_SUN50I_H616_R)+= pinctrl-sun50i-h616-r.o
obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c
b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c
new file mode 100644
index ..8e4f10ab96ce
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Allwinner H616 R_PIO pin controller driver
+ *
+ * Copyright (C) 2020 Arm Ltd.
+ * Based on former work, which is:
+ * Copyright (C) 2017 Icenowy Zheng
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin sun50i_h616_r_pins[] = {
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
+ SUNXI_FUNCTION(0x3, "s_i2c")),/* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
+ SUNXI_FUNCTION(0x3, "s_i2c")),/* SDA */
+};
+
+static const struct sunxi_pinctrl_desc sun50i_h616_r_pinctrl_data = {
+ .pins = sun50i_h616_r_pins,
+ .npins = ARRAY_SIZE(sun50i_h616_r_pins),
+ .pin_base = PL_BASE,
+};
+
+static int sun50i_h616_r_pinctrl_probe(struct platform_device *pdev)
+{
+ return sunxi_pinctrl_init(pdev,
+ _h616_r_pinctrl_data);
+}
+
+static const struct of_device_id sun50i_h616_r_pinctrl_match[] = {
+ { .compatible = "allwinner,sun50i-h616-r-pinctrl", },
+ {}
+};
+
+static struct platform_driver sun50i_h616_r_pinctrl_driver = {
+ .probe = sun50i_h616_r_pinctrl_probe,
+ .driver = {
+ .name = "sun50i-h616-r-pinctrl",
+ .of_match_table = sun50i_h616_r_pinctrl_match,
+ },
+};
+builtin_platform_driver(sun50i_h616_r_pinctrl_driver);
--
2.17.5
[PATCH v3 07/21] clk: sunxi-ng: Add support for the Allwinner H616 R-CCU
The clocks itself are identical to the H6 R-CCU, it's just that the H616
has not all of them implemented (or connected).
Signed-off-by: Andre Przywara
---
drivers/clk/sunxi-ng/Kconfig | 2 +-
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 48 ++
2 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index ce5f5847d5d3..feeb8d2074ee 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -33,7 +33,7 @@ config SUN50I_H6_CCU
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
config SUN50I_H6_R_CCU
- bool "Support for the Allwinner H6 PRCM CCU"
+ bool "Support for the Allwinner H6 and H616 PRCM CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index 56e351b513f3..f8909a7ed553 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -139,6 +139,16 @@ static struct ccu_common *sun50i_h6_r_ccu_clks[] = {
_clk.common,
};
+static struct ccu_common *sun50i_h616_r_ccu_clks[] = {
+ _apb1_clk.common,
+ _apb2_clk.common,
+ _apb1_twd_clk.common,
+ _apb2_i2c_clk.common,
+ _apb2_rsb_clk.common,
+ _apb1_ir_clk.common,
+ _clk.common,
+};
+
static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
.hws= {
[CLK_AR100] = _clk.common.hw,
@@ -159,6 +169,20 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
.num= CLK_NUMBER,
};
+static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
+ .hws= {
+ [CLK_R_AHB] = _ahb_clk.hw,
+ [CLK_R_APB1]= _apb1_clk.common.hw,
+ [CLK_R_APB2]= _apb2_clk.common.hw,
+ [CLK_R_APB1_TWD]= _apb1_twd_clk.common.hw,
+ [CLK_R_APB2_I2C]= _apb2_i2c_clk.common.hw,
+ [CLK_R_APB2_RSB]= _apb2_rsb_clk.common.hw,
+ [CLK_R_APB1_IR] = _apb1_ir_clk.common.hw,
+ [CLK_IR]= _clk.common.hw,
+ },
+ .num= CLK_NUMBER,
+};
+
static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
[RST_R_APB1_TIMER] = { 0x11c, BIT(16) },
[RST_R_APB1_TWD]= { 0x12c, BIT(16) },
@@ -170,6 +194,13 @@ static struct ccu_reset_map sun50i_h6_r_ccu_resets[] = {
[RST_R_APB1_W1] = { 0x1ec, BIT(16) },
};
+static struct ccu_reset_map sun50i_h616_r_ccu_resets[] = {
+ [RST_R_APB1_TWD]= { 0x12c, BIT(16) },
+ [RST_R_APB2_I2C]= { 0x19c, BIT(16) },
+ [RST_R_APB2_RSB]= { 0x1bc, BIT(16) },
+ [RST_R_APB1_IR] = { 0x1cc, BIT(16) },
+};
+
static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
.ccu_clks = sun50i_h6_r_ccu_clks,
.num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
@@ -180,6 +211,16 @@ static const struct sunxi_ccu_desc sun50i_h6_r_ccu_desc = {
.num_resets = ARRAY_SIZE(sun50i_h6_r_ccu_resets),
};
+static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
+ .ccu_clks = sun50i_h616_r_ccu_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks),
+
+ .hw_clks= _h616_r_hw_clks,
+
+ .resets = sun50i_h616_r_ccu_resets,
+ .num_resets = ARRAY_SIZE(sun50i_h616_r_ccu_resets),
+};
+
static void __init sunxi_r_ccu_init(struct device_node *node,
const struct sunxi_ccu_desc *desc)
{
@@ -200,3 +241,10 @@ static void __init sun50i_h6_r_ccu_setup(struct
device_node *node)
}
CLK_OF_DECLARE(sun50i_h6_r_ccu, "allwinner,sun50i-h6-r-ccu",
sun50i_h6_r_ccu_setup);
+
+static void __init sun50i_h616_r_ccu_setup(struct device_node *node)
+{
+ sunxi_r_ccu_init(node, _h616_r_ccu_desc);
+}
+CLK_OF_DECLARE(sun50i_h616_r_ccu, "allwinner,sun50i-h616-r-ccu",
+ sun50i_h616_r_ccu_setup);
--
2.17.5
[PATCH v3 20/21] dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding
Signed-off-by: Andre Przywara Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 7ea4d9645e93..6a2fa84bb785 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -931,4 +931,9 @@ properties: - const: xunlong,orangepi-zero-plus2-h3 - const: allwinner,sun8i-h3 + - description: Xunlong OrangePi Zero 2 +items: + - const: xunlong,orangepi-zero2 + - const: allwinner,sun50i-h616 + additionalProperties: true -- 2.17.5
[PATCH v3 11/21] soc: sunxi: sram: Add support for more than one EMAC clock
The Allwinner H616 adds a second EMAC clock register at offset 0x34, for
controlling the second EMAC in this chip.
Allow to extend the regmap in this case, to cover more than the current
4 bytes exported.
Signed-off-by: Andre Przywara
---
drivers/soc/sunxi/sunxi_sram.c | 31 +++
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
index d4c7bd59429e..42833e33a96c 100644
--- a/drivers/soc/sunxi/sunxi_sram.c
+++ b/drivers/soc/sunxi/sunxi_sram.c
@@ -283,7 +283,7 @@ int sunxi_sram_release(struct device *dev)
EXPORT_SYMBOL(sunxi_sram_release);
struct sunxi_sramc_variant {
- bool has_emac_clock;
+ int num_emac_clocks;
};
static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
@@ -291,20 +291,31 @@ static const struct sunxi_sramc_variant
sun4i_a10_sramc_variant = {
};
static const struct sunxi_sramc_variant sun8i_h3_sramc_variant = {
- .has_emac_clock = true,
+ .num_emac_clocks = 1,
};
static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = {
- .has_emac_clock = true,
+ .num_emac_clocks = 1,
+};
+
+static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
+ .num_emac_clocks = 2,
};
#define SUNXI_SRAM_EMAC_CLOCK_REG 0x30
static bool sunxi_sram_regmap_accessible_reg(struct device *dev,
unsigned int reg)
{
- if (reg == SUNXI_SRAM_EMAC_CLOCK_REG)
- return true;
- return false;
+ const struct sunxi_sramc_variant *variant;
+
+ variant = of_device_get_match_data(dev);
+
+ if (reg < SUNXI_SRAM_EMAC_CLOCK_REG)
+ return false;
+ if (reg > SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
+ return false;
+
+ return true;
}
static struct regmap_config sunxi_sram_emac_clock_regmap = {
@@ -312,7 +323,7 @@ static struct regmap_config sunxi_sram_emac_clock_regmap = {
.val_bits = 32,
.reg_stride = 4,
/* last defined register */
- .max_register = SUNXI_SRAM_EMAC_CLOCK_REG,
+ .max_register = SUNXI_SRAM_EMAC_CLOCK_REG + 4,
/* other devices have no business accessing other registers */
.readable_reg = sunxi_sram_regmap_accessible_reg,
.writeable_reg = sunxi_sram_regmap_accessible_reg,
@@ -343,7 +354,7 @@ static int sunxi_sram_probe(struct platform_device *pdev)
if (!d)
return -ENOMEM;
- if (variant->has_emac_clock) {
+ if (variant->num_emac_clocks > 0) {
emac_clock = devm_regmap_init_mmio(>dev, base,
_sram_emac_clock_regmap);
@@ -387,6 +398,10 @@ static const struct of_device_id sunxi_sram_dt_match[] = {
.compatible = "allwinner,sun50i-h5-system-control",
.data = _a64_sramc_variant,
},
+ {
+ .compatible = "allwinner,sun50i-h616-system-control",
+ .data = _h616_sramc_variant,
+ },
{ },
};
MODULE_DEVICE_TABLE(of, sunxi_sram_dt_match);
--
2.17.5
[PATCH v3 16/21] phy: sun4i-usb: Add support for the H616 USB PHY
The USB PHY used in the Allwinner H616 SoC inherits some traits from its
various predecessors: it has four full PHYs like the H3, needs some
extra bits to be set like the H6, and clears a different bit in the
PMU_UNK1 register like the A100.
Name all those properties in a new config struct and assign a new
compatible name to it.
Signed-off-by: Andre Przywara
---
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 539209fe3468..e71d6b8ccf16 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -964,6 +964,16 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
.missing_phys = BIT(1) | BIT(2),
};
+static const struct sun4i_usb_phy_cfg sun50i_h616_cfg = {
+ .num_phys = 4,
+ .type = sun50i_h6_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A33,
+ .dedicated_clocks = true,
+ .phy0_dual_route = true,
+ .hci_phy_ctl_siddq = BIT(3),
+};
+
static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = _a10_cfg },
{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = _a13_cfg },
@@ -978,6 +988,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] =
{
{ .compatible = "allwinner,sun50i-a64-usb-phy",
.data = _a64_cfg},
{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = _h6_cfg },
+ { .compatible = "allwinner,sun50i-h616-usb-phy", .data =
_h616_cfg },
{ },
};
MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
--
2.17.5
[PATCH v3 18/21] dt-bindings: allwinner: Add H616 compatible strings
Add simple "allwinner,sun50i-h616-xxx" compatible names to existing bindings, and pair them with an existing fallback compatible string, as the devices are compatible. This covers I2C, infrared, RTC and SPI. Use enums to group all compatible devices together. Signed-off-by: Andre Przywara Acked-by: Rob Herring Acked-by: Wolfram Sang # for I2C --- .../bindings/i2c/marvell,mv64xxx-i2c.yaml | 21 +++ .../media/allwinner,sun4i-a10-ir.yaml | 16 ++ .../bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 3 +++ .../bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 + 4 files changed, 17 insertions(+), 24 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml index 5b5ae402f97a..eb72dd571def 100644 --- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml @@ -18,21 +18,14 @@ properties: - const: allwinner,sun4i-a10-i2c - const: allwinner,sun6i-a31-i2c - items: - - const: allwinner,sun8i-a23-i2c + - enum: + - allwinner,sun8i-a23-i2c + - allwinner,sun8i-a83t-i2c + - allwinner,sun50i-a64-i2c + - allwinner,sun50i-a100-i2c + - allwinner,sun50i-h6-i2c + - allwinner,sun50i-h616-i2c - const: allwinner,sun6i-a31-i2c - - items: - - const: allwinner,sun8i-a83t-i2c - - const: allwinner,sun6i-a31-i2c - - items: - - const: allwinner,sun50i-a64-i2c - - const: allwinner,sun6i-a31-i2c - - items: - - const: allwinner,sun50i-a100-i2c - - const: allwinner,sun6i-a31-i2c - - items: - - const: allwinner,sun50i-h6-i2c - - const: allwinner,sun6i-a31-i2c - - const: marvell,mv64xxx-i2c - const: marvell,mv78230-i2c - const: marvell,mv78230-a0-i2c diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml index 5fa19d4aeaf3..6d8395d6bca0 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-ir.yaml @@ -20,16 +20,12 @@ properties: - const: allwinner,sun5i-a13-ir - const: allwinner,sun6i-a31-ir - items: - - const: allwinner,sun8i-a83t-ir - - const: allwinner,sun6i-a31-ir - - items: - - const: allwinner,sun8i-r40-ir - - const: allwinner,sun6i-a31-ir - - items: - - const: allwinner,sun50i-a64-ir - - const: allwinner,sun6i-a31-ir - - items: - - const: allwinner,sun50i-h6-ir + - enum: + - allwinner,sun8i-a83t-ir + - allwinner,sun8i-r40-ir + - allwinner,sun50i-a64-ir + - allwinner,sun50i-h6-ir + - allwinner,sun50i-h616-ir - const: allwinner,sun6i-a31-ir reg: diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml index 37c2a601c3fa..97928efd2bc9 100644 --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -26,6 +26,9 @@ properties: - const: allwinner,sun50i-a64-rtc - const: allwinner,sun8i-h3-rtc - const: allwinner,sun50i-h6-rtc + - items: + - const: allwinner,sun50i-h616-rtc + - const: allwinner,sun50i-h6-rtc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index 7866a655d81c..908248260afa 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -25,6 +25,7 @@ properties: - enum: - allwinner,sun8i-r40-spi - allwinner,sun50i-h6-spi + - allwinner,sun50i-h616-spi - const: allwinner,sun8i-h3-spi reg: -- 2.17.5
[PATCH v3 15/21] dt-bindings: usb: sunxi-musb: Add H616 compatible string
The H616 MUSB peripheral is presumably compatible to the H3 one. Signed-off-by: Andre Przywara --- .../devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml index d9207bf9d894..ad8983debeba 100644 --- a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml +++ b/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml @@ -22,6 +22,9 @@ properties: - allwinner,sun8i-a83t-musb - allwinner,sun50i-h6-musb - const: allwinner,sun8i-a33-musb + - items: + - const: allwinner,sun50i-h616-musb + - const: allwinner,sun8i-h3-musb reg: maxItems: 1 -- 2.17.5
[PATCH v3 21/21] arm64: dts: allwinner: Add OrangePi Zero 2 .dts
The OrangePi Zero 2 is a development board with the new H616 SoC.
It features the usual connectors used on those small boards, and comes
with the AXP305, which seems to be compatible with the AXP805.
For more details see: http://linux-sunxi.org/Xunlong_Orange_Pi_Zero2
Signed-off-by: Andre Przywara
---
arch/arm64/boot/dts/allwinner/Makefile| 1 +
.../allwinner/sun50i-h616-orangepi-zero2.dts | 240 ++
2 files changed, 241 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile
b/arch/arm64/boot/dts/allwinner/Makefile
index 41ce680e5f8d..9ba4b5d92657 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -36,3 +36,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
new file mode 100644
index ..7f49d192fe41
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
@@ -0,0 +1,240 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2020 Arm Ltd.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+
+#include
+#include
+#include
+
+/ {
+ model = "OrangePi Zero2";
+ compatible = "xunlong,orangepi-zero2", "allwinner,sun50i-h616";
+
+ aliases {
+ ethernet0 =
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_POWER;
+ color = ;
+ gpios = < 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
+ default-state = "on";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = ;
+ gpios = < 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
+ };
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the USB-C socket */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ };
+
+ reg_usb1_vbus: usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <_vcc5v>;
+ enable-active-high;
+ gpio = < 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+ status = "okay";
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+/* USB 2 & 3 are on headers only. */
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <_rgmii_phy>;
+ phy-supply = <_dcdce>;
+ allwinner,rx-delay-ps = <3100>;
+ allwinner,tx-delay-ps = <700>;
+ status = "okay";
+};
+
+ {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+ {
+ vmmc-supply = <_dcdce>;
+ cd-gpios = < 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ bus-width = <4>;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+_rsb {
+ status = "okay";
+
+ axp305: pmic@745 {
+ compatible = "x-powers,axp305", "x-powers,axp805",
+"x-powers,axp806";
+ reg = <0x745>;
+
+ x-powers,self-working-mode;
+ vina-supply = <_vcc5v>;
+ vinb-supply = <_vcc5v>;
+ vinc-supply = <_vcc5v>;
+ vind-supply = <_vcc5v>;
+ vine-supply = <_vcc5v>;
+ aldoin-supply = <_vcc5v>;
+ bldoin-supply = <_vcc5v>;
+ cldoin-supply = <_vcc5v>;
+
+ regulators {
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+
[PATCH v3 19/21] arm64: dts: allwinner: Add Allwinner H616 .dtsi file
This (relatively) new SoC is similar to the H6, but drops the (broken)
PCIe support and the USB 3.0 controller. It also gets the management
controller removed, which in turn removes *some*, but not all of the
devices formerly dedicated to the ARISC (CPUS).
There does not seem to be an extra interrupt controller anymore, also
it lacks the corresponding NMI pin, so no interrupts for the PMIC.
Signed-off-by: Andre Przywara
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 750 ++
1 file changed, 750 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
new file mode 100644
index ..953e8fac20f0
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
@@ -0,0 +1,750 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Arm Ltd.
+// based on the H6 dtsi, which is:
+// Copyright (C) 2017 Icenowy Zheng
+
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ interrupt-parent = <>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 512KiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@4000 {
+ reg = <0x0 0x4000 0x0 0x8>;
+ no-map;
+ };
+ };
+
+ osc24M: osc24M_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2400>;
+ clock-output-names = "osc24M";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = ,
+,
+,
+;
+ interrupt-affinity = <>, <>, <>, <>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ arm,no-tick-in-suspend;
+ interrupts = ,
+,
+,
+;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x4000>;
+
+ syscon: syscon@300 {
+ compatible = "allwinner,sun50i-h616-system-control";
+ reg = <0x0300 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_c: sram@28000 {
+ compatible = "mmio-sram";
+ reg = <0x00028000 0x3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00028000 0x3>;
+ };
+ };
+
+ ccu: clock@3001000 {
+ compatible = "allwinner,sun50i-h616-ccu";
+ reg = &
[PATCH v3 13/21] phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling
As Icenowy pointed out, newer manuals (starting with H6) actually
document the register block at offset 0x800 as "HCI controller and PHY
interface", also describe the bits in our "PMU_UNK1" register.
Let's put proper names to those "unknown" variables and symbols.
While we are at it, generalise the existing code by allowing a bitmap
of bits to clear, to cover newer SoCs: The A100 and H616 use a different
bit for the SIDDQ control.
Signed-off-by: Andre Przywara
---
drivers/phy/allwinner/phy-sun4i-usb.c | 29 +++
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 788dd5cdbb7d..539209fe3468 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -43,7 +43,7 @@
#define REG_PHYCTL_A33 0x10
#define REG_PHY_OTGCTL 0x20
-#define REG_PMU_UNK1 0x10
+#define REG_HCI_PHY_CTL0x10
#define PHYCTL_DATABIT(7)
@@ -115,9 +115,9 @@ struct sun4i_usb_phy_cfg {
int hsic_index;
enum sun4i_usb_phy_type type;
u32 disc_thresh;
+ u32 hci_phy_ctl_siddq;
u8 phyctl_offset;
bool dedicated_clocks;
- bool enable_pmu_unk1;
bool phy0_dual_route;
int missing_phys;
};
@@ -288,6 +288,12 @@ static int sun4i_usb_phy_init(struct phy *_phy)
return ret;
}
+ if (phy->pmu && data->cfg->hci_phy_ctl_siddq) {
+ val = readl(phy->pmu + REG_HCI_PHY_CTL);
+ val &= ~data->cfg->hci_phy_ctl_siddq;
+ writel(val, phy->pmu + REG_HCI_PHY_CTL);
+ }
+
if (data->cfg->type == sun8i_a83t_phy ||
data->cfg->type == sun50i_h6_phy) {
if (phy->index == 0) {
@@ -297,11 +303,6 @@ static int sun4i_usb_phy_init(struct phy *_phy)
writel(val, data->base + data->cfg->phyctl_offset);
}
} else {
- if (phy->pmu && data->cfg->enable_pmu_unk1) {
- val = readl(phy->pmu + REG_PMU_UNK1);
- writel(val & ~2, phy->pmu + REG_PMU_UNK1);
- }
-
/* Enable USB 45 Ohm resistor calibration */
if (phy->index == 0)
sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
@@ -863,7 +864,6 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
@@ -872,7 +872,6 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
.disc_thresh = 2,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
@@ -881,7 +880,6 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
@@ -890,7 +888,6 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
.disc_thresh = 2,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
@@ -899,7 +896,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
@@ -908,7 +904,6 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
@@ -925,7 +920,7 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
+ .hci_phy_ctl_siddq = BIT(1),
.phy0_dual_route = true,
};
@@ -935,7 +930,7 @@ static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
+ .hci_phy_ctl_siddq = BIT(1),
.phy0_dual_route = true,
};
@@ -945,7 +940,7 @@ static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
- .enable_pmu_unk1 = true,
+ .hci_phy
[PATCH v3 14/21] dt-bindings: usb: Add H616 compatible string
The H616 has four PHYs as the H3, along with their respective clock gates and resets, so the property description is identical. However the PHYs itself need some special bits, so we need a new compatible string for it. Signed-off-by: Andre Przywara --- .../devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml index 60c344585276..f6f2dcb6dc1e 100644 --- a/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml +++ b/Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml @@ -15,7 +15,9 @@ properties: const: 1 compatible: -const: allwinner,sun8i-h3-usb-phy +oneOf: + - const: allwinner,sun8i-h3-usb-phy + - const: allwinner,sun50i-h616-usb-phy reg: items: -- 2.17.5
[PATCH v3 12/21] net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register
The Allwinner H616 SoC has two EMAC controllers, with the second one
being tied to the internal PHY, but also using a separate EMAC clock
register.
To tell the driver about which clock register to use, we add a parameter
to our syscon phandle. The driver will use this value as an index into
the regmap, so that we can address more than the first register, if
needed.
Signed-off-by: Andre Przywara
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 58e0511badba..00c10ec7b693 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -1129,6 +1129,8 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
struct stmmac_priv *priv;
struct net_device *ndev;
struct regmap *regmap;
+ struct reg_field syscon_field;
+ u32 syscon_idx = 0;
ret = stmmac_get_platform_resources(pdev, _res);
if (ret)
@@ -1190,8 +1192,12 @@ static int sun8i_dwmac_probe(struct platform_device
*pdev)
return ret;
}
- gmac->regmap_field = devm_regmap_field_alloc(dev, regmap,
-
*gmac->variant->syscon_field);
+ syscon_field = *gmac->variant->syscon_field;
+ ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1,
+_idx);
+ if (!ret)
+ syscon_field.reg += syscon_idx * sizeof(u32);
+ gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, syscon_field);
if (IS_ERR(gmac->regmap_field)) {
ret = PTR_ERR(gmac->regmap_field);
dev_err(dev, "Unable to map syscon register: %d\n", ret);
@@ -1263,6 +1269,8 @@ static const struct of_device_id sun8i_dwmac_match[] = {
.data = _variant_a64 },
{ .compatible = "allwinner,sun50i-h6-emac",
.data = _variant_h6 },
+ { .compatible = "allwinner,sun50i-h616-emac",
+ .data = _variant_h6 },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
--
2.17.5
[PATCH v3 09/21] mfd: axp20x: Allow AXP chips without interrupt lines
Currently the AXP chip requires to have its IRQ line connected to some
interrupt controller, and will fail probing when this is not the case.
On a new Allwinner SoC (H616) there is no NMI pin anymore, so the
interrupt functionality of the AXP chip is simply not available.
Check whether the DT describes the AXP chip as an interrupt controller
before trying to register the irqchip, to avoid probe failures on
setups without an interrupt.
Signed-off-by: Andre Przywara
---
drivers/mfd/axp20x.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index aa59496e4376..a52595c49d40 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -959,12 +959,17 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
}
- ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
- IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
- -1, axp20x->regmap_irq_chip, >regmap_irqc);
- if (ret) {
- dev_err(axp20x->dev, "failed to add irq chip: %d\n", ret);
- return ret;
+ if (!axp20x->dev->of_node ||
+ of_property_read_bool(axp20x->dev->of_node,
"interrupt-controller")) {
+ ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
+ IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
+ -1, axp20x->regmap_irq_chip,
+ >regmap_irqc);
+ if (ret) {
+ dev_err(axp20x->dev, "failed to add irq chip: %d\n",
+ ret);
+ return ret;
+ }
}
ret = mfd_add_devices(axp20x->dev, -1, axp20x->cells,
--
2.17.5
[PATCH v3 08/21] clk: sunxi-ng: Add support for the Allwinner H616 CCU
While the clocks are fairly similar to the H6, many differ in tiny
details, so a separate clock driver seems indicated.
Derived from the H6 clock driver, and adjusted according to the manual.
Signed-off-by: Andre Przywara
---
drivers/clk/sunxi-ng/Kconfig|5 +
drivers/clk/sunxi-ng/Makefile |1 +
drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 1150 +++
drivers/clk/sunxi-ng/ccu-sun50i-h616.h | 56 +
include/dt-bindings/clock/sun50i-h616-ccu.h | 115 ++
include/dt-bindings/reset/sun50i-h616-ccu.h | 70 ++
6 files changed, 1397 insertions(+)
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.c
create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.h
create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h
create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index feeb8d2074ee..cd46d8853876 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -32,6 +32,11 @@ config SUN50I_H6_CCU
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+config SUN50I_H616_CCU
+ bool "Support for the Allwinner H616 CCU"
+ default ARM64 && ARCH_SUNXI
+ depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+
config SUN50I_H6_R_CCU
bool "Support for the Allwinner H6 and H616 PRCM CCU"
default ARM64 && ARCH_SUNXI
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 3eb5cff40eac..96c324306d97 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
obj-$(CONFIG_SUN50I_A100_CCU) += ccu-sun50i-a100.o
obj-$(CONFIG_SUN50I_A100_R_CCU)+= ccu-sun50i-a100-r.o
obj-$(CONFIG_SUN50I_H6_CCU)+= ccu-sun50i-h6.o
+obj-$(CONFIG_SUN50I_H616_CCU) += ccu-sun50i-h616.o
obj-$(CONFIG_SUN50I_H6_R_CCU) += ccu-sun50i-h6-r.o
obj-$(CONFIG_SUN4I_A10_CCU)+= ccu-sun4i-a10.o
obj-$(CONFIG_SUN5I_CCU)+= ccu-sun5i.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
new file mode 100644
index ..225307305880
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
@@ -0,0 +1,1150 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020 Arm Ltd.
+ * Based on the H6 CCU driver, which is:
+ * Copyright (c) 2017 Icenowy Zheng
+ */
+
+#include
+#include
+#include
+#include
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+
+#include "ccu-sun50i-h616.h"
+
+/*
+ * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
+ * P should only be used for output frequencies lower than 288 MHz.
+ *
+ * For now we can just model it as a multiplier clock, and force P to /1.
+ *
+ * The M factor is present in the register's description, but not in the
+ * frequency formula, and it's documented as "M is only used for backdoor
+ * testing", so it's not modelled and then force to 0.
+ */
+#define SUN50I_H616_PLL_CPUX_REG 0x000
+static struct ccu_mult pll_cpux_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .common = {
+ .reg= 0x000,
+ .hw.init= CLK_HW_INIT("pll-cpux", "osc24M",
+ _mult_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
+
+/* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
+#define SUN50I_H616_PLL_DDR0_REG 0x010
+static struct ccu_nkmp pll_ddr0_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
+ .common = {
+ .reg= 0x010,
+ .hw.init= CLK_HW_INIT("pll-ddr0", "osc24M",
+ _nkmp_ops,
+ CLK_SET_RATE_UNGATE),
+ },
+};
+
+#define SUN50I_H616_PLL_DDR1_REG 0x018
+static struct ccu_nkmp pll_ddr1_clk = {
+ .enable = BIT(31),
+ .lock = BIT(28),
+ .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
+ .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
+ .p = _SUNXI_CCU_DIV(
[PATCH v3 10/21] dt-bindings: sram: sunxi-sram: Add H616 compatible string
The H616 adds a second EMAC clock register. We don't know about the exact SRAM properties yet, so this gets omitted for now. Signed-off-by: Andre Przywara Acked-by: Rob Herring --- .../bindings/sram/allwinner,sun4i-a10-system-control.yaml| 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml index b66a07e21d1e..1c426c211e36 100644 --- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -49,6 +49,7 @@ properties: - items: - const: allwinner,suniv-f1c100s-system-control - const: allwinner,sun4i-a10-system-control + - const: allwinner,sun50i-h616-system-control reg: maxItems: 1 -- 2.17.5
[PATCH v3 04/21] pinctrl: sunxi: Add support for the Allwinner H616 pin controller
Port A is used for an internal connection to some analogue circuitry
which looks like an AC200 IP (as in the H6), though this is not
mentioned in the manual.
Signed-off-by: Andre Przywara
---
drivers/pinctrl/sunxi/Kconfig | 5 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c | 548
3 files changed, 554 insertions(+)
create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 593293584ecc..73e88ce71a48 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -119,4 +119,9 @@ config PINCTRL_SUN50I_H6_R
default ARM64 && ARCH_SUNXI
select PINCTRL_SUNXI
+config PINCTRL_SUN50I_H616
+ bool "Support for the Allwinner H616 PIO"
+ default ARM64 && ARCH_SUNXI
+ select PINCTRL_SUNXI
+
endif
diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
index 8b7ff0dc3bdf..5359327a3c8f 100644
--- a/drivers/pinctrl/sunxi/Makefile
+++ b/drivers/pinctrl/sunxi/Makefile
@@ -23,5 +23,6 @@ obj-$(CONFIG_PINCTRL_SUN8I_V3S) +=
pinctrl-sun8i-v3s.o
obj-$(CONFIG_PINCTRL_SUN50I_H5)+= pinctrl-sun50i-h5.o
obj-$(CONFIG_PINCTRL_SUN50I_H6)+= pinctrl-sun50i-h6.o
obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o
+obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o
obj-$(CONFIG_PINCTRL_SUN9I_A80)+= pinctrl-sun9i-a80.o
obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
new file mode 100644
index ..ce1917e230f4
--- /dev/null
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
@@ -0,0 +1,548 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Allwinner H616 SoC pinctrl driver.
+ *
+ * Copyright (C) 2020 Arm Ltd.
+ * based on the H6 pinctrl driver
+ * Copyright (C) 2017 Icenowy Zheng
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "pinctrl-sunxi.h"
+
+static const struct sunxi_desc_pin h616_pins[] = {
+ /* Internal connection to the AC200 part */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
+ SUNXI_FUNCTION(0x2, "emac1")),/* ERXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
+ SUNXI_FUNCTION(0x2, "emac1")),/* ERXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
+ SUNXI_FUNCTION(0x2, "emac1")),/* ECRS_DV */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
+ SUNXI_FUNCTION(0x2, "emac1")),/* ERXERR */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
+ SUNXI_FUNCTION(0x2, "emac1")),/* ETXD1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
+ SUNXI_FUNCTION(0x2, "emac1")),/* ETXD0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
+ SUNXI_FUNCTION(0x2, "emac1")),/* ETXCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
+ SUNXI_FUNCTION(0x2, "emac1")),/* ETXEN */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
+ SUNXI_FUNCTION(0x2, "emac1")),/* EMDC */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
+ SUNXI_FUNCTION(0x2, "emac1")),/* EMDIO */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
+ SUNXI_FUNCTION(0x2, "i2c3")), /* SCK */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
+ SUNXI_FUNCTION(0x2, "i2c3")), /* SDA */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
+ SUNXI_FUNCTION(0x2, "pwm5")),
+ /* Hole */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* WE */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* DS */
+ SUNXI_FUNCTION(0x4, "spi0"), /* CLK */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PC_EINT0 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
+ SUNXI_FUNCTION(0x3, "mmc2"), /* RST */
+ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PC_EINT1 */
+ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
+ SUNXI_FUNCTION(0x0, "gpio_in"),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
+ SUNXI_FUNCTION(0x4, "spi0"),
[PATCH v3 03/21] dt-bindings: pinctrl: Add Allwinner H616 compatible strings
A new SoC, a new compatible string. Also we were too miserly with just allowing seven interrupt banks. Signed-off-by: Andre Przywara --- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml| 17 +++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index 5240487dfe50..cce63c3cc463 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -53,6 +53,8 @@ properties: - allwinner,sun50i-h5-pinctrl - allwinner,sun50i-h6-pinctrl - allwinner,sun50i-h6-r-pinctrl + - allwinner,sun50i-h616-pinctrl + - allwinner,sun50i-h616-r-pinctrl - allwinner,suniv-f1c100s-pinctrl - nextthing,gr8-pinctrl @@ -61,7 +63,7 @@ properties: interrupts: minItems: 1 -maxItems: 7 +maxItems: 8 description: One interrupt per external interrupt bank supported on the controller, sorted by bank number ascending order. @@ -91,7 +93,7 @@ properties: bank found in the controller $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 -maxItems: 5 +maxItems: 8 patternProperties: # It's pretty scary, but the basic idea is that: @@ -145,6 +147,17 @@ allOf: # boards are defining it at the moment so it would generate a lot of # warnings. + - if: + properties: +compatible: + enum: +- allwinner,sun50i-h616-pinctrl + +then: + properties: +interrupts: + minItems: 8 + - if: properties: compatible: -- 2.17.5
[PATCH v3 02/21] mmc: sunxi: add support for A100 mmc controller
From: Yangtao Li
This patch adds support for A100 MMC controller, which use word address
for internal dma.
Signed-off-by: Yangtao Li
Signed-off-by: Andre Przywara
---
drivers/mmc/host/sunxi-mmc.c | 28 +---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 6310693f2ac0..e46bb4e404a8 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -245,6 +245,7 @@ struct sunxi_idma_des {
struct sunxi_mmc_cfg {
u32 idma_des_size_bits;
+ u32 idma_des_shift;
const struct sunxi_mmc_clk_delay *clk_delays;
/* does the IP block support autocalibration? */
@@ -344,7 +345,7 @@ static int sunxi_mmc_init_host(struct sunxi_mmc_host *host)
/* Enable CEATA support */
mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
/* Set DMA descriptor list base address */
- mmc_writel(host, REG_DLBA, host->sg_dma);
+ mmc_writel(host, REG_DLBA, host->sg_dma >> host->cfg->idma_des_shift);
rval = mmc_readl(host, REG_GCTRL);
rval |= SDXC_INTERRUPT_ENABLE_BIT;
@@ -374,8 +375,10 @@ static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host
*host,
next_desc += sizeof(struct sunxi_idma_des);
pdes[i].buf_addr_ptr1 =
- cpu_to_le32(sg_dma_address(>sg[i]));
- pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc);
+ cpu_to_le32(sg_dma_address(>sg[i]) >>
+ host->cfg->idma_des_shift);
+ pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc >>
+ host->cfg->idma_des_shift);
}
pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD);
@@ -1179,6 +1182,23 @@ static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
.needs_new_timings = true,
};
+static const struct sunxi_mmc_cfg sun50i_a100_cfg = {
+ .idma_des_size_bits = 16,
+ .idma_des_shift = 2,
+ .clk_delays = NULL,
+ .can_calibrate = true,
+ .mask_data0 = true,
+ .needs_new_timings = true,
+};
+
+static const struct sunxi_mmc_cfg sun50i_a100_emmc_cfg = {
+ .idma_des_size_bits = 13,
+ .idma_des_shift = 2,
+ .clk_delays = NULL,
+ .can_calibrate = true,
+ .needs_new_timings = true,
+};
+
static const struct of_device_id sunxi_mmc_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-mmc", .data = _a10_cfg },
{ .compatible = "allwinner,sun5i-a13-mmc", .data = _a13_cfg },
@@ -1187,6 +1207,8 @@ static const struct of_device_id sunxi_mmc_of_match[] = {
{ .compatible = "allwinner,sun9i-a80-mmc", .data = _a80_cfg },
{ .compatible = "allwinner,sun50i-a64-mmc", .data = _a64_cfg },
{ .compatible = "allwinner,sun50i-a64-emmc", .data =
_a64_emmc_cfg },
+ { .compatible = "allwinner,sun50i-a100-mmc", .data = _a100_cfg },
+ { .compatible = "allwinner,sun50i-a100-emmc", .data =
_a100_emmc_cfg },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
--
2.17.5
[PATCH v3 01/21] dt-bindings: mmc: sunxi: Add Allwinner A100 and H616 compatibles
From: Yangtao Li Add binding for A100's and H616's mmc and emmc controller. Signed-off-by: Yangtao Li Signed-off-by: Andre Przywara Acked-by: Rob Herring --- .../devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 8 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml index e82c9a07b6fb..e75b3a8ba816 100644 --- a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml @@ -26,6 +26,8 @@ properties: - const: allwinner,sun9i-a80-mmc - const: allwinner,sun50i-a64-emmc - const: allwinner,sun50i-a64-mmc + - const: allwinner,sun50i-a100-emmc + - const: allwinner,sun50i-a100-mmc - items: - const: allwinner,sun8i-a83t-mmc - const: allwinner,sun7i-a20-mmc @@ -47,6 +49,12 @@ properties: - items: - const: allwinner,sun50i-h6-mmc - const: allwinner,sun50i-a64-mmc + - items: + - const: allwinner,sun50i-h616-emmc + - const: allwinner,sun50i-a100-emmc + - items: + - const: allwinner,sun50i-h616-mmc + - const: allwinner,sun50i-a100-mmc reg: maxItems: 1 -- 2.17.5
[PATCH v3 00/21] arm64: sunxi: Initial Allwinner H616 SoC support
ort - add DT binding documentation patches Andre Przywara (19): dt-bindings: pinctrl: Add Allwinner H616 compatible strings pinctrl: sunxi: Add support for the Allwinner H616 pin controller pinctrl: sunxi: Add support for the Allwinner H616-R pin controller dt-bindings: clk: sunxi-ccu: Add compatible string for Allwinner H616 clk: sunxi-ng: Add support for the Allwinner H616 R-CCU clk: sunxi-ng: Add support for the Allwinner H616 CCU mfd: axp20x: Allow AXP chips without interrupt lines dt-bindings: sram: sunxi-sram: Add H616 compatible string soc: sunxi: sram: Add support for more than one EMAC clock net: stmmac: dwmac-sun8i: Prepare for second EMAC clock register phy: sun4i-usb: Rework HCI PHY (aka. "pmu_unk1") handling dt-bindings: usb: Add H616 compatible string dt-bindings: usb: sunxi-musb: Add H616 compatible string phy: sun4i-usb: Add support for the H616 USB PHY dt-bindings: watchdog: sun4i: Add H616 compatible string dt-bindings: allwinner: Add H616 compatible strings arm64: dts: allwinner: Add Allwinner H616 .dtsi file dt-bindings: arm: sunxi: Add OrangePi Zero 2 binding arm64: dts: allwinner: Add OrangePi Zero 2 .dts Yangtao Li (2): dt-bindings: mmc: sunxi: Add Allwinner A100 and H616 compatibles mmc: sunxi: add support for A100 mmc controller .../devicetree/bindings/arm/sunxi.yaml|5 + .../clock/allwinner,sun4i-a10-ccu.yaml|2 + .../bindings/i2c/marvell,mv64xxx-i2c.yaml | 21 +- .../media/allwinner,sun4i-a10-ir.yaml | 16 +- .../bindings/mmc/allwinner,sun4i-a10-mmc.yaml |8 + .../phy/allwinner,sun8i-h3-usb-phy.yaml |4 +- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 17 +- .../bindings/rtc/allwinner,sun6i-a31-rtc.yaml |3 + .../bindings/spi/allwinner,sun6i-a31-spi.yaml |1 + .../allwinner,sun4i-a10-system-control.yaml |1 + .../usb/allwinner,sun4i-a10-musb.yaml |3 + .../watchdog/allwinner,sun4i-a10-wdt.yaml | 12 +- arch/arm64/boot/dts/allwinner/Makefile|1 + .../allwinner/sun50i-h616-orangepi-zero2.dts | 240 .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 750 +++ drivers/clk/sunxi-ng/Kconfig |7 +- drivers/clk/sunxi-ng/Makefile |1 + drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c| 48 + drivers/clk/sunxi-ng/ccu-sun50i-h616.c| 1150 + drivers/clk/sunxi-ng/ccu-sun50i-h616.h| 56 + drivers/mfd/axp20x.c | 17 +- drivers/mmc/host/sunxi-mmc.c | 28 +- .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 12 +- drivers/phy/allwinner/phy-sun4i-usb.c | 40 +- drivers/pinctrl/sunxi/Kconfig | 10 + drivers/pinctrl/sunxi/Makefile|2 + drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c | 56 + drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c | 548 drivers/soc/sunxi/sunxi_sram.c| 31 +- include/dt-bindings/clock/sun50i-h616-ccu.h | 115 ++ include/dt-bindings/reset/sun50i-h616-ccu.h | 70 + 31 files changed, 3204 insertions(+), 71 deletions(-) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun50i-h616.h create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h -- 2.17.5
[PATCH v3] clk: sunxi-ng: h6: Fix clock divider range on some clocks
While comparing clocks between the H6 and H616, some of the M factor
ranges were found to be wrong: the manual says they are only covering
two bits [1:0], but our code had "5" in the number-of-bits field.
By writing 0xff into that register in U-Boot and via FEL, it could be
confirmed that bits [4:2] are indeed masked off, so the manual is right.
Change to number of bits in the affected clock's description.
Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Andre Przywara
Reviewed-by: Jernej Skrabec
---
Splitting this off from the H616 series, since there is no dependency
to it.
drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index a26dbbdff80d..bff446b78290 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -237,7 +237,7 @@ static const char * const psi_ahb1_ahb2_parents[] = {
"osc24M", "osc32k",
static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
psi_ahb1_ahb2_parents,
0x510,
-0, 5, /* M */
+0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
@@ -246,19 +246,19 @@ static const char * const ahb3_apb1_apb2_parents[] = {
"osc24M", "osc32k",
"psi-ahb1-ahb2",
"pll-periph0" };
static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
-0, 5, /* M */
+0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
-0, 5, /* M */
+0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
-0, 5, /* M */
+0, 2, /* M */
8, 2, /* P */
24, 2, /* mux */
0);
--
2.17.5
Re: [PATCH v2 02/21] dt-bindings: pinctrl: Add Allwinner H616 compatible strings
On Mon, 14 Dec 2020 10:37:28 +0100 Maxime Ripard wrote: > On Fri, Dec 11, 2020 at 01:19:15AM +0000, Andre Przywara wrote: > > A new SoC, a new compatible string. > > Also we were too miserly with just allowing seven interrupt banks. > > > > Signed-off-by: Andre Przywara > > --- > > .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 18 > > -- 1 file changed, 16 insertions(+), 2 deletions(-) > > > > diff --git > > a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml > > b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml > > index 5240487dfe50..292b05d9ed08 100644 --- > > a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml > > +++ > > b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml > > @@ -53,6 +53,8 @@ properties: > >- allwinner,sun50i-h5-pinctrl > >- allwinner,sun50i-h6-pinctrl > >- allwinner,sun50i-h6-r-pinctrl > > + - allwinner,sun50i-h616-pinctrl > > + - allwinner,sun50i-h616-r-pinctrl > >- allwinner,suniv-f1c100s-pinctrl > >- nextthing,gr8-pinctrl > > > > @@ -61,7 +63,7 @@ properties: > > > >interrupts: > > minItems: 1 > > -maxItems: 7 > > +maxItems: 8 > > description: > >One interrupt per external interrupt bank supported on the > >controller, sorted by bank number ascending order. > > @@ -91,7 +93,7 @@ properties: > >bank found in the controller > > $ref: /schemas/types.yaml#/definitions/uint32-array > > minItems: 1 > > -maxItems: 5 > > +maxItems: 8 > > > > patternProperties: > ># It's pretty scary, but the basic idea is that: > > @@ -145,6 +147,18 @@ allOf: > ># boards are defining it at the moment so it would generate a > > lot of # warnings. > > > > + - if: > > + properties: > > +compatible: > > + enum: > > +- allwinner,sun50i-h616-pinctrl > > + > > +then: > > + properties: > > +interrupts: > > + minItems: 8 > > + maxItems: 8 > > + > > You don't need to have both if they are equals, and in this particular Mmh, but all the other compatibles have both equal, so what would be the recommended way to describe this? Just minItems? I don't find a good explanation at the moment how to handle an explicit number, other than by enumerating the items explicitly. > case we already check that the maximum is 8 so there's no need to > repeat that check here. Are you referring to the overall "maxItems: 8" above, in the 2nd hunk? While this will become redundant, this is apparently prone to changes (as only "7" would be redundant at the moment), so I would rather not rely on a global limit. Cheers, Andre.
[PATCH v6 4/5] arm64: Add support for SMCCC TRNG entropy source
The ARM architected TRNG firmware interface, described in ARM spec
DEN0098, defines an ARM SMCCC based interface to a true random number
generator, provided by firmware.
This can be discovered via the SMCCC >=v1.1 interface, and provides
up to 192 bits of entropy per call.
Hook this SMC call into arm64's arch_get_random_*() implementation,
coming to the rescue when the CPU does not implement the ARM v8.5 RNG
system registers.
For the detection, we piggy back on the PSCI/SMCCC discovery (which gives
us the conduit to use (hvc/smc)), then try to call the
ARM_SMCCC_TRNG_VERSION function, which returns -1 if this interface is
not implemented.
Signed-off-by: Andre Przywara
---
arch/arm64/include/asm/archrandom.h | 72 -
1 file changed, 61 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/include/asm/archrandom.h
b/arch/arm64/include/asm/archrandom.h
index abe07c21da8e..09e43272ccb0 100644
--- a/arch/arm64/include/asm/archrandom.h
+++ b/arch/arm64/include/asm/archrandom.h
@@ -4,13 +4,24 @@
#ifdef CONFIG_ARCH_RANDOM
+#include
#include
#include
#include
+#define ARM_SMCCC_TRNG_MIN_VERSION 0x1UL
+
+extern bool smccc_trng_available;
+
static inline bool __init smccc_probe_trng(void)
{
- return false;
+ struct arm_smccc_res res;
+
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_VERSION, );
+ if ((s32)res.a0 < 0)
+ return false;
+
+ return res.a0 >= ARM_SMCCC_TRNG_MIN_VERSION;
}
static inline bool __arm64_rndr(unsigned long *v)
@@ -43,26 +54,55 @@ static inline bool __must_check
arch_get_random_int(unsigned int *v)
static inline bool __must_check arch_get_random_seed_long(unsigned long *v)
{
+ struct arm_smccc_res res;
+
+ /*
+* We prefer the SMCCC call, since its semantics (return actual
+* hardware backed entropy) is closer to the idea behind this
+* function here than what even the RNDRSS register provides
+* (the output of a pseudo RNG freshly seeded by a TRNG).
+*/
+ if (smccc_trng_available) {
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_RND64, 64, );
+ if ((int)res.a0 >= 0) {
+ *v = res.a3;
+ return true;
+ }
+ }
+
/*
* Only support the generic interface after we have detected
* the system wide capability, avoiding complexity with the
* cpufeature code and with potential scheduling between CPUs
* with and without the feature.
*/
- if (!cpus_have_const_cap(ARM64_HAS_RNG))
- return false;
+ if (cpus_have_const_cap(ARM64_HAS_RNG) && __arm64_rndr(v))
+ return true;
- return __arm64_rndr(v);
+ return false;
}
-
static inline bool __must_check arch_get_random_seed_int(unsigned int *v)
{
+ struct arm_smccc_res res;
unsigned long val;
- bool ok = arch_get_random_seed_long();
- *v = val;
- return ok;
+ if (smccc_trng_available) {
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_RND64, 32, );
+ if ((int)res.a0 >= 0) {
+ *v = res.a3 & GENMASK(31, 0);
+ return true;
+ }
+ }
+
+ if (cpus_have_const_cap(ARM64_HAS_RNG)) {
+ if (__arm64_rndr()) {
+ *v = val;
+ return true;
+ }
+ }
+
+ return false;
}
static inline bool __init __early_cpu_has_rndr(void)
@@ -77,10 +117,20 @@ arch_get_random_seed_long_early(unsigned long *v)
{
WARN_ON(system_state != SYSTEM_BOOTING);
- if (!__early_cpu_has_rndr())
- return false;
+ if (smccc_trng_available) {
+ struct arm_smccc_res res;
+
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_RND64, 64, );
+ if ((int)res.a0 >= 0) {
+ *v = res.a3;
+ return true;
+ }
+ }
- return __arm64_rndr(v);
+ if (__early_cpu_has_rndr() && __arm64_rndr(v))
+ return true;
+
+ return false;
}
#define arch_get_random_seed_long_early arch_get_random_seed_long_early
--
2.17.1
[PATCH v6 5/5] KVM: arm64: implement the TRNG hypervisor call
From: Ard Biesheuvel
Provide a hypervisor implementation of the ARM architected TRNG firmware
interface described in ARM spec DEN0098. All function IDs are implemented,
including both 32-bit and 64-bit versions of the TRNG_RND service, which
is the centerpiece of the API.
The API is backed by the kernel's entropy pool only, to avoid guests
draining more precious direct entropy sources.
Signed-off-by: Ard Biesheuvel
[Andre: minor fixes, drop arch_get_random() usage]
Signed-off-by: Andre Przywara
---
arch/arm64/include/asm/kvm_host.h | 2 +
arch/arm64/kvm/Makefile | 2 +-
arch/arm64/kvm/hypercalls.c | 6 +++
arch/arm64/kvm/trng.c | 85 +++
4 files changed, 94 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/kvm/trng.c
diff --git a/arch/arm64/include/asm/kvm_host.h
b/arch/arm64/include/asm/kvm_host.h
index 11beda85ee7e..271c79914afd 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -748,4 +748,6 @@ bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
#define kvm_vcpu_has_pmu(vcpu) \
(test_bit(KVM_ARM_VCPU_PMU_V3, (vcpu)->arch.features))
+int kvm_trng_call(struct kvm_vcpu *vcpu);
+
#endif /* __ARM64_KVM_HOST_H__ */
diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
index 60fd181df624..8d2b9984ac36 100644
--- a/arch/arm64/kvm/Makefile
+++ b/arch/arm64/kvm/Makefile
@@ -16,7 +16,7 @@ kvm-y := $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o
$(KVM)/eventfd.o \
inject_fault.o va_layout.o handle_exit.o \
guest.o debug.o reset.o sys_regs.o \
vgic-sys-reg-v3.o fpsimd.o pmu.o \
-arch_timer.o \
+arch_timer.o trng.o\
vgic/vgic.o vgic/vgic-init.o \
vgic/vgic-irqfd.o vgic/vgic-v2.o \
vgic/vgic-v3.o vgic/vgic-v4.o \
diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c
index 25ea4ecb6449..ead21b98b620 100644
--- a/arch/arm64/kvm/hypercalls.c
+++ b/arch/arm64/kvm/hypercalls.c
@@ -71,6 +71,12 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu)
if (gpa != GPA_INVALID)
val = gpa;
break;
+ case ARM_SMCCC_TRNG_VERSION:
+ case ARM_SMCCC_TRNG_FEATURES:
+ case ARM_SMCCC_TRNG_GET_UUID:
+ case ARM_SMCCC_TRNG_RND32:
+ case ARM_SMCCC_TRNG_RND64:
+ return kvm_trng_call(vcpu);
default:
return kvm_psci_call(vcpu);
}
diff --git a/arch/arm64/kvm/trng.c b/arch/arm64/kvm/trng.c
new file mode 100644
index ..99bdd7103c9c
--- /dev/null
+++ b/arch/arm64/kvm/trng.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2020 Arm Ltd.
+
+#include
+#include
+
+#include
+
+#include
+
+#define ARM_SMCCC_TRNG_VERSION_1_0 0x1UL
+
+/* Those values are deliberately separate from the generic SMCCC definitions.
*/
+#define TRNG_SUCCESS 0UL
+#define TRNG_NOT_SUPPORTED ((unsigned long)-1)
+#define TRNG_INVALID_PARAMETER ((unsigned long)-2)
+#define TRNG_NO_ENTROPY((unsigned long)-3)
+
+#define TRNG_MAX_BITS64192
+
+static const uuid_t arm_smc_trng_uuid __aligned(4) = UUID_INIT(
+ 0x0d21e000, 0x4384, 0x11eb, 0x80, 0x70, 0x52, 0x44, 0x55, 0x4e, 0x5a,
0x4c);
+
+static int kvm_trng_do_rnd(struct kvm_vcpu *vcpu, int size)
+{
+ DECLARE_BITMAP(bits, TRNG_MAX_BITS64);
+ u32 num_bits = smccc_get_arg1(vcpu);
+ int i;
+
+ if (num_bits > 3 * size) {
+ smccc_set_retval(vcpu, TRNG_INVALID_PARAMETER, 0, 0, 0);
+ return 1;
+ }
+
+ /* get as many bits as we need to fulfil the request */
+ for (i = 0; i < DIV_ROUND_UP(num_bits, BITS_PER_LONG); i++)
+ bits[i] = get_random_long();
+
+ bitmap_clear(bits, num_bits, TRNG_MAX_BITS64 - num_bits);
+
+ if (size == 32)
+ smccc_set_retval(vcpu, TRNG_SUCCESS, lower_32_bits(bits[1]),
+upper_32_bits(bits[0]),
lower_32_bits(bits[0]));
+ else
+ smccc_set_retval(vcpu, TRNG_SUCCESS, bits[2], bits[1], bits[0]);
+
+ memzero_explicit(bits, sizeof(bits));
+ return 1;
+}
+
+int kvm_trng_call(struct kvm_vcpu *vcpu)
+{
+ const __le32 *u = (__le32 *)arm_smc_trng_uuid.b;
+ u32 func_id = smccc_get_function(vcpu);
+ unsigned long val = TRNG_NOT_SUPPORTED;
+ int size = 64;
+
+ switch (func_id) {
+ case ARM_SMCCC_TRNG_VERSION:
+ val = ARM_SMCCC_TRNG_VERSION_1_0;
+ break;
+ case ARM_SMCCC_TRNG_FEATURES:
+ switch (smccc_get_arg1(vcpu)) {
+ case ARM_SMCCC_TRNG_VERSION:
+ case ARM_SMCCC_TRNG_FEATURES:
+ case ARM_SMCCC_TRNG_GET_UUID:
+ case ARM_SMCCC_TRNG_RND32:
+ case ARM_SMCCC_TRNG_RND64:
+
[PATCH v6 3/5] ARM: implement support for SMCCC TRNG entropy source
From: Ard Biesheuvel
Implement arch_get_random_seed_*() for ARM based on the firmware
or hypervisor provided entropy source described in ARM DEN0098.
This will make the kernel's random number generator consume entropy
provided by this interface, at early boot, and periodically at
runtime when reseeding.
Cc: Linus Walleij
Cc: Russell King
Signed-off-by: Ard Biesheuvel
[Andre: rework to be initialised by the SMCCC firmware driver]
Signed-off-by: Andre Przywara
Reviewed-by: Linus Walleij
---
arch/arm/Kconfig | 4 ++
arch/arm/include/asm/archrandom.h | 64 +++
2 files changed, 68 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 138248999df7..bfe642510b0a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1644,6 +1644,10 @@ config STACKPROTECTOR_PER_TASK
Enable this option to switch to a different method that uses a
different canary value for each task.
+config ARCH_RANDOM
+ def_bool y
+ depends on HAVE_ARM_SMCCC_DISCOVERY
+
endmenu
menu "Boot options"
diff --git a/arch/arm/include/asm/archrandom.h
b/arch/arm/include/asm/archrandom.h
index a8e84ca5c2ee..f3e96a5b65f8 100644
--- a/arch/arm/include/asm/archrandom.h
+++ b/arch/arm/include/asm/archrandom.h
@@ -2,9 +2,73 @@
#ifndef _ASM_ARCHRANDOM_H
#define _ASM_ARCHRANDOM_H
+#ifdef CONFIG_ARCH_RANDOM
+
+#include
+#include
+
+#define ARM_SMCCC_TRNG_MIN_VERSION 0x1UL
+
+extern bool smccc_trng_available;
+
+static inline bool __init smccc_probe_trng(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_VERSION, );
+ if ((s32)res.a0 < 0)
+ return false;
+ if (res.a0 >= ARM_SMCCC_TRNG_MIN_VERSION) {
+ /* double check that the 32-bit flavor is available */
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_FEATURES,
+ARM_SMCCC_TRNG_RND32,
+);
+ if ((s32)res.a0 >= 0)
+ return true;
+ }
+
+ return false;
+}
+
+static inline bool __must_check arch_get_random_long(unsigned long *v)
+{
+ return false;
+}
+
+static inline bool __must_check arch_get_random_int(unsigned int *v)
+{
+ return false;
+}
+
+static inline bool __must_check arch_get_random_seed_long(unsigned long *v)
+{
+ struct arm_smccc_res res;
+
+ if (smccc_trng_available) {
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_RND32, 8 * sizeof(*v),
);
+
+ if (res.a0 != 0)
+ return false;
+
+ *v = res.a3;
+ return true;
+ }
+
+ return false;
+}
+
+static inline bool __must_check arch_get_random_seed_int(unsigned int *v)
+{
+ return arch_get_random_seed_long((unsigned long *)v);
+}
+
+
+#else /* !CONFIG_ARCH_RANDOM */
+
static inline bool __init smccc_probe_trng(void)
{
return false;
}
+#endif /* CONFIG_ARCH_RANDOM */
#endif /* _ASM_ARCHRANDOM_H */
--
2.17.1
[PATCH v6 2/5] firmware: smccc: Introduce SMCCC TRNG framework
The ARM DEN0098 document describe an SMCCC based firmware service to
deliver hardware generated random numbers. Its existence is advertised
according to the SMCCC v1.1 specification.
Add a (dummy) call to probe functions implemented in each architecture
(ARM and arm64), to determine the existence of this interface.
For now this return false, but this will be overwritten by each
architecture's support patch.
Signed-off-by: Andre Przywara
Reviewed-by: Linus Walleij
Reviewed-by: Sudeep Holla
---
arch/arm/include/asm/archrandom.h | 10 ++
arch/arm64/include/asm/archrandom.h | 12
drivers/firmware/smccc/smccc.c | 6 ++
3 files changed, 28 insertions(+)
create mode 100644 arch/arm/include/asm/archrandom.h
diff --git a/arch/arm/include/asm/archrandom.h
b/arch/arm/include/asm/archrandom.h
new file mode 100644
index ..a8e84ca5c2ee
--- /dev/null
+++ b/arch/arm/include/asm/archrandom.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_ARCHRANDOM_H
+#define _ASM_ARCHRANDOM_H
+
+static inline bool __init smccc_probe_trng(void)
+{
+ return false;
+}
+
+#endif /* _ASM_ARCHRANDOM_H */
diff --git a/arch/arm64/include/asm/archrandom.h
b/arch/arm64/include/asm/archrandom.h
index ffb1a40d5475..abe07c21da8e 100644
--- a/arch/arm64/include/asm/archrandom.h
+++ b/arch/arm64/include/asm/archrandom.h
@@ -8,6 +8,11 @@
#include
#include
+static inline bool __init smccc_probe_trng(void)
+{
+ return false;
+}
+
static inline bool __arm64_rndr(unsigned long *v)
{
bool ok;
@@ -79,5 +84,12 @@ arch_get_random_seed_long_early(unsigned long *v)
}
#define arch_get_random_seed_long_early arch_get_random_seed_long_early
+#else /* !CONFIG_ARCH_RANDOM */
+
+static inline bool __init smccc_probe_trng(void)
+{
+ return false;
+}
+
#endif /* CONFIG_ARCH_RANDOM */
#endif /* _ASM_ARCHRANDOM_H */
diff --git a/drivers/firmware/smccc/smccc.c b/drivers/firmware/smccc/smccc.c
index 00c88b809c0c..d52bfc5ed5e4 100644
--- a/drivers/firmware/smccc/smccc.c
+++ b/drivers/firmware/smccc/smccc.c
@@ -5,16 +5,22 @@
#define pr_fmt(fmt) "smccc: " fmt
+#include
#include
#include
+#include
static u32 smccc_version = ARM_SMCCC_VERSION_1_0;
static enum arm_smccc_conduit smccc_conduit = SMCCC_CONDUIT_NONE;
+bool __ro_after_init smccc_trng_available = false;
+
void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit)
{
smccc_version = version;
smccc_conduit = conduit;
+
+ smccc_trng_available = smccc_probe_trng();
}
enum arm_smccc_conduit arm_smccc_1_1_get_conduit(void)
--
2.17.1
[PATCH v6 1/5] firmware: smccc: Add SMCCC TRNG function call IDs
From: Ard Biesheuvel The ARM architected TRNG firmware interface, described in ARM spec DEN0098, define an ARM SMCCC based interface to a true random number generator, provided by firmware. Add the definitions of the SMCCC functions as defined by the spec. Signed-off-by: Ard Biesheuvel Signed-off-by: Andre Przywara Reviewed-by: Linus Walleij Reviewed-by: Sudeep Holla --- include/linux/arm-smccc.h | 31 +++ 1 file changed, 31 insertions(+) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index f860645f6512..62c54234576c 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -102,6 +102,37 @@ ARM_SMCCC_OWNER_STANDARD_HYP,\ 0x21) +/* TRNG entropy source calls (defined by ARM DEN0098) */ +#define ARM_SMCCC_TRNG_VERSION \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32,\ + ARM_SMCCC_OWNER_STANDARD,\ + 0x50) + +#define ARM_SMCCC_TRNG_FEATURES\ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32,\ + ARM_SMCCC_OWNER_STANDARD,\ + 0x51) + +#define ARM_SMCCC_TRNG_GET_UUID\ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32,\ + ARM_SMCCC_OWNER_STANDARD,\ + 0x52) + +#define ARM_SMCCC_TRNG_RND32 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32,\ + ARM_SMCCC_OWNER_STANDARD,\ + 0x53) + +#define ARM_SMCCC_TRNG_RND64 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64,\ + ARM_SMCCC_OWNER_STANDARD,\ + 0x53) + /* * Return codes defined in ARM DEN 0070A * ARM DEN 0070A is now merged/consolidated into ARM DEN 0028 C -- 2.17.1
[PATCH v6 0/5] ARM: arm64: Add SMCCC TRNG entropy service
Hi, a fix to v5, now *really* fixing the wrong priority of SMCCC vs. RNDR in arch_get_random_seed_long_early(). Apologies for messing this up in v5 and thanks to broonie for being on the watch! Will, Catalin: it would be much appreciated if you could consider taking patch 1/5. This contains the common definitions, and is a prerequisite for every other patch, although they are somewhat independent and likely will need to go through different subsystems. Cheers, Andre == The ARM architected TRNG firmware interface, described in ARM spec DEN0098[1], defines an ARM SMCCC based interface to a true random number generator, provided by firmware. This series collects all the patches implementing this in various places: as a user feeding into the ARCH_RANDOM pool, both for ARM and arm64, and as a service provider for KVM guests. Patch 1 introduces the interface definition used by all three entities. Patch 2 prepares the Arm SMCCC firmware driver to probe for the interface. This patch is needed to avoid a later dependency on *two* patches (there might be a better solution to this problem). Patch 3 implements the ARM part, patch 4 is the arm64 version. The final patch 5 adds support to provide random numbers to KVM guests. This was tested on: - QEMU -kernel (no SMCCC, regression test) - Juno w/ prototype of the h/w Trusted RNG support - mainline KVM (SMCCC, but no TRNG: regression test) - ARM and arm64 KVM guests, using the KVM service in patch 5/5 Based on v5.11-rc2, please let me know if I should rebase it on something else. A git repo is accessible at: https://gitlab.arm.com/linux-arm/linux-ap/-/commits/smccc-trng/v6/ Cheers, Andre [1] https://developer.arm.com/documentation/den0098/latest/ Changelog v5 ... v6: - *really* fixing order of SMCCC vs. RNDR call in the *_early() version Changelog v4 ... v5: - change order of SMCCC call vs. RNDR call in arch_get_random_seed_long_early - adding Sudeep's R-b: tags Changelog v3 ... v4: - include cache.h to always have __ro_after_init defined - change order of SMCCC call vs. RNDR call in arm64's archrandom.h - adding LinusW's R-b: tags Changelog v2 ... v3: - ARM: fix compilation with randconfig - arm64: use SMCCC call also in arch_get_random_seed_long_early() - KVM: comment on return value usage - KVM: use more interesting UUID (enjoy, Marc!) - KVM: use bitmaps instead of open coded long arrays - KVM: drop direct usage of arch_get_random() interface Changelog "v1" ... v2: - trigger ARCH_RANDOM initialisation from the SMCCC firmware driver - use a single bool in smccc.c to hold the initialisation state for arm64 - handle endianess correctly in the KVM provider Andre Przywara (2): firmware: smccc: Introduce SMCCC TRNG framework arm64: Add support for SMCCC TRNG entropy source Ard Biesheuvel (3): firmware: smccc: Add SMCCC TRNG function call IDs ARM: implement support for SMCCC TRNG entropy source KVM: arm64: implement the TRNG hypervisor call arch/arm/Kconfig| 4 ++ arch/arm/include/asm/archrandom.h | 74 + arch/arm64/include/asm/archrandom.h | 82 arch/arm64/include/asm/kvm_host.h | 2 + arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/hypercalls.c | 6 ++ arch/arm64/kvm/trng.c | 85 + drivers/firmware/smccc/smccc.c | 6 ++ include/linux/arm-smccc.h | 31 +++ 9 files changed, 281 insertions(+), 11 deletions(-) create mode 100644 arch/arm/include/asm/archrandom.h create mode 100644 arch/arm64/kvm/trng.c -- 2.17.1 *** BLURB HERE *** Andre Przywara (2): firmware: smccc: Introduce SMCCC TRNG framework arm64: Add support for SMCCC TRNG entropy source Ard Biesheuvel (3): firmware: smccc: Add SMCCC TRNG function call IDs ARM: implement support for SMCCC TRNG entropy source KVM: arm64: implement the TRNG hypervisor call arch/arm/Kconfig| 4 ++ arch/arm/include/asm/archrandom.h | 74 + arch/arm64/include/asm/archrandom.h | 82 arch/arm64/include/asm/kvm_host.h | 2 + arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/hypercalls.c | 6 ++ arch/arm64/kvm/trng.c | 85 + drivers/firmware/smccc/smccc.c | 6 ++ include/linux/arm-smccc.h | 31 +++ 9 files changed, 281 insertions(+), 11 deletions(-) create mode 100644 arch/arm/include/asm/archrandom.h create mode 100644 arch/arm64/kvm/trng.c -- 2.17.1
Re: [PATCH v5 4/5] arm64: Add support for SMCCC TRNG entropy source
On Tue, 5 Jan 2021 17:00:14 +
Mark Brown wrote:
> On Tue, Jan 05, 2021 at 04:36:51PM +0000, Andre Przywara wrote:
>
> > @@ -77,10 +117,20 @@ arch_get_random_seed_long_early(unsigned long
> > *v) {
> > WARN_ON(system_state != SYSTEM_BOOTING);
> >
> > - if (!__early_cpu_has_rndr())
> > - return false;
> > + if (__early_cpu_has_rndr())
> > + return __arm64_rndr(v);
> > +
> > + if (smccc_trng_available) {
> > + struct arm_smccc_res res;
>
> This still seems to be preferring RNDR over SMCCC for the early seed
> unless I'm misreading the diff?
Argh, my apologies for that blunder. I *did* change it, but must have
lost it when rebasing against my debug patches.
Will send a fixed version in a jiffy.
Cheers,
Andre.
[PATCH v5 5/5] KVM: arm64: implement the TRNG hypervisor call
From: Ard Biesheuvel
Provide a hypervisor implementation of the ARM architected TRNG firmware
interface described in ARM spec DEN0098. All function IDs are implemented,
including both 32-bit and 64-bit versions of the TRNG_RND service, which
is the centerpiece of the API.
The API is backed by the kernel's entropy pool only, to avoid guests
draining more precious direct entropy sources.
Signed-off-by: Ard Biesheuvel
[Andre: minor fixes, drop arch_get_random() usage]
Signed-off-by: Andre Przywara
---
arch/arm64/include/asm/kvm_host.h | 2 +
arch/arm64/kvm/Makefile | 2 +-
arch/arm64/kvm/hypercalls.c | 6 +++
arch/arm64/kvm/trng.c | 85 +++
4 files changed, 94 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/kvm/trng.c
diff --git a/arch/arm64/include/asm/kvm_host.h
b/arch/arm64/include/asm/kvm_host.h
index 11beda85ee7e..271c79914afd 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -748,4 +748,6 @@ bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu);
#define kvm_vcpu_has_pmu(vcpu) \
(test_bit(KVM_ARM_VCPU_PMU_V3, (vcpu)->arch.features))
+int kvm_trng_call(struct kvm_vcpu *vcpu);
+
#endif /* __ARM64_KVM_HOST_H__ */
diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
index 60fd181df624..8d2b9984ac36 100644
--- a/arch/arm64/kvm/Makefile
+++ b/arch/arm64/kvm/Makefile
@@ -16,7 +16,7 @@ kvm-y := $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o
$(KVM)/eventfd.o \
inject_fault.o va_layout.o handle_exit.o \
guest.o debug.o reset.o sys_regs.o \
vgic-sys-reg-v3.o fpsimd.o pmu.o \
-arch_timer.o \
+arch_timer.o trng.o\
vgic/vgic.o vgic/vgic-init.o \
vgic/vgic-irqfd.o vgic/vgic-v2.o \
vgic/vgic-v3.o vgic/vgic-v4.o \
diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c
index 25ea4ecb6449..ead21b98b620 100644
--- a/arch/arm64/kvm/hypercalls.c
+++ b/arch/arm64/kvm/hypercalls.c
@@ -71,6 +71,12 @@ int kvm_hvc_call_handler(struct kvm_vcpu *vcpu)
if (gpa != GPA_INVALID)
val = gpa;
break;
+ case ARM_SMCCC_TRNG_VERSION:
+ case ARM_SMCCC_TRNG_FEATURES:
+ case ARM_SMCCC_TRNG_GET_UUID:
+ case ARM_SMCCC_TRNG_RND32:
+ case ARM_SMCCC_TRNG_RND64:
+ return kvm_trng_call(vcpu);
default:
return kvm_psci_call(vcpu);
}
diff --git a/arch/arm64/kvm/trng.c b/arch/arm64/kvm/trng.c
new file mode 100644
index ..99bdd7103c9c
--- /dev/null
+++ b/arch/arm64/kvm/trng.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2020 Arm Ltd.
+
+#include
+#include
+
+#include
+
+#include
+
+#define ARM_SMCCC_TRNG_VERSION_1_0 0x1UL
+
+/* Those values are deliberately separate from the generic SMCCC definitions.
*/
+#define TRNG_SUCCESS 0UL
+#define TRNG_NOT_SUPPORTED ((unsigned long)-1)
+#define TRNG_INVALID_PARAMETER ((unsigned long)-2)
+#define TRNG_NO_ENTROPY((unsigned long)-3)
+
+#define TRNG_MAX_BITS64192
+
+static const uuid_t arm_smc_trng_uuid __aligned(4) = UUID_INIT(
+ 0x0d21e000, 0x4384, 0x11eb, 0x80, 0x70, 0x52, 0x44, 0x55, 0x4e, 0x5a,
0x4c);
+
+static int kvm_trng_do_rnd(struct kvm_vcpu *vcpu, int size)
+{
+ DECLARE_BITMAP(bits, TRNG_MAX_BITS64);
+ u32 num_bits = smccc_get_arg1(vcpu);
+ int i;
+
+ if (num_bits > 3 * size) {
+ smccc_set_retval(vcpu, TRNG_INVALID_PARAMETER, 0, 0, 0);
+ return 1;
+ }
+
+ /* get as many bits as we need to fulfil the request */
+ for (i = 0; i < DIV_ROUND_UP(num_bits, BITS_PER_LONG); i++)
+ bits[i] = get_random_long();
+
+ bitmap_clear(bits, num_bits, TRNG_MAX_BITS64 - num_bits);
+
+ if (size == 32)
+ smccc_set_retval(vcpu, TRNG_SUCCESS, lower_32_bits(bits[1]),
+upper_32_bits(bits[0]),
lower_32_bits(bits[0]));
+ else
+ smccc_set_retval(vcpu, TRNG_SUCCESS, bits[2], bits[1], bits[0]);
+
+ memzero_explicit(bits, sizeof(bits));
+ return 1;
+}
+
+int kvm_trng_call(struct kvm_vcpu *vcpu)
+{
+ const __le32 *u = (__le32 *)arm_smc_trng_uuid.b;
+ u32 func_id = smccc_get_function(vcpu);
+ unsigned long val = TRNG_NOT_SUPPORTED;
+ int size = 64;
+
+ switch (func_id) {
+ case ARM_SMCCC_TRNG_VERSION:
+ val = ARM_SMCCC_TRNG_VERSION_1_0;
+ break;
+ case ARM_SMCCC_TRNG_FEATURES:
+ switch (smccc_get_arg1(vcpu)) {
+ case ARM_SMCCC_TRNG_VERSION:
+ case ARM_SMCCC_TRNG_FEATURES:
+ case ARM_SMCCC_TRNG_GET_UUID:
+ case ARM_SMCCC_TRNG_RND32:
+ case ARM_SMCCC_TRNG_RND64:
+
[PATCH v5 4/5] arm64: Add support for SMCCC TRNG entropy source
The ARM architected TRNG firmware interface, described in ARM spec
DEN0098, defines an ARM SMCCC based interface to a true random number
generator, provided by firmware.
This can be discovered via the SMCCC >=v1.1 interface, and provides
up to 192 bits of entropy per call.
Hook this SMC call into arm64's arch_get_random_*() implementation,
coming to the rescue when the CPU does not implement the ARM v8.5 RNG
system registers.
For the detection, we piggy back on the PSCI/SMCCC discovery (which gives
us the conduit to use (hvc/smc)), then try to call the
ARM_SMCCC_TRNG_VERSION function, which returns -1 if this interface is
not implemented.
Signed-off-by: Andre Przywara
---
arch/arm64/include/asm/archrandom.h | 72 -
1 file changed, 61 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/include/asm/archrandom.h
b/arch/arm64/include/asm/archrandom.h
index abe07c21da8e..e188228b2bcc 100644
--- a/arch/arm64/include/asm/archrandom.h
+++ b/arch/arm64/include/asm/archrandom.h
@@ -4,13 +4,24 @@
#ifdef CONFIG_ARCH_RANDOM
+#include
#include
#include
#include
+#define ARM_SMCCC_TRNG_MIN_VERSION 0x1UL
+
+extern bool smccc_trng_available;
+
static inline bool __init smccc_probe_trng(void)
{
- return false;
+ struct arm_smccc_res res;
+
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_VERSION, );
+ if ((s32)res.a0 < 0)
+ return false;
+
+ return res.a0 >= ARM_SMCCC_TRNG_MIN_VERSION;
}
static inline bool __arm64_rndr(unsigned long *v)
@@ -43,26 +54,55 @@ static inline bool __must_check
arch_get_random_int(unsigned int *v)
static inline bool __must_check arch_get_random_seed_long(unsigned long *v)
{
+ struct arm_smccc_res res;
+
+ /*
+* We prefer the SMCCC call, since its semantics (return actual
+* hardware backed entropy) is closer to the idea behind this
+* function here than what even the RNDRSS register provides
+* (the output of a pseudo RNG freshly seeded by a TRNG).
+*/
+ if (smccc_trng_available) {
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_RND64, 64, );
+ if ((int)res.a0 >= 0) {
+ *v = res.a3;
+ return true;
+ }
+ }
+
/*
* Only support the generic interface after we have detected
* the system wide capability, avoiding complexity with the
* cpufeature code and with potential scheduling between CPUs
* with and without the feature.
*/
- if (!cpus_have_const_cap(ARM64_HAS_RNG))
- return false;
+ if (cpus_have_const_cap(ARM64_HAS_RNG))
+ return __arm64_rndr(v);
- return __arm64_rndr(v);
+ return false;
}
-
static inline bool __must_check arch_get_random_seed_int(unsigned int *v)
{
+ struct arm_smccc_res res;
unsigned long val;
- bool ok = arch_get_random_seed_long();
- *v = val;
- return ok;
+ if (smccc_trng_available) {
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_RND64, 32, );
+ if ((int)res.a0 >= 0) {
+ *v = res.a3 & GENMASK(31, 0);
+ return true;
+ }
+ }
+
+ if (cpus_have_const_cap(ARM64_HAS_RNG)) {
+ if (__arm64_rndr()) {
+ *v = val;
+ return true;
+ }
+ }
+
+ return false;
}
static inline bool __init __early_cpu_has_rndr(void)
@@ -77,10 +117,20 @@ arch_get_random_seed_long_early(unsigned long *v)
{
WARN_ON(system_state != SYSTEM_BOOTING);
- if (!__early_cpu_has_rndr())
- return false;
+ if (__early_cpu_has_rndr())
+ return __arm64_rndr(v);
+
+ if (smccc_trng_available) {
+ struct arm_smccc_res res;
- return __arm64_rndr(v);
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_RND64, 64, );
+ if ((int)res.a0 >= 0) {
+ *v = res.a3;
+ return true;
+ }
+ }
+
+ return false;
}
#define arch_get_random_seed_long_early arch_get_random_seed_long_early
--
2.17.1
[PATCH v5 3/5] ARM: implement support for SMCCC TRNG entropy source
From: Ard Biesheuvel
Implement arch_get_random_seed_*() for ARM based on the firmware
or hypervisor provided entropy source described in ARM DEN0098.
This will make the kernel's random number generator consume entropy
provided by this interface, at early boot, and periodically at
runtime when reseeding.
Cc: Linus Walleij
Cc: Russell King
Signed-off-by: Ard Biesheuvel
[Andre: rework to be initialised by the SMCCC firmware driver]
Signed-off-by: Andre Przywara
Reviewed-by: Linus Walleij
---
arch/arm/Kconfig | 4 ++
arch/arm/include/asm/archrandom.h | 64 +++
2 files changed, 68 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 138248999df7..bfe642510b0a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1644,6 +1644,10 @@ config STACKPROTECTOR_PER_TASK
Enable this option to switch to a different method that uses a
different canary value for each task.
+config ARCH_RANDOM
+ def_bool y
+ depends on HAVE_ARM_SMCCC_DISCOVERY
+
endmenu
menu "Boot options"
diff --git a/arch/arm/include/asm/archrandom.h
b/arch/arm/include/asm/archrandom.h
index a8e84ca5c2ee..f3e96a5b65f8 100644
--- a/arch/arm/include/asm/archrandom.h
+++ b/arch/arm/include/asm/archrandom.h
@@ -2,9 +2,73 @@
#ifndef _ASM_ARCHRANDOM_H
#define _ASM_ARCHRANDOM_H
+#ifdef CONFIG_ARCH_RANDOM
+
+#include
+#include
+
+#define ARM_SMCCC_TRNG_MIN_VERSION 0x1UL
+
+extern bool smccc_trng_available;
+
+static inline bool __init smccc_probe_trng(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_VERSION, );
+ if ((s32)res.a0 < 0)
+ return false;
+ if (res.a0 >= ARM_SMCCC_TRNG_MIN_VERSION) {
+ /* double check that the 32-bit flavor is available */
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_FEATURES,
+ARM_SMCCC_TRNG_RND32,
+);
+ if ((s32)res.a0 >= 0)
+ return true;
+ }
+
+ return false;
+}
+
+static inline bool __must_check arch_get_random_long(unsigned long *v)
+{
+ return false;
+}
+
+static inline bool __must_check arch_get_random_int(unsigned int *v)
+{
+ return false;
+}
+
+static inline bool __must_check arch_get_random_seed_long(unsigned long *v)
+{
+ struct arm_smccc_res res;
+
+ if (smccc_trng_available) {
+ arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_RND32, 8 * sizeof(*v),
);
+
+ if (res.a0 != 0)
+ return false;
+
+ *v = res.a3;
+ return true;
+ }
+
+ return false;
+}
+
+static inline bool __must_check arch_get_random_seed_int(unsigned int *v)
+{
+ return arch_get_random_seed_long((unsigned long *)v);
+}
+
+
+#else /* !CONFIG_ARCH_RANDOM */
+
static inline bool __init smccc_probe_trng(void)
{
return false;
}
+#endif /* CONFIG_ARCH_RANDOM */
#endif /* _ASM_ARCHRANDOM_H */
--
2.17.1
[PATCH v5 2/5] firmware: smccc: Introduce SMCCC TRNG framework
The ARM DEN0098 document describe an SMCCC based firmware service to
deliver hardware generated random numbers. Its existence is advertised
according to the SMCCC v1.1 specification.
Add a (dummy) call to probe functions implemented in each architecture
(ARM and arm64), to determine the existence of this interface.
For now this return false, but this will be overwritten by each
architecture's support patch.
Signed-off-by: Andre Przywara
Reviewed-by: Linus Walleij
Reviewed-by: Sudeep Holla
---
arch/arm/include/asm/archrandom.h | 10 ++
arch/arm64/include/asm/archrandom.h | 12
drivers/firmware/smccc/smccc.c | 6 ++
3 files changed, 28 insertions(+)
create mode 100644 arch/arm/include/asm/archrandom.h
diff --git a/arch/arm/include/asm/archrandom.h
b/arch/arm/include/asm/archrandom.h
new file mode 100644
index ..a8e84ca5c2ee
--- /dev/null
+++ b/arch/arm/include/asm/archrandom.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_ARCHRANDOM_H
+#define _ASM_ARCHRANDOM_H
+
+static inline bool __init smccc_probe_trng(void)
+{
+ return false;
+}
+
+#endif /* _ASM_ARCHRANDOM_H */
diff --git a/arch/arm64/include/asm/archrandom.h
b/arch/arm64/include/asm/archrandom.h
index ffb1a40d5475..abe07c21da8e 100644
--- a/arch/arm64/include/asm/archrandom.h
+++ b/arch/arm64/include/asm/archrandom.h
@@ -8,6 +8,11 @@
#include
#include
+static inline bool __init smccc_probe_trng(void)
+{
+ return false;
+}
+
static inline bool __arm64_rndr(unsigned long *v)
{
bool ok;
@@ -79,5 +84,12 @@ arch_get_random_seed_long_early(unsigned long *v)
}
#define arch_get_random_seed_long_early arch_get_random_seed_long_early
+#else /* !CONFIG_ARCH_RANDOM */
+
+static inline bool __init smccc_probe_trng(void)
+{
+ return false;
+}
+
#endif /* CONFIG_ARCH_RANDOM */
#endif /* _ASM_ARCHRANDOM_H */
diff --git a/drivers/firmware/smccc/smccc.c b/drivers/firmware/smccc/smccc.c
index 00c88b809c0c..d52bfc5ed5e4 100644
--- a/drivers/firmware/smccc/smccc.c
+++ b/drivers/firmware/smccc/smccc.c
@@ -5,16 +5,22 @@
#define pr_fmt(fmt) "smccc: " fmt
+#include
#include
#include
+#include
static u32 smccc_version = ARM_SMCCC_VERSION_1_0;
static enum arm_smccc_conduit smccc_conduit = SMCCC_CONDUIT_NONE;
+bool __ro_after_init smccc_trng_available = false;
+
void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit)
{
smccc_version = version;
smccc_conduit = conduit;
+
+ smccc_trng_available = smccc_probe_trng();
}
enum arm_smccc_conduit arm_smccc_1_1_get_conduit(void)
--
2.17.1
[PATCH v5 1/5] firmware: smccc: Add SMCCC TRNG function call IDs
From: Ard Biesheuvel The ARM architected TRNG firmware interface, described in ARM spec DEN0098, define an ARM SMCCC based interface to a true random number generator, provided by firmware. Add the definitions of the SMCCC functions as defined by the spec. Signed-off-by: Ard Biesheuvel Signed-off-by: Andre Przywara Reviewed-by: Linus Walleij Reviewed-by: Sudeep Holla --- include/linux/arm-smccc.h | 31 +++ 1 file changed, 31 insertions(+) diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h index f860645f6512..62c54234576c 100644 --- a/include/linux/arm-smccc.h +++ b/include/linux/arm-smccc.h @@ -102,6 +102,37 @@ ARM_SMCCC_OWNER_STANDARD_HYP,\ 0x21) +/* TRNG entropy source calls (defined by ARM DEN0098) */ +#define ARM_SMCCC_TRNG_VERSION \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32,\ + ARM_SMCCC_OWNER_STANDARD,\ + 0x50) + +#define ARM_SMCCC_TRNG_FEATURES\ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32,\ + ARM_SMCCC_OWNER_STANDARD,\ + 0x51) + +#define ARM_SMCCC_TRNG_GET_UUID\ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32,\ + ARM_SMCCC_OWNER_STANDARD,\ + 0x52) + +#define ARM_SMCCC_TRNG_RND32 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_32,\ + ARM_SMCCC_OWNER_STANDARD,\ + 0x53) + +#define ARM_SMCCC_TRNG_RND64 \ + ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \ + ARM_SMCCC_SMC_64,\ + ARM_SMCCC_OWNER_STANDARD,\ + 0x53) + /* * Return codes defined in ARM DEN 0070A * ARM DEN 0070A is now merged/consolidated into ARM DEN 0028 C -- 2.17.1
[PATCH v5 0/5] ARM: arm64: Add SMCCC TRNG entropy service
Hi, a small update to v4, also observing the priority of SMCCC vs. RNDR in the early version of the function (as reported by broonie). Plus adding review tags and rebasing on v5.11-rc2. Changelog below. Will, Catalin: it would be much appreciated if you could consider taking patch 1/5. This contains the common definitions, and is a prerequisite for every other patch, although they are somewhat independent and likely will need to go through different subsystems. Cheers, Andre == The ARM architected TRNG firmware interface, described in ARM spec DEN0098[1], defines an ARM SMCCC based interface to a true random number generator, provided by firmware. This series collects all the patches implementing this in various places: as a user feeding into the ARCH_RANDOM pool, both for ARM and arm64, and as a service provider for KVM guests. Patch 1 introduces the interface definition used by all three entities. Patch 2 prepares the Arm SMCCC firmware driver to probe for the interface. This patch is needed to avoid a later dependency on *two* patches (there might be a better solution to this problem). Patch 3 implements the ARM part, patch 4 is the arm64 version. The final patch 5 adds support to provide random numbers to KVM guests. This was tested on: - QEMU -kernel (no SMCCC, regression test) - Juno w/ prototype of the h/w Trusted RNG support - mainline KVM (SMCCC, but no TRNG: regression test) - ARM and arm64 KVM guests, using the KVM service in patch 5/5 Based on v5.11-rc2, please let me know if I should rebase it on something else. A git repo is accessible at: https://gitlab.arm.com/linux-arm/linux-ap/-/commits/smccc-trng/v5/ Cheers, Andre [1] https://developer.arm.com/documentation/den0098/latest/ Changelog v4 ... v5: - change order of SMCCC call vs. RNDR call in arch_get_random_seed_long_early - adding Sudeep's R-b: tags Changelog v3 ... v4: - include cache.h to always have __ro_after_init defined - change order of SMCCC call vs. RNDR call in arm64's archrandom.h - adding LinusW's R-b: tags Changelog v2 ... v3: - ARM: fix compilation with randconfig - arm64: use SMCCC call also in arch_get_random_seed_long_early() - KVM: comment on return value usage - KVM: use more interesting UUID (enjoy, Marc!) - KVM: use bitmaps instead of open coded long arrays - KVM: drop direct usage of arch_get_random() interface Changelog "v1" ... v2: - trigger ARCH_RANDOM initialisation from the SMCCC firmware driver - use a single bool in smccc.c to hold the initialisation state for arm64 - handle endianess correctly in the KVM provider Andre Przywara (2): firmware: smccc: Introduce SMCCC TRNG framework arm64: Add support for SMCCC TRNG entropy source Ard Biesheuvel (3): firmware: smccc: Add SMCCC TRNG function call IDs ARM: implement support for SMCCC TRNG entropy source KVM: arm64: implement the TRNG hypervisor call arch/arm/Kconfig| 4 ++ arch/arm/include/asm/archrandom.h | 74 + arch/arm64/include/asm/archrandom.h | 82 arch/arm64/include/asm/kvm_host.h | 2 + arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/hypercalls.c | 6 ++ arch/arm64/kvm/trng.c | 85 + drivers/firmware/smccc/smccc.c | 6 ++ include/linux/arm-smccc.h | 31 +++ 9 files changed, 281 insertions(+), 11 deletions(-) create mode 100644 arch/arm/include/asm/archrandom.h create mode 100644 arch/arm64/kvm/trng.c -- 2.17.1
Re: [PATCH v4 4/5] arm64: Add support for SMCCC TRNG entropy source
On Fri, 11 Dec 2020 16:26:12 +
Mark Brown wrote:
> On Fri, Dec 11, 2020 at 04:00:04PM +0000, Andre Przywara wrote:
>
> > static inline bool __must_check arch_get_random_seed_long(unsigned
> > long *v) {
> > + struct arm_smccc_res res;
> > +
> > + /*
> > +* We prefer the SMCCC call, since its semantics (return
> > actual
> > +* hardware backed entropy) is closer to the idea behind
> > this
> > +* function here than what even the RNDRSS register
> > provides
> > +* (the output of a pseudo RNG freshly seeded by a TRNG).
> > +*/
>
> This logic...
>
> > @@ -77,10 +117,20 @@ arch_get_random_seed_long_early(unsigned long
> > *v) {
> > WARN_ON(system_state != SYSTEM_BOOTING);
> >
> > - if (!__early_cpu_has_rndr())
> > - return false;
> > + if (__early_cpu_has_rndr())
> > + return __arm64_rndr(v);
> > +
> > + if (smccc_trng_available) {
> > + struct arm_smccc_res res;
> >
> > - return __arm64_rndr(v);
> > + arm_smccc_1_1_invoke(ARM_SMCCC_TRNG_RND64, 64,
> > );
> > + if ((int)res.a0 >= 0) {
> > + *v = res.a3;
> > + return true;
> > + }
> > + }
> > +
> > + return false;
>
> ...seems to also apply here but we prefer the RNDR instead of the
> SMCC. We probably want to either do the same thing or add a comment
> saying what's going on.
Argh, you are right, I missed to change this part as well.
Will send a fixed and rebased v5 ASAP.
Cheers,
Andre
Re: [PATCH v2 19/21] arm64: dts: allwinner: Add Allwinner H616 .dtsi file
On Mon, 14 Dec 2020 10:58:31 +0100
Maxime Ripard wrote:
Hi,
> On Fri, Dec 11, 2020 at 01:19:32AM +0000, Andre Przywara wrote:
> > + reserved-memory {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + /* 512KiB reserved for ARM Trusted Firmware (BL31)
> > */
> > + secmon_reserved: secmon@4000 {
> > + reg = <0x0 0x4000 0x0 0x8>;
> > + no-map;
> > + };
> > + };
>
> This should still be set by the firmware
>
> > + mmc0: mmc@402 {
> > + compatible = "allwinner,sun50i-h616-mmc",
> > +"allwinner,sun50i-a100-mmc";
> > + reg = <0x0402 0x1000>;
> > + clocks = < CLK_BUS_MMC0>, <
> > CLK_MMC0>;
> > + clock-names = "ahb", "mmc";
> > + resets = < RST_BUS_MMC0>;
> > + reset-names = "ahb";
> > + interrupts = > IRQ_TYPE_LEVEL_HIGH>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <_pins>;
> > + status = "disabled";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
>
> Somewhat related: we shouldn't set the MMC speed flags in the drivers.
> This is biting us on the already supported SoCs, so it would be great
> to not repeat the same mistake with the new ones
Do you mean to list the "sd-uhs-sdr50" and friends properties here in
the DT?
What is the best practice here in terms putting them in the .dts vs.
the .dtsi? Surely the controller has limits, but bad traces on a board
could impose further restrictions, right?
Though that's probably rare, so it sounds like a lot of churn to list
them in every board DT. So can we list everything in here (.dtsi), then
delete in those affected boards only?
Cheers,
Andre
[PATCH v4 2/5] firmware: smccc: Introduce SMCCC TRNG framework
The ARM DEN0098 document describe an SMCCC based firmware service to
deliver hardware generated random numbers. Its existence is advertised
according to the SMCCC v1.1 specification.
Add a (dummy) call to probe functions implemented in each architecture
(ARM and arm64), to determine the existence of this interface.
For now this return false, but this will be overwritten by each
architecture's support patch.
Signed-off-by: Andre Przywara
Reviewed-by: Linus Walleij
---
arch/arm/include/asm/archrandom.h | 10 ++
arch/arm64/include/asm/archrandom.h | 12
drivers/firmware/smccc/smccc.c | 6 ++
3 files changed, 28 insertions(+)
create mode 100644 arch/arm/include/asm/archrandom.h
diff --git a/arch/arm/include/asm/archrandom.h
b/arch/arm/include/asm/archrandom.h
new file mode 100644
index ..a8e84ca5c2ee
--- /dev/null
+++ b/arch/arm/include/asm/archrandom.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef _ASM_ARCHRANDOM_H
+#define _ASM_ARCHRANDOM_H
+
+static inline bool __init smccc_probe_trng(void)
+{
+ return false;
+}
+
+#endif /* _ASM_ARCHRANDOM_H */
diff --git a/arch/arm64/include/asm/archrandom.h
b/arch/arm64/include/asm/archrandom.h
index ffb1a40d5475..abe07c21da8e 100644
--- a/arch/arm64/include/asm/archrandom.h
+++ b/arch/arm64/include/asm/archrandom.h
@@ -8,6 +8,11 @@
#include
#include
+static inline bool __init smccc_probe_trng(void)
+{
+ return false;
+}
+
static inline bool __arm64_rndr(unsigned long *v)
{
bool ok;
@@ -79,5 +84,12 @@ arch_get_random_seed_long_early(unsigned long *v)
}
#define arch_get_random_seed_long_early arch_get_random_seed_long_early
+#else /* !CONFIG_ARCH_RANDOM */
+
+static inline bool __init smccc_probe_trng(void)
+{
+ return false;
+}
+
#endif /* CONFIG_ARCH_RANDOM */
#endif /* _ASM_ARCHRANDOM_H */
diff --git a/drivers/firmware/smccc/smccc.c b/drivers/firmware/smccc/smccc.c
index 00c88b809c0c..d52bfc5ed5e4 100644
--- a/drivers/firmware/smccc/smccc.c
+++ b/drivers/firmware/smccc/smccc.c
@@ -5,16 +5,22 @@
#define pr_fmt(fmt) "smccc: " fmt
+#include
#include
#include
+#include
static u32 smccc_version = ARM_SMCCC_VERSION_1_0;
static enum arm_smccc_conduit smccc_conduit = SMCCC_CONDUIT_NONE;
+bool __ro_after_init smccc_trng_available = false;
+
void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit)
{
smccc_version = version;
smccc_conduit = conduit;
+
+ smccc_trng_available = smccc_probe_trng();
}
enum arm_smccc_conduit arm_smccc_1_1_get_conduit(void)
--
2.17.1
