Re: [PATCH v2 04/13] spidev: Add Pensando CPLD compatible

2021-03-29 Thread Brad Larson 
On Mon, Mar 29, 2021 at 3:45 AM Andy Shevchenko
 wrote:
>
> On Mon, Mar 29, 2021 at 5:01 AM Brad Larson  wrote:
> >
> > Pensando Elba SoC platforms have a SPI connected CPLD
> > for platform management.
>
> And? It's not a good justification to spread the (debugging only)
> spidev interface.
>
> What tool is going to use it? Why can't you have a driver for that in
> the kernel?

The driver is in userspace and we need to instantiate /dev/spi0.N
in the /dev directory.  The CPLD includes a device id and version
id that userspace applications use to differentiate functionality on
different boards.  It wouldn't really be appropriate to use one of
the existing entries.

For example even with high pin count SoCs we are offloading
low speed functionality into the CPLD connected over SPI.  The
elba-asic-common.dtsi file shows a compatible string of
"pensando,cpld-rd1173" which does have a kernel driver we
intend to contribute later if there is interest.  This IP in the CPLD
is readily available from Lattice which provides two I2C Masters
which in our case we use for access to the network port transceivers.
What was missing in the kernel was a bridge driver that exposes
what looks like a standard I2C device to userspace where the
drivers/i2c/busses/i2c-rd1173.c handles the spi transfers to the
Lattice IP in the CPLD.

>
> --
> With Best Regards,
> Andy Shevchenko

Re: [PATCH 1/8] gpio: Add Elba SoC gpio driver for spi cs control

2021-03-29 Thread Brad Larson 
On Thu, Mar 4, 2021 at 12:29 AM Linus Walleij  wrote:
>
> Hi Brad,
>
> thanks for your patch!
>
> On Thu, Mar 4, 2021 at 4:42 AM Brad Larson  wrote:
>
> > This GPIO driver is for the Pensando Elba SoC which
> > provides control of four chip selects on two SPI busses.
> >
> > Signed-off-by: Brad Larson 
> (...)
>
> > +#include 
>
> Use this in new drivers:
> #include 
>
> > + * pin: 32|   10
> > + * bit: 7--6--5--4|---3--2--1--0
> > + * cs1  cs1_ovr  cs0  cs0_ovr |  cs1  cs1_ovr  cs0  cs0_ovr
> > + *ssi1| ssi0
> > + */
> > +#define SPICS_PIN_SHIFT(pin)   (2 * (pin))
> > +#define SPICS_MASK(pin)(0x3 << SPICS_PIN_SHIFT(pin))
> > +#define SPICS_SET(pin, val)val) << 1) | 0x1) << 
> > SPICS_PIN_SHIFT(pin))
>
> So 2 bits per GPIO line in one register? (Nice doc!)
>
> > +struct elba_spics_priv {
> > +   void __iomem *base;
> > +   spinlock_t lock;
> > +   struct gpio_chip chip;
> > +};
> > +
> > +static int elba_spics_get_value(struct gpio_chip *chip, unsigned int pin)
> > +{
> > +   return -ENXIO;
> > +}
>
> Write a comment that the chip only supports output mode,
> because it repurposes SPI CS pins as generic GPIO out,
> maybe at the top of the file?
>

I'll add a comment regarding gpio pin mode.  Yes output
only mode as SPI chip-selects.

> I suppose these systems also actually (ab)use the SPI cs
> for things that are not really SPI CS? Because otherwise
> this could just be part of the SPI driver (native chip select).
>
> > +static const struct of_device_id ebla_spics_of_match[] = {
> > +   { .compatible = "pensando,elba-spics" },
>
> Have you documented this?

Yes in Documentation/devicetree/bindings, I'll double check
the content for completeness.  The SPI CS isn't used for
something else, the integrated DesignWare IP doesn't
support 4 chip-selects on two spi busses.

>
> Other than that this is a nice and complete driver.
>
> Yours,
> Linus Walleij

Thanks for the review!

Re: [PATCH v2 03/13] spi: dw: Add support for Pensando Elba SoC SPI

2021-03-29 Thread Brad Larson 
On Mon, Mar 29, 2021 at 8:58 AM Mark Brown  wrote:
>
> On Sun, Mar 28, 2021 at 06:59:28PM -0700, Brad Larson wrote:
>
> > @@ -56,7 +56,7 @@ struct dw_spi_mscc {
> >  /*
> >   * The Designware SPI controller (referred to as master in the 
> > documentation)
> >   * automatically deasserts chip select when the tx fifo is empty. The chip
> > - * selects then needs to be either driven as GPIOs or, for the first 4 
> > using the
> > + * selects then needs to be either driven as GPIOs or, for the first 4 
> > using
> >   * the SPI boot controller registers. the final chip select is an OR gate
> >   * between the Designware SPI controller and the SPI boot controller.
> >   */
>
> This is an unrelated fix, please send as a separate patch as covered in
> submitting-patches.rst.

I'll remove this.  Belongs in a trivial patch set.

> > @@ -237,6 +237,31 @@ static int dw_spi_canaan_k210_init(struct 
> > platform_device *pdev,
> >   return 0;
> >  }
> >
> > +static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable)
> > +{
> > + struct dw_spi *dws = spi_master_get_devdata(spi->master);
> > +
> > + if (!enable) {
> > + /*
> > +  * Using a GPIO-based chip-select, the DW SPI
> > +  * controller still needs its own CS bit selected
> > +  * to start the serial engine.  On Elba the specific
> > +  * CS doesn't matter to start the serial engine,
> > +  * so using CS0.
> > +  */
>
> Why does this comment only apply to one branch of the conditional?

It doesn't, I'll move it outside the conditional.

Re: [PATCH v2 13/13] gpio: Use linux/gpio/driver.h

2021-03-29 Thread Brad Larson 
On Mon, Mar 29, 2021 at 6:44 AM Linus Walleij  wrote:
>
> On Mon, Mar 29, 2021 at 4:00 AM Brad Larson  wrote:
>
> > New drivers should include  instead
> > of legacy .
> >
> > Signed-off-by: Brad Larson 
>
> Fold into patch 1 as indicated by Greg.
>
> Yours,
> Linus Walleij

Yes, thanks for the quick review.

Re: [PATCH v2 13/13] gpio: Use linux/gpio/driver.h

2021-03-29 Thread Brad Larson 
On Sun, Mar 28, 2021 at 11:48 PM Greg KH  wrote:
>
> On Sun, Mar 28, 2021 at 06:59:38PM -0700, Brad Larson wrote:
> > New drivers should include  instead
> > of legacy .
> >
> > Signed-off-by: Brad Larson 
> > ---
> >  drivers/gpio/gpio-elba-spics.c | 3 +--
> >  1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpio/gpio-elba-spics.c b/drivers/gpio/gpio-elba-spics.c
> > index 351bbaeea033..c0dce5333f35 100644
> > --- a/drivers/gpio/gpio-elba-spics.c
> > +++ b/drivers/gpio/gpio-elba-spics.c
> > @@ -6,11 +6,10 @@
> >   */
> >
> >  #include 
> > -#include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > -//#include 
> >  #include 
> >  #include 
> >  #include 
> > --
> > 2.17.1
> >
>
> This should be part of patch 1/13, do not add a problem and then fix it
> up in the same patch series.
>
> thanks,
>
> greg k-h

Yes, thanks.  I'm laughing at myself today looking at that patch
tagged at the end.

Re: [PATCH v2 10/13] dt-bindings: spi: cadence-qspi: Add support for Pensando Elba SoC

2021-03-29 Thread Brad Larson 
On Mon, Mar 29, 2021 at 9:01 AM Mark Brown  wrote:
>
> On Sun, Mar 28, 2021 at 06:59:35PM -0700, Brad Larson wrote:
> > Add new vendor Pensando Systems Elba SoC compatible
> > string and convert to json-schema.
>
> These are two unrelated changes and should be separate patches, again as
> covered in submitting-patches.rst.  It is generally better to do the
> changes adding new stuff first and then convert to YAML as the final
> patches as the series since there is often a delay on reviews of YAML
> conversions.

The initial patch set only changed the text file and a request was made
to convert to YAML.  I'll change this particular patch to modify just the
text file as before and then the convert to YAML with a later patch in the set.

[PATCH v2 09/13] dt-bindings: mmc: Add Pensando Elba SoC binding

2021-03-28 Thread Brad Larson 
Pensando Elba ARM 64-bit SoC is integrated with this IP

Signed-off-by: Brad Larson 
---
 Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml 
b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
index af7442f73881..3e8eb3254b99 100644
--- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
@@ -18,6 +18,7 @@ properties:
 items:
   - enum:
   - socionext,uniphier-sd4hc
+  - pensando,elba-emmc
   - const: cdns,sd4hc
 
   reg:
-- 
2.17.1

[PATCH v2 05/13] mmc: sdhci-cadence: Add Pensando Elba SoC support

2021-03-28 Thread Brad Larson 
Add support for Pensando Elba SoC which explicitly controls
byte-lane enables on writes.  Refactor to allow platform
specific write ops.

Signed-off-by: Brad Larson 
---
 drivers/mmc/host/Kconfig  |  15 +++
 drivers/mmc/host/Makefile |   1 +
 drivers/mmc/host/sdhci-cadence-elba.c | 137 ++
 drivers/mmc/host/sdhci-cadence.c  |  81 ---
 drivers/mmc/host/sdhci-cadence.h  |  68 +
 5 files changed, 260 insertions(+), 42 deletions(-)
 create mode 100644 drivers/mmc/host/sdhci-cadence-elba.c
 create mode 100644 drivers/mmc/host/sdhci-cadence.h

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index b236dfe2e879..65ea323c06f2 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -250,6 +250,21 @@ config MMC_SDHCI_CADENCE
 
  If unsure, say N.
 
+config MMC_SDHCI_CADENCE_ELBA
+   tristate "SDHCI support for the Pensando/Cadence SD/SDIO/eMMC 
controller"
+   depends on ARCH_PENSANDO_ELBA_SOC
+   depends on MMC_SDHCI
+   depends on OF
+   depends on MMC_SDHCI_CADENCE
+   depends on MMC_SDHCI_PLTFM
+   select MMC_SDHCI_IO_ACCESSORS
+   help
+ This selects the Pensando/Cadence SD/SDIO/eMMC controller.
+
+ If you have a controller with this interface, say Y or M here.
+
+ If unsure, say N.
+
 config MMC_SDHCI_CNS3XXX
tristate "SDHCI support on the Cavium Networks CNS3xxx SoC"
depends on ARCH_CNS3XXX || COMPILE_TEST
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 6df5c4774260..f2a6d50e64de 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -80,6 +80,7 @@ obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o
 
 obj-$(CONFIG_MMC_SDHCI_PLTFM)  += sdhci-pltfm.o
 obj-$(CONFIG_MMC_SDHCI_CADENCE)+= sdhci-cadence.o
+obj-$(CONFIG_MMC_SDHCI_CADENCE_ELBA)   += sdhci-cadence-elba.o
 obj-$(CONFIG_MMC_SDHCI_CNS3XXX)+= sdhci-cns3xxx.o
 obj-$(CONFIG_MMC_SDHCI_ESDHC_MCF)   += sdhci-esdhc-mcf.o
 obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX)  += sdhci-esdhc-imx.o
diff --git a/drivers/mmc/host/sdhci-cadence-elba.c 
b/drivers/mmc/host/sdhci-cadence-elba.c
new file mode 100644
index ..ec23f43de407
--- /dev/null
+++ b/drivers/mmc/host/sdhci-cadence-elba.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2020 Pensando Systems, Inc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "sdhci-pltfm.h"
+#include "sdhci-cadence.h"
+
+// delay regs address
+#define SDIO_REG_HRS4  0x10
+#define REG_DELAY_HS   0x00
+#define REG_DELAY_DEFAULT  0x01
+#define REG_DELAY_UHSI_SDR50   0x04
+#define REG_DELAY_UHSI_DDR50   0x05
+
+static void elba_write_l(struct sdhci_host *host, u32 val, int reg)
+{
+   struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+   unsigned long flags;
+
+   spin_lock_irqsave(>wrlock, flags);
+   writel(0x78, priv->ctl_addr);
+   writel(val, host->ioaddr + reg);
+   spin_unlock_irqrestore(>wrlock, flags);
+}
+
+static void elba_write_w(struct sdhci_host *host, u16 val, int reg)
+{
+   struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+   unsigned long flags;
+   u32 m = (reg & 0x3);
+   u32 msk = (0x3 << (m));
+
+   spin_lock_irqsave(>wrlock, flags);
+   writel(msk << 3, priv->ctl_addr);
+   writew(val, host->ioaddr + reg);
+   spin_unlock_irqrestore(>wrlock, flags);
+}
+
+static void elba_write_b(struct sdhci_host *host, u8 val, int reg)
+{
+   struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+   unsigned long flags;
+   u32 m = (reg & 0x3);
+   u32 msk = (0x1 << (m));
+
+   spin_lock_irqsave(>wrlock, flags);
+   writel(msk << 3, priv->ctl_addr);
+   writeb(val, host->ioaddr + reg);
+   spin_unlock_irqrestore(>wrlock, flags);
+}
+
+static void elba_priv_write_l(struct sdhci_cdns_priv *priv,
+   u32 val, void __iomem *reg)
+{
+   unsigned long flags;
+
+   spin_lock_irqsave(>wrlock, flags);
+   writel(0x78, priv->ctl_addr);
+   writel(val, reg);
+   spin_unlock_irqrestore(>wrlock, flags);
+}
+
+static const struct sdhci_ops sdhci_elba_ops = {
+   .write_l = elba_write_l,
+   .write_w = elba_write_w,
+   .write_b = elba_write_b,
+   .set_clock = sdhci_set_clock,
+   .get_timeout_clock = sdhci_cdns_get_timeout_clock,
+   .set_bus_width = sdhci_set_bus_width,
+   .reset = sdhci_reset,
+   .set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
+};
+
+static void sd4_set_dlyvr(struct sdhci_host *host,
+ unsigned char addr, unsigned char data)
+{
+   unsigned long dlyrv_reg;
+
+   dlyrv_reg = ((unsigned long)data << 8);
+   dlyrv_reg |=

[PATCH v2 07/13] arm64: dts: Add Pensando Elba SoC support

2021-03-28 Thread Brad Larson 
Add Pensando common and Elba SoC specific device nodes

Signed-off-by: Brad Larson 
---
 arch/arm64/boot/dts/Makefile  |   1 +
 arch/arm64/boot/dts/pensando/Makefile |   6 +
 arch/arm64/boot/dts/pensando/elba-16core.dtsi | 170 ++
 .../boot/dts/pensando/elba-asic-common.dtsi   | 112 +++
 arch/arm64/boot/dts/pensando/elba-asic.dts|   7 +
 .../boot/dts/pensando/elba-flash-parts.dtsi   |  78 +
 arch/arm64/boot/dts/pensando/elba.dtsi| 310 ++
 7 files changed, 684 insertions(+)
 create mode 100644 arch/arm64/boot/dts/pensando/Makefile
 create mode 100644 arch/arm64/boot/dts/pensando/elba-16core.dtsi
 create mode 100644 arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
 create mode 100644 arch/arm64/boot/dts/pensando/elba-asic.dts
 create mode 100644 arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
 create mode 100644 arch/arm64/boot/dts/pensando/elba.dtsi

diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index f1173cd93594..c85db0a097fe 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -19,6 +19,7 @@ subdir-y += marvell
 subdir-y += mediatek
 subdir-y += microchip
 subdir-y += nvidia
+subdir-y += pensando
 subdir-y += qcom
 subdir-y += realtek
 subdir-y += renesas
diff --git a/arch/arm64/boot/dts/pensando/Makefile 
b/arch/arm64/boot/dts/pensando/Makefile
new file mode 100644
index ..0c2c0961e64a
--- /dev/null
+++ b/arch/arm64/boot/dts/pensando/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_PENSANDO_ELBA_SOC) += elba-asic.dtb
+
+always-y   := $(dtb-y)
+subdir-y   := $(dts-dirs)
+clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/pensando/elba-16core.dtsi 
b/arch/arm64/boot/dts/pensando/elba-16core.dtsi
new file mode 100644
index ..a6c47899b69a
--- /dev/null
+++ b/arch/arm64/boot/dts/pensando/elba-16core.dtsi
@@ -0,0 +1,170 @@
+
+/ {
+   cpus {
+   #address-cells = <2>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 { cpu = <>; };
+   core1 { cpu = <>; };
+   core2 { cpu = <>; };
+   core3 { cpu = <>; };
+   };
+   cluster1 {
+   core0 { cpu = <>; };
+   core1 { cpu = <>; };
+   core2 { cpu = <>; };
+   core3 { cpu = <>; };
+   };
+   cluster2 {
+   core0 { cpu = <>; };
+   core1 { cpu = <>; };
+   core2 { cpu = <>; };
+   core3 { cpu = <>; };
+   };
+   cluster3 {
+   core0 { cpu = <>; };
+   core1 { cpu = <>; };
+   core2 { cpu = <>; };
+   core3 { cpu = <>; };
+   };
+   };
+
+   // CLUSTER 0
+   cpu0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72", "arm,armv8";
+   reg = <0 0x0>;
+   enable-method = "spin-table";
+   next-level-cache = <_0>;
+   };
+   cpu1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72", "arm,armv8";
+   reg = <0 0x1>;
+   enable-method = "spin-table";
+   next-level-cache = <_0>;
+   };
+   cpu2: cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72", "arm,armv8";
+   reg = <0 0x2>;
+   enable-method = "spin-table";
+   next-level-cache = <_0>;
+   };
+   cpu3: cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72", "arm,armv8";
+   reg = <0 0x3>;
+   enable-method = "spin-table";
+   next-level-cache = <_0>;
+   };
+
+   l2_0: l2-cache0 {
+   compatible = "cache";
+   };
+
+   // CLUSTER 1
+   cpu4: cpu@100 {
+   device_type = "cpu";
+

[PATCH v2 11/13] dt-bindings: gpio: Add Pensando Elba SoC support

2021-03-28 Thread Brad Larson 
The Pensando Elba SoC gpio driver provides control
of four chip selects on two SPI busses.

Signed-off-by: Brad Larson 
---
 .../bindings/gpio/pensando,elba-spics.yaml| 50 +++
 1 file changed, 50 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/gpio/pensando,elba-spics.yaml

diff --git a/Documentation/devicetree/bindings/gpio/pensando,elba-spics.yaml 
b/Documentation/devicetree/bindings/gpio/pensando,elba-spics.yaml
new file mode 100644
index ..c93b481d4ad3
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/pensando,elba-spics.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/pensando,elba-spics.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Pensando Elba SPI Chip Select Driver
+
+description: |
+  The Pensando Elba SoC provides four SPI bus chip selects.
+
+maintainers:
+  - Brad Larson 
+
+properties:
+  $nodename:
+pattern: "^spics@[0-9a-f]+$"
+  
+  compatible:
+const: pensando,elba-spics
+
+  reg:
+maxItems: 1
+
+  gpio-controller: true
+
+  "#gpio-cells":
+const: 2
+
+required:
+  - compatible
+  - reg
+  - gpio-controller
+  - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+soc {
+#address-cells = <2>;
+#size-cells = <2>;
+
+spics: spics@307c2468 {
+compatible = "pensando,elba-spics";
+reg = <0x0 0x307c2468 0x0 0x4>;
+gpio-controller;
+#gpio-cells = <2>;
+};
+};
-- 
2.17.1

[PATCH v2 12/13] MAINTAINERS: Add entry for PENSANDO

2021-03-28 Thread Brad Larson 
Add entry for PENSANDO maintainer and files

Signed-off-by: Brad Larson 
---
 MAINTAINERS | 9 +
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index fb2a3633b719..272c7a7fde75 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2246,6 +2246,15 @@ S:   Maintained
 W: http://hackndev.com
 F: arch/arm/mach-pxa/palmz72.*
 
+ARM/PENSANDO SUPPORT
+M: Brad Larson 
+L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: Documentation/devicetree/bindings/*/pensando*
+F: arch/arm64/boot/dts/pensando/
+F: drivers/gpio/gpio-elba-spics.c
+F: drivers/mmc/host/sdhci-cadence-elba.c
+
 ARM/PLEB SUPPORT
 M: Peter Chubb 
 S: Maintained
-- 
2.17.1

[PATCH v2 13/13] gpio: Use linux/gpio/driver.h

2021-03-28 Thread Brad Larson 
New drivers should include  instead
of legacy .

Signed-off-by: Brad Larson 
---
 drivers/gpio/gpio-elba-spics.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpio/gpio-elba-spics.c b/drivers/gpio/gpio-elba-spics.c
index 351bbaeea033..c0dce5333f35 100644
--- a/drivers/gpio/gpio-elba-spics.c
+++ b/drivers/gpio/gpio-elba-spics.c
@@ -6,11 +6,10 @@
  */
 
 #include 
-#include 
+#include 
 #include 
 #include 
 #include 
-//#include 
 #include 
 #include 
 #include 
-- 
2.17.1

[PATCH v2 10/13] dt-bindings: spi: cadence-qspi: Add support for Pensando Elba SoC

2021-03-28 Thread Brad Larson 
Add new vendor Pensando Systems Elba SoC compatible
string and convert to json-schema.

Signed-off-by: Brad Larson 
---
 .../bindings/spi/cadence-quadspi.txt  |  68 
 .../bindings/spi/cadence-quadspi.yaml | 153 ++
 2 files changed, 153 insertions(+), 68 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.txt
 create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml

diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt 
b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
deleted file mode 100644
index 8ace832a2d80..
--- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-* Cadence Quad SPI controller
-
-Required properties:
-- compatible : should be one of the following:
-   Generic default - "cdns,qspi-nor".
-   For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
-   For TI AM654 SoC  - "ti,am654-ospi", "cdns,qspi-nor".
-   For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".
-- reg : Contains two entries, each of which is a tuple consisting of a
-   physical address and length. The first entry is the address and
-   length of the controller register set. The second entry is the
-   address and length of the QSPI Controller data area.
-- interrupts : Unit interrupt specifier for the controller interrupt.
-- clocks : phandle to the Quad SPI clock.
-- cdns,fifo-depth : Size of the data FIFO in words.
-- cdns,fifo-width : Bus width of the data FIFO in bytes.
-- cdns,trigger-address : 32-bit indirect AHB trigger address.
-
-Optional properties:
-- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
-- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
-  the read data rather than the QSPI clock. Make sure that QSPI return
-  clock is populated on the board before using this property.
-
-Optional subnodes:
-Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
-custom properties:
-- cdns,read-delay : Delay for read capture logic, in clock cycles
-- cdns,tshsl-ns : Delay in nanoseconds for the length that the master
-  mode chip select outputs are de-asserted between
- transactions.
-- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being
-  de-activated and the activation of another.
-- cdns,tchsh-ns : Delay in nanoseconds between last bit of current
-  transaction and deasserting the device chip select
- (qspi_n_ss_out).
-- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low
-  and first bit transfer.
-- resets   : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names  : Must include either "qspi" and/or "qspi-ocp".
-
-Example:
-
-   qspi: spi@ff705000 {
-   compatible = "cdns,qspi-nor";
-   #address-cells = <1>;
-   #size-cells = <0>;
-   reg = <0xff705000 0x1000>,
- <0xffa0 0x1000>;
-   interrupts = <0 151 4>;
-   clocks = <_clk>;
-   cdns,is-decoded-cs;
-   cdns,fifo-depth = <128>;
-   cdns,fifo-width = <4>;
-   cdns,trigger-address = <0x>;
-   resets = < QSPI_RESET>, < QSPI_OCP_RESET>;
-   reset-names = "qspi", "qspi-ocp";
-
-   flash0: n25q00@0 {
-   ...
-   cdns,read-delay = <4>;
-   cdns,tshsl-ns = <50>;
-   cdns,tsd2d-ns = <50>;
-   cdns,tchsh-ns = <4>;
-   cdns,tslch-ns = <4>;
-   };
-   };
diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml 
b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
new file mode 100644
index ..94d631045153
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/cadence-quadspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence Quad SPI controller
+
+maintainers:
+  - Ramuthevar Vadivel Murugan 
+  - Brad Larson 
+
+properties:
+  compatible:
+contains:
+  enum:
+- cdns,qspi-nor   # Generic default
+- ti,k2g-qspi # TI 66AK2G SoC
+- ti,am654-ospi   # TI AM654 SoC
+- intel,lgm-qspi  # Intel LGM SoC
+- pensando,cdns-qspi  # Pensando Elba SoC
+
+  '#address-cells':
+const: 1
+
+  '#size-cells'

[PATCH v2 00/13] Support Pensando Elba SoC

2021-03-28 Thread Brad Larson 
This series enables support for Pensando Elba SoC based platforms.
The Elba SoC has the following features:

- Sixteen ARM64 A72 cores
- Dual DDR 4/5 memory controllers
- 32 lanes of PCIe Gen3/4 to the Host
- Network interfaces: Dual 200GE, Quad 100GE, 50GE, 25GE, 10GE and
  also a single 1GE management port.
- Storage/crypto offloads and 144 programmable P4 cores.
- QSPI and EMMC for SoC storage
- Two SPI interfaces for peripheral management
- I2C bus for platform management

See below for an overview of changes since v1.

== Patch overview ==

- 01Fix typo, return code value and log message.
- 03Remove else clause, intrinsic DW chip-select is never used.
- 08-11 Split out dts and bindings to sub-patches
- 10Converted existing cadence-quadspi.txt to YAML schema
- 13New driver should use 

Brad Larson (13):
  gpio: Add Elba SoC gpio driver for spi cs control
  spi: cadence-quadspi: Add QSPI support for Pensando Elba SoC
  spi: dw: Add support for Pensando Elba SoC SPI
  spidev: Add Pensando CPLD compatible
  mmc: sdhci-cadence: Add Pensando Elba SoC support
  arm64: Add config for Pensando SoC platforms
  arm64: dts: Add Pensando Elba SoC support
  dt-bindings: Add pensando vendor prefix
  dt-bindings: mmc: Add Pensando Elba SoC binding
  dt-bindings: spi: cadence-qspi: Add support for Pensando Elba SoC
  dt-bindings: gpio: Add Pensando Elba SoC support
  MAINTAINERS: Add entry for PENSANDO
  gpio: Use linux/gpio/driver.h

 .../bindings/gpio/pensando,elba-spics.yaml|  50 +++
 .../devicetree/bindings/mmc/cdns,sdhci.yaml   |   1 +
 .../bindings/spi/cadence-quadspi.txt  |  68 
 .../bindings/spi/cadence-quadspi.yaml | 153 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 MAINTAINERS   |   9 +
 arch/arm64/Kconfig.platforms  |   5 +
 arch/arm64/boot/dts/Makefile  |   1 +
 arch/arm64/boot/dts/pensando/Makefile |   6 +
 arch/arm64/boot/dts/pensando/elba-16core.dtsi | 170 ++
 .../boot/dts/pensando/elba-asic-common.dtsi   | 112 +++
 arch/arm64/boot/dts/pensando/elba-asic.dts|   7 +
 .../boot/dts/pensando/elba-flash-parts.dtsi   |  78 +
 arch/arm64/boot/dts/pensando/elba.dtsi| 310 ++
 drivers/gpio/Kconfig  |   6 +
 drivers/gpio/Makefile |   1 +
 drivers/gpio/gpio-elba-spics.c| 113 +++
 drivers/mmc/host/Kconfig  |  15 +
 drivers/mmc/host/Makefile |   1 +
 drivers/mmc/host/sdhci-cadence-elba.c | 137 
 drivers/mmc/host/sdhci-cadence.c  |  81 +++--
 drivers/mmc/host/sdhci-cadence.h  |  68 
 drivers/spi/spi-cadence-quadspi.c |   9 +
 drivers/spi/spi-dw-mmio.c |  28 +-
 drivers/spi/spidev.c  |   1 +
 25 files changed, 1321 insertions(+), 111 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/gpio/pensando,elba-spics.yaml
 delete mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.txt
 create mode 100644 Documentation/devicetree/bindings/spi/cadence-quadspi.yaml
 create mode 100644 arch/arm64/boot/dts/pensando/Makefile
 create mode 100644 arch/arm64/boot/dts/pensando/elba-16core.dtsi
 create mode 100644 arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
 create mode 100644 arch/arm64/boot/dts/pensando/elba-asic.dts
 create mode 100644 arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
 create mode 100644 arch/arm64/boot/dts/pensando/elba.dtsi
 create mode 100644 drivers/gpio/gpio-elba-spics.c
 create mode 100644 drivers/mmc/host/sdhci-cadence-elba.c
 create mode 100644 drivers/mmc/host/sdhci-cadence.h

-- 
2.17.1

[PATCH v2 03/13] spi: dw: Add support for Pensando Elba SoC SPI

2021-03-28 Thread Brad Larson 
The Pensando Elba SoC uses a GPIO based chip select
for two DW SPI busses with each bus having two
chip selects.

Signed-off-by: Brad Larson 
---
 drivers/spi/spi-dw-mmio.c | 28 +++-
 1 file changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 17c06039a74d..c323a5ceecb8 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -56,7 +56,7 @@ struct dw_spi_mscc {
 /*
  * The Designware SPI controller (referred to as master in the documentation)
  * automatically deasserts chip select when the tx fifo is empty. The chip
- * selects then needs to be either driven as GPIOs or, for the first 4 using 
the
+ * selects then needs to be either driven as GPIOs or, for the first 4 using
  * the SPI boot controller registers. the final chip select is an OR gate
  * between the Designware SPI controller and the SPI boot controller.
  */
@@ -237,6 +237,31 @@ static int dw_spi_canaan_k210_init(struct platform_device 
*pdev,
return 0;
 }
 
+static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable)
+{
+   struct dw_spi *dws = spi_master_get_devdata(spi->master);
+
+   if (!enable) {
+   /*
+* Using a GPIO-based chip-select, the DW SPI
+* controller still needs its own CS bit selected
+* to start the serial engine.  On Elba the specific
+* CS doesn't matter to start the serial engine,
+* so using CS0.
+*/
+   dw_writel(dws, DW_SPI_SER, BIT(0));
+   } else {
+   dw_writel(dws, DW_SPI_SER, 0);
+   }
+}
+
+static int dw_spi_elba_init(struct platform_device *pdev,
+   struct dw_spi_mmio *dwsmmio)
+{
+   dwsmmio->dws.set_cs = dw_spi_elba_set_cs;
+   return 0;
+}
+
 static int dw_spi_mmio_probe(struct platform_device *pdev)
 {
int (*init_func)(struct platform_device *pdev,
@@ -351,6 +376,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = {
{ .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},
{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
{ .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
+   { .compatible = "pensando,elba-spi", .data = dw_spi_elba_init},
{ /* end of table */}
 };
 MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
-- 
2.17.1

[PATCH v2 04/13] spidev: Add Pensando CPLD compatible

2021-03-28 Thread Brad Larson 
Pensando Elba SoC platforms have a SPI connected CPLD
for platform management.

Signed-off-by: Brad Larson 
---
 drivers/spi/spidev.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index 8cb4d923aeaa..8b285852ce82 100644
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -683,6 +683,7 @@ static const struct of_device_id spidev_dt_ids[] = {
{ .compatible = "dh,dhcom-board" },
{ .compatible = "menlo,m53cpld" },
{ .compatible = "cisco,spi-petra" },
+   { .compatible = "pensando,cpld" },
{},
 };
 MODULE_DEVICE_TABLE(of, spidev_dt_ids);
-- 
2.17.1

[PATCH v2 08/13] dt-bindings: Add pensando vendor prefix

2021-03-28 Thread Brad Larson 
Add vendor prefix for Pensando Systems, Inc.

Signed-off-by: Brad Larson 
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml 
b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index f6064d84a424..9a21d780c5e1 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -850,6 +850,8 @@ patternProperties:
 description: Parallax Inc.
   "^pda,.*":
 description: Precision Design Associates, Inc.
+  "^pensando,.*":
+description: Pensando Systems Inc.
   "^pericom,.*":
 description: Pericom Technology Inc.
   "^pervasive,.*":
-- 
2.17.1

[PATCH v2 06/13] arm64: Add config for Pensando SoC platforms

2021-03-28 Thread Brad Larson 
Add ARCH_PENSANDO configuration option for Pensando SoC
based platforms.

Signed-off-by: Brad Larson 
---
 arch/arm64/Kconfig.platforms | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index cdfd5fed457f..803e7cf1df55 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -210,6 +210,11 @@ config ARCH_MXC
  This enables support for the ARMv8 based SoCs in the
  NXP i.MX family.
 
+config ARCH_PENSANDO
+   bool "Pensando Platforms"
+   help
+ This enables support for the ARMv8 based Pensando chipsets
+
 config ARCH_QCOM
bool "Qualcomm Platforms"
select GPIOLIB
-- 
2.17.1

[PATCH v2 01/13] gpio: Add Elba SoC gpio driver for spi cs control

2021-03-28 Thread Brad Larson 
This GPIO driver is for the Pensando Elba SoC which
provides control of four chip selects on two SPI busses.

Signed-off-by: Brad Larson 
---
 drivers/gpio/Kconfig   |   6 ++
 drivers/gpio/Makefile  |   1 +
 drivers/gpio/gpio-elba-spics.c | 114 +
 3 files changed, 121 insertions(+)
 create mode 100644 drivers/gpio/gpio-elba-spics.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e3607ec4c2e8..4720459b24f5 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -241,6 +241,12 @@ config GPIO_EIC_SPRD
help
  Say yes here to support Spreadtrum EIC device.
 
+config GPIO_ELBA_SPICS
+   bool "Pensando Elba SPI chip-select"
+   depends on (ARCH_PENSANDO_ELBA_SOC || COMPILE_TEST)
+   help
+ Say yes here to support the Penasndo Elba SoC SPI chip-select driver
+
 config GPIO_EM
tristate "Emma Mobile GPIO"
depends on (ARCH_EMEV2 || COMPILE_TEST) && OF_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index c58a90a3c3b1..c5c7acad371b 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_GPIO_DAVINCI)+= gpio-davinci.o
 obj-$(CONFIG_GPIO_DLN2)+= gpio-dln2.o
 obj-$(CONFIG_GPIO_DWAPB)   += gpio-dwapb.o
 obj-$(CONFIG_GPIO_EIC_SPRD)+= gpio-eic-sprd.o
+obj-$(CONFIG_GPIO_ELBA_SPICS)  += gpio-elba-spics.o
 obj-$(CONFIG_GPIO_EM)  += gpio-em.o
 obj-$(CONFIG_GPIO_EP93XX)  += gpio-ep93xx.o
 obj-$(CONFIG_GPIO_EXAR)+= gpio-exar.o
diff --git a/drivers/gpio/gpio-elba-spics.c b/drivers/gpio/gpio-elba-spics.c
new file mode 100644
index ..351bbaeea033
--- /dev/null
+++ b/drivers/gpio/gpio-elba-spics.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pensando Elba SoC SPI chip select driver
+ *
+ * Copyright (c) 2020-2021, Pensando Systems Inc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+//#include 
+#include 
+#include 
+#include 
+
+/*
+ * pin: 32|   10
+ * bit: 7--6--5--4|---3--2--1--0
+ * cs1  cs1_ovr  cs0  cs0_ovr |  cs1  cs1_ovr  cs0  cs0_ovr
+ *ssi1| ssi0
+ */
+#define SPICS_PIN_SHIFT(pin)   (2 * (pin))
+#define SPICS_MASK(pin)(0x3 << SPICS_PIN_SHIFT(pin))
+#define SPICS_SET(pin, val)val) << 1) | 0x1) << SPICS_PIN_SHIFT(pin))
+
+struct elba_spics_priv {
+   void __iomem *base;
+   spinlock_t lock;
+   struct gpio_chip chip;
+};
+
+static int elba_spics_get_value(struct gpio_chip *chip, unsigned int pin)
+{
+   return -ENOTSUPP;
+}
+
+static void elba_spics_set_value(struct gpio_chip *chip,
+   unsigned int pin, int value)
+{
+   struct elba_spics_priv *p = gpiochip_get_data(chip);
+   unsigned long flags;
+   u32 tmp;
+
+   /* select chip select from register */
+   spin_lock_irqsave(>lock, flags);
+   tmp = readl_relaxed(p->base);
+   tmp = (tmp & ~SPICS_MASK(pin)) | SPICS_SET(pin, value);
+   writel_relaxed(tmp, p->base);
+   spin_unlock_irqrestore(>lock, flags);
+}
+
+static int elba_spics_direction_input(struct gpio_chip *chip, unsigned int pin)
+{
+   return -ENOTSUPP;
+}
+
+static int elba_spics_direction_output(struct gpio_chip *chip,
+   unsigned int pin, int value)
+{
+   elba_spics_set_value(chip, pin, value);
+   return 0;
+}
+
+static int elba_spics_probe(struct platform_device *pdev)
+{
+   struct elba_spics_priv *p;
+   struct resource *res;
+   int ret = 0;
+
+   p = devm_kzalloc(>dev, sizeof(*p), GFP_KERNEL);
+   if (!p)
+   return -ENOMEM;
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   p->base = devm_ioremap_resource(>dev, res);
+   if (IS_ERR(p->base))
+   return PTR_ERR(p->base);
+   spin_lock_init(>lock);
+   platform_set_drvdata(pdev, p);
+
+   p->chip.ngpio = 4;  /* 2 cs pins for spi0, and 2 for spi1 */
+   p->chip.base = -1;
+   p->chip.direction_input = elba_spics_direction_input;
+   p->chip.direction_output = elba_spics_direction_output;
+   p->chip.get = elba_spics_get_value;
+   p->chip.set = elba_spics_set_value;
+   p->chip.label = dev_name(>dev);
+   p->chip.parent = >dev;
+   p->chip.owner = THIS_MODULE;
+
+   ret = devm_gpiochip_add_data(>dev, >chip, p);
+   if (ret)
+   dev_err(>dev, "unable to add gpio chip\n");
+   return ret;
+}
+
+static const struct of_device_id elba_spics_of_match[] = {
+   { .compatible = "pensando,elba-spics" },
+   {}
+};
+
+static struct platform_driver elba_spics_driver = {
+   .prob

[PATCH v2 02/13] spi: cadence-quadspi: Add QSPI support for Pensando Elba SoC

2021-03-28 Thread Brad Larson 
Add QSPI controller support for Pensando Elba SoC

Signed-off-by: Brad Larson 
---
 drivers/spi/spi-cadence-quadspi.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/spi/spi-cadence-quadspi.c 
b/drivers/spi/spi-cadence-quadspi.c
index 52ddb3255d88..4aacb0b2dbc7 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1353,6 +1353,7 @@ static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
cqspi->rx_chan = dma_request_chan_by_mask();
if (IS_ERR(cqspi->rx_chan)) {
int ret = PTR_ERR(cqspi->rx_chan);
+
cqspi->rx_chan = NULL;
return dev_err_probe(>pdev->dev, ret, "No Rx DMA 
available\n");
}
@@ -1633,6 +1634,10 @@ static const struct cqspi_driver_platdata intel_lgm_qspi 
= {
.quirks = CQSPI_DISABLE_DAC_MODE,
 };
 
+static const struct cqspi_driver_platdata pen_cdns_qspi = {
+   .quirks = CQSPI_NEEDS_WR_DELAY | CQSPI_DISABLE_DAC_MODE,
+};
+
 static const struct of_device_id cqspi_dt_ids[] = {
{
.compatible = "cdns,qspi-nor",
@@ -1650,6 +1655,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
.compatible = "intel,lgm-qspi",
.data = _lgm_qspi,
},
+   {
+   .compatible = "pensando,cdns-qspi",
+   .data = _cdns_qspi,
+   },
{ /* end of table */ }
 };
 
-- 
2.17.1

Re: [PATCH 1/8] gpio: Add Elba SoC gpio driver for spi cs control

2021-03-28 Thread Brad Larson 
On Sun, Mar 7, 2021 at 11:21 AM Andy Shevchenko
 wrote:
>
> On Thu, Mar 4, 2021 at 4:40 PM Brad Larson  wrote:
> >
> > This GPIO driver is for the Pensando Elba SoC which
> > provides control of four chip selects on two SPI busses.
>
> > +config GPIO_ELBA_SPICS
> > +   bool "Pensando Elba SPI chip-select"
>
> Can't it be a module? Why?

All Elba SoC based platforms require this driver to be built-in to boot and
removing the module would result in a variety of exceptions/errors.

> > +   depends on ARCH_PENSANDO_ELBA_SOC
> > +   help
> > + Say yes here to support the Pensndo Elba SoC SPI chip-select 
> > driver
>
> Please give more explanation what it is and why users might need it,
> and also tell users how the module will be named (if there is no
> strong argument why it can't be a  module).
>
Fixed the typo.

> > +#include 
>
> It's not used here, but you missed mod_devicetable.h.

Removed .  There is no dependency on mod_devicetable.h.

> ...
>
> > +/*
> > + * pin: 32|   10
> > + * bit: 7--6--5--4|---3--2--1--0
> > + * cs1  cs1_ovr  cs0  cs0_ovr |  cs1  cs1_ovr  cs0  cs0_ovr
> > + *ssi1| ssi0
> > + */
> > +#define SPICS_PIN_SHIFT(pin)   (2 * (pin))
> > +#define SPICS_MASK(pin)(0x3 << SPICS_PIN_SHIFT(pin))
>
> > +#define SPICS_SET(pin, val)val) << 1) | 0x1) << 
> > SPICS_PIN_SHIFT(pin))
>
> Isn't it easier to define as ((value) << (2 * (pin) + 1) | BIT(2 * (pin)))
>
> ...
>
> > +struct elba_spics_priv {
> > +   void __iomem *base;
> > +   spinlock_t lock;
>
> > +   struct gpio_chip chip;
>
> If you put it as a first member a container_of() becomes a no-op. OTOH
> dunno if there is any such container_of() use in the code.
>

There is no use of container_of()

> > +static int elba_spics_get_value(struct gpio_chip *chip, unsigned int pin)
> > +{
> > +   return -ENXIO;
>
> Hmm... Is it really acceptable error code here?
>
> > +static int elba_spics_direction_input(struct gpio_chip *chip, unsigned int 
> > pin)
> > +{
> > +   return -ENXIO;
>
> Ditto.
>
Changed both to -ENOTSUPP.

> > +   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +   p->base = devm_ioremap_resource(>dev, res);
>
> p->base = devm_platform_ioremap_resource(pdev, 0);

Implementation follows devm_ioremap_resource() example in lib/devres.c.

> > +   if (IS_ERR(p->base)) {
>
> > +   dev_err(>dev, "failed to remap I/O memory\n");
>
> Duplicate noisy message.
>
> > +   return PTR_ERR(p->base);
> > +   }
>
> > +   ret = devm_gpiochip_add_data(>dev, >chip, p);
> > +   if (ret) {
> > +   dev_err(>dev, "unable to add gpio chip\n");
>
> > +   return ret;
> > +   }
> > +
> > +   dev_info(>dev, "elba spics registered\n");
> > +   return 0;
>
> if (ret)
>   dev_err(...);
> return ret;

Cleaned this up in patchset v2.

Re: [PATCH 7/8] arm64: dts: Add Pensando Elba SoC support

2021-03-28 Thread Brad Larson 
On Thu, Mar 4, 2021 at 12:03 AM Serge Semin  wrote:
>
> On Wed, Mar 03, 2021 at 07:41:40PM -0800, Brad Larson wrote:
> > Add Pensando common and Elba SoC specific device nodes
> > and corresponding binding documentation.
>
> This also needs to be split up into sub-patches seeing these are
> unrelated changes like device bindings update, new platform DT file.

In patchset v2 this is split into sub-patches.

> What about converting this file to DT-schema and adding new HW
> bindings in there?

Converted existing file devicetree/bindings/spi/cadence-quadspi.txt to
YAML schema.

> > + {
> > + num-cs = <4>;
>
> > + cs-gpios = < 0 0>, < 1 0>, < 1 0>, < 7 0>;
>
> Oh, you've got four peripheral SPI devices connected with only two native CS
> available. Hmm, then I don't really know a better way, but just to forget 
> about
> the native DW APB CS functionality and activate the direct driving of
> all the CS-pins at the moment of the DW APB SPI controller probe
> procedure. Then indeed you'll need a custom CS function defined in the DW APB
> SPI driver to handle that.

Yes, with an Elba SoC specific gpio driver.

> So that GPIO-controller is just a single register which provides a way
> to toggle the DW APB SPI CS-mode together with their output value.
> If so and seeing there are a few more tiny spaces of config
> registers added to eMMC, PCI, etc DT node, I suppose all of them
> belong to some bigger config space of the SoC. Thus I'd suggest to at
> least implement them as part of a System Controller DT node. Then use
> that device service to switch on/off corresponding functionality.
> See [2] and the rest of added to the kernel DTS files with
> syscon-nodes for example.
>
> [2] Documentation/devicetree/bindings/mfd/syscon.yaml

To us it was more understandable to implement a standard gpio driver
for the spi chip-selects.

Re: [PATCH 7/8] arm64: dts: Add Pensando Elba SoC support

2021-03-28 Thread Brad Larson 
On Thu, Mar 4, 2021 at 12:52 AM Linus Walleij  wrote:
>
> On Thu, Mar 4, 2021 at 4:42 AM Brad Larson  wrote:
>
> > Add Pensando common and Elba SoC specific device nodes
> > and corresponding binding documentation.
> >
> > Signed-off-by: Brad Larson 
> (...)
> >  .../bindings/gpio/pensando,elba-spics.txt |  24 ++
>
> Please use YAML schema for this.

In patchset v2 changed to YAML schema and passed dt_binding_check and
dtbs_check.

Re: [PATCH 3/8] spi: dw: Add support for Pensando Elba SoC SPI

2021-03-09 Thread Brad Larson 
On Thu, Mar 4, 2021 at 12:48 AM Linus Walleij  wrote:

> On Thu, Mar 4, 2021 at 4:42 AM Brad Larson  wrote:
>
> > The Pensando Elba SoC uses a GPIO based chip select
> > for two DW SPI busses with each bus having two
> > chip selects.
> >
> > Signed-off-by: Brad Larson 
>
> I agree with Serge's comments here: the existing cs callback should
> work for your SoC, you should only need the new compatible string.
>
> I see why you need the special GPIO driver for this now, as that
> is obviously driven by totally different hardware.
>
> Yours,
> Linus Walleij

Thanks Serge and Linus for the review.

In the SPI driver, the reason we need our own set_cs function is that
our DW SPI controller only supports intrinsic 2 chip-select pins.

This is the standard DW set_cs function:

void dw_spi_set_cs(struct spi_device *spi, bool enable)
{
struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
bool cs_high = !!(spi->mode & SPI_CS_HIGH);

/*
 * DW SPI controller demands any native CS being set in order to
 * proceed with data transfer. So in order to activate the SPI
 * communications we must set a corresponding bit in the Slave
 * Enable register no matter whether the SPI core is configured to
 * support active-high or active-low CS level.
 */
if (cs_high == enable)
dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
else
dw_writel(dws, DW_SPI_SER, 0);
}

The dw_writel function argument DW_SPI_SER, BIT(spi->chip_select)
works for chip-select 0 & 1, but not for 2 & 3, as the IP only
implements bits [1:0] in the DW_SPI_SER register.  In the Elba SoC we
require GPIO-style chip-selects, our own set_cs function, and we
always use bit 0 of DW_SPI_SER to start the serial machine, not as a
chip-select control.  In the dw_spi_set_cs() function the below else
clause is never taken and leads to confusion.

 } else {
/*
 * Using the intrinsic DW chip-select; set the
 * appropriate CS.
 */
dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
}

This else clause will be removed in patch set V2.  I tried the generic
dw_spi_set_cs() thinking it would just start the serial machine while
the Elba spics drives the gpio chip select, that didn't work.  I will
take another look at it as I work on V2 of the patchset to see exactly
what breaks during spi init.

Best,
Brad

[PATCH 5/8] mmc: sdhci-cadence: Add Pensando Elba SoC support

2021-03-03 Thread Brad Larson 
Add support for Pensando Elba SoC which explicitly controls
byte-lane enables on writes.  Refactor to allow platform
specific write ops.

Signed-off-by: Brad Larson 
---
 drivers/mmc/host/Kconfig  |  15 +++
 drivers/mmc/host/Makefile |   1 +
 drivers/mmc/host/sdhci-cadence-elba.c | 137 ++
 drivers/mmc/host/sdhci-cadence.c  |  78 +++
 drivers/mmc/host/sdhci-cadence.h  |  68 +
 5 files changed, 257 insertions(+), 42 deletions(-)
 create mode 100644 drivers/mmc/host/sdhci-cadence-elba.c
 create mode 100644 drivers/mmc/host/sdhci-cadence.h

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index b236dfe2e879..65ea323c06f2 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -250,6 +250,21 @@ config MMC_SDHCI_CADENCE
 
  If unsure, say N.
 
+config MMC_SDHCI_CADENCE_ELBA
+   tristate "SDHCI support for the Pensando/Cadence SD/SDIO/eMMC 
controller"
+   depends on ARCH_PENSANDO_ELBA_SOC
+   depends on MMC_SDHCI
+   depends on OF
+   depends on MMC_SDHCI_CADENCE
+   depends on MMC_SDHCI_PLTFM
+   select MMC_SDHCI_IO_ACCESSORS
+   help
+ This selects the Pensando/Cadence SD/SDIO/eMMC controller.
+
+ If you have a controller with this interface, say Y or M here.
+
+ If unsure, say N.
+
 config MMC_SDHCI_CNS3XXX
tristate "SDHCI support on the Cavium Networks CNS3xxx SoC"
depends on ARCH_CNS3XXX || COMPILE_TEST
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 6df5c4774260..f2a6d50e64de 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -80,6 +80,7 @@ obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o
 
 obj-$(CONFIG_MMC_SDHCI_PLTFM)  += sdhci-pltfm.o
 obj-$(CONFIG_MMC_SDHCI_CADENCE)+= sdhci-cadence.o
+obj-$(CONFIG_MMC_SDHCI_CADENCE_ELBA)   += sdhci-cadence-elba.o
 obj-$(CONFIG_MMC_SDHCI_CNS3XXX)+= sdhci-cns3xxx.o
 obj-$(CONFIG_MMC_SDHCI_ESDHC_MCF)   += sdhci-esdhc-mcf.o
 obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX)  += sdhci-esdhc-imx.o
diff --git a/drivers/mmc/host/sdhci-cadence-elba.c 
b/drivers/mmc/host/sdhci-cadence-elba.c
new file mode 100644
index ..e128e83e9be9
--- /dev/null
+++ b/drivers/mmc/host/sdhci-cadence-elba.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2020-2021 Pensando Systems, Inc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "sdhci-pltfm.h"
+#include "sdhci-cadence.h"
+
+// delay regs address
+#define SDIO_REG_HRS4  0x10
+#define REG_DELAY_HS   0x00
+#define REG_DELAY_DEFAULT  0x01
+#define REG_DELAY_UHSI_SDR50   0x04
+#define REG_DELAY_UHSI_DDR50   0x05
+
+static void elba_write_l(struct sdhci_host *host, u32 val, int reg)
+{
+   struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+   unsigned long flags;
+
+   spin_lock_irqsave(>wrlock, flags);
+   writel(0x78, priv->ctl_addr);
+   writel(val, host->ioaddr + reg);
+   spin_unlock_irqrestore(>wrlock, flags);
+}
+
+static void elba_write_w(struct sdhci_host *host, u16 val, int reg)
+{
+   struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+   unsigned long flags;
+   u32 m = (reg & 0x3);
+   u32 msk = (0x3 << (m));
+
+   spin_lock_irqsave(>wrlock, flags);
+   writel(msk << 3, priv->ctl_addr);
+   writew(val, host->ioaddr + reg);
+   spin_unlock_irqrestore(>wrlock, flags);
+}
+
+static void elba_write_b(struct sdhci_host *host, u8 val, int reg)
+{
+   struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
+   unsigned long flags;
+   u32 m = (reg & 0x3);
+   u32 msk = (0x1 << (m));
+
+   spin_lock_irqsave(>wrlock, flags);
+   writel(msk << 3, priv->ctl_addr);
+   writeb(val, host->ioaddr + reg);
+   spin_unlock_irqrestore(>wrlock, flags);
+}
+
+static void elba_priv_write_l(struct sdhci_cdns_priv *priv,
+   u32 val, void __iomem *reg)
+{
+   unsigned long flags;
+
+   spin_lock_irqsave(>wrlock, flags);
+   writel(0x78, priv->ctl_addr);
+   writel(val, reg);
+   spin_unlock_irqrestore(>wrlock, flags);
+}
+
+static const struct sdhci_ops sdhci_elba_ops = {
+   .write_l = elba_write_l,
+   .write_w = elba_write_w,
+   .write_b = elba_write_b,
+   .set_clock = sdhci_set_clock,
+   .get_timeout_clock = sdhci_cdns_get_timeout_clock,
+   .set_bus_width = sdhci_set_bus_width,
+   .reset = sdhci_reset,
+   .set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
+};
+
+static void sd4_set_dlyvr(struct sdhci_host *host,
+ unsigned char addr, unsigned char data)
+{
+   unsigned long dlyrv_reg;
+
+   dlyrv_reg = ((unsigned long)data << 8);
+   dlyr

[PATCH 7/8] arm64: dts: Add Pensando Elba SoC support

2021-03-03 Thread Brad Larson 
Add Pensando common and Elba SoC specific device nodes
and corresponding binding documentation.

Signed-off-by: Brad Larson 
---
 .../bindings/gpio/pensando,elba-spics.txt |  24 ++
 .../devicetree/bindings/mmc/cdns,sdhci.yaml   |   2 +-
 .../bindings/spi/cadence-quadspi.txt  |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 arch/arm64/boot/dts/Makefile  |   1 +
 arch/arm64/boot/dts/pensando/Makefile |   6 +
 arch/arm64/boot/dts/pensando/elba-16core.dtsi | 171 ++
 .../boot/dts/pensando/elba-asic-common.dtsi   | 113 +++
 arch/arm64/boot/dts/pensando/elba-asic.dts|   8 +
 .../boot/dts/pensando/elba-flash-parts.dtsi   |  80 +
 arch/arm64/boot/dts/pensando/elba.dtsi| 310 ++
 11 files changed, 717 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/gpio/pensando,elba-spics.txt
 create mode 100644 arch/arm64/boot/dts/pensando/Makefile
 create mode 100644 arch/arm64/boot/dts/pensando/elba-16core.dtsi
 create mode 100644 arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
 create mode 100644 arch/arm64/boot/dts/pensando/elba-asic.dts
 create mode 100644 arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
 create mode 100644 arch/arm64/boot/dts/pensando/elba.dtsi

diff --git a/Documentation/devicetree/bindings/gpio/pensando,elba-spics.txt 
b/Documentation/devicetree/bindings/gpio/pensando,elba-spics.txt
new file mode 100644
index ..30f5f3275238
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/pensando,elba-spics.txt
@@ -0,0 +1,24 @@
+Pensando Elba SPI Chip Select Driver
+
+The Pensando Elba ASIC provides four SPI bus chip selects
+
+Required properties:
+- compatible: Should be "pensando,elba-spics"
+- reg: Address range of spics controller
+- gpio-controller: Marks the device node as gpio controller
+- #gpio-cells: Must be 2
+
+Example:
+---
+spics: spics@307c2468 {
+compatible = "pensando,elba-spics";
+reg = <0x0 0x307c2468 0x0 0x4>;
+gpio-controller;
+#gpio-cells = <2>;
+};
+
+ {
+num-cs = <4>;
+cs-gpios = < 0 0>, < 1 0>, < 1 0>, < 7 0>;
+   ...
+}
diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml 
b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
index af7442f73881..645ae696ba24 100644
--- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
@@ -122,7 +122,7 @@ unevaluatedProperties: false
 examples:
   - |
 emmc: mmc@5a00 {
-compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
+compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc", 
"pensando,elba-emmc";
 reg = <0x5a00 0x400>;
 interrupts = <0 78 4>;
 clocks = < 4>;
diff --git a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt 
b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
index 8ace832a2d80..dbb346b2b1d7 100644
--- a/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
+++ b/Documentation/devicetree/bindings/spi/cadence-quadspi.txt
@@ -6,6 +6,7 @@ Required properties:
For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
For TI AM654 SoC  - "ti,am654-ospi", "cdns,qspi-nor".
For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".
+   For Pensando SoC - "pensando,cdns-qspi".
 - reg : Contains two entries, each of which is a tuple consisting of a
physical address and length. The first entry is the address and
length of the controller register set. The second entry is the
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml 
b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index f6064d84a424..9a21d780c5e1 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -850,6 +850,8 @@ patternProperties:
 description: Parallax Inc.
   "^pda,.*":
 description: Precision Design Associates, Inc.
+  "^pensando,.*":
+description: Pensando Systems Inc.
   "^pericom,.*":
 description: Pericom Technology Inc.
   "^pervasive,.*":
diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile
index f1173cd93594..c85db0a097fe 100644
--- a/arch/arm64/boot/dts/Makefile
+++ b/arch/arm64/boot/dts/Makefile
@@ -19,6 +19,7 @@ subdir-y += marvell
 subdir-y += mediatek
 subdir-y += microchip
 subdir-y += nvidia
+subdir-y += pensando
 subdir-y += qcom
 subdir-y += realtek
 subdir-y += renesas
diff --git a/arch/arm64/boot/dts/pensando/Makefile 
b/arch/arm64/boot/dts/pensando/Makefile
new file mode 100644
index ..0c2c0961e64a
--- /dev/null
+++ b/arch/arm64/boot/dts/pensando/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Id

[PATCH 6/8] arm64: Add config for Pensando SoC platforms

2021-03-03 Thread Brad Larson 
Add ARCH_PENSANDO configuration option for Pensando SoC
based platforms.

Signed-off-by: Brad Larson 
---
 arch/arm64/Kconfig.platforms | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index cdfd5fed457f..803e7cf1df55 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -210,6 +210,11 @@ config ARCH_MXC
  This enables support for the ARMv8 based SoCs in the
  NXP i.MX family.
 
+config ARCH_PENSANDO
+   bool "Pensando Platforms"
+   help
+ This enables support for the ARMv8 based Pensando chipsets
+
 config ARCH_QCOM
bool "Qualcomm Platforms"
select GPIOLIB
-- 
2.17.1

[PATCH 2/8] spi: cadence-quadspi: Add QSPI support for Pensando Elba SoC

2021-03-03 Thread Brad Larson 
Add QSPI controller support fo Pensando Elba SoC.

Signed-off-by: Brad Larson 
---
 drivers/spi/spi-cadence-quadspi.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/spi/spi-cadence-quadspi.c 
b/drivers/spi/spi-cadence-quadspi.c
index 442cc7c53a47..fb0d9b0bd596 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -1353,6 +1353,7 @@ static int cqspi_request_mmap_dma(struct cqspi_st *cqspi)
cqspi->rx_chan = dma_request_chan_by_mask();
if (IS_ERR(cqspi->rx_chan)) {
int ret = PTR_ERR(cqspi->rx_chan);
+
cqspi->rx_chan = NULL;
return dev_err_probe(>pdev->dev, ret, "No Rx DMA 
available\n");
}
@@ -1632,6 +1633,10 @@ static const struct cqspi_driver_platdata intel_lgm_qspi 
= {
.quirks = CQSPI_DISABLE_DAC_MODE,
 };
 
+static const struct cqspi_driver_platdata pen_cdns_qspi = {
+   .quirks = CQSPI_NEEDS_WR_DELAY | CQSPI_DISABLE_DAC_MODE,
+};
+
 static const struct of_device_id cqspi_dt_ids[] = {
{
.compatible = "cdns,qspi-nor",
@@ -1649,6 +1654,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
.compatible = "intel,lgm-qspi",
.data = _lgm_qspi,
},
+   {
+   .compatible = "pensando,cdns-qspi",
+   .data = _cdns_qspi,
+   },
{ /* end of table */ }
 };
 
-- 
2.17.1

[PATCH 8/8] MAINTAINERS: Add entry for PENSANDO

2021-03-03 Thread Brad Larson 
Add entry for PENSANDO maintainer and files.

Signed-off-by: Brad Larson 
---
 MAINTAINERS | 9 +
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 973a937386fa..3f2eebda2396 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2246,6 +2246,15 @@ S:   Maintained
 W: http://hackndev.com
 F: arch/arm/mach-pxa/palmz72.*
 
+ARM/PENSANDO SUPPORT
+M: Brad Larson 
+L: linux-arm-ker...@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: Documentation/devicetree/bindings/*/pensando*
+F: arch/arm64/boot/dts/pensando/
+F: drivers/gpio/gpio-elba-spics.c
+F: drivers/mmc/host/sdhci-cadence-elba.c
+
 ARM/PLEB SUPPORT
 M: Peter Chubb 
 S: Maintained
-- 
2.17.1

[PATCH 3/8] spi: dw: Add support for Pensando Elba SoC SPI

2021-03-03 Thread Brad Larson 
The Pensando Elba SoC uses a GPIO based chip select
for two DW SPI busses with each bus having two
chip selects.

Signed-off-by: Brad Larson 
---
 drivers/spi/spi-dw-mmio.c | 35 ++-
 1 file changed, 34 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 17c06039a74d..417bd2125c07 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -56,7 +56,7 @@ struct dw_spi_mscc {
 /*
  * The Designware SPI controller (referred to as master in the documentation)
  * automatically deasserts chip select when the tx fifo is empty. The chip
- * selects then needs to be either driven as GPIOs or, for the first 4 using 
the
+ * selects then needs to be either driven as GPIOs or, for the first 4 using
  * the SPI boot controller registers. the final chip select is an OR gate
  * between the Designware SPI controller and the SPI boot controller.
  */
@@ -237,6 +237,38 @@ static int dw_spi_canaan_k210_init(struct platform_device 
*pdev,
return 0;
 }
 
+static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable)
+{
+   struct dw_spi *dws = spi_master_get_devdata(spi->master);
+
+   if (!enable) {
+   if (spi->cs_gpiod) {
+   /*
+* Using a GPIO-based chip-select, the DW SPI
+* controller still needs its own CS bit selected
+* to start the serial engine.  On Elba the specific
+* CS doesn't matter, so use CS0.
+*/
+   dw_writel(dws, DW_SPI_SER, BIT(0));
+   } else {
+   /*
+* Using the intrinsic DW chip-select; set the
+* appropriate CS.
+*/
+   dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
+   }
+   } else
+   dw_writel(dws, DW_SPI_SER, 0);
+}
+
+static int dw_spi_elba_init(struct platform_device *pdev,
+   struct dw_spi_mmio *dwsmmio)
+{
+   dwsmmio->dws.set_cs = dw_spi_elba_set_cs;
+
+   return 0;
+}
+
 static int dw_spi_mmio_probe(struct platform_device *pdev)
 {
int (*init_func)(struct platform_device *pdev,
@@ -351,6 +383,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = {
{ .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},
{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
{ .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
+   { .compatible = "pensando,elba-spi", .data = dw_spi_elba_init },
{ /* end of table */}
 };
 MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
-- 
2.17.1

[PATCH 4/8] spidev: Add Pensando CPLD compatible

2021-03-03 Thread Brad Larson 
Pensando Elba SoC platforms have a SPI connected CPLD
for platform management.

Signed-off-by: Brad Larson 
---
 drivers/spi/spidev.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index 8cb4d923aeaa..8b285852ce82 100644
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -683,6 +683,7 @@ static const struct of_device_id spidev_dt_ids[] = {
{ .compatible = "dh,dhcom-board" },
{ .compatible = "menlo,m53cpld" },
{ .compatible = "cisco,spi-petra" },
+   { .compatible = "pensando,cpld" },
{},
 };
 MODULE_DEVICE_TABLE(of, spidev_dt_ids);
-- 
2.17.1

[PATCH 1/8] gpio: Add Elba SoC gpio driver for spi cs control

2021-03-03 Thread Brad Larson 
This GPIO driver is for the Pensando Elba SoC which
provides control of four chip selects on two SPI busses.

Signed-off-by: Brad Larson 
---
 drivers/gpio/Kconfig   |   6 ++
 drivers/gpio/Makefile  |   1 +
 drivers/gpio/gpio-elba-spics.c | 120 +
 3 files changed, 127 insertions(+)
 create mode 100644 drivers/gpio/gpio-elba-spics.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index e3607ec4c2e8..d99bc82aa8fa 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -241,6 +241,12 @@ config GPIO_EIC_SPRD
help
  Say yes here to support Spreadtrum EIC device.
 
+config GPIO_ELBA_SPICS
+   bool "Pensando Elba SPI chip-select"
+   depends on ARCH_PENSANDO_ELBA_SOC
+   help
+ Say yes here to support the Pensndo Elba SoC SPI chip-select driver
+
 config GPIO_EM
tristate "Emma Mobile GPIO"
depends on (ARCH_EMEV2 || COMPILE_TEST) && OF_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index c58a90a3c3b1..c5c7acad371b 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_GPIO_DAVINCI)+= gpio-davinci.o
 obj-$(CONFIG_GPIO_DLN2)+= gpio-dln2.o
 obj-$(CONFIG_GPIO_DWAPB)   += gpio-dwapb.o
 obj-$(CONFIG_GPIO_EIC_SPRD)+= gpio-eic-sprd.o
+obj-$(CONFIG_GPIO_ELBA_SPICS)  += gpio-elba-spics.o
 obj-$(CONFIG_GPIO_EM)  += gpio-em.o
 obj-$(CONFIG_GPIO_EP93XX)  += gpio-ep93xx.o
 obj-$(CONFIG_GPIO_EXAR)+= gpio-exar.o
diff --git a/drivers/gpio/gpio-elba-spics.c b/drivers/gpio/gpio-elba-spics.c
new file mode 100644
index ..a845525cf2a3
--- /dev/null
+++ b/drivers/gpio/gpio-elba-spics.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Pensando Elba ASIC SPI chip select driver
+ *
+ * Copyright (c) 2020-2021, Pensando Systems Inc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * pin: 32|   10
+ * bit: 7--6--5--4|---3--2--1--0
+ * cs1  cs1_ovr  cs0  cs0_ovr |  cs1  cs1_ovr  cs0  cs0_ovr
+ *ssi1| ssi0
+ */
+#define SPICS_PIN_SHIFT(pin)   (2 * (pin))
+#define SPICS_MASK(pin)(0x3 << SPICS_PIN_SHIFT(pin))
+#define SPICS_SET(pin, val)val) << 1) | 0x1) << SPICS_PIN_SHIFT(pin))
+
+struct elba_spics_priv {
+   void __iomem *base;
+   spinlock_t lock;
+   struct gpio_chip chip;
+};
+
+static int elba_spics_get_value(struct gpio_chip *chip, unsigned int pin)
+{
+   return -ENXIO;
+}
+
+static void elba_spics_set_value(struct gpio_chip *chip,
+   unsigned int pin, int value)
+{
+   struct elba_spics_priv *p = gpiochip_get_data(chip);
+   unsigned long flags;
+   u32 tmp;
+
+   /* select chip select from register */
+   spin_lock_irqsave(>lock, flags);
+   tmp = readl_relaxed(p->base);
+   tmp = (tmp & ~SPICS_MASK(pin)) | SPICS_SET(pin, value);
+   writel_relaxed(tmp, p->base);
+   spin_unlock_irqrestore(>lock, flags);
+}
+
+static int elba_spics_direction_input(struct gpio_chip *chip, unsigned int pin)
+{
+   return -ENXIO;
+}
+
+static int elba_spics_direction_output(struct gpio_chip *chip,
+   unsigned int pin, int value)
+{
+   elba_spics_set_value(chip, pin, value);
+   return 0;
+}
+
+static int elba_spics_probe(struct platform_device *pdev)
+{
+   struct elba_spics_priv *p;
+   struct resource *res;
+   int ret;
+
+   p = devm_kzalloc(>dev, sizeof(*p), GFP_KERNEL);
+   if (!p)
+   return -ENOMEM;
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   p->base = devm_ioremap_resource(>dev, res);
+   if (IS_ERR(p->base)) {
+   dev_err(>dev, "failed to remap I/O memory\n");
+   return PTR_ERR(p->base);
+   }
+   spin_lock_init(>lock);
+   platform_set_drvdata(pdev, p);
+
+   p->chip.ngpio = 4;  /* 2 cs pins for spi0, and 2 for spi1 */
+   p->chip.base = -1;
+   p->chip.direction_input = elba_spics_direction_input;
+   p->chip.direction_output = elba_spics_direction_output;
+   p->chip.get = elba_spics_get_value;
+   p->chip.set = elba_spics_set_value;
+   p->chip.label = dev_name(>dev);
+   p->chip.parent = >dev;
+   p->chip.owner = THIS_MODULE;
+
+   ret = devm_gpiochip_add_data(>dev, >chip, p);
+   if (ret) {
+   dev_err(>dev, "unable to add gpio chip\n");
+   return ret;
+   }
+
+   dev_info(>dev, "elba spics registered\n");
+   return 0;
+}
+
+static const struct of_device_id ebla_spics_of_match[

[PATCH 0/8] Support Pensando Elba SoC

2021-03-03 Thread Brad Larson 
This series enables support for Pensando Elba SoC based platforms.
The Elba SoC has the following features:

- Sixteen ARM64 A72 cores
- Dual DDR 4/5 memory controllers
- 32 lanes of PCIe Gen3/4 to the Host
- Network interfaces: Dual 200GE, Quad 100GE, 50GE, 25GE, 10GE and
  also a single 1GE management port.
- Storage/crypto offloads and 144 programmable P4 cores.
- QSPI and EMMC for SoC storage
- Two SPI interfaces for peripheral management
- I2C bus for platform management

Brad Larson (8):
  gpio: Add Elba SoC gpio driver for spi cs control
  spi: cadence-quadspi: Add QSPI support for Pensando Elba SoC
  spi: dw: Add support for Pensando Elba SoC SPI
  spidev: Add Pensando CPLD compatible
  mmc: sdhci-cadence: Add Pensando Elba SoC support
  arm64: Add config for Pensando SoC platforms
  arm64: dts: Add Pensando Elba SoC support
  MAINTAINERS: Add entry for PENSANDO

 .../bindings/gpio/pensando,elba-spics.txt |  24 ++
 .../devicetree/bindings/mmc/cdns,sdhci.yaml   |   2 +-
 .../bindings/spi/cadence-quadspi.txt  |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 MAINTAINERS   |   9 +
 arch/arm64/Kconfig.platforms  |   5 +
 arch/arm64/boot/dts/Makefile  |   1 +
 arch/arm64/boot/dts/pensando/Makefile |   6 +
 arch/arm64/boot/dts/pensando/elba-16core.dtsi | 171 ++
 .../boot/dts/pensando/elba-asic-common.dtsi   | 113 +++
 arch/arm64/boot/dts/pensando/elba-asic.dts|   8 +
 .../boot/dts/pensando/elba-flash-parts.dtsi   |  80 +
 arch/arm64/boot/dts/pensando/elba.dtsi| 310 ++
 drivers/gpio/Kconfig  |   6 +
 drivers/gpio/Makefile |   1 +
 drivers/gpio/gpio-elba-spics.c| 120 +++
 drivers/mmc/host/Kconfig  |  15 +
 drivers/mmc/host/Makefile |   1 +
 drivers/mmc/host/sdhci-cadence-elba.c | 137 
 drivers/mmc/host/sdhci-cadence.c  |  78 ++---
 drivers/mmc/host/sdhci-cadence.h  |  68 
 drivers/spi/spi-cadence-quadspi.c |   9 +
 drivers/spi/spi-dw-mmio.c |  35 +-
 drivers/spi/spidev.c  |   1 +
 24 files changed, 1159 insertions(+), 44 deletions(-)
 create mode 100644 
Documentation/devicetree/bindings/gpio/pensando,elba-spics.txt
 create mode 100644 arch/arm64/boot/dts/pensando/Makefile
 create mode 100644 arch/arm64/boot/dts/pensando/elba-16core.dtsi
 create mode 100644 arch/arm64/boot/dts/pensando/elba-asic-common.dtsi
 create mode 100644 arch/arm64/boot/dts/pensando/elba-asic.dts
 create mode 100644 arch/arm64/boot/dts/pensando/elba-flash-parts.dtsi
 create mode 100644 arch/arm64/boot/dts/pensando/elba.dtsi
 create mode 100644 drivers/gpio/gpio-elba-spics.c
 create mode 100644 drivers/mmc/host/sdhci-cadence-elba.c
 create mode 100644 drivers/mmc/host/sdhci-cadence.h

-- 
2.17.1

[PATCH] swiotlb: swiotlb_tbl_map_single() kernel BUG in iommu-helper.h:30

2021-02-26 Thread Brad Larson 
Kernel Oops introduced in next-20210222 due to get_max_slots return arg size.
In the function find_slots() variable max_slots is zero when boundary_mask is
0x.

[0.242119] kernel BUG at ./include/linux/iommu-helper.h:30!
[0.247793] Internal error: Oops - BUG: 0 [#1] SMP
[0.252595] Modules linked in:
[0.255657] CPU: 0 PID: 93 Comm: kworker/0:1 Not tainted 
5.11.0-next-20210224+ #25
[0.263245] Hardware name: Elba ASIC Board (DT)
[0.267784] Workqueue: events_freezable mmc_rescan
[0.272592] pstate: 6085 (nZCv daIf -PAN -UAO -TCO BTYPE=--)
[0.278612] pc : swiotlb_tbl_map_single+0x2b0/0x6a0
[0.283505] lr : swiotlb_tbl_map_single+0x440/0x6a0
[0.288395] sp : ffc0122736b0
[0.291713] x29: ffc0122736b0 x28: ffc010e3
[0.297039] x27: bbf58000 x26: 
[0.302364] x25:  x24: 0001
[0.307689] x23:  x22: 
[0.313013] x21:  x20: 
[0.318338] x19: 001241fd4600 x18: ffc010d288c8
[0.323662] x17: 0007 x16: 0001
[0.328987] x15: ffc092273367 x14: 3a424c54204f4920
[0.334311] x13: 6572617774666f73 x12: 20726e2030207865
[0.339636] x11: 646e692078787820 x10: 3062653737317830
[0.344960] x9 : 2074666968732031 x8 : ff977cf82368
[0.350285] x7 : 0001 x6 : c000efff
[0.355609] x5 : 00017fe8 x4 : 
[0.360934] x3 :  x2 : 18b0d50da009d000
[0.366258] x1 :  x0 : 0042
[0.371583] Call trace:
[0.374032]  swiotlb_tbl_map_single+0x2b0/0x6a0
[0.378573]  swiotlb_map+0xa8/0x2b0

Signed-off-by: Brad Larson 
---
 kernel/dma/swiotlb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/dma/swiotlb.c b/kernel/dma/swiotlb.c
index 369e4c3a0f2b..c10e855a03bc 100644
--- a/kernel/dma/swiotlb.c
+++ b/kernel/dma/swiotlb.c
@@ -534,7 +534,7 @@ static int find_slots(struct device *dev, phys_addr_t 
orig_addr,
unsigned long boundary_mask = dma_get_seg_boundary(dev);
dma_addr_t tbl_dma_addr =
phys_to_dma_unencrypted(dev, io_tlb_start) & boundary_mask;
-   unsigned int max_slots = get_max_slots(boundary_mask);
+   unsigned long max_slots = get_max_slots(boundary_mask);
unsigned int iotlb_align_mask =
dma_get_min_align_mask(dev) & ~(IO_TLB_SIZE - 1);
unsigned int nslots = nr_slots(alloc_size), stride;
-- 
2.17.1