Re: [PATCH 1/1] add rgb888 pins to a20 to enable parallel rgb LCD
在 2017-11-08 18:56,Maxime Ripard 写道: Hi, On Tue, Nov 07, 2017 at 05:38:55PM +0100, Giulio Benetti wrote: Board could be any with A20, for example Olinuxino A20. Or our Q027, S027 boards, but final dts still are not complete. Therefore no upstream boards are using it right now, so we'll merge it when that will be the case. I think the LCD connector on Banana Pi's uses parallel interface, although the LCD should be an external DT overlay. Maxime ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH 1/1] add rgb888 pins to a20 to enable parallel rgb LCD
在 2017-11-08 18:56,Maxime Ripard 写道: Hi, On Tue, Nov 07, 2017 at 05:38:55PM +0100, Giulio Benetti wrote: Board could be any with A20, for example Olinuxino A20. Or our Q027, S027 boards, but final dts still are not complete. Therefore no upstream boards are using it right now, so we'll merge it when that will be the case. I think the LCD connector on Banana Pi's uses parallel interface, although the LCD should be an external DT overlay. Maxime ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: AXP803 I2C support / AXP devicetree-bindings
于 2017年11月7日 GMT+08:00 上午11:13:23, Chen-Yu Tsai写到: On Tue, Nov 7, 2017 at 6:39 AM, Martin Blumenstingl wrote: Hello, recently I discovered that there are some X-Powers AXP chips that support both, Allwinner's own "RSB" as well as the I2C ("TWSI" in the datasheet) busses. one chip that supports both interfaces is the AXP803 the datasheet is linked in the public PINE64 wiki: [1] (direct link: [0]) All the RSB based PMICs support both modes. They start in I2C mode when cold booted. I think it starts at a vendor-customized mode. In all PMICs sold with Allwinner SoCs the mode is predefined to RSB. In fact many registers in AXPs are vendor-customizable, see the datasheets. currently the "x-powers,axp803" binding is "RSB" bus specific as it's currently only listed in drivers/mfd/axp20x-rsb.c was there a discussion about supporting both, the "RSB" and I2C bus for one chip (for example the AXP803) in the past (I couldn't find anything online)? No. None of the boards actually use I2C instead of RSB. RSB mode is initialized by the boot loader. There is no easy way for the kernel to switch it back. what about the device-tree bindings in this case? We can deal with it if someone actually comes up with a practical case needing it. Otherwise things go untested, which is not what we want. ChenYu Regards Martin [0] http://files.pine64.org/doc/datasheet/pine64/AXP803_Datasheet_V1.0.pdf [1] http://wiki.pine64.org/index.php/PINE_A64_Main_Page#Datasheets_for_Components_and_Peripherals
Re: AXP803 I2C support / AXP devicetree-bindings
于 2017年11月7日 GMT+08:00 上午11:13:23, Chen-Yu Tsai 写到: On Tue, Nov 7, 2017 at 6:39 AM, Martin Blumenstingl wrote: Hello, recently I discovered that there are some X-Powers AXP chips that support both, Allwinner's own "RSB" as well as the I2C ("TWSI" in the datasheet) busses. one chip that supports both interfaces is the AXP803 the datasheet is linked in the public PINE64 wiki: [1] (direct link: [0]) All the RSB based PMICs support both modes. They start in I2C mode when cold booted. I think it starts at a vendor-customized mode. In all PMICs sold with Allwinner SoCs the mode is predefined to RSB. In fact many registers in AXPs are vendor-customizable, see the datasheets. currently the "x-powers,axp803" binding is "RSB" bus specific as it's currently only listed in drivers/mfd/axp20x-rsb.c was there a discussion about supporting both, the "RSB" and I2C bus for one chip (for example the AXP803) in the past (I couldn't find anything online)? No. None of the boards actually use I2C instead of RSB. RSB mode is initialized by the boot loader. There is no easy way for the kernel to switch it back. what about the device-tree bindings in this case? We can deal with it if someone actually comes up with a practical case needing it. Otherwise things go untested, which is not what we want. ChenYu Regards Martin [0] http://files.pine64.org/doc/datasheet/pine64/AXP803_Datasheet_V1.0.pdf [1] http://wiki.pine64.org/index.php/PINE_A64_Main_Page#Datasheets_for_Components_and_Peripherals
Re: [linux-sunxi] Re: [PATCH] ARM: sun8i: h2+: add support for Banana Pi M2 Zero board
在 2017-11-02 23:50,Maxime Ripard 写道: On Thu, Nov 02, 2017 at 05:07:30PM +0800, Icenowy Zheng wrote: > > + { > > + pinctrl-names = "default"; > > + pinctrl-0 = <_pins_a>; > > + vmmc-supply = <_vcc3v3>; > > + bus-width = <4>; > > + /* > > + * In different revisions the board have different card detect > > + * configuration. > > + */ > > Which ones? In the sample batch (1.2V fixed voltage) the card detect is normal (PF6 low as inserted), however in the final batch (1.1V/1.3V switchable) it's inverted at PF6 (high as inserted). Then just use the final version's. > > + { > > + usb0_id_det-gpios = <_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ > > + /* USB OTG VBUS is directly connected to 5V without any regulators > > */ > > So it cannot operate in OTG, but it's host only? It can operate in OTG -- you can power the board via the OTG port, as the VBUS is not gated from 5V at all, so 5V power at VBUS will power up the board. Yes, it's a bit unsafe, but the board designer did it. What will provide the 5v in the first place then if a USB device is connected to the micro-USB connector? There're two micro-USB connectors, one is power-only and another is OTG. The Vbus of these two connectors are connected together, so the external USB device will be powered just by the power input from the power-only USB port. Maxime
Re: [linux-sunxi] Re: [PATCH] ARM: sun8i: h2+: add support for Banana Pi M2 Zero board
在 2017-11-02 23:50,Maxime Ripard 写道: On Thu, Nov 02, 2017 at 05:07:30PM +0800, Icenowy Zheng wrote: > > + { > > + pinctrl-names = "default"; > > + pinctrl-0 = <_pins_a>; > > + vmmc-supply = <_vcc3v3>; > > + bus-width = <4>; > > + /* > > + * In different revisions the board have different card detect > > + * configuration. > > + */ > > Which ones? In the sample batch (1.2V fixed voltage) the card detect is normal (PF6 low as inserted), however in the final batch (1.1V/1.3V switchable) it's inverted at PF6 (high as inserted). Then just use the final version's. > > + { > > + usb0_id_det-gpios = <_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ > > + /* USB OTG VBUS is directly connected to 5V without any regulators > > */ > > So it cannot operate in OTG, but it's host only? It can operate in OTG -- you can power the board via the OTG port, as the VBUS is not gated from 5V at all, so 5V power at VBUS will power up the board. Yes, it's a bit unsafe, but the board designer did it. What will provide the 5v in the first place then if a USB device is connected to the micro-USB connector? There're two micro-USB connectors, one is power-only and another is OTG. The Vbus of these two connectors are connected together, so the external USB device will be powered just by the power input from the power-only USB port. Maxime
Re: [linux-sunxi] Re: [PATCH] ARM: sun8i: h2+: add support for Banana Pi M2 Zero board
在 2017-11-02 17:02,Maxime Ripard 写道: Hi, On Wed, Nov 01, 2017 at 05:38:14PM +0800, Icenowy Zheng wrote: Banana Pi M2 Zero board is a H2+-based board by Sinovoip, with a form factor and GPIO holes similar to Raspberry Pi Zero. It features: - Allwinner H2+ SoC - Single-chip (16-bit) 512MiB DDR3 DRAM - Ampak AP6212 Wi-Fi/Bluetooth module - MicroSD slot - Two MicroUSB Type-B ports (one can only be used to power the board and the other features OTG functionality) - Two keys, a reset and a GPIO-connected key. - HDMI Type-C (miniHDMI) connector connected to the HDMI part of H2+. - CSI connector to connect the camera sensor provided by Sinovoip. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts| 156 + 2 files changed, 157 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 3a5b79fd8198..803dbdf03916 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -930,6 +930,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a83t-bananapi-m3.dtb \ sun8i-a83t-cubietruck-plus.dtb \ sun8i-a83t-tbs-a711.dtb \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ sun8i-h2-plus-orangepi-zero.dtb \ sun8i-h3-bananapi-m2-plus.dtb \ sun8i-h3-beelink-x2.dtb \ diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts new file mode 100644 index ..414258da4308 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2017 Icenowy Zheng <icen...@aosc.io> + * + * Based on sun8i-h3-bananapi-m2-plus.dts, which is: + * Copyright (C) 2016 Chen-Yu Tsai <w...@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Banana Pi BPI-M2-Zero"; + compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus"; + + aliases { + serial0 = + serial1 = + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; This property is useless + + pwr_led { + label = "bananapi-m2-zero:red:pwr"; + gpios = <_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; Same thing here. + + sw4 { That node
Re: [linux-sunxi] Re: [PATCH] ARM: sun8i: h2+: add support for Banana Pi M2 Zero board
在 2017-11-02 17:02,Maxime Ripard 写道: Hi, On Wed, Nov 01, 2017 at 05:38:14PM +0800, Icenowy Zheng wrote: Banana Pi M2 Zero board is a H2+-based board by Sinovoip, with a form factor and GPIO holes similar to Raspberry Pi Zero. It features: - Allwinner H2+ SoC - Single-chip (16-bit) 512MiB DDR3 DRAM - Ampak AP6212 Wi-Fi/Bluetooth module - MicroSD slot - Two MicroUSB Type-B ports (one can only be used to power the board and the other features OTG functionality) - Two keys, a reset and a GPIO-connected key. - HDMI Type-C (miniHDMI) connector connected to the HDMI part of H2+. - CSI connector to connect the camera sensor provided by Sinovoip. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts| 156 + 2 files changed, 157 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 3a5b79fd8198..803dbdf03916 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -930,6 +930,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a83t-bananapi-m3.dtb \ sun8i-a83t-cubietruck-plus.dtb \ sun8i-a83t-tbs-a711.dtb \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ sun8i-h2-plus-orangepi-zero.dtb \ sun8i-h3-bananapi-m2-plus.dtb \ sun8i-h3-beelink-x2.dtb \ diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts new file mode 100644 index ..414258da4308 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2017 Icenowy Zheng + * + * Based on sun8i-h3-bananapi-m2-plus.dts, which is: + * Copyright (C) 2016 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Banana Pi BPI-M2-Zero"; + compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus"; + + aliases { + serial0 = + serial1 = + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; This property is useless + + pwr_led { + label = "bananapi-m2-zero:red:pwr"; + gpios = <_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; Same thing here. + + sw4 { That node should be called power. + label = "power"; +
Re: [PATCH v2 00/10] Allwinner H3/H5/A64(DE2) SimpleFB support
在 2017-10-27 23:06,Icenowy Zheng 写道: This patchset adds support for the SimpleFB on Allwinner SoCs with "Display Engine 2.0". PATCH 1 to PATCH 3 are DE2 CCU fixes for H3/H5 SoCs. PATCH 4 adds the pipeline strings for DE2 SimpleFB. PATCH 5 to 7 adds necessary device tree nodes (DE2 CCU and SimpleFB) for H3/H5 SoCs. PATCH 8 to 10 are for Allwinner A64 SoC to enable SimpleFB. Icenowy Zheng (10): dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3 clk: sunxi-ng: add support for Allwinner H3 DE2 CCU clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU dt-bindings: simplefb-sunxi: add pipelines for DE2 ARM: sun8i: h3/h5: add DE2 CCU device node for H3 arm64: allwinner: h5: add compatible string for DE2 CCU ARM: sunxi: h3/h5: add simplefb nodes dt-bindings: add binding for A64 DE2 CCU SRAM arm64: allwinner: a64: add DE2 CCU for A64 SoC arm64: allwinner: a64: add simplefb for A64 SoC Maxime, could you review and, if possible, apply the H3/5 part of this patchset? Thanks! Icenowy .../devicetree/bindings/clock/sun8i-de2.txt| 10 +++- .../bindings/display/simple-framebuffer-sunxi.txt | 4 ++ arch/arm/boot/dts/sun8i-h3.dtsi| 4 ++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 43 ++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 65 ++ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 ++ drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 53 +- 7 files changed, 178 insertions(+), 5 deletions(-)
Re: [PATCH v2 00/10] Allwinner H3/H5/A64(DE2) SimpleFB support
在 2017-10-27 23:06,Icenowy Zheng 写道: This patchset adds support for the SimpleFB on Allwinner SoCs with "Display Engine 2.0". PATCH 1 to PATCH 3 are DE2 CCU fixes for H3/H5 SoCs. PATCH 4 adds the pipeline strings for DE2 SimpleFB. PATCH 5 to 7 adds necessary device tree nodes (DE2 CCU and SimpleFB) for H3/H5 SoCs. PATCH 8 to 10 are for Allwinner A64 SoC to enable SimpleFB. Icenowy Zheng (10): dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3 clk: sunxi-ng: add support for Allwinner H3 DE2 CCU clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU dt-bindings: simplefb-sunxi: add pipelines for DE2 ARM: sun8i: h3/h5: add DE2 CCU device node for H3 arm64: allwinner: h5: add compatible string for DE2 CCU ARM: sunxi: h3/h5: add simplefb nodes dt-bindings: add binding for A64 DE2 CCU SRAM arm64: allwinner: a64: add DE2 CCU for A64 SoC arm64: allwinner: a64: add simplefb for A64 SoC Maxime, could you review and, if possible, apply the H3/5 part of this patchset? Thanks! Icenowy .../devicetree/bindings/clock/sun8i-de2.txt| 10 +++- .../bindings/display/simple-framebuffer-sunxi.txt | 4 ++ arch/arm/boot/dts/sun8i-h3.dtsi| 4 ++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 43 ++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 65 ++ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 ++ drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 53 +- 7 files changed, 178 insertions(+), 5 deletions(-)
Re: [PATCH 0/2] Add a regmap to Allwinner R40 CCU to export GMAC register
在 2017-11-02 15:11,Stephen Boyd 写道: On 10/09, Icenowy Zheng wrote: 于 2017年10月9日 GMT+08:00 下午3:18:09, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Fri, Oct 06, 2017 at 06:33:31AM +, Icenowy Zheng wrote: >> In the CCU of the Allwinner R40 SoC, there's a GMAC configuration >register, >> which is intended to be accessed by the dwmac-sun8i driver. On SoCs >already >> supported by the driver the register is placed in the syscon rather >than >> the CCU. >> >> As CCU is a critical part of the SoC, so write to it should be >strictly >> limited. A regmap with restricted write permission is created by the >R40 >> CCU driver, and can be get with dev_get_regmap. In order to tie the >regmap >> to the CCU device, the R40 CCU is now a platform driver, so a >platform >> device is created for it (and then tied with the regmap). >> >> The first patch does the conversion of the driver to a platform >driver, >> and the second patch adds the regmap. > >I'd like to see first what you want to do with it. Export the GMAC configuration register to dwmac-sun8i. Is this series going to be reposted? Yes, thanks.
Re: [PATCH 0/2] Add a regmap to Allwinner R40 CCU to export GMAC register
在 2017-11-02 15:11,Stephen Boyd 写道: On 10/09, Icenowy Zheng wrote: 于 2017年10月9日 GMT+08:00 下午3:18:09, Maxime Ripard 写到: >On Fri, Oct 06, 2017 at 06:33:31AM +0000, Icenowy Zheng wrote: >> In the CCU of the Allwinner R40 SoC, there's a GMAC configuration >register, >> which is intended to be accessed by the dwmac-sun8i driver. On SoCs >already >> supported by the driver the register is placed in the syscon rather >than >> the CCU. >> >> As CCU is a critical part of the SoC, so write to it should be >strictly >> limited. A regmap with restricted write permission is created by the >R40 >> CCU driver, and can be get with dev_get_regmap. In order to tie the >regmap >> to the CCU device, the R40 CCU is now a platform driver, so a >platform >> device is created for it (and then tied with the regmap). >> >> The first patch does the conversion of the driver to a platform >driver, >> and the second patch adds the regmap. > >I'd like to see first what you want to do with it. Export the GMAC configuration register to dwmac-sun8i. Is this series going to be reposted? Yes, thanks.
[PATCH] ARM: sun8i: h2+: add support for Banana Pi M2 Zero board
Banana Pi M2 Zero board is a H2+-based board by Sinovoip, with a form factor and GPIO holes similar to Raspberry Pi Zero. It features: - Allwinner H2+ SoC - Single-chip (16-bit) 512MiB DDR3 DRAM - Ampak AP6212 Wi-Fi/Bluetooth module - MicroSD slot - Two MicroUSB Type-B ports (one can only be used to power the board and the other features OTG functionality) - Two keys, a reset and a GPIO-connected key. - HDMI Type-C (miniHDMI) connector connected to the HDMI part of H2+. - CSI connector to connect the camera sensor provided by Sinovoip. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts| 156 + 2 files changed, 157 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 3a5b79fd8198..803dbdf03916 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -930,6 +930,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a83t-bananapi-m3.dtb \ sun8i-a83t-cubietruck-plus.dtb \ sun8i-a83t-tbs-a711.dtb \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ sun8i-h2-plus-orangepi-zero.dtb \ sun8i-h3-bananapi-m2-plus.dtb \ sun8i-h3-beelink-x2.dtb \ diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts new file mode 100644 index ..414258da4308 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2017 Icenowy Zheng <icen...@aosc.io> + * + * Based on sun8i-h3-bananapi-m2-plus.dts, which is: + * Copyright (C) 2016 Chen-Yu Tsai <w...@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Banana Pi BPI-M2-Zero"; + compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus"; + + aliases { + serial0 = + serial1 = + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + pwr_led { + label = "bananapi-m2-zero:red:pwr"; + gpios = <_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + + sw4 { + label = "power"; + linux,code = ; + gpios = <_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; + + wifi
[PATCH] ARM: sun8i: h2+: add support for Banana Pi M2 Zero board
Banana Pi M2 Zero board is a H2+-based board by Sinovoip, with a form factor and GPIO holes similar to Raspberry Pi Zero. It features: - Allwinner H2+ SoC - Single-chip (16-bit) 512MiB DDR3 DRAM - Ampak AP6212 Wi-Fi/Bluetooth module - MicroSD slot - Two MicroUSB Type-B ports (one can only be used to power the board and the other features OTG functionality) - Two keys, a reset and a GPIO-connected key. - HDMI Type-C (miniHDMI) connector connected to the HDMI part of H2+. - CSI connector to connect the camera sensor provided by Sinovoip. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts| 156 + 2 files changed, 157 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 3a5b79fd8198..803dbdf03916 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -930,6 +930,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a83t-bananapi-m3.dtb \ sun8i-a83t-cubietruck-plus.dtb \ sun8i-a83t-tbs-a711.dtb \ + sun8i-h2-plus-bananapi-m2-zero.dtb \ sun8i-h2-plus-orangepi-zero.dtb \ sun8i-h3-bananapi-m2-plus.dtb \ sun8i-h3-beelink-x2.dtb \ diff --git a/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts new file mode 100644 index ..414258da4308 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts @@ -0,0 +1,156 @@ +/* + * Copyright (C) 2017 Icenowy Zheng + * + * Based on sun8i-h3-bananapi-m2-plus.dts, which is: + * Copyright (C) 2016 Chen-Yu Tsai + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Banana Pi BPI-M2-Zero"; + compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus"; + + aliases { + serial0 = + serial1 = + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + + pwr_led { + label = "bananapi-m2-zero:red:pwr"; + gpios = <_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + + sw4 { + label = "power"; + linux,code = ; + gpios = <_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwr
[PATCH v2 10/10] arm64: allwinner: a64: add simplefb for A64 SoC
The A64 SoC features two display pipelines, one has a LCD output, the other has a HDMI output. Add support for simplefb for these pipelines on A64 SoC. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 31 +++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 03a46da0f0fa..65ffd94441a1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -42,9 +42,11 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include #include #include #include +#include #include / { @@ -52,6 +54,35 @@ #address-cells = <1>; #size-cells = <1>; + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer-lcd { + compatible = "allwinner,simple-framebuffer", +"simple-framebuffer"; + allwinner,pipeline = "mixer0-lcd0"; + clocks = <_clocks CLK_BUS_MIXER0>, +< CLK_BUS_TCON0>, < CLK_BUS_TCON0>, +<_clocks CLK_MIXER0>, +< CLK_TCON0>; + status = "disabled"; + }; + + framebuffer-hdmi { + compatible = "allwinner,simple-framebuffer", +"simple-framebuffer"; + allwinner,pipeline = "mixer1-lcd1-hdmi"; + clocks = <_clocks CLK_BUS_MIXER1>, +< CLK_BUS_TCON1>, < CLK_BUS_HDMI>, +<_clocks CLK_MIXER1>, +< CLK_TCON1>, < CLK_HDMI>, +< CLK_HDMI_DDC>; + status = "disabled"; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; -- 2.13.6
[PATCH v2 10/10] arm64: allwinner: a64: add simplefb for A64 SoC
The A64 SoC features two display pipelines, one has a LCD output, the other has a HDMI output. Add support for simplefb for these pipelines on A64 SoC. Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 31 +++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 03a46da0f0fa..65ffd94441a1 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -42,9 +42,11 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include #include #include #include +#include #include / { @@ -52,6 +54,35 @@ #address-cells = <1>; #size-cells = <1>; + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer-lcd { + compatible = "allwinner,simple-framebuffer", +"simple-framebuffer"; + allwinner,pipeline = "mixer0-lcd0"; + clocks = <_clocks CLK_BUS_MIXER0>, +< CLK_BUS_TCON0>, < CLK_BUS_TCON0>, +<_clocks CLK_MIXER0>, +< CLK_TCON0>; + status = "disabled"; + }; + + framebuffer-hdmi { + compatible = "allwinner,simple-framebuffer", +"simple-framebuffer"; + allwinner,pipeline = "mixer1-lcd1-hdmi"; + clocks = <_clocks CLK_BUS_MIXER1>, +< CLK_BUS_TCON1>, < CLK_BUS_HDMI>, +<_clocks CLK_MIXER1>, +< CLK_TCON1>, < CLK_HDMI>, +< CLK_HDMI_DDC>; + status = "disabled"; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; -- 2.13.6
[PATCH v2 09/10] arm64: allwinner: a64: add DE2 CCU for A64 SoC
The A64 SoC features a DE2 CCU like the one in H5, but needs to claim a section of SRAM (SRAM C) to be accessed. Adds the device tree nodes for the SRAM controller and the DE2 CCU. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 34 +++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 062040ec2fed..03a46da0f0fa 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -130,6 +130,40 @@ #size-cells = <1>; ranges; + display_clocks: clock@100 { + compatible = "allwinner,sun50i-a64-de2-clk"; + reg = <0x0100 0x10>; + clocks = < CLK_DE>, +< CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = < RST_BUS_DE>; + allwinner,sram = <_sram>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + sram-controller@1c0 { + compatible = "allwinner,sun50i-a64-sram-controller"; + reg = <0x01c0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@18000 { + compatible = "mmio-sram"; + reg = <0x00018000 0x28000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00018000 0x28000>; + + de2_sram: sram-section@0 { + compatible = "allwinner,sun50i-a64-sram-c"; + reg = <0x 0x28000>; + }; + }; + }; + syscon: syscon@1c0 { compatible = "allwinner,sun50i-a64-system-controller", "syscon"; -- 2.13.6
[PATCH v2 09/10] arm64: allwinner: a64: add DE2 CCU for A64 SoC
The A64 SoC features a DE2 CCU like the one in H5, but needs to claim a section of SRAM (SRAM C) to be accessed. Adds the device tree nodes for the SRAM controller and the DE2 CCU. Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 34 +++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 062040ec2fed..03a46da0f0fa 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -130,6 +130,40 @@ #size-cells = <1>; ranges; + display_clocks: clock@100 { + compatible = "allwinner,sun50i-a64-de2-clk"; + reg = <0x0100 0x10>; + clocks = < CLK_DE>, +< CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = < RST_BUS_DE>; + allwinner,sram = <_sram>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + sram-controller@1c0 { + compatible = "allwinner,sun50i-a64-sram-controller"; + reg = <0x01c0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@18000 { + compatible = "mmio-sram"; + reg = <0x00018000 0x28000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x00018000 0x28000>; + + de2_sram: sram-section@0 { + compatible = "allwinner,sun50i-a64-sram-c"; + reg = <0x 0x28000>; + }; + }; + }; + syscon: syscon@1c0 { compatible = "allwinner,sun50i-a64-system-controller", "syscon"; -- 2.13.6
[PATCH v2 08/10] dt-bindings: add binding for A64 DE2 CCU SRAM
A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be claimed, otherwise the whole DE2 memory zone cannot be accessed (kept to all 0). Add binding for this, in order to make the DE2 CCU able to claim the SRAM and enable access to the DE2 clock and reset registers. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Adds description of the situation when the SRAM is not claimed. Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt index f2fa87c4765c..a7d558a2b9b2 100644 --- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt +++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt @@ -6,6 +6,7 @@ Required properties : - "allwinner,sun8i-a83t-de2-clk" - "allwinner,sun8i-h3-de2-clk" - "allwinner,sun8i-v3s-de2-clk" + - "allwinner,sun50i-a64-de2-clk" - "allwinner,sun50i-h5-de2-clk" - reg: Must contain the registers base address and length @@ -18,6 +19,10 @@ Required properties : - #clock-cells : must contain 1 - #reset-cells : must contain 1 +Additional required properties for "allwinner,sun50i-a64-de2-clk" : +- allwinner,sram: See Documentation/devicetree/bindings/sram/sunxi-sram.txt, + should be the SRAM C section on A64 SoC. + Example: de2_clocks: clock@100 { compatible = "allwinner,sun8i-h3-de2-clk"; -- 2.13.6
[PATCH v2 08/10] dt-bindings: add binding for A64 DE2 CCU SRAM
A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be claimed, otherwise the whole DE2 memory zone cannot be accessed (kept to all 0). Add binding for this, in order to make the DE2 CCU able to claim the SRAM and enable access to the DE2 clock and reset registers. Signed-off-by: Icenowy Zheng --- Changes in v2: - Adds description of the situation when the SRAM is not claimed. Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt index f2fa87c4765c..a7d558a2b9b2 100644 --- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt +++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt @@ -6,6 +6,7 @@ Required properties : - "allwinner,sun8i-a83t-de2-clk" - "allwinner,sun8i-h3-de2-clk" - "allwinner,sun8i-v3s-de2-clk" + - "allwinner,sun50i-a64-de2-clk" - "allwinner,sun50i-h5-de2-clk" - reg: Must contain the registers base address and length @@ -18,6 +19,10 @@ Required properties : - #clock-cells : must contain 1 - #reset-cells : must contain 1 +Additional required properties for "allwinner,sun50i-a64-de2-clk" : +- allwinner,sram: See Documentation/devicetree/bindings/sram/sunxi-sram.txt, + should be the SRAM C section on A64 SoC. + Example: de2_clocks: clock@100 { compatible = "allwinner,sun8i-h3-de2-clk"; -- 2.13.6
[PATCH v2 07/10] ARM: sunxi: h3/h5: add simplefb nodes
The H3/H5 SoCs have a HDMI output and a TV Composite output. Add simplefb nodes for these outputs. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 29 + 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 367319d22116..2ce0c3bb9896 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -53,6 +53,35 @@ #address-cells = <1>; #size-cells = <1>; + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer-hdmi { + compatible = "allwinner,simple-framebuffer", +"simple-framebuffer"; + allwinner,pipeline = "mixer0-lcd0-hdmi"; + clocks = <_clocks CLK_BUS_MIXER0>, +< CLK_BUS_TCON0>, < CLK_BUS_HDMI>, +<_clocks CLK_MIXER0>, +< CLK_TCON0>, < CLK_HDMI>, +< CLK_HDMI_DDC>; + status = "disabled"; + }; + + framebuffer-tve { + compatible = "allwinner,simple-framebuffer", +"simple-framebuffer"; + allwinner,pipeline = "mixer1-lcd1-tve"; + clocks = <_clocks CLK_BUS_MIXER1>, +< CLK_BUS_TCON1>, < CLK_BUS_TVE>, +<_clocks CLK_MIXER1>, +< CLK_TVE>; + status = "disabled"; + }; + }; + clocks { #address-cells = <1>; #size-cells = <1>; -- 2.13.6
[PATCH v2 07/10] ARM: sunxi: h3/h5: add simplefb nodes
The H3/H5 SoCs have a HDMI output and a TV Composite output. Add simplefb nodes for these outputs. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 29 + 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 367319d22116..2ce0c3bb9896 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -53,6 +53,35 @@ #address-cells = <1>; #size-cells = <1>; + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer-hdmi { + compatible = "allwinner,simple-framebuffer", +"simple-framebuffer"; + allwinner,pipeline = "mixer0-lcd0-hdmi"; + clocks = <_clocks CLK_BUS_MIXER0>, +< CLK_BUS_TCON0>, < CLK_BUS_HDMI>, +<_clocks CLK_MIXER0>, +< CLK_TCON0>, < CLK_HDMI>, +< CLK_HDMI_DDC>; + status = "disabled"; + }; + + framebuffer-tve { + compatible = "allwinner,simple-framebuffer", +"simple-framebuffer"; + allwinner,pipeline = "mixer1-lcd1-tve"; + clocks = <_clocks CLK_BUS_MIXER1>, +< CLK_BUS_TCON1>, < CLK_BUS_TVE>, +<_clocks CLK_MIXER1>, +< CLK_TVE>; + status = "disabled"; + }; + }; + clocks { #address-cells = <1>; #size-cells = <1>; -- 2.13.6
[PATCH v2 06/10] arm64: allwinner: h5: add compatible string for DE2 CCU
The DE2 CCU on Allwinner H5 SoC has a slightly different behavior than the one on H3, so the compatible string is not set in the common DTSI file. Add the compatible string of H5 DE2 CCU in H5 DTSI file. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index d9a720bff05d..e237c05cfdb4 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -98,6 +98,10 @@ compatible = "allwinner,sun50i-h5-ccu"; }; +_clocks { + compatible = "allwinner,sun50i-h5-de2-clk"; +}; + { compatible = "allwinner,sun50i-h5-mmc", "allwinner,sun50i-a64-mmc"; -- 2.13.6
[PATCH v2 06/10] arm64: allwinner: h5: add compatible string for DE2 CCU
The DE2 CCU on Allwinner H5 SoC has a slightly different behavior than the one on H3, so the compatible string is not set in the common DTSI file. Add the compatible string of H5 DE2 CCU in H5 DTSI file. Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index d9a720bff05d..e237c05cfdb4 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -98,6 +98,10 @@ compatible = "allwinner,sun50i-h5-ccu"; }; +_clocks { + compatible = "allwinner,sun50i-h5-de2-clk"; +}; + { compatible = "allwinner,sun50i-h5-mmc", "allwinner,sun50i-a64-mmc"; -- 2.13.6
[PATCH v2 04/10] dt-bindings: simplefb-sunxi: add pipelines for DE2
As we're going to add simplefb support for Allwinner SoCs with DE2, add suitable pipeline strings in the device tree binding. Acked-by: Rob Herring <r...@kernel.org> Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Adds Rob's ACK. .../devicetree/bindings/display/simple-framebuffer-sunxi.txt | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/simple-framebuffer-sunxi.txt b/Documentation/devicetree/bindings/display/simple-framebuffer-sunxi.txt index a9168ae6946c..d693b8dc9a62 100644 --- a/Documentation/devicetree/bindings/display/simple-framebuffer-sunxi.txt +++ b/Documentation/devicetree/bindings/display/simple-framebuffer-sunxi.txt @@ -15,6 +15,10 @@ Required properties: "de_be1-lcd1" "de_be0-lcd0-hdmi" "de_be1-lcd1-hdmi" + "mixer0-lcd0" + "mixer0-lcd0-hdmi" + "mixer1-lcd1-hdmi" + "mixer1-lcd1-tve" Example: -- 2.13.6
[PATCH v2 05/10] ARM: sun8i: h3/h5: add DE2 CCU device node for H3
The DE2 in H3/H5 has a clock control unit in it, and the behavior is slightly different between H3 and H5. Add the common parts in H3/H5 DTSI, and add the compatible string in H3 DTSI. The compatible string of H5 DE2 CCU will be added in a separated patch. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Use H3 DE2 CCU compatible as it's discovered that H3 and A83T DE2 CCU are not equal. arch/arm/boot/dts/sun8i-h3.dtsi| 4 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 14 ++ 2 files changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..8495deecedad 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -85,6 +85,10 @@ compatible = "allwinner,sun8i-h3-ccu"; }; +_clocks { + compatible = "allwinner,sun8i-h3-de2-clk"; +}; + { compatible = "allwinner,sun7i-a20-mmc"; clocks = < CLK_BUS_MMC0>, diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index d7a71e726a9f..367319d22116 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -40,9 +40,11 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include #include #include #include +#include #include #include @@ -85,6 +87,18 @@ #size-cells = <1>; ranges; + display_clocks: clock@100 { + /* compatible is in per SoC .dtsi file */ + reg = <0x0100 0x10>; + clocks = < CLK_DE>, +< CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = < RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + syscon: syscon@1c0 { compatible = "allwinner,sun8i-h3-system-controller", "syscon"; -- 2.13.6
[PATCH v2 04/10] dt-bindings: simplefb-sunxi: add pipelines for DE2
As we're going to add simplefb support for Allwinner SoCs with DE2, add suitable pipeline strings in the device tree binding. Acked-by: Rob Herring Signed-off-by: Icenowy Zheng --- Changes in v2: - Adds Rob's ACK. .../devicetree/bindings/display/simple-framebuffer-sunxi.txt | 4 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/simple-framebuffer-sunxi.txt b/Documentation/devicetree/bindings/display/simple-framebuffer-sunxi.txt index a9168ae6946c..d693b8dc9a62 100644 --- a/Documentation/devicetree/bindings/display/simple-framebuffer-sunxi.txt +++ b/Documentation/devicetree/bindings/display/simple-framebuffer-sunxi.txt @@ -15,6 +15,10 @@ Required properties: "de_be1-lcd1" "de_be0-lcd0-hdmi" "de_be1-lcd1-hdmi" + "mixer0-lcd0" + "mixer0-lcd0-hdmi" + "mixer1-lcd1-hdmi" + "mixer1-lcd1-tve" Example: -- 2.13.6
[PATCH v2 05/10] ARM: sun8i: h3/h5: add DE2 CCU device node for H3
The DE2 in H3/H5 has a clock control unit in it, and the behavior is slightly different between H3 and H5. Add the common parts in H3/H5 DTSI, and add the compatible string in H3 DTSI. The compatible string of H5 DE2 CCU will be added in a separated patch. Signed-off-by: Icenowy Zheng --- Changes in v2: - Use H3 DE2 CCU compatible as it's discovered that H3 and A83T DE2 CCU are not equal. arch/arm/boot/dts/sun8i-h3.dtsi| 4 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 14 ++ 2 files changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..8495deecedad 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -85,6 +85,10 @@ compatible = "allwinner,sun8i-h3-ccu"; }; +_clocks { + compatible = "allwinner,sun8i-h3-de2-clk"; +}; + { compatible = "allwinner,sun7i-a20-mmc"; clocks = < CLK_BUS_MMC0>, diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index d7a71e726a9f..367319d22116 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -40,9 +40,11 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include #include #include #include +#include #include #include @@ -85,6 +87,18 @@ #size-cells = <1>; ranges; + display_clocks: clock@100 { + /* compatible is in per SoC .dtsi file */ + reg = <0x0100 0x10>; + clocks = < CLK_DE>, +< CLK_BUS_DE>; + clock-names = "mod", + "bus"; + resets = < RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + syscon: syscon@1c0 { compatible = "allwinner,sun8i-h3-system-controller", "syscon"; -- 2.13.6
[PATCH v2 03/10] clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU
The clocks of A64/H5 SoCs in the DE2 CCU is the same as the clocks in H3 DE2 CCU rather than the A83T DE2 CCU (the parent of them is the DE module clock). Fix this by change the clock descriptions to use the clocks of H3. Fixes: 763c5bd045b1 ("clk: sunxi-ng: add support for DE2 CCU") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index 2db5d4e00ea7..468d1abaf0ee 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -177,10 +177,10 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = { }; static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = { - .ccu_clks = sun8i_a83t_de2_clks, - .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks), + .ccu_clks = sun8i_h3_de2_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks), - .hw_clks= _a83t_de2_hw_clks, + .hw_clks= _h3_de2_hw_clks, .resets = sun50i_a64_de2_resets, .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets), -- 2.13.6
[PATCH v2 03/10] clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU
The clocks of A64/H5 SoCs in the DE2 CCU is the same as the clocks in H3 DE2 CCU rather than the A83T DE2 CCU (the parent of them is the DE module clock). Fix this by change the clock descriptions to use the clocks of H3. Fixes: 763c5bd045b1 ("clk: sunxi-ng: add support for DE2 CCU") Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index 2db5d4e00ea7..468d1abaf0ee 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -177,10 +177,10 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = { }; static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = { - .ccu_clks = sun8i_a83t_de2_clks, - .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks), + .ccu_clks = sun8i_h3_de2_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks), - .hw_clks= _a83t_de2_hw_clks, + .hw_clks= _h3_de2_hw_clks, .resets = sun50i_a64_de2_resets, .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets), -- 2.13.6
[PATCH v2 02/10] clk: sunxi-ng: add support for Allwinner H3 DE2 CCU
Allwinner H3 features a DE2 CCU like the one on A83T, however the parent of the clocks is the DE module clock, not the PLL_DE clock. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 47 1 file changed, 47 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index 5cc9d9952121..2db5d4e00ea7 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -41,6 +41,8 @@ static SUNXI_CCU_GATE(wb_clk, "wb", "wb-div", static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4, CLK_SET_RATE_PARENT); +static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4, + CLK_SET_RATE_PARENT); static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4, CLK_SET_RATE_PARENT); @@ -65,6 +67,20 @@ static struct ccu_common *sun8i_a83t_de2_clks[] = { _div_a83_clk.common, }; +static struct ccu_common *sun8i_h3_de2_clks[] = { + _clk.common, + _clk.common, + _clk.common, + + _mixer0_clk.common, + _mixer1_clk.common, + _wb_clk.common, + + _div_clk.common, + _div_clk.common, + _div_clk.common, +}; + static struct ccu_common *sun8i_v3s_de2_clks[] = { _clk.common, _clk.common, @@ -93,6 +109,23 @@ static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = { .num= CLK_NUMBER, }; +static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = { + .hws= { + [CLK_MIXER0]= _clk.common.hw, + [CLK_MIXER1]= _clk.common.hw, + [CLK_WB]= _clk.common.hw, + + [CLK_BUS_MIXER0]= _mixer0_clk.common.hw, + [CLK_BUS_MIXER1]= _mixer1_clk.common.hw, + [CLK_BUS_WB]= _wb_clk.common.hw, + + [CLK_MIXER0_DIV]= _div_clk.common.hw, + [CLK_MIXER1_DIV]= _div_clk.common.hw, + [CLK_WB_DIV]= _div_clk.common.hw, + }, + .num= CLK_NUMBER, +}; + static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = { .hws= { [CLK_MIXER0]= _clk.common.hw, @@ -133,6 +166,16 @@ static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = { .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), }; +static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = { + .ccu_clks = sun8i_h3_de2_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks), + + .hw_clks= _h3_de2_hw_clks, + + .resets = sun8i_a83t_de2_resets, + .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), +}; + static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = { .ccu_clks = sun8i_a83t_de2_clks, .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks), @@ -238,6 +281,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = { .data = _a83t_de2_clk_desc, }, { + .compatible = "allwinner,sun8i-h3-de2-clk", + .data = _h3_de2_clk_desc, + }, + { .compatible = "allwinner,sun8i-v3s-de2-clk", .data = _v3s_de2_clk_desc, }, -- 2.13.6
[PATCH v2 02/10] clk: sunxi-ng: add support for Allwinner H3 DE2 CCU
Allwinner H3 features a DE2 CCU like the one on A83T, however the parent of the clocks is the DE module clock, not the PLL_DE clock. Add support for it. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 47 1 file changed, 47 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index 5cc9d9952121..2db5d4e00ea7 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -41,6 +41,8 @@ static SUNXI_CCU_GATE(wb_clk, "wb", "wb-div", static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4, CLK_SET_RATE_PARENT); +static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4, + CLK_SET_RATE_PARENT); static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4, CLK_SET_RATE_PARENT); @@ -65,6 +67,20 @@ static struct ccu_common *sun8i_a83t_de2_clks[] = { _div_a83_clk.common, }; +static struct ccu_common *sun8i_h3_de2_clks[] = { + _clk.common, + _clk.common, + _clk.common, + + _mixer0_clk.common, + _mixer1_clk.common, + _wb_clk.common, + + _div_clk.common, + _div_clk.common, + _div_clk.common, +}; + static struct ccu_common *sun8i_v3s_de2_clks[] = { _clk.common, _clk.common, @@ -93,6 +109,23 @@ static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = { .num= CLK_NUMBER, }; +static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = { + .hws= { + [CLK_MIXER0]= _clk.common.hw, + [CLK_MIXER1]= _clk.common.hw, + [CLK_WB]= _clk.common.hw, + + [CLK_BUS_MIXER0]= _mixer0_clk.common.hw, + [CLK_BUS_MIXER1]= _mixer1_clk.common.hw, + [CLK_BUS_WB]= _wb_clk.common.hw, + + [CLK_MIXER0_DIV]= _div_clk.common.hw, + [CLK_MIXER1_DIV]= _div_clk.common.hw, + [CLK_WB_DIV]= _div_clk.common.hw, + }, + .num= CLK_NUMBER, +}; + static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = { .hws= { [CLK_MIXER0]= _clk.common.hw, @@ -133,6 +166,16 @@ static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = { .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), }; +static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = { + .ccu_clks = sun8i_h3_de2_clks, + .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks), + + .hw_clks= _h3_de2_hw_clks, + + .resets = sun8i_a83t_de2_resets, + .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), +}; + static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = { .ccu_clks = sun8i_a83t_de2_clks, .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks), @@ -238,6 +281,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = { .data = _a83t_de2_clk_desc, }, { + .compatible = "allwinner,sun8i-h3-de2-clk", + .data = _h3_de2_clk_desc, + }, + { .compatible = "allwinner,sun8i-v3s-de2-clk", .data = _v3s_de2_clk_desc, }, -- 2.13.6
[PATCH v2 01/10] dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3
The DE2 CCU is different on A83T and H3 -- the parent of the clocks on A83T is PLL_DE but on H3 it's the DE module clock. This is not noticed when I develop the DE2 CCU driver. Fix the binding by using different compatibles for A83T and H3, adding notes for the PLL_DE usage on A83T, and change the binding example's compatible from A83T to H3 (as it specifies the DE module clock). Fixes: ed74f8a8a679 ("dt-bindings: add binding for the Allwinner DE2 CCU") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt index 631d27cd89d6..f2fa87c4765c 100644 --- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt +++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt @@ -4,13 +4,14 @@ Allwinner Display Engine 2.0 Clock Control Binding Required properties : - compatible: must contain one of the following compatibles: - "allwinner,sun8i-a83t-de2-clk" + - "allwinner,sun8i-h3-de2-clk" - "allwinner,sun8i-v3s-de2-clk" - "allwinner,sun50i-h5-de2-clk" - reg: Must contain the registers base address and length - clocks: phandle to the clocks feeding the display engine subsystem. Three are needed: - - "mod": the display engine module clock + - "mod": the display engine module clock (on A83T it's the DE PLL) - "bus": the bus clock for the whole display engine subsystem - clock-names: Must contain the clock names described just above - resets: phandle to the reset control for the display engine subsystem. @@ -19,7 +20,7 @@ Required properties : Example: de2_clocks: clock@100 { - compatible = "allwinner,sun8i-a83t-de2-clk"; + compatible = "allwinner,sun8i-h3-de2-clk"; reg = <0x0100 0x10>; clocks = < CLK_BUS_DE>, < CLK_DE>; -- 2.13.6
[PATCH v2 01/10] dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3
The DE2 CCU is different on A83T and H3 -- the parent of the clocks on A83T is PLL_DE but on H3 it's the DE module clock. This is not noticed when I develop the DE2 CCU driver. Fix the binding by using different compatibles for A83T and H3, adding notes for the PLL_DE usage on A83T, and change the binding example's compatible from A83T to H3 (as it specifies the DE module clock). Fixes: ed74f8a8a679 ("dt-bindings: add binding for the Allwinner DE2 CCU") Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt index 631d27cd89d6..f2fa87c4765c 100644 --- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt +++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt @@ -4,13 +4,14 @@ Allwinner Display Engine 2.0 Clock Control Binding Required properties : - compatible: must contain one of the following compatibles: - "allwinner,sun8i-a83t-de2-clk" + - "allwinner,sun8i-h3-de2-clk" - "allwinner,sun8i-v3s-de2-clk" - "allwinner,sun50i-h5-de2-clk" - reg: Must contain the registers base address and length - clocks: phandle to the clocks feeding the display engine subsystem. Three are needed: - - "mod": the display engine module clock + - "mod": the display engine module clock (on A83T it's the DE PLL) - "bus": the bus clock for the whole display engine subsystem - clock-names: Must contain the clock names described just above - resets: phandle to the reset control for the display engine subsystem. @@ -19,7 +20,7 @@ Required properties : Example: de2_clocks: clock@100 { - compatible = "allwinner,sun8i-a83t-de2-clk"; + compatible = "allwinner,sun8i-h3-de2-clk"; reg = <0x0100 0x10>; clocks = < CLK_BUS_DE>, < CLK_DE>; -- 2.13.6
[PATCH v2 00/10] Allwinner H3/H5/A64(DE2) SimpleFB support
This patchset adds support for the SimpleFB on Allwinner SoCs with "Display Engine 2.0". PATCH 1 to PATCH 3 are DE2 CCU fixes for H3/H5 SoCs. PATCH 4 adds the pipeline strings for DE2 SimpleFB. PATCH 5 to 7 adds necessary device tree nodes (DE2 CCU and SimpleFB) for H3/H5 SoCs. PATCH 8 to 10 are for Allwinner A64 SoC to enable SimpleFB. Icenowy Zheng (10): dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3 clk: sunxi-ng: add support for Allwinner H3 DE2 CCU clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU dt-bindings: simplefb-sunxi: add pipelines for DE2 ARM: sun8i: h3/h5: add DE2 CCU device node for H3 arm64: allwinner: h5: add compatible string for DE2 CCU ARM: sunxi: h3/h5: add simplefb nodes dt-bindings: add binding for A64 DE2 CCU SRAM arm64: allwinner: a64: add DE2 CCU for A64 SoC arm64: allwinner: a64: add simplefb for A64 SoC .../devicetree/bindings/clock/sun8i-de2.txt| 10 +++- .../bindings/display/simple-framebuffer-sunxi.txt | 4 ++ arch/arm/boot/dts/sun8i-h3.dtsi| 4 ++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 43 ++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 65 ++ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 ++ drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 53 +- 7 files changed, 178 insertions(+), 5 deletions(-) -- 2.13.6
[PATCH v2 00/10] Allwinner H3/H5/A64(DE2) SimpleFB support
This patchset adds support for the SimpleFB on Allwinner SoCs with "Display Engine 2.0". PATCH 1 to PATCH 3 are DE2 CCU fixes for H3/H5 SoCs. PATCH 4 adds the pipeline strings for DE2 SimpleFB. PATCH 5 to 7 adds necessary device tree nodes (DE2 CCU and SimpleFB) for H3/H5 SoCs. PATCH 8 to 10 are for Allwinner A64 SoC to enable SimpleFB. Icenowy Zheng (10): dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3 clk: sunxi-ng: add support for Allwinner H3 DE2 CCU clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU dt-bindings: simplefb-sunxi: add pipelines for DE2 ARM: sun8i: h3/h5: add DE2 CCU device node for H3 arm64: allwinner: h5: add compatible string for DE2 CCU ARM: sunxi: h3/h5: add simplefb nodes dt-bindings: add binding for A64 DE2 CCU SRAM arm64: allwinner: a64: add DE2 CCU for A64 SoC arm64: allwinner: a64: add simplefb for A64 SoC .../devicetree/bindings/clock/sun8i-de2.txt| 10 +++- .../bindings/display/simple-framebuffer-sunxi.txt | 4 ++ arch/arm/boot/dts/sun8i-h3.dtsi| 4 ++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 43 ++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 65 ++ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 ++ drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 53 +- 7 files changed, 178 insertions(+), 5 deletions(-) -- 2.13.6
[PATCH v2 1/5] ARM: sun8i: r40: add USB host port nodes for R40
From: Icenowy Zheng <icen...@aosc.xyz> Allwinner R40 SoC features a USB OTG port and two USB HOST ports. Add support for the host ports in the DTSI file. The OTG controller still cannot work with existing compatibles, and needs more investigation. So it's not added yet. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- Changes in v2: - Dropped the bogus OHCI resources in EHCI device node. arch/arm/boot/dts/sun8i-r40.dtsi | 72 1 file changed, 72 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index d5a6745409ae..19f270a9f3b1 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -173,6 +173,78 @@ #size-cells = <0>; }; + usbphy: phy@1c13400 { + compatible = "allwinner,sun8i-r40-usb-phy"; + reg = <0x01c13400 0x14>, + <0x01c14800 0x4>, + <0x01c19800 0x4>, + <0x01c1c800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2"; + clocks = < CLK_USB_PHY0>, +< CLK_USB_PHY1>, +< CLK_USB_PHY2>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy"; + resets = < RST_USB_PHY0>, +< RST_USB_PHY1>, +< RST_USB_PHY2>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci1: usb@1c19000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c19000 0x100>; + interrupts = ; + clocks = < CLK_BUS_EHCI1>; + resets = < RST_BUS_EHCI1>; + phys = < 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@1c19400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c19400 0x100>; + interrupts = ; + clocks = < CLK_BUS_OHCI1>, +< CLK_USB_OHCI1>; + resets = < RST_BUS_OHCI1>; + phys = < 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@1c1c000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = ; + clocks = < CLK_BUS_EHCI2>; + resets = < RST_BUS_EHCI2>; + phys = < 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@1c1c400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = ; + clocks = < CLK_BUS_OHCI2>, +< CLK_USB_OHCI2>; + resets = < RST_BUS_OHCI2>; + phys = < 2>; + phy-names = "usb"; + status = "disabled"; + }; + ccu: clock@1c2 { compatible = "allwinner,sun8i-r40-ccu"; reg = <0x01c2 0x400>; -- 2.13.6
[PATCH v2 1/5] ARM: sun8i: r40: add USB host port nodes for R40
From: Icenowy Zheng Allwinner R40 SoC features a USB OTG port and two USB HOST ports. Add support for the host ports in the DTSI file. The OTG controller still cannot work with existing compatibles, and needs more investigation. So it's not added yet. Signed-off-by: Icenowy Zheng --- Changes in v2: - Dropped the bogus OHCI resources in EHCI device node. arch/arm/boot/dts/sun8i-r40.dtsi | 72 1 file changed, 72 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index d5a6745409ae..19f270a9f3b1 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -173,6 +173,78 @@ #size-cells = <0>; }; + usbphy: phy@1c13400 { + compatible = "allwinner,sun8i-r40-usb-phy"; + reg = <0x01c13400 0x14>, + <0x01c14800 0x4>, + <0x01c19800 0x4>, + <0x01c1c800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2"; + clocks = < CLK_USB_PHY0>, +< CLK_USB_PHY1>, +< CLK_USB_PHY2>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy"; + resets = < RST_USB_PHY0>, +< RST_USB_PHY1>, +< RST_USB_PHY2>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci1: usb@1c19000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c19000 0x100>; + interrupts = ; + clocks = < CLK_BUS_EHCI1>; + resets = < RST_BUS_EHCI1>; + phys = < 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@1c19400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c19400 0x100>; + interrupts = ; + clocks = < CLK_BUS_OHCI1>, +< CLK_USB_OHCI1>; + resets = < RST_BUS_OHCI1>; + phys = < 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@1c1c000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = ; + clocks = < CLK_BUS_EHCI2>; + resets = < RST_BUS_EHCI2>; + phys = < 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@1c1c400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = ; + clocks = < CLK_BUS_OHCI2>, +< CLK_USB_OHCI2>; + resets = < RST_BUS_OHCI2>; + phys = < 2>; + phy-names = "usb"; + status = "disabled"; + }; + ccu: clock@1c2 { compatible = "allwinner,sun8i-r40-ccu"; reg = <0x01c2 0x400>; -- 2.13.6
[PATCH v2 5/5] ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry
Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A ports, and it's connected to the USB1 port of the SoC. Enable it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index fe16fc0eb518..45c17c8c5915 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -87,6 +87,10 @@ }; }; + { + status = "okay"; +}; + { status = "okay"; @@ -98,6 +102,10 @@ }; }; + { + status = "okay"; +}; + #include "axp22x.dtsi" _aldo3 { @@ -171,3 +179,8 @@ pinctrl-0 = <_pb_pins>; status = "okay"; }; + + { + usb1_vbus-supply = <_vcc5v0>; + status = "okay"; +}; -- 2.13.6
[PATCH v2 5/5] ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry
Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A ports, and it's connected to the USB1 port of the SoC. Enable it. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index fe16fc0eb518..45c17c8c5915 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -87,6 +87,10 @@ }; }; + { + status = "okay"; +}; + { status = "okay"; @@ -98,6 +102,10 @@ }; }; + { + status = "okay"; +}; + #include "axp22x.dtsi" _aldo3 { @@ -171,3 +179,8 @@ pinctrl-0 = <_pb_pins>; status = "okay"; }; + + { + usb1_vbus-supply = <_vcc5v0>; + status = "okay"; +}; -- 2.13.6
[PATCH v2 4/5] ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra
From: Icenowy Zheng <icen...@aosc.xyz> Banana Pi M2 Ultra board features two USB host ports, connected to the two USB host ports on the SoC. Add support for them. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 22 ++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 035599d870b9..8c5efe2a9881 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -93,6 +93,14 @@ }; }; + { + status = "okay"; +}; + + { + status = "okay"; +}; + { status = "okay"; @@ -180,8 +188,22 @@ status = "okay"; }; + { + status = "okay"; +}; + + { + status = "okay"; +}; + { pinctrl-names = "default"; pinctrl-0 = <_pb_pins>; status = "okay"; }; + + { + usb1_vbus-supply = <_vcc5v0>; + usb2_vbus-supply = <_vcc5v0>; + status = "okay"; +}; -- 2.13.6
[PATCH v2 4/5] ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra
From: Icenowy Zheng Banana Pi M2 Ultra board features two USB host ports, connected to the two USB host ports on the SoC. Add support for them. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 22 ++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 035599d870b9..8c5efe2a9881 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -93,6 +93,14 @@ }; }; + { + status = "okay"; +}; + + { + status = "okay"; +}; + { status = "okay"; @@ -180,8 +188,22 @@ status = "okay"; }; + { + status = "okay"; +}; + + { + status = "okay"; +}; + { pinctrl-names = "default"; pinctrl-0 = <_pb_pins>; status = "okay"; }; + + { + usb1_vbus-supply = <_vcc5v0>; + usb2_vbus-supply = <_vcc5v0>; + status = "okay"; +}; -- 2.13.6
[PATCH v2 0/5] Allwinner R40 USB host support (DT part)
This patchset adds support for the USB host ports on Allwiner R40, and enable them on Banana Pi M2 Ultra and Berry boards. The first patch adds USB PHY and EHCI/OHCI nodes to the R40 DTSI. The second and third patch adds 5V regulator for the two boards, and the fourth and fifth patch finally adds USB host ports support. Icenowy Zheng (5): ARM: sun8i: r40: add USB host port nodes for R40 ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 31 ++ arch/arm/boot/dts/sun8i-r40.dtsi | 72 +++ arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 22 +++ 3 files changed, 125 insertions(+) -- 2.13.6
[PATCH v2 0/5] Allwinner R40 USB host support (DT part)
This patchset adds support for the USB host ports on Allwiner R40, and enable them on Banana Pi M2 Ultra and Berry boards. The first patch adds USB PHY and EHCI/OHCI nodes to the R40 DTSI. The second and third patch adds 5V regulator for the two boards, and the fourth and fifth patch finally adds USB host ports support. Icenowy Zheng (5): ARM: sun8i: r40: add USB host port nodes for R40 ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 31 ++ arch/arm/boot/dts/sun8i-r40.dtsi | 72 +++ arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 22 +++ 3 files changed, 125 insertions(+) -- 2.13.6
[PATCH v2 2/5] ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra
On newer revisions of the Banana Pi M2 Ultra boards, the 5V power output (used by HDMI, SATA and USB) is controller via a GPIO. Add the regulator node for it. Older revisions just have the 5V power output always on, and the GPIO is reserved on these boards. So it won't affect the older revisions. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 7b52608cebe6..035599d870b9 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -78,6 +78,15 @@ }; }; + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <500>; + regulator-max-microvolt = <500>; + gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ -- 2.13.6
[PATCH v2 3/5] ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry
On the Banana Pi M2 Berry board, the 5V power output (used by HDMI, SATA and USB) is controlled via a GPIO. Add regulator node for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index 8a69be2a0842..fe16fc0eb518 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -72,6 +72,15 @@ }; }; + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <500>; + regulator-max-microvolt = <500>; + gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ -- 2.13.6
[PATCH v2 2/5] ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra
On newer revisions of the Banana Pi M2 Ultra boards, the 5V power output (used by HDMI, SATA and USB) is controller via a GPIO. Add the regulator node for it. Older revisions just have the 5V power output always on, and the GPIO is reserved on these boards. So it won't affect the older revisions. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 7b52608cebe6..035599d870b9 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -78,6 +78,15 @@ }; }; + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <500>; + regulator-max-microvolt = <500>; + gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ -- 2.13.6
[PATCH v2 3/5] ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry
On the Banana Pi M2 Berry board, the 5V power output (used by HDMI, SATA and USB) is controlled via a GPIO. Add regulator node for it. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index 8a69be2a0842..fe16fc0eb518 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -72,6 +72,15 @@ }; }; + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <500>; + regulator-max-microvolt = <500>; + gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ -- 2.13.6
[PATCH 1/2] dt-bindings: add binding for A64 DE2 CCU with SRAM section
A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be claimed. Add binding for this. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt index 631d27cd89d6..8b1f86080d3d 100644 --- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt +++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt @@ -5,6 +5,7 @@ Required properties : - compatible: must contain one of the following compatibles: - "allwinner,sun8i-a83t-de2-clk" - "allwinner,sun8i-v3s-de2-clk" + - "allwinner,sun50i-a64-de2-clk" - "allwinner,sun50i-h5-de2-clk" - reg: Must contain the registers base address and length @@ -17,6 +18,10 @@ Required properties : - #clock-cells : must contain 1 - #reset-cells : must contain 1 +Additional required properties for "allwinner,sun50i-a64-de2-clk" : +- allwinner,sram: See Documentation/devicetree/bindings/sram/sunxi-sram.txt, + should be the SRAM C section on A64 SoC. + Example: de2_clocks: clock@100 { compatible = "allwinner,sun8i-a83t-de2-clk"; -- 2.13.6
[PATCH 1/2] dt-bindings: add binding for A64 DE2 CCU with SRAM section
A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be claimed. Add binding for this. Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt index 631d27cd89d6..8b1f86080d3d 100644 --- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt +++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt @@ -5,6 +5,7 @@ Required properties : - compatible: must contain one of the following compatibles: - "allwinner,sun8i-a83t-de2-clk" - "allwinner,sun8i-v3s-de2-clk" + - "allwinner,sun50i-a64-de2-clk" - "allwinner,sun50i-h5-de2-clk" - reg: Must contain the registers base address and length @@ -17,6 +18,10 @@ Required properties : - #clock-cells : must contain 1 - #reset-cells : must contain 1 +Additional required properties for "allwinner,sun50i-a64-de2-clk" : +- allwinner,sram: See Documentation/devicetree/bindings/sram/sunxi-sram.txt, + should be the SRAM C section on A64 SoC. + Example: de2_clocks: clock@100 { compatible = "allwinner,sun8i-a83t-de2-clk"; -- 2.13.6
[PATCH 2/2] clk: sunxi-ng: add support for Allwinner A64 DE2 CCU
Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 32 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index 5cdaf52669e4..2e3a3ca087f7 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "ccu_common.h" #include "ccu_div.h" @@ -148,6 +149,11 @@ static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = { .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), }; +static bool sunxi_de2_clk_has_sram(const struct device_node *node) +{ + return of_device_is_compatible(node, "allwinner,sun50i-a64-de2-clk"); +} + static int sunxi_de2_clk_probe(struct platform_device *pdev) { struct resource *res; @@ -191,11 +197,20 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev) return ret; } + if (sunxi_de2_clk_has_sram(pdev->dev.of_node)) { + ret = sunxi_sram_claim(>dev); + if (ret) { + dev_err(>dev, + "Error couldn't map SRAM to device\n"); + return ret; + } + } + /* The clocks need to be enabled for us to access the registers */ ret = clk_prepare_enable(bus_clk); if (ret) { dev_err(>dev, "Couldn't enable bus clk: %d\n", ret); - return ret; + goto err_release_sram; } ret = clk_prepare_enable(mod_clk); @@ -224,6 +239,10 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev) clk_disable_unprepare(mod_clk); err_disable_bus_clk: clk_disable_unprepare(bus_clk); +err_release_sram: + if (sunxi_de2_clk_has_sram(pdev->dev.of_node)) + sunxi_sram_release(>dev); + return ret; } @@ -237,16 +256,13 @@ static const struct of_device_id sunxi_de2_clk_ids[] = { .data = _v3s_de2_clk_desc, }, { + .compatible = "allwinner,sun50i-a64-de2-clk", + .data = _a64_de2_clk_desc, + }, + { .compatible = "allwinner,sun50i-h5-de2-clk", .data = _a64_de2_clk_desc, }, - /* -* The Allwinner A64 SoC needs some bit to be poke in syscon to make -* DE2 really working. -* So there's currently no A64 compatible here. -* H5 shares the same reset line with A64, so here H5 is using the -* clock description of A64. -*/ { } }; -- 2.13.6
[PATCH 2/2] clk: sunxi-ng: add support for Allwinner A64 DE2 CCU
Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work. Add support for it. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 32 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index 5cdaf52669e4..2e3a3ca087f7 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -17,6 +17,7 @@ #include #include #include +#include #include "ccu_common.h" #include "ccu_div.h" @@ -148,6 +149,11 @@ static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = { .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets), }; +static bool sunxi_de2_clk_has_sram(const struct device_node *node) +{ + return of_device_is_compatible(node, "allwinner,sun50i-a64-de2-clk"); +} + static int sunxi_de2_clk_probe(struct platform_device *pdev) { struct resource *res; @@ -191,11 +197,20 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev) return ret; } + if (sunxi_de2_clk_has_sram(pdev->dev.of_node)) { + ret = sunxi_sram_claim(>dev); + if (ret) { + dev_err(>dev, + "Error couldn't map SRAM to device\n"); + return ret; + } + } + /* The clocks need to be enabled for us to access the registers */ ret = clk_prepare_enable(bus_clk); if (ret) { dev_err(>dev, "Couldn't enable bus clk: %d\n", ret); - return ret; + goto err_release_sram; } ret = clk_prepare_enable(mod_clk); @@ -224,6 +239,10 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev) clk_disable_unprepare(mod_clk); err_disable_bus_clk: clk_disable_unprepare(bus_clk); +err_release_sram: + if (sunxi_de2_clk_has_sram(pdev->dev.of_node)) + sunxi_sram_release(>dev); + return ret; } @@ -237,16 +256,13 @@ static const struct of_device_id sunxi_de2_clk_ids[] = { .data = _v3s_de2_clk_desc, }, { + .compatible = "allwinner,sun50i-a64-de2-clk", + .data = _a64_de2_clk_desc, + }, + { .compatible = "allwinner,sun50i-h5-de2-clk", .data = _a64_de2_clk_desc, }, - /* -* The Allwinner A64 SoC needs some bit to be poke in syscon to make -* DE2 really working. -* So there's currently no A64 compatible here. -* H5 shares the same reset line with A64, so here H5 is using the -* clock description of A64. -*/ { } }; -- 2.13.6
[PATCH] staging: rtl8723bs: hide "nolinked power save" info when not debugging
Currently the rtl8723bs driver will print "nolinked power save enter" and "nolinked power save leave" per minute if it's not connected to any network. These messages are meaningless and annoying to regular users. Hide them when it's not debugging. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/staging/rtl8723bs/core/rtw_pwrctrl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c b/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c index 820a061506cc..80cf5a8b1557 100644 --- a/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c +++ b/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c @@ -34,7 +34,7 @@ void _ips_enter(struct adapter *padapter) if (rf_off == pwrpriv->change_rfpwrstate) { pwrpriv->bpower_saving = true; - DBG_871X_LEVEL(_drv_always_, "nolinked power save enter\n"); + DBG_871X("nolinked power save enter\n"); if (pwrpriv->ips_mode == IPS_LEVEL_2) pwrpriv->bkeepfwalive = true; @@ -73,7 +73,7 @@ int _ips_leave(struct adapter *padapter) if (result == _SUCCESS) { pwrpriv->rf_pwrstate = rf_on; } - DBG_871X_LEVEL(_drv_always_, "nolinked power save leave\n"); + DBG_871X("nolinked power save leave\n"); DBG_871X("==> ips_leave.LED(0x%08x)...\n", rtw_read32(padapter, 0x4c)); pwrpriv->bips_processing = false; -- 2.13.6
[PATCH] staging: rtl8723bs: hide "nolinked power save" info when not debugging
Currently the rtl8723bs driver will print "nolinked power save enter" and "nolinked power save leave" per minute if it's not connected to any network. These messages are meaningless and annoying to regular users. Hide them when it's not debugging. Signed-off-by: Icenowy Zheng --- drivers/staging/rtl8723bs/core/rtw_pwrctrl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c b/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c index 820a061506cc..80cf5a8b1557 100644 --- a/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c +++ b/drivers/staging/rtl8723bs/core/rtw_pwrctrl.c @@ -34,7 +34,7 @@ void _ips_enter(struct adapter *padapter) if (rf_off == pwrpriv->change_rfpwrstate) { pwrpriv->bpower_saving = true; - DBG_871X_LEVEL(_drv_always_, "nolinked power save enter\n"); + DBG_871X("nolinked power save enter\n"); if (pwrpriv->ips_mode == IPS_LEVEL_2) pwrpriv->bkeepfwalive = true; @@ -73,7 +73,7 @@ int _ips_leave(struct adapter *padapter) if (result == _SUCCESS) { pwrpriv->rf_pwrstate = rf_on; } - DBG_871X_LEVEL(_drv_always_, "nolinked power save leave\n"); + DBG_871X("nolinked power save leave\n"); DBG_871X("==> ips_leave.LED(0x%08x)...\n", rtw_read32(padapter, 0x4c)); pwrpriv->bips_processing = false; -- 2.13.6
[PATCH] ARM: sun8i: r40: add watchdog device node
The R40 SoC has a watchdog like the one on A20, in the timer memory zone (which is also the same on A20). Add the device tree node for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-r40.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index d5a6745409ae..ddcb3fff4cd4 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -229,6 +229,11 @@ }; }; + wdt: watchdog@1c20c90 { + compatible = "allwinner,sun4i-a10-wdt"; + reg = <0x01c20c90 0x10>; + }; + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; -- 2.13.6
[PATCH] ARM: sun8i: r40: add watchdog device node
The R40 SoC has a watchdog like the one on A20, in the timer memory zone (which is also the same on A20). Add the device tree node for it. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-r40.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index d5a6745409ae..ddcb3fff4cd4 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -229,6 +229,11 @@ }; }; + wdt: watchdog@1c20c90 { + compatible = "allwinner,sun4i-a10-wdt"; + reg = <0x01c20c90 0x10>; + }; + uart0: serial@1c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; -- 2.13.6
Re: [PATCH 3/6] ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra
于 2017年10月10日 GMT+08:00 上午5:04:07, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Sun, Oct 08, 2017 at 04:29:03AM +, Icenowy Zheng wrote: >> On newer revisions of the Banana Pi M2 Ultra boards, the 5V power >output >> (used by HDMI, SATA and USB) is controller via a GPIO. >> >> Add the regulator node for it. >> >> Older revisions just have the 5V power output always on, and the GPIO >is >> reserved on these boards. So it won't affect the older revisions. >> >> Signed-off-by: Icenowy Zheng <icen...@aosc.io> >> --- >> arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 + >> 1 file changed, 9 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts >b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts >> index 7b52608cebe6..035599d870b9 100644 >> --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts >> +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts >> @@ -78,6 +78,15 @@ >> }; >> }; >> >> +reg_vcc5v0: vcc5v0 { >> +compatible = "regulator-fixed"; >> +regulator-name = "vcc5v0"; >> +regulator-min-microvolt = <500>; >> +regulator-max-microvolt = <500>; >> +gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ >> +enable-active-high; > >This is redundant with the GPIO flag I remember someone suggested me to add this property (maybe wens). It's said that the driver may not process the GPIO_ACTIVE_HIGH correctly. > >Maxime
Re: [PATCH 3/6] ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra
于 2017年10月10日 GMT+08:00 上午5:04:07, Maxime Ripard 写到: >On Sun, Oct 08, 2017 at 04:29:03AM +0000, Icenowy Zheng wrote: >> On newer revisions of the Banana Pi M2 Ultra boards, the 5V power >output >> (used by HDMI, SATA and USB) is controller via a GPIO. >> >> Add the regulator node for it. >> >> Older revisions just have the 5V power output always on, and the GPIO >is >> reserved on these boards. So it won't affect the older revisions. >> >> Signed-off-by: Icenowy Zheng >> --- >> arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 + >> 1 file changed, 9 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts >b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts >> index 7b52608cebe6..035599d870b9 100644 >> --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts >> +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts >> @@ -78,6 +78,15 @@ >> }; >> }; >> >> +reg_vcc5v0: vcc5v0 { >> +compatible = "regulator-fixed"; >> +regulator-name = "vcc5v0"; >> +regulator-min-microvolt = <500>; >> +regulator-max-microvolt = <500>; >> +gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ >> +enable-active-high; > >This is redundant with the GPIO flag I remember someone suggested me to add this property (maybe wens). It's said that the driver may not process the GPIO_ACTIVE_HIGH correctly. > >Maxime
Re: [PATCH 2/6] ARM: sun8i: r40: add USB host port nodes for R40
于 2017年10月10日 GMT+08:00 上午5:03:40, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Sun, Oct 08, 2017 at 04:29:02AM +, Icenowy Zheng wrote: >> From: Icenowy Zheng <icen...@aosc.xyz> >> >> Allwinner R40 SoC features a USB OTG port and two USB HOST ports. >> >> Add support for the host ports in the DTSI file. >> >> The OTG controller still cannot work with existing compatibles, and >needs >> more investigation. So it's not added yet. >> >> Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> >> --- >> arch/arm/boot/dts/sun8i-r40.dtsi | 78 > >> 1 file changed, 78 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi >b/arch/arm/boot/dts/sun8i-r40.dtsi >> index d5a6745409ae..f6c917cbbaac 100644 >> --- a/arch/arm/boot/dts/sun8i-r40.dtsi >> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi >> @@ -173,6 +173,84 @@ >> #size-cells = <0>; >> }; >> >> +usbphy: phy@1c13400 { >> +compatible = "allwinner,sun8i-r40-usb-phy"; >> +reg = <0x01c13400 0x14>, >> + <0x01c14800 0x4>, >> + <0x01c19800 0x4>, >> + <0x01c1c800 0x4>; >> +reg-names = "phy_ctrl", >> +"pmu0", >> +"pmu1", >> +"pmu2"; >> +clocks = < CLK_USB_PHY0>, >> + < CLK_USB_PHY1>, >> + < CLK_USB_PHY2>; >> +clock-names = "usb0_phy", >> + "usb1_phy", >> + "usb2_phy"; >> +resets = < RST_USB_PHY0>, >> + < RST_USB_PHY1>, >> + < RST_USB_PHY2>; >> +reset-names = "usb0_reset", >> + "usb1_reset", >> + "usb2_reset"; >> +status = "disabled"; >> +#phy-cells = <1>; >> +}; >> + >> +ehci1: usb@1c19000 { >> +compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; >> +reg = <0x01c19000 0x100>; > >What is the actual size here? The OHCI/EHCI/PHY-PHY three parts are listed in the user manual as one MMIO zone. The size can be at most 0x400, as the OHCI is at offset 0x400. > >> +interrupts = ; >> +clocks = < CLK_BUS_OHCI1>, >> + < CLK_BUS_EHCI1>, >> + < CLK_USB_OHCI1>; >> +resets = < RST_BUS_OHCI1>, >> + < RST_BUS_EHCI1>; > >Why do you need to take the OHCI resources too? AW's strange design -- without OHCI resources taken EHCI won't work. > >Maxime
Re: [PATCH 2/6] ARM: sun8i: r40: add USB host port nodes for R40
于 2017年10月10日 GMT+08:00 上午5:03:40, Maxime Ripard 写到: >On Sun, Oct 08, 2017 at 04:29:02AM +0000, Icenowy Zheng wrote: >> From: Icenowy Zheng >> >> Allwinner R40 SoC features a USB OTG port and two USB HOST ports. >> >> Add support for the host ports in the DTSI file. >> >> The OTG controller still cannot work with existing compatibles, and >needs >> more investigation. So it's not added yet. >> >> Signed-off-by: Icenowy Zheng >> --- >> arch/arm/boot/dts/sun8i-r40.dtsi | 78 > >> 1 file changed, 78 insertions(+) >> >> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi >b/arch/arm/boot/dts/sun8i-r40.dtsi >> index d5a6745409ae..f6c917cbbaac 100644 >> --- a/arch/arm/boot/dts/sun8i-r40.dtsi >> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi >> @@ -173,6 +173,84 @@ >> #size-cells = <0>; >> }; >> >> +usbphy: phy@1c13400 { >> +compatible = "allwinner,sun8i-r40-usb-phy"; >> +reg = <0x01c13400 0x14>, >> + <0x01c14800 0x4>, >> + <0x01c19800 0x4>, >> + <0x01c1c800 0x4>; >> +reg-names = "phy_ctrl", >> +"pmu0", >> +"pmu1", >> +"pmu2"; >> +clocks = < CLK_USB_PHY0>, >> + < CLK_USB_PHY1>, >> + < CLK_USB_PHY2>; >> +clock-names = "usb0_phy", >> + "usb1_phy", >> + "usb2_phy"; >> +resets = < RST_USB_PHY0>, >> + < RST_USB_PHY1>, >> + < RST_USB_PHY2>; >> +reset-names = "usb0_reset", >> + "usb1_reset", >> + "usb2_reset"; >> +status = "disabled"; >> +#phy-cells = <1>; >> +}; >> + >> +ehci1: usb@1c19000 { >> +compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; >> +reg = <0x01c19000 0x100>; > >What is the actual size here? The OHCI/EHCI/PHY-PHY three parts are listed in the user manual as one MMIO zone. The size can be at most 0x400, as the OHCI is at offset 0x400. > >> +interrupts = ; >> +clocks = < CLK_BUS_OHCI1>, >> + < CLK_BUS_EHCI1>, >> + < CLK_USB_OHCI1>; >> +resets = < RST_BUS_OHCI1>, >> + < RST_BUS_EHCI1>; > >Why do you need to take the OHCI resources too? AW's strange design -- without OHCI resources taken EHCI won't work. > >Maxime
Re: [PATCH 0/2] Add a regmap to Allwinner R40 CCU to export GMAC register
于 2017年10月9日 GMT+08:00 下午3:18:09, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Fri, Oct 06, 2017 at 06:33:31AM +, Icenowy Zheng wrote: >> In the CCU of the Allwinner R40 SoC, there's a GMAC configuration >register, >> which is intended to be accessed by the dwmac-sun8i driver. On SoCs >already >> supported by the driver the register is placed in the syscon rather >than >> the CCU. >> >> As CCU is a critical part of the SoC, so write to it should be >strictly >> limited. A regmap with restricted write permission is created by the >R40 >> CCU driver, and can be get with dev_get_regmap. In order to tie the >regmap >> to the CCU device, the R40 CCU is now a platform driver, so a >platform >> device is created for it (and then tied with the regmap). >> >> The first patch does the conversion of the driver to a platform >driver, >> and the second patch adds the regmap. > >I'd like to see first what you want to do with it. Export the GMAC configuration register to dwmac-sun8i. > >Maxime
Re: [PATCH 0/2] Add a regmap to Allwinner R40 CCU to export GMAC register
于 2017年10月9日 GMT+08:00 下午3:18:09, Maxime Ripard 写到: >On Fri, Oct 06, 2017 at 06:33:31AM +0000, Icenowy Zheng wrote: >> In the CCU of the Allwinner R40 SoC, there's a GMAC configuration >register, >> which is intended to be accessed by the dwmac-sun8i driver. On SoCs >already >> supported by the driver the register is placed in the syscon rather >than >> the CCU. >> >> As CCU is a critical part of the SoC, so write to it should be >strictly >> limited. A regmap with restricted write permission is created by the >R40 >> CCU driver, and can be get with dev_get_regmap. In order to tie the >regmap >> to the CCU device, the R40 CCU is now a platform driver, so a >platform >> device is created for it (and then tied with the regmap). >> >> The first patch does the conversion of the driver to a platform >driver, >> and the second patch adds the regmap. > >I'd like to see first what you want to do with it. Export the GMAC configuration register to dwmac-sun8i. > >Maxime
[PATCH 2/2] ata: ahci_sunxi: add support for R40 SATA controller
Allwinner R40 SoC has an AHCI SATA controller like the one in A10/A20, but with a reset control and two dedicated VDD pins for this controller (one 1.2v and one 2.5v). Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/ata/ahci_sunxi.c | 118 +-- 1 file changed, 115 insertions(+), 3 deletions(-) diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c index b26437430163..a650fd6508be 100644 --- a/drivers/ata/ahci_sunxi.c +++ b/drivers/ata/ahci_sunxi.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "ahci.h" #define DRV_NAME "ahci-sunxi" @@ -58,6 +59,19 @@ MODULE_PARM_DESC(enable_pmp, #define AHCI_P0PHYCR 0x0178 #define AHCI_P0PHYSR 0x017c +struct ahci_sunxi_quirks { + bool has_reset; + bool has_vdd1v2; + bool has_vdd2v5; +}; + +struct ahci_sunxi_data { + const struct ahci_sunxi_quirks *quirks; + struct reset_control *reset; + struct regulator *vdd1v2; + struct regulator *vdd2v5; +}; + static void sunxi_clrbits(void __iomem *reg, u32 clr_val) { u32 reg_val; @@ -179,17 +193,69 @@ static int ahci_sunxi_probe(struct platform_device *pdev) { struct device *dev = >dev; struct ahci_host_priv *hpriv; + struct ahci_sunxi_data *data; int rc; + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->quirks = of_device_get_match_data(dev); + if (!data->quirks) + return -EINVAL; + + if (data->quirks->has_reset) { + data->reset = devm_reset_control_get(dev, NULL); + if (IS_ERR(data->reset)) { + dev_err(dev, "Failed to get reset\n"); + return PTR_ERR(data->reset); + } + } + + if (data->quirks->has_vdd1v2) { + data->vdd1v2 = devm_regulator_get(dev, "vdd1v2"); + if (IS_ERR(data->vdd1v2)) { + dev_err(dev, "Failed to get 1.2v VDD regulator\n"); + return PTR_ERR(data->vdd1v2); + } + } + + if (data->quirks->has_vdd2v5) { + data->vdd2v5 = devm_regulator_get(dev, "vdd2v5"); + if (IS_ERR(data->vdd2v5)) { + dev_err(dev, "Failed to get 2.5v VDD regulator\n"); + return PTR_ERR(data->vdd2v5); + } + } + hpriv = ahci_platform_get_resources(pdev); if (IS_ERR(hpriv)) return PTR_ERR(hpriv); + hpriv->plat_data = data; hpriv->start_engine = ahci_sunxi_start_engine; + if (data->quirks->has_vdd1v2) { + rc = regulator_enable(data->vdd1v2); + if (rc) + return rc; + } + + if (data->quirks->has_vdd2v5) { + rc = regulator_enable(data->vdd2v5); + if (rc) + goto disable_vdd1v2; + } + + if (data->quirks->has_reset) { + rc = reset_control_deassert(data->reset); + if (rc) + goto disable_vdd2v5; + } + rc = ahci_platform_enable_resources(hpriv); if (rc) - return rc; + goto assert_reset; rc = ahci_sunxi_phy_init(dev, hpriv->mmio); if (rc) @@ -215,6 +281,35 @@ static int ahci_sunxi_probe(struct platform_device *pdev) disable_resources: ahci_platform_disable_resources(hpriv); +assert_reset: + if (data->quirks->has_reset) + reset_control_assert(data->reset); +disable_vdd2v5: + if (data->quirks->has_vdd2v5) + regulator_disable(data->vdd2v5); +disable_vdd1v2: + if (data->quirks->has_vdd1v2) + regulator_disable(data->vdd1v2); + return rc; +} + +static int ahci_sunxi_remove(struct platform_device *pdev) +{ + struct device *dev = >dev; + struct ata_host *host = dev_get_drvdata(dev); + struct ahci_host_priv *hpriv = host->private_data; + struct ahci_sunxi_data *data = hpriv->plat_data; + int rc; + + rc = ata_platform_remove_one(pdev); + + if (data->quirks->has_reset) + reset_control_assert(data->reset); + if (data->quirks->has_vdd2v5) + regulator_disable(data->vdd2v5); + if (data->quirks->has_vdd1v2) + regulator_disable(data->vdd1v2); + return rc; } @@ -248,15 +343,32 @@ static int ahci_sunxi_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend, ahci_sunxi_resume); +static const struct ahci_sunxi_quirks sun4i_a
[PATCH 1/2] dt-bindings: add binding for Allwinner R40 SATA AHCI controller
The Allwinner R40 SoC contains a SATA AHCI controller like the one in A10/A20 SoCs, however a reset control and two power supplies are added to it. Add a binding document for it. As a dedicated binding document is needed now for the A10/A20/R40 AHCI controller, drop the A10 compatible line from generic platform AHCI controller binding document. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- .../devicetree/bindings/ata/ahci-platform.txt | 1 - .../bindings/ata/allwinner,sun4i-a10-ahci.txt | 40 ++ 2 files changed, 40 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt index fedc213b5f1a..da6818b2c204 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt @@ -9,7 +9,6 @@ PHYs. Required properties: - compatible: compatible string, one of: - - "allwinner,sun4i-a10-ahci" - "brcm,iproc-ahci" - "hisilicon,hisi-ahci" - "cavium,octeon-7130-ahci" diff --git a/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt b/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt new file mode 100644 index ..0eea78c14ad3 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt @@ -0,0 +1,40 @@ +Allwinner A10/A20/R40 SoC SATA AHCI Controller + +Required properties: +- compatible: compatible string, one of: + - "allwinner,sun4i-a10-ahci" + - "allwinner,sun8i-r40-ahci" +- interrupts: the SATA IRQ +- reg : the register mapping +- clocks: the clocks needed by SATA controller, usually contains + an AHB clock and a mod clock + +Optional properties: +- target-supply : regulator for SATA target power + +Required properties for the following compatibles: + - "allwinner,sun8i-r40-ahci" +- resets: the reset control needed by SATA controller +- vdd1v2-supply : regulator for SATA controller's 1.2V VDD +- vdd2v5-supply : regulator for SATA controller's 2.5V VDD + + +Examples for A10: + ahci: sata@1c18000 { + compatible = "allwinner,sun4i-a10-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = <56>; + clocks = < 0>, <_gates 25>; + target-supply = <_ahci_5v>; + }; + +Examples for R40: + ahci: sata@1c18000 { + compatible = "allwinner,sun8i-r40-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = ; + clocks = < CLK_SATA>, < CLK_BUS_SATA>; + resets = < RST_BUS_SATA>; + vdd1v2-supply = <_eldo3>; + vdd2v5-supply = <_dldo4>; + }; -- 2.13.6
[PATCH 2/2] ata: ahci_sunxi: add support for R40 SATA controller
Allwinner R40 SoC has an AHCI SATA controller like the one in A10/A20, but with a reset control and two dedicated VDD pins for this controller (one 1.2v and one 2.5v). Add support for it. Signed-off-by: Icenowy Zheng --- drivers/ata/ahci_sunxi.c | 118 +-- 1 file changed, 115 insertions(+), 3 deletions(-) diff --git a/drivers/ata/ahci_sunxi.c b/drivers/ata/ahci_sunxi.c index b26437430163..a650fd6508be 100644 --- a/drivers/ata/ahci_sunxi.c +++ b/drivers/ata/ahci_sunxi.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "ahci.h" #define DRV_NAME "ahci-sunxi" @@ -58,6 +59,19 @@ MODULE_PARM_DESC(enable_pmp, #define AHCI_P0PHYCR 0x0178 #define AHCI_P0PHYSR 0x017c +struct ahci_sunxi_quirks { + bool has_reset; + bool has_vdd1v2; + bool has_vdd2v5; +}; + +struct ahci_sunxi_data { + const struct ahci_sunxi_quirks *quirks; + struct reset_control *reset; + struct regulator *vdd1v2; + struct regulator *vdd2v5; +}; + static void sunxi_clrbits(void __iomem *reg, u32 clr_val) { u32 reg_val; @@ -179,17 +193,69 @@ static int ahci_sunxi_probe(struct platform_device *pdev) { struct device *dev = >dev; struct ahci_host_priv *hpriv; + struct ahci_sunxi_data *data; int rc; + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->quirks = of_device_get_match_data(dev); + if (!data->quirks) + return -EINVAL; + + if (data->quirks->has_reset) { + data->reset = devm_reset_control_get(dev, NULL); + if (IS_ERR(data->reset)) { + dev_err(dev, "Failed to get reset\n"); + return PTR_ERR(data->reset); + } + } + + if (data->quirks->has_vdd1v2) { + data->vdd1v2 = devm_regulator_get(dev, "vdd1v2"); + if (IS_ERR(data->vdd1v2)) { + dev_err(dev, "Failed to get 1.2v VDD regulator\n"); + return PTR_ERR(data->vdd1v2); + } + } + + if (data->quirks->has_vdd2v5) { + data->vdd2v5 = devm_regulator_get(dev, "vdd2v5"); + if (IS_ERR(data->vdd2v5)) { + dev_err(dev, "Failed to get 2.5v VDD regulator\n"); + return PTR_ERR(data->vdd2v5); + } + } + hpriv = ahci_platform_get_resources(pdev); if (IS_ERR(hpriv)) return PTR_ERR(hpriv); + hpriv->plat_data = data; hpriv->start_engine = ahci_sunxi_start_engine; + if (data->quirks->has_vdd1v2) { + rc = regulator_enable(data->vdd1v2); + if (rc) + return rc; + } + + if (data->quirks->has_vdd2v5) { + rc = regulator_enable(data->vdd2v5); + if (rc) + goto disable_vdd1v2; + } + + if (data->quirks->has_reset) { + rc = reset_control_deassert(data->reset); + if (rc) + goto disable_vdd2v5; + } + rc = ahci_platform_enable_resources(hpriv); if (rc) - return rc; + goto assert_reset; rc = ahci_sunxi_phy_init(dev, hpriv->mmio); if (rc) @@ -215,6 +281,35 @@ static int ahci_sunxi_probe(struct platform_device *pdev) disable_resources: ahci_platform_disable_resources(hpriv); +assert_reset: + if (data->quirks->has_reset) + reset_control_assert(data->reset); +disable_vdd2v5: + if (data->quirks->has_vdd2v5) + regulator_disable(data->vdd2v5); +disable_vdd1v2: + if (data->quirks->has_vdd1v2) + regulator_disable(data->vdd1v2); + return rc; +} + +static int ahci_sunxi_remove(struct platform_device *pdev) +{ + struct device *dev = >dev; + struct ata_host *host = dev_get_drvdata(dev); + struct ahci_host_priv *hpriv = host->private_data; + struct ahci_sunxi_data *data = hpriv->plat_data; + int rc; + + rc = ata_platform_remove_one(pdev); + + if (data->quirks->has_reset) + reset_control_assert(data->reset); + if (data->quirks->has_vdd2v5) + regulator_disable(data->vdd2v5); + if (data->quirks->has_vdd1v2) + regulator_disable(data->vdd1v2); + return rc; } @@ -248,15 +343,32 @@ static int ahci_sunxi_resume(struct device *dev) static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend, ahci_sunxi_resume); +static const struct ahci_sunxi_quirks sun4i_a10_ahci_quirks = {
[PATCH 1/2] dt-bindings: add binding for Allwinner R40 SATA AHCI controller
The Allwinner R40 SoC contains a SATA AHCI controller like the one in A10/A20 SoCs, however a reset control and two power supplies are added to it. Add a binding document for it. As a dedicated binding document is needed now for the A10/A20/R40 AHCI controller, drop the A10 compatible line from generic platform AHCI controller binding document. Signed-off-by: Icenowy Zheng --- .../devicetree/bindings/ata/ahci-platform.txt | 1 - .../bindings/ata/allwinner,sun4i-a10-ahci.txt | 40 ++ 2 files changed, 40 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt index fedc213b5f1a..da6818b2c204 100644 --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt @@ -9,7 +9,6 @@ PHYs. Required properties: - compatible: compatible string, one of: - - "allwinner,sun4i-a10-ahci" - "brcm,iproc-ahci" - "hisilicon,hisi-ahci" - "cavium,octeon-7130-ahci" diff --git a/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt b/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt new file mode 100644 index ..0eea78c14ad3 --- /dev/null +++ b/Documentation/devicetree/bindings/ata/allwinner,sun4i-a10-ahci.txt @@ -0,0 +1,40 @@ +Allwinner A10/A20/R40 SoC SATA AHCI Controller + +Required properties: +- compatible: compatible string, one of: + - "allwinner,sun4i-a10-ahci" + - "allwinner,sun8i-r40-ahci" +- interrupts: the SATA IRQ +- reg : the register mapping +- clocks: the clocks needed by SATA controller, usually contains + an AHB clock and a mod clock + +Optional properties: +- target-supply : regulator for SATA target power + +Required properties for the following compatibles: + - "allwinner,sun8i-r40-ahci" +- resets: the reset control needed by SATA controller +- vdd1v2-supply : regulator for SATA controller's 1.2V VDD +- vdd2v5-supply : regulator for SATA controller's 2.5V VDD + + +Examples for A10: + ahci: sata@1c18000 { + compatible = "allwinner,sun4i-a10-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = <56>; + clocks = < 0>, <_gates 25>; + target-supply = <_ahci_5v>; + }; + +Examples for R40: + ahci: sata@1c18000 { + compatible = "allwinner,sun8i-r40-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = ; + clocks = < CLK_SATA>, < CLK_BUS_SATA>; + resets = < RST_BUS_SATA>; + vdd1v2-supply = <_eldo3>; + vdd2v5-supply = <_dldo4>; + }; -- 2.13.6
[PATCH 6/6] ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry
Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A ports, and it's connected to the USB1 port of the SoC. Enable it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index fe16fc0eb518..45c17c8c5915 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -87,6 +87,10 @@ }; }; + { + status = "okay"; +}; + { status = "okay"; @@ -98,6 +102,10 @@ }; }; + { + status = "okay"; +}; + #include "axp22x.dtsi" _aldo3 { @@ -171,3 +179,8 @@ pinctrl-0 = <_pb_pins>; status = "okay"; }; + + { + usb1_vbus-supply = <_vcc5v0>; + status = "okay"; +}; -- 2.13.6
[PATCH 6/6] ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry
Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A ports, and it's connected to the USB1 port of the SoC. Enable it. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index fe16fc0eb518..45c17c8c5915 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -87,6 +87,10 @@ }; }; + { + status = "okay"; +}; + { status = "okay"; @@ -98,6 +102,10 @@ }; }; + { + status = "okay"; +}; + #include "axp22x.dtsi" _aldo3 { @@ -171,3 +179,8 @@ pinctrl-0 = <_pb_pins>; status = "okay"; }; + + { + usb1_vbus-supply = <_vcc5v0>; + status = "okay"; +}; -- 2.13.6
[PATCH 4/6] ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry
On the Banana Pi M2 Berry board, the 5V power output (used by HDMI, SATA and USB) is controlled via a GPIO. Add regulator node for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index 8a69be2a0842..fe16fc0eb518 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -72,6 +72,15 @@ }; }; + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <500>; + regulator-max-microvolt = <500>; + gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ -- 2.13.6
[PATCH 2/6] ARM: sun8i: r40: add USB host port nodes for R40
From: Icenowy Zheng <icen...@aosc.xyz> Allwinner R40 SoC features a USB OTG port and two USB HOST ports. Add support for the host ports in the DTSI file. The OTG controller still cannot work with existing compatibles, and needs more investigation. So it's not added yet. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/boot/dts/sun8i-r40.dtsi | 78 1 file changed, 78 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index d5a6745409ae..f6c917cbbaac 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -173,6 +173,84 @@ #size-cells = <0>; }; + usbphy: phy@1c13400 { + compatible = "allwinner,sun8i-r40-usb-phy"; + reg = <0x01c13400 0x14>, + <0x01c14800 0x4>, + <0x01c19800 0x4>, + <0x01c1c800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2"; + clocks = < CLK_USB_PHY0>, +< CLK_USB_PHY1>, +< CLK_USB_PHY2>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy"; + resets = < RST_USB_PHY0>, +< RST_USB_PHY1>, +< RST_USB_PHY2>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci1: usb@1c19000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c19000 0x100>; + interrupts = ; + clocks = < CLK_BUS_OHCI1>, +< CLK_BUS_EHCI1>, +< CLK_USB_OHCI1>; + resets = < RST_BUS_OHCI1>, +< RST_BUS_EHCI1>; + phys = < 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@1c19400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c19400 0x100>; + interrupts = ; + clocks = < CLK_BUS_OHCI1>, +< CLK_USB_OHCI1>; + resets = < RST_BUS_OHCI1>; + phys = < 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@1c1c000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = ; + clocks = < CLK_BUS_OHCI2>, +< CLK_BUS_EHCI2>, +< CLK_USB_OHCI2>; + resets = < RST_BUS_OHCI2>, +< RST_BUS_EHCI2>; + phys = < 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@1c1c400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = ; + clocks = < CLK_BUS_OHCI2>, +< CLK_USB_OHCI2>; + resets = < RST_BUS_OHCI2>; + phys = < 2>; + phy-names = "usb"; + status = "disabled"; + }; + ccu: clock@1c2 { compatible = "allwinner,sun8i-r40-ccu"; reg = <0x01c2 0x400>; -- 2.13.6
[PATCH 3/6] ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra
On newer revisions of the Banana Pi M2 Ultra boards, the 5V power output (used by HDMI, SATA and USB) is controller via a GPIO. Add the regulator node for it. Older revisions just have the 5V power output always on, and the GPIO is reserved on these boards. So it won't affect the older revisions. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 7b52608cebe6..035599d870b9 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -78,6 +78,15 @@ }; }; + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <500>; + regulator-max-microvolt = <500>; + gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ -- 2.13.6
[PATCH 2/6] ARM: sun8i: r40: add USB host port nodes for R40
From: Icenowy Zheng Allwinner R40 SoC features a USB OTG port and two USB HOST ports. Add support for the host ports in the DTSI file. The OTG controller still cannot work with existing compatibles, and needs more investigation. So it's not added yet. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-r40.dtsi | 78 1 file changed, 78 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index d5a6745409ae..f6c917cbbaac 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -173,6 +173,84 @@ #size-cells = <0>; }; + usbphy: phy@1c13400 { + compatible = "allwinner,sun8i-r40-usb-phy"; + reg = <0x01c13400 0x14>, + <0x01c14800 0x4>, + <0x01c19800 0x4>, + <0x01c1c800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2"; + clocks = < CLK_USB_PHY0>, +< CLK_USB_PHY1>, +< CLK_USB_PHY2>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy"; + resets = < RST_USB_PHY0>, +< RST_USB_PHY1>, +< RST_USB_PHY2>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci1: usb@1c19000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c19000 0x100>; + interrupts = ; + clocks = < CLK_BUS_OHCI1>, +< CLK_BUS_EHCI1>, +< CLK_USB_OHCI1>; + resets = < RST_BUS_OHCI1>, +< RST_BUS_EHCI1>; + phys = < 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@1c19400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c19400 0x100>; + interrupts = ; + clocks = < CLK_BUS_OHCI1>, +< CLK_USB_OHCI1>; + resets = < RST_BUS_OHCI1>; + phys = < 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@1c1c000 { + compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = ; + clocks = < CLK_BUS_OHCI2>, +< CLK_BUS_EHCI2>, +< CLK_USB_OHCI2>; + resets = < RST_BUS_OHCI2>, +< RST_BUS_EHCI2>; + phys = < 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@1c1c400 { + compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = ; + clocks = < CLK_BUS_OHCI2>, +< CLK_USB_OHCI2>; + resets = < RST_BUS_OHCI2>; + phys = < 2>; + phy-names = "usb"; + status = "disabled"; + }; + ccu: clock@1c2 { compatible = "allwinner,sun8i-r40-ccu"; reg = <0x01c2 0x400>; -- 2.13.6
[PATCH 3/6] ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra
On newer revisions of the Banana Pi M2 Ultra boards, the 5V power output (used by HDMI, SATA and USB) is controller via a GPIO. Add the regulator node for it. Older revisions just have the 5V power output always on, and the GPIO is reserved on these boards. So it won't affect the older revisions. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 7b52608cebe6..035599d870b9 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -78,6 +78,15 @@ }; }; + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <500>; + regulator-max-microvolt = <500>; + gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ -- 2.13.6
[PATCH 4/6] ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry
On the Banana Pi M2 Berry board, the 5V power output (used by HDMI, SATA and USB) is controlled via a GPIO. Add regulator node for it. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts index 8a69be2a0842..fe16fc0eb518 100644 --- a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -72,6 +72,15 @@ }; }; + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <500>; + regulator-max-microvolt = <500>; + gpio = < 7 23 GPIO_ACTIVE_HIGH>; /* PH23 */ + enable-active-high; + }; + wifi_pwrseq: wifi_pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = < 6 10 GPIO_ACTIVE_LOW>; /* PG10 WIFI_EN */ -- 2.13.6
[PATCH 5/6] ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra
From: Icenowy Zheng <icen...@aosc.xyz> Banana Pi M2 Ultra board features two USB host ports, connected to the two USB host ports on the SoC. Add support for them. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 22 ++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 035599d870b9..8c5efe2a9881 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -93,6 +93,14 @@ }; }; + { + status = "okay"; +}; + + { + status = "okay"; +}; + { status = "okay"; @@ -180,8 +188,22 @@ status = "okay"; }; + { + status = "okay"; +}; + + { + status = "okay"; +}; + { pinctrl-names = "default"; pinctrl-0 = <_pb_pins>; status = "okay"; }; + + { + usb1_vbus-supply = <_vcc5v0>; + usb2_vbus-supply = <_vcc5v0>; + status = "okay"; +}; -- 2.13.6
[PATCH 5/6] ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra
From: Icenowy Zheng Banana Pi M2 Ultra board features two USB host ports, connected to the two USB host ports on the SoC. Add support for them. Signed-off-by: Icenowy Zheng --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 22 ++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 035599d870b9..8c5efe2a9881 100644 --- a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -93,6 +93,14 @@ }; }; + { + status = "okay"; +}; + + { + status = "okay"; +}; + { status = "okay"; @@ -180,8 +188,22 @@ status = "okay"; }; + { + status = "okay"; +}; + + { + status = "okay"; +}; + { pinctrl-names = "default"; pinctrl-0 = <_pb_pins>; status = "okay"; }; + + { + usb1_vbus-supply = <_vcc5v0>; + usb2_vbus-supply = <_vcc5v0>; + status = "okay"; +}; -- 2.13.6
[PATCH 0/6] Allwinner R40 USB host support
This patchset adds support for the USB host ports on Allwiner R40, and enable them on Banana Pi M2 Ultra and Berry boards. The first patch adds R40 support to the USB PHY driver. The second patch adds USB PHY and EHCI/OHCI nodes to the R40 DTSI. The thrid and fourth patch adds 5V regulator for the two boards, and the fifth and sixth patch finally adds USB host ports support. Icenowy Zheng (6): phy: sun4i-usb: add support for R40 USB PHY ARM: sun8i: r40: add USB host port nodes for R40 ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry .../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 + arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 31 + arch/arm/boot/dts/sun8i-r40.dtsi | 78 ++ arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 22 ++ drivers/phy/allwinner/phy-sun4i-usb.c | 12 5 files changed, 144 insertions(+) -- 2.13.6
[PATCH 0/6] Allwinner R40 USB host support
This patchset adds support for the USB host ports on Allwiner R40, and enable them on Banana Pi M2 Ultra and Berry boards. The first patch adds R40 support to the USB PHY driver. The second patch adds USB PHY and EHCI/OHCI nodes to the R40 DTSI. The thrid and fourth patch adds 5V regulator for the two boards, and the fifth and sixth patch finally adds USB host ports support. Icenowy Zheng (6): phy: sun4i-usb: add support for R40 USB PHY ARM: sun8i: r40: add USB host port nodes for R40 ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry .../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 + arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 31 + arch/arm/boot/dts/sun8i-r40.dtsi | 78 ++ arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 22 ++ drivers/phy/allwinner/phy-sun4i-usb.c | 12 5 files changed, 144 insertions(+) -- 2.13.6
[PATCH 1/6] phy: sun4i-usb: add support for R40 USB PHY
Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 + drivers/phy/allwinner/phy-sun4i-usb.c | 12 2 files changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt index cbc7847dbf6c..0f00abd40a50 100644 --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt @@ -11,6 +11,7 @@ Required properties: * allwinner,sun8i-a33-usb-phy * allwinner,sun8i-a83t-usb-phy * allwinner,sun8i-h3-usb-phy + * allwinner,sun8i-r40-usb-phy * allwinner,sun8i-v3s-usb-phy * allwinner,sun50i-a64-usb-phy - reg : a list of offset + length pairs diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 1161e11fb3cf..9df7a2c9ca75 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -112,6 +112,7 @@ enum sun4i_usb_phy_type { sun8i_a33_phy, sun8i_a83t_phy, sun8i_h3_phy, + sun8i_r40_phy, sun8i_v3s_phy, sun50i_a64_phy, }; @@ -919,6 +920,16 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { .phy0_dual_route = true, }; +static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = { + .num_phys = 3, + .type = sun8i_r40_phy, + .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, + .enable_pmu_unk1 = true, + .phy0_dual_route = true, +}; + static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = { .num_phys = 1, .type = sun8i_v3s_phy, @@ -947,6 +958,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = { { .compatible = "allwinner,sun8i-a33-usb-phy", .data = _a33_cfg }, { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = _a83t_cfg }, { .compatible = "allwinner,sun8i-h3-usb-phy", .data = _h3_cfg }, + { .compatible = "allwinner,sun8i-r40-usb-phy", .data = _r40_cfg }, { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = _v3s_cfg }, { .compatible = "allwinner,sun50i-a64-usb-phy", .data = _a64_cfg}, -- 2.13.6
[PATCH 1/6] phy: sun4i-usb: add support for R40 USB PHY
Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs. Add support for it. Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 + drivers/phy/allwinner/phy-sun4i-usb.c | 12 2 files changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt index cbc7847dbf6c..0f00abd40a50 100644 --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt @@ -11,6 +11,7 @@ Required properties: * allwinner,sun8i-a33-usb-phy * allwinner,sun8i-a83t-usb-phy * allwinner,sun8i-h3-usb-phy + * allwinner,sun8i-r40-usb-phy * allwinner,sun8i-v3s-usb-phy * allwinner,sun50i-a64-usb-phy - reg : a list of offset + length pairs diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c index 1161e11fb3cf..9df7a2c9ca75 100644 --- a/drivers/phy/allwinner/phy-sun4i-usb.c +++ b/drivers/phy/allwinner/phy-sun4i-usb.c @@ -112,6 +112,7 @@ enum sun4i_usb_phy_type { sun8i_a33_phy, sun8i_a83t_phy, sun8i_h3_phy, + sun8i_r40_phy, sun8i_v3s_phy, sun50i_a64_phy, }; @@ -919,6 +920,16 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = { .phy0_dual_route = true, }; +static const struct sun4i_usb_phy_cfg sun8i_r40_cfg = { + .num_phys = 3, + .type = sun8i_r40_phy, + .disc_thresh = 3, + .phyctl_offset = REG_PHYCTL_A33, + .dedicated_clocks = true, + .enable_pmu_unk1 = true, + .phy0_dual_route = true, +}; + static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = { .num_phys = 1, .type = sun8i_v3s_phy, @@ -947,6 +958,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = { { .compatible = "allwinner,sun8i-a33-usb-phy", .data = _a33_cfg }, { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = _a83t_cfg }, { .compatible = "allwinner,sun8i-h3-usb-phy", .data = _h3_cfg }, + { .compatible = "allwinner,sun8i-r40-usb-phy", .data = _r40_cfg }, { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = _v3s_cfg }, { .compatible = "allwinner,sun50i-a64-usb-phy", .data = _a64_cfg}, -- 2.13.6
Re: [PATCH review for 4.4 14/24] dmaengine: sun6i: allow build on ARM64 platforms (sun50i)
于 2017年10月8日 GMT+08:00 上午6:37:46, "Levin, Alexander (Sasha Levin)" <alexander.le...@verizon.com> 写到: >From: Icenowy Zheng <icen...@aosc.xyz> > >[ Upstream commit c429ceb1e18252122ba96b52e689dcf87103c186 ] > >As 64-bit Allwinner H5 SoC has the same DMA engine with H3, the DMA >driver should be allowed to be built for ARM64, in order to make it >work on H5. There's no H5 support in 4.4/4.9. This patch can be ignored. > >Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> >Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com> >Acked-by: Chen-Yu Tsai <w...@csie.org> >Signed-off-by: Vinod Koul <vinod.k...@intel.com> >Signed-off-by: Sasha Levin <alexander.le...@verizon.com> >--- > drivers/dma/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > >diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig >index e6cd1a32025a..27b7b3a9bdd2 100644 >--- a/drivers/dma/Kconfig >+++ b/drivers/dma/Kconfig >@@ -158,7 +158,7 @@ config DMA_SUN4I > > config DMA_SUN6I > tristate "Allwinner A31 SoCs DMA support" >- depends on MACH_SUN6I || MACH_SUN8I || COMPILE_TEST >+ depends on MACH_SUN6I || MACH_SUN8I || (ARM64 && ARCH_SUNXI) || >COMPILE_TEST > depends on RESET_CONTROLLER > select DMA_ENGINE > select DMA_VIRTUAL_CHANNELS
Re: [PATCH review for 4.4 14/24] dmaengine: sun6i: allow build on ARM64 platforms (sun50i)
于 2017年10月8日 GMT+08:00 上午6:37:46, "Levin, Alexander (Sasha Levin)" 写到: >From: Icenowy Zheng > >[ Upstream commit c429ceb1e18252122ba96b52e689dcf87103c186 ] > >As 64-bit Allwinner H5 SoC has the same DMA engine with H3, the DMA >driver should be allowed to be built for ARM64, in order to make it >work on H5. There's no H5 support in 4.4/4.9. This patch can be ignored. > >Signed-off-by: Icenowy Zheng >Acked-by: Maxime Ripard >Acked-by: Chen-Yu Tsai >Signed-off-by: Vinod Koul >Signed-off-by: Sasha Levin >--- > drivers/dma/Kconfig | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > >diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig >index e6cd1a32025a..27b7b3a9bdd2 100644 >--- a/drivers/dma/Kconfig >+++ b/drivers/dma/Kconfig >@@ -158,7 +158,7 @@ config DMA_SUN4I > > config DMA_SUN6I > tristate "Allwinner A31 SoCs DMA support" >- depends on MACH_SUN6I || MACH_SUN8I || COMPILE_TEST >+ depends on MACH_SUN6I || MACH_SUN8I || (ARM64 && ARCH_SUNXI) || >COMPILE_TEST > depends on RESET_CONTROLLER > select DMA_ENGINE > select DMA_VIRTUAL_CHANNELS
Re: [PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi
于 2017年10月5日 GMT+08:00 下午2:58:01, Kalle Valo <kv...@codeaurora.org> 写到: >Icenowy Zheng <icen...@aosc.io> writes: > >> 于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard >> <maxime.rip...@free-electrons.com> 写到: >>>On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote: >>>> On 10/4/2017 11:03 AM, Icenowy Zheng wrote: >>>> > >>>> > >>>> > 于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo ><kv...@codeaurora.org> >>>写到: >>>> > > Icenowy Zheng <icen...@aosc.io> writes: >>>> > > >>>> > > > Allwinner XR819 is a SDIO Wi-Fi chip, which has the >>>functionality to >>>> > > use >>>> > > > an out-of-band interrupt pin instead of SDIO in-band >interrupt. >>>> > > > >>>> > > > Add the device tree binding of this chip, in order to make it >>>> > > possible >>>> > > > to add this interrupt pin to device trees. >>>> > > > >>>> > > > Signed-off-by: Icenowy Zheng <icen...@aosc.io> >>>> > > > Acked-by: Rob Herring <r...@kernel.org> >>>> > > > --- >>>> > > > Changes in v3: >>>> > > > - Renames the node name. >>>> > > > - Adds ACK from Rob. >>>> > > > Changes in v2: >>>> > > > - Removed status property in example. >>>> > > > - Added required property reg. >>>> > > > >>>> > > > .../bindings/net/wireless/allwinner,xr819.txt | 38 >>>> > > ++ >>>> > > > 1 file changed, 38 insertions(+) >>>> > > > create mode 100644 >>>> > > >>>Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt >>>> > > >>>> > > Like I asked already last time, AFAICS there is no upstream >xr819 >>>> > > wireless driver in drivers/net/wireless directory. Do we still >>>accept >>>> > > bindings like this for out-of-tree drivers? >>>> > >>>> > See esp8089. >>>> > >>>> > There's also no in-tree driver for it. >>>> >>>> The question is whether we should. The above might be a precedent, >>>but it >>>> may not necessarily be the way to go. The commit message for >esp8089 >>>seems >>>> to hint that there is intent to have an in-tree driver: >>>> >>>> """ >>>> Note that at this point there only is an out of tree driver for >>>this >>>> hardware, there is no clear timeline / path for merging this. >>>Still >>>> I believe it would be good to specify the binding for this in >>>tree >>>> now, so that any future migration to an in tree driver will not >>>cause >>>> compatiblity issues. >>>> >>>> Cc: Icenowy Zheng <icen...@aosc.xyz> >>>> Signed-off-by: Hans de Goede <hdego...@redhat.com> >>>> Signed-off-by: Rob Herring <r...@kernel.org> >>>> """ >>>> >>>> Regardless the bindings are in principle independent of the kernel >>>and just >>>> describing hardware. I think there have been discussions to move >the >>>> bindings to their own repository, but apparently it was decided >>>otherwise. >>> >>>Yeah, I guess especially how it could be merged with the cw1200 >driver >>>would be very relevant to that commit log. >> >> The cw1200 driver seems to still have some legacy platform >> data. Maybe they should also be convert to DT. >> (Or maybe compatible = "allwinner,xr819" is enough, as >> xr819 is a specified variant of cw1200 family) > >Ah, so the upstream cw1200 driver supports xr819? Has anyone tested >that? Or does cw1200 more changes than just adding the DT support? I think the cw1200 driver currently lacks maintain, and the product is already discontinued by ST-E. > >-- >Kalle Valo > >___ >linux-arm-kernel mailing list >linux-arm-ker...@lists.infradead.org >http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi
于 2017年10月5日 GMT+08:00 下午2:58:01, Kalle Valo 写到: >Icenowy Zheng writes: > >> 于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard >> 写到: >>>On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote: >>>> On 10/4/2017 11:03 AM, Icenowy Zheng wrote: >>>> > >>>> > >>>> > 于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo > >>>写到: >>>> > > Icenowy Zheng writes: >>>> > > >>>> > > > Allwinner XR819 is a SDIO Wi-Fi chip, which has the >>>functionality to >>>> > > use >>>> > > > an out-of-band interrupt pin instead of SDIO in-band >interrupt. >>>> > > > >>>> > > > Add the device tree binding of this chip, in order to make it >>>> > > possible >>>> > > > to add this interrupt pin to device trees. >>>> > > > >>>> > > > Signed-off-by: Icenowy Zheng >>>> > > > Acked-by: Rob Herring >>>> > > > --- >>>> > > > Changes in v3: >>>> > > > - Renames the node name. >>>> > > > - Adds ACK from Rob. >>>> > > > Changes in v2: >>>> > > > - Removed status property in example. >>>> > > > - Added required property reg. >>>> > > > >>>> > > > .../bindings/net/wireless/allwinner,xr819.txt | 38 >>>> > > ++ >>>> > > > 1 file changed, 38 insertions(+) >>>> > > > create mode 100644 >>>> > > >>>Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt >>>> > > >>>> > > Like I asked already last time, AFAICS there is no upstream >xr819 >>>> > > wireless driver in drivers/net/wireless directory. Do we still >>>accept >>>> > > bindings like this for out-of-tree drivers? >>>> > >>>> > See esp8089. >>>> > >>>> > There's also no in-tree driver for it. >>>> >>>> The question is whether we should. The above might be a precedent, >>>but it >>>> may not necessarily be the way to go. The commit message for >esp8089 >>>seems >>>> to hint that there is intent to have an in-tree driver: >>>> >>>> """ >>>> Note that at this point there only is an out of tree driver for >>>this >>>> hardware, there is no clear timeline / path for merging this. >>>Still >>>> I believe it would be good to specify the binding for this in >>>tree >>>> now, so that any future migration to an in tree driver will not >>>cause >>>> compatiblity issues. >>>> >>>> Cc: Icenowy Zheng >>>> Signed-off-by: Hans de Goede >>>> Signed-off-by: Rob Herring >>>> """ >>>> >>>> Regardless the bindings are in principle independent of the kernel >>>and just >>>> describing hardware. I think there have been discussions to move >the >>>> bindings to their own repository, but apparently it was decided >>>otherwise. >>> >>>Yeah, I guess especially how it could be merged with the cw1200 >driver >>>would be very relevant to that commit log. >> >> The cw1200 driver seems to still have some legacy platform >> data. Maybe they should also be convert to DT. >> (Or maybe compatible = "allwinner,xr819" is enough, as >> xr819 is a specified variant of cw1200 family) > >Ah, so the upstream cw1200 driver supports xr819? Has anyone tested >that? Or does cw1200 more changes than just adding the DT support? I think the cw1200 driver currently lacks maintain, and the product is already discontinued by ST-E. > >-- >Kalle Valo > >___ >linux-arm-kernel mailing list >linux-arm-ker...@lists.infradead.org >http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
[PATCH v3 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra
From: Chen-Yu Tsai <w...@csie.org> The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The form factor and position of various connectors, leds and buttons is similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same as the latest Banana Pi M64. It features: - X-Powers AXP221s PMIC connected to i2c0 - 2 GB DDR3 DRAM - 8 GB eMMC - micro SD card slot - DC power jack - HDMI output - MIPI DSI connector - 2x USB 2.0 hosts - 1x USB 2.0 OTG - gigabit ethernet with Realtek RTL8211E transceiver - WiFi/Bluetooth with AP6212 chip, with external antenna connector - SATA and power connectors for native SATA support - camera sensor connector - consumer IR receiver - audio out headphone jack - onboard microphone - red, green, and blue LEDs - debug UART pins - Li-Po battery connector - Raspberry Pi B+ compatible GPIO header - power, reset, and boot control buttons This patch adds a dts file that enables UART, MMC and PMIC support. Signed-off-by: Chen-Yu Tsai <w...@csie.org> Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v3: - Added 3.3V vqmmc regulator for mmc2 (eMMC). Changes in v2: - Dropped the vcc5v0 regulator, as it's not used yet. arch/arm/boot/dts/Makefile| 1 + arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 178 ++ 2 files changed, 179 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9cf688d404b8..93b1e63a52af 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -939,6 +939,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-plus2e.dtb \ sun8i-r16-bananapi-m2m.dtb \ sun8i-r16-parrot.dtb \ + sun8i-r40-bananapi-m2-ultra.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb dtb-$(CONFIG_MACH_SUN9I) += \ diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts new file mode 100644 index ..7b52608cebe6 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2017 Chen-Yu Tsai <w...@csie.org> + * Copyright (C) 2017 Icenowy Zheng <icen...@aosc.io> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-r40.dtsi" + +#include + +/ { + model = "Banana Pi BPI-M2-Ultra"; + compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40"; + + aliases { + serial0 = + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pwr-led { + label = "bananapi:red:pwr"; + gpios = < 7 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; +
[PATCH v3 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra
From: Chen-Yu Tsai The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The form factor and position of various connectors, leds and buttons is similar to the Banana Pi M1+, Banana Pi M3, and is exactly the same as the latest Banana Pi M64. It features: - X-Powers AXP221s PMIC connected to i2c0 - 2 GB DDR3 DRAM - 8 GB eMMC - micro SD card slot - DC power jack - HDMI output - MIPI DSI connector - 2x USB 2.0 hosts - 1x USB 2.0 OTG - gigabit ethernet with Realtek RTL8211E transceiver - WiFi/Bluetooth with AP6212 chip, with external antenna connector - SATA and power connectors for native SATA support - camera sensor connector - consumer IR receiver - audio out headphone jack - onboard microphone - red, green, and blue LEDs - debug UART pins - Li-Po battery connector - Raspberry Pi B+ compatible GPIO header - power, reset, and boot control buttons This patch adds a dts file that enables UART, MMC and PMIC support. Signed-off-by: Chen-Yu Tsai Signed-off-by: Icenowy Zheng --- Changes in v3: - Added 3.3V vqmmc regulator for mmc2 (eMMC). Changes in v2: - Dropped the vcc5v0 regulator, as it's not used yet. arch/arm/boot/dts/Makefile| 1 + arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 178 ++ 2 files changed, 179 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9cf688d404b8..93b1e63a52af 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -939,6 +939,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-plus2e.dtb \ sun8i-r16-bananapi-m2m.dtb \ sun8i-r16-parrot.dtb \ + sun8i-r40-bananapi-m2-ultra.dtb \ sun8i-v3s-licheepi-zero.dtb \ sun8i-v3s-licheepi-zero-dock.dtb dtb-$(CONFIG_MACH_SUN9I) += \ diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts new file mode 100644 index ..7b52608cebe6 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2017 Chen-Yu Tsai + * Copyright (C) 2017 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-r40.dtsi" + +#include + +/ { + model = "Banana Pi BPI-M2-Ultra"; + compatible = "sinovoip,bpi-m2-ultra", "allwinner,sun8i-r40"; + + aliases { + serial0 = + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pwr-led { + label = "bananapi:red:pwr"; + gpios = < 7 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led-green { + label = "bananapi:green:user
[PATCH v3 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry
The Banana Pi M2 Ultra is an SBC based on the Allwinner V40 SoC (same as the R40 SoC). The form factor is similar to the Raspberry Pi series. It features: - X-Powers AXP221s PMIC connected to i2c0 - 1GiB DDR3 DRAM - microSD slot - MicroUSB Type-B port for power and connected to usb0 - HDMI output - MIPI DSI connector - 4 USB Type-A ports (connected to the usb1 controller via a hub) - gigabit ethernet with Realtek RTL8211E transceiver - WiFi/Bluetooth with AP6212 module, with external antenna connector - SATA and power connectors for native SATA support - camera sensor connector - audio out headphone jack - red and green LEDs - debug UART pins - Raspberry Pi B+ compatible GPIO header - power and reset buttons This patch adds a dts file that enables UART, MMC and PMIC support. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Dropped the vcc5v0 regulator, as it's not used yet. arch/arm/boot/dts/Makefile| 3 +- arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 164 ++ 2 files changed, 166 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 93b1e63a52af..da3f87b35059 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -941,7 +941,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-r16-parrot.dtb \ sun8i-r40-bananapi-m2-ultra.dtb \ sun8i-v3s-licheepi-zero.dtb \ - sun8i-v3s-licheepi-zero-dock.dtb + sun8i-v3s-licheepi-zero-dock.dtb \ + sun8i-v40-bananapi-m2-berry.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts new file mode 100644 index ..8a69be2a0842 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2017 Icenowy Zheng <icen...@aosc.io> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-r40.dtsi" + +#include + +/ { + model = "Banana Pi M2 Berry"; + compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40"; + + aliases { + serial0 = + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pwr-led { + label = "bananapi:red:pwr"; + gpios = < 7 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led { + label = "bananapi:green:user"; + gpios = < 7 21 GPIO_ACTIVE_HIGH>; + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; +
[PATCH v3 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry
The Banana Pi M2 Ultra is an SBC based on the Allwinner V40 SoC (same as the R40 SoC). The form factor is similar to the Raspberry Pi series. It features: - X-Powers AXP221s PMIC connected to i2c0 - 1GiB DDR3 DRAM - microSD slot - MicroUSB Type-B port for power and connected to usb0 - HDMI output - MIPI DSI connector - 4 USB Type-A ports (connected to the usb1 controller via a hub) - gigabit ethernet with Realtek RTL8211E transceiver - WiFi/Bluetooth with AP6212 module, with external antenna connector - SATA and power connectors for native SATA support - camera sensor connector - audio out headphone jack - red and green LEDs - debug UART pins - Raspberry Pi B+ compatible GPIO header - power and reset buttons This patch adds a dts file that enables UART, MMC and PMIC support. Signed-off-by: Icenowy Zheng --- Changes in v2: - Dropped the vcc5v0 regulator, as it's not used yet. arch/arm/boot/dts/Makefile| 3 +- arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 164 ++ 2 files changed, 166 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 93b1e63a52af..da3f87b35059 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -941,7 +941,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-r16-parrot.dtb \ sun8i-r40-bananapi-m2-ultra.dtb \ sun8i-v3s-licheepi-zero.dtb \ - sun8i-v3s-licheepi-zero-dock.dtb + sun8i-v3s-licheepi-zero-dock.dtb \ + sun8i-v40-bananapi-m2-berry.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts new file mode 100644 index ..8a69be2a0842 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2017 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-r40.dtsi" + +#include + +/ { + model = "Banana Pi M2 Berry"; + compatible = "sinovoip,bpi-m2-berry", "allwinner,sun8i-r40"; + + aliases { + serial0 = + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + pwr-led { + label = "bananapi:red:pwr"; + gpios = < 7 20 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led { + label = "bananapi:green:user"; + gpios = < 7 21 GPIO_ACTIVE_HIGH>; + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = < 6 10 GPIO_ACTIVE_LO
[PATCH v3 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40
From: Chen-Yu Tsai <w...@csie.org> The Allwinner R40 SoC is marketed as the successor to the A20 SoC. The R40 is a smaller chip than the A20, but features the same set of programmable pins, with a couple extra pins and some new pin functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2 GPU. It retains most if not all features from the A20, while adding some new features, such as MIPI DSI output, or updating various hardware blocks, such as DE 2.0. Signed-off-by: Chen-Yu Tsai <w...@csie.org> Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v3: - Dropped all max-frequency properties in MMC nodes. Changes in v2: - Change the MMC frequencies to conservative verified values. - Add fallback R40 compatible for MMC. arch/arm/boot/dts/sun8i-r40.dtsi | 396 +++ 1 file changed, 396 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi new file mode 100644 index ..d5a6745409ae --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -0,0 +1,396 @@ +/* + * Copyright 2017 Chen-Yu Tsai <w...@csie.org> + * Copyright 2017 Icenowy Zheng <icen...@aosc.io> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <>; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <2400>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; +
[PATCH v3 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40
From: Chen-Yu Tsai The Allwinner R40 SoC is marketed as the successor to the A20 SoC. The R40 is a smaller chip than the A20, but features the same set of programmable pins, with a couple extra pins and some new pin functions. The chip features 4 Cortex-A7 cores and a Mali-400 MP2 GPU. It retains most if not all features from the A20, while adding some new features, such as MIPI DSI output, or updating various hardware blocks, such as DE 2.0. Signed-off-by: Chen-Yu Tsai Signed-off-by: Icenowy Zheng --- Changes in v3: - Dropped all max-frequency properties in MMC nodes. Changes in v2: - Change the MMC frequencies to conservative verified values. - Add fallback R40 compatible for MMC. arch/arm/boot/dts/sun8i-r40.dtsi | 396 +++ 1 file changed, 396 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi new file mode 100644 index ..d5a6745409ae --- /dev/null +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -0,0 +1,396 @@ +/* + * Copyright 2017 Chen-Yu Tsai + * Copyright 2017 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <>; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <2400>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + }; + }; + + soc { + compatible = &quo
[PATCH v3 0/3] Basical device tree parts for Allwinner R40 SoC
This patchset adds basical device tree parts for the Allwinner R40 SoC and two boards feature this SoC -- Banana Pi M2 Ultra and Berry (The BPi M2 Berry board uses V40 SoC, which is just a renamed R40). Chen-Yu Tsai (2): ARM: dts: sun8i: Add basic dtsi file for Allwinner R40 ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra Icenowy Zheng (1): ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry arch/arm/boot/dts/Makefile| 4 +- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 178 ++ arch/arm/boot/dts/sun8i-r40.dtsi | 396 ++ arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 164 + 4 files changed, 741 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi create mode 100644 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts -- 2.13.6
[PATCH v3 0/3] Basical device tree parts for Allwinner R40 SoC
This patchset adds basical device tree parts for the Allwinner R40 SoC and two boards feature this SoC -- Banana Pi M2 Ultra and Berry (The BPi M2 Berry board uses V40 SoC, which is just a renamed R40). Chen-Yu Tsai (2): ARM: dts: sun8i: Add basic dtsi file for Allwinner R40 ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra Icenowy Zheng (1): ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry arch/arm/boot/dts/Makefile| 4 +- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 178 ++ arch/arm/boot/dts/sun8i-r40.dtsi | 396 ++ arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 164 + 4 files changed, 741 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts create mode 100644 arch/arm/boot/dts/sun8i-r40.dtsi create mode 100644 arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts -- 2.13.6
[PATCH 1/2] clk: sunxi-ng: r40: rewrite init code to a platform driver
As we need to register a regmap on the R40 CCU, there needs to be a device structure bound to the CCU device node. Rewrite the R40 CCU driver initial code to make it a proper platform driver, thus we will have a platform device bound to it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 37 ++-- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c index 933f2e68f42a..bb94e2c44e86 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c @@ -12,6 +12,7 @@ */ #include +#include #include #include "ccu_common.h" @@ -1250,17 +1251,17 @@ static struct ccu_mux_nb sun8i_r40_cpu_nb = { .bypass_index = 1, /* index of 24 MHz oscillator */ }; -static void __init sun8i_r40_ccu_setup(struct device_node *node) +static int sun8i_r40_ccu_probe(struct platform_device *pdev) { + struct resource *res; void __iomem *reg; u32 val; + int ret; - reg = of_io_request_and_map(node, 0, of_node_full_name(node)); - if (IS_ERR(reg)) { - pr_err("%s: Could not map the clock registers\n", - of_node_full_name(node)); - return; - } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + reg = devm_ioremap_resource(>dev, res); + if (IS_ERR(reg)) + return PTR_ERR(reg); /* Force the PLL-Audio-1x divider to 4 */ val = readl(reg + SUN8I_R40_PLL_AUDIO_REG); @@ -1277,7 +1278,9 @@ static void __init sun8i_r40_ccu_setup(struct device_node *node) val &= ~GENMASK(25, 20); writel(val, reg + SUN8I_R40_USB_CLK_REG); - sunxi_ccu_probe(node, reg, _r40_ccu_desc); + ret = sunxi_ccu_probe(pdev->dev.of_node, reg, _r40_ccu_desc); + if (ret) + return ret; /* Gate then ungate PLL CPU after any rate changes */ ccu_pll_notifier_register(_r40_pll_cpu_nb); @@ -1285,6 +1288,20 @@ static void __init sun8i_r40_ccu_setup(struct device_node *node) /* Reparent CPU during PLL CPU rate changes */ ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, _r40_cpu_nb); + + return 0; } -CLK_OF_DECLARE(sun8i_r40_ccu, "allwinner,sun8i-r40-ccu", - sun8i_r40_ccu_setup); + +static const struct of_device_id sun8i_r40_ccu_ids[] = { + { .compatible = "allwinner,sun8i-r40-ccu" }, + { } +}; + +static struct platform_driver sun8i_r40_ccu_driver = { + .probe = sun8i_r40_ccu_probe, + .driver = { + .name = "sun8i-r40-ccu", + .of_match_table = sun8i_r40_ccu_ids, + }, +}; +builtin_platform_driver(sun8i_r40_ccu_driver); -- 2.13.6
[PATCH 1/2] clk: sunxi-ng: r40: rewrite init code to a platform driver
As we need to register a regmap on the R40 CCU, there needs to be a device structure bound to the CCU device node. Rewrite the R40 CCU driver initial code to make it a proper platform driver, thus we will have a platform device bound to it. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 37 ++-- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c index 933f2e68f42a..bb94e2c44e86 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c @@ -12,6 +12,7 @@ */ #include +#include #include #include "ccu_common.h" @@ -1250,17 +1251,17 @@ static struct ccu_mux_nb sun8i_r40_cpu_nb = { .bypass_index = 1, /* index of 24 MHz oscillator */ }; -static void __init sun8i_r40_ccu_setup(struct device_node *node) +static int sun8i_r40_ccu_probe(struct platform_device *pdev) { + struct resource *res; void __iomem *reg; u32 val; + int ret; - reg = of_io_request_and_map(node, 0, of_node_full_name(node)); - if (IS_ERR(reg)) { - pr_err("%s: Could not map the clock registers\n", - of_node_full_name(node)); - return; - } + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + reg = devm_ioremap_resource(>dev, res); + if (IS_ERR(reg)) + return PTR_ERR(reg); /* Force the PLL-Audio-1x divider to 4 */ val = readl(reg + SUN8I_R40_PLL_AUDIO_REG); @@ -1277,7 +1278,9 @@ static void __init sun8i_r40_ccu_setup(struct device_node *node) val &= ~GENMASK(25, 20); writel(val, reg + SUN8I_R40_USB_CLK_REG); - sunxi_ccu_probe(node, reg, _r40_ccu_desc); + ret = sunxi_ccu_probe(pdev->dev.of_node, reg, _r40_ccu_desc); + if (ret) + return ret; /* Gate then ungate PLL CPU after any rate changes */ ccu_pll_notifier_register(_r40_pll_cpu_nb); @@ -1285,6 +1288,20 @@ static void __init sun8i_r40_ccu_setup(struct device_node *node) /* Reparent CPU during PLL CPU rate changes */ ccu_mux_notifier_register(pll_cpu_clk.common.hw.clk, _r40_cpu_nb); + + return 0; } -CLK_OF_DECLARE(sun8i_r40_ccu, "allwinner,sun8i-r40-ccu", - sun8i_r40_ccu_setup); + +static const struct of_device_id sun8i_r40_ccu_ids[] = { + { .compatible = "allwinner,sun8i-r40-ccu" }, + { } +}; + +static struct platform_driver sun8i_r40_ccu_driver = { + .probe = sun8i_r40_ccu_probe, + .driver = { + .name = "sun8i-r40-ccu", + .of_match_table = sun8i_r40_ccu_ids, + }, +}; +builtin_platform_driver(sun8i_r40_ccu_driver); -- 2.13.6
[PATCH 2/2] clk: sunxi-ng: r40: export a regmap to access the GMAC register
There's a GMAC configuration register, which exists on A64/A83T/H3/H5 in the syscon part, in the CCU of R40 SoC. Export a regmap of the CCU. Read access is not restricted to all registers, but only the GMAC register is allowed to be written. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 32 1 file changed, 32 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c index bb94e2c44e86..df752bf77ff1 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "ccu_common.h" #include "ccu_reset.h" @@ -1251,9 +1252,35 @@ static struct ccu_mux_nb sun8i_r40_cpu_nb = { .bypass_index = 1, /* index of 24 MHz oscillator */ }; +/* + * Add a regmap for the GMAC driver (dwmac-sun8i) to access the + * GMAC configuration register. + * Only this register is allowed to be written, in order to + * prevent overriding critical clock configuration. + */ + +#define SUN8I_R40_GMAC_CFG_REG 0x164 +static bool sun8i_r40_ccu_regmap_writeable_reg(struct device *dev, + unsigned int reg) +{ + if (reg == SUN8I_R40_GMAC_CFG_REG) + return true; + return false; +} + +static struct regmap_config sun8i_r40_ccu_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0x320, /* PLL_LOCK_CTRL_REG */ + + .writeable_reg = sun8i_r40_ccu_regmap_writeable_reg, +}; + static int sun8i_r40_ccu_probe(struct platform_device *pdev) { struct resource *res; + struct regmap *regmap; void __iomem *reg; u32 val; int ret; @@ -1278,6 +1305,11 @@ static int sun8i_r40_ccu_probe(struct platform_device *pdev) val &= ~GENMASK(25, 20); writel(val, reg + SUN8I_R40_USB_CLK_REG); + regmap = devm_regmap_init_mmio(>dev, reg, + _r40_ccu_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + ret = sunxi_ccu_probe(pdev->dev.of_node, reg, _r40_ccu_desc); if (ret) return ret; -- 2.13.6
[PATCH 2/2] clk: sunxi-ng: r40: export a regmap to access the GMAC register
There's a GMAC configuration register, which exists on A64/A83T/H3/H5 in the syscon part, in the CCU of R40 SoC. Export a regmap of the CCU. Read access is not restricted to all registers, but only the GMAC register is allowed to be written. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 32 1 file changed, 32 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c index bb94e2c44e86..df752bf77ff1 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "ccu_common.h" #include "ccu_reset.h" @@ -1251,9 +1252,35 @@ static struct ccu_mux_nb sun8i_r40_cpu_nb = { .bypass_index = 1, /* index of 24 MHz oscillator */ }; +/* + * Add a regmap for the GMAC driver (dwmac-sun8i) to access the + * GMAC configuration register. + * Only this register is allowed to be written, in order to + * prevent overriding critical clock configuration. + */ + +#define SUN8I_R40_GMAC_CFG_REG 0x164 +static bool sun8i_r40_ccu_regmap_writeable_reg(struct device *dev, + unsigned int reg) +{ + if (reg == SUN8I_R40_GMAC_CFG_REG) + return true; + return false; +} + +static struct regmap_config sun8i_r40_ccu_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0x320, /* PLL_LOCK_CTRL_REG */ + + .writeable_reg = sun8i_r40_ccu_regmap_writeable_reg, +}; + static int sun8i_r40_ccu_probe(struct platform_device *pdev) { struct resource *res; + struct regmap *regmap; void __iomem *reg; u32 val; int ret; @@ -1278,6 +1305,11 @@ static int sun8i_r40_ccu_probe(struct platform_device *pdev) val &= ~GENMASK(25, 20); writel(val, reg + SUN8I_R40_USB_CLK_REG); + regmap = devm_regmap_init_mmio(>dev, reg, + _r40_ccu_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + ret = sunxi_ccu_probe(pdev->dev.of_node, reg, _r40_ccu_desc); if (ret) return ret; -- 2.13.6
[PATCH 0/2] Add a regmap to Allwinner R40 CCU to export GMAC register
In the CCU of the Allwinner R40 SoC, there's a GMAC configuration register, which is intended to be accessed by the dwmac-sun8i driver. On SoCs already supported by the driver the register is placed in the syscon rather than the CCU. As CCU is a critical part of the SoC, so write to it should be strictly limited. A regmap with restricted write permission is created by the R40 CCU driver, and can be get with dev_get_regmap. In order to tie the regmap to the CCU device, the R40 CCU is now a platform driver, so a platform device is created for it (and then tied with the regmap). The first patch does the conversion of the driver to a platform driver, and the second patch adds the regmap. Icenowy Zheng (2): clk: sunxi-ng: r40: rewrite init code to a platform driver clk: sunxi-ng: r40: export a regmap to access the GMAC register drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 69 ++-- 1 file changed, 59 insertions(+), 10 deletions(-) -- 2.13.6
[PATCH 0/2] Add a regmap to Allwinner R40 CCU to export GMAC register
In the CCU of the Allwinner R40 SoC, there's a GMAC configuration register, which is intended to be accessed by the dwmac-sun8i driver. On SoCs already supported by the driver the register is placed in the syscon rather than the CCU. As CCU is a critical part of the SoC, so write to it should be strictly limited. A regmap with restricted write permission is created by the R40 CCU driver, and can be get with dev_get_regmap. In order to tie the regmap to the CCU device, the R40 CCU is now a platform driver, so a platform device is created for it (and then tied with the regmap). The first patch does the conversion of the driver to a platform driver, and the second patch adds the regmap. Icenowy Zheng (2): clk: sunxi-ng: r40: rewrite init code to a platform driver clk: sunxi-ng: r40: export a regmap to access the GMAC register drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 69 ++-- 1 file changed, 59 insertions(+), 10 deletions(-) -- 2.13.6
Re: [PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi
于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote: >> On 10/4/2017 11:03 AM, Icenowy Zheng wrote: >> > >> > >> > 于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo <kv...@codeaurora.org> >写到: >> > > Icenowy Zheng <icen...@aosc.io> writes: >> > > >> > > > Allwinner XR819 is a SDIO Wi-Fi chip, which has the >functionality to >> > > use >> > > > an out-of-band interrupt pin instead of SDIO in-band interrupt. >> > > > >> > > > Add the device tree binding of this chip, in order to make it >> > > possible >> > > > to add this interrupt pin to device trees. >> > > > >> > > > Signed-off-by: Icenowy Zheng <icen...@aosc.io> >> > > > Acked-by: Rob Herring <r...@kernel.org> >> > > > --- >> > > > Changes in v3: >> > > > - Renames the node name. >> > > > - Adds ACK from Rob. >> > > > Changes in v2: >> > > > - Removed status property in example. >> > > > - Added required property reg. >> > > > >> > > > .../bindings/net/wireless/allwinner,xr819.txt | 38 >> > > ++ >> > > > 1 file changed, 38 insertions(+) >> > > > create mode 100644 >> > > >Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt >> > > >> > > Like I asked already last time, AFAICS there is no upstream xr819 >> > > wireless driver in drivers/net/wireless directory. Do we still >accept >> > > bindings like this for out-of-tree drivers? >> > >> > See esp8089. >> > >> > There's also no in-tree driver for it. >> >> The question is whether we should. The above might be a precedent, >but it >> may not necessarily be the way to go. The commit message for esp8089 >seems >> to hint that there is intent to have an in-tree driver: >> >> """ >> Note that at this point there only is an out of tree driver for >this >> hardware, there is no clear timeline / path for merging this. >Still >> I believe it would be good to specify the binding for this in >tree >> now, so that any future migration to an in tree driver will not >cause >> compatiblity issues. >> >> Cc: Icenowy Zheng <icen...@aosc.xyz> >> Signed-off-by: Hans de Goede <hdego...@redhat.com> >> Signed-off-by: Rob Herring <r...@kernel.org> >> """ >> >> Regardless the bindings are in principle independent of the kernel >and just >> describing hardware. I think there have been discussions to move the >> bindings to their own repository, but apparently it was decided >otherwise. > >Yeah, I guess especially how it could be merged with the cw1200 driver >would be very relevant to that commit log. The cw1200 driver seems to still have some legacy platform data. Maybe they should also be convert to DT. (Or maybe compatible = "allwinner,xr819" is enough, as xr819 is a specified variant of cw1200 family) > >Maxime
Re: [PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi
于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard 写到: >On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote: >> On 10/4/2017 11:03 AM, Icenowy Zheng wrote: >> > >> > >> > 于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo >写到: >> > > Icenowy Zheng writes: >> > > >> > > > Allwinner XR819 is a SDIO Wi-Fi chip, which has the >functionality to >> > > use >> > > > an out-of-band interrupt pin instead of SDIO in-band interrupt. >> > > > >> > > > Add the device tree binding of this chip, in order to make it >> > > possible >> > > > to add this interrupt pin to device trees. >> > > > >> > > > Signed-off-by: Icenowy Zheng >> > > > Acked-by: Rob Herring >> > > > --- >> > > > Changes in v3: >> > > > - Renames the node name. >> > > > - Adds ACK from Rob. >> > > > Changes in v2: >> > > > - Removed status property in example. >> > > > - Added required property reg. >> > > > >> > > > .../bindings/net/wireless/allwinner,xr819.txt | 38 >> > > ++ >> > > > 1 file changed, 38 insertions(+) >> > > > create mode 100644 >> > > >Documentation/devicetree/bindings/net/wireless/allwinner,xr819.txt >> > > >> > > Like I asked already last time, AFAICS there is no upstream xr819 >> > > wireless driver in drivers/net/wireless directory. Do we still >accept >> > > bindings like this for out-of-tree drivers? >> > >> > See esp8089. >> > >> > There's also no in-tree driver for it. >> >> The question is whether we should. The above might be a precedent, >but it >> may not necessarily be the way to go. The commit message for esp8089 >seems >> to hint that there is intent to have an in-tree driver: >> >> """ >> Note that at this point there only is an out of tree driver for >this >> hardware, there is no clear timeline / path for merging this. >Still >> I believe it would be good to specify the binding for this in >tree >> now, so that any future migration to an in tree driver will not >cause >> compatiblity issues. >> >> Cc: Icenowy Zheng >> Signed-off-by: Hans de Goede >> Signed-off-by: Rob Herring >> """ >> >> Regardless the bindings are in principle independent of the kernel >and just >> describing hardware. I think there have been discussions to move the >> bindings to their own repository, but apparently it was decided >otherwise. > >Yeah, I guess especially how it could be merged with the cw1200 driver >would be very relevant to that commit log. The cw1200 driver seems to still have some legacy platform data. Maybe they should also be convert to DT. (Or maybe compatible = "allwinner,xr819" is enough, as xr819 is a specified variant of cw1200 family) > >Maxime