Re: [PATCH 4/8] dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-kenzo
On 15/04/2021 11:35, Hsin-Yi Wang wrote: > Kenzo is known as Acer Chromebook 311. > > Signed-off-by: Hsin-Yi Wang > --- > Documentation/devicetree/bindings/arm/mediatek.yaml | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml > b/Documentation/devicetree/bindings/arm/mediatek.yaml > index 0870490aa350..39e4a99ebb37 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek.yaml > +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml > @@ -137,9 +137,11 @@ properties: > items: >- const: google,damu >- const: mediatek,mt8183 > - - description: Google Juniper (Acer Chromebook Spin 311) > + - description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer > Crhomebook 311) Crhomebook -> Chromebook :) > items: > - - const: google,juniper-sku16 > + - enum: > + - google,juniper-sku16 > + - google,juniper-sku17 >- const: google,juniper >- const: mediatek,mt8183 >- description: Google Kakadu (ASUS Chromebook Detachable CM3) >
Re: [PATCH 3/3] arm64: dts: mt8183-kukui: fix dtbs_check warnings
Hi Nicolas,
On 15/04/2021 02:29, Nicolas Boichat wrote:
> On Wed, Apr 14, 2021 at 10:46 PM wrote:
>>
>> From: Matthias Brugger
>>
>> The dsi children don't have any reg property,
>
> Confused, see below.
>
>> so we don't need address and
>> size cells. This makes dtbs_check happy.
>>
>> CC: Hsin-Yi Wang
>> CC: Enric Balletbo i Serra
>> CC: Nicolas Boichat
>> Signed-off-by: Matthias Brugger
>>
>> ---
>>
>> arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 3 +--
>> 1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
>> b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
>> index ff56bcfa3370..f4dca6a33168 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
>> @@ -251,8 +251,7 @@ {
>>
>> {
>> status = "okay";
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> +
>> panel: panel@0 {
>> /* compatible will be set in board dts */
>> reg = <0>;
>
> ^^ isn't that... a reg property?
>
Yes, that's my fault. I'm not quite sure why we would need this reg property. In
any case also we have it present "dtbs_check W=1" throws the following warning:
mediatek/mt8183.dtsi:1234.22-1246.5: Warning (avoid_unnecessary_addr_size):
/soc/dsi@14014000: unnecessary #address-cells/#size-cells without "ranges" or
child "reg" property
Can you have a look at that?
Regards,
Matthias
>> --
>> 2.30.2
>>
Re: [PATCH v2, 0/5] Revert "mailbox: mediatek: remove implementation related to atomic_exec"
On 12/04/2021 17:29, Jassi Brar wrote: > On Mon, Apr 12, 2021 at 6:18 AM Yongqiang Niu > wrote: >> >> This series base linux 5.12-rc2 >> these patches will cause home ui flick when cursor moved, >> there is no fix solution yet, revert these patches first. >> >> change since v1: >> add mtk-gce.txt and dts modification >> >> Yongqiang Niu (5): >> Revert "drm/mediatek: Make sure previous message done or be aborted >> before send" >> Revert "mailbox: mediatek: remove implementation related to >> atomic_exec" >> Revert "dt-bindings: mailbox: mtk-gce: fix incorrect mbox-cells value" >> Revert "arm64: dts: mediatek: mt8183: fix gce incorrect mbox-cells >> value" >> arm64: dts: mediatek: mt8183: add gce information for mmsys >> >> .../devicetree/bindings/mailbox/mtk-gce.txt| 2 +- >> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 5 +- >> drivers/gpu/drm/mediatek/mtk_drm_crtc.c| 1 - >> drivers/mailbox/mtk-cmdq-mailbox.c | 80 >> +++--- >> 4 files changed, 76 insertions(+), 12 deletions(-) >> > Please break the patchsets (this and the other 3) into mailbox only > and platform specific ones. > Also, it would help if there are some acked/reviewed by some mtk folks > especially when reverting patches. > I'd prefer to have DT and mailbox patches together as otherwise the burden on me to find out which patches in the driver are needed, and to check if these got accepted, gets higher. Regards, Matthias
Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
On 26/02/2021 11:59, Mason Zhang wrote:
> this patch add spi master dts node for mt6779 SOC.
>
> Signed-off-by: Mason Zhang
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..ca72eb09cff9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -219,6 +219,102 @@
> status = "disabled";
> };
>
> + spi0: spi0@1100a000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
>From the binding description:
- #address-cells: should be 1.
- #size-cells: should be 0.
We are missing both here. Please fix that.
Apart the binding description is naming PLL, clock mux and clock gate IDs which
do not correspond to the ones used here. It seems that this binding was tailored
for a specific SoC family but never made generic. If you want, please do so and
convert it to yaml.
Regards,
Matthias
> + };
> +
> + spi1: spi1@1101 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI1>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi2: spi2@11012000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11012000 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI2>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi3: spi3@11013000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11013000 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI3>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi4: spi4@11018000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI4>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi5: spi5@11019000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11019000 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI5>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi6: spi6@1101d000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101d000 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI6>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi7: spi7@1101e000 {
> +
Re: [PATCH 1/2] dt-bindings: mediatek: mmsys: add mt1867 binding
Hi Chun-Kuang, On 10/01/2021 00:17, Chun-Kuang Hu wrote: > Hi, Matthias: > > Rob Herring 於 2020年10月31日 週六 上午3:17寫道： >> >> On Tue, 27 Oct 2020 17:06:29 +0100, Fabien Parent wrote: >>> Add binding documentation for MT8167 SoC. > > Even though the title need to change to 'mt8167', this patch looks > good to me. How do you think about this patch? One drm patch [1] > depend on this patch, if you like this patch, could you applied this > patch first? > > [1] > https://patchwork.kernel.org/project/linux-mediatek/patch/20201023133130.194140-6-fpar...@baylibre.com/ > I just pushed the latest version [1] of this to v5.12-next/soc-2 I'll try to get this in for v5.13, if not possible we can sync again on how to fix this. Regards, Matthias [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20210405200354.2194930-1-fpar...@baylibre.com/ > Regards, > Chun-Kuang. > >>> >>> Signed-off-by: Fabien Parent >>> --- >>> .../devicetree/bindings/arm/mediatek/mediatek,mmsys.txt | 1 + >>> 1 file changed, 1 insertion(+) >>> >> >> Acked-by: Rob Herring >> >> ___ >> Linux-mediatek mailing list >> linux-media...@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Re: [PATCH v8 2/4] soc: mediatek: add MT6765 scpsys and subdomain support
On 06/04/2021 16:01, Matthias Brugger wrote:
>
>
> On 21/02/2020 11:12, Macpaul Lin wrote:
>> From: Mars Cheng
>>
>> This adds scpsys support for MT6765
>> Add subdomain support for MT6765:
>> isp, mm, connsys, mfg, and cam.
>>
>> Signed-off-by: Mars Cheng
>> Signed-off-by: Owen Chen
>> Signed-off-by: Macpaul Lin
>> ---
>> drivers/soc/mediatek/mtk-scpsys.c | 130
>> +
>> 1 file changed, 130 insertions(+)
>>
>
> Unfortunately scpsys is deprecated in the meantime. Please port you patches to
> the new mtk-pm-domains.c driver. The biggest difference is, that the domain
> and
> subdomain structure of the pm domains is describe in device tree instead of
> hard-coded in the driver.
>
I got confused by the email grouping in my mail client. I already gave the same
feedback in v10 :)
> Regards,
> Matthias
>
>> diff --git a/drivers/soc/mediatek/mtk-scpsys.c
>> b/drivers/soc/mediatek/mtk-scpsys.c
>> index f669d37..9940c6d 100644
>> --- a/drivers/soc/mediatek/mtk-scpsys.c
>> +++ b/drivers/soc/mediatek/mtk-scpsys.c
>> @@ -15,6 +15,7 @@
>>
>> #include
>> #include
>> +#include
>> #include
>> #include
>> #include
>> @@ -750,6 +751,120 @@ static void mtk_register_power_domains(struct
>> platform_device *pdev,
>> };
>>
>> /*
>> + * MT6765 power domain support
>> + */
>> +#define SPM_PWR_STATUS_MT6765 0x0180
>> +#define SPM_PWR_STATUS_2ND_MT6765 0x0184
>> +
>> +static const struct scp_domain_data scp_domain_data_mt6765[] = {
>> +[MT6765_POWER_DOMAIN_VCODEC] = {
>> +.name = "vcodec",
>> +.sta_mask = BIT(26),
>> +.ctl_offs = 0x300,
>> +.sram_pdn_bits = GENMASK(8, 8),
>> +.sram_pdn_ack_bits = GENMASK(12, 12),
>> +},
>> +[MT6765_POWER_DOMAIN_ISP] = {
>> +.name = "isp",
>> +.sta_mask = BIT(5),
>> +.ctl_offs = 0x308,
>> +.sram_pdn_bits = GENMASK(8, 8),
>> +.sram_pdn_ack_bits = GENMASK(12, 12),
>> +.subsys_clk_prefix = "isp",
>> +.bp_table = {
>> +BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
>> +BIT(20), BIT(20)),
>> +BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0,
>> +BIT(2), BIT(2)),
>> +},
>> +},
>> +[MT6765_POWER_DOMAIN_MM] = {
>> +.name = "mm",
>> +.sta_mask = BIT(3),
>> +.ctl_offs = 0x30C,
>> +.sram_pdn_bits = GENMASK(8, 8),
>> +.sram_pdn_ack_bits = GENMASK(12, 12),
>> +.basic_clk_id = {"mm"},
>> +.subsys_clk_prefix = "mm",
>> +.bp_table = {
>> +BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
>> +BIT(16) | BIT(17), BIT(16) | BIT(17)),
>> +BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
>> +BIT(10) | BIT(11), BIT(10) | BIT(11)),
>> +BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
>> +BIT(1) | BIT(2), BIT(1) | BIT(2)),
>> +},
>> +},
>> +[MT6765_POWER_DOMAIN_CONN] = {
>> +.name = "conn",
>> +.sta_mask = BIT(1),
>> +.ctl_offs = 0x32C,
>> +.sram_pdn_bits = 0,
>> +.sram_pdn_ack_bits = 0,
>> +.bp_table = {
>> +BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
>> +BIT(13), BIT(13)),
>> +BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
>> +BIT(18), BIT(18)),
>> +BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
>> +BIT(14) | BIT(16), BIT(14) | BIT(16)),
>> +},
>> +},
>> +[MT6765_POWER_DOMAIN_MFG_ASYNC] = {
>> +.name = "mfg_async",
>> +.sta_mask = BIT(23),
>> +.ctl_offs = 0x334,
>> +.sram_pdn_bits = 0,
>> +.sram_pdn_ack_bits = 0,
>> +.basic_clk_id = {"mfg"},
>> +},
>> +[MT6765_POWER_DOMAIN_MFG] = {
>> +.name = "mfg",
>> +.sta_mask = BIT(4),
>> +
Re: [PATCH v8 2/4] soc: mediatek: add MT6765 scpsys and subdomain support
On 21/02/2020 11:12, Macpaul Lin wrote:
> From: Mars Cheng
>
> This adds scpsys support for MT6765
> Add subdomain support for MT6765:
> isp, mm, connsys, mfg, and cam.
>
> Signed-off-by: Mars Cheng
> Signed-off-by: Owen Chen
> Signed-off-by: Macpaul Lin
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 130
> +
> 1 file changed, 130 insertions(+)
>
Unfortunately scpsys is deprecated in the meantime. Please port you patches to
the new mtk-pm-domains.c driver. The biggest difference is, that the domain and
subdomain structure of the pm domains is describe in device tree instead of
hard-coded in the driver.
Regards,
Matthias
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c
> b/drivers/soc/mediatek/mtk-scpsys.c
> index f669d37..9940c6d 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -15,6 +15,7 @@
>
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -750,6 +751,120 @@ static void mtk_register_power_domains(struct
> platform_device *pdev,
> };
>
> /*
> + * MT6765 power domain support
> + */
> +#define SPM_PWR_STATUS_MT67650x0180
> +#define SPM_PWR_STATUS_2ND_MT67650x0184
> +
> +static const struct scp_domain_data scp_domain_data_mt6765[] = {
> + [MT6765_POWER_DOMAIN_VCODEC] = {
> + .name = "vcodec",
> + .sta_mask = BIT(26),
> + .ctl_offs = 0x300,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + },
> + [MT6765_POWER_DOMAIN_ISP] = {
> + .name = "isp",
> + .sta_mask = BIT(5),
> + .ctl_offs = 0x308,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .subsys_clk_prefix = "isp",
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
> + BIT(20), BIT(20)),
> + BUS_PROT(SMI_TYPE, 0x3C4, 0x3C8, 0, 0x3C0,
> + BIT(2), BIT(2)),
> + },
> + },
> + [MT6765_POWER_DOMAIN_MM] = {
> + .name = "mm",
> + .sta_mask = BIT(3),
> + .ctl_offs = 0x30C,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .basic_clk_id = {"mm"},
> + .subsys_clk_prefix = "mm",
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
> + BIT(16) | BIT(17), BIT(16) | BIT(17)),
> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
> + BIT(10) | BIT(11), BIT(10) | BIT(11)),
> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
> + BIT(1) | BIT(2), BIT(1) | BIT(2)),
> + },
> + },
> + [MT6765_POWER_DOMAIN_CONN] = {
> + .name = "conn",
> + .sta_mask = BIT(1),
> + .ctl_offs = 0x32C,
> + .sram_pdn_bits = 0,
> + .sram_pdn_ack_bits = 0,
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
> + BIT(13), BIT(13)),
> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
> + BIT(18), BIT(18)),
> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
> + BIT(14) | BIT(16), BIT(14) | BIT(16)),
> + },
> + },
> + [MT6765_POWER_DOMAIN_MFG_ASYNC] = {
> + .name = "mfg_async",
> + .sta_mask = BIT(23),
> + .ctl_offs = 0x334,
> + .sram_pdn_bits = 0,
> + .sram_pdn_ack_bits = 0,
> + .basic_clk_id = {"mfg"},
> + },
> + [MT6765_POWER_DOMAIN_MFG] = {
> + .name = "mfg",
> + .sta_mask = BIT(4),
> + .ctl_offs = 0x338,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
> + BIT(25), BIT(25)),
> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
> + BIT(21) | BIT(22), BIT(21) | BIT(22)),
> + }
> + },
> + [MT6765_POWER_DOMAIN_CAM] = {
> + .name = "cam",
> + .sta_mask = BIT(25),
> + .ctl_offs = 0x344,
> + .sram_pdn_bits = GENMASK(8, 9),
> + .sram_pdn_ack_bits = GENMASK(12, 13),
> + .subsys_clk_prefix = "cam",
> + .bp_table = {
> + BUS_PROT(IFR_TYPE, 0x2A8, 0x2AC, 0, 0x258,
> + BIT(19) | BIT(21), BIT(19) | BIT(21)),
> + BUS_PROT(IFR_TYPE, 0x2A0, 0x2A4, 0, 0x228,
> +
Re: [PATCH v2 6/6] soc: mediatek: devapc: support mt8192
On 01/04/2021 08:38, Nina Wu wrote:
> From: Nina Wu
>
> Add compatible to support mt8192.
>
> Signed-off-by: Nina Wu
> ---
Looks good, I'd like to see DTS for this as well, although I understand it
depends on the clock patch series. Please note so in either below the '---' or
in a cover letter.
Regards,
Matthias
> drivers/soc/mediatek/mtk-devapc.c | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-devapc.c
> b/drivers/soc/mediatek/mtk-devapc.c
> index af55c01..a5c15b5 100644
> --- a/drivers/soc/mediatek/mtk-devapc.c
> +++ b/drivers/soc/mediatek/mtk-devapc.c
> @@ -251,11 +251,26 @@ static const struct mtk_devapc_data devapc_mt6779 = {
> .vio_shift_con_offset = 0xF20,
> };
>
> +static const struct mtk_devapc_data devapc_mt8192 = {
> + .vio_mask_offset = 0x0,
> + .vio_sta_offset = 0x400,
> + .vio_dbg0_offset = 0x900,
> + .vio_dbg1_offset = 0x904,
> + .vio_dbg2_offset = 0x908,
> + .apc_con_offset = 0xF00,
> + .vio_shift_sta_offset = 0xF20,
> + .vio_shift_sel_offset = 0xF30,
> + .vio_shift_con_offset = 0xF10,
> +};
> +
> static const struct of_device_id mtk_devapc_dt_match[] = {
> {
> .compatible = "mediatek,mt6779-devapc",
> .data = _mt6779,
> }, {
> + .compatible = "mediatek,mt8192-devapc",
> + .data = _mt8192,
> + }, {
> },
> };
>
>
Re: [PATCH v2 5/6] soc: mediatek: devapc: add debug register for new IC support
On 01/04/2021 08:38, Nina Wu wrote:
> From: Nina Wu
>
> There are 3 debug info registers in new ICs while in legacy ones,
> we have only 2. When dumping the debug info, we need to check first
> if the 3rd debug register exists and then we can konw how to decipher
> the debug info.
>
> Signed-off-by: Nina Wu
> ---
> drivers/soc/mediatek/mtk-devapc.c | 31 +--
> 1 file changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-devapc.c
> b/drivers/soc/mediatek/mtk-devapc.c
> index bcf6e3c..af55c01 100644
> --- a/drivers/soc/mediatek/mtk-devapc.c
> +++ b/drivers/soc/mediatek/mtk-devapc.c
> @@ -26,9 +26,19 @@ struct mtk_devapc_vio_dbgs {
> u32 addr_h:4;
> u32 resv:4;
> } dbg0_bits;
> +
> + /* Not used, reference only */
> + struct {
> + u32 dmnid:6;
> + u32 vio_w:1;
> + u32 vio_r:1;
> + u32 addr_h:4;
> + u32 resv:20;
> + } dbg0_bits_ver2;
> };
>
> u32 vio_dbg1;
> + u32 vio_dbg2;
> };
>
> struct mtk_devapc_data {
> @@ -37,6 +47,7 @@ struct mtk_devapc_data {
> u32 vio_sta_offset;
> u32 vio_dbg0_offset;
> u32 vio_dbg1_offset;
> + u32 vio_dbg2_offset;
> u32 apc_con_offset;
> u32 vio_shift_sta_offset;
> u32 vio_shift_sel_offset;
> @@ -158,12 +169,29 @@ static void devapc_extract_vio_dbg(struct
> mtk_devapc_context *ctx)
> struct mtk_devapc_vio_dbgs vio_dbgs;
> void __iomem *vio_dbg0_reg;
> void __iomem *vio_dbg1_reg;
> + void __iomem *vio_dbg2_reg;
> + u32 vio_addr, bus_id;
>
> vio_dbg0_reg = ctx->base + ctx->data->vio_dbg0_offset;
> vio_dbg1_reg = ctx->base + ctx->data->vio_dbg1_offset;
> + vio_dbg2_reg = ctx->base + ctx->data->vio_dbg2_offset;
We should read this only if we have version2 of the devapc.
>
> vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg);
> vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg);
> + vio_dbgs.vio_dbg2 = readl(vio_dbg2_reg);
> +
> + if (!ctx->data->vio_dbg2_offset) {
I think we should add a version field to mtk_devapc_data to distinguish the two
of them.
> + /* arch version 1 */
> + bus_id = vio_dbgs.dbg0_bits.mstid;
> + vio_addr = vio_dbgs.vio_dbg1;
> + } else {
> + /* arch version 2 */
> + bus_id = vio_dbgs.vio_dbg1;
> + vio_addr = vio_dbgs.vio_dbg2;
> +
> + /* To align with the bit definition of arch_ver 1 */
> + vio_dbgs.vio_dbg0 = (vio_dbgs.vio_dbg0 << 16);
That's magic, better add another variable domain_id and do here:
domain_id = vio_dgbs.dbg0_bits_ver2.dmnid;
> + }
>
> /* Print violation information */
> if (vio_dbgs.dbg0_bits.vio_w)
> @@ -172,8 +200,7 @@ static void devapc_extract_vio_dbg(struct
> mtk_devapc_context *ctx)
> dev_info(ctx->dev, "Read Violation\n");
>
> dev_info(ctx->dev, "Bus ID:0x%x, Dom ID:0x%x, Vio Addr:0x%x\n",
> - vio_dbgs.dbg0_bits.mstid, vio_dbgs.dbg0_bits.dmnid,
> - vio_dbgs.vio_dbg1);
> + bus_id, vio_dbgs.dbg0_bits.dmnid, vio_addr);
> }
>
> /*
>
Re: [PATCH v2 4/6] soc: mediatek: devapc: rename variable for new IC support
Regarding the commit subject:
"soc: mediatek: devapc: rename variable for new IC support"
maybe something like:
"soc: mediatek: devapc: rename register variable infra_base"
Other then that looks good to me.
On 01/04/2021 08:38, Nina Wu wrote:
> From: Nina Wu
>
> For new ICs, there are multiple devapc HWs for different subsys.
> For example, there is devapc respectively for infra, peri, peri2, etc.
> So we rename the variable 'infra_base' to 'base' for code readability.
>
> Signed-off-by: Nina Wu
> ---
> drivers/soc/mediatek/mtk-devapc.c | 24
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-devapc.c
> b/drivers/soc/mediatek/mtk-devapc.c
> index 68c3e35..bcf6e3c 100644
> --- a/drivers/soc/mediatek/mtk-devapc.c
> +++ b/drivers/soc/mediatek/mtk-devapc.c
> @@ -45,7 +45,7 @@ struct mtk_devapc_data {
>
> struct mtk_devapc_context {
> struct device *dev;
> - void __iomem *infra_base;
> + void __iomem *base;
> u32 vio_idx_num;
> struct clk *infra_clk;
> const struct mtk_devapc_data *data;
> @@ -56,7 +56,7 @@ static void clear_vio_status(struct mtk_devapc_context *ctx)
> void __iomem *reg;
> int i;
>
> - reg = ctx->infra_base + ctx->data->vio_sta_offset;
> + reg = ctx->base + ctx->data->vio_sta_offset;
>
> for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++)
> writel(GENMASK(31, 0), reg + 4 * i);
> @@ -71,7 +71,7 @@ static void mask_module_irq(struct mtk_devapc_context *ctx,
> bool mask)
> u32 val;
> int i;
>
> - reg = ctx->infra_base + ctx->data->vio_mask_offset;
> + reg = ctx->base + ctx->data->vio_mask_offset;
>
> if (mask)
> val = GENMASK(31, 0);
> @@ -113,11 +113,11 @@ static int devapc_sync_vio_dbg(struct
> mtk_devapc_context *ctx)
> int ret;
> u32 val;
>
> - pd_vio_shift_sta_reg = ctx->infra_base +
> + pd_vio_shift_sta_reg = ctx->base +
> ctx->data->vio_shift_sta_offset;
> - pd_vio_shift_sel_reg = ctx->infra_base +
> + pd_vio_shift_sel_reg = ctx->base +
> ctx->data->vio_shift_sel_offset;
> - pd_vio_shift_con_reg = ctx->infra_base +
> + pd_vio_shift_con_reg = ctx->base +
> ctx->data->vio_shift_con_offset;
>
> /* Find the minimum shift group which has violation */
> @@ -159,8 +159,8 @@ static void devapc_extract_vio_dbg(struct
> mtk_devapc_context *ctx)
> void __iomem *vio_dbg0_reg;
> void __iomem *vio_dbg1_reg;
>
> - vio_dbg0_reg = ctx->infra_base + ctx->data->vio_dbg0_offset;
> - vio_dbg1_reg = ctx->infra_base + ctx->data->vio_dbg1_offset;
> + vio_dbg0_reg = ctx->base + ctx->data->vio_dbg0_offset;
> + vio_dbg1_reg = ctx->base + ctx->data->vio_dbg1_offset;
>
> vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg);
> vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg);
> @@ -198,7 +198,7 @@ static irqreturn_t devapc_violation_irq(int irq_number,
> void *data)
> */
> static void start_devapc(struct mtk_devapc_context *ctx)
> {
> - writel(BIT(31), ctx->infra_base + ctx->data->apc_con_offset);
> + writel(BIT(31), ctx->base + ctx->data->apc_con_offset);
>
> mask_module_irq(ctx, false);
> }
> @@ -210,7 +210,7 @@ static void stop_devapc(struct mtk_devapc_context *ctx)
> {
> mask_module_irq(ctx, true);
>
> - writel(BIT(2), ctx->infra_base + ctx->data->apc_con_offset);
> + writel(BIT(2), ctx->base + ctx->data->apc_con_offset);
> }
>
> static const struct mtk_devapc_data devapc_mt6779 = {
> @@ -249,8 +249,8 @@ static int mtk_devapc_probe(struct platform_device *pdev)
> ctx->data = of_device_get_match_data(>dev);
> ctx->dev = >dev;
>
> - ctx->infra_base = of_iomap(node, 0);
> - if (!ctx->infra_base)
> + ctx->base = of_iomap(node, 0);
> + if (!ctx->base)
> return -EINVAL;
>
> if (of_property_read_u32(node, "vio_idx_num", >vio_idx_num))
>
Re: [PATCH v2 2/6] soc: mediatek: devapc: move 'vio_idx_num' info to DT
On 01/04/2021 08:38, Nina Wu wrote:
> From: Nina Wu
>
> For new ICs, there are multiple devapc HWs for different subsys.
> The number of devices controlled by each devapc (i.e. 'vio_idx_num'
> in the code) varies.
> We move this info from compatible data to DT so that we do not need
> to add n compatible for a certain IC which has n devapc HWs with
> different 'vio_idx_num', respectively.
>
> Signed-off-by: Nina Wu
> ---
> drivers/soc/mediatek/mtk-devapc.c | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-devapc.c
> b/drivers/soc/mediatek/mtk-devapc.c
> index f1cea04..a0f6fbd 100644
> --- a/drivers/soc/mediatek/mtk-devapc.c
> +++ b/drivers/soc/mediatek/mtk-devapc.c
> @@ -32,9 +32,6 @@ struct mtk_devapc_vio_dbgs {
> };
>
> struct mtk_devapc_data {
> - /* numbers of violation index */
> - u32 vio_idx_num;
> -
> /* reg offset */
> u32 vio_mask_offset;
> u32 vio_sta_offset;
> @@ -49,6 +46,7 @@ struct mtk_devapc_data {
> struct mtk_devapc_context {
> struct device *dev;
> void __iomem *infra_base;
> + u32 vio_idx_num;
We should try to stay backwards compatible (newer kernel with older DTS). I
think we don't need to move vio_idx_num to mtk_devapc_context. Just don't
declare it in the per SoC match data. More details see below...
> struct clk *infra_clk;
> const struct mtk_devapc_data *data;
> };
> @@ -60,10 +58,10 @@ static void clear_vio_status(struct mtk_devapc_context
> *ctx)
>
> reg = ctx->infra_base + ctx->data->vio_sta_offset;
>
> - for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++)
> + for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++)
> writel(GENMASK(31, 0), reg + 4 * i);
>
> - writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 0),
> + writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1), 0),
> reg + 4 * i);
> }
>
> @@ -80,15 +78,15 @@ static void mask_module_irq(struct mtk_devapc_context
> *ctx, bool mask)
> else
> val = 0;
>
> - for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++)
> + for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++)
> writel(val, reg + 4 * i);
>
> val = readl(reg + 4 * i);
> if (mask)
> - val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1,
> + val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1),
> 0);
> else
> - val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1,
> + val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1),
> 0);
>
> writel(val, reg + 4 * i);
> @@ -216,7 +214,6 @@ static void stop_devapc(struct mtk_devapc_context *ctx)
> }
>
> static const struct mtk_devapc_data devapc_mt6779 = {
> - .vio_idx_num = 511,
> .vio_mask_offset = 0x0,
> .vio_sta_offset = 0x400,
> .vio_dbg0_offset = 0x900,
> @@ -256,6 +253,9 @@ static int mtk_devapc_probe(struct platform_device *pdev)
> if (!ctx->infra_base)
> return -EINVAL;
>
> + if (of_property_read_u32(node, "vio_idx_num", >vio_idx_num))
> + return -EINVAL;
> +
...only read the property if vio_idx_num == 0.
What do you think?
Regards,
Matthias
> devapc_irq = irq_of_parse_and_map(node, 0);
> if (!devapc_irq)
> return -EINVAL;
>
Re: [PATCH v3 1/3] arm64: dts: mediatek: mt8167: add larb nodes
On 06/04/2021 13:36, Fabien Parent wrote:
> Add larb nodes for MT8167:
> * larb0 is used for display (dsi and hdmi)
> * larb1 is used for camera (csi)
> * larb2 is used for the video hardware decoder
>
> Signed-off-by: Fabien Parent
Whole series applied to v5.12-next/dts64-2
Thanks!
> ---
>
> Note: This series is based on
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.12-next/dts64-2
>
> V3:
> * Removed unicode character in commit summary
> V2:
> * Removed unneeded mediatek,larb-id property
>
> arch/arm64/boot/dts/mediatek/mt8167.dtsi | 30
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> index 4b951f81db9e..bbddd4b22d3e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> @@ -140,5 +140,35 @@ smi_common: smi@14017000 {
> clock-names = "apb", "smi";
> power-domains = < MT8167_POWER_DOMAIN_MM>;
> };
> +
> + larb0: larb@14016000 {
> + compatible = "mediatek,mt8167-smi-larb";
> + reg = <0 0x14016000 0 0x1000>;
> + mediatek,smi = <_common>;
> + clocks = < CLK_MM_SMI_LARB0>,
> + < CLK_MM_SMI_LARB0>;
> + clock-names = "apb", "smi";
> + power-domains = < MT8167_POWER_DOMAIN_MM>;
> + };
> +
> + larb1: larb@15001000 {
> + compatible = "mediatek,mt8167-smi-larb";
> + reg = <0 0x15001000 0 0x1000>;
> + mediatek,smi = <_common>;
> + clocks = < CLK_IMG_LARB1_SMI>,
> + < CLK_IMG_LARB1_SMI>;
> + clock-names = "apb", "smi";
> + power-domains = < MT8167_POWER_DOMAIN_ISP>;
> + };
> +
> + larb2: larb@1601 {
> + compatible = "mediatek,mt8167-smi-larb";
> + reg = <0 0x1601 0 0x1000>;
> + mediatek,smi = <_common>;
> + clocks = < CLK_VDEC_CKEN>,
> + < CLK_VDEC_LARB1_CKEN>;
> + clock-names = "apb", "smi";
> + power-domains = < MT8167_POWER_DOMAIN_VDEC>;
> + };
> };
> };
>
Re: [PATCH 2/5] arm64: dts: mediatek: mt8167: add smi_common node
On 05/04/2021 22:08, Fabien Parent wrote:
> Add the smi_common node.
>
> Signed-off-by: Fabien Parent
Applied to v5.12-next/dts64-2
I'll leave the others for a v2 of the series, as there a small comments.
Regards,
Matthias
> ---
> arch/arm64/boot/dts/mediatek/mt8167.dtsi | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> index 9d765034dfb0..4b951f81db9e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> @@ -131,5 +131,14 @@ mmsys: mmsys@1400 {
> reg = <0 0x1400 0 0x1000>;
> #clock-cells = <1>;
> };
> +
> + smi_common: smi@14017000 {
> + compatible = "mediatek,mt8167-smi-common";
> + reg = <0 0x14017000 0 0x1000>;
> + clocks = < CLK_MM_SMI_COMMON>,
> + < CLK_MM_SMI_COMMON>;
> + clock-names = "apb", "smi";
> + power-domains = < MT8167_POWER_DOMAIN_MM>;
> + };
> };
> };
>
Re: [PATCH 1/5] arm64: dts: mediatek: mt8167: add mmsys node
On 05/04/2021 22:08, Fabien Parent wrote:
> Add node for MMSYS.
>
> Signed-off-by: Fabien Parent
Applied to v5.12-next/dts64-2
Thanks
> ---
> arch/arm64/boot/dts/mediatek/mt8167.dtsi | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> index 156fbdad01fb..9d765034dfb0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> @@ -125,5 +125,11 @@ pio: pinctrl@1000b000 {
> #interrupt-cells = <2>;
> interrupts = ;
> };
> +
> + mmsys: mmsys@1400 {
> + compatible = "mediatek,mt8167-mmsys", "syscon";
> + reg = <0 0x1400 0 0x1000>;
> + #clock-cells = <1>;
> + };
> };
> };
>
Re: [PATCH] arm64: dts: mediatek: mt8167: add power domains
On 05/04/2021 19:28, Fabien Parent wrote:
> Add support for the MT8167 power domains.
>
> Signed-off-by: Fabien Parent
Applied to v5.12-next/dts64-2
Thanks
> ---
> arch/arm64/boot/dts/mediatek/mt8167.dtsi | 68
> 1 file changed, 68 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> index 1c5639ead622..156fbdad01fb 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> @@ -7,6 +7,7 @@
>
> #include
> #include
> +#include
>
> #include "mt8167-pinfunc.h"
>
> @@ -34,6 +35,73 @@ apmixedsys: apmixedsys@10018000 {
> #clock-cells = <1>;
> };
>
> + scpsys: syscon@10006000 {
> + compatible = "syscon", "simple-mfd";
> + reg = <0 0x10006000 0 0x1000>;
> + #power-domain-cells = <1>;
> +
> + spm: power-controller {
> + compatible = "mediatek,mt8167-power-controller";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> +
> + /* power domains of the SoC */
> + power-domain@MT8167_POWER_DOMAIN_MM {
> + reg = ;
> + clocks = < CLK_TOP_SMI_MM>;
> + clock-names = "mm";
> + #power-domain-cells = <0>;
> + mediatek,infracfg = <>;
> + };
> +
> + power-domain@MT8167_POWER_DOMAIN_VDEC {
> + reg = ;
> + clocks = < CLK_TOP_SMI_MM>,
> + < CLK_TOP_RG_VDEC>;
> + clock-names = "mm", "vdec";
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@MT8167_POWER_DOMAIN_ISP {
> + reg = ;
> + clocks = < CLK_TOP_SMI_MM>;
> + clock-names = "mm";
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {
> + reg = ;
> + clocks = < CLK_TOP_RG_AXI_MFG>,
> + <
> CLK_TOP_RG_SLOW_MFG>;
> + clock-names = "axi_mfg", "mfg";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> + mediatek,infracfg = <>;
> +
> + power-domain@MT8167_POWER_DOMAIN_MFG_2D
> {
> + reg =
> ;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> +
> +
> power-domain@MT8167_POWER_DOMAIN_MFG {
> + reg =
> ;
> + #power-domain-cells =
> <0>;
> + mediatek,infracfg =
> <>;
> + };
> + };
> + };
> +
> + power-domain@MT8167_POWER_DOMAIN_CONN {
> + reg = ;
> + #power-domain-cells = <0>;
> + mediatek,infracfg = <>;
> + };
> + };
> + };
> +
> imgsys: syscon@1500 {
> compatible = "mediatek,mt8167-imgsys", "syscon";
> reg = <0 0x1500 0 0x1000>;
>
Re: [PATCH v2 1/2] dt-bindings: mediatek: mmsys: add mt8167 binding
On 05/04/2021 22:03, Fabien Parent wrote: > Add binding documentation for MT8167 SoC. > > Signed-off-by: Fabien Parent > Reviewed-by: Chun-Kuang Hu > Acked-by: Rob Herring Applied both patches to v5.12-next/soc-2 Thanks! > --- > V2: Rebased + fix typo in commit message. > > .../devicetree/bindings/arm/mediatek/mediatek,mmsys.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git > a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt > b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt > index d8c9108c3b4a..78c50733985c 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt > @@ -13,6 +13,7 @@ Required Properties: > - "mediatek,mt6779-mmsys", "syscon" > - "mediatek,mt6797-mmsys", "syscon" > - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon" > + - "mediatek,mt8167-mmsys", "syscon" > - "mediatek,mt8173-mmsys", "syscon" > - "mediatek,mt8183-mmsys", "syscon" > - #clock-cells: Must be 1 >
Re: [PATCH v2 3/8] dt-bindings: watchdog: Add compatible for Mediatek MT8195
Hi Wim, On 26/03/2021 02:40, Rob Herring wrote: > On Fri, 19 Mar 2021 10:34:22 +0800, Seiya Wang wrote: >> This commit adds dt-binding documentation of watchdog for Mediatek MT8195 SoC >> Platform. >> >> Signed-off-by: Seiya Wang >> Reviewed-by: Guenter Roeck >> --- >> Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 + >> 1 file changed, 1 insertion(+) >> > > Acked-by: Rob Herring > I suppose you will take this patch through your tree. If you want me to take it through the MediaTek SoC tree, please let me know. Regards, Matthias
Re: [PATCH v2 1/8] dt-bindings: timer: Add compatible for Mediatek MT8195
Hi Daniel, On 04/04/2021 22:33, Daniel Lezcano wrote: > On 29/03/2021 13:52, Matthias Brugger wrote: >> >> >> On 19/03/2021 03:34, Seiya Wang wrote: >>> This commit adds dt-binding documentation of timer for Mediatek MT8195 SoC >>> Platform. >>> >>> Signed-off-by: Seiya Wang >> >> Applied to v5.12-next/dts64 > > Usually bindings go through the subsystem maintainer. > Yes I know, although not all maintainers are taking them. I'll coordinate with you the next time, sorry for any inconvenience caused by this. Regards, Matthias
Re: [PATCH v4,2/3] arm64: dts: mt8173: Separating mtk-vcodec-enc device node
On 06/04/2021 12:46, Hans Verkuil wrote:
> Hi Irui,
>
> On 25/03/2021 13:26, Irui Wang wrote:
>> There are two separate hardware encoder blocks inside MT8173.
>> Split the current mtk-vcodec-enc node to match the hardware architecture.
>
> I've accepted patches 1 & 3, so this patch can be merged by whoever maintains
> these dts
> files.
Thanks for the info, patch 2 is now part of v5.12-next/dts64-2
Regards,
Matthias
>
> Regards,
>
> Hans
>
>>
>> Acked-by: Tiffany Lin
>> Signed-off-by: Hsin-Yi Wang
>> Signed-off-by: Maoguang Meng
>> Signed-off-by: Irui Wang
>> ---
>> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 60
>> 1 file changed, 31 insertions(+), 29 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>> b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>> index 7fa870e4386a..f5950e9fc51d 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>> @@ -1458,14 +1458,11 @@
>> clock-names = "apb", "smi";
>> };
>>
>> -vcodec_enc: vcodec@18002000 {
>> +vcodec_enc_avc: vcodec@18002000 {
>> compatible = "mediatek,mt8173-vcodec-enc";
>> -reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
>> - <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
>> -interrupts = ,
>> - ;
>> -mediatek,larb = <>,
>> -<>;
>> +reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
>> +interrupts = ;
>> +mediatek,larb = <>;
>> iommus = < M4U_PORT_VENC_RCPU>,
>> < M4U_PORT_VENC_REC>,
>> < M4U_PORT_VENC_BSDMA>,
>> @@ -1476,29 +1473,12 @@
>> < M4U_PORT_VENC_REF_LUMA>,
>> < M4U_PORT_VENC_REF_CHROMA>,
>> < M4U_PORT_VENC_NBM_RDMA>,
>> - < M4U_PORT_VENC_NBM_WDMA>,
>> - < M4U_PORT_VENC_RCPU_SET2>,
>> - < M4U_PORT_VENC_REC_FRM_SET2>,
>> - < M4U_PORT_VENC_BSDMA_SET2>,
>> - < M4U_PORT_VENC_SV_COMA_SET2>,
>> - < M4U_PORT_VENC_RD_COMA_SET2>,
>> - < M4U_PORT_VENC_CUR_LUMA_SET2>,
>> - < M4U_PORT_VENC_CUR_CHROMA_SET2>,
>> - < M4U_PORT_VENC_REF_LUMA_SET2>,
>> - < M4U_PORT_VENC_REC_CHROMA_SET2>;
>> + < M4U_PORT_VENC_NBM_WDMA>;
>> mediatek,vpu = <>;
>> -clocks = < CLK_TOP_VENCPLL_D2>,
>> - < CLK_TOP_VENC_SEL>,
>> - < CLK_TOP_UNIVPLL1_D2>,
>> - < CLK_TOP_VENC_LT_SEL>;
>> -clock-names = "venc_sel_src",
>> - "venc_sel",
>> - "venc_lt_sel_src",
>> - "venc_lt_sel";
>> -assigned-clocks = < CLK_TOP_VENC_SEL>,
>> - < CLK_TOP_VENC_LT_SEL>;
>> -assigned-clock-parents = < CLK_TOP_VCODECPLL>,
>> - <
>> CLK_TOP_VCODECPLL_370P5>;
>> +clocks = < CLK_TOP_VENC_SEL>;
>> +clock-names = "venc_sel";
>> +assigned-clocks = < CLK_TOP_VENC_SEL>;
>> +assigned-clock-parents = < CLK_TOP_VCODECPLL>;
>> };
>>
>> jpegdec: jpegdec@18004000 {
>> @@ -1530,5 +1510,27 @@
>> < CLK_VENCLT_CKE0>;
>> clock-names = "apb", "smi";
>> };
>> +
>> +vcodec_enc_vp8: vcodec@19002000 {
>> +compatible = "mediatek,mt8173-vcodec-enc-vp8";
>> +reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
>> +interrupts = ;
>> +iommus = < M4U_PORT_VENC_RCPU_SET2>,
>> + < M4U_PORT_VENC_REC_FRM_SET2>,
>> + < M4U_PORT_VENC_BSDMA_SET2>,
>> + < M4U_PORT_VENC_SV_COMA_SET2>,
>> + < M4U_PORT_VENC_RD_COMA_SET2>,
>> + < M4U_PORT_VENC_CUR_LUMA_SET2>,
>> + < M4U_PORT_VENC_CUR_CHROMA_SET2>,
>> + < M4U_PORT_VENC_REF_LUMA_SET2>,
>> + < M4U_PORT_VENC_REC_CHROMA_SET2>;
>> +mediatek,larb = <>;
>> +mediatek,vpu = <>;
>> +clocks = < CLK_TOP_VENC_LT_SEL>;
>> +clock-names =
Re: [PATCH] arm64: dts: mediatek: fix reset GPIO level on pumpkin
On 23/02/2021 23:18, Fabien Parent wrote:
> The tca6416 chip is active low. Fix the reset-gpios value.
>
> Fixes: e2a8fa1e0faa ("arm64: dts: mediatek: fix tca6416 reset GPIOs in
> pumpkin")
> Signed-off-by: Fabien Parent
Applied to v5.12-next/dts64
Thanks!
> ---
> arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
> b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
> index 63fd70086bb8..9f27e7ed5e22 100644
> --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
> @@ -56,7 +56,7 @@ {
> tca6416: gpio@20 {
> compatible = "ti,tca6416";
> reg = <0x20>;
> - reset-gpios = < 65 GPIO_ACTIVE_HIGH>;
> + reset-gpios = < 65 GPIO_ACTIVE_LOW>;
> pinctrl-names = "default";
> pinctrl-0 = <_pins>;
>
>
Re: [PATCH] arm64: dts: mt8183: Add power-domains properity to mfgcfg
On 24/02/2021 11:30, Enric Balletbo Serra wrote:
> Hi Ikjoon,
>
> Thank you for your patch.
>
> Missatge de Ikjoon Jang del dia dc., 24 de febr.
> 2021 a les 10:21:
>>
>> mfgcfg clock is under MFG_ASYNC power domain
>>
>> Signed-off-by: Weiyi Lu
>> Signed-off-by: Ikjoon Jang
>> ---
>>
>> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> index 5b782a4769e7..3384df5284c0 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> @@ -962,6 +962,7 @@ mfgcfg: syscon@1300 {
>> compatible = "mediatek,mt8183-mfgcfg", "syscon";
>> reg = <0 0x1300 0 0x1000>;
>> #clock-cells = <1>;
>> + power-domains = <
>> MT8183_POWER_DOMAIN_MFG_ASYNC>;
>
> I don't think this will work in mainline, at least, the reference name
> should be
>
Correct. Would you mind to resend with the comment from Enric. Apart from that,
patch looks fine to me.
Regards,
Matthias
> Thanks,
> Enric
>> };
>>
>> mmsys: syscon@1400 {
>> --
>> 2.30.0.617.g56c4b15f3c-goog
>>
>>
>> ___
>> Linux-mediatek mailing list
>> linux-media...@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Re: [PATCH 1/4] soc: mediatek: pm-domains: Add a meaningful power domain name
On 25/02/2021 18:49, Enric Balletbo i Serra wrote:
> Add the power domains names to the power domain struct so we
> have meaningful name for every power domain. This also removes the
> following debugfs error message.
>
> [2.242068] debugfs: Directory 'power-domain' with parent 'pm_genpd'
> already present!
> [2.249949] debugfs: Directory 'power-domain' with parent 'pm_genpd'
> already present!
> [2.257784] debugfs: Directory 'power-domain' with parent 'pm_genpd'
> already present!
> ...
>
> Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains")
> Signed-off-by: Enric Balletbo i Serra
Whole series applied to v5.12-next/soc
Thanks a lot!
Matthias
> ---
>
> drivers/soc/mediatek/mt8173-pm-domains.h | 10 ++
> drivers/soc/mediatek/mtk-pm-domains.c| 6 +-
> drivers/soc/mediatek/mtk-pm-domains.h| 2 ++
> 3 files changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h
> b/drivers/soc/mediatek/mt8173-pm-domains.h
> index 3e8ee5dabb43..654c717e5467 100644
> --- a/drivers/soc/mediatek/mt8173-pm-domains.h
> +++ b/drivers/soc/mediatek/mt8173-pm-domains.h
> @@ -12,24 +12,28 @@
>
> static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
> [MT8173_POWER_DOMAIN_VDEC] = {
> + .name = "vdec",
> .sta_mask = PWR_STATUS_VDEC,
> .ctl_offs = SPM_VDE_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> },
> [MT8173_POWER_DOMAIN_VENC] = {
> + .name = "venc",
> .sta_mask = PWR_STATUS_VENC,
> .ctl_offs = SPM_VEN_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> },
> [MT8173_POWER_DOMAIN_ISP] = {
> + .name = "isp",
> .sta_mask = PWR_STATUS_ISP,
> .ctl_offs = SPM_ISP_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(13, 12),
> },
> [MT8173_POWER_DOMAIN_MM] = {
> + .name = "mm",
> .sta_mask = PWR_STATUS_DISP,
> .ctl_offs = SPM_DIS_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> @@ -40,18 +44,21 @@ static const struct scpsys_domain_data
> scpsys_domain_data_mt8173[] = {
> },
> },
> [MT8173_POWER_DOMAIN_VENC_LT] = {
> + .name = "venc_lt",
> .sta_mask = PWR_STATUS_VENC_LT,
> .ctl_offs = SPM_VEN2_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> },
> [MT8173_POWER_DOMAIN_AUDIO] = {
> + .name = "audio",
> .sta_mask = PWR_STATUS_AUDIO,
> .ctl_offs = SPM_AUDIO_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(15, 12),
> },
> [MT8173_POWER_DOMAIN_USB] = {
> + .name = "usb",
> .sta_mask = PWR_STATUS_USB,
> .ctl_offs = SPM_USB_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> @@ -59,18 +66,21 @@ static const struct scpsys_domain_data
> scpsys_domain_data_mt8173[] = {
> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> },
> [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
> + .name = "mfg_async",
> .sta_mask = PWR_STATUS_MFG_ASYNC,
> .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = 0,
> },
> [MT8173_POWER_DOMAIN_MFG_2D] = {
> + .name = "mfg_2d",
> .sta_mask = PWR_STATUS_MFG_2D,
> .ctl_offs = SPM_MFG_2D_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = GENMASK(13, 12),
> },
> [MT8173_POWER_DOMAIN_MFG] = {
> + .name = "mfg",
> .sta_mask = PWR_STATUS_MFG,
> .ctl_offs = SPM_MFG_PWR_CON,
> .sram_pdn_bits = GENMASK(13, 8),
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c
> b/drivers/soc/mediatek/mtk-pm-domains.c
> index b7f697666bdd..694d6ea6de1d 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.c
> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> @@ -438,7 +438,11 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys
> *scpsys, struct device_no
> goto err_unprepare_subsys_clocks;
> }
>
> - pd->genpd.name = node->name;
> + if (!pd->data->name)
> + pd->genpd.name = node->name;
> + else
> + pd->genpd.name = pd->data->name;
> +
> pd->genpd.power_off = scpsys_power_off;
> pd->genpd.power_on = scpsys_power_on;
>
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.h
> b/drivers/soc/mediatek/mtk-pm-domains.h
> index 141dc76054e6..21a4e113bbec 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.h
> +++
Re: [PATCH 1/2] dt-bindings: arm64: dts: mediatek: Add mt8183-pumpkin board
On 17/02/2021 21:59, Fabien Parent wrote: > Add binding documentation for the MT8183 Pumpkin board. > > Signed-off-by: Fabien Parent Whole series applied to v5.12-next/dts64 Thanks! > --- > Documentation/devicetree/bindings/arm/mediatek.yaml | 4 > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml > b/Documentation/devicetree/bindings/arm/mediatek.yaml > index 53f0d4e3ea98..8f5a625cfb3d 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek.yaml > +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml > @@ -123,6 +123,10 @@ properties: >- const: google,krane-sku176 >- const: google,krane >- const: mediatek,mt8183 > + - items: > + - enum: > + - mediatek,mt8183-pumpkin > + - const: mediatek,mt8183 > > additionalProperties: true > >
Re: [PATCH -next] soc: mediatek: Make symbol 'mtk_mutex_driver' static
On 10/02/2021 08:56, Wei Yongjun wrote:
> The sparse tool complains as follows:
>
> drivers/soc/mediatek/mtk-mutex.c:464:24: warning:
> symbol 'mtk_mutex_driver' was not declared. Should it be static?
>
> This symbol is not used outside of mtk-mutex.c, so this
> commit marks it static.
>
> Reported-by: Hulk Robot
> Signed-off-by: Wei Yongjun
Applied to v5.12-next/soc
Thanks!
> ---
> drivers/soc/mediatek/mtk-mutex.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index f531b119da7a..3a315a62e783 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -461,7 +461,7 @@ static const struct of_device_id mutex_driver_dt_match[]
> = {
> };
> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
>
> -struct platform_driver mtk_mutex_driver = {
> +static struct platform_driver mtk_mutex_driver = {
> .probe = mtk_mutex_probe,
> .remove = mtk_mutex_remove,
> .driver = {
>
Re: [PATCH v10 2/4] soc: mediatek: add MT6765 scpsys and subdomain support
Hi Macpaul,
On 10/03/2021 07:36, Macpaul Lin wrote:
> From: Mars Cheng
>
> This adds scpsys support for MT6765
> Add subdomain support for MT6765:
> isp, mm, connsys, mfg, and cam.
>
> Signed-off-by: Mars Cheng
> Signed-off-by: Owen Chen
> Signed-off-by: Macpaul Lin
> ---
> drivers/soc/mediatek/mtk-scpsys.c | 91 +++
> 1 file changed, 91 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-scpsys.c
> b/drivers/soc/mediatek/mtk-scpsys.c
the mtk-scpsys is the old version of the driver. Please port your code to the
new driver: mtk-pm-domains.c
The biggest difference for you will be to describe the power domain hierarchy in
DT instead as in the driver.
Regards,
Matthias
> index ca75b14931ec..fc8d3858f1b4 100644
> --- a/drivers/soc/mediatek/mtk-scpsys.c
> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> @@ -15,6 +15,7 @@
>
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -750,6 +751,81 @@ static const struct scp_subdomain scp_subdomain_mt2712[]
> = {
> {MT2712_POWER_DOMAIN_MFG_SC2, MT2712_POWER_DOMAIN_MFG_SC3},
> };
>
> +/*
> + * MT6765 power domain support
> + */
> +#define SPM_PWR_STATUS_MT67650x0180
> +#define SPM_PWR_STATUS_2ND_MT67650x0184
> +
> +static const struct scp_domain_data scp_domain_data_mt6765[] = {
> + [MT6765_POWER_DOMAIN_VCODEC] = {
> + .name = "vcodec",
> + .sta_mask = BIT(26),
> + .ctl_offs = 0x300,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + },
> + [MT6765_POWER_DOMAIN_ISP] = {
> + .name = "isp",
> + .sta_mask = BIT(5),
> + .ctl_offs = 0x308,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + },
> + [MT6765_POWER_DOMAIN_MM] = {
> + .name = "mm",
> + .sta_mask = BIT(3),
> + .ctl_offs = 0x30C,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .clk_id = {CLK_MM},
> + },
> + [MT6765_POWER_DOMAIN_CONN] = {
> + .name = "conn",
> + .sta_mask = BIT(1),
> + .ctl_offs = 0x32C,
> + .sram_pdn_bits = 0,
> + .sram_pdn_ack_bits = 0,
> + },
> + [MT6765_POWER_DOMAIN_MFG_ASYNC] = {
> + .name = "mfg_async",
> + .sta_mask = BIT(23),
> + .ctl_offs = 0x334,
> + .sram_pdn_bits = 0,
> + .sram_pdn_ack_bits = 0,
> + .clk_id = {CLK_MFG},
> + },
> + [MT6765_POWER_DOMAIN_MFG] = {
> + .name = "mfg",
> + .sta_mask = BIT(4),
> + .ctl_offs = 0x338,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + },
> + [MT6765_POWER_DOMAIN_CAM] = {
> + .name = "cam",
> + .sta_mask = BIT(25),
> + .ctl_offs = 0x344,
> + .sram_pdn_bits = GENMASK(9, 8),
> + .sram_pdn_ack_bits = GENMASK(13, 12),
> + },
> + [MT6765_POWER_DOMAIN_MFG_CORE0] = {
> + .name = "mfg_core0",
> + .sta_mask = BIT(7),
> + .ctl_offs = 0x34C,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + },
> +};
> +
> +static const struct scp_subdomain scp_subdomain_mt6765[] = {
> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_CAM},
> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_ISP},
> + {MT6765_POWER_DOMAIN_MM, MT6765_POWER_DOMAIN_VCODEC},
> + {MT6765_POWER_DOMAIN_MFG_ASYNC, MT6765_POWER_DOMAIN_MFG},
> + {MT6765_POWER_DOMAIN_MFG, MT6765_POWER_DOMAIN_MFG_CORE0},
> +};
> +
> /*
> * MT6797 power domain support
> */
> @@ -1033,6 +1109,18 @@ static const struct scp_soc_data mt2712_data = {
> .bus_prot_reg_update = false,
> };
>
> +static const struct scp_soc_data mt6765_data = {
> + .domains = scp_domain_data_mt6765,
> + .num_domains = ARRAY_SIZE(scp_domain_data_mt6765),
> + .subdomains = scp_subdomain_mt6765,
> + .num_subdomains = ARRAY_SIZE(scp_subdomain_mt6765),
> + .regs = {
> + .pwr_sta_offs = SPM_PWR_STATUS_MT6765,
> + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6765,
> + },
> + .bus_prot_reg_update = true,
> +};
> +
> static const struct scp_soc_data mt6797_data = {
> .domains = scp_domain_data_mt6797,
> .num_domains = ARRAY_SIZE(scp_domain_data_mt6797),
> @@ -1088,6 +1176,9 @@ static const struct of_device_id of_scpsys_match_tbl[]
> = {
> }, {
> .compatible = "mediatek,mt2712-scpsys",
> .data = _data,
> + }, {
> + .compatible = "mediatek,mt6765-scpsys",
> + .data = _data,
> }, {
> .compatible = "mediatek,mt6797-scpsys",
> .data = _data,
>
Re: [PATCH v3] soc: mediatek: mmsys: Add mt8183 mmsys routing table
On 30/03/2021 13:04, Hsin-Yi Wang wrote:
> mt8183 has different routing registers than mt8173.
>
> Signed-off-by: Hsin-Yi Wang
> Tested-by: Enric Balletbo i Serra
Applied to v5.12-next/soc
Thanks!
> ---
> v2->v3:
> Fix comments.
>
> v1->v2:
> Move mt8183 routing table to mt8183-mmsys.h
>
> This patch is based on
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git
> v5.12-next/soc
> ---
> drivers/soc/mediatek/mt8183-mmsys.h | 54 +
> drivers/soc/mediatek/mtk-mmsys.c| 3 ++
> 2 files changed, 57 insertions(+)
> create mode 100644 drivers/soc/mediatek/mt8183-mmsys.h
>
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h
> b/drivers/soc/mediatek/mt8183-mmsys.h
> new file mode 100644
> index ..579dfc8dc8fc
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -0,0 +1,54 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8183_MMSYS_H
> +#define __SOC_MEDIATEK_MT8183_MMSYS_H
> +
> +#define MT8183_DISP_OVL0_MOUT_EN 0xf00
> +#define MT8183_DISP_OVL0_2L_MOUT_EN 0xf04
> +#define MT8183_DISP_OVL1_2L_MOUT_EN 0xf08
> +#define MT8183_DISP_DITHER0_MOUT_EN 0xf0c
> +#define MT8183_DISP_PATH0_SEL_IN 0xf24
> +#define MT8183_DISP_DSI0_SEL_IN 0xf2c
> +#define MT8183_DISP_DPI0_SEL_IN 0xf30
> +#define MT8183_DISP_RDMA0_SOUT_SEL_IN0xf50
> +#define MT8183_DISP_RDMA1_SOUT_SEL_IN0xf54
> +
> +#define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
> +#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0BIT(0)
> +#define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
> +#define MT8183_DITHER0_MOUT_IN_DSI0 BIT(0)
> +#define MT8183_DISP_PATH0_SEL_IN_OVL0_2L 0x1
> +#define MT8183_DSI0_SEL_IN_RDMA0 0x1
> +#define MT8183_DSI0_SEL_IN_RDMA1 0x3
> +#define MT8183_DPI0_SEL_IN_RDMA0 0x1
> +#define MT8183_DPI0_SEL_IN_RDMA1 0x2
> +#define MT8183_RDMA0_SOUT_COLOR0 0x1
> +#define MT8183_RDMA1_SOUT_DSI0 0x1
> +
> +static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
> + MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L
> + }, {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
> + MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
> + }, {
> + DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,
> + MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0
> + }, {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
> + MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L
> + }, {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1
> + }, {
> + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
> + MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0
> + }
> +};
> +
> +#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
> +
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index c46d8ab8b0c2..79e55150210e 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -11,6 +11,7 @@
> #include
>
> #include "mtk-mmsys.h"
> +#include "mt8183-mmsys.h"
>
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .clk_driver = "clk-mt2701-mm",
> @@ -40,6 +41,8 @@ static const struct mtk_mmsys_driver_data
> mt8173_mmsys_driver_data = {
>
> static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .clk_driver = "clk-mt8183-mm",
> + .routes = mmsys_mt8183_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> };
>
> struct mtk_mmsys {
>
Re: [PATCH v2 1/3] soc: mediatek: pm-domains: Use correct mask for bus_prot_clr
On 01/02/2021 13:14, Bilal Wasim wrote:
> When "bus_prot_reg_update" is true, the driver should use
> INFRA_TOPAXI_PROTECTEN for both setting and clearing the bus
> protection. However, the driver does not use this mask for
> clearing bus protection which causes failure when booting
> the imgtec gpu.
>
> Corrected and tested with mt8173 chromebook.
>
> Signed-off-by: Bilal Wasim
> Reviewed-by: Hsin-Yi Wang
BUS_PROT_UPDATE_TOPAXI is also used in mt8167. I'd need feedback if this would
break that SoC before accepting this patch.
Regards,
Matthias
> ---
> drivers/soc/mediatek/mtk-pm-domains.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.h
> b/drivers/soc/mediatek/mtk-pm-domains.h
> index 141dc76054e6..7454c0b4f768 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.h
> +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> @@ -60,7 +60,7 @@
> #define BUS_PROT_UPDATE_TOPAXI(_mask)\
> BUS_PROT_UPDATE(_mask, \
> INFRA_TOPAXI_PROTECTEN, \
> - INFRA_TOPAXI_PROTECTEN_CLR, \
> + INFRA_TOPAXI_PROTECTEN, \
> INFRA_TOPAXI_PROTECTSTA1)
>
> struct scpsys_bus_prot_data {
>
Re: [PATCH v2 2/3] soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD
On 01/02/2021 13:14, Bilal Wasim wrote:
> The mfg_async power domain in mt8173 is used to power up imgtec
> gpu. This domain requires the da9211 regulator to be enabled before
> the power domain can be enabled successfully.
>
> Signed-off-by: Bilal Wasim
> Reviewed-by: Hsin-Yi Wang
> ---
> drivers/soc/mediatek/mt8173-pm-domains.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h
> b/drivers/soc/mediatek/mt8173-pm-domains.h
> index 3e8ee5dabb43..065b8195e7d6 100644
> --- a/drivers/soc/mediatek/mt8173-pm-domains.h
> +++ b/drivers/soc/mediatek/mt8173-pm-domains.h
> @@ -63,6 +63,7 @@ static const struct scpsys_domain_data
> scpsys_domain_data_mt8173[] = {
> .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = 0,
> + .caps = MTK_SCPD_DOMAIN_SUPPLY,
Hm, I think the problem here is, that we don't find the regulator
"domain-supply" in the DTS. And that provokes that we error out on all power
domains. Not sure if we should fix that somehow, so that a missing regulator
will only affect one power domain (and it's childs).
Regards,
Matthias
> },
> [MT8173_POWER_DOMAIN_MFG_2D] = {
> .sta_mask = PWR_STATUS_MFG_2D,
>
Re: [PATCH 1/4] dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-kakadu
On 31/03/2021 11:13, Hsin-Yi Wang wrote: > Kakadu is also known as ASUS Chromebook Detachable CM3. > > Signed-off-by: Hsin-Yi Wang Whole series applied to v5.12-next/dts64 Thanks! > --- > Documentation/devicetree/bindings/arm/mediatek.yaml | 7 +++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml > b/Documentation/devicetree/bindings/arm/mediatek.yaml > index cf24401edb85..9774f44b51d9 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek.yaml > +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml > @@ -138,6 +138,13 @@ properties: >- const: google,juniper-sku16 >- const: google,juniper >- const: mediatek,mt8183 > + - description: Google Kakadu (ASUS Chromebook Detachable CM3) > +items: > + - const: google,kakadu-rev3 > + - const: google,kakadu-rev2 > + - const: google,kakadu > + - const: mediatek,mt8183 > + > > additionalProperties: true > >
Re: [RESEND PATCH 1/2] arm64: defconfig: Allow mt8173-based boards to boot from usb
On 31/03/2021 11:15, Hsin-Yi Wang wrote: > On Wed, Mar 31, 2021 at 5:07 PM Enric Balletbo i Serra > wrote: >> >> Enable the option necessary to boot mt8173-based boards to boot from >> usb devices, like its phy and the regulators needed to have proper >> support. >> >> Signed-off-by: Enric Balletbo i Serra >> --- > Reviewed-by: Hsin-Yi Wang Both patches applied to v5.12-next/defconfig Thanks! > >> This is only a resend rebased on top of mainline to fix some trivial >> conflicts. >> >> arch/arm64/configs/defconfig | 7 +++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig >> index d612f633b771..7b4be3807b6d 100644 >> --- a/arch/arm64/configs/defconfig >> +++ b/arch/arm64/configs/defconfig >> @@ -448,6 +448,7 @@ CONFIG_I2C_GPIO=m >> CONFIG_I2C_IMX=y >> CONFIG_I2C_IMX_LPI2C=y >> CONFIG_I2C_MESON=y >> +CONFIG_I2C_MT65XX=y >> CONFIG_I2C_MV64XXX=y >> CONFIG_I2C_OMAP=y >> CONFIG_I2C_OWL=y >> @@ -594,6 +595,7 @@ CONFIG_MFD_EXYNOS_LPASS=m >> CONFIG_MFD_HI6421_PMIC=y >> CONFIG_MFD_HI655X_PMIC=y >> CONFIG_MFD_MAX77620=y >> +CONFIG_MFD_MT6397=y >> CONFIG_MFD_SPMI_PMIC=y >> CONFIG_MFD_RK808=y >> CONFIG_MFD_SEC_CORE=y >> @@ -611,6 +613,8 @@ CONFIG_REGULATOR_HI655X=y >> CONFIG_REGULATOR_MAX77620=y >> CONFIG_REGULATOR_MAX8973=y >> CONFIG_REGULATOR_MP8859=y >> +CONFIG_REGULATOR_MT6358=y >> +CONFIG_REGULATOR_MT6397=y >> CONFIG_REGULATOR_PCA9450=y >> CONFIG_REGULATOR_PF8X00=y >> CONFIG_REGULATOR_PFUZE100=y >> @@ -787,6 +791,7 @@ CONFIG_USB_RENESAS_USBHS_HCD=m >> CONFIG_USB_RENESAS_USBHS=m >> CONFIG_USB_ACM=m >> CONFIG_USB_STORAGE=y >> +CONFIG_USB_MTU3=y >> CONFIG_USB_MUSB_HDRC=y >> CONFIG_USB_MUSB_SUNXI=y >> CONFIG_USB_DWC3=y >> @@ -988,6 +993,7 @@ CONFIG_OWL_PM_DOMAINS=y >> CONFIG_RASPBERRYPI_POWER=y >> CONFIG_FSL_DPAA=y >> CONFIG_FSL_MC_DPIO=y >> +CONFIG_MTK_PMIC_WRAP=y >> CONFIG_QCOM_AOSS_QMP=y >> CONFIG_QCOM_COMMAND_DB=y >> CONFIG_QCOM_GENI_SE=y >> @@ -1064,6 +1070,7 @@ CONFIG_PHY_HI6220_USB=y >> CONFIG_PHY_HISTB_COMBPHY=y >> CONFIG_PHY_HISI_INNO_USB2=y >> CONFIG_PHY_MVEBU_CP110_COMPHY=y >> +CONFIG_PHY_MTK_TPHY=y >> CONFIG_PHY_QCOM_QMP=m >> CONFIG_PHY_QCOM_QUSB2=m >> CONFIG_PHY_QCOM_USB_HS=y >> -- >> 2.30.2 >>
Re: [PATCH v2] soc: mediatek: mmsys: Add mt8183 mmsys routing table
On 30/03/2021 12:44, Hsin-Yi Wang wrote:
> mt8183 has different routing registers than mt8173.
>
> Signed-off-by: Hsin-Yi Wang
> Tested-by: Enric Balletbo i Serra
> ---
> v1->v2:
> Move mt8183 routing table to mt8183-mmsys.h
>
> This patch is based on
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git
> v5.12-next/soc
> ---
> drivers/soc/mediatek/mt8183-mmsys.h | 56 +
> drivers/soc/mediatek/mtk-mmsys.c| 3 ++
> 2 files changed, 59 insertions(+)
> create mode 100644 drivers/soc/mediatek/mt8183-mmsys.h
>
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h
> b/drivers/soc/mediatek/mt8183-mmsys.h
> new file mode 100644
> index ..38e9f683e5bd
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -0,0 +1,56 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8183_MMSYS_H
> +#define __SOC_MEDIATEK_MT8183_MMSYS_H
> +
> +#include "mtk-mmsys.h"
We can drop this, see below.
> +
> +#define MT8183_DISP_OVL0_MOUT_EN 0xf00
> +#define MT8183_DISP_OVL0_2L_MOUT_EN 0xf04
> +#define MT8183_DISP_OVL1_2L_MOUT_EN 0xf08
> +#define MT8183_DISP_DITHER0_MOUT_EN 0xf0c
> +#define MT8183_DISP_PATH0_SEL_IN 0xf24
> +#define MT8183_DISP_DSI0_SEL_IN 0xf2c
> +#define MT8183_DISP_DPI0_SEL_IN 0xf30
> +#define MT8183_DISP_RDMA0_SOUT_SEL_IN0xf50
> +#define MT8183_DISP_RDMA1_SOUT_SEL_IN0xf54
> +
> +#define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
> +#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0BIT(0)
> +#define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
> +#define MT8183_DITHER0_MOUT_IN_DSI0 BIT(0)
> +#define MT8183_DISP_PATH0_SEL_IN_OVL0_2L 0x1
> +#define MT8183_DSI0_SEL_IN_RDMA0 0x1
> +#define MT8183_DSI0_SEL_IN_RDMA1 0x3
> +#define MT8183_DPI0_SEL_IN_RDMA0 0x1
> +#define MT8183_DPI0_SEL_IN_RDMA1 0x2
> +#define MT8183_RDMA0_SOUT_COLOR0 0x1
> +#define MT8183_RDMA1_SOUT_DSI0 0x1
> +
> +static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
> + MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L
> + }, {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
> + MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
> + }, {
> + DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,
> + MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0
> + }, {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
> + MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L
> + }, {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1
> + }, {
> + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
> + MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0
> + }
> +};
> +
> +#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
> +
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index c46d8ab8b0c2..ac68a989854e 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -10,6 +10,7 @@
> #include
> #include
>
> +#include "mt8183-mmsys.h"
Just add the SoC specific header after mtk-mmsys.h include.
Other then that patch looks good.
Matthias
> #include "mtk-mmsys.h"
>
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> @@ -40,6 +41,8 @@ static const struct mtk_mmsys_driver_data
> mt8173_mmsys_driver_data = {
>
> static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .clk_driver = "clk-mt8183-mm",
> + .routes = mmsys_mt8183_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> };
>
> struct mtk_mmsys {
>
Re: [PATCH v10 1/4] dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC
On 10/03/2021 07:36, Macpaul Lin wrote: > From: Mars Cheng > > This patch adds MT6765 smi binding document > > Signed-off-by: Mars Cheng > Signed-off-by: Owen Chen > Signed-off-by: Macpaul Lin > Acked-by: Rob Herring Patch looks good, but where is the driver part for it? Reviewed-by: Matthias Brugger > --- > .../bindings/memory-controllers/mediatek,smi-common.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git > a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > > b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > index a08a32340987..4a4f4377576f 100644 > --- > a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > +++ > b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml > @@ -31,6 +31,7 @@ properties: >- enum: >- mediatek,mt2701-smi-common >- mediatek,mt2712-smi-common > + - mediatek,mt6765-smi-common >- mediatek,mt6779-smi-common >- mediatek,mt8167-smi-common >- mediatek,mt8173-smi-common >
Re: [PATCH v6 0/5] Add PMIC wrapper support for Mediatek MT6873/8192 SoC IC
On 12/03/2021 16:34, Hsin-Hsiung Wang wrote: > This series adds support for new SoC MT6873/8192 to the pmic-wrap driver. > This series is based on Weiyi's patches[1]. > > [1] > https://patchwork.kernel.org/project/linux-mediatek/patch/1608642587-15634-7-git-send-email-weiyi...@mediatek.com/ > > changes since v5: > - rebase to Linux 5.12 > > Hsin-Hsiung Wang (5): > soc: mediatek: pwrap: use BIT() macro > soc: mediatek: pwrap: add arbiter capability > dt-bindings: mediatek: add compatible for MT6873/8192 pwrap > soc: mediatek: pwrap: add pwrap driver for MT6873/8192 SoCs Applied to first four to v5.12-next/soc Please resubmit the DTS node once the clock driver is accepted. Regards, Matthias > arm64: dts: mt8192: add pwrap node > > .../bindings/soc/mediatek/pwrap.txt | 1 + > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 +++ > drivers/soc/mediatek/mtk-pmic-wrap.c | 97 --- > 3 files changed, 95 insertions(+), 15 deletions(-) >
Re: [PATCH] dt-bindings: arm64: dts: mediatek: Add mt8516-pumpkin board
On 23/02/2021 23:36, Fabien Parent wrote: > Add binding documentation for the MT8516 Pumpkin board. > > Signed-off-by: Fabien Parent > --- Applied to v5.12-next/dts64 Thanks! > Documentation/devicetree/bindings/arm/mediatek.yaml | 4 > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml > b/Documentation/devicetree/bindings/arm/mediatek.yaml > index 93b3bdf6eaeb..366a753f64ba 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek.yaml > +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml > @@ -125,6 +125,10 @@ properties: >- google,krane-sku176 >- const: google,krane >- const: mediatek,mt8183 > + - items: > + - enum: > + - mediatek,mt8516-pumpkin > + - const: mediatek,mt8516 > > additionalProperties: true > >
Re: [PATCH] soc: mediatek: pm-domains: Fix missing error code in scpsys_add_subdomain()
On 03/03/2021 10:10, Enric Balletbo i Serra wrote:
> Adding one power domain in scpsys_add_subdomain is missing to assign an
> error code when it fails. Fix that assigning an error code to 'ret',
> this also fixes the follwowing smatch warning.
>
> drivers/soc/mediatek/mtk-pm-domains.c:492 scpsys_add_subdomain() warn:
> missing error code 'ret'
>
> Fixes: dd65030295e2 ("soc: mediatek: pm-domains: Don't print an error if
> child domain is deferred")
> Reported-by: kernel test robot
> Reported-by: Dan Carpenter
> Signed-off-by: Enric Balletbo i Serra
Applied to v5.12-next/soc
Thanks!
> ---
>
> drivers/soc/mediatek/mtk-pm-domains.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c
> b/drivers/soc/mediatek/mtk-pm-domains.c
> index 694d6ea6de1d..0af00efa0ef8 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.c
> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> @@ -491,8 +491,9 @@ static int scpsys_add_subdomain(struct scpsys *scpsys,
> struct device_node *paren
>
> child_pd = scpsys_add_one_domain(scpsys, child);
> if (IS_ERR(child_pd)) {
> - dev_err_probe(scpsys->dev, PTR_ERR(child_pd),
> - "%pOF: failed to get child domain id\n",
> child);
> + ret = PTR_ERR(child_pd);
> + dev_err_probe(scpsys->dev, ret, "%pOF: failed to get
> child domain id\n",
> + child);
> goto err_put_node;
> }
>
>
Re: [PATCH] soc: mediatek: mmsys: Add mt8183 mmsys routing table
Hi Hsin-Yi,
Patch looks good but please use the new, just merged format, see [1]
Please put the defines and the routing table in a new header file mt8183-mmsys.h
Thanks
Matthias
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.12-next/soc
On 23/03/2021 06:51, Hsin-Yi Wang wrote:
> mt8183 has different routing registers than mt8173.
>
> Signed-off-by: Hsin-Yi Wang
> ---
> This patch is based on series ("soc: mediatek: Prepare MMSYS for DDP routing
> using tables")[1]
> and tested with mt8183 krand and mt8183 juniper device.
> The register value is referenced from [2].
>
> [1]
> https://patchwork.kernel.org/project/linux-mediatek/cover/20210317181711.795245-1-enric.balle...@collabora.com/
> [2]
> https://patchwork.kernel.org/project/linux-mediatek/patch/1609815993-22744-6-git-send-email-yongqiang@mediatek.com/
> ---
> drivers/soc/mediatek/mtk-mmsys.c | 2 ++
> drivers/soc/mediatek/mtk-mmsys.h | 47
> 2 files changed, 49 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index c46d8ab8b0c2..16bb55b0463a 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -40,6 +40,8 @@ static const struct mtk_mmsys_driver_data
> mt8173_mmsys_driver_data = {
>
> static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .clk_driver = "clk-mt8183-mm",
> + .routes = mmsys_mt8183_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> };
>
> struct mtk_mmsys {
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> b/drivers/soc/mediatek/mtk-mmsys.h
> index a760a34e6eca..c55baf5932b8 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -66,6 +66,28 @@
> #define DPI_SEL_IN_BLS 0x0
> #define DSI_SEL_IN_RDMA 0x1
>
> +#define MT8183_DISP_OVL0_MOUT_EN 0xf00
> +#define MT8183_DISP_OVL0_2L_MOUT_EN 0xf04
> +#define MT8183_DISP_OVL1_2L_MOUT_EN 0xf08
> +#define MT8183_DISP_DITHER0_MOUT_EN 0xf0c
> +#define MT8183_DISP_PATH0_SEL_IN 0xf24
> +#define MT8183_DISP_DSI0_SEL_IN 0xf2c
> +#define MT8183_DISP_DPI0_SEL_IN 0xf30
> +#define MT8183_DISP_RDMA0_SOUT_SEL_IN0xf50
> +#define MT8183_DISP_RDMA1_SOUT_SEL_IN0xf54
> +
> +#define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
> +#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0BIT(0)
> +#define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
> +#define MT8183_DITHER0_MOUT_IN_DSI0 BIT(0)
> +#define MT8183_DISP_PATH0_SEL_IN_OVL0_2L 0x1
> +#define MT8183_DSI0_SEL_IN_RDMA0 0x1
> +#define MT8183_DSI0_SEL_IN_RDMA1 0x3
> +#define MT8183_DPI0_SEL_IN_RDMA0 0x1
> +#define MT8183_DPI0_SEL_IN_RDMA1 0x2
> +#define MT8183_RDMA0_SOUT_COLOR0 0x1
> +#define MT8183_RDMA1_SOUT_DSI0 0x1
> +
> struct mtk_mmsys_routes {
> u32 from_comp;
> u32 to_comp;
> @@ -212,4 +234,29 @@ static const struct mtk_mmsys_routes
> mmsys_default_routing_table[] = {
> }
> };
>
> +static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
> + MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L
> + }, {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
> + MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
> + }, {
> + DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,
> + MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0
> + }, {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
> + MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L
> + }, {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1
> + }, {
> + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
> + MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0
> + }
> +};
> +
> #endif /* __SOC_MEDIATEK_MTK_MMSYS_H */
>
Re: [PATCH 2/2] soc: mediatek: mmsys: Add support for MT8167 SoC
Hi Fabien,
Sorry for taking so long on that patch.
Generally the patch looks good, but I just merged a small change how we add new
SoC to the driver.
Please see comments below.
On 27/10/2020 17:06, Fabien Parent wrote:
> Add routing table for DSI on MT8167 SoC. The registers are mostly
> incompatible with the current defines, so new one for MT8167 are added.
>
> Signed-off-by: Fabien Parent
> ---
>
> This patch depends on the patch series
> "soc: mediatek: Prepare MMSYS for DDP routing using tables"
>
> [0] https://lore.kernel.org/patchwork/cover/1317813/
>
> drivers/soc/mediatek/mtk-mmsys.c | 50
> 1 file changed, 50 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index f00d6d08c9c5..9890990a74a9 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -85,6 +85,22 @@
> #define DSI_SEL_IN_RDMA 0x1
> #define DSI_SEL_IN_MASK 0x1
>
> +/* MT8167 */
> +#define MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x030
> +#define MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN 0x038
> +#define MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN0x058
> +#define MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0x064
> +#define MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN0x06c
> +
> +#define MT8167_DITHER_MOUT_EN_RDMA0 BIT(0)
> +#define MT8167_DITHER_MOUT_EN_MASK 0x7
> +
> +#define MT8167_RDMA0_SOUT_DSI0 0x2
> +#define MT8167_RDMA0_SOUT_MASK 0x3
> +
> +#define MT8167_DSI0_SEL_IN_RDMA0 0x1
> +#define MT8167_DSI0_SEL_IN_MASK 0x3
> +
> struct mtk_mmsys_routes {
> u32 from_comp;
> u32 to_comp;
> @@ -124,6 +140,30 @@ struct mtk_mmsys {
> const struct mtk_mmsys_driver_data *data;
> };
>
> +static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
Please put the defines and the routing table in a separate header file
mt8167-mmsys.h
Thanks and once again sorry for the inconvenience.
Matthias
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
> + MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
> + OVL0_MOUT_EN_COLOR0, OVL0_MOUT_EN_COLOR0
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
> + MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN,
> + MT8167_DITHER_MOUT_EN_MASK, MT8167_DITHER_MOUT_EN_RDMA0
> + }, {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
> + MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
> + COLOR0_SEL_IN_OVL0, COLOR0_SEL_IN_OVL0
> + }, {
> + DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
> + MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
> + MT8167_DSI0_SEL_IN_MASK, MT8167_DSI0_SEL_IN_RDMA0
> + }, {
> + DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI0,
> + MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN,
> + MT8167_RDMA0_SOUT_MASK, MT8167_RDMA0_SOUT_DSI0
> + },
> +};
> +
> static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {
> {
> DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
> @@ -288,6 +328,12 @@ static const struct mtk_mmsys_routes
> mt8173_mmsys_routing_table[] = {
> }
> };
>
> +static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
> + .clk_driver = "clk-mt8167-mm",
> + .routes = mt8167_mmsys_routing_table,
> + .num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
> +};
> +
> static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .clk_driver = "clk-mt8173-mm",
> .routes = mt8173_mmsys_routing_table,
> @@ -385,6 +431,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
> .compatible = "mediatek,mt6797-mmsys",
> .data = _mmsys_driver_data,
> },
> + {
> + .compatible = "mediatek,mt8167-mmsys",
> + .data = _mmsys_driver_data,
> + },
> {
> .compatible = "mediatek,mt8173-mmsys",
> .data = _mmsys_driver_data,
>
Re: [PATCH v2 0/2] soc: mediatek: Prepare MMSYS for DDP routing using tables
On 17/03/2021 19:17, Enric Balletbo i Serra wrote: > Dear all, > > This is the second version of this series intended to prepare the > mtk-mmsys driver to allow different DDP (Data Display Path) routing > tables per SoC. Note that the series has been tested only on MT8173 platform, > for MT2701 and MT2712 based devices we're using a default routing table > that should just work. That's a good base to improve the driver. Things I'd like to see: Split the mmsys_default_routing_table in the SoC specific one. But each SoC specific routing table in a new header file. Whole series applied to v5.12-next/soc Thanks a lot! Matthias > > Thanks, > Enric > > Changes in v2: > - Use a default table for mt2701, mt2712 and mt8173. > - Remove the mask field from routes struct as is not needed. > > CK Hu (2): > soc: mediatek: mmsys: Create struct mtk_mmsys to store context data > soc: mediatek: mmsys: Use an array for setting the routing registers > > drivers/soc/mediatek/mtk-mmsys.c | 300 +-- > drivers/soc/mediatek/mtk-mmsys.h | 215 ++ > 2 files changed, 257 insertions(+), 258 deletions(-) > create mode 100644 drivers/soc/mediatek/mtk-mmsys.h >
Re: [PATCH v4 1/2] dt-bindings: nvmem: mediatek: add support for MediaTek mt8192 SoC
On 01/02/2021 04:59, yz...@mediatek.com wrote: > From: Ryan Wu > > This updates dt-binding documentation for MediaTek mt8192 > > Signed-off-by: Ryan Wu Applied to v5.12-next/dts64 Please resend the DTS patch with the comments I made. > --- > This patch is based on v5.10-rc7. > --- > Documentation/devicetree/bindings/nvmem/mtk-efuse.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt > b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt > index 0668c45..82dafa3 100644 > --- a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt > +++ b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt > @@ -7,6 +7,7 @@ Required properties: > "mediatek,mt7622-efuse", "mediatek,efuse": for MT7622 > "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623 > "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173 > + "mediatek,mt8192-efuse", "mediatek,efuse": for MT8192 > - reg: Should contain registers location and length > > = Data cells = >
Re: [PATCH v4 2/2] arm64: dts: mt8192: add eFuse support for MT8192 SoC
On 01/02/2021 04:59, yz...@mediatek.com wrote:
> From: Ryan Wu
>
> Add eFuse node to read Mediatek eFuse
>
> Signed-off-by: Ryan Wu
> ---
> This patch dependents on "arm64: dts: Add Mediatek SoC MT8192 and evaluation
> board dts and Makefile"[1]
>
> mt8192.dtsi file is needed for this patch.
> Please also accept this patch together with [1].
>
> [1]http://lists.infradead.org/pipermail/linux-mediatek/2020-November/019378.html
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 69d45c7..4a0d941 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -422,6 +422,11 @@
> #clock-cells = <1>;
> };
>
> + efuse: efuse@11c1 {
> + compatible = "mediatek,mt8192-efuse",
> + "mediatek,efuse";
We are missing
#address-cells = <1>;
#size-cells = <1>;
Regards,
Matthias
> + };
> +
> i2c3: i2c3@11cb {
> compatible = "mediatek,mt8192-i2c";
> reg = <0 0x11cb 0 0x1000>,
>
Re: [PATCH] arm64: dts: mt8173: fix wrong power-domain phandle of pmic
On 18/03/2021 07:18, Chunfeng Yun wrote:
> Due to power domain controller is added, the power domain's
> phanle is also changed from 'scpsys' to 'spm', but forget to
> modify pmic node's
>
> Fixes: 8b6562644df9 ("arm64: dts: mediatek: Add mt8173 power domain
> controller")
> Signed-off-by: Chunfeng Yun
Applied to v5.12-next/dts64
Thanks!
> ---
> arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> index 6dffada2e66b..28aa634c9780 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> @@ -294,7 +294,7 @@
>
> {
> /* Only MT8173 E1 needs USB power domain */
> - power-domains = < MT8173_POWER_DOMAIN_USB>;
> + power-domains = < MT8173_POWER_DOMAIN_USB>;
>
> pmic: mt6397 {
> compatible = "mediatek,mt6397";
>
Re: [PATCH v4 2/2] power: supply: mt6360_charger: add MT6360 charger support
On 18/01/2021 13:41, Gene Chen wrote: > From: Gene Chen > > Add basic support for the battery charger for MT6360 PMIC > > Signed-off-by: Gene Chen Sebastian, can you have a look on that patch please? Regards, Matthias > --- > drivers/power/supply/Kconfig | 10 + > drivers/power/supply/Makefile | 1 + > drivers/power/supply/mt6360_charger.c | 914 > ++ > 3 files changed, 925 insertions(+) > create mode 100644 drivers/power/supply/mt6360_charger.c > > diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig > index eec646c..dd63bed 100644 > --- a/drivers/power/supply/Kconfig > +++ b/drivers/power/supply/Kconfig > @@ -567,6 +567,16 @@ config CHARGER_MP2629 > Battery charger. This driver provides Battery charger power management > functions on the systems. > > +config CHARGER_MT6360 > + tristate "Mediatek MT6360 Charger Driver" > + depends on MFD_MT6360 > + depends on REGULATOR > + help > + Say Y here to enable MT6360 Charger Part. > + The device supports High-Accuracy Voltage/Current Regulation, > + Average Input Current Regulation, Battery Tempature Sensing, > + Over-Temperature Protection, DPDM Detection for BC1.2 > + > config CHARGER_QCOM_SMBB > tristate "Qualcomm Switch-Mode Battery Charger and Boost" > depends on MFD_SPMI_PMIC || COMPILE_TEST > diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile > index dd4b863..9bd0804 100644 > --- a/drivers/power/supply/Makefile > +++ b/drivers/power/supply/Makefile > @@ -77,6 +77,7 @@ obj-$(CONFIG_CHARGER_MAX77693) += max77693_charger.o > obj-$(CONFIG_CHARGER_MAX8997)+= max8997_charger.o > obj-$(CONFIG_CHARGER_MAX8998)+= max8998_charger.o > obj-$(CONFIG_CHARGER_MP2629) += mp2629_charger.o > +obj-$(CONFIG_CHARGER_MT6360) += mt6360_charger.o > obj-$(CONFIG_CHARGER_QCOM_SMBB) += qcom_smbb.o > obj-$(CONFIG_CHARGER_BQ2415X)+= bq2415x_charger.o > obj-$(CONFIG_CHARGER_BQ24190)+= bq24190_charger.o > diff --git a/drivers/power/supply/mt6360_charger.c > b/drivers/power/supply/mt6360_charger.c > new file mode 100644 > index 000..d80bdad > --- /dev/null > +++ b/drivers/power/supply/mt6360_charger.c > @@ -0,0 +1,914 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2021 MediaTek Inc. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define MT6360_PMU_CHG_CTRL1 0x311 > +#define MT6360_PMU_CHG_CTRL2 0x312 > +#define MT6360_PMU_CHG_CTRL3 0x313 > +#define MT6360_PMU_CHG_CTRL4 0x314 > +#define MT6360_PMU_CHG_CTRL5 0x315 > +#define MT6360_PMU_CHG_CTRL6 0x316 > +#define MT6360_PMU_CHG_CTRL7 0x317 > +#define MT6360_PMU_CHG_CTRL8 0x318 > +#define MT6360_PMU_CHG_CTRL9 0x319 > +#define MT6360_PMU_CHG_CTRL100x31A > +#define MT6360_PMU_DEVICE_TYPE 0x322 > +#define MT6360_PMU_USB_STATUS1 0x327 > +#define MT6360_PMU_CHG_STAT 0x34A > +#define MT6360_PMU_CHG_CTRL190x361 > +#define MT6360_PMU_FOD_STAT 0x3E7 > + > +/* MT6360_PMU_CHG_CTRL1 */ > +#define MT6360_FSLP_SHFT (3) > +#define MT6360_FSLP_MASK BIT(MT6360_FSLP_SHFT) > +#define MT6360_OPA_MODE_SHFT (0) > +#define MT6360_OPA_MODE_MASK BIT(MT6360_OPA_MODE_SHFT) > +/* MT6360_PMU_CHG_CTRL2 */ > +#define MT6360_IINLMTSEL_SHFT(2) > +#define MT6360_IINLMTSEL_MASKGENMASK(3, 2) > +/* MT6360_PMU_CHG_CTRL3 */ > +#define MT6360_IAICR_SHFT(2) > +#define MT6360_IAICR_MASKGENMASK(7, 2) > +#define MT6360_ILIM_EN_MASK BIT(0) > +/* MT6360_PMU_CHG_CTRL4 */ > +#define MT6360_VOREG_SHFT(1) > +#define MT6360_VOREG_MASKGENMASK(7, 1) > +/* MT6360_PMU_CHG_CTRL5 */ > +#define MT6360_VOBST_MASKGENMASK(7, 2) > +/* MT6360_PMU_CHG_CTRL6 */ > +#define MT6360_VMIVR_SHFT (1) > +#define MT6360_VMIVR_MASK GENMASK(7, 1) > +/* MT6360_PMU_CHG_CTRL7 */ > +#define MT6360_ICHG_SHFT (2) > +#define MT6360_ICHG_MASK GENMASK(7, 2) > +/* MT6360_PMU_CHG_CTRL8 */ > +#define MT6360_IPREC_SHFT(0) > +#define MT6360_IPREC_MASKGENMASK(3, 0) > +/* MT6360_PMU_CHG_CTRL9 */ > +#define MT6360_IEOC_SHFT (4) > +#define MT6360_IEOC_MASK GENMASK(7, 4) > +/* MT6360_PMU_CHG_CTRL10 */ > +#define MT6360_OTG_OC_MASK GENMASK(3, 0) > +/* MT6360_PMU_DEVICE_TYPE */ > +#define MT6360_USBCHGEN_MASK BIT(7) > +/* MT6360_PMU_USB_STATUS1 */ > +#define MT6360_USB_STATUS_SHFT (4) > +#define MT6360_USB_STATUS_MASK GENMASK(6, 4) > +/* MT6360_PMU_CHG_STAT */ > +#define MT6360_CHG_STAT_SHFT (6) > +#define MT6360_CHG_STAT_MASK GENMASK(7, 6) > +#define MT6360_VBAT_LVL_MASK BIT(5) > +/* MT6360_PMU_CHG_CTRL19 */ > +#define MT6360_VINOVP_SHFT (5) > +#define MT6360_VINOVP_MASK GENMASK(6, 5) > +/* MT6360_PMU_FOD_STAT */ > +#define MT6360_CHRDET_EXT_MASK BIT(4) > + > +/* uV */ > +#define MT6360_VMIVR_MIN 390 > +#define MT6360_VMIVR_MAX 1340 >
Re: [v7,2/3] arm64: dts: mt8183: Configure CPU cooling
On 16/03/2021 08:01, Michael Kao wrote:
> From: Matthias Kaehlcke
>
> Add two passive trip points at 68°C and 80°C for the CPU temperature.
>
> Signed-off-by: Matthias Kaehlcke
> Signed-off-by: Michael Kao
> Tested-by: Hsin-Yi Wang
Applied to v5.12-next/dts64
Thanks.
Matthias
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 56
> 1 file changed, 56 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index d3550af06408..1ad0a1d55d53 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -13,6 +13,7 @@
> #include
> #include
> #include
> +#include
> #include "mt8183-pinfunc.h"
>
> / {
> @@ -678,6 +679,61 @@
> polling-delay = <500>;
> thermal-sensors = < 0>;
> sustainable-power = <5000>;
> +
> + trips {
> + threshold: trip-point@0 {
> + temperature = <68000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + target: trip-point@1 {
> + temperature = <8>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit: cpu-crit {
> + temperature = <115000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <>;
> + cooling-device = <
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>;
> + contribution = <3072>;
> + };
> + map1 {
> + trip = <>;
> + cooling-device = <
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>,
> + <
> + THERMAL_NO_LIMIT
> + THERMAL_NO_LIMIT>;
> + contribution = <1024>;
> + };
> + };
> };
>
> /* The tzts1 ~ tzts6 don't need to polling */
>
Re: [v7,1/3] arm64: dts: mt8183: add thermal zone node
On 22/03/2021 12:20, Hsin-Yi Wang wrote:
> On Tue, Mar 16, 2021 at 3:02 PM Michael Kao wrote:
>>
>> From: "michael.kao"
>>
>> Add thermal zone node to Mediatek MT8183 dts file.
>>
>> Evaluate the thermal zone every 500ms while not cooling
>> and every 100ms when passive cooling is performed.
>>
>> Signed-off-by: Matthias Kaehlcke
>> Signed-off-by: Michael Kao
>
> Tested-by: Hsin-Yi Wang
>
Applied to v5.12-next/dts64
Thanks!
> Tested this patch on mt8183 devices.
>
>> ---
>> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 85
>> 1 file changed, 85 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> index 5b782a4769e7..d3550af06408 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> @@ -657,6 +657,87 @@
>> status = "disabled";
>> };
>>
>> + thermal: thermal@1100b000 {
>> + #thermal-sensor-cells = <1>;
>> + compatible = "mediatek,mt8183-thermal";
>> + reg = <0 0x1100b000 0 0x1000>;
>> + clocks = < CLK_INFRA_THERM>,
>> +< CLK_INFRA_AUXADC>;
>> + clock-names = "therm", "auxadc";
>> + resets = <
>> MT8183_INFRACFG_AO_THERM_SW_RST>;
>> + interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>;
>> + mediatek,auxadc = <>;
>> + mediatek,apmixedsys = <>;
>> + nvmem-cells = <_calibration>;
>> + nvmem-cell-names = "calibration-data";
>> + };
>> +
>> + thermal-zones {
>> + cpu_thermal: cpu_thermal {
>> + polling-delay-passive = <100>;
>> + polling-delay = <500>;
>> + thermal-sensors = < 0>;
>> + sustainable-power = <5000>;
>> + };
>> +
>> + /* The tzts1 ~ tzts6 don't need to polling */
>> + /* The tzts1 ~ tzts6 don't need to thermal throttle
>> */
>> +
>> + tzts1: tzts1 {
>> + polling-delay-passive = <0>;
>> + polling-delay = <0>;
>> + thermal-sensors = < 1>;
>> + sustainable-power = <5000>;
>> + trips {};
>> + cooling-maps {};
>> + };
>> +
>> + tzts2: tzts2 {
>> + polling-delay-passive = <0>;
>> + polling-delay = <0>;
>> + thermal-sensors = < 2>;
>> + sustainable-power = <5000>;
>> + trips {};
>> + cooling-maps {};
>> + };
>> +
>> + tzts3: tzts3 {
>> + polling-delay-passive = <0>;
>> + polling-delay = <0>;
>> + thermal-sensors = < 3>;
>> + sustainable-power = <5000>;
>> + trips {};
>> + cooling-maps {};
>> + };
>> +
>> + tzts4: tzts4 {
>> + polling-delay-passive = <0>;
>> + polling-delay = <0>;
>> + thermal-sensors = < 4>;
>> + sustainable-power = <5000>;
>> + trips {};
>> + cooling-maps {};
>> + };
>> +
>> + tzts5: tzts5 {
>> + polling-delay-passive = <0>;
>> + polling-delay = <0>;
>> + thermal-sensors = < 5>;
>> + sustainable-power = <5000>;
>> + trips {};
>> + cooling-maps {};
>> + };
>> +
>> + tztsABB: tztsABB {
>> + polling-delay-passive = <0>;
>> + polling-delay = <0>;
>> + thermal-sensors = < 6>;
>> + sustainable-power = <5000>;
>> + trips {};
>> + cooling-maps {};
>> + };
>> + };
>> +
>> pwm0: pwm@1100e000 {
>> compatible = "mediatek,mt8183-disp-pwm";
>> reg = <0 0x1100e000 0 0x1000>;
>> @@ -926,6 +1007,10 @@
>>
Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node
On 26/02/2021 11:59, Mason Zhang wrote:
> this patch add spi master dts node for mt6779 SOC.
>
> Signed-off-by: Mason Zhang
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96
> 1 file changed, 96 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..ca72eb09cff9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -219,6 +219,102 @@
> status = "disabled";
> };
>
> + spi0: spi0@1100a000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1100a000 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI0>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
Please also update binding description accordingling and add as another patch. I
wasn't able to find a 2/2 neither. I foudn v1 2/2 which on a quick look seemed
the same as this patch.
Regards,
Matthias
> +
> + spi1: spi1@1101 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI1>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi2: spi2@11012000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11012000 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI2>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi3: spi3@11013000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11013000 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI3>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi4: spi4@11018000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11018000 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI4>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi5: spi5@11019000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x11019000 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI5>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi6: spi6@1101d000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101d000 0 0x1000>;
> + interrupts = ;
> + clocks = < CLK_TOP_MAINPLL_D5_D2>,
> + < CLK_TOP_SPI>,
> + <_ao CLK_INFRA_SPI6>;
> + clock-names = "parent-clk", "sel-clk", "spi-clk";
> + };
> +
> + spi7: spi7@1101e000 {
> + compatible = "mediatek,mt6779-spi",
> + "mediatek,mt6765-spi";
> + mediatek,pad-select = <0>;
> + reg = <0 0x1101e000 0 0x1000>;
> +
Re: [PATCH v7 04/11] mfd: mt6360: Combine mt6360 pmic/ldo resources into mt6360 regulator resources
On 02/03/2021 08:16, Gene Chen wrote:
> Lee Jones 於 2021年1月15日 週五 下午3:32寫道：
>>
>> On Fri, 15 Jan 2021, Gene Chen wrote:
>>
>>> Matthias Brugger 於 2021年1月12日 週二 下午8:32寫道：
>>>>
>>>>
>>>>
>>>> On 12/11/2020 11:39, Gene Chen wrote:
>>>>> From: Gene Chen
>>>>>
>>>>> Combine mt6360 pmic/ldo resources into mt6360 regulator resources
>>>>> to simplify the similar resources object.
>>>>>
>>>>> Signed-off-by: Gene Chen
>>>>> Acked-for-MFD-by: Lee Jones
>>>>> ---
>>>>> drivers/mfd/mt6360-core.c | 11 +++
>>>>> 1 file changed, 3 insertions(+), 8 deletions(-)
>>>>>
>>>>> diff --git a/drivers/mfd/mt6360-core.c b/drivers/mfd/mt6360-core.c
>>>>> index 692e47b..5119e51 100644
>>>>> --- a/drivers/mfd/mt6360-core.c
>>>>> +++ b/drivers/mfd/mt6360-core.c
>>>>> @@ -265,7 +265,7 @@ static const struct resource mt6360_led_resources[] =
>>>>> {
>>>>> DEFINE_RES_IRQ_NAMED(MT6360_FLED1_STRB_TO_EVT, "fled1_strb_to_evt"),
>>>>> };
>>>>>
>>>>> -static const struct resource mt6360_pmic_resources[] = {
>>>>> +static const struct resource mt6360_regulator_resources[] = {
>>>>> DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_PGB_EVT, "buck1_pgb_evt"),
>>>>> DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OC_EVT, "buck1_oc_evt"),
>>>>> DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OV_EVT, "buck1_ov_evt"),
>>>>> @@ -278,9 +278,6 @@ static const struct resource mt6360_pmic_resources[]
>>>>> = {
>>>>> DEFINE_RES_IRQ_NAMED(MT6360_LDO7_OC_EVT, "ldo7_oc_evt"),
>>>>> DEFINE_RES_IRQ_NAMED(MT6360_LDO6_PGB_EVT, "ldo6_pgb_evt"),
>>>>> DEFINE_RES_IRQ_NAMED(MT6360_LDO7_PGB_EVT, "ldo7_pgb_evt"),
>>>>> -};
>>>>> -
>>>>> -static const struct resource mt6360_ldo_resources[] = {
>>>>> DEFINE_RES_IRQ_NAMED(MT6360_LDO1_OC_EVT, "ldo1_oc_evt"),
>>>>> DEFINE_RES_IRQ_NAMED(MT6360_LDO2_OC_EVT, "ldo2_oc_evt"),
>>>>> DEFINE_RES_IRQ_NAMED(MT6360_LDO3_OC_EVT, "ldo3_oc_evt"),
>>>>> @@ -298,10 +295,8 @@ static const struct mfd_cell mt6360_devs[] = {
>>>>> NULL, 0, 0, "mediatek,mt6360-chg"),
>>>>> OF_MFD_CELL("mt6360-led", mt6360_led_resources,
>>>>> NULL, 0, 0, "mediatek,mt6360-led"),
>>>>> - OF_MFD_CELL("mt6360-pmic", mt6360_pmic_resources,
>>>>> - NULL, 0, 0, "mediatek,mt6360-pmic"),
>>>>> - OF_MFD_CELL("mt6360-ldo", mt6360_ldo_resources,
>>>>> - NULL, 0, 0, "mediatek,mt6360-ldo"),
>>>>> + OF_MFD_CELL("mt6360-regulator", mt6360_regulator_resources,
>>>>> + NULL, 0, 0, "mediatek,mt6360-regulator"),
>>>>
>>>> As discussed with the MFD maintainer [1], the regulator (and probably all
>>>> cells)
>>>> shouldn't have a DT binding.
>>>>
>>>> So please send a new version which fixes that.
>>>>
>>>> Regards,
>>>> Matthias
>>>>
>>>> [1]
>>>> https://lore.kernel.org/linux-mediatek/2021064118.ge4...@sirena.org.uk/
>>
>> I don't think Mark is correct here.
>>
>> We usually do implement compatible strings for sub-devices and they do
>> tend to have their own device nodes.
>>
>> It's a very long time ago since I coded this up myself, but from
>> memory, you can't have 2 devices share a compatible string.
>>
>
> Either Mark or Lee suggestion is work.
> Is there a conclusion that we can apply it?
> If MFD is already supported of_compatible, we prefer use of_compatible
> mapping.
>
For regulator on PMIC you should add the regulator to the pmic node directly.
Please see the series from Hsin-Hsiung for referece:
https://lore.kernel.org/linux-mediatek/1615829757-3223-6-git-send-email-hsin-hsiung.w...@mediatek.com/T/#u
Regards,
Matthias
>>> Should I use parent's device to find sub-devices of_node if without
>>> compatible name?
>>> I trace the function mfd_add_device,
>>>
>>> if (IS_ENABLED(CONFIG_OF) && parent->of_node && cell->of_compatible) {
>>> .
>>> ret = mfd_match_of_node_to_dev(pdev, np, cell);
>>> .
>>> }
>>>
>>> which is binding mfd sub-device with compatible. Does it be removed in
>>> the feature?
>>>
>>>>> OF_MFD_CELL("mt6360-tcpc", NULL,
>>>>> NULL, 0, 0, "mediatek,mt6360-tcpc"),
>>>>> };
>>>>>
>>
>> --
>> Lee Jones [李琼斯]
>> Senior Technical Lead - Developer Services
>> Linaro.org │ Open source software for Arm SoCs
>> Follow Linaro: Facebook | Twitter | Blog
Re: [PATCH 1/2] drivers/clocksource/mediatek: Split mediatek drivers into 2 files
On 18/03/2021 06:04, Evan Benn wrote:
> mtk_gpt and mtk_syst drivers for mt6577 and mt6765 devices were not
> sharing any code. So split them into separate files.
>
> Signed-off-by: Evan Benn
> ---
>
> arch/arm/mach-mediatek/Kconfig| 3 +-
> arch/arm64/Kconfig.platforms | 3 +-
> drivers/clocksource/Kconfig | 13 +-
> drivers/clocksource/Makefile | 3 +-
> ...mer-mediatek.c => timer-mediatek-mt6577.c} | 100 -
> drivers/clocksource/timer-mediatek-mt6765.c | 135 ++
> 6 files changed, 151 insertions(+), 106 deletions(-)
> rename drivers/clocksource/{timer-mediatek.c => timer-mediatek-mt6577.c}
> (69%)
> create mode 100644 drivers/clocksource/timer-mediatek-mt6765.c
>
[...]
> diff --git a/drivers/clocksource/timer-mediatek-mt6765.c
> b/drivers/clocksource/timer-mediatek-mt6765.c
> new file mode 100644
> index ..b4f22f226feb
> --- /dev/null
> +++ b/drivers/clocksource/timer-mediatek-mt6765.c
> @@ -0,0 +1,135 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Mediatek SoCs General-Purpose Timer handling.
> + *
> + * Copyright (C) 2014 Matthias Brugger
> + *
> + * Matthias Brugger
The mt6765 was written by Stanley, I think we should reflcet that. Please see:
e3af677607d9 ("clocksource/drivers/timer-mediatek: Add support for system
timer")
Regards,
Matthias
Re: [PATCH v2] arm64: dts: mt8183: Add gce client reg for display subcomponents
On 24/03/2021 08:08, Hsin-Yi Wang wrote:
> Add mediatek,gce-client-reg for mmsys, ccorr, aal, gamma, dither.
>
> Fixes: 91f9c963ce79 ("arm64: dts: mt8183: Add display nodes for MT8183")
> Signed-off-by: Hsin-Yi Wang
> Tested-by: Enric Balletbo i Serra
Applied to v5.12-next/dts64
Thanks!
> ---
> v1->v2:
> Add for mmsys.
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 80519a145f13..16f4b1fc0fb9 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -983,6 +983,9 @@ mmsys: syscon@1400 {
> compatible = "mediatek,mt8183-mmsys", "syscon";
> reg = <0 0x1400 0 0x1000>;
> #clock-cells = <1>;
> + mboxes = < 0 CMDQ_THR_PRIO_HIGHEST>,
> + < 1 CMDQ_THR_PRIO_HIGHEST>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0
> 0x1000>;
> };
>
> ovl0: ovl@14008000 {
> @@ -1058,6 +1061,7 @@ ccorr0: ccorr@1400f000 {
> interrupts = ;
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> clocks = < CLK_MM_DISP_CCORR0>;
> + mediatek,gce-client-reg = < SUBSYS_1400 0xf000
> 0x1000>;
> };
>
> aal0: aal@1401 {
> @@ -1067,6 +1071,7 @@ aal0: aal@1401 {
> interrupts = ;
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> clocks = < CLK_MM_DISP_AAL0>;
> + mediatek,gce-client-reg = < SUBSYS_1401 0
> 0x1000>;
> };
>
> gamma0: gamma@14011000 {
> @@ -1075,6 +1080,7 @@ gamma0: gamma@14011000 {
> interrupts = ;
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> clocks = < CLK_MM_DISP_GAMMA0>;
> + mediatek,gce-client-reg = < SUBSYS_1401 0x1000
> 0x1000>;
> };
>
> dither0: dither@14012000 {
> @@ -1083,6 +1089,7 @@ dither0: dither@14012000 {
> interrupts = ;
> power-domains = < MT8183_POWER_DOMAIN_DISP>;
> clocks = < CLK_MM_DISP_DITHER0>;
> + mediatek,gce-client-reg = < SUBSYS_1401 0x2000
> 0x1000>;
> };
>
> dsi0: dsi@14014000 {
>
Re: [PATCH v6 8/8] arm64: dts: mt6359: add PMIC MT6359 related nodes
On 15/03/2021 18:35, Hsin-Hsiung Wang wrote:
> From: Wen Su
>
> add PMIC MT6359 related nodes which is for MT6779 platform
>
> Signed-off-by: Wen Su
> Signed-off-by: Hsin-Hsiung Wang
> ---
> changes since v5:
> - update file date.
> ---
> arch/arm64/boot/dts/mediatek/mt6359.dtsi| 298
> arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 1 +
> 2 files changed, 299 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt6359.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi
> b/arch/arm64/boot/dts/mediatek/mt6359.dtsi
> new file mode 100644
> index ..84235db460f8
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi
> @@ -0,0 +1,298 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> + {
> + pmic: pmic {
> + compatible = "mediatek,mt6359";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + mt6359codec: mt6359codec {
> + };
> +
> + mt6359regulator: regulators {
should be just:
regulators {
Other than that looks good to me.
Regards,
Matthias
> + mt6359_vs1_buck_reg: buck_vs1 {
> + regulator-name = "vs1";
> + regulator-min-microvolt = <80>;
> + regulator-max-microvolt = <220>;
> + regulator-enable-ramp-delay = <0>;
> + regulator-always-on;
> + };
> + mt6359_vgpu11_buck_reg: buck_vgpu11 {
> + regulator-name = "vgpu11";
> + regulator-min-microvolt = <40>;
> + regulator-max-microvolt = <1193750>;
> + regulator-ramp-delay = <5000>;
> + regulator-enable-ramp-delay = <200>;
> + regulator-allowed-modes = <0 1 2>;
> + };
> + mt6359_vmodem_buck_reg: buck_vmodem {
> + regulator-name = "vmodem";
> + regulator-min-microvolt = <40>;
> + regulator-max-microvolt = <110>;
> + regulator-ramp-delay = <10760>;
> + regulator-enable-ramp-delay = <200>;
> + };
> + mt6359_vpu_buck_reg: buck_vpu {
> + regulator-name = "vpu";
> + regulator-min-microvolt = <40>;
> + regulator-max-microvolt = <1193750>;
> + regulator-ramp-delay = <5000>;
> + regulator-enable-ramp-delay = <200>;
> + regulator-allowed-modes = <0 1 2>;
> + };
> + mt6359_vcore_buck_reg: buck_vcore {
> + regulator-name = "vcore";
> + regulator-min-microvolt = <40>;
> + regulator-max-microvolt = <130>;
> + regulator-ramp-delay = <5000>;
> + regulator-enable-ramp-delay = <200>;
> + regulator-allowed-modes = <0 1 2>;
> + };
> + mt6359_vs2_buck_reg: buck_vs2 {
> + regulator-name = "vs2";
> + regulator-min-microvolt = <80>;
> + regulator-max-microvolt = <160>;
> + regulator-enable-ramp-delay = <0>;
> + regulator-always-on;
> + };
> + mt6359_vpa_buck_reg: buck_vpa {
> + regulator-name = "vpa";
> + regulator-min-microvolt = <50>;
> + regulator-max-microvolt = <365>;
> + regulator-enable-ramp-delay = <300>;
> + };
> + mt6359_vproc2_buck_reg: buck_vproc2 {
> + regulator-name = "vproc2";
> + regulator-min-microvolt = <40>;
> + regulator-max-microvolt = <1193750>;
> + regulator-ramp-delay = <7500>;
> + regulator-enable-ramp-delay = <200>;
> + regulator-allowed-modes = <0 1 2>;
> + };
> + mt6359_vproc1_buck_reg: buck_vproc1 {
> + regulator-name = "vproc1";
> + regulator-min-microvolt = <40>;
> + regulator-max-microvolt = <1193750>;
> + regulator-ramp-delay = <7500>;
> +
Re: [PATCH v5 13/13] arm: dts: mt2701: harmonize node names and compatibles
On 16/03/2021 10:22, Chunfeng Yun wrote:
> This is used to fix dtbs_check warning
>
> Signed-off-by: Chunfeng Yun
Applied now to v5.12-next/dts32
> ---
> v2~v5: no changes
> ---
> arch/arm/boot/dts/mt2701.dtsi | 19 +++
> 1 file changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index fade14284017..4776f85d6d5b 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -607,7 +607,7 @@
> };
>
> usb0: usb@1a1c {
> - compatible = "mediatek,mt8173-xhci";
> + compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci";
> reg = <0 0x1a1c 0 0x1000>,
> <0 0x1a1c4700 0 0x0100>;
> reg-names = "mac", "ippc";
> @@ -620,8 +620,9 @@
> status = "disabled";
> };
>
> - u3phy0: usb-phy@1a1c4000 {
> - compatible = "mediatek,mt2701-u3phy";
> + u3phy0: t-phy@1a1c4000 {
> + compatible = "mediatek,mt2701-tphy",
> + "mediatek,generic-tphy-v1";
> reg = <0 0x1a1c4000 0 0x0700>;
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -646,7 +647,7 @@
> };
>
> usb1: usb@1a24 {
> - compatible = "mediatek,mt8173-xhci";
> + compatible = "mediatek,mt2701-xhci", "mediatek,mtk-xhci";
> reg = <0 0x1a24 0 0x1000>,
> <0 0x1a244700 0 0x0100>;
> reg-names = "mac", "ippc";
> @@ -659,8 +660,9 @@
> status = "disabled";
> };
>
> - u3phy1: usb-phy@1a244000 {
> - compatible = "mediatek,mt2701-u3phy";
> + u3phy1: t-phy@1a244000 {
> + compatible = "mediatek,mt2701-tphy",
> + "mediatek,generic-tphy-v1";
> reg = <0 0x1a244000 0 0x0700>;
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -700,8 +702,9 @@
> status = "disabled";
> };
>
> - u2phy0: usb-phy@1121 {
> - compatible = "mediatek,generic-tphy-v1";
> + u2phy0: t-phy@1121 {
> + compatible = "mediatek,mt2701-tphy",
> + "mediatek,generic-tphy-v1";
> reg = <0 0x1121 0 0x0800>;
> #address-cells = <2>;
> #size-cells = <2>;
>
Re: [PATCH v5 10/13] arm64: dts: mediatek: mt8183: fix dtbs_check warning
On 16/03/2021 10:22, Chunfeng Yun wrote:
> Harmonize node names, compatibles and properties.
>
> Signed-off-by: Chunfeng Yun
Applied now to v5.12-next/dts64
> ---
> v4~v5: no changes
> v3: remove property clock-names suggested by CK
> v2: no changes
> ---
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 8 +++-
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 80519a145f13..8882d35ac6ab 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -880,7 +880,7 @@
> ranges;
> status = "disabled";
>
> - usb_host: xhci@1120 {
> + usb_host: usb@1120 {
> compatible = "mediatek,mt8183-xhci",
>"mediatek,mtk-xhci";
> reg = <0 0x1120 0 0x1000>;
> @@ -923,11 +923,10 @@
> status = "disabled";
> };
>
> - mipi_tx0: mipi-dphy@11e5 {
> + mipi_tx0: dsi-phy@11e5 {
> compatible = "mediatek,mt8183-mipi-tx";
> reg = <0 0x11e5 0 0x1000>;
> clocks = < CLK_APMIXED_MIPID0_26M>;
> - clock-names = "ref_clk";
> #clock-cells = <0>;
> #phy-cells = <0>;
> clock-output-names = "mipi_tx0_pll";
> @@ -946,11 +945,10 @@
> };
> };
>
> - u3phy: usb-phy@11f4 {
> + u3phy: t-phy@11f4 {
> compatible = "mediatek,mt8183-tphy",
>"mediatek,generic-tphy-v2";
> #address-cells = <1>;
> - #phy-cells = <1>;
> #size-cells = <1>;
> ranges = <0 0 0x11f4 0x1000>;
> status = "okay";
>
Re: [PATCH v5 12/13] arm: dts: mt7623: harmonize node names and compatibles
On 16/03/2021 10:22, Chunfeng Yun wrote:
> This is used to fix dtbs_check warning
>
> Signed-off-by: Chunfeng Yun
Applied now to v5.12-next/dts32
> ---
> v2~v5: no changes
> ---
> arch/arm/boot/dts/mt7623.dtsi | 26 ++
> arch/arm/boot/dts/mt7623n.dtsi | 4 ++--
> 2 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
> index aea6809500d7..3c11f7cfcc40 100644
> --- a/arch/arm/boot/dts/mt7623.dtsi
> +++ b/arch/arm/boot/dts/mt7623.dtsi
> @@ -787,8 +787,9 @@
> };
> };
>
> - pcie0_phy: pcie-phy@1a149000 {
> - compatible = "mediatek,generic-tphy-v1";
> + pcie0_phy: t-phy@1a149000 {
> + compatible = "mediatek,mt7623-tphy",
> + "mediatek,generic-tphy-v1";
> reg = <0 0x1a149000 0 0x0700>;
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -804,8 +805,9 @@
> };
> };
>
> - pcie1_phy: pcie-phy@1a14a000 {
> - compatible = "mediatek,generic-tphy-v1";
> + pcie1_phy: t-phy@1a14a000 {
> + compatible = "mediatek,mt7623-tphy",
> + "mediatek,generic-tphy-v1";
> reg = <0 0x1a14a000 0 0x0700>;
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -823,7 +825,7 @@
>
> usb1: usb@1a1c {
> compatible = "mediatek,mt7623-xhci",
> - "mediatek,mt8173-xhci";
> + "mediatek,mtk-xhci";
> reg = <0 0x1a1c 0 0x1000>,
> <0 0x1a1c4700 0 0x0100>;
> reg-names = "mac", "ippc";
> @@ -836,9 +838,9 @@
> status = "disabled";
> };
>
> - u3phy1: usb-phy@1a1c4000 {
> - compatible = "mediatek,mt7623-u3phy",
> - "mediatek,mt2701-u3phy";
> + u3phy1: t-phy@1a1c4000 {
> + compatible = "mediatek,mt7623-tphy",
> + "mediatek,generic-tphy-v1";
> reg = <0 0x1a1c4000 0 0x0700>;
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -864,7 +866,7 @@
>
> usb2: usb@1a24 {
> compatible = "mediatek,mt7623-xhci",
> - "mediatek,mt8173-xhci";
> + "mediatek,mtk-xhci";
> reg = <0 0x1a24 0 0x1000>,
> <0 0x1a244700 0 0x0100>;
> reg-names = "mac", "ippc";
> @@ -877,9 +879,9 @@
> status = "disabled";
> };
>
> - u3phy2: usb-phy@1a244000 {
> - compatible = "mediatek,mt7623-u3phy",
> - "mediatek,mt2701-u3phy";
> + u3phy2: t-phy@1a244000 {
> + compatible = "mediatek,mt7623-tphy",
> + "mediatek,generic-tphy-v1";
> reg = <0 0x1a244000 0 0x0700>;
> #address-cells = <2>;
> #size-cells = <2>;
> diff --git a/arch/arm/boot/dts/mt7623n.dtsi b/arch/arm/boot/dts/mt7623n.dtsi
> index 1880ac9e32cf..bcb0846e29fd 100644
> --- a/arch/arm/boot/dts/mt7623n.dtsi
> +++ b/arch/arm/boot/dts/mt7623n.dtsi
> @@ -246,7 +246,7 @@
> status = "disabled";
> };
>
> - mipi_tx0: mipi-dphy@1001 {
> + mipi_tx0: dsi-phy@1001 {
> compatible = "mediatek,mt7623-mipi-tx",
>"mediatek,mt2701-mipi-tx";
> reg = <0 0x1001 0 0x90>;
> @@ -265,7 +265,7 @@
> status = "disabled";
> };
>
> - hdmi_phy: phy@10209100 {
> + hdmi_phy: hdmi-phy@10209100 {
> compatible = "mediatek,mt7623-hdmi-phy",
>"mediatek,mt2701-hdmi-phy";
> reg = <0 0x10209100 0 0x24>;
>
Re: [PATCH v5 11/13] arm: dts: mt7629: harmonize node names and compatibles
On 16/03/2021 10:22, Chunfeng Yun wrote:
> This is used to fix dtbs_check warning
>
> Signed-off-by: Chunfeng Yun
Applied now to v5.12-next/dts32
> ---
> v2~v5: no changes
> ---
> arch/arm/boot/dts/mt7629.dtsi | 12 +++-
> 1 file changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi
> index 5cbb3d244c75..874043f0490d 100644
> --- a/arch/arm/boot/dts/mt7629.dtsi
> +++ b/arch/arm/boot/dts/mt7629.dtsi
> @@ -329,8 +329,9 @@
> status = "disabled";
> };
>
> - u3phy0: usb-phy@1a0c4000 {
> - compatible = "mediatek,generic-tphy-v2";
> + u3phy0: t-phy@1a0c4000 {
> + compatible = "mediatek,mt7629-tphy",
> + "mediatek,generic-tphy-v2";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0 0x1a0c4000 0xe00>;
> @@ -413,14 +414,15 @@
> };
> };
>
> - pciephy1: pcie-phy@1a14a000 {
> - compatible = "mediatek,generic-tphy-v2";
> + pciephy1: t-phy@1a14a000 {
> + compatible = "mediatek,mt7629-tphy",
> + "mediatek,generic-tphy-v2";
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0 0x1a14a000 0x1000>;
> status = "disabled";
>
> - pcieport1: port1phy@0 {
> + pcieport1: pcie-phy@0 {
> reg = <0 0x1000>;
> clocks = <>;
> clock-names = "ref";
>
Re: [PATCH v5 09/13] arm64: dts: mediatek: mt7622: harmonize node names and compatibles
On 16/03/2021 10:22, Chunfeng Yun wrote:
> This is used to fix dtbs_check warning
>
> Signed-off-by: Chunfeng Yun
Applied now to v5.12-next/dts64
> ---
> v2~v5: no changes
> ---
> arch/arm64/boot/dts/mediatek/mt7622.dtsi | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> index 7c6d871538a6..890a942ec608 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> @@ -742,8 +742,8 @@
> status = "disabled";
> };
>
> - u3phy: usb-phy@1a0c4000 {
> - compatible = "mediatek,mt7622-u3phy",
> + u3phy: t-phy@1a0c4000 {
> + compatible = "mediatek,mt7622-tphy",
>"mediatek,generic-tphy-v1";
> reg = <0 0x1a0c4000 0 0x700>;
> #address-cells = <2>;
> @@ -877,8 +877,9 @@
> status = "disabled";
> };
>
> - sata_phy: sata-phy@1a243000 {
> - compatible = "mediatek,generic-tphy-v1";
> + sata_phy: t-phy@1a243000 {
> + compatible = "mediatek,mt7622-tphy",
> + "mediatek,generic-tphy-v1";
> #address-cells = <2>;
> #size-cells = <2>;
> ranges;
>
Re: [PATCH v5 08/13] arm64: dts: mediatek: mt8516: harmonize node names and compatibles
On 16/03/2021 10:22, Chunfeng Yun wrote:
> This is used to fix dtbs_check warning:
> harmonize node names and compatibles;
> add property "usb-role-switch" for connector dependence.
>
> Signed-off-by: Chunfeng Yun
Applied now to v5.12-next/dts64
> ---
> v2~v5: no changes
> ---
> arch/arm64/boot/dts/mediatek/mt8516.dtsi | 9 +
> arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi | 1 +
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
> index b80e95574bef..bbe5a1419eff 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
> @@ -480,7 +480,7 @@
> };
>
> usb0: usb@1110 {
> - compatible = "mediatek,mtk-musb";
> + compatible = "mediatek,mt8516-musb",
> "mediatek,mtk-musb";
> reg = <0 0x1110 0 0x1000>;
> interrupts = ;
> interrupt-names = "mc";
> @@ -493,7 +493,7 @@
> };
>
> usb1: usb@1119 {
> - compatible = "mediatek,mtk-musb";
> + compatible = "mediatek,mt8516-musb",
> "mediatek,mtk-musb";
> reg = <0 0x1119 0 0x1000>;
> interrupts = ;
> interrupt-names = "mc";
> @@ -506,8 +506,9 @@
> status = "disabled";
> };
>
> - usb_phy: usb@ {
> - compatible = "mediatek,generic-tphy-v1";
> + usb_phy: t-phy@ {
> + compatible = "mediatek,mt8516-tphy",
> + "mediatek,generic-tphy-v1";
> reg = <0 0x 0 0x800>;
> #address-cells = <2>;
> #size-cells = <2>;
> diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
> b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
> index 63fd70086bb8..7d738f01cf8d 100644
> --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
> @@ -188,6 +188,7 @@
> {
> status = "okay";
> dr_mode = "peripheral";
> + usb-role-switch;
>
> usb_con: connector {
> compatible = "usb-c-connector";
>
Re: [PATCH v5 07/13] arm64: dts: mediatek: mt2712: harmonize node names
On 16/03/2021 10:22, Chunfeng Yun wrote:
> This is used to fix dtbs_check warning.
>
> Signed-off-by: Chunfeng Yun
Applied now to v5.12-next/dts64
> ---
> v2~v5: no changes
> ---
> arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> index db17d0a4ed57..a9cca9c146fd 100644
> --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> @@ -805,7 +805,7 @@
> ranges;
> status = "disabled";
>
> - usb_host0: xhci@1127 {
> + usb_host0: usb@1127 {
> compatible = "mediatek,mt2712-xhci",
>"mediatek,mtk-xhci";
> reg = <0 0x1127 0 0x1000>;
> @@ -818,7 +818,7 @@
> };
> };
>
> - u3phy0: usb-phy@1129 {
> + u3phy0: t-phy@1129 {
> compatible = "mediatek,mt2712-tphy",
>"mediatek,generic-tphy-v2";
> #address-cells = <1>;
> @@ -869,7 +869,7 @@
> ranges;
> status = "disabled";
>
> - usb_host1: xhci@112c {
> + usb_host1: usb@112c {
> compatible = "mediatek,mt2712-xhci",
>"mediatek,mtk-xhci";
> reg = <0 0x112c 0 0x1000>;
> @@ -882,7 +882,7 @@
> };
> };
>
> - u3phy1: usb-phy@112e {
> + u3phy1: t-phy@112e {
> compatible = "mediatek,mt2712-tphy",
>"mediatek,generic-tphy-v2";
> #address-cells = <1>;
>
Re: [PATCH v5 06/13] arm64: dts: mediatek: mt8173: fix dtbs_check warning
On 16/03/2021 10:22, Chunfeng Yun wrote:
> Harmonize nodes names, compatibles and remove unused property.
>
> Signed-off-by: Chunfeng Yun
Applied now to v5.12-next/dts64
> ---
> v2~v5: no changes
> ---
> arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 4 +---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi| 13 +++--
> 2 files changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> index 6dffada2e66b..0ce81c4fe81e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
> @@ -516,10 +516,8 @@
> extcon = <_usb>;
> dr_mode = "otg";
> wakeup-source;
> - pinctrl-names = "default", "id_float", "id_ground";
> + pinctrl-names = "default";
> pinctrl-0 = <_id_pins_float>;
> - pinctrl-1 = <_id_pins_float>;
> - pinctrl-2 = <_id_pins_ground>;
> status = "okay";
> };
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index ecb37a7e6870..003a5653c505 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -631,7 +631,7 @@
> #mbox-cells = <2>;
> };
>
> - mipi_tx0: mipi-dphy@10215000 {
> + mipi_tx0: dsi-phy@10215000 {
> compatible = "mediatek,mt8173-mipi-tx";
> reg = <0 0x10215000 0 0x1000>;
> clocks = <>;
> @@ -641,7 +641,7 @@
> status = "disabled";
> };
>
> - mipi_tx1: mipi-dphy@10216000 {
> + mipi_tx1: dsi-phy@10216000 {
> compatible = "mediatek,mt8173-mipi-tx";
> reg = <0 0x10216000 0 0x1000>;
> clocks = <>;
> @@ -926,7 +926,7 @@
> };
>
> ssusb: usb@11271000 {
> - compatible = "mediatek,mt8173-mtu3";
> + compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
> reg = <0 0x11271000 0 0x3000>,
> <0 0x11280700 0 0x0100>;
> reg-names = "mac", "ippc";
> @@ -943,8 +943,9 @@
> ranges;
> status = "disabled";
>
> - usb_host: xhci@1127 {
> - compatible = "mediatek,mt8173-xhci";
> + usb_host: usb@1127 {
> + compatible = "mediatek,mt8173-xhci",
> + "mediatek,mtk-xhci";
> reg = <0 0x1127 0 0x1000>;
> reg-names = "mac";
> interrupts = ;
> @@ -955,7 +956,7 @@
> };
> };
>
> - u3phy: usb-phy@1129 {
> + u3phy: t-phy@1129 {
> compatible = "mediatek,mt8173-u3phy";
> reg = <0 0x1129 0 0x800>;
> #address-cells = <2>;
>
Re: [PATCH v5 05/13] arm64: dts: mt8173: fix property typo of 'phys' in dsi node
On 16/03/2021 10:22, Chunfeng Yun wrote:
> Use 'phys' instead of 'phy'.
>
> Fixes: 81ad4dbaf7af ("arm64: dts: mt8173: Add display subsystem related
> nodes")
> Cc: stable
> Reviewed-by: Chun-Kuang Hu
> Signed-off-by: Chunfeng Yun
Applied now to v5.12-next/dts64
> ---
> v5: merged into this series, add Reviewed-by CK
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 7fa870e4386a..ecb37a7e6870 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -1235,7 +1235,7 @@
>< CLK_MM_DSI1_DIGITAL>,
><_tx1>;
> clock-names = "engine", "digital", "hs";
> - phy = <_tx1>;
> + phys = <_tx1>;
> phy-names = "dphy";
> status = "disabled";
> };
>
Re: [PATCH v2 6/8] dt-bindings: arm: Add compatible for Mediatek MT8195
On 19/03/2021 03:34, Seiya Wang wrote: > This commit adds dt-binding documentation for the Mediatek MT8195 > reference board. > > Signed-off-by: Seiya Wang Applied to v5.12-next/dts64 Thanks! > --- > Documentation/devicetree/bindings/arm/mediatek.yaml | 4 > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml > b/Documentation/devicetree/bindings/arm/mediatek.yaml > index 93b3bdf6eaeb..a95224fcff9f 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek.yaml > +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml > @@ -118,6 +118,10 @@ properties: >- enum: >- mediatek,mt8183-evb >- const: mediatek,mt8183 > + - items: > + - enum: > + - mediatek,mt8195-evb > + - const: mediatek,mt8195 >- description: Google Krane (Lenovo IdeaPad Duet, 10e,...) > items: >- enum: >
Re: [PATCH v2 2/8] dt-bindings: serial: Add compatible for Mediatek MT8195
On 19/03/2021 03:34, Seiya Wang wrote: > This commit adds dt-binding documentation of uart for Mediatek MT8195 SoC > Platform. > > Signed-off-by: Seiya Wang Applied to v5.12-next/dts64 Thanks! > --- > Documentation/devicetree/bindings/serial/mtk-uart.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/serial/mtk-uart.txt > b/Documentation/devicetree/bindings/serial/mtk-uart.txt > index 647b5aee86f3..64c4fb59acd1 100644 > --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt > +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt > @@ -20,6 +20,7 @@ Required properties: >* "mediatek,mt8173-uart" for MT8173 compatible UARTS >* "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible > UARTS >* "mediatek,mt8192-uart", "mediatek,mt6577-uart" for MT8192 compatible > UARTS > + * "mediatek,mt8195-uart", "mediatek,mt6577-uart" for MT8195 compatible > UARTS >* "mediatek,mt8516-uart" for MT8516 compatible UARTS >* "mediatek,mt6577-uart" for MT6577 and all of the above > >
Re: [PATCH v2 1/8] dt-bindings: timer: Add compatible for Mediatek MT8195
On 19/03/2021 03:34, Seiya Wang wrote: > This commit adds dt-binding documentation of timer for Mediatek MT8195 SoC > Platform. > > Signed-off-by: Seiya Wang Applied to v5.12-next/dts64 Thanks! > --- > Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt > b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt > index 690a9c0966ac..e5c57d6e0186 100644 > --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt > +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt > @@ -23,6 +23,7 @@ Required properties: > For those SoCs that use SYST > * "mediatek,mt8183-timer" for MT8183 compatible timers (SYST) > * "mediatek,mt8192-timer" for MT8192 compatible timers (SYST) > + * "mediatek,mt8195-timer" for MT8195 compatible timers (SYST) > * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST) > * "mediatek,mt6765-timer" for MT6765 and all above compatible timers > (SYST) > >
Re: [PATCH v4 1/4] dt-bindings: arm64: dts: mediatek: Add mt8183-kukui-jacuzzi-damu
On 19/03/2021 04:52, Hsin-Yi Wang wrote: > mt8183-kukui-jacuzzi-damu board also known as ASUS Chromebook Flip CM3, > using mediatek mt8183 SoC. > > Signed-off-by: Hsin-Yi Wang > Reviewed-by: Enric Balletbo i Serra Whole series applied to v5.12-next/dts64 Thanks > --- > Documentation/devicetree/bindings/arm/mediatek.yaml | 4 > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml > b/Documentation/devicetree/bindings/arm/mediatek.yaml > index 93b3bdf6eaeb..a86716cdd408 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek.yaml > +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml > @@ -125,6 +125,10 @@ properties: >- google,krane-sku176 >- const: google,krane >- const: mediatek,mt8183 > + - description: Google Damu (ASUS Chromebook Flip CM3) > +items: > + - const: google,damu > + - const: mediatek,mt8183 > > additionalProperties: true > >
Re: [PATCH 2/2] dt-bindings: cpufreq: update cpu type and clock name for MT8173 SoC
On 26/03/2021 04:12, Seiya Wang wrote:
> Update the cpu type of cpu2 and cpu3 since MT8173 used Cortex-a72.
>
> Signed-off-by: Seiya Wang
Reviewed-by: Matthias Brugger
> ---
> Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
> b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
> index ea4994b35207..ef68711716fb 100644
> --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.txt
> @@ -202,11 +202,11 @@ Example 2 (MT8173 SoC):
>
> cpu2: cpu@100 {
> device_type = "cpu";
> - compatible = "arm,cortex-a57";
> + compatible = "arm,cortex-a72";
> reg = <0x100>;
> enable-method = "psci";
> cpu-idle-states = <_SLEEP_0>;
> - clocks = < CLK_INFRA_CA57SEL>,
> + clocks = < CLK_INFRA_CA72SEL>,
>< CLK_APMIXED_MAINPLL>;
> clock-names = "cpu", "intermediate";
> operating-points-v2 = <_opp_table_b>;
> @@ -214,11 +214,11 @@ Example 2 (MT8173 SoC):
>
> cpu3: cpu@101 {
> device_type = "cpu";
> - compatible = "arm,cortex-a57";
> + compatible = "arm,cortex-a72";
> reg = <0x101>;
> enable-method = "psci";
> cpu-idle-states = <_SLEEP_0>;
> - clocks = < CLK_INFRA_CA57SEL>,
> + clocks = < CLK_INFRA_CA72SEL>,
>< CLK_APMIXED_MAINPLL>;
> clock-names = "cpu", "intermediate";
> operating-points-v2 = <_opp_table_b>;
>
Re: [PATCH 1/2] clk: mediatek: remove deprecated CLK_INFRA_CA57SEL for MT8173 SoC
On 26/03/2021 04:12, Seiya Wang wrote: > Remove CLK_INFRA_CA57SEL for MT8173 since it's no longer used. > > Signed-off-by: Seiya Wang Reviewed-by: Matthias Brugger > --- > include/dt-bindings/clock/mt8173-clk.h | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/include/dt-bindings/clock/mt8173-clk.h > b/include/dt-bindings/clock/mt8173-clk.h > index 3acebe937bfc..3d00c98b9654 100644 > --- a/include/dt-bindings/clock/mt8173-clk.h > +++ b/include/dt-bindings/clock/mt8173-clk.h > @@ -186,7 +186,6 @@ > #define CLK_INFRA_PMICWRAP 11 > #define CLK_INFRA_CLK_13M12 > #define CLK_INFRA_CA53SEL 13 > -#define CLK_INFRA_CA57SEL 14 /* Deprecated. Don't use it. */ > #define CLK_INFRA_CA72SEL 14 > #define CLK_INFRA_NR_CLK15 > >
Re: [PATCH v2 13/13] arm64: dts: mt8183: update wakeup register offset
On 23/03/2021 08:02, Chunfeng Yun wrote: > Use wakeup control register offset exactly, and update revision > number > > Signed-off-by: Chunfeng Yun > --- > v2: modify revision format > --- > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index 80519a145f13..9ea84d636556 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -874,7 +874,7 @@ > clocks = < CLK_INFRA_UNIPRO_SCK>, >< CLK_INFRA_USB>; > clock-names = "sys_ck", "ref_ck"; > - mediatek,syscon-wakeup = < 0x400 0>; > + mediatek,syscon-wakeup = < 0x420 101>; applied to v5.12-next/dts64 Thanks > #address-cells = <2>; > #size-cells = <2>; > ranges; >
Re: [PATCH 1/2] dt-bindings: devapc: Update bindings
On 26/03/2021 08:31, Nina Wu wrote:
> From: Nina Wu
>
> To support newer hardware architecture of devapc,
> update device tree bindings.
>
> Signed-off-by: Nina Wu
> ---
> .../devicetree/bindings/soc/mediatek/devapc.yaml | 41
> ++
> 1 file changed, 41 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
> b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
> index 31e4d3c..489f6a9 100644
> --- a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
> +++ b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml
> @@ -20,9 +20,27 @@ properties:
>compatible:
> enum:
>- mediatek,mt6779-devapc
> + - mediatek,mt8192-devapc
> +
> + version:
> +description: The version of the hardware architecture
> +$ref: /schemas/types.yaml#/definitions/uint32
> +enum: [1, 2]
> +maxItems: 1
> +
> + slave_type_num:
> +description: The number of the devapc set
> +$ref: /schemas/types.yaml#/definitions/uint32
> +enum: [1, 4]
> +maxItems: 1
>
>reg:
> description: The base address of devapc register bank
> +maxItems: 4
> +
> + vio_idx_num:
> +description: The number of the devices controlled by devapc
> +$ref: /schemas/types.yaml#/definitions/uint32-array
This can all per compatible DT data objects in the driver. Don't add new
properties here.
Regards,
Matthias
> maxItems: 1
>
>interrupts:
> @@ -39,7 +57,10 @@ properties:
>
> required:
>- compatible
> + - version
> + - slave_type_num
>- reg
> + - vio_idx_num
>- interrupts
>- clocks
>- clock-names
> @@ -53,8 +74,28 @@ examples:
>
> devapc: devapc@10207000 {
>compatible = "mediatek,mt6779-devapc";
> + version = <1>;
> + slave_type_num = <1>;
>reg = <0x10207000 0x1000>;
> + vio_idx_num = <511>;
>interrupts = ;
>clocks = <_ao CLK_INFRA_DEVICE_APC>;
>clock-names = "devapc-infra-clock";
> };
> + - |
> +#include
> +#include
> +
> +devapc: devapc@10207000 {
> +compatible = "mediatek,mt8192-devapc";
> +version = <2>;
> +slave_type_num = <4>;
> +reg = <0 0x10207000 0 0x1000>,
> +<0 0x10274000 0 0x1000>,
> +<0 0x10275000 0 0x1000>,
> +<0 0x1102 0 0x1000>;
> +vio_idx_num = <367 292 242 58>;
> +interrupts = ;
> +clocks = <_ao CLK_INFRA_DEVICE_APC>;
> +clock-names = "devapc-infra-clock";
> +};
>
Re: [PATCH 2/2] soc: mediatek: Add mt8192 devapc driver
As a general comment:
Please split your patch in several, one introducing changes to the existing code
base which are needed for newer SoCs (depending on the changes more then one)
and one which actually adds support for the new SoC.
More comments below.
On 26/03/2021 08:31, Nina Wu wrote:
> From: Nina Wu
>
> The hardware architecture of mt8192 devapc is slightly
> different from that of the previous IC.
> We add necessary extensions to support mt8192 and be
> back-compatible with other ICs.
>
> Signed-off-by: Nina Wu
> ---
> drivers/soc/mediatek/mtk-devapc.c | 213
> --
> 1 file changed, 156 insertions(+), 57 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-devapc.c
> b/drivers/soc/mediatek/mtk-devapc.c
> index f1cea04..1e40a52 100644
> --- a/drivers/soc/mediatek/mtk-devapc.c
> +++ b/drivers/soc/mediatek/mtk-devapc.c
> @@ -15,6 +15,11 @@
> #define VIO_MOD_TO_REG_IND(m)((m) / 32)
> #define VIO_MOD_TO_REG_OFF(m)((m) % 32)
>
> +#define FOR_EACH_SLAVE_TYPE(ctx, idx) \
> + for ((idx) = 0; (idx) < (ctx)->slave_type_num; (idx)++)
Not really needed, please drop.
> +#define BASE(i) (ctx->base_list[i])
same here.
> +#define VIO_IDX_NUM(i) (ctx->vio_idx_num[i])
same here.
> +
> struct mtk_devapc_vio_dbgs {
> union {
> u32 vio_dbg0;
> @@ -26,20 +31,28 @@ struct mtk_devapc_vio_dbgs {
> u32 addr_h:4;
> u32 resv:4;
> } dbg0_bits;
> +
> + /* Not used, reference only */
> + struct {
> + u32 dmnid:6;
> + u32 vio_w:1;
> + u32 vio_r:1;
> + u32 addr_h:4;
> + u32 resv:20;
> + } dbg0_bits_ver2;
> };
>
> u32 vio_dbg1;
> + u32 vio_dbg2;
> };
>
> struct mtk_devapc_data {
> - /* numbers of violation index */
> - u32 vio_idx_num;
> -
> /* reg offset */
> u32 vio_mask_offset;
> u32 vio_sta_offset;
> u32 vio_dbg0_offset;
> u32 vio_dbg1_offset;
> + u32 vio_dbg2_offset;
> u32 apc_con_offset;
> u32 vio_shift_sta_offset;
> u32 vio_shift_sel_offset;
> @@ -48,7 +61,10 @@ struct mtk_devapc_data {
>
> struct mtk_devapc_context {
> struct device *dev;
> - void __iomem *infra_base;
> + u32 arch_ver;
> + u32 slave_type_num;
> + void __iomem **base_list;
> + u32 *vio_idx_num;
> struct clk *infra_clk;
> const struct mtk_devapc_data *data;
> };
> @@ -56,39 +72,39 @@ struct mtk_devapc_context {
> static void clear_vio_status(struct mtk_devapc_context *ctx)
> {
> void __iomem *reg;
> - int i;
> + int i, j;
>
> - reg = ctx->infra_base + ctx->data->vio_sta_offset;
> + FOR_EACH_SLAVE_TYPE(ctx, i) {
> + reg = BASE(i) + ctx->data->vio_sta_offset;
>
> - for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++)
> - writel(GENMASK(31, 0), reg + 4 * i);
> + for (j = 0; j < VIO_MOD_TO_REG_IND(VIO_IDX_NUM(i) - 1); j++)
> + writel(GENMASK(31, 0), reg + 4 * j);
> +
> + writel(GENMASK(VIO_MOD_TO_REG_OFF(VIO_IDX_NUM(i) - 1), 0),
> +reg + 4 * j);
> + }
>
> - writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 0),
> -reg + 4 * i);
> }
>
> -static void mask_module_irq(struct mtk_devapc_context *ctx, bool mask)
> +static void mask_module_irq(void __iomem *reg, int vio_idx_num, bool mask)
> {
> - void __iomem *reg;
> u32 val;
> int i;
>
> - reg = ctx->infra_base + ctx->data->vio_mask_offset;
> -
> if (mask)
> val = GENMASK(31, 0);
> else
> val = 0;
>
> - for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++)
> + for (i = 0; i < VIO_MOD_TO_REG_IND(vio_idx_num - 1); i++)
> writel(val, reg + 4 * i);
>
> val = readl(reg + 4 * i);
> if (mask)
> - val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1,
> + val |= GENMASK(VIO_MOD_TO_REG_OFF(vio_idx_num - 1),
> 0);
> else
> - val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1,
> + val &= ~GENMASK(VIO_MOD_TO_REG_OFF(vio_idx_num - 1),
> 0);
>
> writel(val, reg + 4 * i);
> @@ -108,6 +124,8 @@ static void mask_module_irq(struct mtk_devapc_context
> *ctx, bool mask)
> */
> static int devapc_sync_vio_dbg(struct mtk_devapc_context *ctx)
> {
> + int i;
> + void __iomem *reg_base;
Not needed.
> void __iomem *pd_vio_shift_sta_reg;
> void __iomem *pd_vio_shift_sel_reg;
> void __iomem *pd_vio_shift_con_reg;
> @@ -115,57 +133,87 @@ static int devapc_sync_vio_dbg(struct
> mtk_devapc_context *ctx)
> int ret;
> u32 val;
>
> -
Re: [PATCH v13 7/8] soc: mediatek: add mtk mutex support for MT8183
On 29/01/2021 10:22, Hsin-Yi Wang wrote:
> From: Yongqiang Niu
>
> Add mtk mutex support for MT8183 SoC.
>
> Signed-off-by: Yongqiang Niu
> Signed-off-by: Hsin-Yi Wang
> Reviewed-by: CK Hu
> ---
> drivers/soc/mediatek/mtk-mutex.c | 50
> 1 file changed, 50 insertions(+)
>
Applied to v5.12-next/soc
Thanks
> diff --git a/drivers/soc/mediatek/mtk-mutex.c
> b/drivers/soc/mediatek/mtk-mutex.c
> index f531b119da7a9..718a41beb6afb 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -14,6 +14,8 @@
>
> #define MT2701_MUTEX0_MOD0 0x2c
> #define MT2701_MUTEX0_SOF0 0x30
> +#define MT8183_MUTEX0_MOD0 0x30
> +#define MT8183_MUTEX0_SOF0 0x2c
>
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n)(0x24 + 0x20 * (n))
> @@ -37,6 +39,18 @@
> #define MT8167_MUTEX_MOD_DISP_DITHER 15
> #define MT8167_MUTEX_MOD_DISP_UFOE 16
>
> +#define MT8183_MUTEX_MOD_DISP_RDMA0 0
> +#define MT8183_MUTEX_MOD_DISP_RDMA1 1
> +#define MT8183_MUTEX_MOD_DISP_OVL0 9
> +#define MT8183_MUTEX_MOD_DISP_OVL0_2L10
> +#define MT8183_MUTEX_MOD_DISP_OVL1_2L11
> +#define MT8183_MUTEX_MOD_DISP_WDMA0 12
> +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
> +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
> +#define MT8183_MUTEX_MOD_DISP_AAL0 15
> +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
> +#define MT8183_MUTEX_MOD_DISP_DITHER017
> +
> #define MT8173_MUTEX_MOD_DISP_OVL0 11
> #define MT8173_MUTEX_MOD_DISP_OVL1 12
> #define MT8173_MUTEX_MOD_DISP_RDMA0 13
> @@ -87,6 +101,11 @@
> #define MT2712_MUTEX_SOF_DSI36
> #define MT8167_MUTEX_SOF_DPI02
> #define MT8167_MUTEX_SOF_DPI13
> +#define MT8183_MUTEX_SOF_DSI01
> +#define MT8183_MUTEX_SOF_DPI02
> +
> +#define MT8183_MUTEX_EOF_DSI0(MT8183_MUTEX_SOF_DSI0
> << 6)
> +#define MT8183_MUTEX_EOF_DPI0(MT8183_MUTEX_SOF_DPI0
> << 6)
>
> struct mtk_mutex {
> int id;
> @@ -181,6 +200,20 @@ static const unsigned int
> mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> };
>
> +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
> + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
> + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> +};
> +
> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> @@ -198,6 +231,13 @@ static const unsigned int
> mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
> };
>
> +/* Add EOF setting so overlay hardware can receive frame done irq */
> +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -227,6 +267,14 @@ static const struct mtk_mutex_data
> mt8173_mutex_driver_data = {
> .mutex_sof_reg = MT2701_MUTEX0_SOF0,
> };
>
> +static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> + .mutex_mod = mt8183_mutex_mod,
> + .mutex_sof = mt8183_mutex_sof,
> + .mutex_mod_reg = MT8183_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> + .no_clk = true,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[]
> = {
> .data = _mutex_driver_data},
> { .compatible = "mediatek,mt8173-disp-mutex",
> .data = _mutex_driver_data},
> + { .compatible = "mediatek,mt8183-disp-mutex",
> + .data = _mutex_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of,
Re: [PATCH v6 10/22] clk: mediatek: Add MT8192 basic clocks support
On 22/12/2020 14:09, Weiyi Lu wrote:
> Add MT8192 basic clock providers, include topckgen, apmixedsys,
> infracfg and pericfg.
>
> Signed-off-by: Weiyi Lu
> ---
> drivers/clk/mediatek/Kconfig |8 +
> drivers/clk/mediatek/Makefile |1 +
> drivers/clk/mediatek/clk-mt8192.c | 1326
> +
> drivers/clk/mediatek/clk-mux.h| 15 +
> 4 files changed, 1350 insertions(+)
> create mode 100644 drivers/clk/mediatek/clk-mt8192.c
>
[...]
> +static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> + int r;
> +
> + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
> + if (!clk_data)
> + return -ENOMEM;
> +
> + mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
> + r = mtk_clk_register_gates(node, apmixed_clks,
> ARRAY_SIZE(apmixed_clks), clk_data);
> + if (r)
> + return r;
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> +static const struct of_device_id of_match_clk_mt8192[] = {
> + {
> + .compatible = "mediatek,mt8192-apmixedsys",
> + .data = clk_mt8192_apmixed_probe,
> + }, {
> + .compatible = "mediatek,mt8192-topckgen",
> + .data = clk_mt8192_top_probe,
> + }, {
> + .compatible = "mediatek,mt8192-infracfg",
> + .data = clk_mt8192_infra_probe,
> + }, {
> + .compatible = "mediatek,mt8192-pericfg",
> + .data = clk_mt8192_peri_probe,
> + }, {
> + /* sentinel */
> + }
> +};
> +
> +static int clk_mt8192_probe(struct platform_device *pdev)
> +{
> + int (*clk_probe)(struct platform_device *pdev);
> + int r;
> +
> + clk_probe = of_device_get_match_data(>dev);
> + if (!clk_probe)
> + return -EINVAL;
> +
> + r = clk_probe(pdev);
> + if (r)
> + dev_err(>dev, "could not register clock provider: %s:
> %d\n", pdev->name, r);
> +
> + return r;
> +}
> +
> +static struct platform_driver clk_mt8192_drv = {
> + .probe = clk_mt8192_probe,
> + .driver = {
> + .name = "clk-mt8192",
> + .of_match_table = of_match_clk_mt8192,
> + },
> +};
> +
> +static int __init clk_mt8192_init(void)
> +{
> + return platform_driver_register(_mt8192_drv);
> +}
> +
> +arch_initcall(clk_mt8192_init);
Do we really need all these clocks that early?
Why don't we use CLK_OF_DECLARE_DRIVER() then and why do we initialize some
clocks CLK_OF_DECLARE_DRIVER and other with arch_initcall?
I know that this is in other drivers for MediaTek SoCs, but that does not mean
it's the right approach.
> diff --git a/drivers/clk/mediatek/clk-mux.h b/drivers/clk/mediatek/clk-mux.h
> index f5625f4..afbc7df 100644
> --- a/drivers/clk/mediatek/clk-mux.h
> +++ b/drivers/clk/mediatek/clk-mux.h
> @@ -77,6 +77,21 @@ struct mtk_mux {
> _width, _gate, _upd_ofs, _upd, \
> CLK_SET_RATE_PARENT)
>
> +#define MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs,
> \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + _upd_ofs, _upd, _flags) \
> + GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + 0, _upd_ofs, _upd, _flags, \
> + mtk_mux_clr_set_upd_ops)
> +
> +#define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs,
> \
> + _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
> + _upd_ofs, _upd) \
> + MUX_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
> + _mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
> + _width, _upd_ofs, _upd, CLK_SET_RATE_PARENT)
> +
Why can't we do something like:
#define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
_upd_ofs, _upd) \
GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
0, _upd_ofs, _upd, CLK_SET_RATE_PARENT,
\
mtk_mux_clr_set_upd_ops)
> struct clk *mtk_clk_register_mux(const struct mtk_mux *mux,
>struct regmap *regmap,
>spinlock_t *lock);
>
Re: [PATCH v6 01/22] dt-bindings: ARM: Mediatek: Add new document bindings of imp i2c wrapper controller
On 22/12/2020 14:09, Weiyi Lu wrote:
> This patch adds the new binding documentation of imp i2c wrapper controller
> for Mediatek MT8192.
The wrapper controller has only clock parts, or are the clock register mapped
into the i2c wrapper block. In that case we might want to probe the clock driver
through the i2c wrapper driver.
Regards,
Matthias
>
> Signed-off-by: Weiyi Lu
> ---
> .../arm/mediatek/mediatek,imp_iic_wrap.yaml| 78
> ++
> 1 file changed, 78 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml
> b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml
> new file mode 100644
> index 000..5d0cf37
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/arm/mediatek/mediatek,imp_iic_wrap.yaml
> @@ -0,0 +1,78 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,imp_iic_wrap.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek IMP I2C Wrapper Controller
> +
> +maintainers:
> + - Weiyi Lu
> +
> +description:
> + The Mediatek imp i2c wrapper controller provides functional configurations
> and clocks to the system.
> +
> +properties:
> + compatible:
> +items:
> + - enum:
> + - mediatek,mt8192-imp_iic_wrap_c
> + - mediatek,mt8192-imp_iic_wrap_e
> + - mediatek,mt8192-imp_iic_wrap_s
> + - mediatek,mt8192-imp_iic_wrap_ws
> + - mediatek,mt8192-imp_iic_wrap_w
> + - mediatek,mt8192-imp_iic_wrap_n
> + - const: syscon
> +
> + reg:
> +maxItems: 1
> +
> + '#clock-cells':
> +const: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +examples:
> + - |
> +imp_iic_wrap_c: syscon@11007000 {
> +compatible = "mediatek,mt8192-imp_iic_wrap_c", "syscon";
> +reg = <0 0x11007000 0 0x1000>;
> +#clock-cells = <1>;
> +};
> +
> + - |
> +imp_iic_wrap_e: syscon@11cb1000 {
> +compatible = "mediatek,mt8192-imp_iic_wrap_e", "syscon";
> +reg = <0 0x11cb1000 0 0x1000>;
> +#clock-cells = <1>;
> +};
> +
> + - |
> +imp_iic_wrap_s: syscon@11d03000 {
> +compatible = "mediatek,mt8192-imp_iic_wrap_s", "syscon";
> +reg = <0 0x11d03000 0 0x1000>;
> +#clock-cells = <1>;
> +};
> +
> + - |
> +imp_iic_wrap_ws: syscon@11d23000 {
> +compatible = "mediatek,mt8192-imp_iic_wrap_ws", "syscon";
> +reg = <0 0x11d23000 0 0x1000>;
> +#clock-cells = <1>;
> +};
> +
> + - |
> +imp_iic_wrap_w: syscon@11e01000 {
> +compatible = "mediatek,mt8192-imp_iic_wrap_w", "syscon";
> +reg = <0 0x11e01000 0 0x1000>;
> +#clock-cells = <1>;
> +};
> +
> + - |
> +imp_iic_wrap_n: syscon@11f02000 {
> +compatible = "mediatek,mt8192-imp_iic_wrap_n", "syscon";
> +reg = <0 0x11f02000 0 0x1000>;
> +#clock-cells = <1>;
> +};
>
Re: [PATCH v13 7/8] soc: mediatek: add mtk mutex support for MT8183
On 09/02/2021 15:48, Enric Balletbo Serra wrote:
> Hi Hsin-Yi,
>
> Thank you for your patch.
>
> Missatge de Hsin-Yi Wang del dia dv., 29 de gen.
> 2021 a les 10:23:
>>
>> From: Yongqiang Niu
>>
>> Add mtk mutex support for MT8183 SoC.
>>
>> Signed-off-by: Yongqiang Niu
>> Signed-off-by: Hsin-Yi Wang
>> Reviewed-by: CK Hu
>
> Reviewed-by: Enric Balletbo i Serra
>
> FWIW this patch is required to have the display working on the
> Chromebook IdeaPad Duet, so
>
> Tested-by: Enric Balletbo i Serra
>
> Matthias, If I am not wrong, this patch is the only one that is not
> applied for this series. I know that is too late for 5.12, but If
> you're fine with it, could you pick this patch directly or do you
> prefer a resend of this patch alone once you will start to accept
> patches for the next release?
This patch is based on top of a patch that's in CK's branch.
Let's wait for v5.12-rc1 then I'll take it. If I forget just ping me here/IRC
Regards,
Matthias
>
> Thanks,
> Enric
>
>> ---
>> drivers/soc/mediatek/mtk-mutex.c | 50
>> 1 file changed, 50 insertions(+)
>>
>> diff --git a/drivers/soc/mediatek/mtk-mutex.c
>> b/drivers/soc/mediatek/mtk-mutex.c
>> index f531b119da7a9..718a41beb6afb 100644
>> --- a/drivers/soc/mediatek/mtk-mutex.c
>> +++ b/drivers/soc/mediatek/mtk-mutex.c
>> @@ -14,6 +14,8 @@
>>
>> #define MT2701_MUTEX0_MOD0 0x2c
>> #define MT2701_MUTEX0_SOF0 0x30
>> +#define MT8183_MUTEX0_MOD0 0x30
>> +#define MT8183_MUTEX0_SOF0 0x2c
>>
>> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
>> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
>> @@ -37,6 +39,18 @@
>> #define MT8167_MUTEX_MOD_DISP_DITHER 15
>> #define MT8167_MUTEX_MOD_DISP_UFOE 16
>>
>> +#define MT8183_MUTEX_MOD_DISP_RDMA00
>> +#define MT8183_MUTEX_MOD_DISP_RDMA11
>> +#define MT8183_MUTEX_MOD_DISP_OVL0 9
>> +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
>> +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
>> +#define MT8183_MUTEX_MOD_DISP_WDMA012
>> +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
>> +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
>> +#define MT8183_MUTEX_MOD_DISP_AAL0 15
>> +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
>> +#define MT8183_MUTEX_MOD_DISP_DITHER0 17
>> +
>> #define MT8173_MUTEX_MOD_DISP_OVL0 11
>> #define MT8173_MUTEX_MOD_DISP_OVL1 12
>> #define MT8173_MUTEX_MOD_DISP_RDMA013
>> @@ -87,6 +101,11 @@
>> #define MT2712_MUTEX_SOF_DSI3 6
>> #define MT8167_MUTEX_SOF_DPI0 2
>> #define MT8167_MUTEX_SOF_DPI1 3
>> +#define MT8183_MUTEX_SOF_DSI0 1
>> +#define MT8183_MUTEX_SOF_DPI0 2
>> +
>> +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
>> +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
>>
>> struct mtk_mutex {
>> int id;
>> @@ -181,6 +200,20 @@ static const unsigned int
>> mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
>> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
>> };
>>
>> +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
>> + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
>> + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
>> + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
>> + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
>> + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
>> + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
>> + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
>> + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
>> + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
>> + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
>> + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
>> +};
>> +
>> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
>> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
>> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
>> @@ -198,6 +231,13 @@ static const unsigned int
>> mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
>> [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
>> };
>>
>> +/* Add EOF setting so overlay hardware can receive frame done irq */
>> +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
>> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
>> + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
>> + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
>> +};
>> +
>> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
>> .mutex_mod = mt2701_mutex_mod,
>> .mutex_sof = mt2712_mutex_sof,
>> @@ -227,6 +267,14 @@ static const struct
Re: [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder
On 09/02/2021 16:38, Enric Balletbo Serra wrote: > Hi Yongqiang Niu, > > Thank you for your patch. > > Missatge de Yongqiang Niu del dia dt., 5 > de gen. 2021 a les 4:07: >> >> the mmsys will more and more complicated after support >> more and more SoCs, add an independent folder will be >> more clear >> >> Signed-off-by: Yongqiang Niu >> --- >> drivers/soc/mediatek/Makefile | 2 +- > > It will not apply cleanly anymore after the below commit that is > already queued. Maybe you could rebase the patches and resend them > again? > Please don't do that, as I pointed out in [1] I don't like the approach of a new folder. If you disagree please let me know why. Otherwise please send a new version with the changes suggested by me :) Regards, Matthias [1] https://lore.kernel.org/linux-mediatek/4cadc9f0-0761-7609-abac-d2211b097...@gmail.com/ > commit e1e4f7fea37572f0ccf3887430e52c491e9accb6 > Author: CK Hu > Date: Tue Jul 21 15:46:06 2020 +0800 > > soc / drm: mediatek: Move mtk mutex driver to soc folder > > mtk mutex is used by DRM and MDP driver, and its function is SoC-specific, > so move it to soc folder. > > With that fixed, > > Reviewed-by: Enric Balletbo i Serra > > Thanks, > Enric > >> drivers/soc/mediatek/mmsys/Makefile| 2 + >> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 >> + >> drivers/soc/mediatek/mtk-mmsys.c | 373 >> - >> 4 files changed, 376 insertions(+), 374 deletions(-) >> create mode 100644 drivers/soc/mediatek/mmsys/Makefile >> create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c >> delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c >> >> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile >> index b6908db..eca9774 100644 >> --- a/drivers/soc/mediatek/Makefile >> +++ b/drivers/soc/mediatek/Makefile >> @@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o >> obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o >> obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o >> obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o >> -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o >> +obj-$(CONFIG_MTK_MMSYS) += mmsys/ >> diff --git a/drivers/soc/mediatek/mmsys/Makefile >> b/drivers/soc/mediatek/mmsys/Makefile >> new file mode 100644 >> index 000..f44eadc >> --- /dev/null >> +++ b/drivers/soc/mediatek/mmsys/Makefile >> @@ -0,0 +1,2 @@ >> +# SPDX-License-Identifier: GPL-2.0-only >> +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o >> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c >> b/drivers/soc/mediatek/mmsys/mtk-mmsys.c >> new file mode 100644 >> index 000..18f9397 >> --- /dev/null >> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c >> @@ -0,0 +1,373 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * Copyright (c) 2014 MediaTek Inc. >> + * Author: James Liao >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 >> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 >> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN0x048 >> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c >> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 >> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 >> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 >> +#define DISP_REG_CONFIG_DSIE_SEL_IN0x0a4 >> +#define DISP_REG_CONFIG_DSIO_SEL_IN0x0a8 >> +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac >> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8 >> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 >> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 >> +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 >> + >> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 >> +#define DISP_REG_CONFIG_OUT_SEL0x04c >> +#define DISP_REG_CONFIG_DSI_SEL0x050 >> +#define DISP_REG_CONFIG_DPI_SEL0x064 >> + >> +#define OVL0_MOUT_EN_COLOR00x1 >> +#define OD_MOUT_EN_RDMA0 0x1 >> +#define OD1_MOUT_EN_RDMA1 BIT(16) >> +#define UFOE_MOUT_EN_DSI0 0x1 >> +#define COLOR0_SEL_IN_OVL0 0x1 >> +#define OVL1_MOUT_EN_COLOR10x1 >> +#define GAMMA_MOUT_EN_RDMA10x1 >> +#define RDMA0_SOUT_DPI00x2 >> +#define RDMA0_SOUT_DPI10x3 >> +#define RDMA0_SOUT_DSI10x1 >> +#define RDMA0_SOUT_DSI20x4 >> +#define RDMA0_SOUT_DSI30x5 >> +#define RDMA1_SOUT_DPI00x2 >> +#define RDMA1_SOUT_DPI10x3 >> +#define RDMA1_SOUT_DSI10x1 >> +#define RDMA1_SOUT_DSI20x4 >>
Re: [PATCH RESEND v5 8/8] arm64: dts: mt6359: add PMIC MT6359 related nodes
On 02/02/2021 04:51, Tzung-Bi Shih wrote:
> On Sun, Jan 31, 2021 at 7:06 PM Matthias Brugger
> wrote:
>> On 29/01/2021 10:49, Hsin-Hsiung Wang wrote:
>>> + mt6359codec: mt6359codec {
>>> + };
>>
>> I understand that the dmic-mode and mic-type-X depends on the actual board on
>> which it is used. In that case I think we should add mt6359codec node in the
>> dts
>> instead of dtsi file. I'd advise to set these properties as well as
>> otherwise we
>> get a (slightly misleading) warning in the driver.
>
> I feel it is better to include the node in dtsi to represent the whole
> MT6359 PMIC.
>
> We could either:
> - Set default values of these properties in the dtsi to avoid the
> warning message.
> - Or
> https://patchwork.kernel.org/project/alsa-devel/patch/20210202033557.1621029-1-tzun...@google.com/
>
As this got accpeted upstream, you don't need to do anything about it.
Thanks for the pointer.
Matthias
Re: [PATCH] arm64: dts: mediatek: mt8183: evb: Add domain supply for mfg
On 01/02/2021 10:30, Hsin-Yi Wang wrote:
> Add domain supply node for mt8183-evb
>
> Signed-off-by: Hsin-Yi Wang
Queued in v5.12-tmp/dts64
Thanks
> ---
> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> index 3249c959f76fc..edff1e03e6fee 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> @@ -352,6 +352,10 @@ pins_pwm {
> };
> };
>
> + {
> + domain-supply = <_vgpu_reg>;
> +};
> +
> {
> pinctrl-names = "default";
> pinctrl-0 = <_pins_0>;
>
Re: [PATCH 0/2] Add MediaTek MT8192 clock provider device nodes
Hi Weiyi, On 01/02/2021 10:31, Weiyi Lu wrote: > On Sun, 2021-01-31 at 14:27 +0100, Matthias Brugger wrote: >> >> On 22/12/2020 14:40, Weiyi Lu wrote: >>> This series is based on v5.10-rc1, MT8192 dts v6[1] and >>> MT8192 clock v6 series[2]. >>> >>> [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=373899 >>> [2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=405295 >>> >> >> [1] is already mainline. You could add this patch as a new one to [2]. But >> please try to improve the series, before sending just a new version with this >> patch added. >> >> Regards, >> Matthias >> > Hi Matthias, > > Actually I'm a little confused now. Stephen suggested me to send clock > dts separately because dts may not go through his tree. > So I separated it from the MT8192 clock series since clock v6. > What do you suggest me to do next time? > Yes, now that you mention that, I remember... OK, then I'd propose to resend the DTS patches once the clock patches are accepted. Regards, Matthias >>> Weiyi Lu (2): >>> arm64: dts: mediatek: Add mt8192 clock controllers >>> arm64: dts: mediatek: Correct UART0 bus clock of MT8192 >>> >>> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 165 ++- >>> 1 file changed, 164 insertions(+), 1 deletion(-) >>> >
Re: [PATCH 2/2] soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD
On 01/02/2021 06:45, Bilal Wasim wrote:
> The mfg_async power domain in mt8173 is used to power up imgtec
> gpu. This domain requires the da9211 regulator to be enabled before
> the power domain can be enabled successfully.
>
> Signed-off-by: Bilal Wasim
> ---
> drivers/soc/mediatek/mt8173-pm-domains.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h
> b/drivers/soc/mediatek/mt8173-pm-domains.h
> index 3e8ee5dabb43..065b8195e7d6 100644
> --- a/drivers/soc/mediatek/mt8173-pm-domains.h
> +++ b/drivers/soc/mediatek/mt8173-pm-domains.h
> @@ -63,6 +63,7 @@ static const struct scpsys_domain_data
> scpsys_domain_data_mt8173[] = {
> .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = 0,
> + .caps = MTK_SCPD_DOMAIN_SUPPLY,
> },
> [MT8173_POWER_DOMAIN_MFG_2D] = {
> .sta_mask = PWR_STATUS_MFG_2D,
>
We are missing a third patch for the DTS to actually add the regulator. Please
provide them for both, mt8173-evb.dts and mt8173-elm.dts
Thanks a lot and I'm very happy to see you starting to contribute!
Regards,
Matthias
Re: [PATCH v2 3/3] arm64: dts: mediatek: mt8183: Add domain supply for mfg
On 31/01/2021 13:05, Matthias Brugger wrote:
>
>
> On 29/01/2021 11:12, Hsin-Yi Wang wrote:
>> Add domain supply node.
>>
>> Signed-off-by: Hsin-Yi Wang
>> ---
>
> Applied to v5.11-next/dts64
>
I just realiezed that we will also need a patch for the MT8183 EVB. I'll leave
this series in, but please provide a follow-up patch for the dts.
Thanks.
Matthias
> Thanks
>
>> arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 4
>> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +-
>> 2 files changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
>> b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
>> index bf2ad1294dd30..ebd53755d538a 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
>> @@ -709,6 +709,10 @@ cros_ec {
>> };
>> };
>>
>> + {
>> +domain-supply = <_vgpu_reg>;
>> +};
>> +
>> _data {
>> status = "okay";
>> };
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> index 5b782a4769e7e..bda283fa92452 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> @@ -360,7 +360,7 @@ power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC {
>> #size-cells = <0>;
>> #power-domain-cells = <1>;
>>
>> -power-domain@MT8183_POWER_DOMAIN_MFG {
>> +mfg:
>> power-domain@MT8183_POWER_DOMAIN_MFG {
>> reg = ;
>> #address-cells = <1>;
>> #size-cells = <0>;
>>
Re: [PATCH 1/2] soc: mediatek: pm-domains: Use correct mask for bus_prot_clr
On 01/02/2021 06:45, Bilal Wasim wrote:
> When "bus_prot_reg_update" is false, the driver should use
> INFRA_TOPAXI_PROTECTEN for both setting and clearing the bus
> protection. However, the driver does not use this mask for
> clearing bus protection which causes failure when booting
> the imgtec gpu.
>
> Corrected and tested with mt8173 chromebook.
>
> Signed-off-by: Bilal Wasim
> ---
> drivers/soc/mediatek/mtk-pm-domains.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.h
> b/drivers/soc/mediatek/mtk-pm-domains.h
> index 141dc76054e6..7454c0b4f768 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.h
> +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> @@ -60,7 +60,7 @@
> #define BUS_PROT_UPDATE_TOPAXI(_mask)\
> BUS_PROT_UPDATE(_mask, \
> INFRA_TOPAXI_PROTECTEN, \
> - INFRA_TOPAXI_PROTECTEN_CLR, \
> + INFRA_TOPAXI_PROTECTEN, \
BUS_PROT_UPDATE sets bus_prot_reg_update to true, which contradicts what you say
in the commit message.
Please clarify.
Regards,
Matthias
> INFRA_TOPAXI_PROTECTSTA1)
>
> struct scpsys_bus_prot_data {
>
Re: [PATCH v1 2/2] arm64: configs: Support DEVAPC on MediaTek platforms
On 31/01/2021 23:23, Arnd Bergmann wrote: > On Sun, Jan 31, 2021 at 3:07 PM Matthias Brugger > wrote: >> On 23/12/2020 09:44, Neal Liu wrote: >>> Support DEVAPC on MediaTek platforms by enabling CONFIG_MTK_DEVAPC. >>> >>> Signed-off-by: Neal Liu >>> --- >>> arch/arm64/configs/defconfig |1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig >>> index 17a2df6..a373776 100644 >>> --- a/arch/arm64/configs/defconfig >>> +++ b/arch/arm64/configs/defconfig >>> @@ -257,6 +257,7 @@ CONFIG_MTD_NAND_MARVELL=y >>> CONFIG_MTD_NAND_FSL_IFC=y >>> CONFIG_MTD_NAND_QCOM=y >>> CONFIG_MTD_SPI_NOR=y >>> +CONFIG_MTK_DEVAPC=m >>> CONFIG_SPI_CADENCE_QUADSPI=y >>> CONFIG_BLK_DEV_LOOP=y >>> CONFIG_BLK_DEV_NBD=m >>> >> >> From my understanding, defconfig is for a minimal config that allows to boot >> a >> machine. As MTK_DEVAPC is a rather exotic driver to detect bus access >> violations, I think it's not a good candidate for inclusion in defconfig. >> >> In any case, I added the SoC maintainer, so that they can correct me, if I'm >> wrong :) > > I generally don't mind adding platform specific drivers as loadable modules > even if they are somewhat obscure. For built-in drivers, this is > different though, > as those have a noticeable impact on other platforms. > > I haven't kept track of what this particular driver does, but from the Kconfig > description, I'd say it should get enabled in defconfig. > Thanks for the feedback Arnd. Applied now to v5.11-next/defconfig
Re: [PATCH] arm64: dts: mt8183: Fix GCE include path
On 31/01/2021 17:17, Chun-Kuang Hu wrote:
> Hi, Matthias:
>
> 於 2021年1月31日 週日 下午6:17寫道：
>>
>> From: Matthias Brugger
>>
>> The header file of GCE should be for MT8183 SoC instead of MT8173.
>>
>
> Reviewed-by: Chun-Kuang Hu
>
Applied to v5.11-next/dts64
Thanks
>> Fixes: 91f9c963ce79 ("arm64: dts: mt8183: Add display nodes for MT8183")
>> Reported-by: CK Hu
>> Signed-off-by: Matthias Brugger
>>
>> ---
>>
>> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> index 5b782a4769e7..80e466ce99f1 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
>> @@ -6,7 +6,7 @@
>> */
>>
>> #include
>> -#include
>> +#include
>> #include
>> #include
>> #include
>> --
>> 2.30.0
>>
>>
>> ___
>> Linux-mediatek mailing list
>> linux-media...@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
Re: [PATCH] arm64: dts: mediatek: Correct i2c clock of MT8192
On 21/12/2020 13:26, qii.w...@mediatek.com wrote:
> From: Qii Wang
>
> imp wrapper clock is the i2c source clock of MT8192
>
> Signed-off-by: Qii Wang
> ---
Thanks for your patch. The next time please provide information about any
out-of-tree series that are needed to apply cleanly.
Regards,
Matthias
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 43
>
> 1 file changed, 33 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index faea0d9..9c194a8 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -17,6 +17,19 @@
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + i2c0 =
> + i2c1 =
> + i2c2 =
> + i2c3 =
> + i2c4 =
> + i2c5 =
> + i2c6 =
> + i2c7 =
> + i2c8 =
> + i2c9 =
> + };
> +
> clk26m: oscillator0 {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> @@ -593,7 +606,8 @@
> reg = <0 0x11cb 0 0x1000>,
> <0 0x10217300 0 0x80>;
> interrupts = ;
> - clocks = <>, <>;
> + clocks = <_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>,
> + < CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -612,7 +626,8 @@
> reg = <0 0x11d0 0 0x1000>,
> <0 0x10217600 0 0x180>;
> interrupts = ;
> - clocks = <>, <>;
> + clocks = <_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
> + < CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -625,7 +640,8 @@
> reg = <0 0x11d01000 0 0x1000>,
> <0 0x10217780 0 0x180>;
> interrupts = ;
> - clocks = <>, <>;
> + clocks = <_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>,
> + < CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -638,7 +654,8 @@
> reg = <0 0x11d02000 0 0x1000>,
> <0 0x10217900 0 0x180>;
> interrupts = ;
> - clocks = <>, <>;
> + clocks = <_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>,
> + < CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -657,7 +674,8 @@
> reg = <0 0x11d2 0 0x1000>,
> <0 0x10217100 0 0x80>;
> interrupts = ;
> - clocks = <>, <>;
> + clocks = <_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>,
> + < CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -670,7 +688,8 @@
> reg = <0 0x11d21000 0 0x1000>,
> <0 0x10217180 0 0x180>;
> interrupts = ;
> - clocks = <>, <>;
> + clocks = <_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>,
> + < CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -683,7 +702,8 @@
> reg = <0 0x11d22000 0 0x1000>,
> <0 0x10217380 0 0x180>;
> interrupts = ;
> - clocks = <>, <>;
> + clocks = <_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>,
> + < CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -702,7 +722,8 @@
> reg = <0 0x11e0 0 0x1000>,
> <0 0x10217500 0 0x80>;
> interrupts = ;
> - clocks = <>, <>;
> + clocks = <_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>,
> + < CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -721,7 +742,8 @@
>
Re: [PATCH 1/2] arm64: dts: mt6779: Support pwrap on Mediatek MT6779 platform
On 04/01/2021 09:08, Argus Lin wrote:
> Support pwrap on Mediatek MT6779 platform by adding pwrap node in dts file.
>
> Signed-off-by: Argus Lin
> ---
Applied to v5.11-next/dts64
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309..2c2ca33 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -189,6 +189,15 @@
> #clock-cells = <1>;
> };
>
> + pwrap: pwrap@1000d000 {
> + compatible = "mediatek,mt6779-pwrap";
> + reg = <0 0x1000d000 0 0x1000>;
> + reg-names = "pwrap";
> + interrupts = ;
> + clocks = <>, <_ao CLK_INFRA_PMIC_AP>;
> + clock-names = "spi", "wrap";
> + };
> +
> uart0: serial@11002000 {
> compatible = "mediatek,mt6779-uart",
>"mediatek,mt6577-uart";
> --
> 1.8.1.1.dirty
>
Re: [PATCH 2/2] arm64: configs: Support pwrap on Mediatek MT6779 platform
On 04/01/2021 09:08, Argus Lin wrote: > Support pwrap on Mediatek MT6779 platform by enabling CONFIG_MTK_PMIC_WRAP. > > Signed-off-by: Argus Lin > --- Applied to v5.11-next/defconfig > arch/arm64/configs/defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index 8383016..a2c926f 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -479,6 +479,7 @@ CONFIG_SPI_S3C64XX=y > CONFIG_SPI_SH_MSIOF=m > CONFIG_SPI_SUN6I=y > CONFIG_SPI_SPIDEV=m > +CONFIG_MTK_PMIC_WRAP=m > CONFIG_SPMI=y > CONFIG_PINCTRL_SINGLE=y > CONFIG_PINCTRL_MAX77620=y > -- > 1.8.1.1.dirty >
Re: [PATCH v2] dts64: mt7622: fix slow sd card access
On 13/01/2021 19:09, Frank Wunderlich wrote:
> From: Frank Wunderlich
>
> Fix extreme slow speed (200MB takes ~20 min) on writing sdcard on
> bananapi-r64 by adding reset-control for mmc1 like it's done for mmc0/emmc.
>
> Cc: sta...@vger.kernel.org
> Fixes: 2c002a3049f7 ("arm64: dts: mt7622: add mmc related device nodes")
> Signed-off-by: Frank Wunderlich
Applied to v5.11-next/dts64
Thanks!
> ---
> changes since v1:
> - drop change to uhs-mode because mt7622 does not support it
> ---
> arch/arm64/boot/dts/mediatek/mt7622.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> index 5b9ec032ce8d..7c6d871538a6 100644
> --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
> @@ -698,6 +698,8 @@ mmc1: mmc@1124 {
> clocks = < CLK_PERI_MSDC30_1_PD>,
>< CLK_TOP_AXI_SEL>;
> clock-names = "source", "hclk";
> + resets = < MT7622_PERI_MSDC1_SW_RST>;
> + reset-names = "hrst";
> status = "disabled";
> };
>
>
Re: [PATCH] soc: mediatek: pm-domains: Don't print an error if child domain is deferred
On 13/01/2021 22:30, Enric Balletbo i Serra wrote:
> Child domains can be deferred by the core because one of its resources
> is not available yet, in such case, it will print an error, but
> later it will succeed to probe. Fix that using the dev_err_probe()
> function so it only prints an error on a real error.
>
> Signed-off-by: Enric Balletbo i Serra
Applied to v5.11-next/soc
Thanks
> ---
>
> drivers/soc/mediatek/mtk-pm-domains.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c
> b/drivers/soc/mediatek/mtk-pm-domains.c
> index ae255aa7b1a9..8055fb019ba6 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.c
> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> @@ -480,8 +480,8 @@ static int scpsys_add_subdomain(struct scpsys *scpsys,
> struct device_node *paren
>
> child_pd = scpsys_add_one_domain(scpsys, child);
> if (IS_ERR(child_pd)) {
> - ret = PTR_ERR(child_pd);
> - dev_err(scpsys->dev, "%pOF: failed to get child domain
> id\n", child);
> + dev_err_probe(scpsys->dev, PTR_ERR(child_pd),
> + "%pOF: failed to get child domain id\n",
> child);
> goto err_put_node;
> }
>
>
Re: [PATCH v4 1/3] arm64: dts: mt8183: config dsi node
On 13/01/2021 12:03, Hsin-Yi Wang wrote:
> Config dsi node for mt8183 kukui. Set panel and ports.
>
> Several kukui boards share the same panel property and only compatible
> is different. So compatible will be set in board dts for comparison
> convenience.
>
> Signed-off-by: Hsin-Yi Wang
> Reviewed-by: Nicolas Boichat
> ---
Whole series applied to v5.11-next/dts64
Thanks!
> change:
> v4: add backlight and enable mipi_tx0
> ---
> .../mediatek/mt8183-kukui-krane-sku176.dts| 5 +++
> .../arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 42 +++
> 2 files changed, 47 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
> b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
> index 47113e275cb52..721d16f9c3b4f 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-krane-sku176.dts
> @@ -16,3 +16,8 @@ / {
> model = "MediaTek krane sku176 board";
> compatible = "google,krane-sku176", "google,krane", "mediatek,mt8183";
> };
> +
> + {
> +status = "okay";
> +compatible = "boe,tv101wum-nl6";
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> index bf2ad1294dd30..da1e947587074 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
> @@ -249,6 +249,36 @@ {
> proc-supply = <_vproc11_reg>;
> };
>
> + {
> + status = "okay";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + panel: panel@0 {
> + /* compatible will be set in board dts */
> + reg = <0>;
> + enable-gpios = < 45 0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <_pins_default>;
> + avdd-supply = <_lcd>;
> + avee-supply = <_lcd>;
> + pp1800-supply = <_lcd>;
> + backlight = <_lcd0>;
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <_out>;
> + };
> + };
> + };
> +
> + ports {
> + port {
> + dsi_out: endpoint {
> + remote-endpoint = <_in>;
> + };
> + };
> + };
> +};
> +
> {
> pinctrl-names = "default";
> pinctrl-0 = <_pins>;
> @@ -290,6 +320,10 @@ {
> clock-frequency = <10>;
> };
>
> +_tx0 {
> + status = "okay";
> +};
> +
> {
> status = "okay";
> pinctrl-names = "default", "state_uhs";
> @@ -547,6 +581,14 @@ pins_clk {
> };
> };
>
> + panel_pins_default: panel_pins_default {
> + panel_reset {
> + pinmux = ;
> + output-low;
> + bias-pull-up;
> + };
> + };
> +
> pwm0_pin_default: pwm0_pin_default {
> pins1 {
> pinmux = ;
>
Re: [PATCH v2] soc: mediatek: cmdq: add address shift in jump
On 08/01/2021 02:48, Yongqiang Niu wrote:
> On Wed, 2020-12-23 at 16:34 +0800, Yongqiang Niu wrote:
>> Add address shift when compose jump instruction
>> to compatible with 35bit format.
>>
>> Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform")
>>
>> Signed-off-by: Yongqiang Niu
>> Reviewed-by: Nicolas Boichat
>> ---
>> drivers/mailbox/mtk-cmdq-mailbox.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c
>> b/drivers/mailbox/mtk-cmdq-mailbox.c
>> index 5665b6e..75378e3 100644
>> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
>> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
>> @@ -168,7 +168,8 @@ static void cmdq_task_insert_into_thread(struct
>> cmdq_task *task)
>> dma_sync_single_for_cpu(dev, prev_task->pa_base,
>> prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
>> prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
>> -(u64)CMDQ_JUMP_BY_PA << 32 | task->pa_base;
>> +(u64)CMDQ_JUMP_BY_PA << 32 |
>> +(task->pa_base >> task->cmdq->shift_pa);
>> dma_sync_single_for_device(dev, prev_task->pa_base,
>> prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
>>
>
> hi jassi
>
> please confirm is there any question about this patch.
> if not, please apply this into next version, tks
>
Please fix the subject line of your patch. It does not apply to
drivers/soc/mediatek and should be something like
mailbox: mediatek: cmdq: add address shift in jump
Thanks,
Matthias
Re: [PATCH v2, 1/3] dt-binding: gce: add gce header file for mt8192
On 24/12/2020 01:48, Yongqiang Niu wrote: > Add documentation for the mt8192 gce. > > Add gce header file defined the gce hardware event, > subsys number and constant for mt8192. > > Signed-off-by: Yongqiang Niu > --- > .../devicetree/bindings/mailbox/mtk-gce.txt| 7 +- > include/dt-bindings/gce/mt8192-gce.h | 419 > + > 2 files changed, 423 insertions(+), 3 deletions(-) > create mode 100644 include/dt-bindings/gce/mt8192-gce.h > > diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > index cf48cd8..f48ae45 100644 > --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt > @@ -9,8 +9,8 @@ CMDQ driver uses mailbox framework for communication. Please > refer to > mailbox.txt for generic information about mailbox device-tree bindings. > > Required properties: > -- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or > - "mediatek,mt6779-gce". > +- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce", > + "mediatek,mt8192-gce" or "mediatek,mt6779-gce". > - reg: Address range of the GCE unit > - interrupts: The interrupt signal from the GCE block > - clock: Clocks according to the common clock binding > @@ -36,7 +36,8 @@ Optional properties for a client device: >size: the total size of register address that GCE can access. > > Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h', > -'dt-binding/gce/mt8183-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. Such as > +'dt-binding/gce/mt8183-gce.h', 'dt-binding/gce/mt8192-gce.h' or > +'dt-bindings/gce/mt6779-gce.h'. Such as > sub-system ids, thread priority, event ids. > > Example: > diff --git a/include/dt-bindings/gce/mt8192-gce.h > b/include/dt-bindings/gce/mt8192-gce.h > new file mode 100644 > index 000..0627544 > --- /dev/null > +++ b/include/dt-bindings/gce/mt8192-gce.h > @@ -0,0 +1,419 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2020 MediaTek Inc. > + * Author: Yongqiang Niu > + */ > + > +#ifndef _DT_BINDINGS_GCE_MT8192_H > +#define _DT_BINDINGS_GCE_MT8192_H > + > +/* assign timeout 0 also means default */ > +#define CMDQ_NO_TIMEOUT 0x > +#define CMDQ_TIMEOUT_DEFAULT 1000 > + > +/* GCE thread priority */ > +#define CMDQ_THR_PRIO_LOWEST 0 > +#define CMDQ_THR_PRIO_1 1 > +#define CMDQ_THR_PRIO_2 2 > +#define CMDQ_THR_PRIO_3 3 > +#define CMDQ_THR_PRIO_4 4 > +#define CMDQ_THR_PRIO_5 5 > +#define CMDQ_THR_PRIO_6 6 > +#define CMDQ_THR_PRIO_HIGHEST7 > + > +/* CPR count in 32bit register */ > +#define GCE_CPR_COUNT1312 > + > +/* GCE subsys table */ > +#define SUBSYS_1300 0 > +#define SUBSYS_1400 1 > +#define SUBSYS_1401 2 > +#define SUBSYS_1402 3 > +#define SUBSYS_1502 4 > +#define SUBSYS_1880 5 > +#define SUBSYS_1881 6 > +#define SUBSYS_1882 7 > +#define SUBSYS_1883 8 > +#define SUBSYS_1884 9 > +#define SUBSYS_1000 10 > +#define SUBSYS_1001 11 > +#define SUBSYS_1002 12 > +#define SUBSYS_1003 13 > +#define SUBSYS_1004 14 > +#define SUBSYS_1005 15 > +#define SUBSYS_1020 16 > +#define SUBSYS_1028 17 > +#define SUBSYS_1700 18 > +#define SUBSYS_1701 19 > +#define SUBSYS_1702 20 > +#define SUBSYS_1703 21 > +#define SUBSYS_1800 22 > +#define SUBSYS_1801 23 > +#define SUBSYS_1802 24 > +#define SUBSYS_1804 25 > +#define SUBSYS_1805 26 > +#define SUBSYS_1808 27 > +#define SUBSYS_180a 28 > +#define SUBSYS_180b 29 > +#define SUBSYS_NO_SUPPORT99 How will we you SUBSYS_NO_SUPPORT? > + > +/* GCE General Purpose Register (GPR) support > + * Leave note for scenario usage here > + */ > +/* GCE: write mask */ > +#define GCE_GPR_R00 0x00 What are these defines for? Regards, Matthias > +#define GCE_GPR_R01 0x01 > +/* MDP: P1: JPEG dest */ > +#define GCE_GPR_R02 0x02 > +#define GCE_GPR_R03 0x03 > +/* MDP: PQ color */ > +#define GCE_GPR_R04 0x04 > +/* MDP: 2D sharpness */ > +#define GCE_GPR_R05 0x05 > +/* DISP: poll esd */ > +#define GCE_GPR_R06 0x06 > +#define GCE_GPR_R07 0x07 > +/* MDP: P4: 2D sharpness dst */ > +#define GCE_GPR_R08 0x08 > +#define GCE_GPR_R09 0x09 > +/* VCU: poll with timeout for GPR timer */ > +#define GCE_GPR_R10 0x0A > +#define GCE_GPR_R11 0x0B > +/*
Re: [PATCH 2/3] usb: xhci-mtk: fix UAS issue by XHCI_BROKEN_STREAMS quirk
On 24/12/2020 08:18, Chunfeng Yun wrote: > On Wed, 2020-12-16 at 19:43 -0800, Rosen Penev wrote: >> On Wed, Dec 16, 2020 at 6:29 PM Chunfeng Yun >> wrote: >>> >>> On Wed, 2020-12-16 at 20:28 +0800, Nicolas Boichat wrote: On Wed, Dec 16, 2020 at 7:53 PM Chunfeng Yun wrote: [...] > mtk->lpm_support = of_property_read_bool(node, > "usb3-lpm-capable"); > + mtk->broken_streams = > + of_property_read_bool(node, > "mediatek,broken_streams_quirk"); Would it be better to add a data field to struct of_device_id mtk_xhci_of_match, and enable this quirk on mediatek,mt8173-xhci only? >>> This is the common issue for all SoCs (before 2016.06) with 0.96 xHCI >>> when the controller don't support bulk stream. If enable this quirk only >>> for mt8173, then for other SoCs, the compatible need include >>> "mediatek,mt8173-xhci" in dts, this may be not flexible for some cases, >>> e.g. a new SoC has the broken stream as mt8173, but also has another >>> different quirk, the way you suggested will not handle it. >>> And I plan to remove "mediatek,mt8173-xhci" in mtk_xhci_of_match after >>> converting the binding to YMAL. >> I'm guessing this also applies to mt7621? > Yes, mt7621 doesn't support bulk stream > Then please provide patches to the DTSI for all SoCs that have this problem. Either as a follow-up or as part of this series, if you need to resubmit. Regards, Matthias
Re: [PATCH v1 1/2] arm64: dts: mt6779: Support devapc
On 23/12/2020 10:52, Neal Liu wrote:
> +add comments & reviewed-by Hanks
>
> On Wed, 2020-12-23 at 16:44 +0800, Neal Liu wrote:
>
> Support DEVAPC on MT6779 platforms by adding device node.
>
> Reviewed-by: Hanks Chen
Apllied with the description and Reviewed-by to v5.11-next/dts64
Thanks a lot!
>> Signed-off-by: Neal Liu
>> ---
>> arch/arm64/boot/dts/mediatek/mt6779.dtsi |8
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
>> b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
>> index 370f309..52ecfc7 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
>> @@ -189,6 +189,14 @@
>> #clock-cells = <1>;
>> };
>>
>> +devapc: devapc@10207000 {
>> +compatible = "mediatek,mt6779-devapc";
>> +reg = <0 0x10207000 0 0x1000>;
>> +interrupts = ;
>> +clocks = <_ao CLK_INFRA_DEVICE_APC>;
>> +clock-names = "devapc-infra-clock";
>> +};
>> +
>> uart0: serial@11002000 {
>> compatible = "mediatek,mt6779-uart",
>> "mediatek,mt6577-uart";
>
Re: [PATCH v1 2/2] arm64: configs: Support DEVAPC on MediaTek platforms
On 23/12/2020 09:44, Neal Liu wrote: > Support DEVAPC on MediaTek platforms by enabling CONFIG_MTK_DEVAPC. > > Signed-off-by: Neal Liu > --- > arch/arm64/configs/defconfig |1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index 17a2df6..a373776 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -257,6 +257,7 @@ CONFIG_MTD_NAND_MARVELL=y > CONFIG_MTD_NAND_FSL_IFC=y > CONFIG_MTD_NAND_QCOM=y > CONFIG_MTD_SPI_NOR=y > +CONFIG_MTK_DEVAPC=m > CONFIG_SPI_CADENCE_QUADSPI=y > CONFIG_BLK_DEV_LOOP=y > CONFIG_BLK_DEV_NBD=m > >From my understanding, defconfig is for a minimal config that allows to boot a machine. As MTK_DEVAPC is a rather exotic driver to detect bus access violations, I think it's not a good candidate for inclusion in defconfig. In any case, I added the SoC maintainer, so that they can correct me, if I'm wrong :) Regards, Matthias
Re: [PATCH v3 1/2] dt-bindings: nvmem: mediatek: add support for MediaTek mt8192 SoC
On 22/01/2021 07:28, mtk23264 wrote: > On Sun, 2021-01-03 at 09:25 -0700, Rob Herring wrote: >> On Mon, Dec 21, 2020 at 02:10:19PM +0800, yz...@mediatek.com wrote: >>> From: Ryan Wu >>> >>> This updates dt-binding documentation for MediaTek mt8192 >>> >>> Signed-off-by: Ryan Wu >>> --- >>> This patch is based on v5.10-rc7. >>> --- >>> Documentation/devicetree/bindings/nvmem/mtk-efuse.txt | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt >>> b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt >>> index 0668c45a156d..e2f0c0f34d10 100644 >>> --- a/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt >>> +++ b/Documentation/devicetree/bindings/nvmem/mtk-efuse.txt >>> @@ -7,6 +7,7 @@ Required properties: >>> "mediatek,mt7622-efuse", "mediatek,efuse": for MT7622 >>> "mediatek,mt7623-efuse", "mediatek,efuse": for MT7623 >>> "mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173 >>> + "mediatek,mt8192-efuse" or "mediatek,efuse": for MT8192 >> >> No, "mediatek,efuse" by itself is only for MT8173. > Is it should be modify from "mediatek,mt8192-efuse" or "mediatek,efuse" > to "mediatek,mt8192-efuse", "mediatek,efuse" ? > Yes, as you can see "mediatek,mt8192-efuse" is not defined in the driver (and should not as long as the HW has no difference from the already implemented driver). Regards, Matthias > Regards, > Yz >> >>> - reg: Should contain registers location and length >>> >>> = Data cells = >>> -- >>> 2.18.0 >>> >> >> ___ >> Linux-mediatek mailing list >> linux-media...@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-mediatek >
Re: [PATCH v1 2/2] arm64: dts: mt6779: Support ufshci and ufsphy
On 23/12/2020 05:13, Stanley Chu wrote:
> Support UFS on MT6779 platforms by adding ufshci and ufsphy
> nodes in dts file.
>
> Reviewed-by: Hanks Chen
> Signed-off-by: Stanley Chu
> ---
> arch/arm64/boot/dts/mediatek/mt6779.dtsi | 36 +++-
> 1 file changed, 35 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> index 370f309d32de..a8584b00cc9d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
> @@ -225,6 +225,41 @@
> #clock-cells = <1>;
> };
>
> + ufshci: ufshci@1127 {
> + compatible = "mediatek,mt8183-ufshci";
> + reg = <0 0x1127 0 0x2300>;
> + interrupts = ;
> + phys = <>;
> +
> + clocks = <_ao CLK_INFRA_UFS>,
> + <_ao CLK_INFRA_UFS_TICK>,
> + <_ao CLK_INFRA_UFS_AXI>,
> + <_ao CLK_INFRA_UNIPRO_TICK>,
> + <_ao CLK_INFRA_UNIPRO_MBIST>,
> + < CLK_TOP_FAES_UFSFDE>,
> + <_ao CLK_INFRA_AES_UFSFDE>,
> + <_ao CLK_INFRA_AES_BCLK>;
> + clock-names = "ufs", "ufs_tick", "ufs_axi",
> + "unipro_tick", "unipro_mbist",
> + "aes_top", "aes_infra", "aes_bclk";
> + freq-table-hz = <0 0>, <0 0>, <0 0>,
> + <0 0>, <0 0>, <0 0>,
> + <0 0>, <0 0>;
We are missing required property: vcc-supply
> +
> + mediatek,ufs-disable-ah8;
> + mediatek,ufs-support-va09;
Although supported in the driver, these are not defined in the binding document
(ufs-mediatek.txt). Before adding them, it would be good if you could update the
description to use yaml syntax instead.
Please also add "mediatek,ufs-boost-crypt" which is not defined in the binding
neither.
Regards,
Matthias
> + };
> +
> + ufsphy: phy@11fa {
> + compatible = "mediatek,mt8183-ufsphy";
> + reg = <0 0x11fa 0 0xc000>;
> + #phy-cells = <0>;
> +
> + clocks = <_ao CLK_INFRA_UNIPRO_SCK>,
> + <_ao CLK_INFRA_UFS_MP_SAP_BCLK>;
> + clock-names = "unipro", "mp";
> + };
> +
> mfgcfg: clock-controller@13fbf000 {
> compatible = "mediatek,mt6779-mfgcfg", "syscon";
> reg = <0 0x13fbf000 0 0x1000>;
> @@ -266,6 +301,5 @@
> reg = <0 0x1b00 0 0x1000>;
> #clock-cells = <1>;
> };
> -
> };
> };
>
Re: [PATCH] arm64: dts: mediatek: Add Mediatek mt8192 cpufreq device nodes
On 21/12/2020 04:36, Andrew-sh.Cheng wrote:
> From: "Andrew-sh.Cheng"
>
> This patch depends on [1] and [2].
>
> [1]http://lists.infradead.org/pipermail/linux-mediatek/2020-November/019378.html
> [2]https://patchwork.kernel.org/project/linux-mediatek/patch/1607586516-6547-3-git-send-email-hector.y...@mediatek.com/
[1] is already upstream. Please resend after [2] is accepted.
Thanks,
Matthias
>
> Signed-off-by: Andrew-sh.Cheng
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 69d45c7b31f1..770f7d8833db 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -39,6 +39,7 @@
> compatible = "arm,cortex-a55";
> reg = <0x000>;
> enable-method = "psci";
> + performance-domain = < 0>;
> clock-frequency = <170100>;
> next-level-cache = <_0>;
> capacity-dmips-mhz = <530>;
> @@ -49,6 +50,7 @@
> compatible = "arm,cortex-a55";
> reg = <0x100>;
> enable-method = "psci";
> + performance-domain = < 0>;
> clock-frequency = <170100>;
> next-level-cache = <_0>;
> capacity-dmips-mhz = <530>;
> @@ -59,6 +61,7 @@
> compatible = "arm,cortex-a55";
> reg = <0x200>;
> enable-method = "psci";
> + performance-domain = < 0>;
> clock-frequency = <170100>;
> next-level-cache = <_0>;
> capacity-dmips-mhz = <530>;
> @@ -69,6 +72,7 @@
> compatible = "arm,cortex-a55";
> reg = <0x300>;
> enable-method = "psci";
> + performance-domain = < 0>;
> clock-frequency = <170100>;
> next-level-cache = <_0>;
> capacity-dmips-mhz = <530>;
> @@ -79,6 +83,7 @@
> compatible = "arm,cortex-a76";
> reg = <0x400>;
> enable-method = "psci";
> + performance-domain = < 1>;
> clock-frequency = <217100>;
> next-level-cache = <_1>;
> capacity-dmips-mhz = <1024>;
> @@ -89,6 +94,7 @@
> compatible = "arm,cortex-a76";
> reg = <0x500>;
> enable-method = "psci";
> + performance-domain = < 1>;
> clock-frequency = <217100>;
> next-level-cache = <_1>;
> capacity-dmips-mhz = <1024>;
> @@ -99,6 +105,7 @@
> compatible = "arm,cortex-a76";
> reg = <0x600>;
> enable-method = "psci";
> + performance-domain = < 1>;
> clock-frequency = <217100>;
> next-level-cache = <_1>;
> capacity-dmips-mhz = <1024>;
> @@ -109,6 +116,7 @@
> compatible = "arm,cortex-a76";
> reg = <0x700>;
> enable-method = "psci";
> + performance-domain = < 1>;
> clock-frequency = <217100>;
> next-level-cache = <_1>;
> capacity-dmips-mhz = <1024>;
> @@ -194,6 +202,12 @@
> compatible = "simple-bus";
> ranges;
>
> + performance: performance-controller@0011bc00 {
> + compatible = "mediatek,cpufreq-hw";
> + reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
> + #performance-domain-cells = <1>;
> + };
> +
> gic: interrupt-controller@c00 {
> compatible = "arm,gic-v3";
> #interrupt-cells = <4>;
>
Re: [PATCH 0/2] Add MediaTek MT8192 clock provider device nodes
On 22/12/2020 14:40, Weiyi Lu wrote: > This series is based on v5.10-rc1, MT8192 dts v6[1] and > MT8192 clock v6 series[2]. > > [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=373899 > [2] https://patchwork.kernel.org/project/linux-mediatek/list/?series=405295 > [1] is already mainline. You could add this patch as a new one to [2]. But please try to improve the series, before sending just a new version with this patch added. Regards, Matthias > Weiyi Lu (2): > arm64: dts: mediatek: Add mt8192 clock controllers > arm64: dts: mediatek: Correct UART0 bus clock of MT8192 > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 165 ++- > 1 file changed, 164 insertions(+), 1 deletion(-) >
Re: [PATCH 2/2] arm64: dts: mediatek: Correct UART0 bus clock of MT8192
On 22/12/2020 14:40, Weiyi Lu wrote: > infra_uart0 clock is the real one what uart0 uses as bus clock. > > Signed-off-by: Weiyi Lu > --- > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > index 92dcfbd..ac5dca6 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi > @@ -283,7 +283,7 @@ >"mediatek,mt6577-uart"; > reg = <0 0x11002000 0 0x1000>; > interrupts = ; > - clocks = <>, <>; > + clocks = <>, < CLK_INFRA_UART0>; Please update the clocks for all nodes to use the clock driver, not just uart or uart0. Thanks, Matthias > clock-names = "baud", "bus"; > status = "disabled"; > }; >
Re: [PATCH v4 2/5] soc: mediatek: pwrap: add arbiter capability
On 21/12/2020 03:33, Nicolas Boichat wrote:
> On Wed, Nov 18, 2020 at 8:08 PM Hsin-Hsiung Wang
> wrote:
>>
>> Add arbiter capability for pwrap driver.
>> The arbiter capability uses new design to judge the priority and latency
>> for multi-channel.
>> This patch is preparing for adding mt6873/8192 pwrap support.
>>
>> Signed-off-by: Hsin-Hsiung Wang
>> ---
>> drivers/soc/mediatek/mtk-pmic-wrap.c | 57
>> ++--
>> 1 file changed, 48 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c
>> b/drivers/soc/mediatek/mtk-pmic-wrap.c
>> index c897205..5678f46 100644
>> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
>> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
>> @@ -25,10 +25,12 @@
>>
>> /* macro for wrapper status */
>> #define PWRAP_GET_WACS_RDATA(x)(((x) >> 0) & 0x)
>> +#define PWRAP_GET_WACS_ARB_FSM(x) (((x) >> 1) & 0x0007)
>> #define PWRAP_GET_WACS_FSM(x) (((x) >> 16) & 0x0007)
>> #define PWRAP_GET_WACS_REQ(x) (((x) >> 19) & 0x0001)
>> #define PWRAP_STATE_SYNC_IDLE0 BIT(20)
>> #define PWRAP_STATE_INIT_DONE0 BIT(21)
>> +#define PWRAP_STATE_INIT_DONE1 BIT(15)
>>
>> /* macro for WACS FSM */
>> #define PWRAP_WACS_FSM_IDLE0x00
>> @@ -74,6 +76,7 @@
>> #define PWRAP_CAP_DCM BIT(2)
>> #define PWRAP_CAP_INT1_EN BIT(3)
>> #define PWRAP_CAP_WDT_SRC1 BIT(4)
>> +#define PWRAP_CAP_ARB BIT(5)
>>
>> /* defines for slave device wrapper registers */
>> enum dew_regs {
>> @@ -340,6 +343,8 @@ enum pwrap_regs {
>> PWRAP_DCM_DBC_PRD,
>> PWRAP_EINT_STA0_ADR,
>> PWRAP_EINT_STA1_ADR,
>> + PWRAP_SWINF_2_WDATA_31_0,
>> + PWRAP_SWINF_2_RDATA_31_0,
>>
>> /* MT2701 only regs */
>> PWRAP_ADC_CMD_ADDR,
>> @@ -1108,14 +1113,22 @@ static void pwrap_writel(struct pmic_wrapper *wrp,
>> u32 val, enum pwrap_regs reg)
>>
>> static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
>> {
>> - u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
>> + u32 val;
>> +
>> + val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
>> + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
>> + return PWRAP_GET_WACS_ARB_FSM(val) == PWRAP_WACS_FSM_IDLE;
>>
>> return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE;
>> }
>>
>> static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
>> {
>> - u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
>> + u32 val;
>> +
>> + val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
>> + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
>> + return PWRAP_GET_WACS_ARB_FSM(val) ==
>> PWRAP_WACS_FSM_WFVLDCLR;
>
> This code is now copied twice. Do you think it'd be better to create a
> new function?
>
> static u32 pwrap_get_fsm_state(struct pmic_wrapper *wrp) {
>if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
> return PWRAP_GET_WACS_ARB_FSM(val);
>else
> return PWRAP_GET_WACS_FSM(val);
> }
>
>>
>> return PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR;
>> }
>> @@ -1165,6 +1178,7 @@ static int pwrap_wait_for_state(struct pmic_wrapper
>> *wrp,
>> static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
>> {
>> int ret;
>> + u32 val;
>>
>> ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
>> if (ret) {
>> @@ -1172,13 +1186,21 @@ static int pwrap_read16(struct pmic_wrapper *wrp,
>> u32 adr, u32 *rdata)
>> return ret;
>> }
>>
>> - pwrap_writel(wrp, (adr >> 1) << 16, PWRAP_WACS2_CMD);
>> + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
>> + val = adr;
>> + else
>> + val = (adr >> 1) << 16;
>> + pwrap_writel(wrp, val, PWRAP_WACS2_CMD);
>>
>> ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_vldclr);
>> if (ret)
>> return ret;
>>
>> - *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
>> + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
>> + val = pwrap_readl(wrp, PWRAP_SWINF_2_RDATA_31_0);
>> + else
>> + val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
>> + *rdata = PWRAP_GET_WACS_RDATA(val);
>>
>> pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
>>
>> @@ -1228,8 +1250,13 @@ static int pwrap_write16(struct pmic_wrapper *wrp,
>> u32 adr, u32 wdata)
>> return ret;
>> }
>>
>> - pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
>> -PWRAP_WACS2_CMD);
>> + if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) {
>> + pwrap_writel(wrp, wdata, PWRAP_SWINF_2_WDATA_31_0);
>> + pwrap_writel(wrp, BIT(29) | adr, PWRAP_WACS2_CMD);
>> + } else {
>> + pwrap_writel(wrp, BIT(31) | ((adr >> 1) << 16) | wdata,
>> +PWRAP_WACS2_CMD);
>> + }
>>
>> return 0;
>> }
>> @@
Re: [PATCH] arm64: dts: mt8192: Add cpu-idle-states
On 22/12/2020 05:58, James Liao wrote:
> Add idle states for cpu-off and cluster-off.
>
> Signed-off-by: James Liao
> ---
Applied to v5.11-next/dts64
Thanks!
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 44
> 1 file changed, 44 insertions(+)
>
> This patch bases on v5.10 and [1], adds idle-states for MT8192 CPUs.
>
> [1]
> https://lore.kernel.org/linux-arm-kernel/20201030092207.26488-2-seiya.w...@mediatek.com/
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index e12e024de122..c7f2ec9ea4f1 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -39,6 +39,7 @@
> reg = <0x000>;
> enable-method = "psci";
> clock-frequency = <170100>;
> + cpu-idle-states = <_l _l>;
> next-level-cache = <_0>;
> capacity-dmips-mhz = <530>;
> };
> @@ -49,6 +50,7 @@
> reg = <0x100>;
> enable-method = "psci";
> clock-frequency = <170100>;
> + cpu-idle-states = <_l _l>;
> next-level-cache = <_0>;
> capacity-dmips-mhz = <530>;
> };
> @@ -59,6 +61,7 @@
> reg = <0x200>;
> enable-method = "psci";
> clock-frequency = <170100>;
> + cpu-idle-states = <_l _l>;
> next-level-cache = <_0>;
> capacity-dmips-mhz = <530>;
> };
> @@ -69,6 +72,7 @@
> reg = <0x300>;
> enable-method = "psci";
> clock-frequency = <170100>;
> + cpu-idle-states = <_l _l>;
> next-level-cache = <_0>;
> capacity-dmips-mhz = <530>;
> };
> @@ -79,6 +83,7 @@
> reg = <0x400>;
> enable-method = "psci";
> clock-frequency = <217100>;
> + cpu-idle-states = <_b _b>;
> next-level-cache = <_1>;
> capacity-dmips-mhz = <1024>;
> };
> @@ -89,6 +94,7 @@
> reg = <0x500>;
> enable-method = "psci";
> clock-frequency = <217100>;
> + cpu-idle-states = <_b _b>;
> next-level-cache = <_1>;
> capacity-dmips-mhz = <1024>;
> };
> @@ -99,6 +105,7 @@
> reg = <0x600>;
> enable-method = "psci";
> clock-frequency = <217100>;
> + cpu-idle-states = <_b _b>;
> next-level-cache = <_1>;
> capacity-dmips-mhz = <1024>;
> };
> @@ -109,6 +116,7 @@
> reg = <0x700>;
> enable-method = "psci";
> clock-frequency = <217100>;
> + cpu-idle-states = <_b _b>;
> next-level-cache = <_1>;
> capacity-dmips-mhz = <1024>;
> };
> @@ -158,6 +166,42 @@
> l3_0: l3-cache {
> compatible = "cache";
> };
> +
> + idle-states {
> + entry-method = "arm,psci";
> + cpuoff_l: cpuoff_l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x00010001>;
> + local-timer-stop;
> + entry-latency-us = <55>;
> + exit-latency-us = <140>;
> + min-residency-us = <780>;
> + };
> + cpuoff_b: cpuoff_b {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x00010001>;
> + local-timer-stop;
> + entry-latency-us = <35>;
> + exit-latency-us = <145>;
> + min-residency-us = <720>;
> + };
> + clusteroff_l: clusteroff_l {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x01010002>;
> + local-timer-stop;
> + entry-latency-us = <60>;
> + exit-latency-us = <155>;
> + min-residency-us = <860>;
> + };
> + clusteroff_b: clusteroff_b {
> + compatible = "arm,idle-state";
> +
Re: [PATCH v10] cpufreq: mediatek-hw: Add support for Mediatek cpufreq HW driver
On 29/12/2020 07:17, Hector Yuan wrote: > The CPUfreq HW present in some Mediatek chipsets offloads the steps necessary > for changing the frequency of CPUs. > The driver implements the cpufreq driver interface for this hardware engine. > This patch depends on MT6779 DTS patchset[1] submitted by Hanks Chen. This dependency got resolved, the patch is mainline since v5.11. Please delete it in further revisions of the patch set to minimize confusion. Thanks! > > From v8 to v9, there are three more modifications. > 1. Based on patchset[2], align binding with scmi for performance domain. > 2. Add the CPUFREQ fast switch function support and define DVFS latency. > 3. Based on patchser[3], add energy model API parameter for mW. > > From v7 to v8, there are three more patches based on patchset v8[4]. > This patchset is about to register power table to Energy model for EAS and > thermal usage. > 1. EM CPU power table > - Register energy model table for EAS and thermal cooling device usage. > - Read the coresponding LUT for power table. > 2. SVS initialization > - The SVS(Smart Voltage Scaling) engine is a hardware which is > used to calculate optimized voltage values for CPU power domain. > DVFS driver could apply those optimized voltage values to reduce power > consumption. > - Driver will polling if HW engine is done for SVS initialization. > After that, driver will read power table and register it to EAS. > - CPUs must be in power on state when doing SVS. Use pm_qos to block cpu-idle > state for SVS initializing. > 3. Cooling device flag > - Add cooling device flag for thermal > > [1] https://lkml.org/lkml/2020/8/4/1094 > [2] > https://lore.kernel.org/lkml/20201116181356.804590-1-sudeep.ho...@arm.com/ > [3] > https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git/commit/?h=linux-next=c250d50fe2ce627ca9805d9c8ac11cbbf922a4a6 > [4] https://lkml.org/lkml/2020/9/23/384 > > > Hector.Yuan (2): > cpufreq: mediatek-hw: Add support for CPUFREQ HW > dt-bindings: cpufreq: add bindings for MediaTek cpufreq HW > > .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 116 ++ > drivers/cpufreq/Kconfig.arm| 12 + > drivers/cpufreq/Makefile |1 + > drivers/cpufreq/mediatek-cpufreq-hw.c | 370 > > 4 files changed, 499 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml > create mode 100644 drivers/cpufreq/mediatek-cpufreq-hw.c >
Re: [PATCH v1] arm64: dts: mt8192: add nor_flash device node
On 31/01/2021 11:26, Matthias Brugger wrote:
>
>
> On 10/12/2020 09:34, Bayi Cheng wrote:
>> From: bayi cheng
>>
>> add nor_flash device node
>>
>> Signed-off-by: bayi cheng
>> ---
>> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 13 +
>> 1 file changed, 13 insertions(+)
>>
>
> Applied to v5.11-next/dts64
reverted and replaced with v2.
Thanks!
>
> Thanks
>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>> b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>> index e12e024..b15b0d3 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
>> @@ -379,6 +379,19 @@
>> status = "disabled";
>> };
>>
>> +nor_flash: spi@11234000 {
>> +compatible = "mediatek,mt8173-nor";
>> +reg = <0 0x11234000 0 0xe0>;
>> +interrupts = ;
>> +clocks = <>,
>> + <>,
>> + <>;
>> +clock-names = "spi", "sf", "axi";
>> +#address-cells = <1>;
>> +#size-cells = <0>;
>> +status = "disable";
>> +};
>> +
>> i2c3: i2c3@11cb {
>> compatible = "mediatek,mt8192-i2c";
>> reg = <0 0x11cb 0 0x1000>,
>>
