[PATCH v2 4/4] arm64: defconfig: Enable MediaTek DRAMC common driver
This commit enables MediaTek DRAMC common driver to be built as a module by default for the ARM64 builds. Signed-off-by: Po-Kai Chi --- arch/arm64/configs/defconfig |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d612f63..49d7464 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1163,3 +1163,4 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_PREEMPT is not set # CONFIG_FTRACE is not set CONFIG_MEMTEST=y +CONFIG_MTK_DRAMC=m -- 1.7.9.5
[PATCH v2] memory: mediatek: add DRAM controller driver
These patch series introduces the MediaTek DRAM controller driver (DRAMC) on MT6779 SoC, and enables to be built as a module by default for the ARM64 builds. MediaTek DRAMC driver provides cross-platform features as below: - API provided to other kernel modules for querying DRAM type, rank count, rank size, channel count and mode register settings. - Sysfs interface used to pass DRAM mode register settings and current DRAM data rate to user-space for MediaTek ecosystem. The API user includes MediaTek External Memory Interface (EMI) and DVFS Resource Control (DVFSRC), which will be sent to mainline later. Changes since v1: - add prefix to vendor properties in device tree, dt-binding and drivers - fix dt-binding check fail Po-Kai Chi (4): dt-bindings: memory: Add binding for MediaTek DRAM Controller memory: mediatek: add DRAM controller driver arm64: dts: add DRAMC node for MT6779 arm64: defconfig: Enable MediaTek DRAMC common driver .../memory-controllers/mediatek,dramc.yaml| 162 arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 9 + arch/arm64/boot/dts/mediatek/mt6779.dtsi | 18 + arch/arm64/configs/defconfig | 1 + drivers/memory/Kconfig| 1 + drivers/memory/Makefile | 1 + drivers/memory/mediatek/Kconfig | 9 + drivers/memory/mediatek/Makefile | 3 + drivers/memory/mediatek/mtk-dramc.c | 711 ++ include/memory/mediatek/dramc.h | 18 + 10 files changed, 933 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml create mode 100644 drivers/memory/mediatek/Kconfig create mode 100644 drivers/memory/mediatek/Makefile create mode 100644 drivers/memory/mediatek/mtk-dramc.c create mode 100644 include/memory/mediatek/dramc.h
[PATCH v2 2/4] memory: mediatek: add DRAM controller driver
MediaTek DRAM controller (DRAMC) driver provides cross-platform features
as below:
1. provide APIs for low power feature queries
2. create sysfs to pass the DRAM information to user-space
Signed-off-by: Po-Kai Chi
---
drivers/memory/Kconfig |1 +
drivers/memory/Makefile |1 +
drivers/memory/mediatek/Kconfig |9 +
drivers/memory/mediatek/Makefile|3 +
drivers/memory/mediatek/mtk-dramc.c | 711 +++
include/memory/mediatek/dramc.h | 18 +
6 files changed, 743 insertions(+)
create mode 100644 drivers/memory/mediatek/Kconfig
create mode 100644 drivers/memory/mediatek/Makefile
create mode 100644 drivers/memory/mediatek/mtk-dramc.c
create mode 100644 include/memory/mediatek/dramc.h
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 72c0df1..056e906 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -225,6 +225,7 @@ config STM32_FMC2_EBI
devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
SOCs containing the FMC2 External Bus Interface.
+source "drivers/memory/mediatek/Kconfig"
source "drivers/memory/samsung/Kconfig"
source "drivers/memory/tegra/Kconfig"
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index bc7663e..cd4f8cf 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_PL353_SMC) += pl353-smc.o
obj-$(CONFIG_RENESAS_RPCIF)+= renesas-rpc-if.o
obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o
+obj-$(CONFIG_MTK_DRAMC)+= mediatek/
obj-$(CONFIG_SAMSUNG_MC) += samsung/
obj-$(CONFIG_TEGRA_MC) += tegra/
obj-$(CONFIG_TI_EMIF_SRAM) += ti-emif-sram.o
diff --git a/drivers/memory/mediatek/Kconfig b/drivers/memory/mediatek/Kconfig
new file mode 100644
index 000..a1618b0
--- /dev/null
+++ b/drivers/memory/mediatek/Kconfig
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config MTK_DRAMC
+ tristate "MediaTek DRAMC driver"
+ help
+ This selects the MediaTek(R) DRAMC driver.
+ Provide the API for DRAMC low power scenario, and the interface
+ for reporting DRAM information, e.g. DRAM mode register (MR) for
+ DRAM vendor ID, temperature, and density.
diff --git a/drivers/memory/mediatek/Makefile b/drivers/memory/mediatek/Makefile
new file mode 100644
index 000..632be48
--- /dev/null
+++ b/drivers/memory/mediatek/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_MTK_DRAMC)+= mtk-dramc.o
diff --git a/drivers/memory/mediatek/mtk-dramc.c
b/drivers/memory/mediatek/mtk-dramc.c
new file mode 100644
index 000..155b3b7
--- /dev/null
+++ b/drivers/memory/mediatek/mtk-dramc.c
@@ -0,0 +1,711 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DRAMC_DRV_NAME "mtk-dramc"
+
+struct mr_info_t {
+ unsigned int mr_index;
+ unsigned int mr_value;
+};
+
+/*
+ * struct reg_ctrl_t - to describe the bits required in a register
+ * @offset: register address offset from a base
+ * @mask: bitmask of the target bits
+ * @shift: starting bit of the target bits
+ */
+struct reg_ctrl_t {
+ unsigned int offset;
+ unsigned int mask;
+ unsigned int shift;
+};
+
+struct fmeter_dev_t {
+ unsigned int crystal_freq;
+ unsigned int shu_of;
+ struct reg_ctrl_t shu_lv;
+ struct reg_ctrl_t pll_id;
+ struct reg_ctrl_t pll_md[2];
+ struct reg_ctrl_t sdmpcw[2];
+ struct reg_ctrl_t prediv[2];
+ struct reg_ctrl_t posdiv[2];
+ struct reg_ctrl_t ckdiv4[2];
+ struct reg_ctrl_t cldiv2[2];
+ struct reg_ctrl_t fbksel[2];
+ struct reg_ctrl_t dqopen[2];
+};
+
+struct mr4_dev_t {
+ struct reg_ctrl_t mr4_rg;
+};
+
+struct dramc_dev_t {
+ unsigned int dram_type;
+ unsigned int support_channel_cnt;
+ unsigned int channel_cnt;
+ unsigned int rank_cnt;
+ unsigned int mr_cnt;
+ unsigned int freq_cnt;
+ unsigned int *rank_size;
+ unsigned int *freq_step;
+ struct mr_info_t *mr_info_ptr;
+ void __iomem **dramc_chn_base_ao;
+ void __iomem **dramc_chn_base_nao;
+ void __iomem **ddrphy_chn_base_ao;
+ void *mr4_dev_ptr;
+ void *fmeter_dev_ptr;
+};
+
+enum DRAM_TYPE {
+ TYPE_NONE = 0,
+ TYPE_DDR1,
+ TYPE_LPDDR2,
+ TYPE_LPDDR3,
+ TYPE_PCDDR3,
+ TYPE_LPDDR4,
+ TYPE_LPDDR4X,
+ TYPE_LPDDR4P
+};
+
+static const struct fmeter_dev_t fmeter_v0_mt6779_t = {
+ .crystal_freq = 52,
+ .shu_of = 0x500,
+ .shu_lv = { .offset = 0x00e4, .mask = 0x0006, .shift = 1 },
+ .pll_id = { .offset = 0x0510, .mask = 0x8000, .shift = 31 },
+ .pl
[PATCH v2 3/4] arm64: dts: add DRAMC node for MT6779
Add the DRAMC node for the DRAMC kernel driver.
Properties are divided into three categories:
- Platform DTS:
MediaTek DRAMC platform common part.
- Project DTS:
Runtime filled in by bootloader according to the board
hardware configuration.
- Driver level:
Hardware-specific register settings, encapsulated as
compatible data for better DTS compatibility.
Signed-off-by: Po-Kai Chi
---
arch/arm64/boot/dts/mediatek/mt6779-evb.dts |9 +
arch/arm64/boot/dts/mediatek/mt6779.dtsi| 18 ++
2 files changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
index 164f5cb..5d2dde7 100644
--- a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
@@ -29,3 +29,12 @@
{
status = "okay";
};
+
+ {
+ mediatek,dram-type = <0>;
+ mediatek,channel-cnt = <2>;
+ mediatek,rank-cnt = <2>;
+ mediatek,rank-size = <0x0 0x0>;
+ mediatek,mr-cnt = <1>;
+ mediatek,mr = <0x5 0xff>;
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
index 9bdf514..28492a0 100644
--- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -206,6 +206,24 @@
clock-names = "devapc-infra-clock";
};
+ dramc: dramc@1023 {
+ compatible = "mediatek,mt6779-dramc";
+ reg = <0 0x1023 0 0x2000>, /* DRAMC AO CHA */
+ <0 0x1024 0 0x2000>, /* DRAMC AO CHB */
+ <0 0x10234000 0 0x1000>, /* DRAMC NAO CHA */
+ <0 0x10244000 0 0x1000>, /* DRAMC NAO CHB */
+ <0 0x10238000 0 0x2000>, /* DDRPHY AO CHA */
+ <0 0x10248000 0 0x2000>; /* DDRPHY AO CHB */
+ mediatek,support-channel-cnt = <2>;
+ mediatek,freq-cnt = <6>;
+ mediatek,freq-step = <3718 3733>,
+ <3094 3200>,
+ <2392 2400>,
+ <1534 1600>,
+ <1196 1200>,
+ <754 800>;
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt6779-uart",
"mediatek,mt6577-uart";
--
1.7.9.5
[PATCH v2 1/4] dt-bindings: memory: Add binding for MediaTek DRAM Controller
This patch adds the documentation of the device-tree binding for
MediaTek DRAM Controller.
Signed-off-by: Po-Kai Chi
---
.../memory-controllers/mediatek,dramc.yaml | 162
1 file changed, 162 insertions(+)
create mode 100644
Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
diff --git
a/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
b/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
new file mode 100644
index 000..18f77c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
@@ -0,0 +1,162 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2021 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/mediatek,dramc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek DRAM Controller
+
+maintainers:
+ - Po-Kai Chi
+
+description: |
+ MediaTek DRAM controller (DRAMC) provides an interface to query information
+ about DRAM which collected from bootloader and device tree.
+ This is mainly used by MediaTek Extended Memory Interface (EMI) and DVFS
Resource
+ Control (DVFSRC).
+
+properties:
+ compatible:
+items:
+ - enum:
+ - mediatek,mt6779-dramc
+
+ reg:
+description:
+ Base address of MediaTek DRAM related hardware modules, each channel has
+ its own base address in order of
+ DRAMC_AO_{CH}, DRAMC_NAO_{CH}, DDRPHY_AO_{CH}.
+minItems: 3# 3 * N channels
+maxItems: 6
+
+ mediatek,dram-type:
+description:
+ The DRAM type of current DRAM chip.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 0
+maximum: 7
+
+ mediatek,support-channel-cnt:
+description:
+ The maximum DRAM channel count supported by SoC.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 4
+
+ mediatek,channel-cnt:
+description:
+ The DRAM channel count of current DRAM chip.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 4
+
+ mediatek,rank-cnt:
+description:
+ The DRAM rank count of current DRAM chip.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 2
+
+ mediatek,rank-size:
+description:
+ An array of 64-bits unsigned integer that describes the size of each
+ DRAM rank.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint64-array
+minItems: 1
+maxItems: 2
+items:
+ minimum: 0x0
+ maximum: 0x1# support up to 4GB in single rank
+
+ mediatek,mr-cnt:
+description:
+ Specifies how many sets of DRAM mode register information to provide.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint32
+maximum: 40# total 40 MRs for JEDEC LPDDR4X
+
+ mediatek,mr:
+description:
+ Pair of DRAM mode register information.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint32-matrix
+maxItems: 40# align with mediatek,mr-cnt
+items:
+ items:
+- description:
+Mode register index
+- description:
+Mode register value
+
+ mediatek,freq-cnt:
+description:
+ Specifies how many sets of DRAM data clock rate supported by SoC.
+$ref: /schemas/types.yaml#/definitions/uint32
+
+ mediatek,freq-step:
+description:
+ The DRAM data clock rate may be slightly different from those defined
+ by the specification due to errors in multiples of the base frequency.
+ This describe the mapping from real data clock rate measured by
+ frequency meter to JEDEC data clock rate.
+$ref: /schemas/types.yaml#/definitions/uint32-matrix
+items:
+ items:
+- description:
+Real data rate
+- description:
+Spec data rate
+
+required:
+ - compatible
+ - reg
+ - mediatek,dram-type
+ - mediatek,support-channel-cnt
+ - mediatek,channel-cnt
+ - mediatek,rank-cnt
+ - mediatek,mr-cnt
+ - mediatek,freq-cnt
+
+additionalProperties: false
+
+examples:
+ - |
+soc {
+#address-cells = <2>;
+#size-cells = <2>;
+
+dramc@1023 {
+compatible = "mediatek,mt6779-dramc";
+reg = <0 0x1023 0 0x2000>, /* DRAMC AO CHA */
+<0 0x1024 0 0x2000>, /* D
Re: [PATCH v1 1/4] dt-bindings: memory: Add binding for MediaTek Common DRAM Controller
Hello Rob,
Thanks for the remind about dt_binding_check fail and the comments, my
reply is as follows and will fix it in the next version (v2).
Po-Kai
On Tue, 2021-03-30 at 21:58 +0800, Rob Herring wrote:
> On Tue, Mar 30, 2021 at 01:22:08PM +0800, Po-Kai Chi wrote:
> > This patch adds the documentation of the device-tree binding for
> > MediaTek Common DRAM Controller.
> >
> > Signed-off-by: Po-Kai Chi
> > ---
> > .../memory-controllers/mediatek,dramc.yaml | 155
> >
> > 1 file changed, 155 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
> > b/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
> > new file mode 100644
> > index 000..0217ce0
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
> > @@ -0,0 +1,155 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (c) 2021 MediaTek Inc.
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/memory-controllers/mediatek,dramc.yaml*__;Iw!!CTRNKA9wMg0ARbw!y9zM5d-aNLK99Y_ag2yvqq3TI1Xvm6TV_Vu03VVD3Qbe69N1qZXFFk2DUFb6CG0$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!y9zM5d-aNLK99Y_ag2yvqq3TI1Xvm6TV_Vu03VVD3Qbe69N1qZXFFk2DiMad89A$
> >
> > +
> > +title: MediaTek DRAM Controller
> > +
> > +maintainers:
> > + - Po-Kai Chi
> > +
> > +description: |
> > + MediaTek DRAM controller (DRAMC) provides an interface to query
> > information
> > + about DRAM which collected from bootloader and device tree.
> > + This is mainly used by MediaTek Extended Memory Interface (EMI) and DVFS
> > Resource
> > + Control (DVFSRC).
> > +
> > +properties:
> > + compatible:
> > +items:
> > + - enum:
> > + - mediatek,mt6779-dramc
> > +
> > + reg:
> > +description:
> > + Base address of MediaTek DRAM related hardware modules, each channel
> > has
> > + its own base address in order of
> > + DRAMC_AO_{CH}, DRAMC_NAO_{CH}, DDRPHY_AO_{CH}.
> > +minItems: 3# 3 * N channels
> > +maxItems: 6
> > +
> > + dram_type:
>
> These need to be either common or have a vendor prefix.
>
> Also, s/_/-/
Okay, I have revised the naming rule according to writing-schema.rst.
> > +description:
> > + The DRAM type of current DRAM chip.
> > + This property is filled in by bootloader according to the board
> > hardware
> > + configuration.
> > +$ref: /schemas/types.yaml#/definitions/uint32
> > +minimum: 0
> > +maximum: 7
> > +
> > + support_channel_cnt:
> > +description:
> > + The maximum DRAM channel count supported by SoC.
> > +$ref: /schemas/types.yaml#/definitions/uint32
> > +minimum: 1
> > +maximum: 4
> > +
> > + channel_cnt:
> > +description:
> > + The DRAM channel count of current DRAM chip.
> > + This property is filled in by bootloader according to the board
> > hardware
> > + configuration.
> > +$ref: /schemas/types.yaml#/definitions/uint32
> > +minimum: 1
> > +maximum: 4
> > +
> > + rank_cnt:
> > +description:
> > + The DRAM rank count of current DRAM chip.
> > + This property is filled in by bootloader according to the board
> > hardware
> > + configuration.
> > +$ref: /schemas/types.yaml#/definitions/uint32
> > +minimum: 1
> > +maximum: 2
> > +
> > + rank_size:
> > +description:
> > + The size of each DRAM rank.
> > + This property is filled in by bootloader according to the board
> > hardware
> > + configuration.
> > +$ref: /schemas/types.yaml#/definitions/uint64
There may be some misunderstanding.
rank_size uses the full 64 bits to describe the size of each DRAM rank.
So the type of rank_size should be uint64-array, instead of uint64.
> > +minItems: 1
> > +maxItems: 2
> > +items:
> > + minimum: 0x0
> > + maximum: 0x1# support up to 4GB in single rank
> > +
> > + mr_cnt:
> > +description:
> > + Specifies how many sets of DRAM mode register i
[PATCH v1 3/4] arm64: dts: add DRAMC node for MT6779
Add the DRAMC node for the DRAMC kernel driver.
Properties are divided into three categories:
- Platform DTS:
MediaTek DRAMC platform common part.
- Project DTS:
Runtime filled in by bootloader according to the board
hardware configuration.
- Driver level:
Hardware-specific register settings, encapsulated as
compatible data for better DTS compatibility.
Signed-off-by: Po-Kai Chi
---
arch/arm64/boot/dts/mediatek/mt6779-evb.dts |9 +
arch/arm64/boot/dts/mediatek/mt6779.dtsi| 18 ++
2 files changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
index 164f5cb..9a556ad 100644
--- a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
@@ -29,3 +29,12 @@
{
status = "okay";
};
+
+ {
+ dram_type = <0>;
+ channel_cnt = <2>;
+ rank_cnt = <2>;
+ rank_size = <0x0 0x0>;
+ mr_cnt = <1>;
+ mr = <0x5 0xff>;
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
index 9bdf514..332d48d 100644
--- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -206,6 +206,24 @@
clock-names = "devapc-infra-clock";
};
+ dramc: dramc@1023 {
+ compatible = "mediatek,mt6779-dramc";
+ reg = <0 0x1023 0 0x2000>, /* DRAMC AO CHA */
+ <0 0x1024 0 0x2000>, /* DRAMC AO CHB */
+ <0 0x10234000 0 0x1000>, /* DRAMC NAO CHA */
+ <0 0x10244000 0 0x1000>, /* DRAMC NAO CHB */
+ <0 0x10238000 0 0x2000>, /* DDRPHY AO CHA */
+ <0 0x10248000 0 0x2000>; /* DDRPHY AO CHB */
+ support_channel_cnt = <2>;
+ freq_cnt = <6>;
+ freq_step = <3718 3733>,
+ <3094 3200>,
+ <2392 2400>,
+ <1534 1600>,
+ <1196 1200>,
+ <754 800>;
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,mt6779-uart",
"mediatek,mt6577-uart";
--
1.7.9.5
[PATCH v1 4/4] arm64: defconfig: Enable MediaTek DRAMC common driver
This commit enables MediaTek DRAMC common driver to be built as a module by default for the ARM64 builds. Signed-off-by: Po-Kai Chi --- arch/arm64/configs/defconfig |1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d612f63..49d7464 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1163,3 +1163,4 @@ CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_PREEMPT is not set # CONFIG_FTRACE is not set CONFIG_MEMTEST=y +CONFIG_MTK_DRAMC=m -- 1.7.9.5
[PATCH v1 2/4] memory: mediatek: add DRAM controller driver
MediaTek DRAM controller (DRAMC) driver provides cross-platform features
as below:
- API provided to other kernel modules for querying DRAM type,
rank count, rank size, channel count and mode register settings.
- Sysfs interface used to pass DRAM mode register settings and current
DRAM data rate to user-space for MediaTek ecosystem.
Signed-off-by: Po-Kai Chi
---
drivers/memory/Kconfig |1 +
drivers/memory/Makefile |1 +
drivers/memory/mediatek/Kconfig |9 +
drivers/memory/mediatek/Makefile|3 +
drivers/memory/mediatek/mtk-dramc.c | 711 +++
include/memory/mediatek/dramc.h | 18 +
6 files changed, 743 insertions(+)
create mode 100644 drivers/memory/mediatek/Kconfig
create mode 100644 drivers/memory/mediatek/Makefile
create mode 100644 drivers/memory/mediatek/mtk-dramc.c
create mode 100644 include/memory/mediatek/dramc.h
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 72c0df1..056e906 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -225,6 +225,7 @@ config STM32_FMC2_EBI
devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
SOCs containing the FMC2 External Bus Interface.
+source "drivers/memory/mediatek/Kconfig"
source "drivers/memory/samsung/Kconfig"
source "drivers/memory/tegra/Kconfig"
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index bc7663e..cd4f8cf 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_PL353_SMC) += pl353-smc.o
obj-$(CONFIG_RENESAS_RPCIF)+= renesas-rpc-if.o
obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o
+obj-$(CONFIG_MTK_DRAMC)+= mediatek/
obj-$(CONFIG_SAMSUNG_MC) += samsung/
obj-$(CONFIG_TEGRA_MC) += tegra/
obj-$(CONFIG_TI_EMIF_SRAM) += ti-emif-sram.o
diff --git a/drivers/memory/mediatek/Kconfig b/drivers/memory/mediatek/Kconfig
new file mode 100644
index 000..a1618b0
--- /dev/null
+++ b/drivers/memory/mediatek/Kconfig
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config MTK_DRAMC
+ tristate "MediaTek DRAMC driver"
+ help
+ This selects the MediaTek(R) DRAMC driver.
+ Provide the API for DRAMC low power scenario, and the interface
+ for reporting DRAM information, e.g. DRAM mode register (MR) for
+ DRAM vendor ID, temperature, and density.
diff --git a/drivers/memory/mediatek/Makefile b/drivers/memory/mediatek/Makefile
new file mode 100644
index 000..632be48
--- /dev/null
+++ b/drivers/memory/mediatek/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_MTK_DRAMC)+= mtk-dramc.o
diff --git a/drivers/memory/mediatek/mtk-dramc.c
b/drivers/memory/mediatek/mtk-dramc.c
new file mode 100644
index 000..d81d311
--- /dev/null
+++ b/drivers/memory/mediatek/mtk-dramc.c
@@ -0,0 +1,711 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DRAMC_DRV_NAME "mtk-dramc"
+
+struct mr_info_t {
+ unsigned int mr_index;
+ unsigned int mr_value;
+};
+
+/*
+ * struct reg_ctrl_t - to describe the bits required in a register
+ * @offset: register address offset from a base
+ * @mask: bitmask of the target bits
+ * @shift: starting bit of the target bits
+ */
+struct reg_ctrl_t {
+ unsigned int offset;
+ unsigned int mask;
+ unsigned int shift;
+};
+
+struct fmeter_dev_t {
+ unsigned int crystal_freq;
+ unsigned int shu_of;
+ struct reg_ctrl_t shu_lv;
+ struct reg_ctrl_t pll_id;
+ struct reg_ctrl_t pll_md[2];
+ struct reg_ctrl_t sdmpcw[2];
+ struct reg_ctrl_t prediv[2];
+ struct reg_ctrl_t posdiv[2];
+ struct reg_ctrl_t ckdiv4[2];
+ struct reg_ctrl_t cldiv2[2];
+ struct reg_ctrl_t fbksel[2];
+ struct reg_ctrl_t dqopen[2];
+};
+
+struct mr4_dev_t {
+ struct reg_ctrl_t mr4_rg;
+};
+
+struct dramc_dev_t {
+ unsigned int dram_type;
+ unsigned int support_channel_cnt;
+ unsigned int channel_cnt;
+ unsigned int rank_cnt;
+ unsigned int mr_cnt;
+ unsigned int freq_cnt;
+ unsigned int *rank_size;
+ unsigned int *freq_step;
+ struct mr_info_t *mr_info_ptr;
+ void __iomem **dramc_chn_base_ao;
+ void __iomem **dramc_chn_base_nao;
+ void __iomem **ddrphy_chn_base_ao;
+ void *mr4_dev_ptr;
+ void *fmeter_dev_ptr;
+};
+
+enum DRAM_TYPE {
+ TYPE_NONE = 0,
+ TYPE_DDR1,
+ TYPE_LPDDR2,
+ TYPE_LPDDR3,
+ TYPE_PCDDR3,
+ TYPE_LPDDR4,
+ TYPE_LPDDR4X,
+ TYPE_LPDDR4P
+};
+
+static const struct fmeter_dev_t fmeter_v0_mt6779_t = {
+ .crystal_freq = 52,
+ .shu_of = 0x500,
+
[PATCH v1 1/4] dt-bindings: memory: Add binding for MediaTek Common DRAM Controller
This patch adds the documentation of the device-tree binding for
MediaTek Common DRAM Controller.
Signed-off-by: Po-Kai Chi
---
.../memory-controllers/mediatek,dramc.yaml | 155
1 file changed, 155 insertions(+)
create mode 100644
Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
diff --git
a/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
b/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
new file mode 100644
index 000..0217ce0
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,dramc.yaml
@@ -0,0 +1,155 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2021 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/mediatek,dramc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek DRAM Controller
+
+maintainers:
+ - Po-Kai Chi
+
+description: |
+ MediaTek DRAM controller (DRAMC) provides an interface to query information
+ about DRAM which collected from bootloader and device tree.
+ This is mainly used by MediaTek Extended Memory Interface (EMI) and DVFS
Resource
+ Control (DVFSRC).
+
+properties:
+ compatible:
+items:
+ - enum:
+ - mediatek,mt6779-dramc
+
+ reg:
+description:
+ Base address of MediaTek DRAM related hardware modules, each channel has
+ its own base address in order of
+ DRAMC_AO_{CH}, DRAMC_NAO_{CH}, DDRPHY_AO_{CH}.
+minItems: 3# 3 * N channels
+maxItems: 6
+
+ dram_type:
+description:
+ The DRAM type of current DRAM chip.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 0
+maximum: 7
+
+ support_channel_cnt:
+description:
+ The maximum DRAM channel count supported by SoC.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 4
+
+ channel_cnt:
+description:
+ The DRAM channel count of current DRAM chip.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 4
+
+ rank_cnt:
+description:
+ The DRAM rank count of current DRAM chip.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 1
+maximum: 2
+
+ rank_size:
+description:
+ The size of each DRAM rank.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint64
+minItems: 1
+maxItems: 2
+items:
+ minimum: 0x0
+ maximum: 0x1# support up to 4GB in single rank
+
+ mr_cnt:
+description:
+ Specifies how many sets of DRAM mode register information to provide.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint32
+maximum: 40# total 40 MRs for JEDEC LPDDR4X
+
+ mr:
+description:
+ Pair of DRAM mode register information.
+ This property is filled in by bootloader according to the board hardware
+ configuration.
+$ref: /schemas/types.yaml#/definitions/uint32-matrix
+maxItems: 40# align with mr_cnt
+items:
+ items:
+- description:
+Mode register index
+- description:
+Mode register value
+
+ freq_cnt:
+description:
+ Specifies how many sets of DRAM data clock rate supported by SoC.
+$ref: /schemas/types.yaml#/definitions/uint32
+
+ freq_step:
+description:
+ The DRAM data clock rate may be slightly different from those defined
+ by the specification due to errors in multiples of the base frequency.
+ This describe the mapping from real data clock rate measured by
+ frequency meter to JEDEC data clock rate.
+$ref: /schemas/types.yaml#/definitions/uint32-matrix
+items:
+ items:
+- description:
+Real data rate
+- description:
+Spec data rate
+
+required:
+ - compatible
+ - reg
+ - dram_type
+ - support_channel_cnt
+ - channel_cnt
+ - rank_cnt
+ - mr_cnt
+ - freq_cnt
+
+additionalProperties: false
+
+examples:
+ - |
+dramc@1023 {
+compatible = "mediatek,mt6779-dramc";
+reg = <0 0x1023 0 0x2000>, /* DRAMC AO CHA */
+<0 0x1024 0 0x2000>, /* DRAMC AO CHB */
+<0 0x10234000 0 0x1000>, /* DRAMC NAO CHA */
+<0 0x10244000 0 0x1000>, /* DRAMC NAO CHB */
+<0 0x10238000 0 0x2000>, /* DDRPHY AO CHA */
+<0 0x10248000 0 0x2000>; /* DDRPHY AO CHB */
+dram
[PATCH v1] memory: mediatek: add DRAM controller driver
These patch series introduces the MediaTek DRAM controller driver (DRAMC) on MT6779 SoC, and enables to be built as a module by default for the ARM64 builds. MediaTek DRAMC driver provides cross-platform features as below: - API provided to other kernel modules for querying DRAM type, rank count, rank size, channel count and mode register settings. - Sysfs interface used to pass DRAM mode register settings and current DRAM data rate to user-space for MediaTek ecosystem. The API user includes MediaTek External Memory Interface (EMI) and DVFS Resource Control (DVFSRC), which will be sent to mainline later.
