[irqchip: irq/irqchip-next] dt-bindings: qcom,pdc: Add compatible for sc7280
The following commit has been merged into the irq/irqchip-next branch of irqchip: Commit-ID: 5deaa1d7c49151988b0bf919eeea6ad5535a29a2 Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/5deaa1d7c49151988b0bf919eeea6ad5535a29a2 Author:Rajendra Nayak AuthorDate:Mon, 15 Mar 2021 11:29:06 +05:30 Committer: Marc Zyngier CommitterDate: Wed, 07 Apr 2021 13:26:00 +01:00 dt-bindings: qcom,pdc: Add compatible for sc7280 Add the compatible string for sc7280 SoC from Qualcomm Signed-off-by: Rajendra Nayak Reviewed-by: Stephen Boyd Acked-by: Rob Herring Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/1615787946-26474-1-git-send-email-rna...@codeaurora.org --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt index e9afb48..98d89e5 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt @@ -19,6 +19,7 @@ Properties: Value type: Definition: Should contain "qcom,-pdc" and "qcom,pdc" - "qcom,sc7180-pdc": For SC7180 + - "qcom,sc7280-pdc": For SC7280 - "qcom,sdm845-pdc": For SDM845 - "qcom,sdm8250-pdc": For SM8250 - "qcom,sdm8350-pdc": For SM8350
Re: [PATCH 2/2] nvmem: qfprom: Add support for fuse blowing on sc7280
On 3/31/2021 2:49 AM, Doug Anderson wrote:
Hi,
On Wed, Mar 24, 2021 at 10:45 PM Rajendra Nayak wrote:
@@ -111,6 +113,15 @@ static const struct qfprom_soc_compatible_data
sc7180_qfprom = {
.nkeepout = ARRAY_SIZE(sc7180_qfprom_keepout)
};
+static const struct nvmem_keepout sc7280_qfprom_keepout[] = {
+ {.start = 0x128, .end = 0x148},
+ {.start = 0x238, .end = 0x248}
+};
+
+static const struct qfprom_soc_compatible_data sc7280_qfprom = {
+ .keepout = sc7280_qfprom_keepout,
+ .nkeepout = ARRAY_SIZE(sc7280_qfprom_keepout)
+};
/**
nit: blank line between structure and comment?
@@ -187,9 +199,9 @@ static int qfprom_enable_fuse_blowing(const struct
qfprom_priv *priv,
* a rail shared do don't specify a max--regulator constraints
* will handle.
*/
- ret = regulator_set_voltage(priv->vcc, 180, INT_MAX);
+ ret = regulator_set_voltage(priv->vcc, qfprom_blow_uV, INT_MAX);
if (ret) {
- dev_err(priv->dev, "Failed to set 1.8 voltage\n");
+ dev_err(priv->dev, "Failed to set %duV\n", qfprom_blow_uV);
nit: the comment above this block (not in the unified diff)
specifically calls out 1.8V. It'd be nice if you updated the comment
since it's no longer fixed at 1.8V.
@@ -379,6 +399,8 @@ static int qfprom_probe(struct platform_device *pdev)
if (major_version == 7 && minor_version == 8)
priv->soc_data = _7_8_data;
+ if (major_version == 7 && minor_version == 15)
+ priv->soc_data = _7_15_data;
nit: "else if" instead of "if"?
I guess I'm a little late since I think this already got applied, but
all the above are nits. Maybe you could send a follow-up patch to
address them?
Thanks Doug for the review, yes, I'll send a follow-up patch since
Srini already has these pulled in.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH] drivers: nvmem: Fix voltage settings for QTI qfprom-efuse
On 2/5/2021 8:25 PM, Doug Anderson wrote:
Hi,
On Fri, Feb 5, 2021 at 3:29 AM Ravi Kumar Bokka wrote:
QFPROM controller hardware requires 1.8V min for fuse blowing.
So, this change sets the voltage to 1.8V, required to blow the fuse
for qfprom-efuse controller.
To disable fuse blowing, we set the voltage to 0V since this may
be a shared rail and may be able to run at a lower rate when we're
not blowing fuses.
Fixes: 93b4e49f8c86 ("nvmem: qfprom: Add fuse blowing support")
Reported-by: Douglas Anderson
Suggested-by: Douglas Anderson
Signed-off-by: Ravi Kumar Bokka
---
drivers/nvmem/qfprom.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c
index 6cace24..100d69d 100644
--- a/drivers/nvmem/qfprom.c
+++ b/drivers/nvmem/qfprom.c
@@ -127,6 +127,16 @@ static void qfprom_disable_fuse_blowing(const struct
qfprom_priv *priv,
{
int ret;
+ /*
+* This may be a shared rail and may be able to run at a lower rate
+* when we're not blowing fuses. At the moment, the regulator framework
+* applies voltage constraints even on disabled rails, so remove our
+* constraints and allow the rail to be adjusted by other users.
Some year maybe I'll try to fix the regulator framework to not count
voltage constraints for disbled rails, or perhaps have it be optional.
;-) In theory it should be much easier after the patches we already
landed not to count current requests for disabled rails...
+*/
+ ret = regulator_set_voltage(priv->vcc, 0, INT_MAX);
+ if (ret)
+ dev_warn(priv->dev, "Failed to set 0 voltage (ignoring)\n");
+
ret = regulator_disable(priv->vcc);
if (ret)
dev_warn(priv->dev, "Failed to disable regulator
(ignoring)\n");
@@ -172,6 +182,17 @@ static int qfprom_enable_fuse_blowing(const struct
qfprom_priv *priv,
goto err_clk_prepared;
}
+ /*
+* Hardware requires 1.8V min for fuse blowing; this may be
+* a rail shared do don't specify a max--regulator constraints
+* will handle.
+*/
+ ret = regulator_set_voltage(priv->vcc, 180, INT_MAX);
+ if (ret) {
+ dev_err(priv->dev, "Failed to set 1.8 voltage\n");
+ goto err_clk_rate_set;
+ }
+
Looks right to me. Assuming that this works.
Reviewed-by: Douglas Anderson
Srini, any plans to queue this up for merge?
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 2/2] nvmem: qfprom: Add support for fuse blowing on sc7280
Handle the differences across LDO voltage needed for blowing fuses,
and the blow timer value, identified using a minor version of 15
on sc7280.
Signed-off-by: Rajendra Nayak
Signed-off-by: Ravi Kumar Bokka
---
Applies on top of https://lore.kernel.org/patchwork/patch/1376175/
drivers/nvmem/qfprom.c | 27 +--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c
index 100d69d..d6d3f24 100644
--- a/drivers/nvmem/qfprom.c
+++ b/drivers/nvmem/qfprom.c
@@ -45,11 +45,13 @@ MODULE_PARM_DESC(read_raw_data, "Read raw instead of
corrected data");
* @qfprom_blow_timer_value: The timer value of qfprom when doing efuse blow.
* @qfprom_blow_set_freq:The frequency required to set when we start the
* fuse blowing.
+ * @qfprom_blow_uV: LDO voltage to be set when doing efuse blow
*/
struct qfprom_soc_data {
u32 accel_value;
u32 qfprom_blow_timer_value;
u32 qfprom_blow_set_freq;
+ int qfprom_blow_uV;
};
/**
@@ -111,6 +113,15 @@ static const struct qfprom_soc_compatible_data
sc7180_qfprom = {
.nkeepout = ARRAY_SIZE(sc7180_qfprom_keepout)
};
+static const struct nvmem_keepout sc7280_qfprom_keepout[] = {
+ {.start = 0x128, .end = 0x148},
+ {.start = 0x238, .end = 0x248}
+};
+
+static const struct qfprom_soc_compatible_data sc7280_qfprom = {
+ .keepout = sc7280_qfprom_keepout,
+ .nkeepout = ARRAY_SIZE(sc7280_qfprom_keepout)
+};
/**
* qfprom_disable_fuse_blowing() - Undo enabling of fuse blowing.
* @priv: Our driver data.
@@ -168,6 +179,7 @@ static int qfprom_enable_fuse_blowing(const struct
qfprom_priv *priv,
struct qfprom_touched_values *old)
{
int ret;
+ int qfprom_blow_uV = priv->soc_data->qfprom_blow_uV;
ret = clk_prepare_enable(priv->secclk);
if (ret) {
@@ -187,9 +199,9 @@ static int qfprom_enable_fuse_blowing(const struct
qfprom_priv *priv,
* a rail shared do don't specify a max--regulator constraints
* will handle.
*/
- ret = regulator_set_voltage(priv->vcc, 180, INT_MAX);
+ ret = regulator_set_voltage(priv->vcc, qfprom_blow_uV, INT_MAX);
if (ret) {
- dev_err(priv->dev, "Failed to set 1.8 voltage\n");
+ dev_err(priv->dev, "Failed to set %duV\n", qfprom_blow_uV);
goto err_clk_rate_set;
}
@@ -311,6 +323,14 @@ static const struct qfprom_soc_data qfprom_7_8_data = {
.accel_value = 0xD10,
.qfprom_blow_timer_value = 25,
.qfprom_blow_set_freq = 480,
+ .qfprom_blow_uV = 180,
+};
+
+static const struct qfprom_soc_data qfprom_7_15_data = {
+ .accel_value = 0xD08,
+ .qfprom_blow_timer_value = 24,
+ .qfprom_blow_set_freq = 480,
+ .qfprom_blow_uV = 190,
};
static int qfprom_probe(struct platform_device *pdev)
@@ -379,6 +399,8 @@ static int qfprom_probe(struct platform_device *pdev)
if (major_version == 7 && minor_version == 8)
priv->soc_data = _7_8_data;
+ if (major_version == 7 && minor_version == 15)
+ priv->soc_data = _7_15_data;
priv->vcc = devm_regulator_get(>dev, "vcc");
if (IS_ERR(priv->vcc))
@@ -405,6 +427,7 @@ static int qfprom_probe(struct platform_device *pdev)
static const struct of_device_id qfprom_of_match[] = {
{ .compatible = "qcom,qfprom",},
{ .compatible = "qcom,sc7180-qfprom", .data = _qfprom},
+ { .compatible = "qcom,sc7280-qfprom", .data = _qfprom},
{/* sentinel */},
};
MODULE_DEVICE_TABLE(of, qfprom_of_match);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 1/2] dt-bindings: nvmem: Add SoC compatible for sc7280
Document SoC compatible for sc7280 Signed-off-by: Rajendra Nayak --- Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml index 992777c..861b205 100644 --- a/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml +++ b/Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml @@ -24,6 +24,7 @@ properties: - qcom,msm8998-qfprom - qcom,qcs404-qfprom - qcom,sc7180-qfprom + - qcom,sc7280-qfprom - qcom,sdm845-qfprom - const: qcom,qfprom -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH] dt-bindings: watchdog: Add compatible for SC7280 SoC
From: Sai Prakash Ranjan Add compatible for watchdog timer on SC7280 SoC. Signed-off-by: Sai Prakash Ranjan Signed-off-by: Rajendra Nayak Reviewed-by: Stephen Boyd Acked-by: Rob Herring --- This was earlier posted as part of the entire DT series for sc7280 [1] Rest of the patches are now picked, posting this separately so it can be picked up via the WDT tree. [1] https://lore.kernel.org/patchwork/project/lkml/list/?series=488871 Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml index b8e4118..ba60bdf 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml @@ -17,6 +17,7 @@ properties: enum: - qcom,apss-wdt-qcs404 - qcom,apss-wdt-sc7180 + - qcom,apss-wdt-sc7280 - qcom,apss-wdt-sdm845 - qcom,apss-wdt-sdx55 - qcom,apss-wdt-sm8150 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH] dt-bindings: arm-smmu: Add compatible for SC7280 SoC
From: Sai Prakash Ranjan Add the SoC specific compatible for SC7280 implementing arm,mmu-500. Signed-off-by: Sai Prakash Ranjan Signed-off-by: Rajendra Nayak Reviewed-by: Stephen Boyd Acked-by: Rob Herring --- This was earlier posted as part of the entire DT series for sc7280 [1] Rest of the patches are now picked, posting this separately so it can be picked up via the ARM SMMU tree. [1] https://lore.kernel.org/patchwork/project/lkml/list/?series=488871 Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 6ba161d..9d27aa5 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -34,6 +34,7 @@ properties: items: - enum: - qcom,sc7180-smmu-500 + - qcom,sc7280-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sdm845-smmu-500 - qcom,sm8150-smmu-500 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH] dt-bindings: qcom,pdc: Add compatible for sc7280
Add the compatible string for sc7280 SoC from Qualcomm Signed-off-by: Rajendra Nayak Reviewed-by: Stephen Boyd Acked-by: Rob Herring --- This was earlier posted as part of the entire DT series for sc7280 [1] Rest of the patches are now picked, posting this separately so it can be picked up via the IRQ tree. [1] https://lore.kernel.org/patchwork/project/lkml/list/?series=488871 Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt index e9afb48..98d89e5 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt @@ -19,6 +19,7 @@ Properties: Value type: Definition: Should contain "qcom,-pdc" and "qcom,pdc" - "qcom,sc7180-pdc": For SC7180 + - "qcom,sc7280-pdc": For SC7280 - "qcom,sdm845-pdc": For SDM845 - "qcom,sdm8250-pdc": For SM8250 - "qcom,sdm8350-pdc": For SM8350 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v3 02/14] dt-bindings: firmware: scm: Add sc7280 support
Add compatible for sc7280 SoC Signed-off-by: Rajendra Nayak Reviewed-by: Stephen Boyd Acked-by: Rob Herring --- Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index a884955..1edc311 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -20,6 +20,7 @@ Required properties: * "qcom,scm-msm8996" * "qcom,scm-msm8998" * "qcom,scm-sc7180" + * "qcom,scm-sc7280" * "qcom,scm-sdm845" * "qcom,scm-sm8150" * "qcom,scm-sm8250" -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 00/13] Add binding updates and DT files for SC7280 SoC
On 3/11/2021 2:45 PM, Rajendra Nayak wrote: On 3/11/2021 5:43 AM, Bjorn Andersson wrote: On Fri 12 Feb 01:28 CST 2021, Rajendra Nayak wrote: This series includes a few minor binding updates and base device tree files (to boot to shell) for SC7280 SoC and the IDP board using this SoC. The series is dependent on a few driver patches to merge first, for gcc, rpmhcc and pinctrl https://lore.kernel.org/patchwork/project/lkml/list/?series=484517 https://lore.kernel.org/patchwork/project/lkml/list/?series=484489 https://lore.kernel.org/patchwork/patch/1379831/ I'm not able to find v2 of this series, but plenty of patches that depends on its content. Do I somehow miss it, or is it coming? I did post v2 [1], and will post v3 shortly addressing some of Posted a v3 now [1], also re-based on msm/for-next [1] https://lore.kernel.org/patchwork/project/lkml/list/?series=488871 the feedback from Stephen on v2. I was waiting on the rpmh clock fix to come out [2], which addresses the question about the XO clock frequency [3] in DT [1] https://lore.kernel.org/patchwork/project/lkml/list/?series=487403 [2] https://lore.kernel.org/patchwork/patch/1393159/ [3] https://lore.kernel.org/patchwork/patch/1389019/ Regards, Bjorn Maulik Shah (3): arm64: dts: qcom: sc7280: Add RSC and PDC devices arm64: dts: qcom: Add reserved memory for fw arm64: dts: qcom: sc7280: Add cpuidle states Rajendra Nayak (5): dt-bindings: arm: qcom: Document SC7280 SoC and board dt-bindings: firmware: scm: Add SC7280 support arm64: dts: sc7280: Add basic dts/dtsi files for SC7280 soc dt-bindings: qcom,pdc: Add compatible for sc7280 arm64: dts: qcom: SC7280: Add rpmhcc clock controller node Sai Prakash Ranjan (4): dt-bindings: arm-smmu: Add compatible for SC7280 SoC arm64: dts: qcom: sc7280: Add device node for APPS SMMU dt-bindings: watchdog: Add compatible for SC7280 SoC arm64: dts: qcom: sc7280: Add APSS watchdog node satya priya (1): arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280 Documentation/devicetree/bindings/arm/qcom.yaml | 6 + .../devicetree/bindings/firmware/qcom,scm.txt | 1 + .../bindings/interrupt-controller/qcom,pdc.txt | 1 + .../devicetree/bindings/iommu/arm,smmu.yaml | 1 + .../devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 ++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 596 + 8 files changed, 654 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v3 13/14] arm64: dts: qcom: sc7280: Add cpuidle states
From: Maulik Shah
Add cpuidle states for little and big cpus.
The latency values are preliminary placeholders and will be updated
once testing provides the real numbers.
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 78
1 file changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 9c34169..64d4ba1 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -63,6 +63,9 @@
compatible = "arm,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -78,6 +81,9 @@
compatible = "arm,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_100>;
L2_100: l2-cache {
compatible = "cache";
@@ -90,6 +96,9 @@
compatible = "arm,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_200>;
L2_200: l2-cache {
compatible = "cache";
@@ -102,6 +111,9 @@
compatible = "arm,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_300>;
L2_300: l2-cache {
compatible = "cache";
@@ -114,6 +126,9 @@
compatible = "arm,kryo";
reg = <0x0 0x400>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_400>;
L2_400: l2-cache {
compatible = "cache";
@@ -126,6 +141,9 @@
compatible = "arm,kryo";
reg = <0x0 0x500>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_500>;
L2_500: l2-cache {
compatible = "cache";
@@ -138,6 +156,9 @@
compatible = "arm,kryo";
reg = <0x0 0x600>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_600>;
L2_600: l2-cache {
compatible = "cache";
@@ -150,12 +171,69 @@
compatible = "arm,kryo";
reg = <0x0 0x700>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_700>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <_0>;
};
};
+
+ idle-states {
+ entry-method = "psci";
+
+ LITTLE_CPU_S
[PATCH v3 12/14] arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280
From: satya priya
Add SPMI PMIC arbiter device to communicate with PMICs
attached to SPMI bus.
Signed-off-by: satya priya
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 2759736..9c34169 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -239,6 +239,24 @@
interrupt-controller;
};
+ spmi_bus: spmi@c44 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0 0x0c44 0 0x1100>,
+ <0 0x0c60 0 0x200>,
+ <0 0x0e60 0 0x10>,
+ <0 0x0e70 0 0xa>,
+ <0 0x0c40a000 0 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = < 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
tlmm: pinctrl@f10 {
compatible = "qcom,sc7280-pinctrl";
reg = <0 0x0f10 0 0x30>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v3 06/14] arm64: dts: qcom: SC7280: Add rpmhcc clock controller node
Add rpmhcc clock controller node for SC7280. Also add references to
rpmhcc clocks in gcc.
Signed-off-by: Taniya Das
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 92c38264..baae828 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -6,6 +6,7 @@
*/
#include
+#include
#include
#include
@@ -179,6 +180,14 @@
gcc: clock-controller@10 {
compatible = "qcom,gcc-sc7280";
reg = <0 0x0010 0 0x1f>;
+ clocks = < RPMH_CXO_CLK>,
+< RPMH_CXO_CLK_A>, <_clk>,
+<0>, <0>, <0>, <0>, <0>, <0>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
+ "pcie_0_pipe_clk", "pcie_1_pipe-clk",
+ "ufs_phy_rx_symbol_0_clk",
"ufs_phy_rx_symbol_1_clk",
+ "ufs_phy_tx_symbol_0_clk",
+ "usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@@ -330,6 +339,13 @@
,
,
;
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sc7280-rpmh-clk";
+ clocks = <_board>;
+ clock-names = "xo";
+ #clock-cells = <1>;
+ };
};
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v3 14/14] arm64: dts: qcom: sc7280: Add rpmh power-domain node
Add the DT node for the rpmhpd power controller on SC7280 SoCs.
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 47
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 64d4ba1..39cf0be 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
/ {
@@ -542,6 +543,52 @@
,
;
+ rpmhpd: power-controller {
+ compatible = "qcom,sc7280-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp1 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_low_svs: opp2 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_svs: opp3 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_svs_l1: opp4 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_svs_l2: opp5 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_nom: opp6 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_nom_l1: opp7 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_turbo: opp8 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_turbo_l1: opp9 {
+ opp-level =
;
+ };
+ };
+ };
+
rpmhcc: clock-controller {
compatible = "qcom,sc7280-rpmh-clk";
clocks = <_board>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v3 10/14] dt-bindings: watchdog: Add compatible for SC7280 SoC
From: Sai Prakash Ranjan Add compatible for watchdog timer on SC7280 SoC. Signed-off-by: Sai Prakash Ranjan Signed-off-by: Rajendra Nayak Reviewed-by: Stephen Boyd Acked-by: Rob Herring --- Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml index b8e4118..ba60bdf 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml @@ -17,6 +17,7 @@ properties: enum: - qcom,apss-wdt-qcs404 - qcom,apss-wdt-sc7180 + - qcom,apss-wdt-sc7280 - qcom,apss-wdt-sdm845 - qcom,apss-wdt-sdx55 - qcom,apss-wdt-sm8150 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v3 09/14] arm64: dts: qcom: Add reserved memory for fw
From: Maulik Shah
Add fw reserved memory area for CPUCP (CPUSS control
processor) and AOP (Always ON processor)
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index d72f507..daac303 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -37,11 +37,21 @@
#size-cells = <2>;
ranges;
+ aop_mem: memory@8080 {
+ reg = <0x0 0x8080 0x0 0x6>;
+ no-map;
+ };
+
aop_cmd_db_mem: memory@8086 {
reg = <0x0 0x8086 0x0 0x2>;
compatible = "qcom,cmd-db";
no-map;
};
+
+ cpucp_mem: memory@80b0 {
+ no-map;
+ reg = <0x0 0x80b0 0x0 0x10>;
+ };
};
cpus {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v3 11/14] arm64: dts: qcom: sc7280: Add APSS watchdog node
From: Sai Prakash Ranjan
Add APSS (Application Processor Subsystem) watchdog
DT node for SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index daac303..2759736 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -365,6 +365,13 @@
};
};
+ watchdog@17c1 {
+ compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
+ reg = <0 0x17c1 0 0x1000>;
+ clocks = <_clk>;
+ interrupts = ;
+ };
+
timer@17c2 {
#address-cells = <2>;
#size-cells = <2>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v3 08/14] arm64: dts: qcom: sc7280: Add device node for APPS SMMU
From: Sai Prakash Ranjan
Adding device node for APPS SMMU available on SC7280 chipset.
This is shared among the multiple client devices such as
display, video, usb, mmc and others.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 89
1 file changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index baae828..d72f507 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -246,6 +246,95 @@
};
};
+ apps_smmu: iommu@1500 {
+ compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
+ reg = <0 0x1500 0 0x10>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ dma-coherent;
+ interrupts = ,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+;
+ };
+
intc: interrupt-controller@17a0 {
compatible = "arm,gic-v3";
#address-cells = <2>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v3 03/14] arm64: dts: sc7280: Add basic dts/dtsi files for sc7280 soc
Add initial device tree support for the sc7280 SoC and the IDP
boards based on this SoC
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 +
arch/arm64/boot/dts/qcom/sc7280.dtsi| 299
3 files changed, 347 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile
b/arch/arm64/boot/dts/qcom/Makefile
index cf1128c..22dadd2 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sc7180-trogdor-pompom-r2-lte.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sc7180-trogdor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sc7180-trogdor-r1-lte.dtb
+dtb-$(CONFIG_ARCH_QCOM)+= sc7280-idp.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sdm630-sony-xperia-ganges-kirin.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sdm630-sony-xperia-nile-discovery.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sdm630-sony-xperia-nile-pioneer.dtb
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
new file mode 100644
index 000..950ecb2
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * sc7280 IDP board device tree source
+ *
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sc7280.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. sc7280 IDP platform";
+ compatible = "qcom,sc7280-idp", "qcom,sc7280";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+_id_0 {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+/* PINCTRL - additions to nodes defined in sc7280.dtsi */
+
+_uart5_default {
+ tx {
+ pins = "gpio46";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx {
+ pins = "gpio47";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
new file mode 100644
index 000..69adf73
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * sc7280 SoC device tree source
+ *
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+
+/ {
+ interrupt-parent = <>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <7680>;
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <_100>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x200>;
+ enable-method = "p
[PATCH v3 07/14] dt-bindings: arm-smmu: Add compatible for SC7280 SoC
From: Sai Prakash Ranjan Add the SoC specific compatible for SC7280 implementing arm,mmu-500. Signed-off-by: Sai Prakash Ranjan Signed-off-by: Rajendra Nayak Reviewed-by: Stephen Boyd Acked-by: Rob Herring --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 6ba161d..9d27aa5 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -34,6 +34,7 @@ properties: items: - enum: - qcom,sc7180-smmu-500 + - qcom,sc7280-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sdm845-smmu-500 - qcom,sm8150-smmu-500 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v3 05/14] arm64: dts: qcom: sc7280: Add RSC and PDC devices
From: Maulik Shah
Add PDC interrupt controller along with apps RSC device.
Also add reserved memory for command_db.
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 44
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 69adf73..92c38264 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -7,6 +7,7 @@
#include
#include
+#include
/ {
interrupt-parent = <>;
@@ -30,6 +31,18 @@
};
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ aop_cmd_db_mem: memory@8086 {
+ reg = <0x0 0x8086 0x0 0x2>;
+ compatible = "qcom,cmd-db";
+ no-map;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -194,6 +207,19 @@
};
};
+ pdc: interrupt-controller@b22 {
+ compatible = "qcom,sc7280-pdc", "qcom,pdc";
+ reg = <0 0x0b22 0 0x3>;
+ qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
+ <55 306 4>, <59 312 3>, <62 374 2>,
+ <64 434 2>, <66 438 3>, <69 86 1>,
+ <70 520 54>, <124 609 31>, <155 63 1>,
+ <156 716 12>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <>;
+ interrupt-controller;
+ };
+
tlmm: pinctrl@f10 {
compatible = "qcom,sc7280-pinctrl";
reg = <0 0x0f10 0 0x30>;
@@ -203,6 +229,7 @@
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = < 0 0 175>;
+ wakeup-parent = <>;
qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
@@ -287,6 +314,23 @@
status = "disabled";
};
};
+
+ apps_rsc: rsc@1820 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0 0x1820 0 0x1>,
+ <0 0x1821 0 0x1>,
+ <0 0x1822 0 0x1>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = ,
+,
+;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = ,
+ ,
+ ,
+ ;
+ };
};
timer {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v3 04/14] dt-bindings: qcom,pdc: Add compatible for sc7280
Add the compatible string for sc7180 SoC from Qualcomm Signed-off-by: Rajendra Nayak Reviewed-by: Stephen Boyd Acked-by: Rob Herring --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt index e9afb48..98d89e5 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt @@ -19,6 +19,7 @@ Properties: Value type: Definition: Should contain "qcom,-pdc" and "qcom,pdc" - "qcom,sc7180-pdc": For SC7180 + - "qcom,sc7280-pdc": For SC7280 - "qcom,sdm845-pdc": For SDM845 - "qcom,sdm8250-pdc": For SM8250 - "qcom,sdm8350-pdc": For SM8350 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v3 00/14] Add binding updates and DT files for SC7280 SoC
This series includes a few minor binding updates and base device tree files (to boot to shell) for SC7280 SoC and the IDP board using this SoC. Maulik Shah (3): arm64: dts: qcom: sc7280: Add RSC and PDC devices arm64: dts: qcom: Add reserved memory for fw arm64: dts: qcom: sc7280: Add cpuidle states Rajendra Nayak (6): dt-bindings: arm: qcom: Document sc7280 SoC and board dt-bindings: firmware: scm: Add sc7280 support arm64: dts: sc7280: Add basic dts/dtsi files for sc7280 soc dt-bindings: qcom,pdc: Add compatible for sc7280 arm64: dts: qcom: SC7280: Add rpmhcc clock controller node arm64: dts: qcom: sc7280: Add rpmh power-domain node Sai Prakash Ranjan (4): dt-bindings: arm-smmu: Add compatible for SC7280 SoC arm64: dts: qcom: sc7280: Add device node for APPS SMMU dt-bindings: watchdog: Add compatible for SC7280 SoC arm64: dts: qcom: sc7280: Add APSS watchdog node satya priya (1): arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280 Documentation/devicetree/bindings/arm/qcom.yaml| 6 + .../devicetree/bindings/firmware/qcom,scm.txt | 1 + .../bindings/interrupt-controller/qcom,pdc.txt | 1 + .../devicetree/bindings/iommu/arm,smmu.yaml| 1 + .../devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc7280-idp.dts| 47 ++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 608 + 8 files changed, 666 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v3 01/14] dt-bindings: arm: qcom: Document sc7280 SoC and board
Document the sc7280 SoC and the IDP board bindings Signed-off-by: Rajendra Nayak Reviewed-by: Stephen Boyd Acked-by: Rob Herring --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index dc87238..ad97ef4 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -37,6 +37,7 @@ description: | msm8994 msm8996 sc7180 +sc7280 sdm630 sdm660 sdm845 @@ -176,6 +177,11 @@ properties: - items: - enum: + - qcom,sc7280-idp + - const: qcom,sc7280 + + - items: + - enum: - xiaomi,lavender - const: qcom,sdm660 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v2 03/14] arm64: dts: sc7280: Add basic dts/dtsi files for sc7280 soc
On 3/4/2021 5:37 AM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2021-03-03 04:17:47)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
new file mode 100644
index 000..4a56d9c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * sc7280 SoC device tree source
+ *
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+
+/ {
+ interrupt-parent = <>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <7680>;
If this is the correct frequency I think we need to update the rpmh clk
driver to use the correct divider? Right now I think it is a 2 when it
should be 4?
Looks like this is fixed now [1]
[1] https://lore.kernel.org/patchwork/patch/1393159/
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 00/13] Add binding updates and DT files for SC7280 SoC
On 3/11/2021 5:43 AM, Bjorn Andersson wrote: On Fri 12 Feb 01:28 CST 2021, Rajendra Nayak wrote: This series includes a few minor binding updates and base device tree files (to boot to shell) for SC7280 SoC and the IDP board using this SoC. The series is dependent on a few driver patches to merge first, for gcc, rpmhcc and pinctrl https://lore.kernel.org/patchwork/project/lkml/list/?series=484517 https://lore.kernel.org/patchwork/project/lkml/list/?series=484489 https://lore.kernel.org/patchwork/patch/1379831/ I'm not able to find v2 of this series, but plenty of patches that depends on its content. Do I somehow miss it, or is it coming? I did post v2 [1], and will post v3 shortly addressing some of the feedback from Stephen on v2. I was waiting on the rpmh clock fix to come out [2], which addresses the question about the XO clock frequency [3] in DT [1] https://lore.kernel.org/patchwork/project/lkml/list/?series=487403 [2] https://lore.kernel.org/patchwork/patch/1393159/ [3] https://lore.kernel.org/patchwork/patch/1389019/ Regards, Bjorn Maulik Shah (3): arm64: dts: qcom: sc7280: Add RSC and PDC devices arm64: dts: qcom: Add reserved memory for fw arm64: dts: qcom: sc7280: Add cpuidle states Rajendra Nayak (5): dt-bindings: arm: qcom: Document SC7280 SoC and board dt-bindings: firmware: scm: Add SC7280 support arm64: dts: sc7280: Add basic dts/dtsi files for SC7280 soc dt-bindings: qcom,pdc: Add compatible for sc7280 arm64: dts: qcom: SC7280: Add rpmhcc clock controller node Sai Prakash Ranjan (4): dt-bindings: arm-smmu: Add compatible for SC7280 SoC arm64: dts: qcom: sc7280: Add device node for APPS SMMU dt-bindings: watchdog: Add compatible for SC7280 SoC arm64: dts: qcom: sc7280: Add APSS watchdog node satya priya (1): arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280 Documentation/devicetree/bindings/arm/qcom.yaml| 6 + .../devicetree/bindings/firmware/qcom,scm.txt | 1 + .../bindings/interrupt-controller/qcom,pdc.txt | 1 + .../devicetree/bindings/iommu/arm,smmu.yaml| 1 + .../devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc7280-idp.dts| 47 ++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 596 + 8 files changed, 654 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 04/13] dt-bindings: qcom,pdc: Add compatible for sc7280
On 2/23/2021 1:09 PM, Stephen Boyd wrote: Quoting Rajendra Nayak (2021-02-11 23:28:41) Add the compatible string for sc7180 SoC from Qualcomm Signed-off-by: Rajendra Nayak --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 + Is this being YAML-ified at some point? forgot to mention, Maulik already has a patch for it which he plans to post soon. -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v2 13/14] arm64: dts: qcom: sc7280: Add cpuidle states
On 3/4/2021 5:43 AM, Stephen Boyd wrote: Quoting Rajendra Nayak (2021-03-03 04:17:57) From: Maulik Shah Add cpuidle states for little and big cpus. Please also say "The latency values are preliminary placeholders and will be updated once testing provides the real numbers". will do when I respin, thanks. Signed-off-by: Maulik Shah Signed-off-by: Rajendra Nayak --- With that commit text update Reviewed-by: Stephen Boyd -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v2 12/14] arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280
On 3/4/2021 5:42 AM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2021-03-03 04:17:56)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index fe4fdb9..aa6f847 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -239,6 +239,25 @@
interrupt-controller;
};
+ spmi_bus: spmi@c44 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0 0x0c44 0 0x1100>,
+ <0 0x0c60 0 0x200>,
+ <0 0x0e60 0 0x10>,
+ <0 0x0e70 0 0xa>,
+ <0 0x0c40a000 0 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = < 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
I see the binding says these should be 2 instead of 1 but I suspect that
is incorrect.
yeah looks like the bindings need to be fixed
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
Is cell-index used? Please remove as I don't see it used anywhere and
not in the binding.
I'll drop it. thanks
+ };
+
tlmm: pinctrl@f10 {
compatible = "qcom,sc7280-pinctrl";
reg = <0 0x0f10 0 0x100>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v2 05/14] arm64: dts: qcom: sc7280: Add RSC and PDC devices
On 3/4/2021 5:34 AM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2021-03-03 04:17:49)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 4a56d9c..21c2399 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -30,6 +31,18 @@
};
};
+ reserved_memory: reserved-memory {
Do we plan to use this label at any point? I'd prefer we remove this
until it becomes useful.
sure, i'll drop it
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ aop_cmd_db_mem: memory@8086 {
+ reg = <0x0 0x8086 0x0 0x2>;
+ compatible = "qcom,cmd-db";
+ no-map;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -203,6 +229,7 @@
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = < 0 0 175>;
+ wakeup-parent = <>;
qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
@@ -287,6 +314,23 @@
status = "disabled";
};
};
+
+ apps_rsc: rsc@1820 {
Any better name than 'rsc'? Maybe 'power-controller'?
hmm, Maulik, any thoughts? This would perhaps need the bindings docs
to be updated as well (and maybe the existing platform DTs using rsc too)
+ compatible = "qcom,rpmh-rsc";
+ reg = <0 0x1820 0 0x1>,
+ <0 0x1821 0 0x1>,
+ <0 0x1822 0 0x1>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = ,
+,
+;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = ,
+ ,
+ ,
+ ;
+ };
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v2 14/14] arm64: dts: qcom: sc7280: Add rpmh power-domain node
Add the DT node for the rpmhpd power controller on SC7280 SoCs.
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 47
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 06fbf2e..8af6d77 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
/ {
@@ -543,6 +544,52 @@
,
;
+ rpmhpd: power-controller {
+ compatible = "qcom,sc7280-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp1 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_low_svs: opp2 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_svs: opp3 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_svs_l1: opp4 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_svs_l2: opp5 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_nom: opp6 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_nom_l1: opp7 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_turbo: opp8 {
+ opp-level =
;
+ };
+
+ rpmhpd_opp_turbo_l1: opp9 {
+ opp-level =
;
+ };
+ };
+ };
+
rpmhcc: clock-controller {
compatible = "qcom,sc7280-rpmh-clk";
clocks = <_board>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v2 13/14] arm64: dts: qcom: sc7280: Add cpuidle states
From: Maulik Shah
Add cpuidle states for little and big cpus.
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 78
1 file changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index aa6f847..06fbf2e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -63,6 +63,9 @@
compatible = "arm,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -78,6 +81,9 @@
compatible = "arm,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_100>;
L2_100: l2-cache {
compatible = "cache";
@@ -90,6 +96,9 @@
compatible = "arm,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_200>;
L2_200: l2-cache {
compatible = "cache";
@@ -102,6 +111,9 @@
compatible = "arm,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_300>;
L2_300: l2-cache {
compatible = "cache";
@@ -114,6 +126,9 @@
compatible = "arm,kryo";
reg = <0x0 0x400>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_400>;
L2_400: l2-cache {
compatible = "cache";
@@ -126,6 +141,9 @@
compatible = "arm,kryo";
reg = <0x0 0x500>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_500>;
L2_500: l2-cache {
compatible = "cache";
@@ -138,6 +156,9 @@
compatible = "arm,kryo";
reg = <0x0 0x600>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_600>;
L2_600: l2-cache {
compatible = "cache";
@@ -150,12 +171,69 @@
compatible = "arm,kryo";
reg = <0x0 0x700>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_700>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <_0>;
};
};
+
+ idle-states {
+ entry-method = "psci";
+
+ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state
[PATCH v2 10/14] dt-bindings: watchdog: Add compatible for SC7280 SoC
From: Sai Prakash Ranjan Add compatible for watchdog timer on SC7280 SoC. Signed-off-by: Sai Prakash Ranjan Signed-off-by: Rajendra Nayak Reviewed-by: Stephen Boyd --- Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml index b8e4118..ba60bdf 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml @@ -17,6 +17,7 @@ properties: enum: - qcom,apss-wdt-qcs404 - qcom,apss-wdt-sc7180 + - qcom,apss-wdt-sc7280 - qcom,apss-wdt-sdm845 - qcom,apss-wdt-sdx55 - qcom,apss-wdt-sm8150 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v2 08/14] arm64: dts: qcom: sc7280: Add device node for APPS SMMU
From: Sai Prakash Ranjan
Adding device node for APPS SMMU available on SC7280 chipset.
This is shared among the multiple client devices such as
display, video, usb, mmc and others.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 89
1 file changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 9bfa1e06..2d1209f 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -246,6 +246,95 @@
};
};
+ apps_smmu: iommu@1500 {
+ compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
+ reg = <0 0x1500 0 0x10>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ dma-coherent;
+ interrupts = ,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+;
+ };
+
intc: interrupt-controller@17a0 {
compatible = "arm,gic-v3";
#address-cells = <2>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v2 11/14] arm64: dts: qcom: sc7280: Add APSS watchdog node
From: Sai Prakash Ranjan
Add APSS (Application Processor Subsystem) watchdog
DT node for SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index b4c522a..fe4fdb9 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -365,6 +365,13 @@
};
};
+ watchdog@17c1 {
+ compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
+ reg = <0 0x17c1 0 0x1000>;
+ clocks = <_clk>;
+ interrupts = ;
+ };
+
timer@17c2 {
#address-cells = <2>;
#size-cells = <2>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v2 07/14] dt-bindings: arm-smmu: Add compatible for SC7280 SoC
From: Sai Prakash Ranjan Add the SoC specific compatible for SC7280 implementing arm,mmu-500. Signed-off-by: Sai Prakash Ranjan Signed-off-by: Rajendra Nayak Reviewed-by: Stephen Boyd --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 6ba161d..9d27aa5 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -34,6 +34,7 @@ properties: items: - enum: - qcom,sc7180-smmu-500 + - qcom,sc7280-smmu-500 - qcom,sc8180x-smmu-500 - qcom,sdm845-smmu-500 - qcom,sm8150-smmu-500 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v2 12/14] arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280
From: satya priya
Add SPMI PMIC arbiter device to communicate with PMICs
attached to SPMI bus.
Signed-off-by: satya priya
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index fe4fdb9..aa6f847 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -239,6 +239,25 @@
interrupt-controller;
};
+ spmi_bus: spmi@c44 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0 0x0c44 0 0x1100>,
+ <0 0x0c60 0 0x200>,
+ <0 0x0e60 0 0x10>,
+ <0 0x0e70 0 0xa>,
+ <0 0x0c40a000 0 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = < 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
tlmm: pinctrl@f10 {
compatible = "qcom,sc7280-pinctrl";
reg = <0 0x0f10 0 0x100>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v2 09/14] arm64: dts: qcom: Add reserved memory for fw
From: Maulik Shah
Add fw reserved memory area for CPUCP (CPUSS control
processor) and AOP (Always ON processor)
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 2d1209f..b4c522a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -37,11 +37,21 @@
#size-cells = <2>;
ranges;
+ aop_mem: memory@8080 {
+ reg = <0x0 0x8080 0x0 0x6>;
+ no-map;
+ };
+
aop_cmd_db_mem: memory@8086 {
reg = <0x0 0x8086 0x0 0x2>;
compatible = "qcom,cmd-db";
no-map;
};
+
+ cpucp_mem: memory@80b0 {
+ no-map;
+ reg = <0x0 0x80b0 0x0 0x10>;
+ };
};
cpus {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v2 05/14] arm64: dts: qcom: sc7280: Add RSC and PDC devices
From: Maulik Shah
Add PDC interrupt controller along with apps RSC device.
Also add reserved memory for command_db.
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 44
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 4a56d9c..21c2399 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -7,6 +7,7 @@
#include
#include
+#include
/ {
interrupt-parent = <>;
@@ -30,6 +31,18 @@
};
};
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ aop_cmd_db_mem: memory@8086 {
+ reg = <0x0 0x8086 0x0 0x2>;
+ compatible = "qcom,cmd-db";
+ no-map;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -194,6 +207,19 @@
};
};
+ pdc: interrupt-controller@b22 {
+ compatible = "qcom,sc7280-pdc", "qcom,pdc";
+ reg = <0 0x0b22 0 0x3>;
+ qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
+ <55 306 4>, <59 312 3>, <62 374 2>,
+ <64 434 2>, <66 438 3>, <69 86 1>,
+ <70 520 54>, <124 609 31>, <155 63 1>,
+ <156 716 12>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <>;
+ interrupt-controller;
+ };
+
tlmm: pinctrl@f10 {
compatible = "qcom,sc7280-pinctrl";
reg = <0 0x0f10 0 0x100>;
@@ -203,6 +229,7 @@
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = < 0 0 175>;
+ wakeup-parent = <>;
qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
@@ -287,6 +314,23 @@
status = "disabled";
};
};
+
+ apps_rsc: rsc@1820 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0 0x1820 0 0x1>,
+ <0 0x1821 0 0x1>,
+ <0 0x1822 0 0x1>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = ,
+,
+;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = ,
+ ,
+ ,
+ ;
+ };
};
timer {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v2 06/14] arm64: dts: qcom: SC7280: Add rpmhcc clock controller node
Add rpmhcc clock controller node for SC7280. Also add references to
rpmhcc clocks in gcc.
Signed-off-by: Taniya Das
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 21c2399..9bfa1e06 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -6,6 +6,7 @@
*/
#include
+#include
#include
#include
@@ -179,6 +180,14 @@
gcc: clock-controller@10 {
compatible = "qcom,gcc-sc7280";
reg = <0 0x0010 0 0x1f>;
+ clocks = < RPMH_CXO_CLK>,
+< RPMH_CXO_CLK_A>, <_clk>,
+<0>, <0>, <0>, <0>, <0>, <0>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
+ "pcie_0_pipe_clk", "pcie_1_pipe-clk",
+ "ufs_phy_rx_symbol_0_clk",
"ufs_phy_rx_symbol_1_clk",
+ "ufs_phy_tx_symbol_0_clk",
+ "usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@@ -330,6 +339,13 @@
,
,
;
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sc7280-rpmh-clk";
+ clocks = <_board>;
+ clock-names = "xo";
+ #clock-cells = <1>;
+ };
};
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v2 04/14] dt-bindings: qcom,pdc: Add compatible for sc7280
Add the compatible string for sc7180 SoC from Qualcomm Signed-off-by: Rajendra Nayak Reviewed-by: Stephen Boyd --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt index e9afb48..98d89e5 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt @@ -19,6 +19,7 @@ Properties: Value type: Definition: Should contain "qcom,-pdc" and "qcom,pdc" - "qcom,sc7180-pdc": For SC7180 + - "qcom,sc7280-pdc": For SC7280 - "qcom,sdm845-pdc": For SDM845 - "qcom,sdm8250-pdc": For SM8250 - "qcom,sdm8350-pdc": For SM8350 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v2 02/14] dt-bindings: firmware: scm: Add sc7280 support
Add compatible for sc7280 SoC Signed-off-by: Rajendra Nayak Reviewed-by: Stephen Boyd --- Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index a884955..1edc311 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -20,6 +20,7 @@ Required properties: * "qcom,scm-msm8996" * "qcom,scm-msm8998" * "qcom,scm-sc7180" + * "qcom,scm-sc7280" * "qcom,scm-sdm845" * "qcom,scm-sm8150" * "qcom,scm-sm8250" -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v2 01/14] dt-bindings: arm: qcom: Document sc7280 SoC and board
Document the sc7280 SoC and the IDP board bindings Signed-off-by: Rajendra Nayak Reviewed-by: Stephen Boyd --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 174134f..847f102 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -37,6 +37,7 @@ description: | msm8994 msm8996 sc7180 +sc7280 sdm630 sdm660 sdm845 @@ -166,6 +167,11 @@ properties: - items: - enum: + - qcom,sc7280-idp + - const: qcom,sc7280 + + - items: + - enum: - xiaomi,lavender - const: qcom,sdm660 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v2 03/14] arm64: dts: sc7280: Add basic dts/dtsi files for sc7280 soc
Add initial device tree support for the sc7280 SoC and the IDP
boards based on this SoC
Signed-off-by: Rajendra Nayak
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 +
arch/arm64/boot/dts/qcom/sc7280.dtsi| 299
3 files changed, 347 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile
b/arch/arm64/boot/dts/qcom/Makefile
index 549a7a2..54cd8ea 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=
sc7180-trogdor-lazor-r3-kb.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sc7180-trogdor-lazor-r3-lte.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sc7180-trogdor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sc7180-trogdor-r1-lte.dtb
+dtb-$(CONFIG_ARCH_QCOM)+= sc7280-idp.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sdm630-sony-xperia-ganges-kirin.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sdm630-sony-xperia-nile-discovery.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sdm630-sony-xperia-nile-pioneer.dtb
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
new file mode 100644
index 000..950ecb2
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * sc7280 IDP board device tree source
+ *
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sc7280.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. sc7280 IDP platform";
+ compatible = "qcom,sc7280-idp", "qcom,sc7280";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+_id_0 {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+/* PINCTRL - additions to nodes defined in sc7280.dtsi */
+
+_uart5_default {
+ tx {
+ pins = "gpio46";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx {
+ pins = "gpio47";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
new file mode 100644
index 000..4a56d9c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * sc7280 SoC device tree source
+ *
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+
+/ {
+ interrupt-parent = <>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <7680>;
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <_100>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x200>;
+ enable-method = "p
[PATCH v2 00/14] Add binding updates and DT files for SC7280 SoC
This series includes a few minor binding updates and base device tree files (to boot to shell) for SC7280 SoC and the IDP board using this SoC. Maulik Shah (3): arm64: dts: qcom: sc7280: Add RSC and PDC devices arm64: dts: qcom: Add reserved memory for fw arm64: dts: qcom: sc7280: Add cpuidle states Rajendra Nayak (6): dt-bindings: arm: qcom: Document sc7280 SoC and board dt-bindings: firmware: scm: Add sc7280 support arm64: dts: sc7280: Add basic dts/dtsi files for sc7280 soc dt-bindings: qcom,pdc: Add compatible for sc7280 arm64: dts: qcom: SC7280: Add rpmhcc clock controller node arm64: dts: qcom: sc7280: Add rpmh power-domain node Sai Prakash Ranjan (4): dt-bindings: arm-smmu: Add compatible for SC7280 SoC arm64: dts: qcom: sc7280: Add device node for APPS SMMU dt-bindings: watchdog: Add compatible for SC7280 SoC arm64: dts: qcom: sc7280: Add APSS watchdog node satya priya (1): arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280 Documentation/devicetree/bindings/arm/qcom.yaml| 6 + .../devicetree/bindings/firmware/qcom,scm.txt | 1 + .../bindings/interrupt-controller/qcom,pdc.txt | 1 + .../devicetree/bindings/iommu/arm,smmu.yaml| 1 + .../devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc7280-idp.dts| 47 ++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 609 + 8 files changed, 667 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 2/2] soc: qcom: rpmhpd: Add sc7280 powerdomains
Add the power domains exposed by RPMH in the Qualcomm Technologies Inc
sc7280 platform
Signed-off-by: Rajendra Nayak
---
drivers/soc/qcom/rpmhpd.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c
index 7ce0635..2a0c55f 100644
--- a/drivers/soc/qcom/rpmhpd.c
+++ b/drivers/soc/qcom/rpmhpd.c
@@ -217,8 +217,27 @@ static const struct rpmhpd_desc sc7180_desc = {
.num_pds = ARRAY_SIZE(sc7180_rpmhpds),
};
+/* SC7280 RPMH powerdomains */
+static struct rpmhpd *sc7280_rpmhpds[] = {
+ [SC7280_CX] = _cx,
+ [SC7280_CX_AO] = _cx_ao,
+ [SC7280_EBI] = _ebi,
+ [SC7280_GFX] = _gfx,
+ [SC7280_MX] = _mx,
+ [SC7280_MX_AO] = _mx_ao,
+ [SC7280_LMX] = _lmx,
+ [SC7280_LCX] = _lcx,
+ [SC7280_MSS] = _mss,
+};
+
+static const struct rpmhpd_desc sc7280_desc = {
+ .rpmhpds = sc7280_rpmhpds,
+ .num_pds = ARRAY_SIZE(sc7280_rpmhpds),
+};
+
static const struct of_device_id rpmhpd_match_table[] = {
{ .compatible = "qcom,sc7180-rpmhpd", .data = _desc },
+ { .compatible = "qcom,sc7280-rpmhpd", .data = _desc },
{ .compatible = "qcom,sdm845-rpmhpd", .data = _desc },
{ .compatible = "qcom,sdx55-rpmhpd", .data = _desc},
{ .compatible = "qcom,sm8150-rpmhpd", .data = _desc },
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 1/2] dt-bindings: power: rpmpd: Add sc7280 to rpmpd binding
Add compatible and constants for the power domains exposed by the RPMH in the Qualcomm Technologies Inc sc7280 platform. Signed-off-by: Rajendra Nayak --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom-rpmpd.h | 11 +++ 2 files changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 1ea21ac..e2179a6 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -25,6 +25,7 @@ properties: - qcom,qcs404-rpmpd - qcom,sdm660-rpmpd - qcom,sc7180-rpmhpd + - qcom,sc7280-rpmhpd - qcom,sdm845-rpmhpd - qcom,sdx55-rpmhpd - qcom,sm8150-rpmhpd diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index d711e25..0679fd1 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -55,6 +55,17 @@ #define SC7180_LCX 6 #define SC7180_MSS 7 +/* SC7280 Power Domain Indexes */ +#define SC7280_CX 0 +#define SC7280_CX_AO 1 +#define SC7280_EBI 2 +#define SC7280_GFX 3 +#define SC7280_MX 4 +#define SC7280_MX_AO 5 +#define SC7280_LMX 6 +#define SC7280_LCX 7 +#define SC7280_MSS 8 + /* SDM845 Power Domain performance levels */ #define RPMH_REGULATOR_LEVEL_RETENTION 16 #define RPMH_REGULATOR_LEVEL_MIN_SVS 48 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 1/2] pinctrl: qcom: sc7280: Fix SDC_QDSD_PINGROUP and UFS_RESET offsets
The offsets for SDC_QDSD_PINGROUP and UFS_RESET were off by 0x10
due to an issue in the scripts generating the data.
Fixes: ecb454594c43: ("pinctrl: qcom: Add sc7280 pinctrl driver")
Reported-by: Veerabhadrarao Badiganti
Signed-off-by: Rajendra Nayak
---
drivers/pinctrl/qcom/pinctrl-sc7280.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c
b/drivers/pinctrl/qcom/pinctrl-sc7280.c
index 8daccd5..49c4347 100644
--- a/drivers/pinctrl/qcom/pinctrl-sc7280.c
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c
@@ -1439,14 +1439,14 @@ static const struct msm_pingroup sc7280_groups[] = {
[172] = PINGROUP(172, qdss, _, _, _, _, _, _, _, _),
[173] = PINGROUP(173, qdss, _, _, _, _, _, _, _, _),
[174] = PINGROUP(174, qdss, _, _, _, _, _, _, _, _),
- [175] = UFS_RESET(ufs_reset, 0x1be000),
- [176] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x1b3000, 15, 0),
- [177] = SDC_QDSD_PINGROUP(sdc1_clk, 0x1b3000, 13, 6),
- [178] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x1b3000, 11, 3),
- [179] = SDC_QDSD_PINGROUP(sdc1_data, 0x1b3000, 9, 0),
- [180] = SDC_QDSD_PINGROUP(sdc2_clk, 0x1b4000, 14, 6),
- [181] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x1b4000, 11, 3),
- [182] = SDC_QDSD_PINGROUP(sdc2_data, 0x1b4000, 9, 0),
+ [175] = UFS_RESET(ufs_reset, 0xbe000),
+ [176] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xb3000, 15, 0),
+ [177] = SDC_QDSD_PINGROUP(sdc1_clk, 0xb3000, 13, 6),
+ [178] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xb3000, 11, 3),
+ [179] = SDC_QDSD_PINGROUP(sdc1_data, 0xb3000, 9, 0),
+ [180] = SDC_QDSD_PINGROUP(sdc2_clk, 0xb4000, 14, 6),
+ [181] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xb4000, 11, 3),
+ [182] = SDC_QDSD_PINGROUP(sdc2_data, 0xb4000, 9, 0),
};
static const struct msm_pinctrl_soc_data sc7280_pinctrl = {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 2/2] pinctrl: qcom: sc7280: Fix SDC1_RCLK configurations
Fix SDC1_RCLK configurations which are in a different register so fix the
offset from 0xb3000 to 0xb3004.
Fixes: ecb454594c43: ("pinctrl: qcom: Add sc7280 pinctrl driver")
Reported-by: Veerabhadrarao Badiganti
Signed-off-by: Rajendra Nayak
---
drivers/pinctrl/qcom/pinctrl-sc7280.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c
b/drivers/pinctrl/qcom/pinctrl-sc7280.c
index 49c4347..9d41abf 100644
--- a/drivers/pinctrl/qcom/pinctrl-sc7280.c
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c
@@ -1440,7 +1440,7 @@ static const struct msm_pingroup sc7280_groups[] = {
[173] = PINGROUP(173, qdss, _, _, _, _, _, _, _, _),
[174] = PINGROUP(174, qdss, _, _, _, _, _, _, _, _),
[175] = UFS_RESET(ufs_reset, 0xbe000),
- [176] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xb3000, 15, 0),
+ [176] = SDC_QDSD_PINGROUP(sdc1_rclk, 0xb3004, 0, 6),
[177] = SDC_QDSD_PINGROUP(sdc1_clk, 0xb3000, 13, 6),
[178] = SDC_QDSD_PINGROUP(sdc1_cmd, 0xb3000, 11, 3),
[179] = SDC_QDSD_PINGROUP(sdc1_data, 0xb3000, 9, 0),
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 09/13] arm64: dts: qcom: Add reserved memory for fw
On 2/23/2021 1:15 PM, Stephen Boyd wrote: Quoting Rajendra Nayak (2021-02-11 23:28:46) From: Maulik Shah Add fw reserved memory area for CPUCP and AOP. Does CPUCP stand for CPU Content Protection? AOP is Always On Processor. It would help if the commit text told us what these acronyms were. Thanks, I'll expand the acronyms when I re-post. Signed-off-by: Maulik Shah Signed-off-by: Rajendra Nayak --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++ 1 file changed, 10 insertions(+) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 03/13] arm64: dts: sc7280: Add basic dts/dtsi files for SC7280 soc
On 2/23/2021 1:07 PM, Stephen Boyd wrote:
Quoting Rajendra Nayak (2021-02-11 23:28:40)
Add initial device tree support for the SC7280 SoC and the IDP
boards based on this SoC
Signed-off-by: Rajendra Nayak
---
Reviewed-by: Stephen Boyd
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
new file mode 100644
index 000..428f863
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * sc7280 IDP board device tree source
Is it capitalized or not capitalized for SC?
:) I'll be consistent and make it not capitalized everywhere.
+ *
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sc7280.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SC7280 IDP platform";
Because it is capitalized here.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 10/13] dt-bindings: watchdog: Add compatible for SC7280 SoC
From: Sai Prakash Ranjan Add compatible for watchdog timer on SC7280 SoC. Signed-off-by: Sai Prakash Ranjan Signed-off-by: Rajendra Nayak --- Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml index 8e3760a..b5b1268 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml @@ -17,6 +17,7 @@ properties: enum: - qcom,apss-wdt-qcs404 - qcom,apss-wdt-sc7180 + - qcom,apss-wdt-sc7280 - qcom,apss-wdt-sdm845 - qcom,apss-wdt-sm8150 - qcom,kpss-timer -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 11/13] arm64: dts: qcom: sc7280: Add APSS watchdog node
From: Sai Prakash Ranjan
Add APSS (Application Processor Subsystem) watchdog
DT node for SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index b5b9b6a..ef82d77 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -399,6 +399,13 @@
};
};
+ watchdog@17c1 {
+ compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
+ reg = <0 0x17c1 0 0x1000>;
+ clocks = <_clk>;
+ interrupts = ;
+ };
+
timer@17c2 {
#address-cells = <2>;
#size-cells = <2>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 13/13] arm64: dts: qcom: sc7280: Add cpuidle states
From: Maulik Shah
Add cpuidle states for little and big cpus.
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 78
1 file changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 8f2002b..3b86052 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -99,6 +99,9 @@
compatible = "arm,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -114,6 +117,9 @@
compatible = "arm,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_100>;
L2_100: l2-cache {
compatible = "cache";
@@ -126,6 +132,9 @@
compatible = "arm,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_200>;
L2_200: l2-cache {
compatible = "cache";
@@ -138,6 +147,9 @@
compatible = "arm,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_300>;
L2_300: l2-cache {
compatible = "cache";
@@ -150,6 +162,9 @@
compatible = "arm,kryo";
reg = <0x0 0x400>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_400>;
L2_400: l2-cache {
compatible = "cache";
@@ -162,6 +177,9 @@
compatible = "arm,kryo";
reg = <0x0 0x500>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_500>;
L2_500: l2-cache {
compatible = "cache";
@@ -174,6 +192,9 @@
compatible = "arm,kryo";
reg = <0x0 0x600>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_600>;
L2_600: l2-cache {
compatible = "cache";
@@ -186,12 +207,69 @@
compatible = "arm,kryo";
reg = <0x0 0x700>;
enable-method = "psci";
+ cpu-idle-states = <_CPU_SLEEP_0
+ _CPU_SLEEP_1
+ _SLEEP_0>;
next-level-cache = <_700>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <_0>;
};
};
+
+ idle-states {
+ entry-method = "psci";
+
+ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state
[PATCH 04/13] dt-bindings: qcom,pdc: Add compatible for sc7280
Add the compatible string for sc7180 SoC from Qualcomm Signed-off-by: Rajendra Nayak --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt index 1df2939..9345c2e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt @@ -19,6 +19,7 @@ Properties: Value type: Definition: Should contain "qcom,-pdc" and "qcom,pdc" - "qcom,sc7180-pdc": For SC7180 + - "qcom,sc7280-pdc": For SC7280 - "qcom,sdm845-pdc": For SDM845 - reg: -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 08/13] arm64: dts: qcom: sc7280: Add device node for APPS SMMU
From: Sai Prakash Ranjan
Adding device node for APPS SMMU available on SC7280 chipset.
This is shared among the multiple client devices such as
display, video, usb, mmc and others.
Signed-off-by: Sai Prakash Ranjan
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 89
1 file changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 10851e7..f71ba21 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -280,6 +280,95 @@
};
};
+ apps_smmu: iommu@1500 {
+ compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
+ reg = <0 0x1500 0 0x10>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ dma-coherent;
+ interrupts = ,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+;
+ };
+
intc: interrupt-controller@17a0 {
compatible = "arm,gic-v3";
#address-cells = <2>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 12/13] arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280
From: satya priya
Add SPMI PMIC arbiter device to communicate with PMICs
attached to SPMI bus.
Signed-off-by: satya priya
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index ef82d77..8f2002b 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -273,6 +273,25 @@
interrupt-controller;
};
+ spmi_bus: qcom,spmi@c44 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0 0x0c44 0 0x1100>,
+ <0 0x0c60 0 0x200>,
+ <0 0x0e60 0 0x10>,
+ <0 0x0e70 0 0xa>,
+ <0 0x0c40a000 0 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = < 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
tlmm: pinctrl@f10 {
compatible = "qcom,sc7280-pinctrl";
reg = <0 0xf10 0 0x100>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 09/13] arm64: dts: qcom: Add reserved memory for fw
From: Maulik Shah
Add fw reserved memory area for CPUCP and AOP.
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index f71ba21..b5b9b6a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -73,11 +73,21 @@
#size-cells = <2>;
ranges;
+ aop_mem: memory@8080 {
+ reg = <0x0 0x8080 0x0 0x6>;
+ no-map;
+ };
+
aop_cmd_db_mem: memory@8086 {
reg = <0x0 0x8086 0x0 0x2>;
compatible = "qcom,cmd-db";
no-map;
};
+
+ cpucp_mem: memory@80b0 {
+ no-map;
+ reg = <0x0 0x80b0 0x0 0x10>;
+ };
};
cpus {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 07/13] dt-bindings: arm-smmu: Add compatible for SC7280 SoC
From: Sai Prakash Ranjan Add the SoC specific compatible for SC7280 implementing arm,mmu-500. Signed-off-by: Sai Prakash Ranjan Signed-off-by: Rajendra Nayak --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 3b63f2a..c6e82ca 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -34,6 +34,7 @@ properties: items: - enum: - qcom,sc7180-smmu-500 + - qcom,sc7280-smmu-500 - qcom,sdm845-smmu-500 - qcom,sm8150-smmu-500 - qcom,sm8250-smmu-500 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 06/13] arm64: dts: qcom: SC7280: Add rpmhcc clock controller node
Add rpmhcc clock controller node for SC7280. Also add the 'fixed
clock' nodes which can now be referenced in gcc.
Signed-off-by: Taniya Das
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 55
1 file changed, 55 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 7848e88..10851e7 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -6,6 +6,7 @@
*/
#include
+#include
#include
#include
@@ -29,6 +30,42 @@
clock-frequency = <32000>;
#clock-cells = <0>;
};
+
+ pcie_0_pipe_clk: pcie-0-pipe-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <1000>;
+ #clock-cells = <0>;
+ };
+
+ pcie_1_pipe_clk: pcie-1-pipe-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <1000>;
+ #clock-cells = <0>;
+ };
+
+ ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <1000>;
+ #clock-cells = <0>;
+ };
+
+ ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <1000>;
+ #clock-cells = <0>;
+ };
+
+ ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <1000>;
+ #clock-cells = <0>;
+ };
+
+ usb3_phy_wrapper_gcc_usb30_pipe_clk:
usb3-phy-wrapper-gcc-usb30-pipe-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <1000>;
+ #clock-cells = <0>;
+ };
};
reserved_memory: reserved-memory {
@@ -174,6 +211,17 @@
gcc: clock-controller@10 {
compatible = "qcom,gcc-sc7280";
reg = <0 0x0010 0 0x1f>;
+ clocks = < RPMH_CXO_CLK>,
+< RPMH_CXO_CLK_A>, <_clk>,
+<_0_pipe_clk>, <_1_pipe_clk>,
+<_phy_rx_symbol_0_clk>,
<_phy_rx_symbol_1_clk>,
+<_phy_tx_symbol_0_clk>,
+<_phy_wrapper_gcc_usb30_pipe_clk>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
+ "pcie_0_pipe_clk", "pcie_1_pipe-clk",
+ "ufs_phy_rx_symbol_0_clk",
"ufs_phy_rx_symbol_1_clk",
+ "ufs_phy_tx_symbol_0_clk",
+ "usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@@ -325,6 +373,13 @@
,
,
;
+
+ rpmhcc: qcom,rpmhcc {
+ compatible = "qcom,sc7280-rpmh-clk";
+ clocks = <_board>;
+ clock-names = "xo";
+ #clock-cells = <1>;
+ };
};
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 00/13] Add binding updates and DT files for SC7280 SoC
This series includes a few minor binding updates and base device tree files (to boot to shell) for SC7280 SoC and the IDP board using this SoC. The series is dependent on a few driver patches to merge first, for gcc, rpmhcc and pinctrl https://lore.kernel.org/patchwork/project/lkml/list/?series=484517 https://lore.kernel.org/patchwork/project/lkml/list/?series=484489 https://lore.kernel.org/patchwork/patch/1379831/ Maulik Shah (3): arm64: dts: qcom: sc7280: Add RSC and PDC devices arm64: dts: qcom: Add reserved memory for fw arm64: dts: qcom: sc7280: Add cpuidle states Rajendra Nayak (5): dt-bindings: arm: qcom: Document SC7280 SoC and board dt-bindings: firmware: scm: Add SC7280 support arm64: dts: sc7280: Add basic dts/dtsi files for SC7280 soc dt-bindings: qcom,pdc: Add compatible for sc7280 arm64: dts: qcom: SC7280: Add rpmhcc clock controller node Sai Prakash Ranjan (4): dt-bindings: arm-smmu: Add compatible for SC7280 SoC arm64: dts: qcom: sc7280: Add device node for APPS SMMU dt-bindings: watchdog: Add compatible for SC7280 SoC arm64: dts: qcom: sc7280: Add APSS watchdog node satya priya (1): arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280 Documentation/devicetree/bindings/arm/qcom.yaml| 6 + .../devicetree/bindings/firmware/qcom,scm.txt | 1 + .../bindings/interrupt-controller/qcom,pdc.txt | 1 + .../devicetree/bindings/iommu/arm,smmu.yaml| 1 + .../devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc7280-idp.dts| 47 ++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 596 + 8 files changed, 654 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 03/13] arm64: dts: sc7280: Add basic dts/dtsi files for SC7280 soc
Add initial device tree support for the SC7280 SoC and the IDP
boards based on this SoC
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 +
arch/arm64/boot/dts/qcom/sc7280.dtsi| 294
3 files changed, 342 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile
b/arch/arm64/boot/dts/qcom/Makefile
index 5113fac..6f16ff6 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -32,6 +32,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=
sc7180-trogdor-lazor-r3-kb.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sc7180-trogdor-lazor-r3-lte.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sc7180-trogdor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sc7180-trogdor-r1-lte.dtb
+dtb-$(CONFIG_ARCH_QCOM)+= sc7280-idp.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sdm630-sony-xperia-ganges-kirin.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sdm630-sony-xperia-nile-discovery.dtb
dtb-$(CONFIG_ARCH_QCOM)+= sdm630-sony-xperia-nile-pioneer.dtb
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts
b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
new file mode 100644
index 000..428f863
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * sc7280 IDP board device tree source
+ *
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sc7280.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SC7280 IDP platform";
+ compatible = "qcom,sc7280-idp";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+_id_0 {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+/* PINCTRL - additions to nodes defined in sc7280.dtsi */
+
+_uart5_default {
+ tx {
+ pins = "gpio46";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx {
+ pins = "gpio47";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
new file mode 100644
index 000..1fe2eba
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -0,0 +1,294 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * sc7280 SoC device tree source
+ *
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+
+/ {
+ interrupt-parent = <>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <7680>;
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <_100>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <_
[PATCH 02/13] dt-bindings: firmware: scm: Add SC7280 support
Add compatible for SC7280 SoC Signed-off-by: Rajendra Nayak --- Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt index 7845643..4871fc5 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt @@ -20,6 +20,7 @@ Required properties: * "qcom,scm-msm8996" * "qcom,scm-msm8998" * "qcom,scm-sc7180" + * "qcom,scm-sc7280" * "qcom,scm-sdm845" * "qcom,scm-sm8150" and: -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 05/13] arm64: dts: qcom: sc7280: Add RSC and PDC devices
From: Maulik Shah
Add PDC interrupt controller along with apps RSC device.
Also add reserved memory for command_db.
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 44
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 1fe2eba..7848e88 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -7,6 +7,7 @@
#include
#include
+#include
/ {
interrupt-parent = <>;
@@ -30,6 +31,18 @@
};
};
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ aop_cmd_db_mem: memory@8086 {
+ reg = <0x0 0x8086 0x0 0x2>;
+ compatible = "qcom,cmd-db";
+ no-map;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -189,6 +202,19 @@
};
};
+ pdc: interrupt-controller@b22 {
+ compatible = "qcom,sc7280-pdc", "qcom,pdc";
+ reg = <0 0xb22 0 0x3>;
+ qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
+ <55 306 4>, <59 312 3>, <62 374 2>,
+ <64 434 2>, <66 438 3>, <69 86 1>,
+ <70 520 54>, <124 609 31>, <155 63 1>,
+ <156 716 12>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <>;
+ interrupt-controller;
+ };
+
tlmm: pinctrl@f10 {
compatible = "qcom,sc7280-pinctrl";
reg = <0 0xf10 0 0x100>;
@@ -198,6 +224,7 @@
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = < 0 0 175>;
+ wakeup-parent = <>;
qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
@@ -282,6 +309,23 @@
status = "disabled";
};
};
+
+ apps_rsc: rsc@1820 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0 0x1820 0 0x1>,
+ <0 0x1821 0 0x1>,
+ <0 0x1822 0 0x1>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = ,
+,
+;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = ,
+ ,
+ ,
+ ;
+ };
};
timer {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH 01/13] dt-bindings: arm: qcom: Document SC7280 SoC and board
Document the SC7280 SoC and the IDP board bindings Signed-off-by: Rajendra Nayak --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index c97d4a5..f730843 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -37,6 +37,7 @@ description: | msm8994 msm8996 sc7180 +sc7280 sdm630 sdm660 sdm845 @@ -164,6 +165,11 @@ properties: - items: - enum: + - qcom,sc7280-idp + - const: qcom,sc7280 + + - items: + - enum: - xiaomi,lavender - const: qcom,sdm660 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH] pinctrl: qcom: sc7280: Add GPIO wakeup interrupt map
From: Maulik Shah
GPIOs that can be configured as wakeup sources, have their
interrupt lines routed to PDC interrupt controller.
Provide the interrupt map of the GPIO to its wakeup capable
interrupt parent.
Signed-off-by: Maulik Shah
Signed-off-by: Rajendra Nayak
---
drivers/pinctrl/qcom/pinctrl-sc7280.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c
b/drivers/pinctrl/qcom/pinctrl-sc7280.c
index 8daccd5..99c416e 100644
--- a/drivers/pinctrl/qcom/pinctrl-sc7280.c
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c
@@ -1449,6 +1449,28 @@ static const struct msm_pingroup sc7280_groups[] = {
[182] = SDC_QDSD_PINGROUP(sdc2_data, 0x1b4000, 9, 0),
};
+static const struct msm_gpio_wakeirq_map sc7280_pdc_map[] = {
+ { 0, 134 }, { 3, 131 }, { 4, 121 }, { 7, 103 }, { 8, 155 },
+ { 11, 93 }, { 12, 78 }, { 15, 79 }, { 16, 80 }, { 18, 81 },
+ { 19, 107 }, { 20, 82 }, { 21, 83 }, { 23, 99 }, { 24, 86 },
+ { 25, 95 }, { 27, 158 }, { 28, 159 }, { 31, 90 }, { 32, 144 },
+ { 34, 77 }, { 35, 92 }, { 36, 157 }, { 39, 73 }, { 40, 97 },
+ { 41, 98 }, { 43, 85 }, { 44, 100 }, { 45, 101 }, { 47, 102 },
+ { 48, 74 }, { 51, 112 }, { 52, 156 }, { 54, 117 }, { 55, 84 },
+ { 56, 108 }, { 59, 110 }, { 60, 111 }, { 61, 123 }, { 63, 104 },
+ { 68, 127 }, { 72, 150 }, { 75, 133 }, { 77, 125 }, { 78, 105 },
+ { 79, 106 }, { 80, 118 }, { 81, 119 }, { 82, 162 }, { 83, 122 },
+ { 86, 75 }, { 88, 154 }, { 89, 124 }, { 90, 149 }, { 91, 76 },
+ { 93, 128 }, { 95, 160 }, { 101, 126 }, { 102, 96 }, { 103, 116 },
+ { 104, 114 }, { 112, 72 }, { 116, 135 }, { 117, 163 }, { 119, 137 },
+ { 121, 138 }, { 123, 139 }, { 125, 140 }, { 127, 141 }, { 128, 165 },
+ { 129, 143 }, { 130, 94 }, { 131, 145 }, { 133, 146 }, { 136, 147 },
+ { 140, 148 }, { 141, 115 }, { 142, 113 }, { 145, 130 }, { 148, 132 },
+ { 150, 87 }, { 151, 88 }, { 153, 89 }, { 155, 164 }, { 156, 129 },
+ { 157, 161 }, { 158, 120 }, { 161, 136 }, { 163, 142 }, { 172, 166 },
+ { 174, 167 },
+};
+
static const struct msm_pinctrl_soc_data sc7280_pinctrl = {
.pins = sc7280_pins,
.npins = ARRAY_SIZE(sc7280_pins),
@@ -1457,6 +1479,8 @@ static const struct msm_pinctrl_soc_data sc7280_pinctrl =
{
.groups = sc7280_groups,
.ngroups = ARRAY_SIZE(sc7280_groups),
.ngpios = 176,
+ .wakeirq_map = sc7280_pdc_map,
+ .nwakeirq_map = ARRAY_SIZE(sc7280_pdc_map),
};
static int sc7280_pinctrl_probe(struct platform_device *pdev)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 1/3] dt-bindings: power: Introduce 'assigned-performance-states' property
On 1/15/2021 9:45 PM, Bjorn Andersson wrote:
On Thu 24 Dec 05:12 CST 2020, Roja Rani Yarubandi wrote:
While most devices within power-domains which support performance states,
scale the performance state dynamically, some devices might want to
set a static/default performance state while the device is active.
These devices typically would also run off a fixed clock and not support
dynamically scaling the device's performance, also known as DVFS
techniques.
Add a property 'assigned-performance-states' which client devices can
use to set this default performance state on their power-domains.
Signed-off-by: Roja Rani Yarubandi
---
.../bindings/power/power-domain.yaml | 49 +++
1 file changed, 49 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/power-domain.yaml
b/Documentation/devicetree/bindings/power/power-domain.yaml
index aed51e9dcb11..a42977a82d06 100644
--- a/Documentation/devicetree/bindings/power/power-domain.yaml
+++ b/Documentation/devicetree/bindings/power/power-domain.yaml
@@ -66,6 +66,18 @@ properties:
by the given provider should be subdomains of the domain specified
by this binding.
+ assigned-performance-states:
+$ref: /schemas/types.yaml#/definitions/uint32-array
+description:
+ Some devices might need to configure their power domains in a default
+ performance state while the device is active. These devices typcially
+ would also run off a fixed clock and not support dynamically scaling
+ the device's performance, also known as DVFS techniques. Each cell in
+ performance state value corresponds to one power domain specified as
+ part of the power-domains property. Performance state value can be an
+ opp-level inside an OPP table of the power-domain and need not match
+ with any OPP table performance state.
+
required:
- "#power-domain-cells"
@@ -131,3 +143,40 @@ examples:
min-residency-us = <7000>;
};
};
+
+ - |
+parent4: power-controller@1234 {
+compatible = "foo,power-controller";
+reg = <0x1234 0x1000>;
+#power-domain-cells = <0>;
+};
+
+parent5: power-controller@4321 {
+compatible = "foo,power-controller";
+reg = <0x4321 0x1000>;
+#power-domain-cells = <0>;
+operating-points-v2 = <_opp_table>;
+
+power_opp_table: opp-table {
+compatible = "operating-points-v2";
+
+power_opp_low: opp1 {
+opp-level = <16>;
+};
+
+rpmpd_opp_ret: opp2 {
+opp-level = <64>;
+};
+
+rpmpd_opp_svs: opp3 {
+opp-level = <256>;
+};
+};
+};
+
+child4: consumer@12341000 {
+compatible = "foo,consumer";
+reg = <0x12341000 0x1000>;
+power-domains = <>, <>;
+assigned-performance-states = <0>, <256>;
May I ask how this is different from saying something like:
required-opps = <&??>, <_opp_svs>:
I think its potentially the same. We just don't have any code to handle this
binding in kernel yet (when this property is part of the device/consumer node)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 3/3] i2c: i2c-qcom-geni: Add support for 'assigned-performance-states'
On 1/15/2021 8:13 PM, Bjorn Andersson wrote:
On Thu 24 Dec 05:12 CST 2020, Roja Rani Yarubandi wrote:
@@ -629,6 +658,16 @@ static int __maybe_unused geni_i2c_runtime_suspend(struct
device *dev)
struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
disable_irq(gi2c->irq);
+
+ /* Drop the assigned performance state */
+ if (gi2c->assigned_pstate) {
+ ret = dev_pm_genpd_set_performance_state(dev, 0);
+ if (ret) {
+ dev_err(dev, "Failed to set performance state\n");
+ return ret;
+ }
+ }
+
Ulf, Viresh, I think we discussed this at the time of introducing the
performance states.
The client's state does not affect if its performance_state should
be included in the calculation of the aggregated performance_state, so
each driver that needs to keep some minimum performance state needs to
have these two snippets.
Would it not make sense to on enable/disable re-evaluate the
performance_state and potentially reconfigure the hardware
automatically?
I agree, this will be repeated across multiple drivers which would
need some minimal vote while they are active, handling this during
genpd enable/disable in genpd core makes sense.
Regards,
Bjorn
ret = geni_se_resources_off(>se);
if (ret) {
enable_irq(gi2c->irq);
@@ -654,6 +693,16 @@ static int __maybe_unused geni_i2c_runtime_resume(struct
device *dev)
if (ret)
return ret;
+ /* Set the assigned performance state */
+ if (gi2c->assigned_pstate) {
+ ret = dev_pm_genpd_set_performance_state(dev,
+gi2c->assigned_pstate);
+ if (ret) {
+ dev_err(dev, "Failed to set performance state\n");
+ return ret;
+ }
+ }
+
enable_irq(gi2c->irq);
gi2c->suspended = 0;
return 0;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v4 3/4] pinctrl: qcom: Don't clear pending interrupts when enabling
On 12/12/2020 3:45 AM, Douglas Anderson wrote:
In Linux, if a driver does disable_irq() and later does enable_irq()
on its interrupt, I believe it's expecting these properties:
* If an interrupt was pending when the driver disabled then it will
still be pending after the driver re-enables.
* If an edge-triggered interrupt comes in while an interrupt is
disabled it should assert when the interrupt is re-enabled.
If you think that the above sounds a lot like the disable_irq() and
enable_irq() are supposed to be masking/unmasking the interrupt
instead of disabling/enabling it then you've made an astute
observation. Specifically when talking about interrupts, "mask"
usually means to stop posting interrupts but keep tracking them and
"disable" means to fully shut off interrupt detection. It's
unfortunate that this is so confusing, but presumably this is all the
way it is for historical reasons.
Perhaps more confusing than the above is that, even though clients of
IRQs themselves don't have a way to request mask/unmask
vs. disable/enable calls, IRQ chips themselves can implement both.
...and yet more confusing is that if an IRQ chip implements
disable/enable then they will be called when a client driver calls
disable_irq() / enable_irq().
It does feel like some of the above could be cleared up. However,
without any other core interrupt changes it should be clear that when
an IRQ chip gets a request to "disable" an IRQ that it has to treat it
like a mask of that IRQ.
In any case, after that long interlude you can see that the "unmask
and clear" can break things. Maulik tried to fix it so that we no
longer did "unmask and clear" in commit 71266d9d3936 ("pinctrl: qcom:
Move clearing pending IRQ to .irq_request_resources callback"), but it
only handled the PDC case (it also had problems, but that's the
subject of another patch). Let's fix this for the non-PDC case.
From my understanding the source of the phantom interrupt in the
non-PDC case was the one that could have been introduced in
msm_gpio_irq_set_type(). Let's handle that one and then get rid of
the clear.
Fixes: 4b7618fdc7e6 ("pinctrl: qcom: Add irq_enable callback for msm gpio")
Signed-off-by: Douglas Anderson
---
I don't have lots of good test cases here, so hopefully someone from
Qualcomm can confirm that this works well for them and there isn't
some other phantom interrupt source that I'm not aware of.
I currently don;t have access to any non-PDC hardware, so could not really do
any real tests, but the changes seem sane, so
Reviewed-by: Rajendra Nayak
Changes in v4:
- ("pinctrl: qcom: Don't clear pending interrupts when enabling") split for v4.
drivers/pinctrl/qcom/pinctrl-msm.c | 32 +-
1 file changed, 14 insertions(+), 18 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c
b/drivers/pinctrl/qcom/pinctrl-msm.c
index 588df91274e2..f785646d1df7 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -774,7 +774,7 @@ static void msm_gpio_irq_mask(struct irq_data *d)
raw_spin_unlock_irqrestore(>lock, flags);
}
-static void msm_gpio_irq_clear_unmask(struct irq_data *d, bool status_clear)
+static void msm_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
@@ -792,17 +792,6 @@ static void msm_gpio_irq_clear_unmask(struct irq_data *d,
bool status_clear)
raw_spin_lock_irqsave(>lock, flags);
- if (status_clear) {
- /*
-* clear the interrupt status bit before unmask to avoid
-* any erroneous interrupts that would have got latched
-* when the interrupt is not in use.
-*/
- val = msm_readl_intr_status(pctrl, g);
- val &= ~BIT(g->intr_status_bit);
- msm_writel_intr_status(val, pctrl, g);
- }
-
val = msm_readl_intr_cfg(pctrl, g);
val |= BIT(g->intr_raw_status_bit);
val |= BIT(g->intr_enable_bit);
@@ -822,7 +811,7 @@ static void msm_gpio_irq_enable(struct irq_data *d)
irq_chip_enable_parent(d);
if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
- msm_gpio_irq_clear_unmask(d, true);
+ msm_gpio_irq_unmask(d);
}
static void msm_gpio_irq_disable(struct irq_data *d)
@@ -837,11 +826,6 @@ static void msm_gpio_irq_disable(struct irq_data *d)
msm_gpio_irq_mask(d);
}
-static void msm_gpio_irq_unmask(struct irq_data *d)
-{
- msm_gpio_irq_clear_unmask(d, false);
-}
-
/**
* msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by
parent.
* @d: The irq dta.
@@ -936,6 +920,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d,
unsigned int type)
struct msm_pinctrl *pctrl
[PATCH v2 1/2] dt-bindings: pinctrl: qcom: Add sc7280 pinctrl bindings
Add device tree binding Documentation details for Qualcomm SC7280 TLMM block. Signed-off-by: Rajendra Nayak Reviewed-by: Rob Herring --- v2: Consolidated functions under phase_flag and qdss .../bindings/pinctrl/qcom,sc7280-pinctrl.yaml | 158 + 1 file changed, 158 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml new file mode 100644 index 000..7d6a2ab --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SC7280 TLMM block + +maintainers: + - Rajendra Nayak + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + SC7280 platform. + +properties: + compatible: +const: qcom,sc7280-pinctrl + + reg: +maxItems: 1 + + interrupts: +description: Specifies the TLMM summary IRQ +maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': +description: + Specifies the PIN numbers and Flags, as defined in defined in + include/dt-bindings/interrupt-controller/irq.h +const: 2 + + gpio-controller: true + + '#gpio-cells': +description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h +const: 2 + + gpio-ranges: +maxItems: 1 + + wakeup-parent: +maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': +type: object +description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. +$ref: "/schemas/pinctrl/pincfg-node.yaml" + +properties: + pins: +description: + List of gpio pins affected by the properties specified in this + subnode. +items: + oneOf: +- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-4])$" +- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, + sdc2_cmd, sdc2_data, ufs_reset ] +minItems: 1 +maxItems: 16 + + function: +description: + Specify the alternative function to be configured for the specified + pins. + +enum: [ atest_char, atest_char0, atest_char1, atest_char2, +atest_char3, atest_usb0, atest_usb00, atest_usb01, +atest_usb02, atest_usb03, atest_usb1, atest_usb10, +atest_usb11, atest_usb12, atest_usb13, audio_ref, +cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1, +cci_timer2, cci_timer3, cci_timer4, cmu_rng0, cmu_rng1, +cmu_rng2, cmu_rng3, coex_uart1, cri_trng, cri_trng0, +cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, dp_hot, +dp_lcd, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, +gpio, host2wlan_sol, ibi_i3c, jitter_bist, lpass_slimbus, +mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, +mdp_vsync4, mdp_vsync5, mi2s0_data0, mi2s0_data1, mi2s0_sck, +mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, +mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mss_grfc0, +mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, mss_grfc2, +mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7, +mss_grfc8, mss_grfc9, nav_gpio0, nav_gpio1, nav_gpio2, +pa_indicator, pcie0_clkreqn, pcie1_clkreqn, phase_flag, +pll_bist, pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc, +qdss, qdss_cti, qlink0_enable, qlink0_request, qlink0_wmss, +qlink1_enable, qlink1_request, qlink1_wmss, qspi_clk, qspi_cs, +qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, qup06, qup07, +qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17, +sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sd_write, +sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tsense_pwm1, +tsense_pwm2, uim0_clk, uim0_data, uim0_present, uim0_reset, +uim1_clk, uim1_data, uim1_present, uim1_reset, usb2phy_ac, +usb_phy, vfr_0, vfr_1, vsense_trigger ] + + drive-strength: +enum: [2, 4, 6, 8, 10, 12, 14, 16] +default: 2 +description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + +required: + - pi
[PATCH v2 2/2] pinctrl: qcom: Add sc7280 pinctrl driver
Add initial pinctrl driver to support pin configuration with
pinctrl framework for SC7280 SoC
Signed-off-by: Rajendra Nayak
---
v2: Consolidated functions under phase_flag and qdss
Moved ufs reset pin to pin175 so its exposed as a gpio
npios updated from 175 to 176
drivers/pinctrl/qcom/Kconfig |9 +
drivers/pinctrl/qcom/Makefile |1 +
drivers/pinctrl/qcom/pinctrl-sc7280.c | 1495 +
3 files changed, 1505 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7280.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 5fe7b8a..e0b76fb 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -200,6 +200,15 @@ config PINCTRL_SC7180
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SC7180 platform.
+config PINCTRL_SC7280
+ tristate "Qualcomm Technologies Inc SC7280 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc SC7280 platform.
+
config PINCTRL_SDM660
tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
depends on GPIOLIB && OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 9e3d9c9..6ad586c 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o
+obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o
obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c
b/drivers/pinctrl/qcom/pinctrl-sc7280.c
new file mode 100644
index 000..8daccd5
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c
@@ -0,0 +1,1495 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname)\
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins,\
+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9\
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = 0x1000 * id, \
+ .io_reg = 0x1000 * id + 0x4,\
+ .intr_cfg_reg = 0x1000 * id + 0x8, \
+ .intr_status_reg = 0x1000 * id + 0xc, \
+ .intr_target_reg = 0x1000 * id + 0x8, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9,\
+ .in_bit = 0,\
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2,\
+ .intr_detection_width = 2, \
+ }
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = #pg_name,
Re: [PATCH] venus: pm_helpers: Fix kernel module reload
On 11/1/2020 6:30 PM, Stanimir Varbanov wrote:
After initial kernel module load during kernel boot and removing
the module and try to load it again an Unable to handle kernel
paging request is observed:
Unable to handle kernel paging request at virtual address a44f7416eae0
Mem abort info:
ESR = 0x9647
EC = 0x25: DABT (current EL), IL = 32 bits
SET = 0, FnV = 0
EA = 0, S1PTW = 0
Data abort info:
ISV = 0, ISS = 0x0047
CM = 0, WnR = 1
swapper pgtable: 4k pages, 48-bit VAs, pgdp=8147c000
[a44f7416eae0] pgd=00017df9f003, p4d=00017df9f003,
pud=00017df9e003, pmd=00017df9b003, pte=
Internal error: Oops: 9647 [#1] PREEMPT SMP
Modules linked in: venus_core(+) snd_soc_wsa881x regmap_sdw af_alg
snd_soc_wcd934x soundwire_qcom gpio_wcd934x q6asm_dai q6routing
q6adm q6afe_dai snd_soc_hdmi_codec q6afe q6asm q6dsp_common q6cor
display_connector rmtfs_mem drm ip_tables x_tables ipv6
[last unloaded: venus_core]
CPU: 6 PID: 889 Comm: modprobe Tainted: GW 5.10.0-rc1+ #8
Hardware name: Thundercomm Dragonboard 845c (DT)
pstate: 80400085 (Nzcv daIf +PAN -UAO -TCO BTYPE=--)
pc : queued_spin_lock_slowpath+0x1dc/0x3c8
lr : do_raw_spin_lock+0xc0/0x118
sp : 8000142cb7b0
x29: 8000142cb7b0 x28: 0013
x27: a44f72de5690 x26: 0003
x25: 17c2d00f8080 x24: 17c2c0d78010
x23: 17c2c0d4f700 x22: 17c2d00f8080
x21: x20: a44f74148000
x19: 17c2c0d4f8f8 x18:
x17: x16: a44f7342f158
x15: 0040 x14: a44f746e8320
x13: 0228 x12: 0020
x11: x10: 001c
x9 : x8 : 17c33d746ac0
x7 : 17c2c109b000 x6 : a44f7416eac0
x5 : 17c33d746ac0 x4 :
x3 : 17c2c0d4f8f8 x2 : a44f7416eae0
x1 : a44f7416eae0 x0 : 17c33d746ac8
Call trace:
queued_spin_lock_slowpath+0x1dc/0x3c8
do_raw_spin_lock+0xc0/0x118
_raw_spin_lock_irqsave+0x80/0x14c
__pm_runtime_resume+0x38/0xb8
device_link_add+0x3b8/0x5d0
core_get_v4+0x268/0x2d8 [venus_core]
venus_probe+0x108/0x458 [venus_core]
platform_drv_probe+0x54/0xa8
really_probe+0xe4/0x3b0
driver_probe_device+0x58/0xb8
device_driver_attach+0x74/0x80
__driver_attach+0x58/0xe8
bus_for_each_dev+0x70/0xc0
driver_attach+0x24/0x30
bus_add_driver+0x150/0x1f8
driver_register+0x64/0x120
__platform_driver_register+0x48/0x58
qcom_venus_driver_init+0x20/0x1000 [venus_core]
do_one_initcall+0x84/0x458
do_init_module+0x58/0x208
load_module+0x1ec0/0x26a8
__do_sys_finit_module+0xb8/0xf8
__arm64_sys_finit_module+0x20/0x30
el0_svc_common.constprop.0+0x7c/0x1c0
do_el0_svc+0x24/0x90
el0_sync_handler+0x180/0x188
el0_sync+0x174/0x180
Code: 91002100 8b0200c2 f861d884 aa0203e1 (f8246828)
---[ end trace f1f687c15fd6b2ca ]---
note: modprobe[889] exited with preempt_count 1
After revisit the OPP part of the code I found that OPP pmdomain
is detached with direct call to dev_pm_domain_detach instead of
OPP wraper for detaching pmdomains with OPP table. Correct this
by calling the OPP dev_pm_opp_detach_genpd.
ah, that seems like the right thing to do. Sorry, looks like I hadn't
really tested the cleanup path by loading/unloading the module :/
Reviewed-by: Rajendra Nayak
Fixes: 9a538b83612c ('media: venus: core: Add support for opp tables/perf
voting')
Signed-off-by: Stanimir Varbanov
---
drivers/media/platform/qcom/venus/pm_helpers.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/qcom/venus/pm_helpers.c
b/drivers/media/platform/qcom/venus/pm_helpers.c
index 0ebba8e3bd75..2946547a0df4 100644
--- a/drivers/media/platform/qcom/venus/pm_helpers.c
+++ b/drivers/media/platform/qcom/venus/pm_helpers.c
@@ -804,7 +804,7 @@ static int vcodec_domains_get(struct device *dev)
return 0;
opp_dl_add_err:
- dev_pm_domain_detach(core->opp_pmdomain, true);
+ dev_pm_opp_detach_genpd(core->opp_table);
opp_attach_err:
if (core->pd_dl_venus) {
device_link_del(core->pd_dl_venus);
@@ -842,7 +842,7 @@ static void vcodec_domains_put(struct device *dev)
if (core->opp_dl_venus)
device_link_del(core->opp_dl_venus);
- dev_pm_domain_detach(core->opp_pmdomain, true);
+ dev_pm_opp_detach_genpd(core->opp_table);
}
static int core_get_v4(struct device *dev)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 2/2] pinctrl: qcom: Add sc7280 pinctrl driver
On 10/29/2020 7:50 PM, Bjorn Andersson wrote:
On Fri 16 Oct 01:58 CDT 2020, Rajendra Nayak wrote:
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c
b/drivers/pinctrl/qcom/pinctrl-sc7280.c
[..]
+static const struct msm_function sc7280_functions[] = {
[..]
+ FUNCTION(phase_flag0),
+ FUNCTION(phase_flag1),
+ FUNCTION(phase_flag10),
+ FUNCTION(phase_flag11),
+ FUNCTION(phase_flag12),
+ FUNCTION(phase_flag13),
+ FUNCTION(phase_flag14),
+ FUNCTION(phase_flag15),
+ FUNCTION(phase_flag16),
+ FUNCTION(phase_flag17),
+ FUNCTION(phase_flag18),
+ FUNCTION(phase_flag19),
+ FUNCTION(phase_flag2),
+ FUNCTION(phase_flag20),
+ FUNCTION(phase_flag21),
+ FUNCTION(phase_flag22),
+ FUNCTION(phase_flag23),
+ FUNCTION(phase_flag24),
+ FUNCTION(phase_flag25),
+ FUNCTION(phase_flag26),
+ FUNCTION(phase_flag27),
+ FUNCTION(phase_flag28),
+ FUNCTION(phase_flag29),
+ FUNCTION(phase_flag3),
+ FUNCTION(phase_flag30),
+ FUNCTION(phase_flag31),
+ FUNCTION(phase_flag4),
+ FUNCTION(phase_flag5),
+ FUNCTION(phase_flag6),
+ FUNCTION(phase_flag7),
+ FUNCTION(phase_flag8),
+ FUNCTION(phase_flag9),
I prefer when we squash these into a single function.
+ FUNCTION(pll_bist),
+ FUNCTION(pll_bypassnl),
+ FUNCTION(pll_clk),
+ FUNCTION(pll_reset),
+ FUNCTION(pri_mi2s),
+ FUNCTION(prng_rosc),
+ FUNCTION(qdss_cti),
+ FUNCTION(qdss_gpio),
+ FUNCTION(qdss_gpio0),
+ FUNCTION(qdss_gpio1),
+ FUNCTION(qdss_gpio10),
+ FUNCTION(qdss_gpio11),
+ FUNCTION(qdss_gpio12),
+ FUNCTION(qdss_gpio13),
+ FUNCTION(qdss_gpio14),
+ FUNCTION(qdss_gpio15),
+ FUNCTION(qdss_gpio2),
+ FUNCTION(qdss_gpio3),
+ FUNCTION(qdss_gpio4),
+ FUNCTION(qdss_gpio5),
+ FUNCTION(qdss_gpio6),
+ FUNCTION(qdss_gpio7),
+ FUNCTION(qdss_gpio8),
+ FUNCTION(qdss_gpio9),
Ditto.
+ FUNCTION(qlink0_enable),
+ FUNCTION(qlink0_request),
+ FUNCTION(qlink0_wmss),
+ FUNCTION(qlink1_enable),
+ FUNCTION(qlink1_request),
+ FUNCTION(qlink1_wmss),
+ FUNCTION(qspi_clk),
+ FUNCTION(qspi_cs),
+ FUNCTION(qspi_data),
+ FUNCTION(qup00),
+ FUNCTION(qup01),
+ FUNCTION(qup02),
+ FUNCTION(qup03),
+ FUNCTION(qup04),
+ FUNCTION(qup05),
+ FUNCTION(qup06),
+ FUNCTION(qup07),
+ FUNCTION(qup10),
+ FUNCTION(qup11),
+ FUNCTION(qup12),
+ FUNCTION(qup13),
+ FUNCTION(qup14),
+ FUNCTION(qup15),
+ FUNCTION(qup16),
+ FUNCTION(qup17),
+ FUNCTION(sdc40),
+ FUNCTION(sdc41),
+ FUNCTION(sdc42),
+ FUNCTION(sdc43),
+ FUNCTION(sdc4_clk),
+ FUNCTION(sdc4_cmd),
+ FUNCTION(sd_write),
+ FUNCTION(sec_mi2s),
+ FUNCTION(tb_trig),
+ FUNCTION(tgu_ch0),
+ FUNCTION(tgu_ch1),
+ FUNCTION(tsense_pwm1),
+ FUNCTION(tsense_pwm2),
+ FUNCTION(uim0_clk),
+ FUNCTION(uim0_data),
+ FUNCTION(uim0_present),
+ FUNCTION(uim0_reset),
+ FUNCTION(uim1_clk),
+ FUNCTION(uim1_data),
+ FUNCTION(uim1_present),
+ FUNCTION(uim1_reset),
+ FUNCTION(usb2phy_ac),
+ FUNCTION(usb_phy),
+ FUNCTION(vfr_0),
+ FUNCTION(vfr_1),
+ FUNCTION(vsense_trigger),
+};
+
+/* Every pin is maintained as a single group, and missing or non-existing pin
+ * would be maintained as dummy group to synchronize pin group index with
+ * pin descriptor registered with pinctrl core.
+ * Clients would not be able to request these dummy pin groups.
+ */
+static const struct msm_pingroup sc7280_groups[] = {
[..]
+ [174] = PINGROUP(174, qdss_gpio15, _, _, _, _, _, _, _, _),
+ [175] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x1b3000, 15, 0),
+ [176] = SDC_QDSD_PINGROUP(sdc1_clk, 0x1b3000, 13, 6),
+ [177] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x1b3000, 11, 3),
+ [178] = SDC_QDSD_PINGROUP(sdc1_data, 0x1b3000, 9, 0),
+ [179] = SDC_QDSD_PINGROUP(sdc2_clk, 0x1b4000, 14, 6),
+ [180] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x1b4000, 11, 3),
+ [181] = SDC_QDSD_PINGROUP(sdc2_data, 0x1b4000, 9, 0),
+ [182] = UFS_RESET(ufs_reset, 0x1be000),
Rather than fiddling ufs reset using pinconf we expose it as a gp(i)o
pin upstream. So please move this to be the 175th item in the list and
bump ngpios to 176 below.
+};
+
+static const struct msm_pinctrl_soc_data sc7280_pinctrl = {
+ .pins = sc7280_pins,
+ .npins = ARRAY_SIZE(sc7280_pins),
+ .functions = sc7280_functions,
+ .nfunctions = ARRAY_SIZE(sc7280_functions),
+ .groups = sc7280_groups,
+ .ngroups = ARRAY_SIZE(sc7280_groups),
+ .ngpios = 175,
+};
+
Apart from that it looks good.
thanks Bjorn, I'll fix-up and re-post.
--
QUALCOMM INDIA, on behalf of Qualcomm
[PATCH 2/2] pinctrl: qcom: Add sc7280 pinctrl driver
Add initial pinctrl driver to support pin configuration with
pinctrl framework for SC7280 SoC
Signed-off-by: Rajendra Nayak
---
drivers/pinctrl/qcom/Kconfig |9 +
drivers/pinctrl/qcom/Makefile |1 +
drivers/pinctrl/qcom/pinctrl-sc7280.c | 1717 +
3 files changed, 1727 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7280.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index f8ff30c..e5bcffc 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -191,6 +191,15 @@ config PINCTRL_SC7180
Qualcomm Technologies Inc TLMM block found on the Qualcomm
Technologies Inc SC7180 platform.
+config PINCTRL_SC7280
+ tristate "Qualcomm Technologies Inc SC7280 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc SC7280 platform.
+
config PINCTRL_SDM660
tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
depends on GPIOLIB && OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 061ec9f..5ee6edd 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o
+obj-$(CONFIG_PINCTRL_SC7280) += pinctrl-sc7280.o
obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280.c
b/drivers/pinctrl/qcom/pinctrl-sc7280.c
new file mode 100644
index 000..36a5f82
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sc7280.c
@@ -0,0 +1,1717 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname)\
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins,\
+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9\
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = 0x1000 * id, \
+ .io_reg = 0x1000 * id + 0x4,\
+ .intr_cfg_reg = 0x1000 * id + 0x8, \
+ .intr_status_reg = 0x1000 * id + 0xc, \
+ .intr_target_reg = 0x1000 * id + 0x8, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9,\
+ .in_bit = 0,\
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2,\
+ .intr_detection_width = 2, \
+ }
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = (unsigned int)ARRAY_SIZ
[PATCH 1/2] dt-bindings: pinctrl: qcom: Add sc7280 pinctrl bindings
Add device tree binding Documentation details for Qualcomm SC7280 TLMM block. Signed-off-by: Rajendra Nayak --- .../bindings/pinctrl/qcom,sc7280-pinctrl.yaml | 170 + 1 file changed, 170 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml new file mode 100644 index 000..971cfaf --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-pinctrl.yaml @@ -0,0 +1,170 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc7280-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SC7280 TLMM block + +maintainers: + - Rajendra Nayak + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + SC7280 platform. + +properties: + compatible: +const: qcom,sc7280-pinctrl + + reg: +maxItems: 1 + + interrupts: +description: Specifies the TLMM summary IRQ +maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': +description: + Specifies the PIN numbers and Flags, as defined in defined in + include/dt-bindings/interrupt-controller/irq.h +const: 2 + + gpio-controller: true + + '#gpio-cells': +description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h +const: 2 + + gpio-ranges: +maxItems: 1 + + wakeup-parent: +maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': +type: object +description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. +$ref: "/schemas/pinctrl/pincfg-node.yaml" + +properties: + pins: +description: + List of gpio pins affected by the properties specified in this + subnode. +items: + oneOf: +- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-4])$" +- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, + sdc2_cmd, sdc2_data, ufs_reset ] +minItems: 1 +maxItems: 16 + + function: +description: + Specify the alternative function to be configured for the specified + pins. + +enum: [ atest_char, atest_char0, atest_char1, atest_char2, +atest_char3, atest_usb0, atest_usb00, atest_usb01, +atest_usb02, atest_usb03, atest_usb1, atest_usb10, +atest_usb11, atest_usb12, atest_usb13, audio_ref, +cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1, +cci_timer2, cci_timer3, cci_timer4, cmu_rng0, cmu_rng1, +cmu_rng2, cmu_rng3, coex_uart1, cri_trng, cri_trng0, +cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, dp_hot, +dp_lcd, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, +gpio, host2wlan_sol, ibi_i3c, jitter_bist, lpass_slimbus, +mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, +mdp_vsync4, mdp_vsync5, mi2s0_data0, mi2s0_data1, mi2s0_sck, +mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, +mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mss_grfc0, +mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, mss_grfc2, +mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, mss_grfc7, +mss_grfc8, mss_grfc9, nav_gpio0, nav_gpio1, nav_gpio2, +pa_indicator, pcie0_clkreqn, pcie1_clkreqn, phase_flag0, +phase_flag1, phase_flag10, phase_flag11, phase_flag12, +phase_flag13, phase_flag14, phase_flag15, phase_flag16, +phase_flag17, phase_flag18, phase_flag19, phase_flag2, +phase_flag20, phase_flag21, phase_flag22, phase_flag23, +phase_flag24, phase_flag25, phase_flag26, phase_flag27, +phase_flag28, phase_flag29, phase_flag3, phase_flag30, +phase_flag31, phase_flag4, phase_flag5, phase_flag6, +phase_flag7, phase_flag8, phase_flag9, pll_bist, +pll_bypassnl, pll_clk, pll_reset, pri_mi2s, prng_rosc, +qdss_cti, qdss_gpio, qdss_gpio0, qdss_gpio1, qdss_gpio10, +qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14, +qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5, +qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, +qlink0_enable, qlink0_request, qlink0_wmss, qlink1_enable, +qlink1_request, qlink1_wmss, qspi_clk, qspi_cs, qspi_data, +qup00, qup01, qup02, qup03, qup04, qup05, qup06, qup07, +qup10,
Re: [PATCH v2] drm/msm/dp: add opp_table corner voting support base on dp_ink_clk rate
On 10/4/2020 3:56 AM, Kuogee Hsieh wrote:
Set link rate by using OPP set rate api so that CX level will be set
accordingly based on the link rate.
Changes in v2:
-- remove dev from dp_ctrl_put() parameters
-- address review comments
This needs to go below '---' and should not be part of the
change log.
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_ctrl.c| 26 +
drivers/gpu/drm/msm/dp/dp_display.c | 2 +-
drivers/gpu/drm/msm/dp/dp_power.c | 44 ++---
drivers/gpu/drm/msm/dp/dp_power.h | 2 +-
4 files changed, 68 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 2e3e1917351f..6eb9cdad1421 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -76,6 +77,8 @@ struct dp_ctrl_private {
struct dp_parser *parser;
struct dp_catalog *catalog;
+ struct opp_table *opp_table;
+
struct completion idle_comp;
struct completion video_comp;
};
@@ -1836,6 +1839,7 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct
dp_link *link,
struct dp_parser *parser)
{
struct dp_ctrl_private *ctrl;
+ int ret;
if (!dev || !panel || !aux ||
!link || !catalog) {
@@ -1849,6 +1853,19 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct
dp_link *link,
return ERR_PTR(-ENOMEM);
}
+ ctrl->opp_table = dev_pm_opp_set_clkname(dev, "ctrl_link");
+ if (IS_ERR(ctrl->opp_table)) {
+ dev_err(dev, "invalid DP OPP table in device tree\n");
You do this regardless of an OPP table in DT, so for starters the error
message is wrong. Secondly this can return you a -EPROBE_DEFER if the
clock driver isn't ready yet.
So the ideal thing to do here, is return a PTR_ERR(ctrl->opp_table)
+ ctrl->opp_table = NULL;
+ } else {
+ /* OPP table is optional */
+ ret = dev_pm_opp_of_add_table(dev);
+ if (ret && ret != -ENODEV) {
+ dev_pm_opp_put_clkname(ctrl->opp_table);
+ ctrl->opp_table = NULL;
+ }
+ }
+
init_completion(>idle_comp);
init_completion(>video_comp);
@@ -1866,4 +1883,13 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
void dp_ctrl_put(struct dp_ctrl *dp_ctrl)
{
+ struct dp_ctrl_private *ctrl;
+
+ ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
+
+ if (ctrl->opp_table) {
+ dev_pm_opp_of_remove_table(ctrl->dev);
+ dev_pm_opp_put_clkname(ctrl->opp_table);
+ ctrl->opp_table = NULL;
+ }
}
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c
b/drivers/gpu/drm/msm/dp/dp_display.c
index e175aa3fd3a9..269f83550b46 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -698,7 +698,7 @@ static int dp_init_sub_modules(struct dp_display_private
*dp)
goto error;
}
- dp->power = dp_power_get(dp->parser);
+ dp->power = dp_power_get(dev, dp->parser);
if (IS_ERR(dp->power)) {
rc = PTR_ERR(dp->power);
DRM_ERROR("failed to initialize power, rc = %d\n", rc);
diff --git a/drivers/gpu/drm/msm/dp/dp_power.c
b/drivers/gpu/drm/msm/dp/dp_power.c
index 17c1fc6a2d44..9c4ea00a5f2a 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.c
+++ b/drivers/gpu/drm/msm/dp/dp_power.c
@@ -8,12 +8,14 @@
#include
#include
#include
+#include
#include "dp_power.h"
#include "msm_drv.h"
struct dp_power_private {
struct dp_parser *parser;
struct platform_device *pdev;
+ struct device *dev;
struct clk *link_clk_src;
struct clk *pixel_provider;
struct clk *link_provider;
@@ -148,18 +150,51 @@ static int dp_power_clk_deinit(struct dp_power_private
*power)
return 0;
}
+static int dp_power_clk_set_link_rate(struct dp_power_private *power,
+ struct dss_clk *clk_arry, int num_clk, int enable)
+{
+ u32 rate;
+ int i, rc = 0;
+
+ for (i = 0; i < num_clk; i++) {
+ if (clk_arry[i].clk) {
+ if (clk_arry[i].type == DSS_CLK_PCLK) {
+ if (enable)
+ rate = clk_arry[i].rate;
+ else
+ rate = 0;
+
+ rc = dev_pm_opp_set_rate(power->dev, rate);
I am not sure how this is expected to work when you have multiple link clocks,
since you can only associate one of them with the OPP table which ends up
getting scaled when you do a dev_pm_opp_set_rate()
Do you really have platforms which will have multiple link clocks?
+
Re: [PATCH] drm/msm/dp: add voltage corners voting support base on dp link rate
On 9/30/2020 1:54 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2020-09-29 10:10:26)
Set link rate by using OPP set rate api so that CX level will be set
accordingly base on the link rate.
s/base/based/
Signed-off-by: Kuogee Hsieh
---
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 2e3e1917351f..e1595d829e04 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -1849,6 +1853,21 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct
dp_link *link,
return ERR_PTR(-ENOMEM);
}
+ ctrl->opp_table = dev_pm_opp_set_clkname(dev, "ctrl_link");
I see that downstream has multiple DP clocks which end up voting on CX, we
don't have a
way of associating multiple OPP tables with a device upstream, so whats usually
done is
(assuming all the clocks get scaled in lock step, which I assume is the case
here) we pick
the clock with the 'highest' CX requirement and associate that with the OPP
table.
I haven't looked but I am hoping thats how we have decided to associate
"ctrl_link" clock
here?
+
+ if (IS_ERR(ctrl->opp_table)) {
+ dev_err(dev, "invalid DP OPP table in device tree\n");
+ ctrl->opp_table = NULL;
+ } else {
+ /* OPP table is optional */
+ ret = dev_pm_opp_of_add_table(dev);
+ if (ret && ret != -ENODEV) {
+ dev_err(dev, "add DP OPP table\n");
This is debug noise right?
+ dev_pm_opp_put_clkname(ctrl->opp_table);
+ ctrl->opp_table = NULL;
+ }
+ }
+
init_completion(>idle_comp);
init_completion(>video_comp);
@@ -1864,6 +1883,18 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
return >dp_ctrl;
}
-void dp_ctrl_put(struct dp_ctrl *dp_ctrl)
+void dp_ctrl_put(struct device *dev, struct dp_ctrl *dp_ctrl)
{
+ struct dp_ctrl_private *ctrl;
+
+ if (!dp_ctrl)
Can this happen?
+ return;
+
+ ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
+
+ if (ctrl->opp_table != NULL) {
This is usually written as
if (ctrl->opp_table)
+ dev_pm_opp_of_remove_table(dev);
+ dev_pm_opp_put_clkname(ctrl->opp_table);
+ ctrl->opp_table = NULL;
+ }
}
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h
index f60ba93c8678..19b412a93e02 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.h
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h
@@ -31,6 +31,6 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct
dp_link *link,
struct dp_panel *panel, struct drm_dp_aux *aux,
struct dp_power *power, struct dp_catalog *catalog,
struct dp_parser *parser);
-void dp_ctrl_put(struct dp_ctrl *dp_ctrl);
+void dp_ctrl_put(struct device *dev, struct dp_ctrl *dp_ctrl);
Is 'dev' not inside 'dp_ctrl'?
#endif /* _DP_CTRL_H_ */
diff --git a/drivers/gpu/drm/msm/dp/dp_power.c
b/drivers/gpu/drm/msm/dp/dp_power.c
index 17c1fc6a2d44..3d75bf09e38f 100644
--- a/drivers/gpu/drm/msm/dp/dp_power.c
+++ b/drivers/gpu/drm/msm/dp/dp_power.c
@@ -8,12 +8,14 @@
#include
#include
#include
+#include
#include "dp_power.h"
#include "msm_drv.h"
struct dp_power_private {
struct dp_parser *parser;
struct platform_device *pdev;
+ struct device *dev;
struct clk *link_clk_src;
struct clk *pixel_provider;
struct clk *link_provider;
@@ -148,18 +150,49 @@ static int dp_power_clk_deinit(struct dp_power_private
*power)
return 0;
}
+static int dp_power_clk_set_link_rate(struct dp_power_private *power,
+ struct dss_clk *clk_arry, int num_clk, int enable)
+{
+ u32 rate;
+ int i, rc = 0;
+
+ for (i = 0; i < num_clk; i++) {
+ if (clk_arry[i].clk) {
+ if (clk_arry[i].type == DSS_CLK_PCLK) {
+ if (enable)
+ rate = clk_arry[i].rate;
+ else
+ rate = 0;
+
+ rc = dev_pm_opp_set_rate(power->dev, rate);
Why do we keep going if rc is non-zero?
+ }
+
+ }
+ }
+ return rc;
+}
+
static int dp_power_clk_set_rate(struct dp_power_private *power,
enum dp_pm_type module, bool enable)
{
int rc = 0;
struct dss_module_power *mp = >parser->mp[module];
- if (enable) {
- rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk);
+ if (module == DP_CTRL_PM) {
+ rc = dp_power_clk_set_link_rate(power, mp->clk_config,
mp->num_clk, enable);
if (rc) {
- DRM_ERROR("failed to set
Re: [PATCH 1/2] docs: Clarify abstract scale usage for power values in Energy Model
On 9/30/2020 7:34 PM, Lukasz Luba wrote: On 9/30/20 11:55 AM, Rajendra Nayak wrote: On 9/30/2020 1:55 PM, Lukasz Luba wrote: Hi Douglas, On 9/30/20 12:53 AM, Doug Anderson wrote: Hi, On Tue, Sep 29, 2020 at 5:16 AM Lukasz Luba wrote: The Energy Model (EM) can store power values in milli-Watts or in abstract scale. This might cause issues in the subsystems which use the EM for estimating the device power, such as: - mixing of different scales in a subsystem which uses multiple (cooling) devices (e.g. thermal Intelligent Power Allocation (IPA)) - assuming that energy [milli-Joules] can be derived from the EM power values which might not be possible since the power scale doesn't have to be in milli-Watts To avoid misconfiguration add the needed documentation to the EM and related subsystems: EAS and IPA. Signed-off-by: Lukasz Luba --- .../driver-api/thermal/power_allocator.rst | 8 Documentation/power/energy-model.rst | 13 + Documentation/scheduler/sched-energy.rst | 5 + 3 files changed, 26 insertions(+) I haven't read through these files in massive detail, but the quick skim makes me believe that your additions seem sane. In general, I'm happy with documenting reality, thus: Reviewed-by: Douglas Anderson Thank you for the review. I will note: you haven't actually updated the device tree bindings. Thus, presumably, anyone who is specifying these numbers in the device tree is still supposed to specify them in a way that mW can be recovered, right? Said another way: nothing about your patches makes it OK to specify numbers in device trees using an "abstract scale", right? For completeness, we are talking here about the binding from: Documentation/devicetree/bindings/arm/cpus.yaml which is 'dynamic-power-coefficient'. Yes, it stays untouched, also the unit (uW/MHz/V^2) which then allows to have mW in the power values in the EM. So for platforms where 'dynamic-power-coefficient' is specified in device tree, its always expected to be derived from 'real' power numbers on these platforms in 'real' mW? Yes, the purpose and the name of that binding was only for 'real' power in mW. Atleast on Qualcomm platforms we have these numbers scaled, so in essence it can't be used to derive 'real' mW values. That said we also do not have any of the 'platform might face potential issue of mixing devices in one thermal zone of two scales' problem. If you have these numbers scaled, then it's probably documented somewhere in your docs for your OEMs, because they might assume it's in uW/MHz/V^2 (according to the bindings doc). If not, they probably realized it during the measurements and comparison (that the power in EM is not what they see on the power meter). This binding actually helps those developers who take the experiments and based on measured power values, store derived coefficient. Everyone can just measure in local setup and compare the results easily, speaking the same language (proposing maybe a patch adjusting the value in DT). So the question is, can such platforms still use 'dynamic-power-coefficient' in device tree and create an abstract scale? The other way of doing this would be to *not* specify this value in device tree and have these values stored in the cpufreq driver and register a custom callback to do the math. But then we would also have to change the name of that binding. I'd recommend you the second way that you've described. It will avoid your OEMs confusion. In your cpufreq driver you can simply register to EM using the em_dev_register_perf_domain(). In your local callback you can do whatever you need (read driver array, firmware, DT, scale or not, etc). The helper code in dev_pm_opp_of_register_em() is probably not suited for your use case (when you don't want to share the real power of the SoC). Got it, thanks for the clarification. I will get the cpufreq driver updated to use em_dev_register_perf_domain() with a custom callback and get rid of these values from device tree. -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 1/2] docs: Clarify abstract scale usage for power values in Energy Model
On 9/30/2020 1:55 PM, Lukasz Luba wrote: Hi Douglas, On 9/30/20 12:53 AM, Doug Anderson wrote: Hi, On Tue, Sep 29, 2020 at 5:16 AM Lukasz Luba wrote: The Energy Model (EM) can store power values in milli-Watts or in abstract scale. This might cause issues in the subsystems which use the EM for estimating the device power, such as: - mixing of different scales in a subsystem which uses multiple (cooling) devices (e.g. thermal Intelligent Power Allocation (IPA)) - assuming that energy [milli-Joules] can be derived from the EM power values which might not be possible since the power scale doesn't have to be in milli-Watts To avoid misconfiguration add the needed documentation to the EM and related subsystems: EAS and IPA. Signed-off-by: Lukasz Luba --- .../driver-api/thermal/power_allocator.rst | 8 Documentation/power/energy-model.rst | 13 + Documentation/scheduler/sched-energy.rst | 5 + 3 files changed, 26 insertions(+) I haven't read through these files in massive detail, but the quick skim makes me believe that your additions seem sane. In general, I'm happy with documenting reality, thus: Reviewed-by: Douglas Anderson Thank you for the review. I will note: you haven't actually updated the device tree bindings. Thus, presumably, anyone who is specifying these numbers in the device tree is still supposed to specify them in a way that mW can be recovered, right? Said another way: nothing about your patches makes it OK to specify numbers in device trees using an "abstract scale", right? For completeness, we are talking here about the binding from: Documentation/devicetree/bindings/arm/cpus.yaml which is 'dynamic-power-coefficient'. Yes, it stays untouched, also the unit (uW/MHz/V^2) which then allows to have mW in the power values in the EM. So for platforms where 'dynamic-power-coefficient' is specified in device tree, its always expected to be derived from 'real' power numbers on these platforms in 'real' mW? Atleast on Qualcomm platforms we have these numbers scaled, so in essence it can't be used to derive 'real' mW values. That said we also do not have any of the 'platform might face potential issue of mixing devices in one thermal zone of two scales' problem. So the question is, can such platforms still use 'dynamic-power-coefficient' in device tree and create an abstract scale? The other way of doing this would be to *not* specify this value in device tree and have these values stored in the cpufreq driver and register a custom callback to do the math. It just feels like jumping through hoops just to deal with the fact that the device tree bindings say its expected to be in mW and can't be abstract. -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v6 0/5] DVFS support for Venus
On 9/1/2020 7:50 PM, Rajendra Nayak wrote: Rob, can you pick PATCH 1 since its already reviewed by you. Stan, Patch 2 and 3 will need to be picked by you and they both have your ACKs Rob/Stan, any plans to get the patches merged for 5.10? Patch 4 and 5 will need to be merged via the qcom tree once we have them reviewed. v6: No changes, rebased on 5.9-rc3 v5: Fixed the opp-tables (patch 4/5) to avoid -ERANGE from dev_pm_opp_set_rate v4: Moved code from probe/remove/runtime_suspend into different pm_ops callbacks v3: Renamed the optional power domain as cx v2: Fixed up the labels of OPP nodes in patch 4 Included the bindings update patch as part of this series, a resend of https://lore.kernel.org/patchwork/patch/1241077/ These patches add DVFS support for Venus Rajendra Nayak (5): dt-bindings: media: venus: Add an optional power domain for perf voting media: venus: core: Fix error handling in probe media: venus: core: Add support for opp tables/perf voting arm64: dts: sdm845: Add OPP tables and power-domains for venus arm64: dts: sc7180: Add OPP tables and power-domains for venus .../bindings/media/qcom,sc7180-venus.yaml | 6 +- .../bindings/media/qcom,sdm845-venus-v2.yaml | 6 +- arch/arm64/boot/dts/qcom/sc7180.dtsi | 35 +++- arch/arm64/boot/dts/qcom/sdm845.dtsi | 40 +- drivers/media/platform/qcom/venus/core.c | 17 ++-- drivers/media/platform/qcom/venus/core.h | 5 ++ drivers/media/platform/qcom/venus/pm_helpers.c | 92 -- 7 files changed, 183 insertions(+), 18 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH] arm64: dts: qcom: sc7180: Add 'sustainable_power' for CPU thermal zones
On 9/3/2020 10:14 AM, Rajendra Nayak wrote: On 9/2/2020 9:02 PM, Doug Anderson wrote: Hi, On Tue, Sep 1, 2020 at 10:36 PM Rajendra Nayak wrote: * In terms of the numbers here, I believe that you're claiming that we can dissipate 768 mW * 6 + 1202 mW * 2 = ~7 Watts of power. My memory of how much power we could dissipate in previous laptops I worked on is a little fuzzy, but that doesn't seem insane for a passively-cooled laptop. However, I think someone could conceivably put this chip in a smaller form factor. In such a case, it seems like we'd want these things to sum up to ~2000 (if it would ever make sense for someone to put this chip in a phone) or ~4000 (if it would ever make sense for someone to put this chip in a small tablet). It seems possible that, to achieve this, we might have to tweak the "dynamic-power-coefficient". DPC values are calculated (at a SoC) by actually measuring max power at various frequency/voltage combinations by running things like dhrystone. How would the max power a SoC can generate depend on form factors? How much it can dissipate sure is, but then I am not super familiar how thermal frameworks end up using DPC for calculating power dissipated, I am guessing they don't. I don't know how much thought was put into those numbers, but the fact that the little cores have a super round 100 for their dynamic-power-coefficient makes me feel like they might have been more schwags than anything. Rajendra maybe knows? FWIK, the values are always scaled and normalized to 100 for silver and then used to derive the relative DPC number for gold. If you see the DPC for silver cores even on sdm845 is a 100. Again these are not estimations but based on actual power measurements. The scaling to 100 doesn't seem to match how the thermal framework is using them. Take a look at of_cpufreq_cooling_register(). It takes the "dynamic-power-coefficient" and passes it as "capacitance" into __cpufreq_cooling_register(). That's eventually used to compute power, which is documented in the code to be in mW. power = (u64)capacitance * freq_mhz * voltage_mv * voltage_mv; do_div(power, 10); /* power is stored in mW */ freq_table[i].power = power; That's used together with "sustainable-power", which is the attribute that Matthias is trying to set. That value is documented to be in mW as well. ...so if the silver cores are always scaled to 100 regardless of how much power they actually draw then it'll be impossible to actually think about "sustainable-power" as a mW value. Presumably we either need to accept that fact (and ideally document it) or we need to change the values for silver / gold cores (we could still keep the relative values the same and just scale them). That sounds reasonable (still keep the relative values and scale them) I'll get back on what those scaled numbers would look like, and try to get some sense of why this scaling to 100 was done (like you said I don't see any documentation on this), but I see atleast a few other non-qcom SoCs doing this too in mainline (like rockchip/rk3399) On second thoughts, why wouldn't a relative 'sustainable-power' value work? On every device, one would need to do the exercise that Matthias did to come up with the OPP at which we can sustain max CPU/GPU loads anyway. I mean even if we do change the DPC values to match actual power, Matthias would still observe that we can sustain at the very same OPP and not any different. Its just that the mW values that are passed to kernel are relative and not absolute. My worry is that perhaps no SoC vendor wants to put these absolute numbers out. -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH] arm64: dts: qcom: sc7180: Add 'sustainable_power' for CPU thermal zones
On 9/2/2020 9:02 PM, Doug Anderson wrote: Hi, On Tue, Sep 1, 2020 at 10:36 PM Rajendra Nayak wrote: * In terms of the numbers here, I believe that you're claiming that we can dissipate 768 mW * 6 + 1202 mW * 2 = ~7 Watts of power. My memory of how much power we could dissipate in previous laptops I worked on is a little fuzzy, but that doesn't seem insane for a passively-cooled laptop. However, I think someone could conceivably put this chip in a smaller form factor. In such a case, it seems like we'd want these things to sum up to ~2000 (if it would ever make sense for someone to put this chip in a phone) or ~4000 (if it would ever make sense for someone to put this chip in a small tablet). It seems possible that, to achieve this, we might have to tweak the "dynamic-power-coefficient". DPC values are calculated (at a SoC) by actually measuring max power at various frequency/voltage combinations by running things like dhrystone. How would the max power a SoC can generate depend on form factors? How much it can dissipate sure is, but then I am not super familiar how thermal frameworks end up using DPC for calculating power dissipated, I am guessing they don't. I don't know how much thought was put into those numbers, but the fact that the little cores have a super round 100 for their dynamic-power-coefficient makes me feel like they might have been more schwags than anything. Rajendra maybe knows? FWIK, the values are always scaled and normalized to 100 for silver and then used to derive the relative DPC number for gold. If you see the DPC for silver cores even on sdm845 is a 100. Again these are not estimations but based on actual power measurements. The scaling to 100 doesn't seem to match how the thermal framework is using them. Take a look at of_cpufreq_cooling_register(). It takes the "dynamic-power-coefficient" and passes it as "capacitance" into __cpufreq_cooling_register(). That's eventually used to compute power, which is documented in the code to be in mW. power = (u64)capacitance * freq_mhz * voltage_mv * voltage_mv; do_div(power, 10); /* power is stored in mW */ freq_table[i].power = power; That's used together with "sustainable-power", which is the attribute that Matthias is trying to set. That value is documented to be in mW as well. ...so if the silver cores are always scaled to 100 regardless of how much power they actually draw then it'll be impossible to actually think about "sustainable-power" as a mW value. Presumably we either need to accept that fact (and ideally document it) or we need to change the values for silver / gold cores (we could still keep the relative values the same and just scale them). That sounds reasonable (still keep the relative values and scale them) I'll get back on what those scaled numbers would look like, and try to get some sense of why this scaling to 100 was done (like you said I don't see any documentation on this), but I see atleast a few other non-qcom SoCs doing this too in mainline (like rockchip/rk3399) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH] arm64: dts: qcom: sc7180: Add 'sustainable_power' for CPU thermal zones
I'm not massively familiar with this area of the code, but I guess I
shouldn't let that stop me from having an opinion! :-P
* I would agree that it seems highly unlikely that someone would put
one of these chips in a device that could only dissipate the heat from
the lowest OPP, so having some higher estimate definitely makes sense.
* In terms of the numbers here, I believe that you're claiming that we
can dissipate 768 mW * 6 + 1202 mW * 2 = ~7 Watts of power.
No, I'm claiming it's 768 mW + 1202 mW = ~2 W.
SC7180 has a 6 thermal zones for the 6 little cores and 4 zones for the
2 big cores. Each of these thermal zones uses either all little or all big
cores as cooling devices, hence the power sustainable power of the
individual zones doesn't add up. 768 mW corresponds to 6x 128 mW (aka all
little cores at 1.8 GHz), and 1202 mW to 2x 601 mW (both big cores at 1.9 GHz).
My memory
of how much power we could dissipate in previous laptops I worked on
is a little fuzzy, but that doesn't seem insane for a passively-cooled
laptop. However, I think someone could conceivably put this chip in a
smaller form factor. In such a case, it seems like we'd want these
things to sum up to ~2000 (if it would ever make sense for someone to
put this chip in a phone) or ~4000 (if it would ever make sense for
someone to put this chip in a small tablet).
See above, the sustainable power with this patch only adds up to ~2000.
It is possible though that it would be lower in a smaller form factor
device.
I'd be ok with posting something lower for SC7180 (it would be a guess
though) and use the specific numbers in the device specific DT.
It seems possible that,
to achieve this, we might have to tweak the
"dynamic-power-coefficient". I don't know how much thought was put
into those numbers, but the fact that the little cores have a super
round 100 for their dynamic-power-coefficient makes me feel like they
might have been more schwags than anything. Rajendra maybe knows?
Yeah, it's possible that that was just an approximation
No, these are based on actual power measurements.
* I'm curious about the fact that there are two numbers here: one for
littles and one for bigs. If I had to guess I'd say that since all
the cores are in one package so the contributions kinda need to be
thought of together, right? If we're sitting there thermally
throttled then we'd want to pick the best perf-per-watt for the
overall package. This is why your patch says we can sustain the
little cores at max and the big cores get whatever is left over,
right?
It's derived from how Qualcomm specified the thermal zones and cooling
devices. Any ("cpu") zone is either cooled by (all) big cores or by (all)
little cores, but not a mix of them. In my tests I also saw that the big
cores seemed to have little impact on the little ones. The little cores
are at max because even running at max frequency the temperature in the
'little zones' wouldn't come close to the trip point.
* Should we be leaving some room in here for the GPU? ...or I guess
once we list it as a cooling device we'll have to decrease the amount
the CPUs can use?
I don't know for sure, but judging from the CPU zones I wouldn't be
surprised if the GPU was managed exclusively in the dedicated GPU
thermal zones (I guess that's what 'gpuss0-thermal' and 'gpuss1-thermal'
are). If that's not the case the values in the CPU zones can be
adjusted when specific data is available.
So I guess the tl; dr is:
a) We should check "dynamic-power-coefficient" and possibly adjust.
ok, lets see if Rajendra can check if there is room for tweaking.
I suggest we don't :)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH] arm64: dts: qcom: sc7180: Add 'sustainable_power' for CPU thermal zones
* In terms of the numbers here, I believe that you're claiming that we can dissipate 768 mW * 6 + 1202 mW * 2 = ~7 Watts of power. My memory of how much power we could dissipate in previous laptops I worked on is a little fuzzy, but that doesn't seem insane for a passively-cooled laptop. However, I think someone could conceivably put this chip in a smaller form factor. In such a case, it seems like we'd want these things to sum up to ~2000 (if it would ever make sense for someone to put this chip in a phone) or ~4000 (if it would ever make sense for someone to put this chip in a small tablet). It seems possible that, to achieve this, we might have to tweak the "dynamic-power-coefficient". DPC values are calculated (at a SoC) by actually measuring max power at various frequency/voltage combinations by running things like dhrystone. How would the max power a SoC can generate depend on form factors? How much it can dissipate sure is, but then I am not super familiar how thermal frameworks end up using DPC for calculating power dissipated, I am guessing they don't. I don't know how much thought was put into those numbers, but the fact that the little cores have a super round 100 for their dynamic-power-coefficient makes me feel like they might have been more schwags than anything. Rajendra maybe knows? FWIK, the values are always scaled and normalized to 100 for silver and then used to derive the relative DPC number for gold. If you see the DPC for silver cores even on sdm845 is a 100. Again these are not estimations but based on actual power measurements. -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v6 2/5] media: venus: core: Fix error handling in probe
Post a successful pm_ops->core_get, an error in probe
should exit by doing a pm_ops->core_put which seems
to be missing. So fix it.
Signed-off-by: Rajendra Nayak
Acked-by: Stanimir Varbanov
Reviewed-by: Bjorn Andersson
---
drivers/media/platform/qcom/venus/core.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/media/platform/qcom/venus/core.c
b/drivers/media/platform/qcom/venus/core.c
index 203c653..bfcaba3 100644
--- a/drivers/media/platform/qcom/venus/core.c
+++ b/drivers/media/platform/qcom/venus/core.c
@@ -224,13 +224,15 @@ static int venus_probe(struct platform_device *pdev)
ret = dma_set_mask_and_coherent(dev, core->res->dma_mask);
if (ret)
- return ret;
+ goto err_core_put;
if (!dev->dma_parms) {
dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms),
GFP_KERNEL);
- if (!dev->dma_parms)
- return -ENOMEM;
+ if (!dev->dma_parms) {
+ ret = -ENOMEM;
+ goto err_core_put;
+ }
}
dma_set_max_seg_size(dev, DMA_BIT_MASK(32));
@@ -242,11 +244,11 @@ static int venus_probe(struct platform_device *pdev)
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
"venus", core);
if (ret)
- return ret;
+ goto err_core_put;
ret = hfi_create(core, _core_ops);
if (ret)
- return ret;
+ goto err_core_put;
pm_runtime_enable(dev);
@@ -302,6 +304,9 @@ static int venus_probe(struct platform_device *pdev)
pm_runtime_set_suspended(dev);
pm_runtime_disable(dev);
hfi_destroy(core);
+err_core_put:
+ if (core->pm_ops->core_put)
+ core->pm_ops->core_put(dev);
return ret;
}
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v6 0/5] DVFS support for Venus
Rob, can you pick PATCH 1 since its already reviewed by you. Stan, Patch 2 and 3 will need to be picked by you and they both have your ACKs Patch 4 and 5 will need to be merged via the qcom tree once we have them reviewed. v6: No changes, rebased on 5.9-rc3 v5: Fixed the opp-tables (patch 4/5) to avoid -ERANGE from dev_pm_opp_set_rate v4: Moved code from probe/remove/runtime_suspend into different pm_ops callbacks v3: Renamed the optional power domain as cx v2: Fixed up the labels of OPP nodes in patch 4 Included the bindings update patch as part of this series, a resend of https://lore.kernel.org/patchwork/patch/1241077/ These patches add DVFS support for Venus Rajendra Nayak (5): dt-bindings: media: venus: Add an optional power domain for perf voting media: venus: core: Fix error handling in probe media: venus: core: Add support for opp tables/perf voting arm64: dts: sdm845: Add OPP tables and power-domains for venus arm64: dts: sc7180: Add OPP tables and power-domains for venus .../bindings/media/qcom,sc7180-venus.yaml | 6 +- .../bindings/media/qcom,sdm845-venus-v2.yaml | 6 +- arch/arm64/boot/dts/qcom/sc7180.dtsi | 35 +++- arch/arm64/boot/dts/qcom/sdm845.dtsi | 40 +- drivers/media/platform/qcom/venus/core.c | 17 ++-- drivers/media/platform/qcom/venus/core.h | 5 ++ drivers/media/platform/qcom/venus/pm_helpers.c | 92 -- 7 files changed, 183 insertions(+), 18 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v6 1/5] dt-bindings: media: venus: Add an optional power domain for perf voting
Venus needs to vote for the performance state of a power domain (cx) to be able to support DVFS. This 'cx' power domain is controlled by rpmh and is a common power domain (scalable) not specific to venus alone. This is optional in the sense that, leaving this power domain out does not really impact the functionality but just makes the platform a little less power efficient. Signed-off-by: Rajendra Nayak Reviewed-by: Rob Herring Reviewed-by: Bjorn Andersson --- Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml| 6 +- Documentation/devicetree/bindings/media/qcom,sdm845-venus-v2.yaml | 6 +- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml index 55f2d67..04e303b 100644 --- a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml @@ -25,12 +25,16 @@ properties: maxItems: 1 power-domains: -maxItems: 2 +minItems: 2 +maxItems: 3 power-domain-names: +minItems: 2 +maxItems: 3 items: - const: venus - const: vcodec0 + - const: cx clocks: maxItems: 5 diff --git a/Documentation/devicetree/bindings/media/qcom,sdm845-venus-v2.yaml b/Documentation/devicetree/bindings/media/qcom,sdm845-venus-v2.yaml index 157dff8..90013d4 100644 --- a/Documentation/devicetree/bindings/media/qcom,sdm845-venus-v2.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sdm845-venus-v2.yaml @@ -25,13 +25,17 @@ properties: maxItems: 1 power-domains: -maxItems: 3 +minItems: 3 +maxItems: 4 power-domain-names: +minItems: 3 +maxItems: 4 items: - const: venus - const: vcodec0 - const: vcodec1 + - const: cx clocks: maxItems: 7 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v6 5/5] arm64: dts: sc7180: Add OPP tables and power-domains for venus
Add the OPP tables in order to be able to vote on the performance state
of a power-domain
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 35 +--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index d46b383..94a0ec4 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2691,8 +2691,10 @@
reg = <0 0x0aa0 0 0xff000>;
interrupts = ;
power-domains = < VENUS_GDSC>,
- < VCODEC0_GDSC>;
- power-domain-names = "venus", "vcodec0";
+ < VCODEC0_GDSC>,
+ < SC7180_CX>;
+ power-domain-names = "venus", "vcodec0", "cx";
+ operating-points-v2 = <_opp_table>;
clocks = < VIDEO_CC_VENUS_CTL_CORE_CLK>,
< VIDEO_CC_VENUS_AHB_CLK>,
< VIDEO_CC_VENUS_CTL_AXI_CLK>,
@@ -2713,6 +2715,35 @@
video-encoder {
compatible = "venus-encoder";
};
+
+ venus_opp_table: venus-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-15000 {
+ opp-hz = /bits/ 64 <15000>;
+ required-opps = <_opp_low_svs>;
+ };
+
+ opp-27000 {
+ opp-hz = /bits/ 64 <27000>;
+ required-opps = <_opp_svs>;
+ };
+
+ opp-34000 {
+ opp-hz = /bits/ 64 <34000>;
+ required-opps = <_opp_svs_l1>;
+ };
+
+ opp-43400 {
+ opp-hz = /bits/ 64 <43400>;
+ required-opps = <_opp_nom>;
+ };
+
+ opp-50097 {
+ opp-hz = /bits/ 64 <50097>;
+ required-opps = <_opp_turbo>;
+ };
+ };
};
videocc: clock-controller@ab0 {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
[PATCH v6 3/5] media: venus: core: Add support for opp tables/perf voting
Add support to add OPP tables and perf voting on the OPP powerdomain.
This is needed so venus votes on the corresponding performance state
for the OPP powerdomain along with setting the core clock rate.
Signed-off-by: Rajendra Nayak
Reviewed-by: Matthias Kaehlcke
Acked-by: Stanimir Varbanov
Reviewed-by: Bjorn Andersson
---
drivers/media/platform/qcom/venus/core.c | 2 +
drivers/media/platform/qcom/venus/core.h | 5 ++
drivers/media/platform/qcom/venus/pm_helpers.c | 92 --
3 files changed, 92 insertions(+), 7 deletions(-)
diff --git a/drivers/media/platform/qcom/venus/core.c
b/drivers/media/platform/qcom/venus/core.c
index bfcaba3..a3e98a5 100644
--- a/drivers/media/platform/qcom/venus/core.c
+++ b/drivers/media/platform/qcom/venus/core.c
@@ -525,6 +525,7 @@ static const struct venus_resources sdm845_res_v2 = {
.vcodec_clks_num = 2,
.vcodec_pmdomains = { "venus", "vcodec0", "vcodec1" },
.vcodec_pmdomains_num = 3,
+ .opp_pmdomain = (const char *[]) { "cx", NULL },
.vcodec_num = 2,
.max_load = 3110400,/* 4096x2160@90 */
.hfi_version = HFI_VERSION_4XX,
@@ -570,6 +571,7 @@ static const struct venus_resources sc7180_res = {
.vcodec_clks_num = 2,
.vcodec_pmdomains = { "venus", "vcodec0" },
.vcodec_pmdomains_num = 2,
+ .opp_pmdomain = (const char *[]) { "cx", NULL },
.vcodec_num = 1,
.hfi_version = HFI_VERSION_4XX,
.vmem_id = VIDC_RESOURCE_NONE,
diff --git a/drivers/media/platform/qcom/venus/core.h
b/drivers/media/platform/qcom/venus/core.h
index 7118612..b0cc544 100644
--- a/drivers/media/platform/qcom/venus/core.h
+++ b/drivers/media/platform/qcom/venus/core.h
@@ -62,6 +62,7 @@ struct venus_resources {
unsigned int vcodec_clks_num;
const char * const vcodec_pmdomains[VIDC_PMDOMAINS_NUM_MAX];
unsigned int vcodec_pmdomains_num;
+ const char **opp_pmdomain;
unsigned int vcodec_num;
enum hfi_version hfi_version;
u32 max_load;
@@ -145,8 +146,12 @@ struct venus_core {
struct clk *vcodec1_clks[VIDC_VCODEC_CLKS_NUM_MAX];
struct icc_path *video_path;
struct icc_path *cpucfg_path;
+ struct opp_table *opp_table;
+ bool has_opp_table;
struct device_link *pd_dl_venus;
struct device *pmdomains[VIDC_PMDOMAINS_NUM_MAX];
+ struct device_link *opp_dl_venus;
+ struct device *opp_pmdomain;
struct video_device *vdev_dec;
struct video_device *vdev_enc;
struct v4l2_device v4l2_dev;
diff --git a/drivers/media/platform/qcom/venus/pm_helpers.c
b/drivers/media/platform/qcom/venus/pm_helpers.c
index 531e7a4..3127af8 100644
--- a/drivers/media/platform/qcom/venus/pm_helpers.c
+++ b/drivers/media/platform/qcom/venus/pm_helpers.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -66,10 +67,9 @@ static void core_clks_disable(struct venus_core *core)
static int core_clks_set_rate(struct venus_core *core, unsigned long freq)
{
- struct clk *clk = core->clks[0];
int ret;
- ret = clk_set_rate(clk, freq);
+ ret = dev_pm_opp_set_rate(core->dev, freq);
if (ret)
return ret;
@@ -744,13 +744,16 @@ static int venc_power_v4(struct device *dev, int on)
static int vcodec_domains_get(struct device *dev)
{
+ int ret;
+ struct opp_table *opp_table;
+ struct device **opp_virt_dev;
struct venus_core *core = dev_get_drvdata(dev);
const struct venus_resources *res = core->res;
struct device *pd;
unsigned int i;
if (!res->vcodec_pmdomains_num)
- return -ENODEV;
+ goto skip_pmdomains;
for (i = 0; i < res->vcodec_pmdomains_num; i++) {
pd = dev_pm_domain_attach_by_name(dev,
@@ -767,7 +770,41 @@ static int vcodec_domains_get(struct device *dev)
if (!core->pd_dl_venus)
return -ENODEV;
+skip_pmdomains:
+ if (!core->has_opp_table)
+ return 0;
+
+ /* Attach the power domain for setting performance state */
+ opp_table = dev_pm_opp_attach_genpd(dev, res->opp_pmdomain,
_virt_dev);
+ if (IS_ERR(opp_table)) {
+ ret = PTR_ERR(opp_table);
+ goto opp_attach_err;
+ }
+
+ core->opp_pmdomain = *opp_virt_dev;
+ core->opp_dl_venus = device_link_add(dev, core->opp_pmdomain,
+DL_FLAG_RPM_ACTIVE |
+DL_FLAG_PM_RUNTIME |
+DL_FLAG_STATELESS);
+ if (!core->opp_dl_venus) {
+ ret = -ENODEV;
+ goto opp_dl_add_err;
+ }
+
return 0;
+
+opp_dl_add_err:
+ dev_pm_domain_detach(core
[PATCH v6 4/5] arm64: dts: sdm845: Add OPP tables and power-domains for venus
Add the OPP tables in order to be able to vote on the performance state of
a power-domain.
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 40 ++--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 2884577..86457d9b 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -3639,8 +3639,10 @@
interrupts = ;
power-domains = < VENUS_GDSC>,
< VCODEC0_GDSC>,
- < VCODEC1_GDSC>;
- power-domain-names = "venus", "vcodec0", "vcodec1";
+ < VCODEC1_GDSC>,
+ < SDM845_CX>;
+ power-domain-names = "venus", "vcodec0", "vcodec1",
"cx";
+ operating-points-v2 = <_opp_table>;
clocks = < VIDEO_CC_VENUS_CTL_CORE_CLK>,
< VIDEO_CC_VENUS_AHB_CLK>,
< VIDEO_CC_VENUS_CTL_AXI_CLK>,
@@ -3662,6 +3664,40 @@
video-core1 {
compatible = "venus-encoder";
};
+
+ venus_opp_table: venus-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-1 {
+ opp-hz = /bits/ 64 <1>;
+ required-opps = <_opp_min_svs>;
+ };
+
+ opp-2 {
+ opp-hz = /bits/ 64 <2>;
+ required-opps = <_opp_low_svs>;
+ };
+
+ opp-32000 {
+ opp-hz = /bits/ 64 <32000>;
+ required-opps = <_opp_svs>;
+ };
+
+ opp-38000 {
+ opp-hz = /bits/ 64 <38000>;
+ required-opps = <_opp_svs_l1>;
+ };
+
+ opp-44400 {
+ opp-hz = /bits/ 64 <44400>;
+ required-opps = <_opp_nom>;
+ };
+
+ opp-53397 {
+ opp-hz = /bits/ 64 <53397>;
+ required-opps = <_opp_turbo>;
+ };
+ };
};
videocc: clock-controller@ab0 {
--
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of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH V2 3/8] drm/msm: Unconditionally call dev_pm_opp_of_remove_table()
On 9/1/2020 2:08 PM, Viresh Kumar wrote: On 01-09-20, 13:01, Rajendra Nayak wrote: So FWIU, dpu_unbind() gets called even when dpu_bind() fails for some reason. Ahh, I see. I tried to address that earlier [1] which I realized did not land. I don't think that patch was required, as you can call dev_pm_opp_put_clkname() multiple times and it will return without any errors/crash. We did see a crash (Sai had reported it), perhaps with dsi [1] and not this driver. But it was the same scenario that was possible here as well, which is dev_pm_opp_put_clkname() getting called without dev_pm_opp_set_clkname() being done. I think we ended up passing a NULL as opp_table in that case and the function tries de-referencing it. But with these changes it will be even more broken unless we identify if we failed dpu_bind() before adding the OPP table, while adding it, or all went well with opps and handle things accordingly in dpu_unbind. Maybe not as dev_pm_opp_of_remove_table() can be called multiple times as well without any errors or crash. Can it be called without the driver ever doing a dev_pm_opp_of_add_table()? [1] https://lore.kernel.org/patchwork/patch/1275628/ -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH V2 3/8] drm/msm: Unconditionally call dev_pm_opp_of_remove_table()
On 8/28/2020 11:37 AM, Viresh Kumar wrote:
dev_pm_opp_of_remove_table() doesn't report any errors when it fails to
find the OPP table with error -ENODEV (i.e. OPP table not present for
the device). And we can call dev_pm_opp_of_remove_table()
unconditionally here.
Its a little tricky to call things unconditionally for this driver, more below.
While at it, also create a label to put clkname.
Signed-off-by: Viresh Kumar
---
V2:
- Compare with -ENODEV only for failures.
- Create new label to put clkname.
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 14 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 -
drivers/gpu/drm/msm/dsi/dsi_host.c | 8 ++--
3 files changed, 7 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index c0a4d4e16d82..c8287191951f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1010,12 +1010,9 @@ static int dpu_bind(struct device *dev, struct device
*master, void *data)
return PTR_ERR(dpu_kms->opp_table);
/* OPP table is optional */
ret = dev_pm_opp_of_add_table(dev);
- if (!ret) {
- dpu_kms->has_opp_table = true;
- } else if (ret != -ENODEV) {
+ if (ret && ret != -ENODEV) {
dev_err(dev, "invalid OPP table in device tree\n");
- dev_pm_opp_put_clkname(dpu_kms->opp_table);
- return ret;
+ goto put_clkname;
So FWIU, dpu_unbind() gets called even when dpu_bind() fails for some reason.
I tried to address that earlier [1] which I realized did not land. But with
these changes
it will be even more broken unless we identify if we failed dpu_bind() before
adding the OPP table, while adding it, or all went well with opps and handle
things
accordingly in dpu_unbind.
[1] https://lore.kernel.org/patchwork/patch/1275632/
}
mp = _kms->mp;
@@ -1037,8 +1034,8 @@ static int dpu_bind(struct device *dev, struct device
*master, void *data)
priv->kms = _kms->base;
return ret;
err:
- if (dpu_kms->has_opp_table)
- dev_pm_opp_of_remove_table(dev);
+ dev_pm_opp_of_remove_table(dev);
+put_clkname:
dev_pm_opp_put_clkname(dpu_kms->opp_table);
return ret;
}
@@ -1056,8 +1053,7 @@ static void dpu_unbind(struct device *dev, struct device
*master, void *data)
if (dpu_kms->rpm_enabled)
pm_runtime_disable(>dev);
- if (dpu_kms->has_opp_table)
- dev_pm_opp_of_remove_table(dev);
+ dev_pm_opp_of_remove_table(dev);
dev_pm_opp_put_clkname(dpu_kms->opp_table);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index e140cd633071..8295979a7165 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -129,7 +129,6 @@ struct dpu_kms {
bool rpm_enabled;
struct opp_table *opp_table;
- bool has_opp_table;
struct dss_module_power mp;
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index b17ac6c27554..4335fe33250c 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -113,7 +113,6 @@ struct msm_dsi_host {
struct clk *byte_intf_clk;
struct opp_table *opp_table;
- bool has_opp_table;
u32 byte_clk_rate;
u32 pixel_clk_rate;
@@ -1891,9 +1890,7 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi)
return PTR_ERR(msm_host->opp_table);
/* OPP table is optional */
ret = dev_pm_opp_of_add_table(>dev);
- if (!ret) {
- msm_host->has_opp_table = true;
- } else if (ret != -ENODEV) {
+ if (ret && ret != -ENODEV) {
dev_err(>dev, "invalid OPP table in device tree\n");
dev_pm_opp_put_clkname(msm_host->opp_table);
return ret;
@@ -1934,8 +1931,7 @@ void msm_dsi_host_destroy(struct mipi_dsi_host *host)
mutex_destroy(_host->cmd_mutex);
mutex_destroy(_host->dev_mutex);
- if (msm_host->has_opp_table)
- dev_pm_opp_of_remove_table(_host->pdev->dev);
+ dev_pm_opp_of_remove_table(_host->pdev->dev);
dev_pm_opp_put_clkname(msm_host->opp_table);
pm_runtime_disable(_host->pdev->dev);
}
--
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of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH V3 0/4] opp: general cleanups
On 8/20/2020 1:26 PM, Viresh Kumar wrote: Hi, Here is another version of the cleanups I sent earlier. Rajendra: Please see if these work fine now. I gave these a quick spin, and they don';t result in the crash I earlier observed Tested-by: Rajendra Nayak V3: - Dropped v2 1/4 as it is already merged. - New patch 4/4 added. - Reordered the first two patches here (Stephen) - disable regulator only if present Viresh Kumar (4): opp: Rename regulator_enabled and use it as status of all resources opp: Track device's resources configuration status opp: Split out _opp_set_rate_zero() opp: Remove _dev_pm_opp_find_and_remove_table() wrapper drivers/opp/core.c | 103 + drivers/opp/cpu.c | 2 +- drivers/opp/of.c | 2 +- drivers/opp/opp.h | 5 +-- 4 files changed, 52 insertions(+), 60 deletions(-) -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 3/4] opp: Reused enabled flag and remove regulator_enabled
On 8/13/2020 9:59 AM, Viresh Kumar wrote:
The common "enabled" flag can be used here instead of
"regulator_enabled" now.
Signed-off-by: Viresh Kumar
---
drivers/opp/core.c | 13 +++--
drivers/opp/opp.h | 2 --
2 files changed, 3 insertions(+), 12 deletions(-)
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index e8882e7fd8a5..5f5da257f58a 100644
--- a/drivers/opp/core.c
+++ b/drivers/opp/core.c
@@ -703,12 +703,10 @@ static int _generic_set_opp_regulator(struct opp_table
*opp_table,
* Enable the regulator after setting its voltages, otherwise it breaks
* some boot-enabled regulators.
*/
- if (unlikely(!opp_table->regulator_enabled)) {
+ if (unlikely(!opp_table->enabled)) {
ret = regulator_enable(reg);
if (ret < 0)
dev_warn(dev, "Failed to enable regulator: %d", ret);
- else
- opp_table->regulator_enabled = true;
}
return 0;
@@ -905,10 +903,7 @@ int dev_pm_opp_set_rate(struct device *dev, unsigned long
target_freq)
if (ret)
goto put_opp_table;
- if (opp_table->regulator_enabled) {
- regulator_disable(opp_table->regulators[0]);
- opp_table->regulator_enabled = false;
- }
+ regulator_disable(opp_table->regulators[0]);
unconditionally calling regulator_disable() here based on the common
'enabled' flag results in a crash on platforms without regulators
associated with the opp table.
ret = _set_required_opps(dev, opp_table, NULL);
if (!ret)
@@ -1795,11 +1790,9 @@ void dev_pm_opp_put_regulators(struct opp_table
*opp_table)
/* Make sure there are no concurrent readers while updating opp_table */
WARN_ON(!list_empty(_table->opp_list));
- if (opp_table->regulator_enabled) {
+ if (opp_table->enabled) {
for (i = opp_table->regulator_count - 1; i >= 0; i--)
regulator_disable(opp_table->regulators[i]);
-
- opp_table->regulator_enabled = false;
}
for (i = opp_table->regulator_count - 1; i >= 0; i--)
diff --git a/drivers/opp/opp.h b/drivers/opp/opp.h
index bd35802acc6e..0c3de3f6db5c 100644
--- a/drivers/opp/opp.h
+++ b/drivers/opp/opp.h
@@ -147,7 +147,6 @@ enum opp_table_access {
* @clk: Device's clock handle
* @regulators: Supply regulators
* @regulator_count: Number of power supply regulators. Its value can be -1
- * @regulator_enabled: Set to true if regulators were previously enabled.
* (uninitialized), 0 (no opp-microvolt property) or > 0 (has opp-microvolt
* property).
* @paths: Interconnect path handles
@@ -196,7 +195,6 @@ struct opp_table {
struct clk *clk;
struct regulator **regulators;
int regulator_count;
- bool regulator_enabled;
struct icc_path **paths;
unsigned int path_count;
bool enabled;
--
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of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH] opp: Fix dev_pm_opp_set_rate() to not return early
On 8/13/2020 9:59 AM, Viresh Kumar wrote: On 11-08-20, 14:09, Stephen Boyd wrote: This is a goto maze! Any chance we can clean this up? I have sent a short series in reply to this series, please have a look. It should look better now. Thanks, I was out a few days so could not get to the cleanups that Stephen was suggesting. I will give your series a try. -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
[PATCH] arm64: dts: sdm845: Fixup OPP table for all qup devices
This OPP table was based on the clock VDD-FMAX tables seen in
downstream code, however it turns out the downstream clock
driver does update these tables based on later/production
rev of the chip and whats seen in the tables belongs to an
early engineering rev of the SoC.
Fix up the OPP tables such that it now matches with the
production rev of sdm845 SoC.
Fixes: 13cadb34e593 ("arm64: dts: sdm845: Add OPP table for all qup
devices")
Reported-by: John Stultz
Signed-off-by: Rajendra Nayak
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 2884577..eca81cf 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1093,8 +1093,8 @@
qup_opp_table: qup-opp-table {
compatible = "operating-points-v2";
- opp-1920 {
- opp-hz = /bits/ 64 <1920>;
+ opp-5000 {
+ opp-hz = /bits/ 64 <5000>;
required-opps = <_opp_min_svs>;
};
@@ -1107,6 +1107,11 @@
opp-hz = /bits/ 64 <1>;
required-opps = <_opp_svs>;
};
+
+ opp-12800 {
+ opp-hz = /bits/ 64 <12800>;
+ required-opps = <_opp_nom>;
+ };
};
qupv3_id_0: geniqup@8c {
--
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Re: [RFC v2 03/11] tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state
On 8/12/2020 1:09 PM, Rajendra Nayak wrote: On 8/12/2020 1:05 PM, Amit Pundir wrote: Hi Rajendra, On Wed, 12 Aug 2020 at 11:18, Rajendra Nayak wrote: On 8/12/2020 7:03 AM, John Stultz wrote: On Tue, Aug 11, 2020 at 4:11 PM John Stultz wrote: On Wed, Mar 20, 2019 at 2:49 AM Rajendra Nayak wrote: geni serial needs to express a perforamnce state requirement on CX depending on the frequency of the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. Signed-off-by: Rajendra Nayak Signed-off-by: Stephen Boyd --- drivers/tty/serial/qcom_geni_serial.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) Hey, I just wanted to follow up on this patch, as I've bisected it (a5819b548af0) down as having broken qca bluetooth on the Dragonboard 845c. I haven't yet had time to debug it yet, but wanted to raise the issue in case anyone else has seen similar trouble. So I dug in a bit further, and this chunk seems to be causing the issue: @@ -961,7 +963,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, goto out_restart_rx; uport->uartclk = clk_rate; - clk_set_rate(port->se.clk, clk_rate); + dev_pm_opp_set_rate(port->dev, clk_rate); ser_clk_cfg = SER_CLK_EN; ser_clk_cfg |= clk_div << CLK_DIV_SHFT; With that applied, I see the following errors in dmesg and bluetooth fails to function: [ 4.763467] qcom_geni_serial 898000.serial: dev_pm_opp_set_rate: failed to find OPP for freq 10240 (-34) [ 4.773493] qcom_geni_serial 898000.serial: dev_pm_opp_set_rate: failed to find OPP for freq 10240 (-34) With just that chunk reverted on linus/HEAD, bluetooth seems to work ok. This seems like the same issue that was also reported on venus [1] because the clock frequency tables apparently don;t exactly match the achievable clock frequencies (which we also used to construct the OPP tables) Can you try updating the OPP table for QUP to have 10240 instead of the current 1 and see if that fixes it? That worked. Thanks. Should this change be common to base sdm845.dtsi or platform specific dts? For what it's worth, we see this BT breakage on PocoF1 phone too. Thanks for confirming, it will have to be part of the SoC dtsi, and I am guessing a similar change is perhaps also needed on sc7180. I will send a patch out to fix the OPP tables for both. I spent some more time looking at this and it does not look like this is the rounding issues with clock FMAX tables. I had these tables picked from downstream clock code and it turns out these tables were reworked at clock init based on the silicon rev, so I need to fix up the OPP tables accordingly which will add a new OPP entry for 102.4Mhz. I'll post a patch shortly. Regards, Amit Pundir [1] https://lkml.org/lkml/2020/7/27/507 thanks -john -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [RFC v2 03/11] tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state
On 8/12/2020 1:05 PM, Amit Pundir wrote: Hi Rajendra, On Wed, 12 Aug 2020 at 11:18, Rajendra Nayak wrote: On 8/12/2020 7:03 AM, John Stultz wrote: On Tue, Aug 11, 2020 at 4:11 PM John Stultz wrote: On Wed, Mar 20, 2019 at 2:49 AM Rajendra Nayak wrote: geni serial needs to express a perforamnce state requirement on CX depending on the frequency of the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. Signed-off-by: Rajendra Nayak Signed-off-by: Stephen Boyd --- drivers/tty/serial/qcom_geni_serial.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) Hey, I just wanted to follow up on this patch, as I've bisected it (a5819b548af0) down as having broken qca bluetooth on the Dragonboard 845c. I haven't yet had time to debug it yet, but wanted to raise the issue in case anyone else has seen similar trouble. So I dug in a bit further, and this chunk seems to be causing the issue: @@ -961,7 +963,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, goto out_restart_rx; uport->uartclk = clk_rate; - clk_set_rate(port->se.clk, clk_rate); + dev_pm_opp_set_rate(port->dev, clk_rate); ser_clk_cfg = SER_CLK_EN; ser_clk_cfg |= clk_div << CLK_DIV_SHFT; With that applied, I see the following errors in dmesg and bluetooth fails to function: [4.763467] qcom_geni_serial 898000.serial: dev_pm_opp_set_rate: failed to find OPP for freq 10240 (-34) [4.773493] qcom_geni_serial 898000.serial: dev_pm_opp_set_rate: failed to find OPP for freq 10240 (-34) With just that chunk reverted on linus/HEAD, bluetooth seems to work ok. This seems like the same issue that was also reported on venus [1] because the clock frequency tables apparently don;t exactly match the achievable clock frequencies (which we also used to construct the OPP tables) Can you try updating the OPP table for QUP to have 10240 instead of the current 1 and see if that fixes it? That worked. Thanks. Should this change be common to base sdm845.dtsi or platform specific dts? For what it's worth, we see this BT breakage on PocoF1 phone too. Thanks for confirming, it will have to be part of the SoC dtsi, and I am guessing a similar change is perhaps also needed on sc7180. I will send a patch out to fix the OPP tables for both. Regards, Amit Pundir [1] https://lkml.org/lkml/2020/7/27/507 thanks -john -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH] OPP: Put opp table in dev_pm_opp_set_rate() all the time
On 8/12/2020 2:58 AM, Stephen Boyd wrote:
We get the opp_table pointer at the top of the function and so we should
put the pointer at the end of the function like all other exit paths
from this function do.
Cc: Rajendra Nayak
Fixes: aca48b61f963 ("opp: Manage empty OPP tables with clk handle")
Signed-off-by: Stephen Boyd
Thanks for the fix.
Reviewed-by: Rajendra Nayak
---
drivers/opp/core.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index 9d7fb45b1786..bdb028c7793d 100644
--- a/drivers/opp/core.c
+++ b/drivers/opp/core.c
@@ -893,8 +893,10 @@ int dev_pm_opp_set_rate(struct device *dev, unsigned long
target_freq)
* have OPP table for the device, while others don't and
* opp_set_rate() just needs to behave like clk_set_rate().
*/
- if (!_get_opp_count(opp_table))
- return 0;
+ if (!_get_opp_count(opp_table)) {
+ ret = 0;
+ goto put_opp_table;
+ }
if (!opp_table->required_opp_tables && !opp_table->regulators &&
!opp_table->paths) {
@@ -905,7 +907,7 @@ int dev_pm_opp_set_rate(struct device *dev, unsigned long
target_freq)
ret = _set_opp_bw(opp_table, NULL, dev, true);
if (ret)
- return ret;
+ goto put_opp_table;
if (opp_table->regulator_enabled) {
regulator_disable(opp_table->regulators[0]);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Re: [RFC v2 03/11] tty: serial: qcom_geni_serial: Use OPP API to set clk/perf state
On 8/12/2020 7:03 AM, John Stultz wrote: On Tue, Aug 11, 2020 at 4:11 PM John Stultz wrote: On Wed, Mar 20, 2019 at 2:49 AM Rajendra Nayak wrote: geni serial needs to express a perforamnce state requirement on CX depending on the frequency of the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. Signed-off-by: Rajendra Nayak Signed-off-by: Stephen Boyd --- drivers/tty/serial/qcom_geni_serial.c | 15 +-- 1 file changed, 13 insertions(+), 2 deletions(-) Hey, I just wanted to follow up on this patch, as I've bisected it (a5819b548af0) down as having broken qca bluetooth on the Dragonboard 845c. I haven't yet had time to debug it yet, but wanted to raise the issue in case anyone else has seen similar trouble. So I dug in a bit further, and this chunk seems to be causing the issue: @@ -961,7 +963,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport, goto out_restart_rx; uport->uartclk = clk_rate; - clk_set_rate(port->se.clk, clk_rate); + dev_pm_opp_set_rate(port->dev, clk_rate); ser_clk_cfg = SER_CLK_EN; ser_clk_cfg |= clk_div << CLK_DIV_SHFT; With that applied, I see the following errors in dmesg and bluetooth fails to function: [4.763467] qcom_geni_serial 898000.serial: dev_pm_opp_set_rate: failed to find OPP for freq 10240 (-34) [4.773493] qcom_geni_serial 898000.serial: dev_pm_opp_set_rate: failed to find OPP for freq 10240 (-34) With just that chunk reverted on linus/HEAD, bluetooth seems to work ok. This seems like the same issue that was also reported on venus [1] because the clock frequency tables apparently don;t exactly match the achievable clock frequencies (which we also used to construct the OPP tables) Can you try updating the OPP table for QUP to have 10240 instead of the current 1 and see if that fixes it? [1] https://lkml.org/lkml/2020/7/27/507 thanks -john -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
