from:"Yongqiang Niu"

Re: [PATCH v2, 3/5] Revert "dt-bindings: mailbox: mtk-gce: fix incorrect mbox-cells value"

2021-04-13 Thread Yongqiang Niu

On Wed, 2021-04-14 at 07:38 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
> 
> Yongqiang Niu  於 2021年4月12日 週一 下午7:19寫道：
> >
> > This reverts commit f83b03fc727ab56a77e68713d6e40299698f3c9f.
> >
> > Signed-off-by: Yongqiang Niu 
> > ---
> >  Documentation/devicetree/bindings/mailbox/mtk-gce.txt | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt 
> > b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
> > index 7771eca..cf48cd8 100644
> > --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
> > +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
> > @@ -47,7 +47,7 @@ Example:
> > interrupts = ;
> > clocks = < CLK_INFRA_GCE>;
> > clock-names = "gce";
> > -   #mbox-cells = <2>;
> > +   #mbox-cells = <3>;
> 
> I think we should not change the binding just to fix software bug.
> I think there are many temporary solution to fix drm bug. If drm bug
> is caused by cursor plane, you could temporarily let drm not support
> cursor plane to fix it (in [1], do not return DRM_PLANE_TYPE_CURSOR).
> But I would like you to find out the correct solution rather than a
> temporary solution because this bug is not so urgent. (For me, bug of
> build fail, boot fail, black screen is urgent).
> 
> [1] 
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/mediatek/mtk_drm_crtc.c?h=v5.12-rc7#n699
> 
> Regards,
> Chun-Kuang.

this not drm bug, but caused by cmdq patch
https://patchwork.kernel.org/project/linux-mediatek/patch/20200214043325.16618-3-bibby.hs...@mediatek.com/
before this patch, drm cursor and ui works well
after this patch, ui will flash when move cursor

this is critical issue,

> 
> > };
> >
> >  Example for a client device:
> > --
> > 1.8.1.1.dirty
> >

[PATCH v7, 5/5] drm/mediatek: add support for mediatek SOC MT8192

2021-04-12 Thread Yongqiang Niu

add support for mediatek SOC MT8192

Signed-off-by: Yongqiang Niu 
Signed-off-by: Hsin-Yi Wang 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c |  6 +
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c   | 20 +++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c  |  6 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c| 42 +++
 4 files changed, 74 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
index 141cb36..3a53ebc 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -205,9 +205,15 @@ static int mtk_disp_ccorr_remove(struct platform_device 
*pdev)
.matrix_bits = 10,
 };
 
+static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = {
+   .matrix_bits = 11,
+};
+
 static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
{ .compatible = "mediatek,mt8183-disp-ccorr",
  .data = _ccorr_driver_data},
+   { .compatible = "mediatek,mt8192-disp-ccorr",
+ .data = _ccorr_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 961f87f..e266baa 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -455,6 +455,22 @@ static int mtk_disp_ovl_remove(struct platform_device 
*pdev)
.fmt_rgb565_is_0 = true,
 };
 
+static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
+   .addr = DISP_REG_OVL_ADDR_MT8173,
+   .gmc_bits = 10,
+   .layer_nr = 4,
+   .fmt_rgb565_is_0 = true,
+   .smi_id_en = true,
+};
+
+static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
+   .addr = DISP_REG_OVL_ADDR_MT8173,
+   .gmc_bits = 10,
+   .layer_nr = 2,
+   .fmt_rgb565_is_0 = true,
+   .smi_id_en = true,
+};
+
 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-ovl",
  .data = _ovl_driver_data},
@@ -464,6 +480,10 @@ static int mtk_disp_ovl_remove(struct platform_device 
*pdev)
  .data = _ovl_driver_data},
{ .compatible = "mediatek,mt8183-disp-ovl-2l",
  .data = _ovl_2l_driver_data},
+   { .compatible = "mediatek,mt8192-disp-ovl",
+ .data = _ovl_driver_data},
+   { .compatible = "mediatek,mt8192-disp-ovl-2l",
+ .data = _ovl_2l_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 8c9371b..274f3ce 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -355,6 +355,10 @@ static int mtk_disp_rdma_remove(struct platform_device 
*pdev)
.fifo_size = 5 * SZ_1K,
 };
 
+static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
+   .fifo_size = 5 * SZ_1K,
+};
+
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
  .data = _rdma_driver_data},
@@ -362,6 +366,8 @@ static int mtk_disp_rdma_remove(struct platform_device 
*pdev)
  .data = _rdma_driver_data},
{ .compatible = "mediatek,mt8183-disp-rdma",
  .data = _rdma_driver_data},
+   { .compatible = "mediatek,mt8192-disp-rdma",
+ .data = _rdma_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c 
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b013d56..6df5510 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -147,6 +147,25 @@
DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
+   DDP_COMPONENT_OVL0,
+   DDP_COMPONENT_OVL_2L0,
+   DDP_COMPONENT_RDMA0,
+   DDP_COMPONENT_COLOR0,
+   DDP_COMPONENT_CCORR,
+   DDP_COMPONENT_AAL0,
+   DDP_COMPONENT_GAMMA,
+   DDP_COMPONENT_POSTMASK0,
+   DDP_COMPONENT_DITHER,
+   DDP_COMPONENT_DSI0,
+};
+
+static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
+   DDP_COMPONENT_OVL_2L2,
+   DDP_COMPONENT_RDMA4,
+   DDP_COMPONENT_DPI0,
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -186,6 +205,13 @@
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
+   .main_path = mt8192_mtk_ddp_main,
+   .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
+   .ext_path = mt8192_mtk_ddp_ext,
+   .ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
+};
+
 static int mtk_drm_kms_

[PATCH v7, 3/5] drm/mediatek: add component RDMA4

2021-04-12 Thread Yongqiang Niu

This patch add component RDMA4

Signed-off-by: Yongqiang Niu 
Reviewed-by: Chun-Kuang Hu 
Signed-off-by: Hsin-Yi Wang 
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 17309ce..ebe8eec 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -434,6 +434,7 @@ struct mtk_ddp_comp_match {
[DDP_COMPONENT_RDMA0]   = { MTK_DISP_RDMA,  0, _rdma },
[DDP_COMPONENT_RDMA1]   = { MTK_DISP_RDMA,  1, _rdma },
[DDP_COMPONENT_RDMA2]   = { MTK_DISP_RDMA,  2, _rdma },
+   [DDP_COMPONENT_RDMA4]   = { MTK_DISP_RDMA,  4, _rdma },
[DDP_COMPONENT_UFOE]= { MTK_DISP_UFOE,  0, _ufoe },
[DDP_COMPONENT_WDMA0]   = { MTK_DISP_WDMA,  0, NULL },
[DDP_COMPONENT_WDMA1]   = { MTK_DISP_WDMA,  1, NULL },
-- 
1.8.1.1.dirty

[PATCH v7, 4/5] soc: mediatek: add mtk mutex support for MT8192

2021-04-12 Thread Yongqiang Niu

Add mtk mutex support for MT8192 SoC.

Signed-off-by: Yongqiang Niu 
Signed-off-by: Hsin-Yi Wang 
Reviewed-by: CK Hu 
---
 drivers/soc/mediatek/mtk-mutex.c | 35 +++
 1 file changed, 35 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 718a41b..dfd9806 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -39,6 +39,18 @@
 #define MT8167_MUTEX_MOD_DISP_DITHER   15
 #define MT8167_MUTEX_MOD_DISP_UFOE 16
 
+#define MT8192_MUTEX_MOD_DISP_OVL0 0
+#define MT8192_MUTEX_MOD_DISP_OVL0_2L  1
+#define MT8192_MUTEX_MOD_DISP_RDMA02
+#define MT8192_MUTEX_MOD_DISP_COLOR0   4
+#define MT8192_MUTEX_MOD_DISP_CCORR0   5
+#define MT8192_MUTEX_MOD_DISP_AAL0 6
+#define MT8192_MUTEX_MOD_DISP_GAMMA0   7
+#define MT8192_MUTEX_MOD_DISP_POSTMASK08
+#define MT8192_MUTEX_MOD_DISP_DITHER0  9
+#define MT8192_MUTEX_MOD_DISP_OVL2_2L  16
+#define MT8192_MUTEX_MOD_DISP_RDMA417
+
 #define MT8183_MUTEX_MOD_DISP_RDMA00
 #define MT8183_MUTEX_MOD_DISP_RDMA11
 #define MT8183_MUTEX_MOD_DISP_OVL0 9
@@ -214,6 +226,20 @@ struct mtk_mutex_ctx {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
 };
 
+static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+   [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
+   [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
+   [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
+   [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
+   [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
+   [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
+   [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
+   [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L,
+   [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L,
+   [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0,
+   [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
+};
+
 static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
@@ -275,6 +301,13 @@ struct mtk_mutex_ctx {
.no_clk = true,
 };
 
+static const struct mtk_mutex_data mt8192_mutex_driver_data = {
+   .mutex_mod = mt8192_mutex_mod,
+   .mutex_sof = mt8183_mutex_sof,
+   .mutex_mod_reg = MT8183_MUTEX0_MOD0,
+   .mutex_sof_reg = MT8183_MUTEX0_SOF0,
+};
+
 struct mtk_mutex *mtk_mutex_get(struct device *dev)
 {
struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -507,6 +540,8 @@ static int mtk_mutex_remove(struct platform_device *pdev)
  .data = _mutex_driver_data},
{ .compatible = "mediatek,mt8183-disp-mutex",
  .data = _mutex_driver_data},
+   { .compatible = "mediatek,mt8192-disp-mutex",
+ .data = _mutex_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
-- 
1.8.1.1.dirty

[PATCH v7, 1/5] drm/mediatek: add component OVL_2L2

2021-04-12 Thread Yongqiang Niu

This patch add component OVL_2L2

Signed-off-by: Yongqiang Niu 
Reviewed-by: Chun-Kuang Hu 
Signed-off-by: Hsin-Yi Wang 
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 75bc00e..b564513 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -385,6 +385,7 @@ struct mtk_ddp_comp_match {
[DDP_COMPONENT_OVL1]= { MTK_DISP_OVL,   1, _ovl },
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L,0, _ovl },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L,1, _ovl },
+   [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L,2, _ovl },
[DDP_COMPONENT_PWM0]= { MTK_DISP_PWM,   0, NULL },
[DDP_COMPONENT_PWM1]= { MTK_DISP_PWM,   1, NULL },
[DDP_COMPONENT_PWM2]= { MTK_DISP_PWM,   2, NULL },
-- 
1.8.1.1.dirty

[PATCH v7, 0/5] drm/mediatek: add support for mediatek SOC MT8192

2021-04-12 Thread Yongqiang Niu

This series are based on Linux v5.12-rc2
and following patch:
https://patchwork.kernel.org/project/linux-mediatek/cover/1618236288-1617-1-git-send-email-yongqiang@mediatek.com/

Change since v6:
- rebase


Yongqiang Niu (5):
  drm/mediatek: add component OVL_2L2
  drm/mediatek: add component POSTMASK
  drm/mediatek: add component RDMA4
  soc: mediatek: add mtk mutex support for MT8192
  drm/mediatek: add support for mediatek SOC MT8192

 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c   |   6 ++
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c |  20 ++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c|   6 ++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  42 
 drivers/soc/mediatek/mtk-mutex.c|  35 ++
 7 files changed, 183 insertions(+), 29 deletions(-)

-- 
1.8.1.1.dirty

[PATCH v7, 2/5] drm/mediatek: add component POSTMASK

2021-04-12 Thread Yongqiang Niu

This patch add component POSTMASK.

Signed-off-by: Yongqiang Niu 
Signed-off-by: Hsin-Yi Wang 
Reviewed-by: CK Hu 
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 102 
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 2 files changed, 73 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index b564513..17309ce 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -50,6 +50,12 @@
 
 #define AAL_EN BIT(0)
 
+#define DISP_POSTMASK_EN   0x
+#define POSTMASK_ENBIT(0)
+#define DISP_POSTMASK_CFG  0x0020
+#define POSTMASK_RELAY_MODEBIT(0)
+#define DISP_POSTMASK_SIZE 0x0030
+
 #define DISP_DITHERING BIT(2)
 #define DITHER_LSB_ERR_SHIFT_R(x)  (((x) & 0x7) << 28)
 #define DITHER_OVFLW_BIT_R(x)  (((x) & 0x7) << 24)
@@ -190,6 +196,32 @@ static void mtk_ufoe_start(struct device *dev)
writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
 }
 
+static void mtk_postmask_config(struct device *dev, unsigned int w,
+   unsigned int h, unsigned int vrefresh,
+   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+   struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+   mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, priv->regs,
+ DISP_POSTMASK_SIZE);
+   mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, >cmdq_reg,
+ priv->regs, DISP_POSTMASK_CFG);
+}
+
+static void mtk_postmask_start(struct device *dev)
+{
+   struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+   writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN);
+}
+
+static void mtk_postmask_stop(struct device *dev)
+{
+   struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+   writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN);
+}
+
 static void mtk_aal_config(struct device *dev, unsigned int w,
   unsigned int h, unsigned int vrefresh,
   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -321,6 +353,14 @@ static void mtk_dither_stop(struct device *dev)
.bgclr_in_off = mtk_ovl_bgclr_in_off,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_postmask = {
+   .clk_enable = mtk_ddp_clk_enable,
+   .clk_disable = mtk_ddp_clk_disable,
+   .config = mtk_postmask_config,
+   .start = mtk_postmask_start,
+   .stop = mtk_postmask_stop,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_rdma = {
.clk_enable = mtk_rdma_clk_enable,
.clk_disable = mtk_rdma_clk_disable,
@@ -356,6 +396,7 @@ static void mtk_dither_stop(struct device *dev)
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
[MTK_DISP_BLS] = "bls",
+   [MTK_DISP_POSTMASK] = "postmask",
 };
 
 struct mtk_ddp_comp_match {
@@ -365,36 +406,37 @@ struct mtk_ddp_comp_match {
 };
 
 static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = 
{
-   [DDP_COMPONENT_AAL0]= { MTK_DISP_AAL,   0, _aal },
-   [DDP_COMPONENT_AAL1]= { MTK_DISP_AAL,   1, _aal },
-   [DDP_COMPONENT_BLS] = { MTK_DISP_BLS,   0, NULL },
-   [DDP_COMPONENT_CCORR]   = { MTK_DISP_CCORR, 0, _ccorr },
-   [DDP_COMPONENT_COLOR0]  = { MTK_DISP_COLOR, 0, _color },
-   [DDP_COMPONENT_COLOR1]  = { MTK_DISP_COLOR, 1, _color },
-   [DDP_COMPONENT_DITHER]  = { MTK_DISP_DITHER,0, _dither },
-   [DDP_COMPONENT_DPI0]= { MTK_DPI,0, _dpi },
-   [DDP_COMPONENT_DPI1]= { MTK_DPI,1, _dpi },
-   [DDP_COMPONENT_DSI0]= { MTK_DSI,0, _dsi },
-   [DDP_COMPONENT_DSI1]= { MTK_DSI,1, _dsi },
-   [DDP_COMPONENT_DSI2]= { MTK_DSI,2, _dsi },
-   [DDP_COMPONENT_DSI3]= { MTK_DSI,3, _dsi },
-   [DDP_COMPONENT_GAMMA]   = { MTK_DISP_GAMMA, 0, _gamma },
-   [DDP_COMPONENT_OD0] = { MTK_DISP_OD,0, _od },
-   [DDP_COMPONENT_OD1] = { MTK_DISP_OD,1, _od },
-   [DDP_COMPONENT_OVL0]= { MTK_DISP_OVL,   0, _ovl },
-   [DDP_COMPONENT_OVL1]= { MTK_DISP_OVL,   1, _ovl },
-   [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L,0, _ovl },
-   [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L,1, _ovl },
-   [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L,2, _ovl },
-   [DDP_COMPONENT_PWM0]= { MTK_DISP_PWM,   0, NULL },
-   [DDP_COMPONENT_PWM1]= { MTK_DISP_PWM,   1, NULL },
-   [DDP_COMPONENT_PWM2]= { MTK_DISP_PWM,   2, NULL },
-   [DDP_COMPONENT_RDMA0]   = { MTK_DISP_RDMA,  0, _rdma },
-   [DDP_COMPONENT_RDMA1]

[PATCH v5, 2/4] soc: mediatek: mmsys: add component POSTMASK

2021-04-12 Thread Yongqiang Niu

This patch add component POSTMASK

Signed-off-by: Yongqiang Niu 
---
 include/linux/soc/mediatek/mtk-mmsys.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/soc/mediatek/mtk-mmsys.h 
b/include/linux/soc/mediatek/mtk-mmsys.h
index f6b58f9..7718cd6 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -31,6 +31,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL_2L1,
DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
+   DDP_COMPONENT_POSTMASK0,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
DDP_COMPONENT_PWM2,
-- 
1.8.1.1.dirty

[PATCH v5, 4/4] soc: mediatek: mmsys: Add mt8192 mmsys routing table

2021-04-12 Thread Yongqiang Niu

mt8192 has different routing registers than mt8183

Signed-off-by: Yongqiang Niu 
---
 drivers/soc/mediatek/mt8192-mmsys.h | 68 +
 drivers/soc/mediatek/mtk-mmsys.c|  7 
 2 files changed, 75 insertions(+)
 create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h

diff --git a/drivers/soc/mediatek/mt8192-mmsys.h 
b/drivers/soc/mediatek/mt8192-mmsys.h
new file mode 100644
index 000..3179029
--- /dev/null
+++ b/drivers/soc/mediatek/mt8192-mmsys.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8192_MMSYS_H
+#define __SOC_MEDIATEK_MT8192_MMSYS_H
+
+#define MT8192_MMSYS_OVL_MOUT_EN   0xf04
+#define MT8192_DISP_OVL1_2L_MOUT_EN0xf08
+#define MT8192_DISP_OVL0_2L_MOUT_EN0xf18
+#define MT8192_DISP_OVL0_MOUT_EN   0xf1c
+#define MT8192_DISP_RDMA0_SEL_IN   0xf2c
+#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30
+#define MT8192_DISP_CCORR0_SOUT_SEL0xf34
+#define MT8192_DISP_AAL0_SEL_IN0xf38
+#define MT8192_DISP_DITHER0_MOUT_EN0xf3c
+#define MT8192_DISP_DSI0_SEL_IN0xf40
+#define MT8192_DISP_OVL2_2L_MOUT_EN0xf4c
+
+#define MT8192_DISP_OVL0_GO_BLEND  BIT(0)
+#define MT8192_DITHER0_MOUT_IN_DSI0BIT(0)
+#define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
+#define MT8192_OVL2_2L_MOUT_EN_RDMA4   BIT(0)
+#define MT8192_DISP_OVL0_GO_BG BIT(1)
+#define MT8192_DISP_OVL0_2L_GO_BLEND   BIT(2)
+#define MT8192_DISP_OVL0_2L_GO_BG  BIT(3)
+#define MT8192_OVL1_2L_MOUT_EN_RDMA1   BIT(4)
+#define MT8192_OVL0_MOUT_EN_OVL0_2LBIT(4)
+#define MT8192_RDMA0_SEL_IN_OVL0_2L0x3
+#define MT8192_RDMA0_SOUT_COLOR0   0x1
+#define MT8192_CCORR0_SOUT_AAL00x1
+#define MT8192_AAL0_SEL_IN_CCORR0  0x1
+#define MT8192_DSI0_SEL_IN_DITHER0 0x1
+
+static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
+   {
+   DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+   MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
+   }, {
+   DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4,
+   MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4
+   }, {
+   DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+   MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0
+   }, {
+   DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+   MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L
+   }, {
+   DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
+   MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0
+   }, {
+   DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+   MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0
+   }, {
+   DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
+   MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0
+   }, {
+   DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
+   MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0
+   }, {
+   DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
+   MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
+   }, {
+   DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+   MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
+   }
+};
+
+#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */
+
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 79e5515..c755617 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -12,6 +12,7 @@
 
 #include "mtk-mmsys.h"
 #include "mt8183-mmsys.h"
+#include "mt8192-mmsys.h"
 
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
@@ -45,6 +46,12 @@
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
 };
 
+static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
+   .clk_driver = "clk-mt8192-mm",
+   .routes = mmsys_mt8192_routing_table,
+   .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
+};
+
 struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
-- 
1.8.1.1.dirty

[PATCH v5, 1/4] soc: mediatek: mmsys: add component OVL_2L2

2021-04-12 Thread Yongqiang Niu

This patch add component OVL_2L2

Signed-off-by: Yongqiang Niu 
Reviewed-by: Chun-Kuang Hu 
---
 include/linux/soc/mediatek/mtk-mmsys.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/soc/mediatek/mtk-mmsys.h 
b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6..f6b58f9 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -29,6 +29,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
+   DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
-- 
1.8.1.1.dirty

[PATCH v5, 3/4] soc: mediatek: mmsys: add component RDMA4

2021-04-12 Thread Yongqiang Niu

This patch add component RDMA4

Signed-off-by: Yongqiang Niu 
Reviewed-by: Chun-Kuang Hu 
---
 include/linux/soc/mediatek/mtk-mmsys.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/soc/mediatek/mtk-mmsys.h 
b/include/linux/soc/mediatek/mtk-mmsys.h
index 7718cd6..4bba275 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -38,6 +38,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_RDMA1,
DDP_COMPONENT_RDMA2,
+   DDP_COMPONENT_RDMA4,
DDP_COMPONENT_UFOE,
DDP_COMPONENT_WDMA0,
DDP_COMPONENT_WDMA1,
-- 
1.8.1.1.dirty

[PATCH v5, 0/4] soc: mediatek: mmsys: add mt8192 mmsys support

2021-04-12 Thread Yongqiang Niu

base 5.12-rc2 and
https://patchwork.kernel.org/project/linux-mediatek/patch/20210330110423.3542163-1-hsi...@chromium.org/

Change since v4:
- use routing table

Yongqiang Niu (4):
  soc: mediatek: mmsys: add component OVL_2L2
  soc: mediatek: mmsys: add component POSTMASK
  soc: mediatek: mmsys: add component RDMA4
  soc: mediatek: mmsys: Add mt8192 mmsys routing table

 drivers/soc/mediatek/mt8192-mmsys.h| 68 ++
 drivers/soc/mediatek/mtk-mmsys.c   |  7 
 include/linux/soc/mediatek/mtk-mmsys.h |  3 ++
 3 files changed, 78 insertions(+)
 create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h

-- 
1.8.1.1.dirty

[PATCH v4, 1/3] dt-binding: gce: add gce header file for mt8192

2021-04-12 Thread Yongqiang Niu

Add documentation for the mt8192 gce.

Add gce header file defined the gce hardware event,
subsys number and constant for mt8192.

Signed-off-by: Yongqiang Niu 
Reviewed-by: Rob Herring 
Signed-off-by: Hsin-Yi Wang 
---
 .../devicetree/bindings/mailbox/mtk-gce.txt|   7 +-
 include/dt-bindings/gce/mt8192-gce.h   | 335 +
 2 files changed, 339 insertions(+), 3 deletions(-)
 create mode 100644 include/dt-bindings/gce/mt8192-gce.h

diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt 
b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
index cf48cd8..f48ae45 100644
--- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
+++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
@@ -9,8 +9,8 @@ CMDQ driver uses mailbox framework for communication. Please 
refer to
 mailbox.txt for generic information about mailbox device-tree bindings.
 
 Required properties:
-- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or
-  "mediatek,mt6779-gce".
+- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce",
+  "mediatek,mt8192-gce" or "mediatek,mt6779-gce".
 - reg: Address range of the GCE unit
 - interrupts: The interrupt signal from the GCE block
 - clock: Clocks according to the common clock binding
@@ -36,7 +36,8 @@ Optional properties for a client device:
   size: the total size of register address that GCE can access.
 
 Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h',
-'dt-binding/gce/mt8183-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. Such as
+'dt-binding/gce/mt8183-gce.h', 'dt-binding/gce/mt8192-gce.h' or
+'dt-bindings/gce/mt6779-gce.h'. Such as
 sub-system ids, thread priority, event ids.
 
 Example:
diff --git a/include/dt-bindings/gce/mt8192-gce.h 
b/include/dt-bindings/gce/mt8192-gce.h
new file mode 100644
index 000..9e5a0eb
--- /dev/null
+++ b/include/dt-bindings/gce/mt8192-gce.h
@@ -0,0 +1,335 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Yongqiang Niu 
+ */
+
+#ifndef _DT_BINDINGS_GCE_MT8192_H
+#define _DT_BINDINGS_GCE_MT8192_H
+
+/* assign timeout 0 also means default */
+#define CMDQ_NO_TIMEOUT0x
+#define CMDQ_TIMEOUT_DEFAULT   1000
+
+/* GCE thread priority */
+#define CMDQ_THR_PRIO_LOWEST   0
+#define CMDQ_THR_PRIO_11
+#define CMDQ_THR_PRIO_22
+#define CMDQ_THR_PRIO_33
+#define CMDQ_THR_PRIO_44
+#define CMDQ_THR_PRIO_55
+#define CMDQ_THR_PRIO_66
+#define CMDQ_THR_PRIO_HIGHEST  7
+
+/* CPR count in 32bit register */
+#define GCE_CPR_COUNT  1312
+
+/* GCE subsys table */
+#define SUBSYS_13000
+#define SUBSYS_14001
+#define SUBSYS_14012
+#define SUBSYS_14023
+#define SUBSYS_15024
+#define SUBSYS_18805
+#define SUBSYS_18816
+#define SUBSYS_18827
+#define SUBSYS_18838
+#define SUBSYS_18849
+#define SUBSYS_100010
+#define SUBSYS_100111
+#define SUBSYS_100212
+#define SUBSYS_100313
+#define SUBSYS_100414
+#define SUBSYS_100515
+#define SUBSYS_102016
+#define SUBSYS_102817
+#define SUBSYS_170018
+#define SUBSYS_170119
+#define SUBSYS_170220
+#define SUBSYS_170321
+#define SUBSYS_180022
+#define SUBSYS_180123
+#define SUBSYS_180224
+#define SUBSYS_180425
+#define SUBSYS_180526
+#define SUBSYS_180827
+#define SUBSYS_180a28
+#define SUBSYS_180b29
+
+#define CMDQ_EVENT_VDEC_LAT_SOF_0  0
+#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_0   1
+#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_1   2
+#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_2   3
+#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_3   4
+#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_4   5
+#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_5   6
+#define CMDQ_EVENT_VDEC_LAT_FRAME_DONE_6   7
+#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_08
+#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_19
+#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_210
+#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_311
+#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_412
+#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_513
+#define CMDQ_EVENT_VDEC_LAT_ENG_EVENT_614
+#defin

[PATCH v4, 2/3] arm64: dts: mt8192: add gce node

2021-04-12 Thread Yongqiang Niu

add gce node for mt8192

Signed-off-by: Yongqiang Niu 
Signed-off-by: Hsin-Yi Wang 
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 9757138..1afa6ad 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -5,6 +5,7 @@
  */
 
 /dts-v1/;
+#include 
 #include 
 #include 
 #include 
@@ -291,6 +292,15 @@
clock-names = "clk13m";
};
 
+   gce: mailbox@10228000 {
+   compatible = "mediatek,mt8192-gce";
+   reg = <0 0x10228000 0 0x4000>;
+   interrupts = ;
+   #mbox-cells = <3>;
+   clocks = < CLK_INFRA_GCE>;
+   clock-names = "gce";
+   };
+
uart0: serial@11002000 {
compatible = "mediatek,mt8192-uart",
 "mediatek,mt6577-uart";
-- 
1.8.1.1.dirty

[PATCH v4, 3/3] mailbox: cmdq: add mt8192 support

2021-04-12 Thread Yongqiang Niu

add mt8192 support

Signed-off-by: Yongqiang Niu 
Signed-off-by: Hsin-Yi Wang 
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c 
b/drivers/mailbox/mtk-cmdq-mailbox.c
index e0d9a86..8da700a 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -36,6 +36,8 @@
 #define CMDQ_THR_WAIT_TOKEN0x30
 #define CMDQ_THR_PRIORITY  0x40
 
+#define GCE_GCTL_VALUE 0x48
+
 #define CMDQ_THR_ACTIVE_SLOT_CYCLES0x3200
 #define CMDQ_THR_ENABLED   0x1
 #define CMDQ_THR_DISABLED  0x0
@@ -77,11 +79,13 @@ struct cmdq {
struct clk  *clock;
boolsuspended;
u8  shift_pa;
+   boolcontrol_by_sw;
 };
 
 struct gce_plat {
u32 thread_nr;
u8 shift;
+   bool control_by_sw;
 };
 
 u8 cmdq_get_shift_pa(struct mbox_chan *chan)
@@ -122,6 +126,8 @@ static void cmdq_init(struct cmdq *cmdq)
int i;
 
WARN_ON(clk_enable(cmdq->clock) < 0);
+   if (cmdq->control_by_sw)
+   writel(0x7, cmdq->base + GCE_GCTL_VALUE);
writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES);
for (i = 0; i <= CMDQ_MAX_EVENT; i++)
writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE);
@@ -598,6 +604,7 @@ static int cmdq_probe(struct platform_device *pdev)
 
cmdq->thread_nr = plat_data->thread_nr;
cmdq->shift_pa = plat_data->shift;
+   cmdq->control_by_sw = plat_data->control_by_sw;
cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
   "mtk_cmdq", cmdq);
@@ -663,11 +670,14 @@ static int cmdq_probe(struct platform_device *pdev)
 static const struct gce_plat gce_plat_v2 = {.thread_nr = 16};
 static const struct gce_plat gce_plat_v3 = {.thread_nr = 24};
 static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3};
+static const struct gce_plat gce_plat_v5 = {.thread_nr = 24, .shift = 3,
+   .control_by_sw = true};
 
 static const struct of_device_id cmdq_of_ids[] = {
{.compatible = "mediatek,mt8173-gce", .data = (void *)_plat_v2},
{.compatible = "mediatek,mt8183-gce", .data = (void *)_plat_v3},
{.compatible = "mediatek,mt6779-gce", .data = (void *)_plat_v4},
+   {.compatible = "mediatek,mt8192-gce", .data = (void *)_plat_v5},
{}
 };
 
-- 
1.8.1.1.dirty

[PATCH v4, 0/3] support gce on mt8192 platform

2021-04-12 Thread Yongqiang Niu

Change since v3:
-fix review comment in v2

Change since v2:
- add controy_by_sw for mt8192

Change since v1:
- move out shift jump patch
- remove useless patch

Yongqiang Niu (3):
  dt-binding: gce: add gce header file for mt8192
  arm64: dts: mt8192: add gce node
  mailbox: cmdq: add mt8192 support

 .../devicetree/bindings/mailbox/mtk-gce.txt|   7 +-
 arch/arm64/boot/dts/mediatek/mt8192.dtsi   |  10 +
 drivers/mailbox/mtk-cmdq-mailbox.c |  10 +
 include/dt-bindings/gce/mt8192-gce.h   | 335 +
 4 files changed, 359 insertions(+), 3 deletions(-)
 create mode 100644 include/dt-bindings/gce/mt8192-gce.h

-- 
1.8.1.1.dirty

[PATCH v2, 5/5] arm64: dts: mediatek: mt8183: add gce information for mmsys

2021-04-12 Thread Yongqiang Niu

add gce information for mmsys

Signed-off-by: Yongqiang Niu 
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index bc89283..e3a8b10 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -983,6 +983,9 @@
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x1400 0 0x1000>;
#clock-cells = <1>;
+   mboxes = < 0 CMDQ_THR_PRIO_HIGHEST 1>,
+< 1 CMDQ_THR_PRIO_HIGHEST 1>;
+   mediatek,gce-client-reg = < SUBSYS_1400 0 
0x1000>;
};
 
ovl0: ovl@14008000 {
-- 
1.8.1.1.dirty

[PATCH v2, 2/5] Revert "mailbox: mediatek: remove implementation related to atomic_exec"

2021-04-12 Thread Yongqiang Niu

This reverts commit c9ea564f3d9dd20d88bd34f40a6ff6d31a0d7e8c.

Signed-off-by: Yongqiang Niu 
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 80 +-
 1 file changed, 71 insertions(+), 9 deletions(-)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c 
b/drivers/mailbox/mtk-cmdq-mailbox.c
index 5665b6e..e0d9a86 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -56,6 +56,7 @@ struct cmdq_thread {
void __iomem*base;
struct list_headtask_busy_list;
u32 priority;
+   boolatomic_exec;
 };
 
 struct cmdq_task {
@@ -168,18 +169,56 @@ static void cmdq_task_insert_into_thread(struct cmdq_task 
*task)
dma_sync_single_for_cpu(dev, prev_task->pa_base,
prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
-   (u64)CMDQ_JUMP_BY_PA << 32 | task->pa_base;
+   (u64)CMDQ_JUMP_BY_PA << 32 |
+   (task->pa_base >> task->cmdq->shift_pa);
dma_sync_single_for_device(dev, prev_task->pa_base,
   prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
 
cmdq_thread_invalidate_fetched_data(thread);
 }
 
+static bool cmdq_command_is_wfe(u64 cmd)
+{
+   u64 wfe_option = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE;
+   u64 wfe_op = (u64)(CMDQ_CODE_WFE << CMDQ_OP_CODE_SHIFT) << 32;
+   u64 wfe_mask = (u64)CMDQ_OP_CODE_MASK << 32 | 0x;
+
+   return ((cmd & wfe_mask) == (wfe_op | wfe_option));
+}
+
+/* we assume tasks in the same display GCE thread are waiting the same event. 
*/
+static void cmdq_task_remove_wfe(struct cmdq_task *task)
+{
+   struct device *dev = task->cmdq->mbox.dev;
+   u64 *base = task->pkt->va_base;
+   int i;
+
+   dma_sync_single_for_cpu(dev, task->pa_base, task->pkt->cmd_buf_size,
+   DMA_TO_DEVICE);
+   for (i = 0; i < CMDQ_NUM_CMD(task->pkt); i++)
+   if (cmdq_command_is_wfe(base[i]))
+   base[i] = (u64)CMDQ_JUMP_BY_OFFSET << 32 |
+ (CMDQ_JUMP_PASS >> task->cmdq->shift_pa);
+   dma_sync_single_for_device(dev, task->pa_base, task->pkt->cmd_buf_size,
+  DMA_TO_DEVICE);
+}
+
 static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread)
 {
return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING;
 }
 
+static void cmdq_thread_wait_end(struct cmdq_thread *thread,
+unsigned long end_pa)
+{
+   struct device *dev = thread->chan->mbox->dev;
+   unsigned long curr_pa;
+
+   if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_ADDR,
+   curr_pa, curr_pa == end_pa, 1, 20))
+   dev_err(dev, "GCE thread cannot run to end.\n");
+}
+
 static void cmdq_task_exec_done(struct cmdq_task *task, enum cmdq_cb_status 
sta)
 {
struct cmdq_task_cb *cb = >pkt->async_cb;
@@ -371,15 +410,37 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, 
void *data)
cmdq->shift_pa;
end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
cmdq->shift_pa;
-   /* check boundary */
-   if (curr_pa == end_pa - CMDQ_INST_SIZE ||
-   curr_pa == end_pa) {
-   /* set to this task directly */
-   writel(task->pa_base >> cmdq->shift_pa,
-  thread->base + CMDQ_THR_CURR_ADDR);
+
+   /*
+* Atomic execution should remove the following wfe, i.e. only
+* wait event at first task, and prevent to pause when running.
+*/
+   if (thread->atomic_exec) {
+   /* GCE is executing if command is not WFE */
+   if (!cmdq_thread_is_in_wfe(thread)) {
+   cmdq_thread_resume(thread);
+   cmdq_thread_wait_end(thread,
+end_pa >> cmdq->shift_pa);
+   WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
+   /* set to this task directly */
+   writel(task->pa_base >> cmdq->shift_pa,
+  thread->base + CMDQ_THR_CURR_ADDR);
+   } else {
+   cmdq_task_insert_into_thread(task);
+   cmdq_task_remove_wfe(task);
+   smp_mb(); /* modify jump before enable thread */
+

[PATCH v2, 1/5] Revert "drm/mediatek: Make sure previous message done or be aborted before send"

2021-04-12 Thread Yongqiang Niu

This reverts commit 839cbf0531428f3f9535077a461b8631359c1165.

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c 
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 8b0de90..c76f446 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -463,7 +463,6 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc 
*mtk_crtc)
}
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
if (mtk_crtc->cmdq_client) {
-   mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
-- 
1.8.1.1.dirty

[PATCH v2, 4/5] Revert "arm64: dts: mediatek: mt8183: fix gce incorrect mbox-cells value"

2021-04-12 Thread Yongqiang Niu

This reverts commit e55c56df43dd11de4a6c08e3ea52ca45b51c8800.

Signed-off-by: Yongqiang Niu 
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 80519a1..bc89283 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -541,7 +541,7 @@
compatible = "mediatek,mt8183-gce";
reg = <0 0x10238000 0 0x4000>;
interrupts = ;
-   #mbox-cells = <2>;
+   #mbox-cells = <3>;
clocks = < CLK_INFRA_GCE>;
clock-names = "gce";
};
-- 
1.8.1.1.dirty

[PATCH v2, 3/5] Revert "dt-bindings: mailbox: mtk-gce: fix incorrect mbox-cells value"

2021-04-12 Thread Yongqiang Niu

This reverts commit f83b03fc727ab56a77e68713d6e40299698f3c9f.

Signed-off-by: Yongqiang Niu 
---
 Documentation/devicetree/bindings/mailbox/mtk-gce.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt 
b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
index 7771eca..cf48cd8 100644
--- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
+++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
@@ -47,7 +47,7 @@ Example:
interrupts = ;
clocks = < CLK_INFRA_GCE>;
clock-names = "gce";
-   #mbox-cells = <2>;
+   #mbox-cells = <3>;
};
 
 Example for a client device:
-- 
1.8.1.1.dirty

[PATCH v2, 0/5] Revert "mailbox: mediatek: remove implementation related to atomic_exec"

2021-04-12 Thread Yongqiang Niu

This series base linux 5.12-rc2
these patches will cause home ui flick when cursor moved,
there is no fix solution yet, revert these patches first.

change since v1:
add mtk-gce.txt and dts modification

Yongqiang Niu (5):
  Revert "drm/mediatek: Make sure previous message done or be aborted
before send"
  Revert "mailbox: mediatek: remove implementation related to
atomic_exec"
  Revert "dt-bindings: mailbox: mtk-gce: fix incorrect mbox-cells value"
  Revert "arm64: dts: mediatek: mt8183: fix gce incorrect mbox-cells
value"
  arm64: dts: mediatek: mt8183: add gce information for mmsys

 .../devicetree/bindings/mailbox/mtk-gce.txt|  2 +-
 arch/arm64/boot/dts/mediatek/mt8183.dtsi   |  5 +-
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c|  1 -
 drivers/mailbox/mtk-cmdq-mailbox.c | 80 +++---
 4 files changed, 76 insertions(+), 12 deletions(-)

-- 
1.8.1.1.dirty

Re: [PATCH v1, 3/3] drm/mediatek: gamma set with cmdq

2021-04-12 Thread Yongqiang Niu

On Mon, 2021-04-12 at 16:28 +0800, CK Hu wrote:
> Hi, Yongqiang:
> 
> On Mon, 2021-04-12 at 14:35 +0800, Yongqiang Niu wrote:
> > gamma lut set in vsync active will caused display flash issue
> > set gamma lut with cmdq 
> 
> In MT8173, it's ok to set gammma out of vblank period. Why do you
> setting gamma in vblank in this patch?
> 
> Regards,
> CK
> 

mtk drm driver code has changed many since mt8173, there is no one test
this in the newest version for mt8173.

and this issue is random.
https://partnerissuetracker.corp.google.com/u/1/issues/153842418

and not all platform will set gamma lut.
some project platform will not set gamma lut from chrome os
(crhome os set gamma lut may be with some special panel, like AUO
B116XTN02.3 in
https://partnerissuetracker.corp.google.com/u/1/issues/153842418
)

> > 
> > Signed-off-by: Yongqiang Niu 
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_aal.c |  4 ++--
> >  drivers/gpu/drm/mediatek/mtk_disp_drv.h |  7 ---
> >  drivers/gpu/drm/mediatek/mtk_disp_gamma.c   | 11 ++-
> >  drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  8 +---
> >  5 files changed, 28 insertions(+), 20 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c 
> > b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> > index 64b4528..c8e178e 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
> > @@ -59,12 +59,12 @@ void mtk_aal_config(struct device *dev, unsigned int w,
> > mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, aal->regs, 
> > DISP_AAL_SIZE);
> >  }
> >  
> > -void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
> > +void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state, 
> > struct cmdq_pkt *cmdq_pkt)
> >  {
> > struct mtk_disp_aal *aal = dev_get_drvdata(dev);
> >  
> > if (aal->data && aal->data->has_gamma)
> > -   mtk_gamma_set_common(aal->regs, state);
> > +   mtk_gamma_set_common(aal->regs, >cmdq_reg, state, 
> > cmdq_pkt);
> >  }
> >  
> >  void mtk_aal_start(struct device *dev)
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h 
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index 86c3068..c2e7dcb 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -14,7 +14,7 @@
> >  void mtk_aal_config(struct device *dev, unsigned int w,
> > unsigned int h, unsigned int vrefresh,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > -void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state);
> > +void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state, 
> > struct cmdq_pkt *cmdq_pkt);
> >  void mtk_aal_start(struct device *dev);
> >  void mtk_aal_stop(struct device *dev);
> >  
> > @@ -50,8 +50,9 @@ void mtk_dither_set_common(void __iomem *regs, struct 
> > cmdq_client_reg *cmdq_reg,
> >  void mtk_gamma_config(struct device *dev, unsigned int w,
> >   unsigned int h, unsigned int vrefresh,
> >   unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > -void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state);
> > -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state 
> > *state);
> > +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state, 
> > struct cmdq_pkt *cmdq_pkt);
> > +void mtk_gamma_set_common(void __iomem *regs, struct cmdq_client_reg 
> > *cmdq_reg,
> > + struct drm_crtc_state *state, struct cmdq_pkt 
> > *cmdq_pkt);
> >  void mtk_gamma_start(struct device *dev);
> >  void mtk_gamma_stop(struct device *dev);
> >  
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c 
> > b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> > index 3ebf91e..99a4ff3 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> > @@ -55,7 +55,8 @@ void mtk_gamma_clk_disable(struct device *dev)
> > clk_disable_unprepare(gamma->clk);
> >  }
> >  
> > -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state)
> > +void mtk_gamma_set_common(void __iomem *regs, struct cmdq_client_reg 
> > *cmdq_reg,
> > + struct drm_crtc_state *state, struct cmdq_pkt 
> > *cmdq_pkt)
> >  {
> > unsigned int i,

[PATCH v1] drm/mediatek: adjust rdma fifo threshold calculate formula

2021-04-12 Thread Yongqiang Niu

the orginal formula will caused rdma fifo threshold config overflow

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 728aaad..8c9371b 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -167,7 +167,7 @@ void mtk_rdma_config(struct device *dev, unsigned int width,
 * output threshold to 6 microseconds with 7/6 overhead to
 * account for blanking, and with a pixel depth of 4 bytes:
 */
-   threshold = width * height * vrefresh * 4 * 7 / 100;
+   threshold = rdma_fifo_size * 7 / 10;
reg = RDMA_FIFO_UNDERFLOW_EN |
  RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
  RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
-- 
1.8.1.1.dirty

adjust rdma fifo threshold calculate formula

2021-04-12 Thread Yongqiang Niu

This patch base Linux 5.12-rc2 provide one patch

Yongqiang Niu (1):
  drm/mediatek: adjust rdma fifo threshold calculate formula

 drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
1.8.1.1.dirty

[PATCH v1, 1/3] drm/mediatek: Separate aal module

2021-04-12 Thread Yongqiang Niu

mt8183 aal has no gamma function

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/Makefile   |   3 +-
 drivers/gpu/drm/mediatek/mtk_disp_aal.c | 167 
 drivers/gpu/drm/mediatek/mtk_disp_drv.h |   9 ++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  39 +--
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |   8 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   1 +
 6 files changed, 187 insertions(+), 40 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_aal.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index dc54a7a..29098d7 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 
-mediatek-drm-y := mtk_disp_ccorr.o \
+mediatek-drm-y := mtk_disp_aal.o \
+ mtk_disp_ccorr.o \
  mtk_disp_color.o \
  mtk_disp_gamma.o \
  mtk_disp_ovl.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c 
b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
new file mode 100644
index 000..64b4528
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "mtk_disp_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+#define DISP_AAL_EN0x
+#define AAL_EN BIT(0)
+#define DISP_AAL_SIZE  0x0030
+
+
+struct mtk_disp_aal_data {
+   bool has_gamma;
+};
+
+/**
+ * struct mtk_disp_aal - DISP_AAL driver structure
+ * @ddp_comp - structure containing type enum and hardware resources
+ * @crtc - associated crtc to report irq events to
+ */
+struct mtk_disp_aal {
+   struct clk *clk;
+   void __iomem *regs;
+   struct cmdq_client_reg cmdq_reg;
+   const struct mtk_disp_aal_data *data;
+};
+
+int mtk_aal_clk_enable(struct device *dev)
+{
+   struct mtk_disp_aal *aal = dev_get_drvdata(dev);
+
+   return clk_prepare_enable(aal->clk);
+}
+
+void mtk_aal_clk_disable(struct device *dev)
+{
+   struct mtk_disp_aal *aal = dev_get_drvdata(dev);
+
+   clk_disable_unprepare(aal->clk);
+}
+
+void mtk_aal_config(struct device *dev, unsigned int w,
+  unsigned int h, unsigned int vrefresh,
+  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+   struct mtk_disp_aal *aal = dev_get_drvdata(dev);
+
+   mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, aal->regs, 
DISP_AAL_SIZE);
+}
+
+void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
+{
+   struct mtk_disp_aal *aal = dev_get_drvdata(dev);
+
+   if (aal->data && aal->data->has_gamma)
+   mtk_gamma_set_common(aal->regs, state);
+}
+
+void mtk_aal_start(struct device *dev)
+{
+   struct mtk_disp_aal *aal = dev_get_drvdata(dev);
+
+   writel(AAL_EN, aal->regs + DISP_AAL_EN);
+}
+
+void mtk_aal_stop(struct device *dev)
+{
+   struct mtk_disp_aal *aal = dev_get_drvdata(dev);
+
+   writel_relaxed(0x0, aal->regs + DISP_AAL_EN);
+}
+
+static int mtk_disp_aal_bind(struct device *dev, struct device *master,
+  void *data)
+{
+   return 0;
+}
+
+static void mtk_disp_aal_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_aal_component_ops = {
+   .bind   = mtk_disp_aal_bind,
+   .unbind = mtk_disp_aal_unbind,
+};
+
+static int mtk_disp_aal_probe(struct platform_device *pdev)
+{
+   struct device *dev = >dev;
+   struct mtk_disp_aal *priv;
+   struct resource *res;
+   int ret;
+
+   priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+   if (!priv)
+   return -ENOMEM;
+
+   priv->clk = devm_clk_get(dev, NULL);
+   if (IS_ERR(priv->clk)) {
+   dev_err(dev, "failed to get aal clk\n");
+   return PTR_ERR(priv->clk);
+   }
+
+   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+   priv->regs = devm_ioremap_resource(dev, res);
+   if (IS_ERR(priv->regs)) {
+   dev_err(dev, "failed to ioremap aal\n");
+   return PTR_ERR(priv->regs);
+   }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+   ret = cmdq_dev_get_client_reg(dev, >cmdq_reg, 0);
+   if (ret)
+   dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+   priv->data = of_device_get_match_data(dev);
+   platform_set_drvdata(pdev, priv);
+
+   ret = component_add(dev, _disp_aal_component_ops);
+   if (ret)
+   dev_err(dev, "Failed to add c

[PATCH v1, 3/3] drm/mediatek: gamma set with cmdq

2021-04-12 Thread Yongqiang Niu

gamma lut set in vsync active will caused display flash issue
set gamma lut with cmdq 

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_disp_aal.c |  4 ++--
 drivers/gpu/drm/mediatek/mtk_disp_drv.h |  7 ---
 drivers/gpu/drm/mediatek/mtk_disp_gamma.c   | 11 ++-
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 18 +++---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  8 +---
 5 files changed, 28 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c 
b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
index 64b4528..c8e178e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c
@@ -59,12 +59,12 @@ void mtk_aal_config(struct device *dev, unsigned int w,
mtk_ddp_write(cmdq_pkt, w << 16 | h, >cmdq_reg, aal->regs, 
DISP_AAL_SIZE);
 }
 
-void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
+void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state, 
struct cmdq_pkt *cmdq_pkt)
 {
struct mtk_disp_aal *aal = dev_get_drvdata(dev);
 
if (aal->data && aal->data->has_gamma)
-   mtk_gamma_set_common(aal->regs, state);
+   mtk_gamma_set_common(aal->regs, >cmdq_reg, state, 
cmdq_pkt);
 }
 
 void mtk_aal_start(struct device *dev)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h 
b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 86c3068..c2e7dcb 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -14,7 +14,7 @@
 void mtk_aal_config(struct device *dev, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
-void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state);
+void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state, 
struct cmdq_pkt *cmdq_pkt);
 void mtk_aal_start(struct device *dev);
 void mtk_aal_stop(struct device *dev);
 
@@ -50,8 +50,9 @@ void mtk_dither_set_common(void __iomem *regs, struct 
cmdq_client_reg *cmdq_reg,
 void mtk_gamma_config(struct device *dev, unsigned int w,
  unsigned int h, unsigned int vrefresh,
  unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
-void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state);
-void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
+void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state, struct 
cmdq_pkt *cmdq_pkt);
+void mtk_gamma_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
+ struct drm_crtc_state *state, struct cmdq_pkt 
*cmdq_pkt);
 void mtk_gamma_start(struct device *dev);
 void mtk_gamma_stop(struct device *dev);
 
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
index 3ebf91e..99a4ff3 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
@@ -55,7 +55,8 @@ void mtk_gamma_clk_disable(struct device *dev)
clk_disable_unprepare(gamma->clk);
 }
 
-void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state)
+void mtk_gamma_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
+ struct drm_crtc_state *state, struct cmdq_pkt 
*cmdq_pkt)
 {
unsigned int i, reg;
struct drm_color_lut *lut;
@@ -65,23 +66,23 @@ void mtk_gamma_set_common(void __iomem *regs, struct 
drm_crtc_state *state)
if (state->gamma_lut) {
reg = readl(regs + DISP_GAMMA_CFG);
reg = reg | GAMMA_LUT_EN;
-   writel(reg, regs + DISP_GAMMA_CFG);
+   mtk_ddp_write(cmdq_pkt, reg, cmdq_reg, regs, DISP_GAMMA_CFG);
lut_base = regs + DISP_GAMMA_LUT;
lut = (struct drm_color_lut *)state->gamma_lut->data;
for (i = 0; i < MTK_LUT_SIZE; i++) {
word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
(((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
((lut[i].blue >> 6) & LUT_10BIT_MASK);
-   writel(word, (lut_base + i * 4));
+   mtk_ddp_write(cmdq_pkt, word, cmdq_reg, regs, (lut_base 
+ i * 4));
}
}
 }
 
-void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state)
+void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state, struct 
cmdq_pkt *cmdq_pkt)
 {
struct mtk_disp_gamma *gamma = dev_get_drvdata(dev);
 
-   mtk_gamma_set_common(gamma->regs, state);
+   mtk_gamma_set_common(gamma->regs, >cmdq_reg, state, cmdq_pkt);
 }
 
 void mtk_gamma_config(struct device *dev, unsigned int w,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c 
b/drivers/gpu/drm/mediatek/mtk_drm_

[PATCH v1, 2/3] arm64: dts: mt8183: refine aal compatible name

2021-04-12 Thread Yongqiang Niu

mt8183 aal is different with mt8173
remove mt8173 compatible name for mt8183 aal

Signed-off-by: Yongqiang Niu 
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 80519a1..ee8f87f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1061,8 +1061,7 @@
};
 
aal0: aal@1401 {
-   compatible = "mediatek,mt8183-disp-aal",
-"mediatek,mt8173-disp-aal";
+   compatible = "mediatek,mt8183-disp-aal";
reg = <0 0x1401 0 0x1000>;
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
-- 
1.8.1.1.dirty

[PATCH v1, 0/3] gamma set with cmdq

2021-04-12 Thread Yongqiang Niu

This series are based on 5.12-rc2 and provide 3 patch
to set gamma lut with cmdq

Yongqiang Niu (3):
  drm/mediatek: Separate aal module
  arm64: dts: mt8183: refine aal compatible name
  drm/mediatek: gamma set with cmdq

 arch/arm64/boot/dts/mediatek/mt8183.dtsi|   3 +-
 drivers/gpu/drm/mediatek/Makefile   |   3 +-
 drivers/gpu/drm/mediatek/mtk_disp_aal.c | 167 
 drivers/gpu/drm/mediatek/mtk_disp_drv.h |  14 ++-
 drivers/gpu/drm/mediatek/mtk_disp_gamma.c   |  11 +-
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c |  18 +--
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  39 +--
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   8 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |   8 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   1 +
 10 files changed, 213 insertions(+), 59 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_aal.c

-- 
1.8.1.1.dirty

[RESEND PATCH v1 2/2] Revert "mailbox: mediatek: remove implementation related to atomic_exec"

2021-03-10 Thread Yongqiang Niu

This reverts commit c9ea564f3d9dd20d88bd34f40a6ff6d31a0d7e8c.

Signed-off-by: Yongqiang Niu 
---
 drivers/mailbox/mtk-cmdq-mailbox.c | 80 +-
 1 file changed, 71 insertions(+), 9 deletions(-)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c 
b/drivers/mailbox/mtk-cmdq-mailbox.c
index 5665b6e..e0d9a86 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -56,6 +56,7 @@ struct cmdq_thread {
void __iomem*base;
struct list_headtask_busy_list;
u32 priority;
+   boolatomic_exec;
 };
 
 struct cmdq_task {
@@ -168,18 +169,56 @@ static void cmdq_task_insert_into_thread(struct cmdq_task 
*task)
dma_sync_single_for_cpu(dev, prev_task->pa_base,
prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
-   (u64)CMDQ_JUMP_BY_PA << 32 | task->pa_base;
+   (u64)CMDQ_JUMP_BY_PA << 32 |
+   (task->pa_base >> task->cmdq->shift_pa);
dma_sync_single_for_device(dev, prev_task->pa_base,
   prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
 
cmdq_thread_invalidate_fetched_data(thread);
 }
 
+static bool cmdq_command_is_wfe(u64 cmd)
+{
+   u64 wfe_option = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE;
+   u64 wfe_op = (u64)(CMDQ_CODE_WFE << CMDQ_OP_CODE_SHIFT) << 32;
+   u64 wfe_mask = (u64)CMDQ_OP_CODE_MASK << 32 | 0x;
+
+   return ((cmd & wfe_mask) == (wfe_op | wfe_option));
+}
+
+/* we assume tasks in the same display GCE thread are waiting the same event. 
*/
+static void cmdq_task_remove_wfe(struct cmdq_task *task)
+{
+   struct device *dev = task->cmdq->mbox.dev;
+   u64 *base = task->pkt->va_base;
+   int i;
+
+   dma_sync_single_for_cpu(dev, task->pa_base, task->pkt->cmd_buf_size,
+   DMA_TO_DEVICE);
+   for (i = 0; i < CMDQ_NUM_CMD(task->pkt); i++)
+   if (cmdq_command_is_wfe(base[i]))
+   base[i] = (u64)CMDQ_JUMP_BY_OFFSET << 32 |
+ (CMDQ_JUMP_PASS >> task->cmdq->shift_pa);
+   dma_sync_single_for_device(dev, task->pa_base, task->pkt->cmd_buf_size,
+  DMA_TO_DEVICE);
+}
+
 static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread)
 {
return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING;
 }
 
+static void cmdq_thread_wait_end(struct cmdq_thread *thread,
+unsigned long end_pa)
+{
+   struct device *dev = thread->chan->mbox->dev;
+   unsigned long curr_pa;
+
+   if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_ADDR,
+   curr_pa, curr_pa == end_pa, 1, 20))
+   dev_err(dev, "GCE thread cannot run to end.\n");
+}
+
 static void cmdq_task_exec_done(struct cmdq_task *task, enum cmdq_cb_status 
sta)
 {
struct cmdq_task_cb *cb = >pkt->async_cb;
@@ -371,15 +410,37 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, 
void *data)
cmdq->shift_pa;
end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
cmdq->shift_pa;
-   /* check boundary */
-   if (curr_pa == end_pa - CMDQ_INST_SIZE ||
-   curr_pa == end_pa) {
-   /* set to this task directly */
-   writel(task->pa_base >> cmdq->shift_pa,
-  thread->base + CMDQ_THR_CURR_ADDR);
+
+   /*
+* Atomic execution should remove the following wfe, i.e. only
+* wait event at first task, and prevent to pause when running.
+*/
+   if (thread->atomic_exec) {
+   /* GCE is executing if command is not WFE */
+   if (!cmdq_thread_is_in_wfe(thread)) {
+   cmdq_thread_resume(thread);
+   cmdq_thread_wait_end(thread,
+end_pa >> cmdq->shift_pa);
+   WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
+   /* set to this task directly */
+   writel(task->pa_base >> cmdq->shift_pa,
+  thread->base + CMDQ_THR_CURR_ADDR);
+   } else {
+   cmdq_task_insert_into_thread(task);
+   cmdq_task_remove_wfe(task);
+   smp_mb(); /* modify jump before enable thread */
+

[RESEND PATCH v1 0/2] Revert "mailbox: mediatek: remove implementation related to atomic_exec"

2021-03-10 Thread Yongqiang Niu

This series base linux 5.12-rc1
these two patches will cause home ui flick when cursor moved,
there is no fix solution yet, revert these patches first.

change since v1:
fix build error

Yongqiang Niu (2):
  Revert "drm/mediatek: Make sure previous message done or be aborted
before send"
  Revert "mailbox: mediatek: remove implementation related to
atomic_exec"

 drivers/gpu/drm/mediatek/mtk_drm_crtc.c |  1 -
 drivers/mailbox/mtk-cmdq-mailbox.c  | 80 +
 2 files changed, 71 insertions(+), 10 deletions(-)

-- 
1.8.1.1.dirty

[RESEND PATCH v1 1/2] Revert "drm/mediatek: Make sure previous message done or be aborted before send"

2021-03-10 Thread Yongqiang Niu

This reverts commit 839cbf0531428f3f9535077a461b8631359c1165.

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c 
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 8b0de90..c76f446 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -463,7 +463,6 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc 
*mtk_crtc)
}
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
if (mtk_crtc->cmdq_client) {
-   mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
-- 
1.8.1.1.dirty

[PATCH v1 2/2] Revert "mailbox: mediatek: remove implementation related to atomic_exec"

2021-03-09 Thread Yongqiang Niu

This reverts commit c9ea564f3d9dd20d88bd34f40a6ff6d31a0d7e8c.

Signed-off-by: Yongqiang Niu pa_base,
prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
-   (u64)CMDQ_JUMP_BY_PA << 32 | task->pa_base;
+   (u64)CMDQ_JUMP_BY_PA << 32 |
+   (task->pa_base >> cmdq->shift_pa);
dma_sync_single_for_device(dev, prev_task->pa_base,
   prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
 
cmdq_thread_invalidate_fetched_data(thread);
 }
 
+static bool cmdq_command_is_wfe(u64 cmd)
+{
+   u64 wfe_option = CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE;
+   u64 wfe_op = (u64)(CMDQ_CODE_WFE << CMDQ_OP_CODE_SHIFT) << 32;
+   u64 wfe_mask = (u64)CMDQ_OP_CODE_MASK << 32 | 0x;
+
+   return ((cmd & wfe_mask) == (wfe_op | wfe_option));
+}
+
+/* we assume tasks in the same display GCE thread are waiting the same event. 
*/
+static void cmdq_task_remove_wfe(struct cmdq_task *task)
+{
+   struct device *dev = task->cmdq->mbox.dev;
+   u64 *base = task->pkt->va_base;
+   int i;
+
+   dma_sync_single_for_cpu(dev, task->pa_base, task->pkt->cmd_buf_size,
+   DMA_TO_DEVICE);
+   for (i = 0; i < CMDQ_NUM_CMD(task->pkt); i++)
+   if (cmdq_command_is_wfe(base[i]))
+   base[i] = (u64)CMDQ_JUMP_BY_OFFSET << 32 |
+ (CMDQ_JUMP_PASS >> task->cmdq->shift_pa);
+   dma_sync_single_for_device(dev, task->pa_base, task->pkt->cmd_buf_size,
+  DMA_TO_DEVICE);
+}
+
 static bool cmdq_thread_is_in_wfe(struct cmdq_thread *thread)
 {
return readl(thread->base + CMDQ_THR_WAIT_TOKEN) & CMDQ_THR_IS_WAITING;
 }
 
+static void cmdq_thread_wait_end(struct cmdq_thread *thread,
+unsigned long end_pa)
+{
+   struct device *dev = thread->chan->mbox->dev;
+   unsigned long curr_pa;
+
+   if (readl_poll_timeout_atomic(thread->base + CMDQ_THR_CURR_ADDR,
+   curr_pa, curr_pa == end_pa, 1, 20))
+   dev_err(dev, "GCE thread cannot run to end.\n");
+}
+
 static void cmdq_task_exec_done(struct cmdq_task *task, enum cmdq_cb_status 
sta)
 {
struct cmdq_task_cb *cb = >pkt->async_cb;
@@ -371,15 +410,37 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, 
void *data)
cmdq->shift_pa;
end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
cmdq->shift_pa;
-   /* check boundary */
-   if (curr_pa == end_pa - CMDQ_INST_SIZE ||
-   curr_pa == end_pa) {
-   /* set to this task directly */
-   writel(task->pa_base >> cmdq->shift_pa,
-  thread->base + CMDQ_THR_CURR_ADDR);
+
+   /*
+* Atomic execution should remove the following wfe, i.e. only
+* wait event at first task, and prevent to pause when running.
+*/
+   if (thread->atomic_exec) {
+   /* GCE is executing if command is not WFE */
+   if (!cmdq_thread_is_in_wfe(thread)) {
+   cmdq_thread_resume(thread);
+   cmdq_thread_wait_end(thread,
+end_pa >> cmdq->shift_pa);
+   WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
+   /* set to this task directly */
+   writel(task->pa_base >> cmdq->shift_pa,
+  thread->base + CMDQ_THR_CURR_ADDR);
+   } else {
+   cmdq_task_insert_into_thread(task);
+   cmdq_task_remove_wfe(task);
+   smp_mb(); /* modify jump before enable thread */
+   }
} else {
-   cmdq_task_insert_into_thread(task);
-   smp_mb(); /* modify jump before enable thread */
+   /* check boundary */
+   if (curr_pa == end_pa - CMDQ_INST_SIZE ||
+   curr_pa == end_pa) {
+   /* set to this task directly */
+   writel(task->pa_base >> cmdq->shift_pa,
+  thread->base + CMDQ_THR_CURR_ADDR);
+   } else {
+   cmdq_task_insert_into_thread(task);
+   smp_mb(); /* modify jump

[PATCH v1 0/2] Revert "mailbox: mediatek: remove implementation related to atomic_exec"

2021-03-09 Thread Yongqiang Niu

This series base linux 5.12-rc1
these two patches will cause home ui flick when cursor moved,
there is no fix solution yet, revert these patches first.

Yongqiang Niu (2):
  Revert "drm/mediatek: Make sure previous message done or be aborted
before send"
  Revert "mailbox: mediatek: remove implementation related to
atomic_exec"

 drivers/gpu/drm/mediatek/mtk_drm_crtc.c |  1 -
 drivers/mailbox/mtk-cmdq-mailbox.c  | 80 +
 2 files changed, 71 insertions(+), 10 deletions(-)

-- 
1.8.1.1.dirty

[PATCH v1 1/2] Revert "drm/mediatek: Make sure previous message done or be aborted before send"

2021-03-09 Thread Yongqiang Niu

This reverts commit 839cbf0531428f3f9535077a461b8631359c1165.

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c 
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 8b0de90..c76f446 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -463,7 +463,6 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc 
*mtk_crtc)
}
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
if (mtk_crtc->cmdq_client) {
-   mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
-- 
1.8.1.1.dirty

[PATCH v1] move page flip handle into cmdq cb

2021-02-19 Thread Yongqiang Niu

irq callback will before cmdq flush ddp register
into hardware, that will cause the display frame page
flip event before it realy display out time


Yongqiang Niu (1):
  CHROMIUM: drm/mediatek: move page flip handle into cmdq cb

 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 33 +
 1 file changed, 29 insertions(+), 4 deletions(-)

-- 
1.8.1.1.dirty

[PATCH v1] drm/mediatek: move page flip handle into cmdq cb

2021-02-19 Thread Yongqiang Niu

move page flip handle into cmdq cb
irq callback will before cmdq flush ddp register
into hardware, that will cause the display frame page
flip event before it realy display out time

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 33 +
 1 file changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c 
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index bdd37ea..bece327 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -72,6 +72,13 @@ struct mtk_crtc_state {
unsigned intpending_vrefresh;
 };
 
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+struct mtk_cmdq_cb_data {
+   struct cmdq_pkt *cmdq_handle;
+   struct mtk_drm_crtc *mtk_crtc;
+};
+#endif
+
 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
 {
return container_of(c, struct mtk_drm_crtc, base);
@@ -96,7 +103,6 @@ static void mtk_drm_crtc_finish_page_flip(struct 
mtk_drm_crtc *mtk_crtc)
 
 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc)
 {
-   drm_crtc_handle_vblank(_crtc->base);
if (mtk_crtc->pending_needs_vblank) {
mtk_drm_crtc_finish_page_flip(mtk_crtc);
mtk_crtc->pending_needs_vblank = false;
@@ -241,7 +247,19 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct 
drm_crtc *crtc,
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 static void ddp_cmdq_cb(struct cmdq_cb_data data)
 {
-   cmdq_pkt_destroy(data.data);
+   struct mtk_cmdq_cb_data *cb_data = data.data;
+
+   if (cb_data) {
+   struct mtk_drm_crtc *mtk_crtc = cb_data->mtk_crtc;
+
+   if (mtk_crtc)
+   mtk_drm_finish_page_flip(mtk_crtc);
+
+   if (cb_data->cmdq_handle)
+   cmdq_pkt_destroy(cb_data->cmdq_handle);
+
+   kfree(cb_data);
+   }
 }
 #endif
 
@@ -481,13 +499,20 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc 
*mtk_crtc)
}
 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
if (mtk_crtc->cmdq_client) {
+   struct mtk_cmdq_cb_data *cb_data;
+
mbox_flush(mtk_crtc->cmdq_client->chan, 2000);
cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
mtk_crtc_ddp_config(crtc, cmdq_handle);
cmdq_pkt_finalize(cmdq_handle);
-   cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle);
+
+   cb_data = kmalloc(sizeof(*cb_data), GFP_KERNEL);
+   cb_data->cmdq_handle = cmdq_handle;
+   cb_data->mtk_crtc = mtk_crtc;
+
+   cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cb_data);
}
 #endif
mutex_unlock(_crtc->hw_lock);
@@ -674,7 +699,7 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct 
mtk_ddp_comp *comp)
 #endif
mtk_crtc_ddp_config(crtc, NULL);
 
-   mtk_drm_finish_page_flip(mtk_crtc);
+   drm_crtc_handle_vblank(_crtc->base);
 }
 
 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc,
-- 
1.8.1.1.dirty

Re: [PATCH v12 6/8] drm/mediatek: enable dither function

2021-01-28 Thread Yongqiang Niu

On Fri, 2021-01-29 at 14:46 +0800, Hsin-Yi Wang wrote:
> On Fri, Jan 29, 2021 at 2:30 PM Yongqiang Niu
>  wrote:
> >
> > On Fri, 2021-01-29 at 14:24 +0800, Hsin-Yi Wang wrote:
> > > On Fri, Jan 29, 2021 at 9:33 AM CK Hu  wrote:
> > > >
> > > > Hi, Hsin-Yi:
> > > >
> > > > On Thu, 2021-01-28 at 19:23 +0800, Hsin-Yi Wang wrote:
> > > > > From: Yongqiang Niu 
> > > > >
> > > > > for 5 or 6 bpc panel, we need enable dither function
> > > > > to improve the display quality
> > > > >
> > > > > Signed-off-by: Yongqiang Niu 
> > > > > Signed-off-by: Hsin-Yi Wang 
> > > > > ---
> > > > >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +--
> > > > >  1 file changed, 13 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
> > > > > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > index ac2cb25620357..6c8f246380a74 100644
> > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > @@ -53,6 +53,7 @@
> > > > >  #define DITHER_ENBIT(0)
> > > > >  #define DISP_DITHER_CFG  0x0020
> > > > >  #define DITHER_RELAY_MODEBIT(0)
> > > > > +#define DITHER_ENGINE_EN BIT(1)
> > > > >  #define DISP_DITHER_SIZE 0x0030
> > > > >
> > > > >  #define LUT_10BIT_MASK   0x03ff
> > > > > @@ -314,9 +315,19 @@ static void mtk_dither_config(struct device 
> > > > > *dev, unsigned int w,
> > > > > unsigned int bpc, struct cmdq_pkt 
> > > > > *cmdq_pkt)
> > > > >  {
> > > > >   struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > > > > + bool enable = (bpc == 5 || bpc == 6);
> > > >
> > > > I strongly believe that dither function in dither is identical to the
> > > > one in gamma and od, and in mtk_dither_set_common(), 'bpc >=
> > > > MTK_MIN_BPC' is valid, so I believe we need not to limit bpc to 5 or 6.
> > > > But we should consider the case that bpc is invalid in
> > > > mtk_dither_set_common(). Invalid case in gamma and od use different way
> > > > to process. For gamma, dither is default relay mode, so invalid bpc
> > > > would do nothing in mtk_dither_set_common() and result in relay mode.
> > > > For od, it set to relay mode first, them invalid bpc would do nothing in
> > > > mtk_dither_set_common() and result in relay mode. I would like dither,
> > > > gamma and od to process invalid bpc in the same way. One solution is to
> > > > set relay mode in mtk_dither_set_common() for invalid bpc.
> > > >
> > > > Regards,
> > > > CK
> > > >
> > >
> > > I modify the mtk_dither_config() to follow:
> > >
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > index ac2cb25620357..5b7fcedb9f9a8 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > @@ -53,6 +53,7 @@
> > >  #define DITHER_EN  BIT(0)
> > >  #define DISP_DITHER_CFG0x0020
> > >  #define DITHER_RELAY_MODE  BIT(0)
> > > +#define DITHER_ENGINE_EN   BIT(1)
> > >  #define DISP_DITHER_SIZE   0x0030
> > >
> > >  #define LUT_10BIT_MASK 0x03ff
> > > @@ -166,6 +167,8 @@ void mtk_dither_set_common(void __iomem *regs,
> > > struct cmdq_client_reg *cmdq_reg,
> > >   DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> > >   cmdq_reg, regs, DISP_DITHER_16);
> > > mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
> > > +   } else {
> > > +   mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, cmdq_reg, 
> > > regs, cfg);
> > > }
> > >  }
> > >
> > > @@ -315,8 +318,12 @@ static void mtk_dither_config(struct device *dev,
> > > unsi

Re: [PATCH v12 6/8] drm/mediatek: enable dither function

2021-01-28 Thread Yongqiang Niu

On Fri, 2021-01-29 at 14:24 +0800, Hsin-Yi Wang wrote:
> On Fri, Jan 29, 2021 at 9:33 AM CK Hu  wrote:
> >
> > Hi, Hsin-Yi:
> >
> > On Thu, 2021-01-28 at 19:23 +0800, Hsin-Yi Wang wrote:
> > > From: Yongqiang Niu 
> > >
> > > for 5 or 6 bpc panel, we need enable dither function
> > > to improve the display quality
> > >
> > > Signed-off-by: Yongqiang Niu 
> > > Signed-off-by: Hsin-Yi Wang 
> > > ---
> > >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +--
> > >  1 file changed, 13 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
> > > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > index ac2cb25620357..6c8f246380a74 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > @@ -53,6 +53,7 @@
> > >  #define DITHER_ENBIT(0)
> > >  #define DISP_DITHER_CFG  0x0020
> > >  #define DITHER_RELAY_MODEBIT(0)
> > > +#define DITHER_ENGINE_EN BIT(1)
> > >  #define DISP_DITHER_SIZE 0x0030
> > >
> > >  #define LUT_10BIT_MASK   0x03ff
> > > @@ -314,9 +315,19 @@ static void mtk_dither_config(struct device *dev, 
> > > unsigned int w,
> > > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > >  {
> > >   struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > > + bool enable = (bpc == 5 || bpc == 6);
> >
> > I strongly believe that dither function in dither is identical to the
> > one in gamma and od, and in mtk_dither_set_common(), 'bpc >=
> > MTK_MIN_BPC' is valid, so I believe we need not to limit bpc to 5 or 6.
> > But we should consider the case that bpc is invalid in
> > mtk_dither_set_common(). Invalid case in gamma and od use different way
> > to process. For gamma, dither is default relay mode, so invalid bpc
> > would do nothing in mtk_dither_set_common() and result in relay mode.
> > For od, it set to relay mode first, them invalid bpc would do nothing in
> > mtk_dither_set_common() and result in relay mode. I would like dither,
> > gamma and od to process invalid bpc in the same way. One solution is to
> > set relay mode in mtk_dither_set_common() for invalid bpc.
> >
> > Regards,
> > CK
> >
> 
> I modify the mtk_dither_config() to follow:
> 
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index ac2cb25620357..5b7fcedb9f9a8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -53,6 +53,7 @@
>  #define DITHER_EN  BIT(0)
>  #define DISP_DITHER_CFG0x0020
>  #define DITHER_RELAY_MODE  BIT(0)
> +#define DITHER_ENGINE_EN   BIT(1)
>  #define DISP_DITHER_SIZE   0x0030
> 
>  #define LUT_10BIT_MASK 0x03ff
> @@ -166,6 +167,8 @@ void mtk_dither_set_common(void __iomem *regs,
> struct cmdq_client_reg *cmdq_reg,
>   DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
>   cmdq_reg, regs, DISP_DITHER_16);
> mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
> +   } else {
> +   mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, cmdq_reg, regs, 
> cfg);
> }
>  }
> 
> @@ -315,8 +318,12 @@ static void mtk_dither_config(struct device *dev,
> unsigned int w,
>  {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> 
> -   mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg,
> priv->regs, DISP_DITHER_SIZE);
> -   mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, >cmdq_reg,
> priv->regs, DISP_DITHER_CFG);
> +   mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, priv->regs,
> + DISP_DITHER_SIZE);
> +   mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, >cmdq_reg, 
> priv->regs,
> + DISP_DITHER_CFG);
> +   mtk_dither_set_common(priv->regs, >cmdq_reg, bpc, 
> DISP_DITHER_CFG,
> +  DITHER_ENGINE_EN, cmdq_pkt);
>  }
> 
> So now, not only bpc==5 or 6, but all valid bpc, dither config will
> call mtk_dither_set_common() with the flag DITHER_ENGINE_EN(BIT(1)).
> od config will call mtk_dither_set_common() with the flag
> DIS

Re: [PATCH v11 7/9] drm/mediatek: enable dither function

2021-01-28 Thread Yongqiang Niu

On Thu, 2021-01-28 at 16:28 +0800, CK Hu wrote:
> On Thu, 2021-01-28 at 16:18 +0800, Hsin-Yi Wang wrote:
> > On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu
> >  wrote:
> > >
> > > On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote:
> > > > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
> > > > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
> > > > > > Hi, Hsin-Yi:
> > > > > >
> > > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> > > > > > > From: Yongqiang Niu 
> > > > > > >
> > > > > > > for 5 or 6 bpc panel, we need enable dither function
> > > > > > > to improve the display quality
> > > > > > >
> > > > > > > Signed-off-by: Yongqiang Niu 
> > > > > > > Signed-off-by: Hsin-Yi Wang 
> > > > > > > ---
> > > > > > >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 
> > > > > > > -
> > > > > > >  1 file changed, 43 insertions(+), 1 deletion(-)
> > > > > > >
> > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
> > > > > > > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > > > index 8173f709272be..e85625704d611 100644
> > > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > > > @@ -53,7 +53,9 @@
> > > > > > >  #define DITHER_EN  BIT(0)
> > > > > > >  #define DISP_DITHER_CFG0x0020
> > > > > > >  #define DITHER_RELAY_MODE  BIT(0)
> > > > > > > +#define DITHER_ENGINE_EN   BIT(1)
> > > > > > >  #define DISP_DITHER_SIZE   0x0030
> > > > > > > +#define DITHER_REG(idx)(0x100 + 
> > > > > > > (idx) * 4)
> > > > > > >
> > > > > > >  #define LUT_10BIT_MASK 0x03ff
> > > > > > >
> > > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device 
> > > > > > > *dev, unsigned int w,
> > > > > > >  {
> > > > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > > > > > >
> > > > > > > +   bool enable = false;
> > > > > > > +
> > > > > > > +   /* default value for dither reg 5 to 14 */
> > > > > > > +   const u32 dither_setting[] = {
> > > > > > > +   0x, /* 5 */
> > > > > > > +   0x3002, /* 6 */
> > > > > > > +   0x, /* 7 */
> > > > > > > +   0x, /* 8 */
> > > > > > > +   0x, /* 9 */
> > > > > > > +   0x, /* 10 */
> > > > > > > +   0x, /* 11 */
> > > > > > > +   0x0011, /* 12 */
> > > > > > > +   0x, /* 13 */
> > > > > > > +   0x, /* 14 */
> > > > > >
> > > > > > Could you explain what is this?
> > > > >
> > > > > this is dither 5 to dither 14 setting
> > > > > this will be useless, we just need set dither 5 and dither 7 like
> > > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5);
> > > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7);
> > > > > other value is same with hardware default value.
> > > > >
> > > > >
> > > > > >
> > > > > > > +   };
> > > > > > > +
> > > > > > > +   if (bpc == 5 || bpc == 6) {
> > > > > > > +   enable = true;
> > > > > > > +   mtk_ddp_write(cmdq_pkt,
> > > > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC 
> > > > > > > - bpc) |
> > > > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - 
> > > > > > > bpc) |
> > >

Re: [PATCH v11 7/9] drm/mediatek: enable dither function

2021-01-28 Thread Yongqiang Niu

On Thu, 2021-01-28 at 16:18 +0800, Hsin-Yi Wang wrote:
> On Thu, Jan 28, 2021 at 4:10 PM Yongqiang Niu
>  wrote:
> >
> > On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote:
> > > On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
> > > > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
> > > > > Hi, Hsin-Yi:
> > > > >
> > > > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> > > > > > From: Yongqiang Niu 
> > > > > >
> > > > > > for 5 or 6 bpc panel, we need enable dither function
> > > > > > to improve the display quality
> > > > > >
> > > > > > Signed-off-by: Yongqiang Niu 
> > > > > > Signed-off-by: Hsin-Yi Wang 
> > > > > > ---
> > > > > >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 
> > > > > > -
> > > > > >  1 file changed, 43 insertions(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
> > > > > > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > > index 8173f709272be..e85625704d611 100644
> > > > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > > > @@ -53,7 +53,9 @@
> > > > > >  #define DITHER_EN  BIT(0)
> > > > > >  #define DISP_DITHER_CFG0x0020
> > > > > >  #define DITHER_RELAY_MODE  BIT(0)
> > > > > > +#define DITHER_ENGINE_EN   BIT(1)
> > > > > >  #define DISP_DITHER_SIZE   0x0030
> > > > > > +#define DITHER_REG(idx)(0x100 + 
> > > > > > (idx) * 4)
> > > > > >
> > > > > >  #define LUT_10BIT_MASK 0x03ff
> > > > > >
> > > > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device 
> > > > > > *dev, unsigned int w,
> > > > > >  {
> > > > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > > > > >
> > > > > > +   bool enable = false;
> > > > > > +
> > > > > > +   /* default value for dither reg 5 to 14 */
> > > > > > +   const u32 dither_setting[] = {
> > > > > > +   0x, /* 5 */
> > > > > > +   0x3002, /* 6 */
> > > > > > +   0x, /* 7 */
> > > > > > +   0x, /* 8 */
> > > > > > +   0x, /* 9 */
> > > > > > +   0x, /* 10 */
> > > > > > +   0x, /* 11 */
> > > > > > +   0x0011, /* 12 */
> > > > > > +   0x, /* 13 */
> > > > > > +   0x, /* 14 */
> > > > >
> > > > > Could you explain what is this?
> > > >
> > > > this is dither 5 to dither 14 setting
> > > > this will be useless, we just need set dither 5 and dither 7 like
> > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5);
> > > > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7);
> > > > other value is same with hardware default value.
> > > >
> > > >
> > > > >
> > > > > > +   };
> > > > > > +
> > > > > > +   if (bpc == 5 || bpc == 6) {
> > > > > > +   enable = true;
> > > > > > +   mtk_ddp_write(cmdq_pkt,
> > > > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - 
> > > > > > bpc) |
> > > > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - 
> > > > > > bpc) |
> > > > > > + DITHER_NEW_BIT_MODE,
> > > > > > + >cmdq_reg, priv->regs, 
> > > > > > DITHER_REG(15));
> > > > > > +   mtk_ddp_write(cmdq_pkt,
> > > > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - 
> > > > > > bpc) |
> > > &g

Re: [PATCH v11 7/9] drm/mediatek: enable dither function

2021-01-28 Thread Yongqiang Niu

On Thu, 2021-01-28 at 16:07 +0800, CK Hu wrote:
> On Thu, 2021-01-28 at 15:59 +0800, Yongqiang Niu wrote:
> > On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
> > > Hi, Hsin-Yi:
> > > 
> > > On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> > > > From: Yongqiang Niu 
> > > > 
> > > > for 5 or 6 bpc panel, we need enable dither function
> > > > to improve the display quality
> > > > 
> > > > Signed-off-by: Yongqiang Niu 
> > > > Signed-off-by: Hsin-Yi Wang 
> > > > ---
> > > >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 -
> > > >  1 file changed, 43 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
> > > > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > index 8173f709272be..e85625704d611 100644
> > > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > > @@ -53,7 +53,9 @@
> > > >  #define DITHER_EN  BIT(0)
> > > >  #define DISP_DITHER_CFG0x0020
> > > >  #define DITHER_RELAY_MODE  BIT(0)
> > > > +#define DITHER_ENGINE_EN   BIT(1)
> > > >  #define DISP_DITHER_SIZE   0x0030
> > > > +#define DITHER_REG(idx)(0x100 + (idx) 
> > > > * 4)
> > > >  
> > > >  #define LUT_10BIT_MASK 0x03ff
> > > >  
> > > > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, 
> > > > unsigned int w,
> > > >  {
> > > > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > > >  
> > > > +   bool enable = false;
> > > > +
> > > > +   /* default value for dither reg 5 to 14 */
> > > > +   const u32 dither_setting[] = {
> > > > +   0x, /* 5 */
> > > > +   0x3002, /* 6 */
> > > > +   0x, /* 7 */
> > > > +   0x, /* 8 */
> > > > +   0x, /* 9 */
> > > > +   0x, /* 10 */
> > > > +   0x, /* 11 */
> > > > +   0x0011, /* 12 */
> > > > +   0x, /* 13 */
> > > > +   0x, /* 14 */
> > > 
> > > Could you explain what is this?
> > 
> > this is dither 5 to dither 14 setting
> > this will be useless, we just need set dither 5 and dither 7 like 
> > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5);
> > mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7);
> > other value is same with hardware default value.
> > 
> > 
> > > 
> > > > +   };
> > > > +
> > > > +   if (bpc == 5 || bpc == 6) {
> > > > +   enable = true;
> > > > +   mtk_ddp_write(cmdq_pkt,
> > > > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) 
> > > > |
> > > > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> > > > + DITHER_NEW_BIT_MODE,
> > > > + >cmdq_reg, priv->regs, 
> > > > DITHER_REG(15));
> > > > +   mtk_ddp_write(cmdq_pkt,
> > > > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) 
> > > > |
> > > > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> > > > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) 
> > > > |
> > > > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> > > 
> > > This result in 0x50505050, but previous version is 0x50504040, so this
> > > version is correct and previous version is incorrect?
> > 
> > the new version set r g b 3 channel same, seams more reasonable
> > 
> > 
> 
> So all the setting of DISP_DITHER_5, DISP_DITHER_7, DISP_DITHER_15,
> DISP_DITHER_16 is identical to mtk_dither_set(), so call
> mtk_dither_set() instead of duplication here.
> 

dither enable set in mtk_dither_set is
mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG);

that is different 8183 and mt8192.
mt8173 dither enable in gamma is bit2
mt8183 and mt8192 dither en

Re: [PATCH v11 7/9] drm/mediatek: enable dither function

2021-01-28 Thread Yongqiang Niu

On Thu, 2021-01-28 at 15:42 +0800, CK Hu wrote:
> Hi, Hsin-Yi:
> 
> On Thu, 2021-01-28 at 15:28 +0800, Hsin-Yi Wang wrote:
> > From: Yongqiang Niu 
> > 
> > for 5 or 6 bpc panel, we need enable dither function
> > to improve the display quality
> > 
> > Signed-off-by: Yongqiang Niu 
> > Signed-off-by: Hsin-Yi Wang 
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 44 -
> >  1 file changed, 43 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 8173f709272be..e85625704d611 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -53,7 +53,9 @@
> >  #define DITHER_EN  BIT(0)
> >  #define DISP_DITHER_CFG0x0020
> >  #define DITHER_RELAY_MODE  BIT(0)
> > +#define DITHER_ENGINE_EN   BIT(1)
> >  #define DISP_DITHER_SIZE   0x0030
> > +#define DITHER_REG(idx)(0x100 + (idx) * 4)
> >  
> >  #define LUT_10BIT_MASK 0x03ff
> >  
> > @@ -313,8 +315,48 @@ static void mtk_dither_config(struct device *dev, 
> > unsigned int w,
> >  {
> > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> >  
> > +   bool enable = false;
> > +
> > +   /* default value for dither reg 5 to 14 */
> > +   const u32 dither_setting[] = {
> > +   0x, /* 5 */
> > +   0x3002, /* 6 */
> > +   0x, /* 7 */
> > +   0x, /* 8 */
> > +   0x, /* 9 */
> > +   0x, /* 10 */
> > +   0x, /* 11 */
> > +   0x0011, /* 12 */
> > +   0x, /* 13 */
> > +   0x, /* 14 */
> 
> Could you explain what is this?

this is dither 5 to dither 14 setting
this will be useless, we just need set dither 5 and dither 7 like 
mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5);
mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7);
other value is same with hardware default value.


> 
> > +   };
> > +
> > +   if (bpc == 5 || bpc == 6) {
> > +   enable = true;
> > +   mtk_ddp_write(cmdq_pkt,
> > + DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> > + DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> > + DITHER_NEW_BIT_MODE,
> > + >cmdq_reg, priv->regs, DITHER_REG(15));
> > +   mtk_ddp_write(cmdq_pkt,
> > + DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> > + DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> > + DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
> > + DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> 
> This result in 0x50505050, but previous version is 0x50504040, so this
> version is correct and previous version is incorrect?

the new version set r g b 3 channel same, seams more reasonable


> 
> Regards,
> CK
> 
> > + >cmdq_reg, priv->regs, DITHER_REG(16));
> > +   }
> > +
> > +
> > +   if (enable) {
> > +   u32 idx;
> > +
> > +   for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)
> > +   mtk_ddp_write(cmdq_pkt, dither_setting[idx], 
> > >cmdq_reg, priv->regs,
> > + DITHER_REG(idx + 5));
> > +   }
> > +
> > mtk_ddp_write(cmdq_pkt, h << 16 | w, >cmdq_reg, priv->regs, 
> > DISP_DITHER_SIZE);
> > -   mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, >cmdq_reg, priv->regs, 
> > DISP_DITHER_CFG);
> > +mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : 
> > DITHER_RELAY_MODE, >cmdq_reg, priv->regs, DISP_DITHER_CFG);
> >  }
> >  
> >  static void mtk_dither_start(struct device *dev)
> 
>

Re: [PATCH v3, 07/15] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase

2021-01-27 Thread Yongqiang Niu

On Tue, 2021-01-12 at 07:59 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
> 
> Yongqiang Niu  於 2021年1月11日 週一 下午3:44寫道：
> >
> > enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
> 
> Could you describe more information? Without this patch, what would happen?
> 

without this patch, ovl will hang up when more than 1 layer enabled

> >
> > Signed-off-by: Yongqiang Niu 
> > ---
> >  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c 
> > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > index b47c238..4934bee 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> > @@ -23,6 +23,7 @@
> >  #define DISP_REG_OVL_RST   0x0014
> >  #define DISP_REG_OVL_ROI_SIZE  0x0020
> >  #define DISP_REG_OVL_DATAPATH_CON  0x0024
> > +#define OVL_LAYER_SMI_ID_ENBIT(0)
> >  #define OVL_BGCLR_SEL_IN   BIT(2)
> >  #define DISP_REG_OVL_ROI_BGCLR 0x0028
> >  #define DISP_REG_OVL_SRC_CON   0x002c
> > @@ -61,6 +62,7 @@ struct mtk_disp_ovl_data {
> > unsigned int gmc_bits;
> > unsigned int layer_nr;
> > bool fmt_rgb565_is_0;
> > +   bool smi_id_en;
> >  };
> >
> >  /**
> > @@ -116,7 +118,17 @@ static void mtk_ovl_disable_vblank(struct mtk_ddp_comp 
> > *comp)
> >
> >  static void mtk_ovl_start(struct mtk_ddp_comp *comp)
> >  {
> > +   struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
> > +
> > writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
> > +
> > +   if(ovl->data->smi_id_en) {
> > +   unsigned int reg;
> > +
> > +   reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
> > +   reg = reg | OVL_LAYER_SMI_ID_EN;
> > +   writel_relaxed(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
> 
> I think this setting should before write 1 to DISP_REG_OVL_EN.
> 
> > +   }
> >  }
> >
> >  static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
> 
> Should clear DISP_REG_OVL_DATAPATH_CON when stop?
> 
> Regards,
> Chun-Kuang.
> 
> > --
> > 1.8.1.1.dirty
> > ___
> > Linux-mediatek mailing list
> > linux-media...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function

2021-01-20 Thread Yongqiang Niu

On Wed, 2021-01-20 at 20:38 +0100, Matthias Brugger wrote:
> On Tue, Jan 05, 2021 at 11:06:26AM +0800, Yongqiang Niu wrote:
> > move register operation into mmsys path select function
> 
> Why do you want to do that. It seems the register access pattern is the
> same for all SoCs so far supported, so I don't see the need to duplicate
> the code in every SoC.
> 
> Regards,
> Matthias

mt2701 and mt8173 ovl mout en already different.
mt2701 ovl mout en register offset is 0x30
mt8173 olv mout en register offset is 0x40

only the use case is different;
mt2701 ovl->color0
mt8173 ovl->rmda0
there make different define for this different.

#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN   0x040

#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN0x030

for the future mt8183, ovl mout en register offset will change to
0xf00

this is only one different sample, there will be more and more
different, so we add this patch for different soc


> 
> > 
> > Signed-off-by: Yongqiang Niu 
> > ---
> >  drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 
> > +
> >  1 file changed, 71 insertions(+), 69 deletions(-)
> > 
> > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c 
> > b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > index 6c03282..64c8030 100644
> > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > @@ -106,141 +106,161 @@ struct mtk_mmsys {
> > .clk_driver = "clk-mt8183-mm",
> >  };
> >  
> > -static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > - enum mtk_ddp_comp_id next,
> > - unsigned int *addr)
> > +static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
> > + enum mtk_ddp_comp_id cur,
> > + enum mtk_ddp_comp_id next,
> > + bool enable)
> >  {
> > -   unsigned int value;
> > +   unsigned int addr, value, reg;
> >  
> > if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > -   *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> > value = OVL0_MOUT_EN_COLOR0;
> > } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> > -   *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> > value = OVL_MOUT_EN_RDMA;
> > } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> > -   *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > value = OD_MOUT_EN_RDMA0;
> > } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> > -   *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> > value = UFOE_MOUT_EN_DSI0;
> > } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > -   *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> > value = OVL1_MOUT_EN_COLOR1;
> > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> > -   *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > value = GAMMA_MOUT_EN_RDMA1;
> > } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> > -   *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > value = OD1_MOUT_EN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> > -   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DPI0;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> > -   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DPI1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> > -   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > +   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > value = RDMA0_SOUT_DSI1;
> > } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT

[PATCH v3, 13/15] drm/mediatek: add matrix bits private data for ccorr

2021-01-10 Thread Yongqiang Niu

matrix bits of mt8183 is 12
matrix bits of mt8192 is 13

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 23 ---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
index 63b3ef6..755e75b 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -30,8 +30,10 @@
 #define DISP_CCORR_COEF_3  0x008C
 #define DISP_CCORR_COEF_4  0x0090
 
+#define CCORR_MATRIX_BITS  12
+
 struct mtk_disp_ccorr_data {
-   u32 reserved;
+   u32 matrix_bits;
 };
 
 /**
@@ -96,6 +98,8 @@ static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
uint16_t coeffs[9] = { 0 };
int i;
struct cmdq_pkt *cmdq_pkt = NULL;
+   struct mtk_disp_ccorr *ccorr = comp_to_ccorr(comp);
+   u32 matrix_bits;
 
if (!blob)
return;
@@ -103,8 +107,16 @@ static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
ctm = (struct drm_color_ctm *)blob->data;
input = ctm->matrix;
 
-   for (i = 0; i < ARRAY_SIZE(coeffs); i++)
+   if (ccorr->data)
+   matrix_bits = ccorr->data->matrix_bits;
+   else
+   matrix_bits = CCORR_MATRIX_BITS;
+
+   for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
+   if (matrix_bits > CCORR_MATRIX_BITS)
+   coeffs[i] <<= (matrix_bits - CCORR_MATRIX_BITS);
+   }
 
mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
  comp, DISP_CCORR_COEF_0);
@@ -205,8 +217,13 @@ static int mtk_disp_ccorr_remove(struct platform_device 
*pdev)
return 0;
 }
 
+static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = {
+   .matrix_bits = CCORR_MATRIX_BITS,
+};
+
 static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
-   { .compatible = "mediatek,mt8183-disp-ccorr"},
+   { .compatible = "mediatek,mt8183-disp-ccorr",
+ .data = _ccorr_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
-- 
1.8.1.1.dirty

[PATCH v3, 01/15] dt-bindings: mediatek: add description for postmask

2021-01-10 Thread Yongqiang Niu

add description for postmask
postmask is used control round corner for display frame

Signed-off-by: Yongqiang Niu 
---
 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index c562cda..9d9ab65 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -37,6 +37,7 @@ Required properties (all function blocks):
"mediatek,-disp-aal"  - adaptive ambient light 
controller
"mediatek,-disp-gamma"- gamma correction
"mediatek,-disp-merge"- merge streams from two RDMA 
sources
+   "mediatek,-disp-postmask" - control round corner for 
display frame
"mediatek,-disp-split"- split stream to two encoders
"mediatek,-disp-ufoe" - data compression engine
"mediatek,-dsi"   - DSI controller, see 
mediatek,dsi.txt
-- 
1.8.1.1.dirty

[PATCH v3, 12/15] drm/mediatek: separate ccorr module

2021-01-10 Thread Yongqiang Niu

ccorr ctm matrix bits will be different in mt8192

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/Makefile   |   3 +-
 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c   | 222 
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  92 +---
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |   8 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   1 +
 5 files changed, 231 insertions(+), 95 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index ce5ad59..a02f534 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 
-mediatek-drm-y := mtk_disp_color.o \
+mediatek-drm-y := mtk_disp_ccorr.o \
+ mtk_disp_color.o \
  mtk_disp_gamma.o \
  mtk_disp_ovl.o \
  mtk_disp_postmask.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
new file mode 100644
index 000..63b3ef6
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -0,0 +1,222 @@
+/*
+ * SPDX-License-Identifier:
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+#define DISP_CCORR_EN  0x
+#define CCORR_EN   BIT(0)
+#define DISP_CCORR_CFG 0x0020
+#define CCORR_RELAY_MODE   BIT(0)
+#define CCORR_ENGINE_ENBIT(1)
+#define CCORR_GAMMA_OFFBIT(2)
+#define CCORR_WGAMUT_SRC_CLIP  BIT(3)
+#define DISP_CCORR_SIZE0x0030
+#define DISP_CCORR_COEF_0  0x0080
+#define DISP_CCORR_COEF_1  0x0084
+#define DISP_CCORR_COEF_2  0x0088
+#define DISP_CCORR_COEF_3  0x008C
+#define DISP_CCORR_COEF_4  0x0090
+
+struct mtk_disp_ccorr_data {
+   u32 reserved;
+};
+
+/**
+ * struct mtk_disp_ccorr - DISP_CCORR driver structure
+ * @ddp_comp - structure containing type enum and hardware resources
+ * @crtc - associated crtc to report irq events to
+ */
+struct mtk_disp_ccorr {
+   struct mtk_ddp_comp ddp_comp;
+   const struct mtk_disp_ccorr_data*data;
+};
+
+static inline struct mtk_disp_ccorr *comp_to_ccorr(struct mtk_ddp_comp *comp)
+{
+   return container_of(comp, struct mtk_disp_ccorr, ddp_comp);
+}
+
+static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
+unsigned int h, unsigned int vrefresh,
+unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+   mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_CCORR_SIZE);
+   mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
+}
+
+static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
+{
+   writel(CCORR_EN, comp->regs + DISP_CCORR_EN);
+}
+
+static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
+{
+   writel_relaxed(0x0, comp->regs + DISP_CCORR_EN);
+}
+
+/* Converts a DRM S31.32 value to the HW S1.10 format. */
+static u16 mtk_ctm_s31_32_to_s1_10(u64 in)
+{
+   u16 r;
+
+   /* Sign bit. */
+   r = in & BIT_ULL(63) ? BIT(11) : 0;
+
+   if ((in & GENMASK_ULL(62, 33)) > 0) {
+   /* identity value 0x1 -> 0x400, */
+   /* if bigger this, set it to max 0x7ff. */
+   r |= GENMASK(10, 0);
+   } else {
+   /* take the 11 most important bits. */
+   r |= (in >> 22) & GENMASK(10, 0);
+   }
+
+   return r;
+}
+
+static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp,
+ struct drm_crtc_state *state)
+{
+   struct drm_property_blob *blob = state->ctm;
+   struct drm_color_ctm *ctm;
+   const u64 *input;
+   uint16_t coeffs[9] = { 0 };
+   int i;
+   struct cmdq_pkt *cmdq_pkt = NULL;
+
+   if (!blob)
+   return;
+
+   ctm = (struct drm_color_ctm *)blob->data;
+   input = ctm->matrix;
+
+   for (i = 0; i < ARRAY_SIZE(coeffs); i++)
+   coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]);
+
+   mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
+ comp, DISP_CCORR_COEF_0);
+   mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
+ comp, DISP_CCORR_COEF_1);
+   mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
+ comp, DISP_CCORR_COEF_2);
+   mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
+ comp, DIS

[PATCH v3, 14/15] drm/mediatek: add DDP support for MT8192

2021-01-10 Thread Yongqiang Niu

Add DDP support for MT8192 SoC.

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 35 ++
 1 file changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 1308046..7aa7fc3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -40,6 +40,18 @@
 #define MT8167_MUTEX_MOD_DISP_DITHER   15
 #define MT8167_MUTEX_MOD_DISP_UFOE 16
 
+#define MT8192_MUTEX_MOD_DISP_OVL0 0
+#define MT8192_MUTEX_MOD_DISP_OVL0_2L  1
+#define MT8192_MUTEX_MOD_DISP_RDMA02
+#define MT8192_MUTEX_MOD_DISP_COLOR0   4
+#define MT8192_MUTEX_MOD_DISP_CCORR0   5
+#define MT8192_MUTEX_MOD_DISP_AAL0 6
+#define MT8192_MUTEX_MOD_DISP_GAMMA0   7
+#define MT8192_MUTEX_MOD_DISP_POSTMASK08
+#define MT8192_MUTEX_MOD_DISP_DITHER0  9
+#define MT8192_MUTEX_MOD_DISP_OVL2_2L  16
+#define MT8192_MUTEX_MOD_DISP_RDMA417
+
 #define MT8183_MUTEX_MOD_DISP_RDMA00
 #define MT8183_MUTEX_MOD_DISP_RDMA11
 #define MT8183_MUTEX_MOD_DISP_OVL0 9
@@ -215,6 +227,20 @@ struct mtk_ddp {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
 };
 
+static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+   [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
+   [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
+   [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
+   [DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
+   [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
+   [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
+   [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
+   [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L,
+   [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L,
+   [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0,
+   [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
+};
+
 static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
[DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
@@ -275,6 +301,13 @@ struct mtk_ddp {
.no_clk = true,
 };
 
+static const struct mtk_ddp_data mt8192_ddp_driver_data = {
+   .mutex_mod = mt8192_mutex_mod,
+   .mutex_sof = mt8183_mutex_sof,
+   .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
+   .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
+};
+
 struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
 {
struct mtk_ddp *ddp = dev_get_drvdata(dev);
@@ -497,6 +530,8 @@ static int mtk_ddp_remove(struct platform_device *pdev)
  .data = _ddp_driver_data},
{ .compatible = "mediatek,mt8183-disp-mutex",
  .data = _ddp_driver_data},
+   { .compatible = "mediatek,mt8192-disp-mutex",
+ .data = _ddp_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, ddp_driver_dt_match);
-- 
1.8.1.1.dirty

[PATCH v3, 15/15] drm/mediatek: add support for mediatek SOC MT8192

2021-01-10 Thread Yongqiang Niu

add support for mediatek SOC MT8192

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c|  6 
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c  | 20 +
 drivers/gpu/drm/mediatek/mtk_disp_postmask.c |  1 +
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c |  6 
 drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 42 
 5 files changed, 75 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
index 755e75b..da3fd98 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -221,9 +221,15 @@ static int mtk_disp_ccorr_remove(struct platform_device 
*pdev)
.matrix_bits = CCORR_MATRIX_BITS,
 };
 
+static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = {
+   .matrix_bits = 13,
+};
+
 static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
{ .compatible = "mediatek,mt8183-disp-ccorr",
  .data = _ccorr_driver_data},
+   { .compatible = "mediatek,mt8192-disp-ccorr",
+ .data = _ccorr_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 8e7f494..4e6679e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -457,6 +457,22 @@ static int mtk_disp_ovl_remove(struct platform_device 
*pdev)
.fmt_rgb565_is_0 = true,
 };
 
+static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
+   .addr = DISP_REG_OVL_ADDR_MT8173,
+   .gmc_bits = 10,
+   .layer_nr = 4,
+   .fmt_rgb565_is_0 = true,
+   .smi_id_en = true,
+};
+
+static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
+   .addr = DISP_REG_OVL_ADDR_MT8173,
+   .gmc_bits = 10,
+   .layer_nr = 2,
+   .fmt_rgb565_is_0 = true,
+   .smi_id_en = true,
+};
+
 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-ovl",
  .data = _ovl_driver_data},
@@ -466,6 +482,10 @@ static int mtk_disp_ovl_remove(struct platform_device 
*pdev)
  .data = _ovl_driver_data},
{ .compatible = "mediatek,mt8183-disp-ovl-2l",
  .data = _ovl_2l_driver_data},
+   { .compatible = "mediatek,mt8192-disp-ovl",
+ .data = _ovl_driver_data},
+   { .compatible = "mediatek,mt8192-disp-ovl-2l",
+ .data = _ovl_2l_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c 
b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
index 736224c..3b38157 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
@@ -145,6 +145,7 @@ static int mtk_disp_postmask_remove(struct platform_device 
*pdev)
 }
 
 static const struct of_device_id mtk_disp_postmask_driver_dt_match[] = {
+   { .compatible = "mediatek,mt8192-disp-postmask"},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_postmask_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index e914e3a..b160ebe 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -364,6 +364,10 @@ static int mtk_disp_rdma_remove(struct platform_device 
*pdev)
.fifo_size = 5 * SZ_1K,
 };
 
+static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
+   .fifo_size = 5 * SZ_1K,
+};
+
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
  .data = _rdma_driver_data},
@@ -371,6 +375,8 @@ static int mtk_disp_rdma_remove(struct platform_device 
*pdev)
  .data = _rdma_driver_data},
{ .compatible = "mediatek,mt8183-disp-rdma",
  .data = _rdma_driver_data},
+   { .compatible = "mediatek,mt8192-disp-rdma",
+ .data = _rdma_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c 
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 79e86f7..24ce37c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -149,6 +149,25 @@
DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
+   DDP_COMPONENT_OVL0,
+   DDP_COMPONENT_OVL_2L0,
+   DDP_COMPONENT_RDMA0,
+   DDP_COMPONENT_COLOR0,
+   DDP_COMPONENT_CCORR,
+   DDP_COMPONENT_AAL0,
+   DDP_COMPONENT_GAMMA,
+   DDP_COMPONENT_POSTMASK0,
+   DDP_COMPONENT_DITHER,
+   DDP_COMPONENT_DSI0,
+};
+
+static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
+   DDP_COMPONENT_OVL_2L2,
+

[PATCH v3, 10/15] drm/mediatek: Add pm runtime support for color

2021-01-10 Thread Yongqiang Niu

color power domain need controled in the device.

Signed-off-by: Yongqiang Niu 
Signed-off-by: Yidi Lin 
---
 drivers/gpu/drm/mediatek/mtk_disp_color.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c 
b/drivers/gpu/drm/mediatek/mtk_disp_color.c
index 6048cbc..14b9dd3 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "mtk_drm_crtc.h"
@@ -132,6 +133,8 @@ static int mtk_disp_color_probe(struct platform_device 
*pdev)
 
platform_set_drvdata(pdev, priv);
 
+   pm_runtime_enable(dev);
+
ret = component_add(dev, _disp_color_component_ops);
if (ret)
dev_err(dev, "Failed to add component: %d\n", ret);
@@ -141,6 +144,8 @@ static int mtk_disp_color_probe(struct platform_device 
*pdev)
 
 static int mtk_disp_color_remove(struct platform_device *pdev)
 {
+   pm_runtime_disable(>dev);
+
component_del(>dev, _disp_color_component_ops);
 
return 0;
-- 
1.8.1.1.dirty

[PATCH v3, 11/15] drm/mediatek: fix aal size config

2021-01-10 Thread Yongqiang Niu

the orginal setting is not correct, fix it follow hardware data sheet.
if keep this error setting, mt8173/mt8183 display ok
but mt8192 display abnormal.

Fixes: 0664d1392c26 (drm/mediatek: Add AAL engine basic function)

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index fc01fea..6081800 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -174,7 +174,7 @@ static void mtk_aal_config(struct mtk_ddp_comp *comp, 
unsigned int w,
   unsigned int h, unsigned int vrefresh,
   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 {
-   mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE);
+   mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_SIZE);
 }
 
 static void mtk_aal_start(struct mtk_ddp_comp *comp)
-- 
1.8.1.1.dirty

[PATCH v3, 07/15] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase

2021-01-10 Thread Yongqiang Niu

enable OVL_LAYER_SMI_ID_EN for multi-layer usecase

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index b47c238..4934bee 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -23,6 +23,7 @@
 #define DISP_REG_OVL_RST   0x0014
 #define DISP_REG_OVL_ROI_SIZE  0x0020
 #define DISP_REG_OVL_DATAPATH_CON  0x0024
+#define OVL_LAYER_SMI_ID_ENBIT(0)
 #define OVL_BGCLR_SEL_IN   BIT(2)
 #define DISP_REG_OVL_ROI_BGCLR 0x0028
 #define DISP_REG_OVL_SRC_CON   0x002c
@@ -61,6 +62,7 @@ struct mtk_disp_ovl_data {
unsigned int gmc_bits;
unsigned int layer_nr;
bool fmt_rgb565_is_0;
+   bool smi_id_en;
 };
 
 /**
@@ -116,7 +118,17 @@ static void mtk_ovl_disable_vblank(struct mtk_ddp_comp 
*comp)
 
 static void mtk_ovl_start(struct mtk_ddp_comp *comp)
 {
+   struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
+
writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
+
+   if(ovl->data->smi_id_en) {
+   unsigned int reg;
+
+   reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
+   reg = reg | OVL_LAYER_SMI_ID_EN;
+   writel_relaxed(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
+   }
 }
 
 static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
-- 
1.8.1.1.dirty

[PATCH v3, 03/15] arm64: dts: mt8192: add display node

2021-01-10 Thread Yongqiang Niu

add display node

Signed-off-by: Yongqiang Niu 
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 134 +++
 1 file changed, 134 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index e12e024..dcf9fdf 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -15,6 +15,11 @@
#address-cells = <2>;
#size-cells = <2>;
 
+   aliases {
+   ovl2-2l2 = _2l2;
+   rdma4 = 
+   };
+
clk26m: oscillator0 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -508,5 +513,134 @@
#size-cells = <0>;
status = "disabled";
};
+   
+   mmsys: syscon@1400 {
+   compatible = "mediatek,mt8192-mmsys", "syscon";
+   reg = <0 0x1400 0 0x1000>;
+   //mboxes = < 0 CMDQ_THR_PRIO_HIGHEST 1>,
+   //   < 1 CMDQ_THR_PRIO_HIGHEST 1>;
+   //mediatek,gce-client-reg = < SUBSYS_1400 0 
0x1000>;
+   #clock-cells = <1>;
+   };
+
+mutex: mutex@14001000 {
+   compatible = "mediatek,mt8192-disp-mutex";
+   reg = <0 0x14001000 0 0x1000>;
+   interrupts = ;
+   //clocks = < CLK_MM_DISP_MUTEX0>;
+   //mediatek,gce-events = 
,
+   //
;
+   };
+
+   ovl0: ovl@14005000 {
+   compatible = "mediatek,mt8192-disp-ovl";
+   reg = <0 0x14005000 0 0x1000>;
+   interrupts = ;
+   //clocks = < CLK_MM_DISP_OVL0>;
+   //iommus = < M4U_PORT_L0_OVL_RDMA0>;
+   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
+   //mediatek,gce-client-reg = < SUBSYS_1400 
0x5000 0x1000>;
+   };
+
+   ovl_2l0: ovl@14006000 {
+   compatible = "mediatek,mt8192-disp-ovl-2l";
+   reg = <0 0x14006000 0 0x1000>;
+   interrupts = ;
+   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
+   //clocks = < CLK_MM_DISP_OVL0_2L>;
+   //iommus = < M4U_PORT_L1_OVL_2L_RDMA0>;
+   //mediatek,gce-client-reg = < SUBSYS_1400 
0x6000 0x1000>;
+   };
+
+   rdma0: rdma@14007000 {
+   compatible = "mediatek,mt8192-disp-rdma";
+   reg = <0 0x14007000 0 0x1000>;
+   interrupts = ;
+   //clocks = < CLK_MM_DISP_RDMA0>;
+   //iommus = < M4U_PORT_L0_DISP_RDMA0>;
+   //mediatek,larb = <>;
+   //mediatek,rdma-fifo-size = <5120>;
+   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
+   //mediatek,gce-client-reg = < SUBSYS_1400 
0x7000 0x1000>;
+   };
+
+   color0: color@14009000 {
+   compatible = "mediatek,mt8192-disp-color",
+"mediatek,mt8173-disp-color";
+   reg = <0 0x14009000 0 0x1000>;
+   interrupts = ;
+   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
+   //clocks = < CLK_MM_DISP_COLOR0>;
+   //mediatek,gce-client-reg = < SUBSYS_1400 
0x9000 0x1000>;
+   };
+
+   ccorr0: ccorr@1400a000 {
+   compatible = "mediatek,mt8192-disp-ccorr";
+   reg = <0 0x1400a000 0 0x1000>;
+   interrupts = ;
+   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
+   //clocks = < CLK_MM_DISP_CCORR0>;
+   //mediatek,gce-client-reg = < SUBSYS_1400 
0xa000 0x1000>;
+   };
+
+   aal0: aal@1400b000 {
+   compatible = "mediatek,mt8192-disp-aal";
+   reg = <0 0x1400b000 0 0x1000>;
+   interrupts = ;
+   //power-domains = < MT8192_POWER_DOMAIN_DISP>;
+   //clocks = < CLK_MM_DISP_AAL0>;
+   //mediatek,gce-client-reg = < SUBSYS_1400 
0xb000 0x1000>;
+   };
+
+

[PATCH v3, 06/15] drm/mediatek: add component RDMA4

2021-01-10 Thread Yongqiang Niu

This patch add component RDMA4

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index bc6b10a..fc01fea 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -392,6 +392,7 @@ struct mtk_ddp_comp_match {
[DDP_COMPONENT_RDMA0]   = { MTK_DISP_RDMA,  0, NULL },
[DDP_COMPONENT_RDMA1]   = { MTK_DISP_RDMA,  1, NULL },
[DDP_COMPONENT_RDMA2]   = { MTK_DISP_RDMA,  2, NULL },
+   [DDP_COMPONENT_RDMA4]   = { MTK_DISP_RDMA,  4, NULL },
[DDP_COMPONENT_UFOE]= { MTK_DISP_UFOE,  0, _ufoe },
[DDP_COMPONENT_WDMA0]   = { MTK_DISP_WDMA,  0, NULL },
[DDP_COMPONENT_WDMA1]   = { MTK_DISP_WDMA,  1, NULL },
-- 
1.8.1.1.dirty

[PATCH v3, 05/15] drm/mediatek: add component POSTMASK

2021-01-10 Thread Yongqiang Niu

This patch add component POSTMASK,

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/Makefile|   1 +
 drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 160 +++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c  |   2 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h  |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c   |   4 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h   |   1 +
 6 files changed, 168 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index 17a08e2..ce5ad59 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -3,6 +3,7 @@
 mediatek-drm-y := mtk_disp_color.o \
  mtk_disp_gamma.o \
  mtk_disp_ovl.o \
+ mtk_disp_postmask.o \
  mtk_disp_rdma.o \
  mtk_drm_crtc.o \
  mtk_drm_ddp.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c 
b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
new file mode 100644
index 000..736224c
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
@@ -0,0 +1,160 @@
+/*
+ * SPDX-License-Identifier:
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+#define DISP_POSTMASK_EN   0x
+#define POSTMASK_ENBIT(0)
+#define DISP_POSTMASK_CFG  0x0020
+#define POSTMASK_RELAY_MODEBIT(0)
+#define DISP_POSTMASK_SIZE 0x0030
+
+struct mtk_disp_postmask_data {
+   u32 reserved;
+};
+
+/**
+ * struct mtk_disp_postmask - DISP_postmask driver structure
+ * @ddp_comp - structure containing type enum and hardware resources
+ * @crtc - associated crtc to report irq events to
+ */
+struct mtk_disp_postmask {
+   struct mtk_ddp_comp ddp_comp;
+   const struct mtk_disp_postmask_data *data;
+};
+
+static inline struct mtk_disp_postmask *comp_to_postmask(struct mtk_ddp_comp 
*comp)
+{
+   return container_of(comp, struct mtk_disp_postmask, ddp_comp);
+}
+
+static void mtk_postmask_config(struct mtk_ddp_comp *comp, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+   mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_POSTMASK_SIZE);
+   mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, comp, DISP_POSTMASK_CFG);
+}
+
+static void mtk_postmask_start(struct mtk_ddp_comp *comp)
+{
+   writel(POSTMASK_EN, comp->regs + DISP_POSTMASK_EN);
+}
+
+static void mtk_postmask_stop(struct mtk_ddp_comp *comp)
+{
+   writel_relaxed(0x0, comp->regs + DISP_POSTMASK_EN);
+}
+
+static const struct mtk_ddp_comp_funcs mtk_disp_postmask_funcs = {
+   .config = mtk_postmask_config,
+   .start = mtk_postmask_start,
+   .stop = mtk_postmask_stop,
+};
+
+static int mtk_disp_postmask_bind(struct device *dev, struct device *master, 
void *data)
+{
+   struct mtk_disp_postmask *priv = dev_get_drvdata(dev);
+   struct drm_device *drm_dev = data;
+   int ret;
+
+   ret = mtk_ddp_comp_register(drm_dev, >ddp_comp);
+   if (ret < 0) {
+   dev_err(dev, "Failed to register component %pOF: %d\n",
+   dev->of_node, ret);
+   return ret;
+   }
+
+   return 0;
+}
+
+static void mtk_disp_postmask_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+   struct mtk_disp_postmask *priv = dev_get_drvdata(dev);
+   struct drm_device *drm_dev = data;
+
+   mtk_ddp_comp_unregister(drm_dev, >ddp_comp);
+}
+
+static const struct component_ops mtk_disp_postmask_component_ops = {
+   .bind   = mtk_disp_postmask_bind,
+   .unbind = mtk_disp_postmask_unbind,
+};
+
+static int mtk_disp_postmask_probe(struct platform_device *pdev)
+{
+   struct device *dev = >dev;
+   struct mtk_disp_postmask *priv;
+   int comp_id;
+   int ret;
+
+   priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+   if (!priv)
+   return -ENOMEM;
+
+   comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_POSTMASK);
+   if (comp_id < 0) {
+   dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
+   return comp_id;
+   }
+
+   ret = mtk_ddp_comp_init(dev, dev->of_node, >ddp_comp, comp_id,
+   _disp_postmask_funcs);
+   if (ret) {
+   if (ret != -EPROBE_DEFER)
+   dev_err(dev, "Failed to initialize component: %d\n",
+   ret);
+

[PATCH v3, 09/15] drm/mediatek: Add pm runtime support for gamma

2021-01-10 Thread Yongqiang Niu

gamma power domain need controled in the device.

Signed-off-by: Yongqiang Niu 
Signed-off-by: Yidi Lin 
---
 drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
index 3c1ea07..da93079 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "mtk_drm_crtc.h"
@@ -156,6 +157,8 @@ static int mtk_disp_gamma_probe(struct platform_device 
*pdev)
 
platform_set_drvdata(pdev, priv);
 
+   pm_runtime_enable(dev);
+
ret = component_add(dev, _disp_gamma_component_ops);
if (ret)
dev_err(dev, "Failed to add component: %d\n", ret);
@@ -165,6 +168,8 @@ static int mtk_disp_gamma_probe(struct platform_device 
*pdev)
 
 static int mtk_disp_gamma_remove(struct platform_device *pdev)
 {
+   pm_runtime_disable(>dev);
+
component_del(>dev, _disp_gamma_component_ops);
 
return 0;
-- 
1.8.1.1.dirty

[PATCH v3, 08/15] drm/mediatek: check if fb is null

2021-01-10 Thread Yongqiang Niu

It's possible that state->base.fb is null. Add a check before access its
format.

Fixes: b6b1bb980ec4 ( drm/mediatek: Turn off Alpha bit when plane format has no 
alpha)
Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 4934bee..8e7f494 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -279,7 +279,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, 
unsigned int idx,
}
 
con = ovl_fmt_convert(ovl, fmt);
-   if (state->base.fb->format->has_alpha)
+   if (state->base.fb && state->base.fb->format->has_alpha)
con |= OVL_CON_AEN | OVL_CON_ALPHA;
 
if (pending->rotation & DRM_MODE_REFLECT_Y) {
-- 
1.8.1.1.dirty

[PATCH v3, 00/15] drm/mediatek: add support for mediatek SOC MT8192

2021-01-10 Thread Yongqiang Niu

This series are based on 5.11-rc1 and SoC MT8183,
and provide 15 patch to support mediatek SOC MT8192

Changes since v2:
- fix review comment in v2
- add pm runtime for gamma and color 
- move ddp path select patch to mmsys series
- remove some useless patch

Yongqiang Niu (15):
  dt-bindings: mediatek: add description for postmask
  dt-bindings: mediatek: add description for mt8192 display
  arm64: dts: mt8192: add display node
  drm/mediatek: add component OVL_2L2
  drm/mediatek: add component POSTMASK
  drm/mediatek: add component RDMA4
  drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
  drm/mediatek: check if fb is null
  drm/mediatek: Add pm runtime support for gamma
  drm/mediatek: Add pm runtime support for color
  drm/mediatek: fix aal size config
  drm/mediatek: separate ccorr module
  drm/mediatek: add matrix bits private data for ccorr
  drm/mediatek: add DDP support for MT8192
  drm/mediatek: add support for mediatek SOC MT8192

 .../bindings/display/mediatek/mediatek,disp.txt|   3 +-
 arch/arm64/boot/dts/mediatek/mt8192.dtsi   | 134 +++
 drivers/gpu/drm/mediatek/Makefile  |   4 +-
 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c  | 245 +
 drivers/gpu/drm/mediatek/mtk_disp_color.c  |   5 +
 drivers/gpu/drm/mediatek/mtk_disp_gamma.c  |   5 +
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c|  34 ++-
 drivers/gpu/drm/mediatek/mtk_disp_postmask.c   | 161 ++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c   |   6 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c |  35 +++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c|  98 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h|   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c |  52 -
 drivers/gpu/drm/mediatek/mtk_drm_drv.h |   2 +
 14 files changed, 687 insertions(+), 98 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c

-- 
1.8.1.1.dirty

[PATCH v3, 04/15] drm/mediatek: add component OVL_2L2

2021-01-10 Thread Yongqiang Niu

This patch add component OVL_2L2

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 81ed076..a715127 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -383,6 +383,7 @@ struct mtk_ddp_comp_match {
[DDP_COMPONENT_OVL1]= { MTK_DISP_OVL,   1, NULL },
[DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L,0, NULL },
[DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L,1, NULL },
+   [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L,2, NULL },
[DDP_COMPONENT_PWM0]= { MTK_DISP_PWM,   0, NULL },
[DDP_COMPONENT_PWM1]= { MTK_DISP_PWM,   1, NULL },
[DDP_COMPONENT_PWM2]= { MTK_DISP_PWM,   2, NULL },
-- 
1.8.1.1.dirty

[PATCH v3, 02/15] dt-bindings: mediatek: add description for mt8192 display

2021-01-10 Thread Yongqiang Niu

add description for mt8192 display

Signed-off-by: Yongqiang Niu 
Reviewed-by: Chun-Kuang Hu 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index 9d9ab65..b47e1a0 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -44,7 +44,7 @@ Required properties (all function blocks):
"mediatek,-dpi"   - DPI controller, see 
mediatek,dpi.txt
"mediatek,-disp-mutex"- display mutex
"mediatek,-disp-od"   - overdrive
-  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173 and mt8183.
+  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and 
mt8192.
 - reg: Physical base address and length of the function block register space
 - interrupts: The interrupt signal from the function block (required, except 
for
   merge and split function blocks).
-- 
1.8.1.1.dirty

Re: [PATCH v2] soc: mediatek: cmdq: add address shift in jump

2021-01-07 Thread Yongqiang Niu

On Wed, 2020-12-23 at 16:34 +0800, Yongqiang Niu wrote:
> Add address shift when compose jump instruction
> to compatible with 35bit format.
> 
> Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform")
> 
> Signed-off-by: Yongqiang Niu 
> Reviewed-by: Nicolas Boichat 
> ---
>  drivers/mailbox/mtk-cmdq-mailbox.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c 
> b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 5665b6e..75378e3 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -168,7 +168,8 @@ static void cmdq_task_insert_into_thread(struct cmdq_task 
> *task)
>   dma_sync_single_for_cpu(dev, prev_task->pa_base,
>   prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
>   prev_task_base[CMDQ_NUM_CMD(prev_task->pkt) - 1] =
> - (u64)CMDQ_JUMP_BY_PA << 32 | task->pa_base;
> + (u64)CMDQ_JUMP_BY_PA << 32 |
> + (task->pa_base >> task->cmdq->shift_pa);
>   dma_sync_single_for_device(dev, prev_task->pa_base,
>  prev_task->pkt->cmd_buf_size, DMA_TO_DEVICE);
>  

hi jassi

please confirm is there any question about this patch.
if not, please apply this into next version, tks

[PATCH v9, 10/11] drm/mediatek: add DDP support for MT8183

2021-01-06 Thread Yongqiang Niu

Add DDP support for MT8167 SoC.

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 48 ++
 1 file changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 1f99db6..1308046 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -15,6 +15,8 @@
 
 #define MT2701_DISP_MUTEX0_MOD00x2c
 #define MT2701_DISP_MUTEX0_SOF00x30
+#define MT8183_DISP_MUTEX0_MOD00x30
+#define MT8183_DISP_MUTEX0_SOF00x2c
 
 #define DISP_REG_MUTEX_EN(n)   (0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)  (0x24 + 0x20 * (n))
@@ -38,6 +40,18 @@
 #define MT8167_MUTEX_MOD_DISP_DITHER   15
 #define MT8167_MUTEX_MOD_DISP_UFOE 16
 
+#define MT8183_MUTEX_MOD_DISP_RDMA00
+#define MT8183_MUTEX_MOD_DISP_RDMA11
+#define MT8183_MUTEX_MOD_DISP_OVL0 9
+#define MT8183_MUTEX_MOD_DISP_OVL0_2L  10
+#define MT8183_MUTEX_MOD_DISP_OVL1_2L  11
+#define MT8183_MUTEX_MOD_DISP_WDMA012
+#define MT8183_MUTEX_MOD_DISP_COLOR0   13
+#define MT8183_MUTEX_MOD_DISP_CCORR0   14
+#define MT8183_MUTEX_MOD_DISP_AAL0 15
+#define MT8183_MUTEX_MOD_DISP_GAMMA0   16
+#define MT8183_MUTEX_MOD_DISP_DITHER0  17
+
 #define MT8173_MUTEX_MOD_DISP_OVL0 11
 #define MT8173_MUTEX_MOD_DISP_OVL1 12
 #define MT8173_MUTEX_MOD_DISP_RDMA013
@@ -89,6 +103,10 @@
 #define MT8167_MUTEX_SOF_DPI0  2
 #define MT8167_MUTEX_SOF_DPI1  3
 
+#define MT8183_MUTEX_SOF_DPI0  2
+#define MT8183_MUTEX_EOF_DSI0  (MUTEX_SOF_DSI0 << 6)
+#define MT8183_MUTEX_EOF_DPI0  (MT8183_MUTEX_SOF_DPI0 << 6)
+
 
 struct mtk_disp_mutex {
int id;
@@ -183,6 +201,20 @@ struct mtk_ddp {
[DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
 };
 
+static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+   [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
+   [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
+   [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
+   [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
+   [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
+   [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
+   [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
+   [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
+   [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
+   [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
+   [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
+};
+
 static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
[DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
@@ -200,6 +232,12 @@ struct mtk_ddp {
[DDP_MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
 };
 
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
+   [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+   [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
+   [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
+};
+
 static const struct mtk_ddp_data mt2701_ddp_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -229,6 +267,14 @@ struct mtk_ddp {
.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
 };
 
+static const struct mtk_ddp_data mt8183_ddp_driver_data = {
+   .mutex_mod = mt8183_mutex_mod,
+   .mutex_sof = mt8183_mutex_sof,
+   .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
+   .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
+   .no_clk = true,
+};
+
 struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
 {
struct mtk_ddp *ddp = dev_get_drvdata(dev);
@@ -449,6 +495,8 @@ static int mtk_ddp_remove(struct platform_device *pdev)
  .data = _ddp_driver_data},
{ .compatible = "mediatek,mt8173-disp-mutex",
  .data = _ddp_driver_data},
+   { .compatible = "mediatek,mt8183-disp-mutex",
+ .data = _ddp_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, ddp_driver_dt_match);
-- 
1.8.1.1.dirty

[PATCH v9, 11/11] This patch add support for mediatek SOC MT8183

2021-01-06 Thread Yongqiang Niu

1. add ovl private data
2. add rdma private data
3. add gamma privte data
4. add main and external path module for crtc create

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_disp_gamma.c |  1 +
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c   | 18 +
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c  |  6 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c| 45 +++
 4 files changed, 70 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
index 4eab82a..10fed3b 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
@@ -176,6 +176,7 @@ static int mtk_disp_gamma_remove(struct platform_device 
*pdev)
 static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = {
{ .compatible = "mediatek,mt8173-disp-gamma",
  .data = _gamma_driver_data},
+   { .compatible = "mediatek,mt8183-disp-gamma"},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c 
b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 74ef6fc..b47c238 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -431,11 +431,29 @@ static int mtk_disp_ovl_remove(struct platform_device 
*pdev)
.fmt_rgb565_is_0 = true,
 };
 
+static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
+   .addr = DISP_REG_OVL_ADDR_MT8173,
+   .gmc_bits = 10,
+   .layer_nr = 4,
+   .fmt_rgb565_is_0 = true,
+};
+
+static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
+   .addr = DISP_REG_OVL_ADDR_MT8173,
+   .gmc_bits = 10,
+   .layer_nr = 2,
+   .fmt_rgb565_is_0 = true,
+};
+
 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-ovl",
  .data = _ovl_driver_data},
{ .compatible = "mediatek,mt8173-disp-ovl",
  .data = _ovl_driver_data},
+   { .compatible = "mediatek,mt8183-disp-ovl",
+ .data = _ovl_driver_data},
+   { .compatible = "mediatek,mt8183-disp-ovl-2l",
+ .data = _ovl_2l_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 2d2cca2..e914e3a 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -360,11 +360,17 @@ static int mtk_disp_rdma_remove(struct platform_device 
*pdev)
.fifo_size = SZ_8K,
 };
 
+static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
+   .fifo_size = 5 * SZ_1K,
+};
+
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
  .data = _rdma_driver_data},
{ .compatible = "mediatek,mt8173-disp-rdma",
  .data = _rdma_driver_data},
+   { .compatible = "mediatek,mt8183-disp-rdma",
+ .data = _rdma_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c 
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 37fec25..b6e963e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -131,6 +131,24 @@
DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
+   DDP_COMPONENT_OVL0,
+   DDP_COMPONENT_OVL_2L0,
+   DDP_COMPONENT_RDMA0,
+   DDP_COMPONENT_COLOR0,
+   DDP_COMPONENT_CCORR,
+   DDP_COMPONENT_AAL0,
+   DDP_COMPONENT_GAMMA,
+   DDP_COMPONENT_DITHER,
+   DDP_COMPONENT_DSI0,
+};
+
+static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
+   DDP_COMPONENT_OVL_2L1,
+   DDP_COMPONENT_RDMA1,
+   DDP_COMPONENT_DPI0,
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -163,6 +181,13 @@
.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
+   .main_path = mt8183_mtk_ddp_main,
+   .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
+   .ext_path = mt8183_mtk_ddp_ext,
+   .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
+};
+
 static int mtk_drm_kms_init(struct drm_device *drm)
 {
struct mtk_drm_private *private = drm->dev_private;
@@ -377,12 +402,20 @@ static void mtk_drm_unbind(struct device *dev)
  .data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8173-disp-ovl",
  .data = (void *)MTK_DISP_OVL },
+   { .compatible = "mediatek,mt8183-disp-ovl",
+ .data = (void *)MTK_DISP_OVL },
+   { .compatible = "mediatek,mt8183-disp-ovl-2l"

[PATCH v9, 09/11] drm/mediatek: enable dither function

2021-01-06 Thread Yongqiang Niu

for 5 or 6 bpc panel, we need enable dither function
to improve the display quality

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 38 -
 1 file changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c 
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 03589c9..81ed076 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -53,7 +53,9 @@
 #define DITHER_EN  BIT(0)
 #define DISP_DITHER_CFG0x0020
 #define DITHER_RELAY_MODE  BIT(0)
+#define DITHER_ENGINE_EN   BIT(1)
 #define DISP_DITHER_SIZE   0x0030
+#define DITHER_REG(idx)(0x100 + (idx) * 4)
 
 #define LUT_10BIT_MASK 0x03ff
 
@@ -258,8 +260,42 @@ static void mtk_dither_config(struct mtk_ddp_comp *comp, 
unsigned int w,
  unsigned int h, unsigned int vrefresh,
  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 {
+   bool enable = true;
+
+   const u32 dither_setting[] = {
+   0x, /* 5 */
+   0x3002, /* 6 */
+   0x, /* 7 */
+   0x, /* 8 */
+   0x, /* 9 */
+   0x, /* 10 */
+   0x, /* 11 */
+   0x0011, /* 12 */
+   0x, /* 13 */
+   0x, /* 14 */
+   };
+
+   if (bpc == 6) {
+   mtk_ddp_write(cmdq_pkt, 0x4041, comp, DITHER_REG(15));
+   mtk_ddp_write(cmdq_pkt, 0x40404040, comp, DITHER_REG(16));
+   } else if (bpc == 5) {
+   mtk_ddp_write(cmdq_pkt, 0x5051, comp, DITHER_REG(15));
+   mtk_ddp_write(cmdq_pkt, 0x50504040, comp, DITHER_REG(16));
+   } else {
+   enable = false;
+   }
+
+   if (enable) {
+   u32 idx;
+
+   for (idx = 0; idx < ARRAY_SIZE(dither_setting); idx++)
+   mtk_ddp_write(cmdq_pkt, dither_setting[idx], comp,
+ DITHER_REG(idx + 5));
+   }
+
mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_DITHER_SIZE);
-   mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, DISP_DITHER_CFG);
+   mtk_ddp_write(cmdq_pkt, enable ? DITHER_ENGINE_EN : DITHER_RELAY_MODE,
+ comp, DISP_DITHER_CFG);
 }
 
 static void mtk_dither_start(struct mtk_ddp_comp *comp)
-- 
1.8.1.1.dirty

[PATCH v9, 07/11] drm/mediatek: separate gamma module

2021-01-06 Thread Yongqiang Niu

mt8183 gamma module will different with mt8173
separate gamma for add private data

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/Makefile   |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_gamma.c   | 185 
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  58 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |   4 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   1 +
 6 files changed, 192 insertions(+), 58 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_gamma.c

diff --git a/drivers/gpu/drm/mediatek/Makefile 
b/drivers/gpu/drm/mediatek/Makefile
index a892ede..17a08e2 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 
 mediatek-drm-y := mtk_disp_color.o \
+ mtk_disp_gamma.o \
  mtk_disp_ovl.o \
  mtk_disp_rdma.o \
  mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
new file mode 100644
index 000..8501821
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
@@ -0,0 +1,185 @@
+/*
+ * SPDX-License-Identifier:
+ *
+ * Copyright (c) 2020 MediaTek Inc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+#define DISP_GAMMA_EN  0x
+#define GAMMA_EN   BIT(0)
+#define DISP_GAMMA_CFG 0x0020
+#define GAMMA_LUT_EN   BIT(1)
+#define DISP_GAMMA_SIZE0x0030
+#define DISP_GAMMA_LUT 0x0700
+
+#define LUT_10BIT_MASK 0x03ff
+
+struct mtk_disp_gamma_data {
+   u32 reserved;
+};
+
+/**
+ * struct mtk_disp_gamma - DISP_GAMMA driver structure
+ * @ddp_comp - structure containing type enum and hardware resources
+ * @crtc - associated crtc to report irq events to
+ */
+struct mtk_disp_gamma {
+   struct mtk_ddp_comp ddp_comp;
+   const struct mtk_disp_gamma_data*data;
+};
+
+static inline struct mtk_disp_gamma *comp_to_gamma(struct mtk_ddp_comp *comp)
+{
+   return container_of(comp, struct mtk_disp_gamma, ddp_comp);
+}
+
+void mtk_gamma_set(struct mtk_ddp_comp *comp, struct drm_crtc_state *state)
+{
+   unsigned int i, reg;
+   struct drm_color_lut *lut;
+   void __iomem *lut_base;
+   u32 word;
+
+   if (state->gamma_lut) {
+   reg = readl(comp->regs + DISP_GAMMA_CFG);
+   reg = reg | GAMMA_LUT_EN;
+   writel(reg, comp->regs + DISP_GAMMA_CFG);
+   lut_base = comp->regs + DISP_GAMMA_LUT;
+   lut = (struct drm_color_lut *)state->gamma_lut->data;
+   for (i = 0; i < MTK_LUT_SIZE; i++) {
+   word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
+   (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
+   ((lut[i].blue >> 6) & LUT_10BIT_MASK);
+   writel(word, (lut_base + i * 4));
+   }
+   }
+}
+
+static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
+unsigned int h, unsigned int vrefresh,
+unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+   struct mtk_disp_gamma *gamma = comp_to_gamma(comp);
+
+   mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE);
+
+   mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt);
+}
+
+static void mtk_gamma_start(struct mtk_ddp_comp *comp)
+{
+   writel(GAMMA_EN, comp->regs  + DISP_GAMMA_EN);
+}
+
+static void mtk_gamma_stop(struct mtk_ddp_comp *comp)
+{
+   writel_relaxed(0x0, comp->regs + DISP_GAMMA_EN);
+}
+
+static const struct mtk_ddp_comp_funcs mtk_disp_gamma_funcs = {
+   .gamma_set = mtk_gamma_set,
+   .config = mtk_gamma_config,
+   .start = mtk_gamma_start,
+   .stop = mtk_gamma_stop,
+};
+
+static int mtk_disp_gamma_bind(struct device *dev, struct device *master,
+  void *data)
+{
+   struct mtk_disp_gamma *priv = dev_get_drvdata(dev);
+   struct drm_device *drm_dev = data;
+   int ret;
+
+   ret = mtk_ddp_comp_register(drm_dev, >ddp_comp);
+   if (ret < 0) {
+   dev_err(dev, "Failed to register component %pOF: %d\n",
+   dev->of_node, ret);
+   return ret;
+   }
+
+   return 0;
+}
+
+static void mtk_disp_gamma_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+   struct mtk_disp_gamma *priv = dev_get_drvdata(dev);
+   struct drm_devi

[PATCH v9, 05/11] drm/mediatek: add fifo_size into rdma private data

2021-01-06 Thread Yongqiang Niu

Get the fifo size from device tree
because each rdma in the same SoC may have different fifo size

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index d46b8ae..8c64d5c 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -64,6 +64,7 @@ struct mtk_disp_rdma {
struct mtk_ddp_comp ddp_comp;
struct drm_crtc *crtc;
const struct mtk_disp_rdma_data *data;
+   u32 fifo_size;
 };
 
 static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
@@ -132,12 +133,18 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, 
unsigned int width,
unsigned int threshold;
unsigned int reg;
struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
+   u32 rdma_fifo_size;
 
mtk_ddp_write_mask(cmdq_pkt, width, comp,
   DISP_REG_RDMA_SIZE_CON_0, 0xfff);
mtk_ddp_write_mask(cmdq_pkt, height, comp,
   DISP_REG_RDMA_SIZE_CON_1, 0xf);
 
+   if (rdma->fifo_size)
+   rdma_fifo_size = rdma->fifo_size;
+   else
+   rdma_fifo_size = RDMA_FIFO_SIZE(rdma);
+
/*
 * Enable FIFO underflow since DSI and DPI can't be blocked.
 * Keep the FIFO pseudo size reset default of 8 KiB. Set the
@@ -146,7 +153,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, 
unsigned int width,
 */
threshold = width * height * vrefresh * 4 * 7 / 100;
reg = RDMA_FIFO_UNDERFLOW_EN |
- RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) |
+ RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
  RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON);
 }
@@ -292,6 +299,16 @@ static int mtk_disp_rdma_probe(struct platform_device 
*pdev)
return comp_id;
}
 
+   if (of_find_property(dev->of_node, "mediatek,rdma-fifo-size", )) {
+   ret = of_property_read_u32(dev->of_node,
+  "mediatek,rdma-fifo-size",
+  >fifo_size);
+   if (ret) {
+   dev_err(dev, "Failed to get rdma fifo size\n");
+   return ret;
+   }
+   }
+
ret = mtk_ddp_comp_init(dev, dev->of_node, >ddp_comp, comp_id,
_disp_rdma_funcs);
if (ret) {
-- 
1.8.1.1.dirty

[PATCH v9, 08/11] drm/mediatek: add has_dither private data for gamma

2021-01-06 Thread Yongqiang Niu

not all SoC has dither function in gamma module
dd private data to control this function setting

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
index 8501821..4eab82a 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
@@ -24,7 +24,7 @@
 #define LUT_10BIT_MASK 0x03ff
 
 struct mtk_disp_gamma_data {
-   u32 reserved;
+   bool has_dither;
 };
 
 /**
@@ -72,7 +72,8 @@ static void mtk_gamma_config(struct mtk_ddp_comp *comp, 
unsigned int w,
 
mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE);
 
-   mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt);
+   if (gamma->data && gamma->data->has_dither)
+   mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt);
 }
 
 static void mtk_gamma_start(struct mtk_ddp_comp *comp)
@@ -168,8 +169,13 @@ static int mtk_disp_gamma_remove(struct platform_device 
*pdev)
return 0;
 }
 
+static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = {
+   .has_dither = true,
+};
+
 static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = {
-   { .compatible = "mediatek,mt8173-disp-gamma"},
+   { .compatible = "mediatek,mt8173-disp-gamma",
+ .data = _gamma_driver_data},
{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match);
-- 
1.8.1.1.dirty

[PATCH v9, 06/11] drm/mediatek: add RDMA fifo size error handle

2021-01-06 Thread Yongqiang Niu

This patch add RDMA fifo size error handle
rdma fifo size will not always bigger than the calculated threshold
if that case happened, we need set fifo size as the threshold

Signed-off-by: Yongqiang Niu 
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c 
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 8c64d5c..2d2cca2 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -152,6 +152,10 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, 
unsigned int width,
 * account for blanking, and with a pixel depth of 4 bytes:
 */
threshold = width * height * vrefresh * 4 * 7 / 100;
+
+   if (threshold > rdma_fifo_size)
+   threshold = rdma_fifo_size;
+
reg = RDMA_FIFO_UNDERFLOW_EN |
  RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
  RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
-- 
1.8.1.1.dirty

[PATCH v9, 02/11] dt-bindings: mediatek: add description for mt8183 display

2021-01-06 Thread Yongqiang Niu

add description for mt8183 display

Signed-off-by: Yongqiang Niu 
Reviewed-by: Chun-Kuang Hu 
Acked-by: Rob Herring 
---
 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index b07881e..c562cda 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -43,7 +43,7 @@ Required properties (all function blocks):
"mediatek,-dpi"   - DPI controller, see 
mediatek,dpi.txt
"mediatek,-disp-mutex"- display mutex
"mediatek,-disp-od"   - overdrive
-  the supported chips are mt2701, mt7623, mt2712, mt8167 and mt8173.
+  the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173 and mt8183.
 - reg: Physical base address and length of the function block register space
 - interrupts: The interrupt signal from the function block (required, except 
for
   merge and split function blocks).
-- 
1.8.1.1.dirty

[PATCH v9, 04/11] arm64: dts: mt8183: refine gamma compatible name

2021-01-06 Thread Yongqiang Niu

mt8183 gamma is different with mt8173
remove mt8173 compatible name for mt8183 gamma

Signed-off-by: Yongqiang Niu 
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 6c84ccb7..9c0073cf 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1055,8 +1055,7 @@
};
 
gamma0: gamma@14011000 {
-   compatible = "mediatek,mt8183-disp-gamma",
-"mediatek,mt8173-disp-gamma";
+   compatible = "mediatek,mt8183-disp-gamma";
reg = <0 0x14011000 0 0x1000>;
interrupts = ;
power-domains = < MT8183_POWER_DOMAIN_DISP>;
-- 
1.8.1.1.dirty

[PATCH v9, 03/11] arm64: dts: mt8183: rename rdma fifo size

2021-01-06 Thread Yongqiang Niu

property name must include only lowercase and '-'

Signed-off-by: Yongqiang Niu 
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi 
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 5b782a4..6c84ccb7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1011,7 +1011,7 @@
clocks = < CLK_MM_DISP_RDMA0>;
iommus = < M4U_PORT_DISP_RDMA0>;
mediatek,larb = <>;
-   mediatek,rdma_fifo_size = <5120>;
+   mediatek,rdma-fifo-size = <5120>;
mediatek,gce-client-reg = < SUBSYS_1400 0xb000 
0x1000>;
};
 
@@ -1023,7 +1023,7 @@
clocks = < CLK_MM_DISP_RDMA1>;
iommus = < M4U_PORT_DISP_RDMA1>;
mediatek,larb = <>;
-   mediatek,rdma_fifo_size = <2048>;
+   mediatek,rdma-fifo-size = <2048>;
mediatek,gce-client-reg = < SUBSYS_1400 0xc000 
0x1000>;
};
 
-- 
1.8.1.1.dirty

[PATCH v9, 01/11] dt-bindings: mediatek: add rdma-fifo-size description for mt8183 display

2021-01-06 Thread Yongqiang Niu

rdma fifo size may be different even in same SOC, add this
property to the corresponding rdma

Signed-off-by: Yongqiang Niu 
---
 .../devicetree/bindings/display/mediatek/mediatek,disp.txt   | 9 +
 1 file changed, 9 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt 
b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index 33977e1..b07881e 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -66,6 +66,14 @@ Required properties (DMA function blocks):
   argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
   for details.
 
+Optional properties (RDMA function blocks):
+- mediatek,rdma-fifo-size: rdma fifo size may be different even in same SOC, 
add this
+  property to the corresponding rdma
+  the value is the Max value which defined in hardware data sheet.
+  mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
+  mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
+  mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
+
 Examples:
 
 mmsys: clock-controller@1400 {
@@ -103,6 +111,7 @@ rdma0: rdma@1400e000 {
clocks = < CLK_MM_DISP_RDMA0>;
iommus = < M4U_PORT_DISP_RDMA0>;
mediatek,larb = <>;
+   mediatek,rdma-fifosize = <8192>;
 };
 
 rdma1: rdma@1400f000 {
-- 
1.8.1.1.dirty

[PATCH v9, 00/11] drm/mediatek: add support for mediatek SOC MT8183

2021-01-06 Thread Yongqiang Niu

This series are based on 5.11-rc1 and provide 11 patch
to support mediatek SOC MT8183

Change since v8
- fix some review comment in v8
- separate gamma module for mt8183 has no dither function in gamma
- enable dither function for 5 or 6 bpc panel display
- separate ddp mutex patch from the whole Soc patch

Change since v7
- add dt-binding for mt8183 display
- base mmsys patch
https://patchwork.kernel.org/project/linux-mediatek/cover/1607506379-10998-1-git-send-email-yongqiang@mediatek.com/
- base dts patch
https://patchwork.kernel.org/project/linux-mediatek/cover/20201127104930.1981497-1-enric.balle...@collabora.com/
- add mt8183 function call for setting the routing registers
- add RDMA fifo size error handle

Change since v6
- move ddp component define into mtk_mmsys.h
- add mmsys private data to support different ic path connection
- add mt8183-mmsys.c to support 8183 path connection
- fix reviewed issue in v6

Change since v5
- fix reviewed issue in v5
base https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219

Change since v4
- fix reviewed issue in v4

Change since v3
- fix reviewed issue in v3
- fix type error in v3
- fix conflict with iommu patch

Change since v2
- fix reviewed issue in v2
- add mutex node into dts file

Changes since v1:
- fix reviewed issue in v1
- add dts for mt8183 display nodes
- adjust display clock control flow in patch 22
- add vmap support for mediatek drm in patch 23
- fix page offset issue for mmap function in patch 24
- enable allow_fb_modifiers for mediatek drm in patch 25

Yongqiang Niu (11):
  dt-bindings: mediatek: add rdma-fifo-size description for mt8183
display
  dt-bindings: mediatek: add description for mt8183 display
  arm64: dts: mt8183: rename rdma fifo size
  arm64: dts: mt8183: refine gamma compatible name
  drm/mediatek: add fifo_size into rdma private data
  drm/mediatek: add RDMA fifo size error handle
  drm/mediatek: separate gamma module
  drm/mediatek: add has_dither private data for gamma
  drm/mediatek: enable dither function
  drm/mediatek: add DDP support for MT8183
  This patch add support for mediatek SOC MT8183

 .../bindings/display/mediatek/mediatek,disp.txt|  11 +-
 arch/arm64/boot/dts/mediatek/mt8183.dtsi   |   7 +-
 drivers/gpu/drm/mediatek/Makefile  |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_gamma.c  | 192 +
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c|  18 ++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c   |  29 +++-
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c |  48 ++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c|  96 ---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h|   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c |  49 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h |   1 +
 11 files changed, 388 insertions(+), 65 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_gamma.c

-- 
1.8.1.1.dirty

Re: [PATCH v8, 5/6] drm/mediatek: add RDMA fifo size error handle

2021-01-04 Thread Yongqiang Niu

On Mon, 2020-12-14 at 22:54 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
> 
> Yongqiang Niu  於 2020年12月11日 週五 上午8:45寫道：
> >
> > On Thu, 2020-12-10 at 23:50 +0800, Chun-Kuang Hu wrote:
> > > Hi, Yongqiang:
> > >
> > > Yongqiang Niu  於 2020年12月10日 週四 下午5:08寫道：
> > > >
> > > > This patch add RDMA fifo size error handle
> > > > rdma fifo size will not always bigger than the calculated threshold
> > > > if that case happened, we need set fifo size as the threshold
> > > >
> > > > Signed-off-by: Yongqiang Niu 
> > > > ---
> > > >  drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4 
> > > >  1 file changed, 4 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c 
> > > > b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > > > index 794acc5..0508392 100644
> > > > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> > > > @@ -151,6 +151,10 @@ static void mtk_rdma_config(struct mtk_ddp_comp 
> > > > *comp, unsigned int width,
> > > >  * account for blanking, and with a pixel depth of 4 bytes:
> > > >  */
> > > > threshold = width * height * vrefresh * 4 * 7 / 100;
> > > > +
> > > > +   if (threshold > rdma_fifo_size)
> > > > +   threshold = rdma_fifo_size;
> > >
> > > If the formula is not correct, you should fix the formula not work around.
> > >
> > > Regards,
> > > Chun-Kuang.
> >
> > how about this:
> > threshold = max(width * height * vrefresh * 4 * 7 / 100,
> > rdma_fifo_size);
> 
> When I use width = 1920, height = 1080, vrefresh = 60 to calculate, I
> get threshold = 2985.
> So I think set threshold to half of fifo size is OK for MAX_WIDTH,
> MAX_HEIGHT, MAX_VREFRESH (these three may be different in each SoC)
> 
> threshold = RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) / 2;
> 
> But I worry half fifo size is too big for small resolution and let
> small resolution too easy to trigger burst read DRAM. So let the
> formula to be this:
> 
> threshold = RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) * width * height *
> vrefresh / 2 / MAX_WIDTH / MAX_HEIGHT / MAX_VREFRESH;
> 
> How do you think about this?
> 
> Regards,
> Chun-Kuang.

how about remove this formula, and set threshold = rdma_fifo_size
> 
> > >
> > > > +
> > > > reg = RDMA_FIFO_UNDERFLOW_EN |
> > > >   RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
> > > >   RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
> > > > --
> > > > 1.8.1.1.dirty
> > > > ___
> > > > Linux-mediatek mailing list
> > > > linux-media...@lists.infradead.org
> > > > http://lists.infradead.org/mailman/listinfo/linux-mediatek
> >

[PATCH v4, 07/10] soc: mediatek: mmsys: add component POSTMASK

2021-01-04 Thread Yongqiang Niu

This patch add component POSTMASK

Signed-off-by: Yongqiang Niu 
---
 include/linux/soc/mediatek/mtk-mmsys.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/soc/mediatek/mtk-mmsys.h 
b/include/linux/soc/mediatek/mtk-mmsys.h
index ed99122..13546e9 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -31,6 +31,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL_2L1,
DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
+   DDP_COMPONENT_POSTMASK0,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
DDP_COMPONENT_PWM2,
-- 
1.8.1.1.dirty

[PATCH v4, 10/10] soc: mediatek: mmsys: add mt8192 mmsys support

2021-01-04 Thread Yongqiang Niu

add mt8192 mmsys support

Signed-off-by: Yongqiang Niu 
---
 drivers/soc/mediatek/mmsys/Makefile   |   1 +
 drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 ++
 drivers/soc/mediatek/mmsys/mtk-mmsys.c|   9 ++
 include/linux/soc/mediatek/mtk-mmsys.h|   1 +
 4 files changed, 160 insertions(+)
 create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c

diff --git a/drivers/soc/mediatek/mmsys/Makefile 
b/drivers/soc/mediatek/mmsys/Makefile
index 25eeb9e5..7508cd3 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
 obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o
 obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c 
b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
new file mode 100644
index 000..2e350d1
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MMSYS_OVL_MOUT_EN  0xf04
+#define DISP_OVL0_GO_BLEND BIT(0)
+#define DISP_OVL0_GO_BGBIT(1)
+#define DISP_OVL0_2L_GO_BLEND  BIT(2)
+#define DISP_OVL0_2L_GO_BG BIT(3)
+#define DISP_OVL1_2L_MOUT_EN   0xf08
+#define OVL1_2L_MOUT_EN_RDMA1  BIT(4)
+#define DISP_OVL0_2L_MOUT_EN   0xf18
+#define DISP_OVL0_MOUT_EN  0xf1c
+#define OVL0_MOUT_EN_DISP_RDMA0BIT(0)
+#define OVL0_MOUT_EN_OVL0_2L   BIT(4)
+#define DISP_RDMA0_SEL_IN  0xf2c
+#define RDMA0_SEL_IN_OVL0_2L   0x3
+#define DISP_RDMA0_SOUT_SEL0xf30
+#define RDMA0_SOUT_COLOR0  0x1
+#define DISP_CCORR0_SOUT_SEL   0xf34
+#define CCORR0_SOUT_AAL0   0x1
+#define DISP_AAL0_SEL_IN   0xf38
+#define AAL0_SEL_IN_CCORR0 0x1
+#define DISP_DITHER0_MOUT_EN   0xf3c
+#define DITHER0_MOUT_DSI0  BIT(0)
+#define DISP_DSI0_SEL_IN   0xf40
+#define DSI0_SEL_IN_DITHER00x1
+#define DISP_OVL2_2L_MOUT_EN   0xf4c
+#define OVL2_2L_MOUT_RDMA4 BIT(0)
+
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+   unsigned int addr, value, reg;
+
+   if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+   addr = DISP_OVL0_2L_MOUT_EN;
+   value = OVL0_MOUT_EN_DISP_RDMA0;
+   } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) 
{
+   addr = DISP_OVL2_2L_MOUT_EN;
+   value = OVL2_2L_MOUT_RDMA4;
+   } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+   addr = DISP_DITHER0_MOUT_EN;
+   value = DITHER0_MOUT_DSI0;
+   } else {
+   value = 0;
+   }
+
+   if (value) {
+   reg = readl_relaxed(config_regs + addr);
+
+   if (enable)
+   reg |= value;
+   else
+   reg &= ~value;
+
+   writel_relaxed(reg, config_regs + addr);
+   }
+}
+
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+enum mtk_ddp_comp_id cur,
+enum mtk_ddp_comp_id next,
+bool enable)
+{
+   unsigned int addr, value, reg;
+
+   if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+   addr = DISP_RDMA0_SEL_IN;
+   value = RDMA0_SEL_IN_OVL0_2L;
+   } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
+   addr = DISP_AAL0_SEL_IN;
+   value = AAL0_SEL_IN_CCORR0;
+   } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+   addr = DISP_DSI0_SEL_IN;
+   value = DSI0_SEL_IN_DITHER0;
+   } else {
+   value = 0;
+   }
+
+   if (value) {
+   reg = readl_relaxed(config_regs + addr);
+
+   if (enable)
+   reg |= value;
+   else
+   reg &= ~value;
+
+   writel_relaxed(reg, config_regs + addr);
+   }
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+  enum mtk_ddp_comp_id cur,
+  enum mtk_ddp_comp_id next)
+{
+   if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMP

[PATCH v4, 04/10] soc: mediatek: mmsys: Use function call for setting the routing registers

2021-01-04 Thread Yongqiang Niu

Actually, setting the registers for routing, use multiple 'if-else' for 
different
routes, but this code would be more and more complicated while we
support more and more SoCs. Change that and use a function call per SoC so the
code will be more portable and clear.

Signed-off-by: Yongqiang Niu 
---
 drivers/soc/mediatek/mmsys/Makefile   |   1 +
 drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 254 
 drivers/soc/mediatek/mmsys/mtk-mmsys.c| 266 +++---
 include/linux/soc/mediatek/mtk-mmsys.h|  16 ++
 4 files changed, 295 insertions(+), 242 deletions(-)
 create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c

diff --git a/drivers/soc/mediatek/mmsys/Makefile 
b/drivers/soc/mediatek/mmsys/Makefile
index f44eadc..ac03025 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,2 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
 obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c 
b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
new file mode 100644
index 000..6bcc5f2
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN  0x040
+#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN  0x044
+#define DISP_REG_CONFIG_DISP_OD_MOUT_EN0x048
+#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
+#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN  0x050
+#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
+#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
+#define DISP_REG_CONFIG_DSIE_SEL_IN0x0a4
+#define DISP_REG_CONFIG_DSIO_SEL_IN0x0a8
+#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
+#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8
+#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
+#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
+#define DISP_REG_CONFIG_MMSYS_CG_CON0  0x100
+
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN   0x030
+#define DISP_REG_CONFIG_OUT_SEL0x04c
+#define DISP_REG_CONFIG_DSI_SEL0x050
+#define DISP_REG_CONFIG_DPI_SEL0x064
+
+#define OVL0_MOUT_EN_COLOR00x1
+#define OD_MOUT_EN_RDMA0   0x1
+#define OD1_MOUT_EN_RDMA1  BIT(16)
+#define UFOE_MOUT_EN_DSI0  0x1
+#define COLOR0_SEL_IN_OVL0 0x1
+#define OVL1_MOUT_EN_COLOR10x1
+#define GAMMA_MOUT_EN_RDMA10x1
+#define RDMA0_SOUT_DPI00x2
+#define RDMA0_SOUT_DPI10x3
+#define RDMA0_SOUT_DSI10x1
+#define RDMA0_SOUT_DSI20x4
+#define RDMA0_SOUT_DSI30x5
+#define RDMA1_SOUT_DPI00x2
+#define RDMA1_SOUT_DPI10x3
+#define RDMA1_SOUT_DSI10x1
+#define RDMA1_SOUT_DSI20x4
+#define RDMA1_SOUT_DSI30x5
+#define RDMA2_SOUT_DPI00x2
+#define RDMA2_SOUT_DPI10x3
+#define RDMA2_SOUT_DSI10x1
+#define RDMA2_SOUT_DSI20x4
+#define RDMA2_SOUT_DSI30x5
+#define DPI0_SEL_IN_RDMA1  0x1
+#define DPI0_SEL_IN_RDMA2  0x3
+#define DPI1_SEL_IN_RDMA1  (0x1 << 8)
+#define DPI1_SEL_IN_RDMA2  (0x3 << 8)
+#define DSI0_SEL_IN_RDMA1  0x1
+#define DSI0_SEL_IN_RDMA2  0x4
+#define DSI1_SEL_IN_RDMA1  0x1
+#define DSI1_SEL_IN_RDMA2  0x4
+#define DSI2_SEL_IN_RDMA1  (0x1 << 16)
+#define DSI2_SEL_IN_RDMA2  (0x4 << 16)
+#define DSI3_SEL_IN_RDMA1  (0x1 << 16)
+#define DSI3_SEL_IN_RDMA2  (0x4 << 16)
+#define COLOR1_SEL_IN_OVL1 0x1
+
+#define OVL_MOUT_EN_RDMA   0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1   0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI0x2
+#define DSI_SEL_IN_BLS 0x0
+#define DPI_SEL_IN_BLS 0x0
+#define DSI_SEL_IN_RDMA0x1
+
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+

[PATCH v4, 05/10] soc: mediatek: mmsys: add mt8183 function call for setting the routing registers

2021-01-04 Thread Yongqiang Niu

add mt8183 function call for setting the routing registers

Signed-off-by: Yongqiang Niu 
---
 drivers/soc/mediatek/mmsys/Makefile   |   1 +
 drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 110 ++
 drivers/soc/mediatek/mmsys/mtk-mmsys.c|   1 +
 include/linux/soc/mediatek/mtk-mmsys.h|   1 +
 4 files changed, 113 insertions(+)
 create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c

diff --git a/drivers/soc/mediatek/mmsys/Makefile 
b/drivers/soc/mediatek/mmsys/Makefile
index ac03025..25eeb9e5 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
 obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c 
b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c
new file mode 100644
index 000..8311f89
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DISP_OVL0_MOUT_EN  0xf00
+#define DISP_OVL0_2L_MOUT_EN   0xf04
+#define DISP_OVL1_2L_MOUT_EN   0xf08
+#define DISP_DITHER0_MOUT_EN   0xf0c
+#define DISP_PATH0_SEL_IN  0xf24
+#define DISP_DSI0_SEL_IN   0xf2c
+#define DISP_DPI0_SEL_IN   0xf30
+#define DISP_RDMA0_SOUT_SEL_IN 0xf50
+#define DISP_RDMA1_SOUT_SEL_IN 0xf54
+
+#define OVL0_MOUT_EN_OVL0_2L   BIT(4)
+#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
+#define OVL1_2L_MOUT_EN_RDMA1  BIT(4)
+#define DITHER0_MOUT_IN_DSI0   BIT(0)
+#define DISP_PATH0_SEL_IN_OVL0_2L  0x1
+#define DSI0_SEL_IN_RDMA0  0x1
+#define DSI0_SEL_IN_RDMA1  0x3
+#define DPI0_SEL_IN_RDMA0  0x1
+#define DPI0_SEL_IN_RDMA1  0x2
+#define RDMA0_SOUT_COLOR0  0x1
+#define RDMA1_SOUT_DSI00x1
+
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
+{
+   unsigned int addr, value, reg;
+
+   if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) {
+   addr = DISP_OVL0_MOUT_EN;
+   value = OVL0_MOUT_EN_OVL0_2L;
+   } else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) 
{
+   addr = DISP_OVL0_2L_MOUT_EN;
+   value = OVL0_2L_MOUT_EN_DISP_PATH0;
+   } else if (cur == DDP_COMPONENT_OVL_2L1 && next == DDP_COMPONENT_RDMA1) 
{
+   addr = DISP_OVL1_2L_MOUT_EN;
+   value = OVL1_2L_MOUT_EN_RDMA1;
+   } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+   addr = DISP_DITHER0_MOUT_EN;
+   value = DITHER0_MOUT_IN_DSI0;
+   } else {
+   value = 0;
+   }
+
+   if (value) {
+   reg = readl_relaxed(config_regs + addr);
+
+   if (enable)
+   reg |= value;
+   else
+   reg &= ~value;
+
+   writel_relaxed(reg, config_regs + addr);
+   }
+}
+
+static void mtk_mmsys_ddp_sel_in(void __iomem *config_regs,
+enum mtk_ddp_comp_id cur,
+enum mtk_ddp_comp_id next,
+bool enable)
+{
+   unsigned int addr, value, reg;
+
+   if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+   addr = DISP_PATH0_SEL_IN;
+   value = DISP_PATH0_SEL_IN_OVL0_2L;
+   } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+   addr = DISP_DPI0_SEL_IN;
+   value = DPI0_SEL_IN_RDMA1;
+   } else {
+   value = 0;
+   }
+
+   if (value) {
+   reg = readl_relaxed(config_regs + addr);
+
+   if (enable)
+   reg |= value;
+   else
+   reg &= ~value;
+
+   writel_relaxed(reg, config_regs + addr);
+   }
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+  enum mtk_ddp_comp_id cur,
+  enum mtk_ddp_comp_id next)
+{
+   if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
+   writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + 
DISP_RDMA0_SOUT_SEL_IN);
+   }
+}
+
+struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs = {
+   .mout_en = mtk_mmsys_ddp_mout_en,
+   .sel_in = mtk_mmsys_ddp_sel_in,
+

[PATCH v4, 09/10] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register

2021-01-04 Thread Yongqiang Niu

Use function call for setting mmsys ovl mout register

Signed-off-by: Yongqiang Niu 
---
 drivers/soc/mediatek/mmsys/mtk-mmsys.c | 6 ++
 include/linux/soc/mediatek/mtk-mmsys.h | 4 
 2 files changed, 10 insertions(+)

diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c 
b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 075d356..34728ed 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -68,6 +68,9 @@ void mtk_mmsys_ddp_connect(struct device *dev,
 
if (funcs->sel_in)
funcs->sel_in(mmsys->regs, cur, next, true);
+
+   if (funcs->ovl_mout_en)
+   funcs->ovl_mout_en(mmsys->regs, cur, next, true);
 }
 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
 
@@ -86,6 +89,9 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
 
if (funcs->sel_in)
funcs->sel_in(mmsys->regs, cur, next, false);
+
+   if (funcs->ovl_mout_en)
+   funcs->ovl_mout_en(mmsys->regs, cur, next, false);
 }
 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
 
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h 
b/include/linux/soc/mediatek/mtk-mmsys.h
index 2c11617..19318d2 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -50,6 +50,10 @@ struct mtk_mmsys_conn_funcs {
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next,
bool enable);
+   void (*ovl_mout_en)(void __iomem *config_regs,
+   enum mtk_ddp_comp_id cur,
+   enum mtk_ddp_comp_id next,
+   bool enable);
void (*sel_in)(void __iomem *config_regs,
   enum mtk_ddp_comp_id cur,
   enum mtk_ddp_comp_id next,
-- 
1.8.1.1.dirty

[PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder

2021-01-04 Thread Yongqiang Niu

the mmsys will more and more complicated after support
more and more SoCs, add an independent folder will be
more clear

Signed-off-by: Yongqiang Niu 
---
 drivers/soc/mediatek/Makefile  |   2 +-
 drivers/soc/mediatek/mmsys/Makefile|   2 +
 drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 +
 drivers/soc/mediatek/mtk-mmsys.c   | 373 -
 4 files changed, 376 insertions(+), 374 deletions(-)
 create mode 100644 drivers/soc/mediatek/mmsys/Makefile
 create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
 delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c

diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b6908db..eca9774 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
 obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
 obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
 obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o
-obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mmsys/
diff --git a/drivers/soc/mediatek/mmsys/Makefile 
b/drivers/soc/mediatek/mmsys/Makefile
new file mode 100644
index 000..f44eadc
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c 
b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
new file mode 100644
index 000..18f9397
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN  0x040
+#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN  0x044
+#define DISP_REG_CONFIG_DISP_OD_MOUT_EN0x048
+#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
+#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN  0x050
+#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
+#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
+#define DISP_REG_CONFIG_DSIE_SEL_IN0x0a4
+#define DISP_REG_CONFIG_DSIO_SEL_IN0x0a8
+#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
+#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8
+#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
+#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
+#define DISP_REG_CONFIG_MMSYS_CG_CON0  0x100
+
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN   0x030
+#define DISP_REG_CONFIG_OUT_SEL0x04c
+#define DISP_REG_CONFIG_DSI_SEL0x050
+#define DISP_REG_CONFIG_DPI_SEL0x064
+
+#define OVL0_MOUT_EN_COLOR00x1
+#define OD_MOUT_EN_RDMA0   0x1
+#define OD1_MOUT_EN_RDMA1  BIT(16)
+#define UFOE_MOUT_EN_DSI0  0x1
+#define COLOR0_SEL_IN_OVL0 0x1
+#define OVL1_MOUT_EN_COLOR10x1
+#define GAMMA_MOUT_EN_RDMA10x1
+#define RDMA0_SOUT_DPI00x2
+#define RDMA0_SOUT_DPI10x3
+#define RDMA0_SOUT_DSI10x1
+#define RDMA0_SOUT_DSI20x4
+#define RDMA0_SOUT_DSI30x5
+#define RDMA1_SOUT_DPI00x2
+#define RDMA1_SOUT_DPI10x3
+#define RDMA1_SOUT_DSI10x1
+#define RDMA1_SOUT_DSI20x4
+#define RDMA1_SOUT_DSI30x5
+#define RDMA2_SOUT_DPI00x2
+#define RDMA2_SOUT_DPI10x3
+#define RDMA2_SOUT_DSI10x1
+#define RDMA2_SOUT_DSI20x4
+#define RDMA2_SOUT_DSI30x5
+#define DPI0_SEL_IN_RDMA1  0x1
+#define DPI0_SEL_IN_RDMA2  0x3
+#define DPI1_SEL_IN_RDMA1  (0x1 << 8)
+#define DPI1_SEL_IN_RDMA2  (0x3 << 8)
+#define DSI0_SEL_IN_RDMA1  0x1
+#define DSI0_SEL_IN_RDMA2  0x4
+#define DSI1_SEL_IN_RDMA1  0x1
+#define DSI1_SEL_IN_RDMA2  0x4
+#define DSI2_SEL_IN_RDMA1  (0x1 << 16)
+#define DSI2_SEL_IN_RDMA2  (0x4 << 16)
+#define DSI3_SEL_IN_RDMA1  (0x1 << 16)
+#define DSI3_SEL_IN_RDMA2  (0x4 << 16)
+#define COLOR1_SEL_IN_OVL1 0x1
+
+#define OVL_MOUT_EN_RDMA   0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1   0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI0x2
+#define DSI_SEL_IN_BLS

[PATCH v4, 06/10] soc: mediatek: mmsys: add component OVL_2L2

2021-01-04 Thread Yongqiang Niu

This patch add component OVL_2L2

Signed-off-by: Yongqiang Niu 
Reviewed-by: Chun-Kuang Hu 
---
 include/linux/soc/mediatek/mtk-mmsys.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/soc/mediatek/mtk-mmsys.h 
b/include/linux/soc/mediatek/mtk-mmsys.h
index 7e2c0fe..ed99122 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -29,6 +29,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
+   DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
-- 
1.8.1.1.dirty

[PATCH v4, 08/10] soc: mediatek: mmsys: add component RDMA4

2021-01-04 Thread Yongqiang Niu

This patch add component RDMA4

Signed-off-by: Yongqiang Niu 
Reviewed-by: Chun-Kuang Hu 
---
 include/linux/soc/mediatek/mtk-mmsys.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/soc/mediatek/mtk-mmsys.h 
b/include/linux/soc/mediatek/mtk-mmsys.h
index 13546e9..2c11617 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -38,6 +38,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_RDMA1,
DDP_COMPONENT_RDMA2,
+   DDP_COMPONENT_RDMA4,
DDP_COMPONENT_UFOE,
DDP_COMPONENT_WDMA0,
DDP_COMPONENT_WDMA1,
-- 
1.8.1.1.dirty

[PATCH v4, 02/10] soc: mediatek: mmsys: Create struct mtk_mmsys to store context data

2021-01-04 Thread Yongqiang Niu

Apart from the driver data, in order to extend the driver to support more
and more SoCs, we will need to store other configuration data. So, create
a mtk_mmsys struct to encapsulate all that information.

Signed-off-by: CK Hu 
Signed-off-by: Enric Balletbo i Serra 
Signed-off-by: Yongqiang Niu 
Reviewed-by: Chun-Kuang Hu 
---
 drivers/soc/mediatek/mmsys/mtk-mmsys.c | 47 +++---
 1 file changed, 27 insertions(+), 20 deletions(-)

diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c 
b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 18f9397..6c03282 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -77,6 +77,11 @@ struct mtk_mmsys_driver_data {
const char *clk_driver;
 };
 
+struct mtk_mmsys {
+   void __iomem *regs;
+   const struct mtk_mmsys_driver_data *data;
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
 };
@@ -259,21 +264,21 @@ void mtk_mmsys_ddp_connect(struct device *dev,
   enum mtk_ddp_comp_id cur,
   enum mtk_ddp_comp_id next)
 {
-   void __iomem *config_regs = dev_get_drvdata(dev);
+   struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
unsigned int addr, value, reg;
 
value = mtk_mmsys_ddp_mout_en(cur, next, );
if (value) {
-   reg = readl_relaxed(config_regs + addr) | value;
-   writel_relaxed(reg, config_regs + addr);
+   reg = readl_relaxed(mmsys->regs + addr) | value;
+   writel_relaxed(reg, mmsys->regs + addr);
}
 
-   mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
+   mtk_mmsys_ddp_sout_sel(mmsys->regs, cur, next);
 
value = mtk_mmsys_ddp_sel_in(cur, next, );
if (value) {
-   reg = readl_relaxed(config_regs + addr) | value;
-   writel_relaxed(reg, config_regs + addr);
+   reg = readl_relaxed(mmsys->regs + addr) | value;
+   writel_relaxed(reg, mmsys->regs + addr);
}
 }
 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
@@ -282,44 +287,46 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
  enum mtk_ddp_comp_id cur,
  enum mtk_ddp_comp_id next)
 {
-   void __iomem *config_regs = dev_get_drvdata(dev);
+   struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
unsigned int addr, value, reg;
 
value = mtk_mmsys_ddp_mout_en(cur, next, );
if (value) {
-   reg = readl_relaxed(config_regs + addr) & ~value;
-   writel_relaxed(reg, config_regs + addr);
+   reg = readl_relaxed(mmsys->regs + addr) & ~value;
+   writel_relaxed(reg, mmsys->regs + addr);
}
 
value = mtk_mmsys_ddp_sel_in(cur, next, );
if (value) {
-   reg = readl_relaxed(config_regs + addr) & ~value;
-   writel_relaxed(reg, config_regs + addr);
+   reg = readl_relaxed(mmsys->regs + addr) & ~value;
+   writel_relaxed(reg, mmsys->regs + addr);
}
 }
 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
 
 static int mtk_mmsys_probe(struct platform_device *pdev)
 {
-   const struct mtk_mmsys_driver_data *data;
struct device *dev = >dev;
struct platform_device *clks;
struct platform_device *drm;
-   void __iomem *config_regs;
+   struct mtk_mmsys *mmsys;
int ret;
 
-   config_regs = devm_platform_ioremap_resource(pdev, 0);
-   if (IS_ERR(config_regs)) {
-   ret = PTR_ERR(config_regs);
+   mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
+   if (!mmsys)
+   return -ENOMEM;
+
+   mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
+   if (IS_ERR(mmsys->regs)) {
+   ret = PTR_ERR(mmsys->regs);
dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
return ret;
}
 
-   platform_set_drvdata(pdev, config_regs);
-
-   data = of_device_get_match_data(>dev);
+   mmsys->data = of_device_get_match_data(>dev);
+   platform_set_drvdata(pdev, mmsys);
 
-   clks = platform_device_register_data(>dev, data->clk_driver,
+   clks = platform_device_register_data(>dev, 
mmsys->data->clk_driver,
 PLATFORM_DEVID_AUTO, NULL, 0);
if (IS_ERR(clks))
return PTR_ERR(clks);
-- 
1.8.1.1.dirty

[PATCH v4, 03/10] soc: mediatek: mmsys: move register operation into mmsys path select function

2021-01-04 Thread Yongqiang Niu

move register operation into mmsys path select function

Signed-off-by: Yongqiang Niu 
---
 drivers/soc/mediatek/mmsys/mtk-mmsys.c | 140 +
 1 file changed, 71 insertions(+), 69 deletions(-)

diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c 
b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index 6c03282..64c8030 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -106,141 +106,161 @@ struct mtk_mmsys {
.clk_driver = "clk-mt8183-mm",
 };
 
-static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
- enum mtk_ddp_comp_id next,
- unsigned int *addr)
+static void mtk_mmsys_ddp_mout_en(void __iomem *config_regs,
+ enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ bool enable)
 {
-   unsigned int value;
+   unsigned int addr, value, reg;
 
if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
-   *addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
value = OVL0_MOUT_EN_COLOR0;
} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
-   *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
value = OVL_MOUT_EN_RDMA;
} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
-   *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD_MOUT_EN_RDMA0;
} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
-   *addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
value = UFOE_MOUT_EN_DSI0;
} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
-   *addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
value = OVL1_MOUT_EN_COLOR1;
} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
-   *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
value = GAMMA_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
-   *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD1_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DPI0;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DPI1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
value = RDMA0_SOUT_DSI3;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI2;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DSI3;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
-   *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+   addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
value = RDMA1_SOUT_DPI0;

[PATCH v4, 00/10] soc: mediatek: mmsys: Use function call for setting the routing registers

2021-01-04 Thread Yongqiang Niu

The following series are intended to prepare the mtk-mmsys driver to
allow different DDP (Data Display Path) function call per SoC.

base 5.11-rc1

change since v3:
- move register operation into mmsys path select function

Yongqiang Niu (10):
  soc: mediatek: mmsys: create mmsys folder
  soc: mediatek: mmsys: Create struct mtk_mmsys to store context data
  soc: mediatek: mmsys: move register operation into mmsys path select
function
  soc: mediatek: mmsys: Use function call for setting the routing
registers
  soc: mediatek: mmsys: add mt8183 function call for setting the routing
registers
  soc: mediatek: mmsys: add component OVL_2L2
  soc: mediatek: mmsys: add component POSTMASK
  soc: mediatek: mmsys: add component RDMA4
  soc: mediatek: mmsys: Use function call for setting mmsys ovl mout
register
  soc: mediatek: mmsys: add mt8192 mmsys support

 drivers/soc/mediatek/Makefile |   2 +-
 drivers/soc/mediatek/mmsys/Makefile   |   5 +
 drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 254 
 drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 110 +
 drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 149 
 drivers/soc/mediatek/mmsys/mtk-mmsys.c| 180 ++
 drivers/soc/mediatek/mtk-mmsys.c  | 373 --
 include/linux/soc/mediatek/mtk-mmsys.h|  25 ++
 8 files changed, 724 insertions(+), 374 deletions(-)
 create mode 100644 drivers/soc/mediatek/mmsys/Makefile
 create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c
 create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c
 create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
 create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
 delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c

-- 
1.8.1.1.dirty

Re: [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder

2021-01-03 Thread Yongqiang Niu

On Thu, 2020-12-31 at 09:21 +0800, Nicolas Boichat wrote:
> On Mon, Dec 28, 2020 at 4:38 PM Yongqiang Niu
>  wrote:
> >
> > the mmsys will more and more complicated after support
> > more and more SoCs, add an independent folder will be
> > more clear
> >
> > Signed-off-by: Yongqiang Niu 
> > ---
> >  drivers/soc/mediatek/Makefile  |   2 +-
> >  drivers/soc/mediatek/mmsys/Makefile|   2 +
> >  drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 
> > +
> >  drivers/soc/mediatek/mtk-mmsys.c   | 380 
> > -
> 
> I wonder why this doesn't get detected as a rename?
> 

git commit --amend
[detached HEAD 1f10c05] soc: mediatek: mmsys: create mmsys folder
 3 files changed, 3 insertions(+), 1 deletion(-)
 create mode 100644 drivers/soc/mediatek/mmsys/Makefile
 rename drivers/soc/mediatek/{ => mmsys}/mtk-mmsys.c (100%)


> >  4 files changed, 383 insertions(+), 381 deletions(-)
> >  create mode 100644 drivers/soc/mediatek/mmsys/Makefile
> >  create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
> >  delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
> >
> > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> > index 01f9f87..b5987ca 100644
> > --- a/drivers/soc/mediatek/Makefile
> > +++ b/drivers/soc/mediatek/Makefile
> > @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
> >  obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
> >  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> >  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> > -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> > +obj-$(CONFIG_MTK_MMSYS) += mmsys/
> > diff --git a/drivers/soc/mediatek/mmsys/Makefile 
> > b/drivers/soc/mediatek/mmsys/Makefile
> > new file mode 100644
> > index 000..5d976d7
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mmsys/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> > \ No newline at end of file
> 
> Nit: newline at end of file please.

Re: [PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder

2021-01-03 Thread Yongqiang Niu

On Thu, 2020-12-31 at 09:21 +0800, Nicolas Boichat wrote:
> On Mon, Dec 28, 2020 at 4:38 PM Yongqiang Niu
>  wrote:
> >
> > the mmsys will more and more complicated after support
> > more and more SoCs, add an independent folder will be
> > more clear
> >
> > Signed-off-by: Yongqiang Niu 
> > ---
> >  drivers/soc/mediatek/Makefile  |   2 +-
> >  drivers/soc/mediatek/mmsys/Makefile|   2 +
> >  drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 
> > +
> >  drivers/soc/mediatek/mtk-mmsys.c   | 380 
> > -
> 
> I wonder why this doesn't get detected as a rename?

the rename message displayed when git commit -s
git show will not show the rename information

> 
> >  4 files changed, 383 insertions(+), 381 deletions(-)
> >  create mode 100644 drivers/soc/mediatek/mmsys/Makefile
> >  create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
> >  delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c
> >
> > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> > index 01f9f87..b5987ca 100644
> > --- a/drivers/soc/mediatek/Makefile
> > +++ b/drivers/soc/mediatek/Makefile
> > @@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
> >  obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
> >  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
> >  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> > -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> > +obj-$(CONFIG_MTK_MMSYS) += mmsys/
> > diff --git a/drivers/soc/mediatek/mmsys/Makefile 
> > b/drivers/soc/mediatek/mmsys/Makefile
> > new file mode 100644
> > index 000..5d976d7
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mmsys/Makefile
> > @@ -0,0 +1,2 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> > \ No newline at end of file
> 
> Nit: newline at end of file please.

it will be fixed in next version

Re: [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register

2020-12-28 Thread Yongqiang Niu

On Tue, 2020-12-29 at 00:38 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
> 
> Yongqiang Niu  於 2020年12月28日 週一 下午4:38寫道：
> >
> > Use function call for setting mmsys ovl mout register
> >
> > Signed-off-by: Yongqiang Niu 
> > ---
> >  drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 
> >  include/linux/soc/mediatek/mtk-mmsys.h |  3 +++
> >  2 files changed, 23 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c 
> > b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > index dae665b..ea36a11 100644
> > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev,
> > reg = readl_relaxed(mmsys->regs + addr) | value;
> > writel_relaxed(reg, mmsys->regs + addr);
> > }
> > +
> > +   if (!funcs->ovl_mout_en)
> > +   return;
> > +
> > +   if (funcs->ovl_mout_en) {
> > +   value = funcs->ovl_mout_en(cur, next, );
> > +   if (value) {
> > +   reg = readl_relaxed(mmsys->regs + addr) | value;
> > +   writel_relaxed(reg, mmsys->regs + addr);
> > +   }
> > +   }
> 
> mtk_mmsys_ddp_mout_en() could write register inside it rather than
> return value and write register in mtk_mmsys_ddp_connect(). So you
> could do ovl_mout_en() in mtk_mmsys_ddp_mout_en().
> 
> Regards,
> Chun-Kuang.

i will add this modification in next version
> 
> >  }
> >  EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
> >
> > @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> > reg = readl_relaxed(mmsys->regs + addr) & ~value;
> > writel_relaxed(reg, mmsys->regs + addr);
> > }
> > +
> > +   if (!funcs->ovl_mout_en)
> > +   return;
> > +
> > +   value = funcs->ovl_mout_en(cur, next, );
> > +   if (value) {
> > +   reg = readl_relaxed(mmsys->regs + addr) & ~value;
> > +   writel_relaxed(reg, mmsys->regs + addr);
> > +   }
> >  }
> >  EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> >
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h 
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index aa4f60e..220203d 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs {
> > u32 (*mout_en)(enum mtk_ddp_comp_id cur,
> >enum mtk_ddp_comp_id next,
> >unsigned int *addr);
> > +   u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur,
> > +  enum mtk_ddp_comp_id next,
> > +  unsigned int *addr);
> > u32 (*sel_in)(enum mtk_ddp_comp_id cur,
> >   enum mtk_ddp_comp_id next,
> >   unsigned int *addr);
> > --
> > 1.8.1.1.dirty
> > ___
> > Linux-mediatek mailing list
> > linux-media...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register

2020-12-28 Thread Yongqiang Niu

On Tue, 2020-12-29 at 00:38 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
> 
> Yongqiang Niu  於 2020年12月28日 週一 下午4:38寫道：
> >
> > Use function call for setting mmsys ovl mout register
> >
> > Signed-off-by: Yongqiang Niu 
> > ---
> >  drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 
> >  include/linux/soc/mediatek/mtk-mmsys.h |  3 +++
> >  2 files changed, 23 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c 
> > b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > index dae665b..ea36a11 100644
> > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > @@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev,
> > reg = readl_relaxed(mmsys->regs + addr) | value;
> > writel_relaxed(reg, mmsys->regs + addr);
> > }
> > +
> > +   if (!funcs->ovl_mout_en)
> > +   return;
> > +
> > +   if (funcs->ovl_mout_en) {
> > +   value = funcs->ovl_mout_en(cur, next, );
> > +   if (value) {
> > +   reg = readl_relaxed(mmsys->regs + addr) | value;
> > +   writel_relaxed(reg, mmsys->regs + addr);
> > +   }
> > +   }
> 
> mtk_mmsys_ddp_mout_en() could write register inside it rather than
> return value and write register in mtk_mmsys_ddp_connect(). So you
> could do ovl_mout_en() in mtk_mmsys_ddp_mout_en().
> 
> Regards,
> Chun-Kuang.

if that, there will be many repeat code like this:

if (value) {
reg = readl_relaxed(mmsys->regs + addr) | value;
writel_relaxed(reg, mmsys->regs + addr);
 }


> 
> >  }
> >  EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
> >
> > @@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> > reg = readl_relaxed(mmsys->regs + addr) & ~value;
> > writel_relaxed(reg, mmsys->regs + addr);
> > }
> > +
> > +   if (!funcs->ovl_mout_en)
> > +   return;
> > +
> > +   value = funcs->ovl_mout_en(cur, next, );
> > +   if (value) {
> > +   reg = readl_relaxed(mmsys->regs + addr) & ~value;
> > +   writel_relaxed(reg, mmsys->regs + addr);
> > +   }
> >  }
> >  EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> >
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h 
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index aa4f60e..220203d 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs {
> > u32 (*mout_en)(enum mtk_ddp_comp_id cur,
> >enum mtk_ddp_comp_id next,
> >unsigned int *addr);
> > +   u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur,
> > +  enum mtk_ddp_comp_id next,
> > +  unsigned int *addr);
> > u32 (*sel_in)(enum mtk_ddp_comp_id cur,
> >   enum mtk_ddp_comp_id next,
> >   unsigned int *addr);
> > --
> > 1.8.1.1.dirty
> > ___
> > Linux-mediatek mailing list
> > linux-media...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH v3, 8/8] soc: mediatek: mmsys: add mt8192 mmsys support

2020-12-28 Thread Yongqiang Niu

add mt8192 mmsys support

Signed-off-by: Yongqiang Niu 
---
 drivers/soc/mediatek/mmsys/Makefile   |   1 +
 drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 119 ++
 drivers/soc/mediatek/mmsys/mtk-mmsys.c|   9 +++
 include/linux/soc/mediatek/mtk-mmsys.h|   1 +
 4 files changed, 130 insertions(+)
 create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c

diff --git a/drivers/soc/mediatek/mmsys/Makefile 
b/drivers/soc/mediatek/mmsys/Makefile
index 25eeb9e5..7508cd3 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
 obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o
 obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c 
b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
new file mode 100644
index 000..a5145ff
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MMSYS_OVL_MOUT_EN  0xf04
+#define DISP_OVL0_GO_BLEND BIT(0)
+#define DISP_OVL0_GO_BGBIT(1)
+#define DISP_OVL0_2L_GO_BLEND  BIT(2)
+#define DISP_OVL0_2L_GO_BG BIT(3)
+#define DISP_OVL1_2L_MOUT_EN   0xf08
+#define OVL1_2L_MOUT_EN_RDMA1  BIT(4)
+#define DISP_OVL0_2L_MOUT_EN   0xf18
+#define DISP_OVL0_MOUT_EN  0xf1c
+#define OVL0_MOUT_EN_DISP_RDMA0BIT(0)
+#define OVL0_MOUT_EN_OVL0_2L   BIT(4)
+#define DISP_RDMA0_SEL_IN  0xf2c
+#define RDMA0_SEL_IN_OVL0_2L   0x3
+#define DISP_RDMA0_SOUT_SEL0xf30
+#define RDMA0_SOUT_COLOR0  0x1
+#define DISP_CCORR0_SOUT_SEL   0xf34
+#define CCORR0_SOUT_AAL0   0x1
+#define DISP_AAL0_SEL_IN   0xf38
+#define AAL0_SEL_IN_CCORR0 0x1
+#define DISP_DITHER0_MOUT_EN   0xf3c
+#define DITHER0_MOUT_DSI0  BIT(0)
+#define DISP_DSI0_SEL_IN   0xf40
+#define DSI0_SEL_IN_DITHER00x1
+#define DISP_OVL2_2L_MOUT_EN   0xf4c
+#define OVL2_2L_MOUT_RDMA4 BIT(0)
+
+static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ unsigned int *addr)
+{
+   unsigned int value;
+
+   if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+   *addr = DISP_OVL0_2L_MOUT_EN;
+   value = OVL0_MOUT_EN_DISP_RDMA0;
+   } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) 
{
+   *addr = DISP_OVL2_2L_MOUT_EN;
+   value = OVL2_2L_MOUT_RDMA4;
+   } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+   *addr = DISP_DITHER0_MOUT_EN;
+   value = DITHER0_MOUT_DSI0;
+   } else {
+   value = 0;
+   }
+
+   return value;
+}
+
+static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
+enum mtk_ddp_comp_id next,
+unsigned int *addr)
+{
+   unsigned int value;
+
+   if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+   *addr = DISP_RDMA0_SEL_IN;
+   value = RDMA0_SEL_IN_OVL0_2L;
+   } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
+   *addr = DISP_AAL0_SEL_IN;
+   value = AAL0_SEL_IN_CCORR0;
+   } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+   *addr = DISP_DSI0_SEL_IN;
+   value = DSI0_SEL_IN_DITHER0;
+   } else {
+   value = 0;
+   }
+
+   return value;
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+  enum mtk_ddp_comp_id cur,
+  enum mtk_ddp_comp_id next)
+{
+   if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
+   writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + 
DISP_RDMA0_SOUT_SEL);
+   } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
+   writel_relaxed(CCORR0_SOUT_AAL0, config_regs + 
DISP_CCORR0_SOUT_SEL);
+   }
+}
+
+static unsigned int mtk_mmsys_ovl_mout_en(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ unsigned int *addr)
+{
+   unsigned int value;
+
+   *addr = MMSYS_OVL_MOUT_EN;
+
+   if (cur == DDP_COMPON

[PATCH v3, 6/8] soc: mediatek: mmsys: add component RDMA4

2020-12-28 Thread Yongqiang Niu

This patch add component RDMA4

Signed-off-by: Yongqiang Niu 
---
 include/linux/soc/mediatek/mtk-mmsys.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/soc/mediatek/mtk-mmsys.h 
b/include/linux/soc/mediatek/mtk-mmsys.h
index 09ee424..aa4f60e 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -38,6 +38,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_RDMA1,
DDP_COMPONENT_RDMA2,
+   DDP_COMPONENT_RDMA4,
DDP_COMPONENT_UFOE,
DDP_COMPONENT_WDMA0,
DDP_COMPONENT_WDMA1,
-- 
1.8.1.1.dirty

[PATCH v3, 2/8] soc: mediatek: mmsys: Use function call for setting the routing registers

2020-12-28 Thread Yongqiang Niu

Actually, setting the registers for routing, use multiple 'if-else' for 
different
routes, but this code would be more and more complicated while we
support more and more SoCs. Change that and use a function call per SoC so the
code will be more portable and clear.

Signed-off-by: Yongqiang Niu 
---
 drivers/soc/mediatek/mmsys/Makefile   |   3 +-
 drivers/soc/mediatek/mmsys/mt2701-mmsys.c | 233 +
 drivers/soc/mediatek/mmsys/mtk-mmsys.c| 241 +++---
 include/linux/soc/mediatek/mtk-mmsys.h|  14 ++
 4 files changed, 268 insertions(+), 223 deletions(-)
 create mode 100644 drivers/soc/mediatek/mmsys/mt2701-mmsys.c

diff --git a/drivers/soc/mediatek/mmsys/Makefile 
b/drivers/soc/mediatek/mmsys/Makefile
index 5d976d7..ac03025 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,2 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
\ No newline at end of file
+obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt2701-mmsys.c 
b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
new file mode 100644
index 000..40576d3
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt2701-mmsys.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN  0x040
+#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN  0x044
+#define DISP_REG_CONFIG_DISP_OD_MOUT_EN0x048
+#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
+#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN  0x050
+#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
+#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
+#define DISP_REG_CONFIG_DSIE_SEL_IN0x0a4
+#define DISP_REG_CONFIG_DSIO_SEL_IN0x0a8
+#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
+#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8
+#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
+#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
+#define DISP_REG_CONFIG_MMSYS_CG_CON0  0x100
+
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN   0x030
+#define DISP_REG_CONFIG_OUT_SEL0x04c
+#define DISP_REG_CONFIG_DSI_SEL0x050
+#define DISP_REG_CONFIG_DPI_SEL0x064
+
+#define OVL0_MOUT_EN_COLOR00x1
+#define OD_MOUT_EN_RDMA0   0x1
+#define OD1_MOUT_EN_RDMA1  BIT(16)
+#define UFOE_MOUT_EN_DSI0  0x1
+#define COLOR0_SEL_IN_OVL0 0x1
+#define OVL1_MOUT_EN_COLOR10x1
+#define GAMMA_MOUT_EN_RDMA10x1
+#define RDMA0_SOUT_DPI00x2
+#define RDMA0_SOUT_DPI10x3
+#define RDMA0_SOUT_DSI10x1
+#define RDMA0_SOUT_DSI20x4
+#define RDMA0_SOUT_DSI30x5
+#define RDMA1_SOUT_DPI00x2
+#define RDMA1_SOUT_DPI10x3
+#define RDMA1_SOUT_DSI10x1
+#define RDMA1_SOUT_DSI20x4
+#define RDMA1_SOUT_DSI30x5
+#define RDMA2_SOUT_DPI00x2
+#define RDMA2_SOUT_DPI10x3
+#define RDMA2_SOUT_DSI10x1
+#define RDMA2_SOUT_DSI20x4
+#define RDMA2_SOUT_DSI30x5
+#define DPI0_SEL_IN_RDMA1  0x1
+#define DPI0_SEL_IN_RDMA2  0x3
+#define DPI1_SEL_IN_RDMA1  (0x1 << 8)
+#define DPI1_SEL_IN_RDMA2  (0x3 << 8)
+#define DSI0_SEL_IN_RDMA1  0x1
+#define DSI0_SEL_IN_RDMA2  0x4
+#define DSI1_SEL_IN_RDMA1  0x1
+#define DSI1_SEL_IN_RDMA2  0x4
+#define DSI2_SEL_IN_RDMA1  (0x1 << 16)
+#define DSI2_SEL_IN_RDMA2  (0x4 << 16)
+#define DSI3_SEL_IN_RDMA1  (0x1 << 16)
+#define DSI3_SEL_IN_RDMA2  (0x4 << 16)
+#define COLOR1_SEL_IN_OVL1 0x1
+
+#define OVL_MOUT_EN_RDMA   0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1   0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI0x2
+#define DSI_SEL_IN_BLS 0x0
+#define DPI_SEL_IN_BLS 0x0
+#define DSI_SEL_IN_RDMA0x1
+
+static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+

[PATCH v3, 7/8] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register

2020-12-28 Thread Yongqiang Niu

Use function call for setting mmsys ovl mout register

Signed-off-by: Yongqiang Niu 
---
 drivers/soc/mediatek/mmsys/mtk-mmsys.c | 20 
 include/linux/soc/mediatek/mtk-mmsys.h |  3 +++
 2 files changed, 23 insertions(+)

diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c 
b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index dae665b..ea36a11 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -74,6 +74,17 @@ void mtk_mmsys_ddp_connect(struct device *dev,
reg = readl_relaxed(mmsys->regs + addr) | value;
writel_relaxed(reg, mmsys->regs + addr);
}
+
+   if (!funcs->ovl_mout_en)
+   return;
+
+   if (funcs->ovl_mout_en) {
+   value = funcs->ovl_mout_en(cur, next, );
+   if (value) {
+   reg = readl_relaxed(mmsys->regs + addr) | value;
+   writel_relaxed(reg, mmsys->regs + addr);
+   }
+   }
 }
 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
 
@@ -99,6 +110,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
reg = readl_relaxed(mmsys->regs + addr) & ~value;
writel_relaxed(reg, mmsys->regs + addr);
}
+
+   if (!funcs->ovl_mout_en)
+   return;
+
+   value = funcs->ovl_mout_en(cur, next, );
+   if (value) {
+   reg = readl_relaxed(mmsys->regs + addr) & ~value;
+   writel_relaxed(reg, mmsys->regs + addr);
+   }
 }
 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
 
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h 
b/include/linux/soc/mediatek/mtk-mmsys.h
index aa4f60e..220203d 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs {
u32 (*mout_en)(enum mtk_ddp_comp_id cur,
   enum mtk_ddp_comp_id next,
   unsigned int *addr);
+   u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur,
+  enum mtk_ddp_comp_id next,
+  unsigned int *addr);
u32 (*sel_in)(enum mtk_ddp_comp_id cur,
  enum mtk_ddp_comp_id next,
  unsigned int *addr);
-- 
1.8.1.1.dirty

[PATCH v3, 3/8] soc: mediatek: mmsys: add mt8183 function call for setting the routing registers

2020-12-28 Thread Yongqiang Niu

add mt8183 function call for setting the routing registers

Signed-off-by: Yongqiang Niu 
---
 drivers/soc/mediatek/mmsys/Makefile   |  1 +
 drivers/soc/mediatek/mmsys/mt8183-mmsys.c | 90 +++
 drivers/soc/mediatek/mmsys/mtk-mmsys.c|  1 +
 include/linux/soc/mediatek/mtk-mmsys.h|  1 +
 4 files changed, 93 insertions(+)
 create mode 100644 drivers/soc/mediatek/mmsys/mt8183-mmsys.c

diff --git a/drivers/soc/mediatek/mmsys/Makefile 
b/drivers/soc/mediatek/mmsys/Makefile
index ac03025..25eeb9e5 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
 obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt8183-mmsys.c 
b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c
new file mode 100644
index 000..192b4ab
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt8183-mmsys.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DISP_OVL0_MOUT_EN  0xf00
+#define DISP_OVL0_2L_MOUT_EN   0xf04
+#define DISP_OVL1_2L_MOUT_EN   0xf08
+#define DISP_DITHER0_MOUT_EN   0xf0c
+#define DISP_PATH0_SEL_IN  0xf24
+#define DISP_DSI0_SEL_IN   0xf2c
+#define DISP_DPI0_SEL_IN   0xf30
+#define DISP_RDMA0_SOUT_SEL_IN 0xf50
+#define DISP_RDMA1_SOUT_SEL_IN 0xf54
+
+#define OVL0_MOUT_EN_OVL0_2L   BIT(4)
+#define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
+#define OVL1_2L_MOUT_EN_RDMA1  BIT(4)
+#define DITHER0_MOUT_IN_DSI0   BIT(0)
+#define DISP_PATH0_SEL_IN_OVL0_2L  0x1
+#define DSI0_SEL_IN_RDMA0  0x1
+#define DSI0_SEL_IN_RDMA1  0x3
+#define DPI0_SEL_IN_RDMA0  0x1
+#define DPI0_SEL_IN_RDMA1  0x2
+#define RDMA0_SOUT_COLOR0  0x1
+#define RDMA1_SOUT_DSI00x1
+
+static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
+ enum mtk_ddp_comp_id next,
+ unsigned int *addr)
+{
+   unsigned int value;
+
+   if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0) {
+   *addr = DISP_OVL0_MOUT_EN;
+   value = OVL0_MOUT_EN_OVL0_2L;
+   } else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) 
{
+   *addr = DISP_OVL0_2L_MOUT_EN;
+   value = OVL0_2L_MOUT_EN_DISP_PATH0;
+   } else if (cur == DDP_COMPONENT_OVL_2L1 && next == DDP_COMPONENT_RDMA1) 
{
+   *addr = DISP_OVL1_2L_MOUT_EN;
+   value = OVL1_2L_MOUT_EN_RDMA1;
+   } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+   *addr = DISP_DITHER0_MOUT_EN;
+   value = DITHER0_MOUT_IN_DSI0;
+   } else {
+   value = 0;
+   }
+
+   return value;
+}
+
+static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
+enum mtk_ddp_comp_id next,
+unsigned int *addr)
+{
+   unsigned int value;
+
+   if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+   *addr = DISP_PATH0_SEL_IN;
+   value = DISP_PATH0_SEL_IN_OVL0_2L;
+   } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+   *addr = DISP_DPI0_SEL_IN;
+   value = DPI0_SEL_IN_RDMA1;
+   } else {
+   value = 0;
+   }
+
+   return value;
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+  enum mtk_ddp_comp_id cur,
+  enum mtk_ddp_comp_id next)
+{
+   if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
+   writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + 
DISP_RDMA0_SOUT_SEL_IN);
+   }
+}
+
+struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs = {
+   .mout_en = mtk_mmsys_ddp_mout_en,
+   .sel_in = mtk_mmsys_ddp_sel_in,
+   .sout_sel = mtk_mmsys_ddp_sout_sel,
+};
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c 
b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index c35bda1..dae665b 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -42,6 +42,7 @@ struct mtk_mmsys_driver_data {
 
 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
+   .funcs = _mmsys_funcs,
 };
 
 struct mtk_mmsys {
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h 
b/include/linux/soc/mediatek/mtk-mmsys.h
index 17e8b91..4b6c514

[PATCH v3, 1/8] soc: mediatek: mmsys: create mmsys folder

2020-12-28 Thread Yongqiang Niu

the mmsys will more and more complicated after support
more and more SoCs, add an independent folder will be
more clear

Signed-off-by: Yongqiang Niu 
---
 drivers/soc/mediatek/Makefile  |   2 +-
 drivers/soc/mediatek/mmsys/Makefile|   2 +
 drivers/soc/mediatek/mmsys/mtk-mmsys.c | 380 +
 drivers/soc/mediatek/mtk-mmsys.c   | 380 -
 4 files changed, 383 insertions(+), 381 deletions(-)
 create mode 100644 drivers/soc/mediatek/mmsys/Makefile
 create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c
 delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c

diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index 01f9f87..b5987ca 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -3,4 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
 obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
 obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
 obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
-obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mmsys/
diff --git a/drivers/soc/mediatek/mmsys/Makefile 
b/drivers/soc/mediatek/mmsys/Makefile
new file mode 100644
index 000..5d976d7
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
\ No newline at end of file
diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c 
b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
new file mode 100644
index 000..da2de8f
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -0,0 +1,380 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN  0x040
+#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN  0x044
+#define DISP_REG_CONFIG_DISP_OD_MOUT_EN0x048
+#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
+#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN  0x050
+#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
+#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
+#define DISP_REG_CONFIG_DSIE_SEL_IN0x0a4
+#define DISP_REG_CONFIG_DSIO_SEL_IN0x0a8
+#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
+#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8
+#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4
+#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
+#define DISP_REG_CONFIG_MMSYS_CG_CON0  0x100
+
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN   0x030
+#define DISP_REG_CONFIG_OUT_SEL0x04c
+#define DISP_REG_CONFIG_DSI_SEL0x050
+#define DISP_REG_CONFIG_DPI_SEL0x064
+
+#define OVL0_MOUT_EN_COLOR00x1
+#define OD_MOUT_EN_RDMA0   0x1
+#define OD1_MOUT_EN_RDMA1  BIT(16)
+#define UFOE_MOUT_EN_DSI0  0x1
+#define COLOR0_SEL_IN_OVL0 0x1
+#define OVL1_MOUT_EN_COLOR10x1
+#define GAMMA_MOUT_EN_RDMA10x1
+#define RDMA0_SOUT_DPI00x2
+#define RDMA0_SOUT_DPI10x3
+#define RDMA0_SOUT_DSI10x1
+#define RDMA0_SOUT_DSI20x4
+#define RDMA0_SOUT_DSI30x5
+#define RDMA1_SOUT_DPI00x2
+#define RDMA1_SOUT_DPI10x3
+#define RDMA1_SOUT_DSI10x1
+#define RDMA1_SOUT_DSI20x4
+#define RDMA1_SOUT_DSI30x5
+#define RDMA2_SOUT_DPI00x2
+#define RDMA2_SOUT_DPI10x3
+#define RDMA2_SOUT_DSI10x1
+#define RDMA2_SOUT_DSI20x4
+#define RDMA2_SOUT_DSI30x5
+#define DPI0_SEL_IN_RDMA1  0x1
+#define DPI0_SEL_IN_RDMA2  0x3
+#define DPI1_SEL_IN_RDMA1  (0x1 << 8)
+#define DPI1_SEL_IN_RDMA2  (0x3 << 8)
+#define DSI0_SEL_IN_RDMA1  0x1
+#define DSI0_SEL_IN_RDMA2  0x4
+#define DSI1_SEL_IN_RDMA1  0x1
+#define DSI1_SEL_IN_RDMA2  0x4
+#define DSI2_SEL_IN_RDMA1  (0x1 << 16)
+#define DSI2_SEL_IN_RDMA2  (0x4 << 16)
+#define DSI3_SEL_IN_RDMA1  (0x1 << 16)
+#define DSI3_SEL_IN_RDMA2  (0x4 << 16)
+#define COLOR1_SEL_IN_OVL1 0x1
+
+#define OVL_MOUT_EN_RDMA   0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1   0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI

[PATCH v3, 5/8] soc: mediatek: mmsys: add component POSTMASK

2020-12-28 Thread Yongqiang Niu

This patch add component POSTMASK

Signed-off-by: Yongqiang Niu 
---
 include/linux/soc/mediatek/mtk-mmsys.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/soc/mediatek/mtk-mmsys.h 
b/include/linux/soc/mediatek/mtk-mmsys.h
index 42476c2..09ee424 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -31,6 +31,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL_2L1,
DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
+   DDP_COMPONENT_POSTMASK0,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
DDP_COMPONENT_PWM2,
-- 
1.8.1.1.dirty

[PATCH v3, 4/8] soc: mediatek: mmsys: add component OVL_2L2

2020-12-28 Thread Yongqiang Niu

This patch add component OVL_2L2

Signed-off-by: Yongqiang Niu 
---
 include/linux/soc/mediatek/mtk-mmsys.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/soc/mediatek/mtk-mmsys.h 
b/include/linux/soc/mediatek/mtk-mmsys.h
index 4b6c514..42476c2 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -29,6 +29,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
+   DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
-- 
1.8.1.1.dirty

soc: mediatek: Prepare MMSYS for DDP routing using function call

2020-12-28 Thread Yongqiang Niu

The following series are intended to prepare the mtk-mmsys driver to
allow different DDP (Data Display Path) function call per SoC.

base change:
https://patchwork.kernel.org/project/linux-mediatek/patch/20201006193320.405529-4-enric.balle...@collabora.com/

Change since v2:
- fix review issue in v2
- add 8183 mmsys function call
- add 8192 new component
- add 8192 mmsys function call

Re: [PATCH v2, 3/3] mailbox: cmdq: add mt8192 support

2020-12-24 Thread Yongqiang Niu

On Thu, 2020-12-24 at 22:28 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
> 
> Yongqiang Niu  於 2020年12月24日 週四 上午8:55寫道：
> >
> > add mt8192 support
> >
> > Signed-off-by: Yongqiang Niu 
> > ---
> >  drivers/mailbox/mtk-cmdq-mailbox.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c 
> > b/drivers/mailbox/mtk-cmdq-mailbox.c
> > index 75378e3..7f243e1 100644
> > --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> > @@ -607,6 +607,7 @@ static int cmdq_probe(struct platform_device *pdev)
> > {.compatible = "mediatek,mt8173-gce", .data = (void *)_plat_v2},
> > {.compatible = "mediatek,mt8183-gce", .data = (void *)_plat_v3},
> > {.compatible = "mediatek,mt6779-gce", .data = (void *)_plat_v4},
> > +   {.compatible = "mediatek,mt8192-gce", .data = (void *)_plat_v4},
> 
> In the view of hardware function, is mt8192-gce identical to
> mt6779-gce? If these two are identical, you need not to modify driver,
> and the compatible should be
> 
> compatible = "mediatek,mt8192-gce", "mediatek,mt6779-gce";
> 
> If they are not identical, what's the different?
> 
> Regards,
> Chun-Kuang.

irq id is different 
mt8192 dts
https://patchwork.kernel.org/project/linux-mediatek/patch/1608770889-9403-3-git-send-email-yongqiang@mediatek.com/

mt6779 dts
https://patchwork.kernel.org/project/linux-mediatek/patch/1574327552-11806-6-git-send-email-dennis-yc.hs...@mediatek.com/

and gce event id also different
https://patchwork.kernel.org/project/linux-mediatek/patch/1608770889-9403-2-git-send-email-yongqiang@mediatek.com/

https://patchwork.kernel.org/project/linux-mediatek/patch/1574327552-11806-2-git-send-email-dennis-yc.hs...@mediatek.com/


> 
> > {}
> >  };
> >
> > --
> > 1.8.1.1.dirty
> > ___
> > Linux-mediatek mailing list
> > linux-media...@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

1 2 >

1 - 100 of 198 matches

Mail list logo