subject:"\[PATCH 2\/2\] phy\: qcom\-qmp\: new qmp phy driver for qcom\-chipsets"

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-11-22 Thread Kishon Vijay Abraham I

Hi,

On Tuesday 22 November 2016 01:17 PM, Vivek Gautam wrote:
> Hi Kishon,
> 
> 
> On Thu, Nov 10, 2016 at 2:33 PM, Vivek Gautam
>  wrote:
>> Hi Kishon,
>>
> 
 +unsigned int msm8996_pciephy_tx_offsets[] = { 0x1000, 0x2000, 0x3000 };
 +unsigned int msm8996_pciephy_rx_offsets[] = { 0x1200, 0x2200, 0x3200 };
 +unsigned int msm8996_pciephy_pcs_offsets[] = { 0x1400, 0x2400, 0x3400 };
> 
>>> you can have a separate reg map for each lane and all these can come from 
>>> dt.
>>
>> The idea is to avoid the any child nodes for lanes. So, we have the complete
>> ioremaped region and these offsets to tx, rx and pcs blocks.
> 
> I don't see benefits in using regmap for different lanes.
> Do you see benefits in replacing a bunch of readl()/writel() with
> regmap_read()/regmap_update_bits()/regmap_write() ?

By reg map, I meant register spaces allocated for different lanes.
> 
> I can as well use separate 'reg' values for each lanes, and have the offsets
> come from dt. Something like below :
> 
>  - reg: array of offset and length of the PHY register sets.
>at index 0: offset and length of register set for PHY common
>serdes block.
>from index 1 - N: offset and length of register set for each lane,
>  for N number of phy lanes (ports).
>  - lane-offsets: array of offsets to tx, rx and pcs blocks for phy lanes.
> 
> Example:
>pcie_phy: pciephy@34000 {
>compatible = "qcom,msm8996-qmp-pcie-phy";
>reg = <0x034000 0x48f>,
><0x035000 5bf>,
><0x036000 5bf>,
><0x037000 5bf>;
>/* tx, rx, pcs */
>lane-offsets = <0x0 0x200 0x400>;

right, I meant something like this.

Thanks
Kishon

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-11-22 Thread Kishon Vijay Abraham I

Hi,

On Tuesday 22 November 2016 01:17 PM, Vivek Gautam wrote:
> Hi Kishon,
> 
> 
> On Thu, Nov 10, 2016 at 2:33 PM, Vivek Gautam
>  wrote:
>> Hi Kishon,
>>
> 
 +unsigned int msm8996_pciephy_tx_offsets[] = { 0x1000, 0x2000, 0x3000 };
 +unsigned int msm8996_pciephy_rx_offsets[] = { 0x1200, 0x2200, 0x3200 };
 +unsigned int msm8996_pciephy_pcs_offsets[] = { 0x1400, 0x2400, 0x3400 };
> 
>>> you can have a separate reg map for each lane and all these can come from 
>>> dt.
>>
>> The idea is to avoid the any child nodes for lanes. So, we have the complete
>> ioremaped region and these offsets to tx, rx and pcs blocks.
> 
> I don't see benefits in using regmap for different lanes.
> Do you see benefits in replacing a bunch of readl()/writel() with
> regmap_read()/regmap_update_bits()/regmap_write() ?

By reg map, I meant register spaces allocated for different lanes.
> 
> I can as well use separate 'reg' values for each lanes, and have the offsets
> come from dt. Something like below :
> 
>  - reg: array of offset and length of the PHY register sets.
>at index 0: offset and length of register set for PHY common
>serdes block.
>from index 1 - N: offset and length of register set for each lane,
>  for N number of phy lanes (ports).
>  - lane-offsets: array of offsets to tx, rx and pcs blocks for phy lanes.
> 
> Example:
>pcie_phy: pciephy@34000 {
>compatible = "qcom,msm8996-qmp-pcie-phy";
>reg = <0x034000 0x48f>,
><0x035000 5bf>,
><0x036000 5bf>,
><0x037000 5bf>;
>/* tx, rx, pcs */
>lane-offsets = <0x0 0x200 0x400>;

right, I meant something like this.

Thanks
Kishon

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-11-21 Thread Vivek Gautam

Hi Kishon,


On Thu, Nov 10, 2016 at 2:33 PM, Vivek Gautam
 wrote:
> Hi Kishon,
>

>>> +unsigned int msm8996_pciephy_tx_offsets[] = { 0x1000, 0x2000, 0x3000 };
>>> +unsigned int msm8996_pciephy_rx_offsets[] = { 0x1200, 0x2200, 0x3200 };
>>> +unsigned int msm8996_pciephy_pcs_offsets[] = { 0x1400, 0x2400, 0x3400 };

>> you can have a separate reg map for each lane and all these can come from dt.
>
> The idea is to avoid the any child nodes for lanes. So, we have the complete
> ioremaped region and these offsets to tx, rx and pcs blocks.

I don't see benefits in using regmap for different lanes.
Do you see benefits in replacing a bunch of readl()/writel() with
regmap_read()/regmap_update_bits()/regmap_write() ?

I can as well use separate 'reg' values for each lanes, and have the offsets
come from dt. Something like below :

 - reg: array of offset and length of the PHY register sets.
   at index 0: offset and length of register set for PHY common
   serdes block.
   from index 1 - N: offset and length of register set for each lane,
 for N number of phy lanes (ports).
 - lane-offsets: array of offsets to tx, rx and pcs blocks for phy lanes.

Example:
   pcie_phy: pciephy@34000 {
   compatible = "qcom,msm8996-qmp-pcie-phy";
   reg = <0x034000 0x48f>,
   <0x035000 5bf>,
   <0x036000 5bf>,
   <0x037000 5bf>;
   /* tx, rx, pcs */
   lane-offsets = <0x0 0x200 0x400>;


Does this look OK ? Or should i use regmap only ?


Thanks
Vivek
-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-11-21 Thread Vivek Gautam

Hi Kishon,


On Thu, Nov 10, 2016 at 2:33 PM, Vivek Gautam
 wrote:
> Hi Kishon,
>

>>> +unsigned int msm8996_pciephy_tx_offsets[] = { 0x1000, 0x2000, 0x3000 };
>>> +unsigned int msm8996_pciephy_rx_offsets[] = { 0x1200, 0x2200, 0x3200 };
>>> +unsigned int msm8996_pciephy_pcs_offsets[] = { 0x1400, 0x2400, 0x3400 };

>> you can have a separate reg map for each lane and all these can come from dt.
>
> The idea is to avoid the any child nodes for lanes. So, we have the complete
> ioremaped region and these offsets to tx, rx and pcs blocks.

I don't see benefits in using regmap for different lanes.
Do you see benefits in replacing a bunch of readl()/writel() with
regmap_read()/regmap_update_bits()/regmap_write() ?

I can as well use separate 'reg' values for each lanes, and have the offsets
come from dt. Something like below :

 - reg: array of offset and length of the PHY register sets.
   at index 0: offset and length of register set for PHY common
   serdes block.
   from index 1 - N: offset and length of register set for each lane,
 for N number of phy lanes (ports).
 - lane-offsets: array of offsets to tx, rx and pcs blocks for phy lanes.

Example:
   pcie_phy: pciephy@34000 {
   compatible = "qcom,msm8996-qmp-pcie-phy";
   reg = <0x034000 0x48f>,
   <0x035000 5bf>,
   <0x036000 5bf>,
   <0x037000 5bf>;
   /* tx, rx, pcs */
   lane-offsets = <0x0 0x200 0x400>;


Does this look OK ? Or should i use regmap only ?


Thanks
Vivek
-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-11-10 Thread Vivek Gautam

Hi Kishon,


On Thu, Oct 27, 2016 at 1:41 AM, Kishon Vijay Abraham I  wrote:
> Hi,
>
> On Wednesday 19 October 2016 04:13 PM, Vivek Gautam wrote:
>> Qualcomm SOCs have QMP phy controller that provides support
>> to a number of controller, viz. PCIe, UFS, and USB.
>> Add a new driver, based on generic phy framework, for this
>> phy controller.
>>
>> USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
>> msm-4.4 kernel @codeaurora[1].
>> PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
>> Srinivas [2].
>>
>> [1] 
>> https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
>> [2] https://patchwork.kernel.org/patch/9318947/
>
> use only lkml links here.

Ok.

>>
>> Signed-off-by: Vivek Gautam 
>> Cc: Kishon Vijay Abraham I 
>> ---
>>  .../devicetree/bindings/phy/qcom-qmp-phy.txt   |   61 ++
>>  drivers/phy/Kconfig|8 +
>>  drivers/phy/Makefile   |1 +
>>  drivers/phy/phy-qcom-qmp.c | 1154 
>> 
>>  4 files changed, 1224 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>>  create mode 100644 drivers/phy/phy-qcom-qmp.c
>>
>> diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt 
>> b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>> new file mode 100644
>> index 000..90214aa
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>> @@ -0,0 +1,61 @@
>> +Qualcomm QMP PHY
>> +
>> +
>> +QMP phy controller supports physical layer functionality for a number of
>> +controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
>> +
>> +Required properties:
>> + - compatible: compatible list, contains:
>> +"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
>> +"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
>> + - reg: offset and length of the PHY register set.
>> + - #phy-cells: must be 1
>> +- Cell after phy phandle should be the port (lane) number.
>> + - clocks: a list of phandles and clock-specifier pairs,
>> +one for each entry in clock-names.
>> + - clock-names: must be "cfg_ahb" for phy config clock,
>> + "aux" for phy aux clock,
>> + "ref_clk" for 19.2 MHz ref clk,
>> + "ref_clk_src" for reference clock source,
>> + "pipe" for pipe clock specific to
>> + each port/lane (Optional).
>> + - resets: a list of phandles and reset controller specifier pairs,
>> +one for each entry in reset-names.
>> + - reset-names: must be "phy" for reset of phy block,
>> + "common" for phy common block reset,
>> + "cfg" for phy's ahb cfg block reset (Optional).
>> + "port" for reset specific to
>> + each port/lane. (Optional)
>> + - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
>> + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll 
>> block.
>> +
>> +Optional properties:
>> + - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
>> + pll block.
>> +
>> +Example:
>> + pcie_phy: pciephy@34000 {
>> + compatible = "qcom,qmp-14nm-pcie-phy";
>> + reg = <0x034000 0x3fff>;
>> + #phy-cells = <1>;
>> +
>> + clocks = < GCC_PCIE_PHY_AUX_CLK>,
>> + < GCC_PCIE_PHY_CFG_AHB_CLK>,
>> + < GCC_PCIE_0_PIPE_CLK>,
>> + < GCC_PCIE_1_PIPE_CLK>,
>> + < GCC_PCIE_2_PIPE_CLK>;
>> + clock-names = "aux", "cfg_ahb",
>> + "pipe0", "pipe1", "pipe2";
>> +
>> + vdda-phy-supply = <_l28>;
>> + vdda-pll-supply = <_l12>;
>> +
>> + resets = < GCC_PCIE_PHY_BCR>,
>> + < GCC_PCIE_PHY_COM_BCR>,
>> + < GCC_PCIE_PHY_COM_NOCSR_BCR>,
>> + < GCC_PCIE_0_PHY_BCR>,
>> + < GCC_PCIE_1_PHY_BCR>,
>> + < GCC_PCIE_2_PHY_BCR>;
>> + reset-names = "phy", "common", "cfg",
>> + "lane0", "lane1", "lane2";
>> + };
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 5547984..d5e2b50f 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -446,6 +446,14 @@ config PHY_STIH41X_USB
>> Enable this to support the USB transceiver that is part of
>> STMicroelectronics STiH41x SoC series.
>>
>> +config PHY_QCOM_QMP
>> + tristate "Qualcomm QMP PHY Driver"
>> + depends on OF && (ARCH_QCOM || COMPILE_TEST)
>> + select GENERIC_PHY
>> + help
>> +   Enable this to support the QMP PHY transceiver that is used
>> +   with controllers such as PCIe, UFS, and

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-11-10 Thread Vivek Gautam

Hi Kishon,


On Thu, Oct 27, 2016 at 1:41 AM, Kishon Vijay Abraham I  wrote:
> Hi,
>
> On Wednesday 19 October 2016 04:13 PM, Vivek Gautam wrote:
>> Qualcomm SOCs have QMP phy controller that provides support
>> to a number of controller, viz. PCIe, UFS, and USB.
>> Add a new driver, based on generic phy framework, for this
>> phy controller.
>>
>> USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
>> msm-4.4 kernel @codeaurora[1].
>> PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
>> Srinivas [2].
>>
>> [1] 
>> https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
>> [2] https://patchwork.kernel.org/patch/9318947/
>
> use only lkml links here.

Ok.

>>
>> Signed-off-by: Vivek Gautam 
>> Cc: Kishon Vijay Abraham I 
>> ---
>>  .../devicetree/bindings/phy/qcom-qmp-phy.txt   |   61 ++
>>  drivers/phy/Kconfig|8 +
>>  drivers/phy/Makefile   |1 +
>>  drivers/phy/phy-qcom-qmp.c | 1154 
>> 
>>  4 files changed, 1224 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>>  create mode 100644 drivers/phy/phy-qcom-qmp.c
>>
>> diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt 
>> b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>> new file mode 100644
>> index 000..90214aa
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>> @@ -0,0 +1,61 @@
>> +Qualcomm QMP PHY
>> +
>> +
>> +QMP phy controller supports physical layer functionality for a number of
>> +controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
>> +
>> +Required properties:
>> + - compatible: compatible list, contains:
>> +"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
>> +"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
>> + - reg: offset and length of the PHY register set.
>> + - #phy-cells: must be 1
>> +- Cell after phy phandle should be the port (lane) number.
>> + - clocks: a list of phandles and clock-specifier pairs,
>> +one for each entry in clock-names.
>> + - clock-names: must be "cfg_ahb" for phy config clock,
>> + "aux" for phy aux clock,
>> + "ref_clk" for 19.2 MHz ref clk,
>> + "ref_clk_src" for reference clock source,
>> + "pipe" for pipe clock specific to
>> + each port/lane (Optional).
>> + - resets: a list of phandles and reset controller specifier pairs,
>> +one for each entry in reset-names.
>> + - reset-names: must be "phy" for reset of phy block,
>> + "common" for phy common block reset,
>> + "cfg" for phy's ahb cfg block reset (Optional).
>> + "port" for reset specific to
>> + each port/lane. (Optional)
>> + - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
>> + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll 
>> block.
>> +
>> +Optional properties:
>> + - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
>> + pll block.
>> +
>> +Example:
>> + pcie_phy: pciephy@34000 {
>> + compatible = "qcom,qmp-14nm-pcie-phy";
>> + reg = <0x034000 0x3fff>;
>> + #phy-cells = <1>;
>> +
>> + clocks = < GCC_PCIE_PHY_AUX_CLK>,
>> + < GCC_PCIE_PHY_CFG_AHB_CLK>,
>> + < GCC_PCIE_0_PIPE_CLK>,
>> + < GCC_PCIE_1_PIPE_CLK>,
>> + < GCC_PCIE_2_PIPE_CLK>;
>> + clock-names = "aux", "cfg_ahb",
>> + "pipe0", "pipe1", "pipe2";
>> +
>> + vdda-phy-supply = <_l28>;
>> + vdda-pll-supply = <_l12>;
>> +
>> + resets = < GCC_PCIE_PHY_BCR>,
>> + < GCC_PCIE_PHY_COM_BCR>,
>> + < GCC_PCIE_PHY_COM_NOCSR_BCR>,
>> + < GCC_PCIE_0_PHY_BCR>,
>> + < GCC_PCIE_1_PHY_BCR>,
>> + < GCC_PCIE_2_PHY_BCR>;
>> + reset-names = "phy", "common", "cfg",
>> + "lane0", "lane1", "lane2";
>> + };
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 5547984..d5e2b50f 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -446,6 +446,14 @@ config PHY_STIH41X_USB
>> Enable this to support the USB transceiver that is part of
>> STMicroelectronics STiH41x SoC series.
>>
>> +config PHY_QCOM_QMP
>> + tristate "Qualcomm QMP PHY Driver"
>> + depends on OF && (ARCH_QCOM || COMPILE_TEST)
>> + select GENERIC_PHY
>> + help
>> +   Enable this to support the QMP PHY transceiver that is used
>> +   with controllers such as PCIe, UFS, and USB on Qualcomm chips.
>> +
>>  config PHY_QCOM_QUSB2
>>

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-11-02 Thread Srinivas Kandagatla

On 02/11/16 07:26, Vivek Gautam wrote:

+   phy_desc->tx = base + qphy->cfg->tx_offsets[id];
>> +   phy_desc->rx = base + qphy->cfg->rx_offsets[id];
>> +   phy_desc->pcs = base + qphy->cfg->pcs_offsets[id];
>> +
>> +   /*
>> +* Get PHY's Pipe clock, if any; USB3 and PCIe are PIPE
>> +* based phys, so they essentially have pipe clock
>> +*/
>> +   memset(_name, 0, sizeof(prop_name));
>> +   snprintf(prop_name, MAX_PROP_NAME, "pipe%d", id);
>> +   phy_desc->pipe_clk = devm_clk_get(dev, prop_name);
>> +   if (IS_ERR(phy_desc->pipe_clk)) {
>> +   if (qphy->cfg->type == PHY_TYPE_PCIE ||
>> +   qphy->cfg->type == PHY_TYPE_USB3) {
>> +   ret = PTR_ERR(phy_desc->pipe_clk);
>> +   if (ret != -EPROBE_DEFER)
>> +   dev_err(dev,
>> +   "failed to get lane%d pipe_clk\n",
>> id);
>> +   return ret;
>> +   } else {
>> +   phy_desc->pipe_clk = NULL;
>> +   }
>> +   }

>
>
> Do we need to really need phy type for this?
> You should proably make a flag in cfg to mark this rather then using phy
> type. Hopefully it will also simplify the logic.

The pipe clock is something that's specific to PCIe and USB3 type
phys (both are PIPE3 specs based phys). So i think it is okay
to use the PHY_TYPE_{*} macros here. Looks a bit cleaner rather
than having a cfg flag. No ?
Yes, it makes sense, I was not sure of full details of the pipe3 specs, 
now that you made it more clear.

Remember to add this in comments.

Thanks,
srini

Using PHY_TYPE_{*} macros will also keep the doors open to
other PHY types that are added at a later point in time.

>

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-11-02 Thread Srinivas Kandagatla

On 02/11/16 07:26, Vivek Gautam wrote:

+   phy_desc->tx = base + qphy->cfg->tx_offsets[id];
>> +   phy_desc->rx = base + qphy->cfg->rx_offsets[id];
>> +   phy_desc->pcs = base + qphy->cfg->pcs_offsets[id];
>> +
>> +   /*
>> +* Get PHY's Pipe clock, if any; USB3 and PCIe are PIPE
>> +* based phys, so they essentially have pipe clock
>> +*/
>> +   memset(_name, 0, sizeof(prop_name));
>> +   snprintf(prop_name, MAX_PROP_NAME, "pipe%d", id);
>> +   phy_desc->pipe_clk = devm_clk_get(dev, prop_name);
>> +   if (IS_ERR(phy_desc->pipe_clk)) {
>> +   if (qphy->cfg->type == PHY_TYPE_PCIE ||
>> +   qphy->cfg->type == PHY_TYPE_USB3) {
>> +   ret = PTR_ERR(phy_desc->pipe_clk);
>> +   if (ret != -EPROBE_DEFER)
>> +   dev_err(dev,
>> +   "failed to get lane%d pipe_clk\n",
>> id);
>> +   return ret;
>> +   } else {
>> +   phy_desc->pipe_clk = NULL;
>> +   }
>> +   }

>
>
> Do we need to really need phy type for this?
> You should proably make a flag in cfg to mark this rather then using phy
> type. Hopefully it will also simplify the logic.

The pipe clock is something that's specific to PCIe and USB3 type
phys (both are PIPE3 specs based phys). So i think it is okay
to use the PHY_TYPE_{*} macros here. Looks a bit cleaner rather
than having a cfg flag. No ?
Yes, it makes sense, I was not sure of full details of the pipe3 specs, 
now that you made it more clear.

Remember to add this in comments.

Thanks,
srini

Using PHY_TYPE_{*} macros will also keep the doors open to
other PHY types that are added at a later point in time.

>

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-11-02 Thread Vivek Gautam

On Thu, Oct 27, 2016 at 2:48 AM, Rob Herring  wrote:
> On Wed, Oct 19, 2016 at 04:13:47PM +0530, Vivek Gautam wrote:
>> Qualcomm SOCs have QMP phy controller that provides support
>> to a number of controller, viz. PCIe, UFS, and USB.
>> Add a new driver, based on generic phy framework, for this
>> phy controller.
>>
>> USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
>> msm-4.4 kernel @codeaurora[1].
>> PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
>> Srinivas [2].
>>
>> [1] 
>> https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
>> [2] https://patchwork.kernel.org/patch/9318947/
>>
>> Signed-off-by: Vivek Gautam 
>> Cc: Kishon Vijay Abraham I 
>> ---
>>  .../devicetree/bindings/phy/qcom-qmp-phy.txt   |   61 ++
>
> Acked-by: Rob Herring 

Thanks Rob.


Regards
Vivek

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-11-02 Thread Vivek Gautam

On Thu, Oct 27, 2016 at 2:48 AM, Rob Herring  wrote:
> On Wed, Oct 19, 2016 at 04:13:47PM +0530, Vivek Gautam wrote:
>> Qualcomm SOCs have QMP phy controller that provides support
>> to a number of controller, viz. PCIe, UFS, and USB.
>> Add a new driver, based on generic phy framework, for this
>> phy controller.
>>
>> USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
>> msm-4.4 kernel @codeaurora[1].
>> PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
>> Srinivas [2].
>>
>> [1] 
>> https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
>> [2] https://patchwork.kernel.org/patch/9318947/
>>
>> Signed-off-by: Vivek Gautam 
>> Cc: Kishon Vijay Abraham I 
>> ---
>>  .../devicetree/bindings/phy/qcom-qmp-phy.txt   |   61 ++
>
> Acked-by: Rob Herring 

Thanks Rob.


Regards
Vivek

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-11-02 Thread Vivek Gautam

Hi Srini,


On Wed, Oct 26, 2016 at 7:27 PM, Srinivas Kandagatla
 wrote:
> Hi Vivek,
>
> Thanks for consolidating qmp phy support for both usb and pcie.

On vacation, so responses are bit late. Please bear with me.

>
> On 19/10/16 11:43, Vivek Gautam wrote:
>>
>> Qualcomm SOCs have QMP phy controller that provides support
>> to a number of controller, viz. PCIe, UFS, and USB.
>> Add a new driver, based on generic phy framework, for this
>> phy controller.
>>
>> USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
>> msm-4.4 kernel @codeaurora[1].
>> PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
>> Srinivas [2].
>>
>> [1]
>> https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
>> [2] https://patchwork.kernel.org/patch/9318947/
>>
>> Signed-off-by: Vivek Gautam 
>> Cc: Kishon Vijay Abraham I 
>
>
> very few minor nits which needs fixing in next version.
>
> I have tested this patch on DB820c PCIE with ethernet and SATA ports.
>
> Tested-by: Srinivas Kandagatla 

Thanks for testing the patch.

>
>
>> ---
>>  .../devicetree/bindings/phy/qcom-qmp-phy.txt   |   61 ++
>>  drivers/phy/Kconfig|8 +
>>  drivers/phy/Makefile   |1 +
>>  drivers/phy/phy-qcom-qmp.c | 1154
>> 
>>  4 files changed, 1224 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>>  create mode 100644 drivers/phy/phy-qcom-qmp.c
>>
>> diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>> b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>> new file mode 100644
>> index 000..90214aa
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>> @@ -0,0 +1,61 @@
>> +Qualcomm QMP PHY
>> +
>> +
>> +QMP phy controller supports physical layer functionality for a number of
>> +controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
>> +
>> +Required properties:
>> + - compatible: compatible list, contains:
>> +  "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
>> +  "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
>> + - reg: offset and length of the PHY register set.
>> + - #phy-cells: must be 1
>> +- Cell after phy phandle should be the port (lane) number.
>> + - clocks: a list of phandles and clock-specifier pairs,
>> +  one for each entry in clock-names.
>> + - clock-names: must be "cfg_ahb" for phy config clock,
>> +   "aux" for phy aux clock,
>> +   "ref_clk" for 19.2 MHz ref clk,
>> +   "ref_clk_src" for reference clock source,
>> +   "pipe" for pipe clock specific to
>> +   each port/lane (Optional).
>
>
>> + - resets: a list of phandles and reset controller specifier pairs,
>> +  one for each entry in reset-names.
>> + - reset-names: must be "phy" for reset of phy block,
>> +   "common" for phy common block reset,
>> +   "cfg" for phy's ahb cfg block reset (Optional).
>> +   "port" for reset specific to
>> +   each port/lane. (Optional)
>> + - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
>> + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll
>> block.
>> +
>> +Optional properties:
>> + - vddp-ref-clk-supply: Phandle to a regulator supply to any specific
>> refclk
>> +   pll block.
>> +
>> +Example:
>> +   pcie_phy: pciephy@34000 {
>> +   compatible = "qcom,qmp-14nm-pcie-phy";
>
>
> Fix this according to the compatibilities listed above.

Sure, will fix this.

>
>
>> +   reg = <0x034000 0x3fff>;
>> +   #phy-cells = <1>;
>> +
>> +   clocks = < GCC_PCIE_PHY_AUX_CLK>,
>> +   < GCC_PCIE_PHY_CFG_AHB_CLK>,
>> +   < GCC_PCIE_0_PIPE_CLK>,
>> +   < GCC_PCIE_1_PIPE_CLK>,
>> +   < GCC_PCIE_2_PIPE_CLK>;
>> +   clock-names = "aux", "cfg_ahb",
>> +   "pipe0", "pipe1", "pipe2";
>> +
>> +   vdda-phy-supply = <_l28>;
>> +   vdda-pll-supply = <_l12>;
>> +
>> +   resets = < GCC_PCIE_PHY_BCR>,
>> +   < GCC_PCIE_PHY_COM_BCR>,
>> +   < GCC_PCIE_PHY_COM_NOCSR_BCR>,
>> +   < GCC_PCIE_0_PHY_BCR>,
>> +   < GCC_PCIE_1_PHY_BCR>,
>> +   < GCC_PCIE_2_PHY_BCR>;
>> +   reset-names = "phy", "common", "cfg",
>> +   "lane0", "lane1", "lane2";
>> +   };
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 5547984..d5e2b50f 100644
>> ---

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-11-02 Thread Vivek Gautam

Hi Srini,


On Wed, Oct 26, 2016 at 7:27 PM, Srinivas Kandagatla
 wrote:
> Hi Vivek,
>
> Thanks for consolidating qmp phy support for both usb and pcie.

On vacation, so responses are bit late. Please bear with me.

>
> On 19/10/16 11:43, Vivek Gautam wrote:
>>
>> Qualcomm SOCs have QMP phy controller that provides support
>> to a number of controller, viz. PCIe, UFS, and USB.
>> Add a new driver, based on generic phy framework, for this
>> phy controller.
>>
>> USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
>> msm-4.4 kernel @codeaurora[1].
>> PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
>> Srinivas [2].
>>
>> [1]
>> https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
>> [2] https://patchwork.kernel.org/patch/9318947/
>>
>> Signed-off-by: Vivek Gautam 
>> Cc: Kishon Vijay Abraham I 
>
>
> very few minor nits which needs fixing in next version.
>
> I have tested this patch on DB820c PCIE with ethernet and SATA ports.
>
> Tested-by: Srinivas Kandagatla 

Thanks for testing the patch.

>
>
>> ---
>>  .../devicetree/bindings/phy/qcom-qmp-phy.txt   |   61 ++
>>  drivers/phy/Kconfig|8 +
>>  drivers/phy/Makefile   |1 +
>>  drivers/phy/phy-qcom-qmp.c | 1154
>> 
>>  4 files changed, 1224 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>>  create mode 100644 drivers/phy/phy-qcom-qmp.c
>>
>> diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>> b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>> new file mode 100644
>> index 000..90214aa
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>> @@ -0,0 +1,61 @@
>> +Qualcomm QMP PHY
>> +
>> +
>> +QMP phy controller supports physical layer functionality for a number of
>> +controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
>> +
>> +Required properties:
>> + - compatible: compatible list, contains:
>> +  "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
>> +  "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
>> + - reg: offset and length of the PHY register set.
>> + - #phy-cells: must be 1
>> +- Cell after phy phandle should be the port (lane) number.
>> + - clocks: a list of phandles and clock-specifier pairs,
>> +  one for each entry in clock-names.
>> + - clock-names: must be "cfg_ahb" for phy config clock,
>> +   "aux" for phy aux clock,
>> +   "ref_clk" for 19.2 MHz ref clk,
>> +   "ref_clk_src" for reference clock source,
>> +   "pipe" for pipe clock specific to
>> +   each port/lane (Optional).
>
>
>> + - resets: a list of phandles and reset controller specifier pairs,
>> +  one for each entry in reset-names.
>> + - reset-names: must be "phy" for reset of phy block,
>> +   "common" for phy common block reset,
>> +   "cfg" for phy's ahb cfg block reset (Optional).
>> +   "port" for reset specific to
>> +   each port/lane. (Optional)
>> + - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
>> + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll
>> block.
>> +
>> +Optional properties:
>> + - vddp-ref-clk-supply: Phandle to a regulator supply to any specific
>> refclk
>> +   pll block.
>> +
>> +Example:
>> +   pcie_phy: pciephy@34000 {
>> +   compatible = "qcom,qmp-14nm-pcie-phy";
>
>
> Fix this according to the compatibilities listed above.

Sure, will fix this.

>
>
>> +   reg = <0x034000 0x3fff>;
>> +   #phy-cells = <1>;
>> +
>> +   clocks = < GCC_PCIE_PHY_AUX_CLK>,
>> +   < GCC_PCIE_PHY_CFG_AHB_CLK>,
>> +   < GCC_PCIE_0_PIPE_CLK>,
>> +   < GCC_PCIE_1_PIPE_CLK>,
>> +   < GCC_PCIE_2_PIPE_CLK>;
>> +   clock-names = "aux", "cfg_ahb",
>> +   "pipe0", "pipe1", "pipe2";
>> +
>> +   vdda-phy-supply = <_l28>;
>> +   vdda-pll-supply = <_l12>;
>> +
>> +   resets = < GCC_PCIE_PHY_BCR>,
>> +   < GCC_PCIE_PHY_COM_BCR>,
>> +   < GCC_PCIE_PHY_COM_NOCSR_BCR>,
>> +   < GCC_PCIE_0_PHY_BCR>,
>> +   < GCC_PCIE_1_PHY_BCR>,
>> +   < GCC_PCIE_2_PHY_BCR>;
>> +   reset-names = "phy", "common", "cfg",
>> +   "lane0", "lane1", "lane2";
>> +   };
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 5547984..d5e2b50f 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -446,6 +446,14 @@ config PHY_STIH41X_USB
>>

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-10-26 Thread Rob Herring

On Wed, Oct 19, 2016 at 04:13:47PM +0530, Vivek Gautam wrote:
> Qualcomm SOCs have QMP phy controller that provides support
> to a number of controller, viz. PCIe, UFS, and USB.
> Add a new driver, based on generic phy framework, for this
> phy controller.
> 
> USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
> msm-4.4 kernel @codeaurora[1].
> PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
> Srinivas [2].
> 
> [1] 
> https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
> [2] https://patchwork.kernel.org/patch/9318947/
> 
> Signed-off-by: Vivek Gautam 
> Cc: Kishon Vijay Abraham I 
> ---
>  .../devicetree/bindings/phy/qcom-qmp-phy.txt   |   61 ++

Acked-by: Rob Herring 

>  drivers/phy/Kconfig|8 +
>  drivers/phy/Makefile   |1 +
>  drivers/phy/phy-qcom-qmp.c | 1154 
> 
>  4 files changed, 1224 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>  create mode 100644 drivers/phy/phy-qcom-qmp.c

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-10-26 Thread Rob Herring

On Wed, Oct 19, 2016 at 04:13:47PM +0530, Vivek Gautam wrote:
> Qualcomm SOCs have QMP phy controller that provides support
> to a number of controller, viz. PCIe, UFS, and USB.
> Add a new driver, based on generic phy framework, for this
> phy controller.
> 
> USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
> msm-4.4 kernel @codeaurora[1].
> PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
> Srinivas [2].
> 
> [1] 
> https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
> [2] https://patchwork.kernel.org/patch/9318947/
> 
> Signed-off-by: Vivek Gautam 
> Cc: Kishon Vijay Abraham I 
> ---
>  .../devicetree/bindings/phy/qcom-qmp-phy.txt   |   61 ++

Acked-by: Rob Herring 

>  drivers/phy/Kconfig|8 +
>  drivers/phy/Makefile   |1 +
>  drivers/phy/phy-qcom-qmp.c | 1154 
> 
>  4 files changed, 1224 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>  create mode 100644 drivers/phy/phy-qcom-qmp.c

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-10-26 Thread Kishon Vijay Abraham I

Hi,

On Wednesday 19 October 2016 04:13 PM, Vivek Gautam wrote:
> Qualcomm SOCs have QMP phy controller that provides support
> to a number of controller, viz. PCIe, UFS, and USB.
> Add a new driver, based on generic phy framework, for this
> phy controller.
> 
> USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
> msm-4.4 kernel @codeaurora[1].
> PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
> Srinivas [2].
> 
> [1] 
> https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
> [2] https://patchwork.kernel.org/patch/9318947/

use only lkml links here.
> 
> Signed-off-by: Vivek Gautam 
> Cc: Kishon Vijay Abraham I 
> ---
>  .../devicetree/bindings/phy/qcom-qmp-phy.txt   |   61 ++
>  drivers/phy/Kconfig|8 +
>  drivers/phy/Makefile   |1 +
>  drivers/phy/phy-qcom-qmp.c | 1154 
> 
>  4 files changed, 1224 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>  create mode 100644 drivers/phy/phy-qcom-qmp.c
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt 
> b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> new file mode 100644
> index 000..90214aa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> @@ -0,0 +1,61 @@
> +Qualcomm QMP PHY
> +
> +
> +QMP phy controller supports physical layer functionality for a number of
> +controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
> +
> +Required properties:
> + - compatible: compatible list, contains:
> +"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
> +"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
> + - reg: offset and length of the PHY register set.
> + - #phy-cells: must be 1
> +- Cell after phy phandle should be the port (lane) number.
> + - clocks: a list of phandles and clock-specifier pairs,
> +one for each entry in clock-names.
> + - clock-names: must be "cfg_ahb" for phy config clock,
> + "aux" for phy aux clock,
> + "ref_clk" for 19.2 MHz ref clk,
> + "ref_clk_src" for reference clock source,
> + "pipe" for pipe clock specific to
> + each port/lane (Optional).
> + - resets: a list of phandles and reset controller specifier pairs,
> +one for each entry in reset-names.
> + - reset-names: must be "phy" for reset of phy block,
> + "common" for phy common block reset,
> + "cfg" for phy's ahb cfg block reset (Optional).
> + "port" for reset specific to
> + each port/lane. (Optional)
> + - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
> + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
> +
> +Optional properties:
> + - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
> + pll block.
> +
> +Example:
> + pcie_phy: pciephy@34000 {
> + compatible = "qcom,qmp-14nm-pcie-phy";
> + reg = <0x034000 0x3fff>;
> + #phy-cells = <1>;
> +
> + clocks = < GCC_PCIE_PHY_AUX_CLK>,
> + < GCC_PCIE_PHY_CFG_AHB_CLK>,
> + < GCC_PCIE_0_PIPE_CLK>,
> + < GCC_PCIE_1_PIPE_CLK>,
> + < GCC_PCIE_2_PIPE_CLK>;
> + clock-names = "aux", "cfg_ahb",
> + "pipe0", "pipe1", "pipe2";
> +
> + vdda-phy-supply = <_l28>;
> + vdda-pll-supply = <_l12>;
> +
> + resets = < GCC_PCIE_PHY_BCR>,
> + < GCC_PCIE_PHY_COM_BCR>,
> + < GCC_PCIE_PHY_COM_NOCSR_BCR>,
> + < GCC_PCIE_0_PHY_BCR>,
> + < GCC_PCIE_1_PHY_BCR>,
> + < GCC_PCIE_2_PHY_BCR>;
> + reset-names = "phy", "common", "cfg",
> + "lane0", "lane1", "lane2";
> + };
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 5547984..d5e2b50f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -446,6 +446,14 @@ config PHY_STIH41X_USB
> Enable this to support the USB transceiver that is part of
> STMicroelectronics STiH41x SoC series.
>  
> +config PHY_QCOM_QMP
> + tristate "Qualcomm QMP PHY Driver"
> + depends on OF && (ARCH_QCOM || COMPILE_TEST)
> + select GENERIC_PHY
> + help
> +   Enable this to support the QMP PHY transceiver that is used
> +   with controllers such as PCIe, UFS, and USB on Qualcomm chips.
> +
>  config PHY_QCOM_QUSB2
>   tristate "Qualcomm QUSB2 PHY Driver"
>   depends on OF && (ARCH_QCOM || COMPILE_TEST)
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-10-26 Thread Kishon Vijay Abraham I

Hi,

On Wednesday 19 October 2016 04:13 PM, Vivek Gautam wrote:
> Qualcomm SOCs have QMP phy controller that provides support
> to a number of controller, viz. PCIe, UFS, and USB.
> Add a new driver, based on generic phy framework, for this
> phy controller.
> 
> USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
> msm-4.4 kernel @codeaurora[1].
> PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
> Srinivas [2].
> 
> [1] 
> https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
> [2] https://patchwork.kernel.org/patch/9318947/

use only lkml links here.
> 
> Signed-off-by: Vivek Gautam 
> Cc: Kishon Vijay Abraham I 
> ---
>  .../devicetree/bindings/phy/qcom-qmp-phy.txt   |   61 ++
>  drivers/phy/Kconfig|8 +
>  drivers/phy/Makefile   |1 +
>  drivers/phy/phy-qcom-qmp.c | 1154 
> 
>  4 files changed, 1224 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>  create mode 100644 drivers/phy/phy-qcom-qmp.c
> 
> diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt 
> b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> new file mode 100644
> index 000..90214aa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> @@ -0,0 +1,61 @@
> +Qualcomm QMP PHY
> +
> +
> +QMP phy controller supports physical layer functionality for a number of
> +controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
> +
> +Required properties:
> + - compatible: compatible list, contains:
> +"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
> +"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
> + - reg: offset and length of the PHY register set.
> + - #phy-cells: must be 1
> +- Cell after phy phandle should be the port (lane) number.
> + - clocks: a list of phandles and clock-specifier pairs,
> +one for each entry in clock-names.
> + - clock-names: must be "cfg_ahb" for phy config clock,
> + "aux" for phy aux clock,
> + "ref_clk" for 19.2 MHz ref clk,
> + "ref_clk_src" for reference clock source,
> + "pipe" for pipe clock specific to
> + each port/lane (Optional).
> + - resets: a list of phandles and reset controller specifier pairs,
> +one for each entry in reset-names.
> + - reset-names: must be "phy" for reset of phy block,
> + "common" for phy common block reset,
> + "cfg" for phy's ahb cfg block reset (Optional).
> + "port" for reset specific to
> + each port/lane. (Optional)
> + - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
> + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
> +
> +Optional properties:
> + - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
> + pll block.
> +
> +Example:
> + pcie_phy: pciephy@34000 {
> + compatible = "qcom,qmp-14nm-pcie-phy";
> + reg = <0x034000 0x3fff>;
> + #phy-cells = <1>;
> +
> + clocks = < GCC_PCIE_PHY_AUX_CLK>,
> + < GCC_PCIE_PHY_CFG_AHB_CLK>,
> + < GCC_PCIE_0_PIPE_CLK>,
> + < GCC_PCIE_1_PIPE_CLK>,
> + < GCC_PCIE_2_PIPE_CLK>;
> + clock-names = "aux", "cfg_ahb",
> + "pipe0", "pipe1", "pipe2";
> +
> + vdda-phy-supply = <_l28>;
> + vdda-pll-supply = <_l12>;
> +
> + resets = < GCC_PCIE_PHY_BCR>,
> + < GCC_PCIE_PHY_COM_BCR>,
> + < GCC_PCIE_PHY_COM_NOCSR_BCR>,
> + < GCC_PCIE_0_PHY_BCR>,
> + < GCC_PCIE_1_PHY_BCR>,
> + < GCC_PCIE_2_PHY_BCR>;
> + reset-names = "phy", "common", "cfg",
> + "lane0", "lane1", "lane2";
> + };
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 5547984..d5e2b50f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -446,6 +446,14 @@ config PHY_STIH41X_USB
> Enable this to support the USB transceiver that is part of
> STMicroelectronics STiH41x SoC series.
>  
> +config PHY_QCOM_QMP
> + tristate "Qualcomm QMP PHY Driver"
> + depends on OF && (ARCH_QCOM || COMPILE_TEST)
> + select GENERIC_PHY
> + help
> +   Enable this to support the QMP PHY transceiver that is used
> +   with controllers such as PCIe, UFS, and USB on Qualcomm chips.
> +
>  config PHY_QCOM_QUSB2
>   tristate "Qualcomm QUSB2 PHY Driver"
>   depends on OF && (ARCH_QCOM || COMPILE_TEST)
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 848489d..fde9fba 100644
> ---

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-10-26 Thread Srinivas Kandagatla


Hi Vivek,

Thanks for consolidating qmp phy support for both usb and pcie.

On 19/10/16 11:43, Vivek Gautam wrote:

Qualcomm SOCs have QMP phy controller that provides support
to a number of controller, viz. PCIe, UFS, and USB.
Add a new driver, based on generic phy framework, for this
phy controller.

USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
msm-4.4 kernel @codeaurora[1].
PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
Srinivas [2].

[1] 
https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
[2] https://patchwork.kernel.org/patch/9318947/

Signed-off-by: Vivek Gautam 
Cc: Kishon Vijay Abraham I 


very few minor nits which needs fixing in next version.

I have tested this patch on DB820c PCIE with ethernet and SATA ports.

Tested-by: Srinivas Kandagatla 


---
 .../devicetree/bindings/phy/qcom-qmp-phy.txt   |   61 ++
 drivers/phy/Kconfig|8 +
 drivers/phy/Makefile   |1 +
 drivers/phy/phy-qcom-qmp.c | 1154 
 4 files changed, 1224 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
 create mode 100644 drivers/phy/phy-qcom-qmp.c

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt 
b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
new file mode 100644
index 000..90214aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -0,0 +1,61 @@
+Qualcomm QMP PHY
+
+
+QMP phy controller supports physical layer functionality for a number of
+controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+Required properties:
+ - compatible: compatible list, contains:
+  "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
+  "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
+ - reg: offset and length of the PHY register set.
+ - #phy-cells: must be 1
+- Cell after phy phandle should be the port (lane) number.
+ - clocks: a list of phandles and clock-specifier pairs,
+  one for each entry in clock-names.
+ - clock-names: must be "cfg_ahb" for phy config clock,
+   "aux" for phy aux clock,
+   "ref_clk" for 19.2 MHz ref clk,
+   "ref_clk_src" for reference clock source,
+   "pipe" for pipe clock specific to
+   each port/lane (Optional).



+ - resets: a list of phandles and reset controller specifier pairs,
+  one for each entry in reset-names.
+ - reset-names: must be "phy" for reset of phy block,
+   "common" for phy common block reset,
+   "cfg" for phy's ahb cfg block reset (Optional).
+   "port" for reset specific to
+   each port/lane. (Optional)
+ - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
+ - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+Optional properties:
+ - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
+   pll block.
+
+Example:
+   pcie_phy: pciephy@34000 {
+   compatible = "qcom,qmp-14nm-pcie-phy";


Fix this according to the compatibilities listed above.


+   reg = <0x034000 0x3fff>;
+   #phy-cells = <1>;
+
+   clocks = < GCC_PCIE_PHY_AUX_CLK>,
+   < GCC_PCIE_PHY_CFG_AHB_CLK>,
+   < GCC_PCIE_0_PIPE_CLK>,
+   < GCC_PCIE_1_PIPE_CLK>,
+   < GCC_PCIE_2_PIPE_CLK>;
+   clock-names = "aux", "cfg_ahb",
+   "pipe0", "pipe1", "pipe2";
+
+   vdda-phy-supply = <_l28>;
+   vdda-pll-supply = <_l12>;
+
+   resets = < GCC_PCIE_PHY_BCR>,
+   < GCC_PCIE_PHY_COM_BCR>,
+   < GCC_PCIE_PHY_COM_NOCSR_BCR>,
+   < GCC_PCIE_0_PHY_BCR>,
+   < GCC_PCIE_1_PHY_BCR>,
+   < GCC_PCIE_2_PHY_BCR>;
+   reset-names = "phy", "common", "cfg",
+   "lane0", "lane1", "lane2";
+   };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5547984..d5e2b50f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -446,6 +446,14 @@ config PHY_STIH41X_USB
  Enable this to support the USB transceiver that is part of
  STMicroelectronics STiH41x SoC series.

+config PHY_QCOM_QMP
+   tristate "Qualcomm QMP PHY Driver"
+   depends on OF && (ARCH_QCOM || COMPILE_TEST)
+   select GENERIC_PHY
+   help
+ Enable this to support the QMP PHY transceiver that is used
+ with controllers such as PCIe, UFS, and USB on Qualcomm chips.
+
 config PHY_QCOM_QUSB2

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-10-26 Thread Srinivas Kandagatla


Hi Vivek,

Thanks for consolidating qmp phy support for both usb and pcie.

On 19/10/16 11:43, Vivek Gautam wrote:

Qualcomm SOCs have QMP phy controller that provides support
to a number of controller, viz. PCIe, UFS, and USB.
Add a new driver, based on generic phy framework, for this
phy controller.

USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
msm-4.4 kernel @codeaurora[1].
PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
Srinivas [2].

[1] 
https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
[2] https://patchwork.kernel.org/patch/9318947/

Signed-off-by: Vivek Gautam 
Cc: Kishon Vijay Abraham I 


very few minor nits which needs fixing in next version.

I have tested this patch on DB820c PCIE with ethernet and SATA ports.

Tested-by: Srinivas Kandagatla 


---
 .../devicetree/bindings/phy/qcom-qmp-phy.txt   |   61 ++
 drivers/phy/Kconfig|8 +
 drivers/phy/Makefile   |1 +
 drivers/phy/phy-qcom-qmp.c | 1154 
 4 files changed, 1224 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
 create mode 100644 drivers/phy/phy-qcom-qmp.c

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt 
b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
new file mode 100644
index 000..90214aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -0,0 +1,61 @@
+Qualcomm QMP PHY
+
+
+QMP phy controller supports physical layer functionality for a number of
+controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+Required properties:
+ - compatible: compatible list, contains:
+  "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
+  "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
+ - reg: offset and length of the PHY register set.
+ - #phy-cells: must be 1
+- Cell after phy phandle should be the port (lane) number.
+ - clocks: a list of phandles and clock-specifier pairs,
+  one for each entry in clock-names.
+ - clock-names: must be "cfg_ahb" for phy config clock,
+   "aux" for phy aux clock,
+   "ref_clk" for 19.2 MHz ref clk,
+   "ref_clk_src" for reference clock source,
+   "pipe" for pipe clock specific to
+   each port/lane (Optional).



+ - resets: a list of phandles and reset controller specifier pairs,
+  one for each entry in reset-names.
+ - reset-names: must be "phy" for reset of phy block,
+   "common" for phy common block reset,
+   "cfg" for phy's ahb cfg block reset (Optional).
+   "port" for reset specific to
+   each port/lane. (Optional)
+ - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
+ - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+Optional properties:
+ - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
+   pll block.
+
+Example:
+   pcie_phy: pciephy@34000 {
+   compatible = "qcom,qmp-14nm-pcie-phy";


Fix this according to the compatibilities listed above.


+   reg = <0x034000 0x3fff>;
+   #phy-cells = <1>;
+
+   clocks = < GCC_PCIE_PHY_AUX_CLK>,
+   < GCC_PCIE_PHY_CFG_AHB_CLK>,
+   < GCC_PCIE_0_PIPE_CLK>,
+   < GCC_PCIE_1_PIPE_CLK>,
+   < GCC_PCIE_2_PIPE_CLK>;
+   clock-names = "aux", "cfg_ahb",
+   "pipe0", "pipe1", "pipe2";
+
+   vdda-phy-supply = <_l28>;
+   vdda-pll-supply = <_l12>;
+
+   resets = < GCC_PCIE_PHY_BCR>,
+   < GCC_PCIE_PHY_COM_BCR>,
+   < GCC_PCIE_PHY_COM_NOCSR_BCR>,
+   < GCC_PCIE_0_PHY_BCR>,
+   < GCC_PCIE_1_PHY_BCR>,
+   < GCC_PCIE_2_PHY_BCR>;
+   reset-names = "phy", "common", "cfg",
+   "lane0", "lane1", "lane2";
+   };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5547984..d5e2b50f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -446,6 +446,14 @@ config PHY_STIH41X_USB
  Enable this to support the USB transceiver that is part of
  STMicroelectronics STiH41x SoC series.

+config PHY_QCOM_QMP
+   tristate "Qualcomm QMP PHY Driver"
+   depends on OF && (ARCH_QCOM || COMPILE_TEST)
+   select GENERIC_PHY
+   help
+ Enable this to support the QMP PHY transceiver that is used
+ with controllers such as PCIe, UFS, and USB on Qualcomm chips.
+
 config PHY_QCOM_QUSB2
tristate "Qualcomm QUSB2 PHY Driver"
depends on OF && (ARCH_QCOM ||

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-10-19 Thread Vivek Gautam

On Wed, Oct 19, 2016 at 4:24 PM, Vivek Gautam
 wrote:
> CC: Srinivas Kandagatla
>
>
> On 10/19/2016 04:13 PM, Vivek Gautam wrote:
>>
>> Qualcomm SOCs have QMP phy controller that provides support
>> to a number of controller, viz. PCIe, UFS, and USB.
>> Add a new driver, based on generic phy framework, for this
>> phy controller.
>>
>> USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
>> msm-4.4 kernel @codeaurora[1].
>> PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
>> Srinivas [2].
>>
>> [1]
>> https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
>> [2] https://patchwork.kernel.org/patch/9318947/
>>
>> Signed-off-by: Vivek Gautam 
>> Cc: Kishon Vijay Abraham I 
>> ---

[snip]

>> +static int qcom_qmp_phy_com_init(struct qcom_qmp_phy *qphy)
>> +{
>> +   const struct qmp_phy_init_cfg *cfg = qphy->cfg;
>> +   void __iomem *serdes = qphy->serdes;
>> +   int ret;
>> +
>> +   mutex_lock(>phy_mutex);
>> +   if (qphy->init_count++) {
>> +   mutex_unlock(>phy_mutex);
>> +   return 0;
>> +   }
>> +
>> +   ret = reset_control_deassert(qphy->phy_rst);
>> +   if (ret) {
>> +   dev_err(qphy->dev, "phy reset deassert failed\n");
>> +   return ret;

Pointed out by Kbuild-test: drivers/phy/phy-qcom-qmp.c:677:2-8:
preceding lock on line 668

The mutex has to be unlocked for all error cases.
Will fix this in the next patch version.

[snip]


Thanks
Vivek


-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-10-19 Thread Vivek Gautam

On Wed, Oct 19, 2016 at 4:24 PM, Vivek Gautam
 wrote:
> CC: Srinivas Kandagatla
>
>
> On 10/19/2016 04:13 PM, Vivek Gautam wrote:
>>
>> Qualcomm SOCs have QMP phy controller that provides support
>> to a number of controller, viz. PCIe, UFS, and USB.
>> Add a new driver, based on generic phy framework, for this
>> phy controller.
>>
>> USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
>> msm-4.4 kernel @codeaurora[1].
>> PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
>> Srinivas [2].
>>
>> [1]
>> https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
>> [2] https://patchwork.kernel.org/patch/9318947/
>>
>> Signed-off-by: Vivek Gautam 
>> Cc: Kishon Vijay Abraham I 
>> ---

[snip]

>> +static int qcom_qmp_phy_com_init(struct qcom_qmp_phy *qphy)
>> +{
>> +   const struct qmp_phy_init_cfg *cfg = qphy->cfg;
>> +   void __iomem *serdes = qphy->serdes;
>> +   int ret;
>> +
>> +   mutex_lock(>phy_mutex);
>> +   if (qphy->init_count++) {
>> +   mutex_unlock(>phy_mutex);
>> +   return 0;
>> +   }
>> +
>> +   ret = reset_control_deassert(qphy->phy_rst);
>> +   if (ret) {
>> +   dev_err(qphy->dev, "phy reset deassert failed\n");
>> +   return ret;

Pointed out by Kbuild-test: drivers/phy/phy-qcom-qmp.c:677:2-8:
preceding lock on line 668

The mutex has to be unlocked for all error cases.
Will fix this in the next patch version.

[snip]


Thanks
Vivek


-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-10-19 Thread Vivek Gautam

Qualcomm SOCs have QMP phy controller that provides support
to a number of controller, viz. PCIe, UFS, and USB.
Add a new driver, based on generic phy framework, for this
phy controller.

USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
msm-4.4 kernel @codeaurora[1].
PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
Srinivas [2].

[1] 
https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
[2] https://patchwork.kernel.org/patch/9318947/

Signed-off-by: Vivek Gautam 
Cc: Kishon Vijay Abraham I 
---
 .../devicetree/bindings/phy/qcom-qmp-phy.txt   |   61 ++
 drivers/phy/Kconfig|8 +
 drivers/phy/Makefile   |1 +
 drivers/phy/phy-qcom-qmp.c | 1154 
 4 files changed, 1224 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
 create mode 100644 drivers/phy/phy-qcom-qmp.c

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt 
b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
new file mode 100644
index 000..90214aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -0,0 +1,61 @@
+Qualcomm QMP PHY
+
+
+QMP phy controller supports physical layer functionality for a number of
+controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+Required properties:
+ - compatible: compatible list, contains:
+  "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
+  "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
+ - reg: offset and length of the PHY register set.
+ - #phy-cells: must be 1
+- Cell after phy phandle should be the port (lane) number.
+ - clocks: a list of phandles and clock-specifier pairs,
+  one for each entry in clock-names.
+ - clock-names: must be "cfg_ahb" for phy config clock,
+   "aux" for phy aux clock,
+   "ref_clk" for 19.2 MHz ref clk,
+   "ref_clk_src" for reference clock source,
+   "pipe" for pipe clock specific to
+   each port/lane (Optional).
+ - resets: a list of phandles and reset controller specifier pairs,
+  one for each entry in reset-names.
+ - reset-names: must be "phy" for reset of phy block,
+   "common" for phy common block reset,
+   "cfg" for phy's ahb cfg block reset (Optional).
+   "port" for reset specific to
+   each port/lane. (Optional)
+ - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
+ - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+Optional properties:
+ - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
+   pll block.
+
+Example:
+   pcie_phy: pciephy@34000 {
+   compatible = "qcom,qmp-14nm-pcie-phy";
+   reg = <0x034000 0x3fff>;
+   #phy-cells = <1>;
+
+   clocks = < GCC_PCIE_PHY_AUX_CLK>,
+   < GCC_PCIE_PHY_CFG_AHB_CLK>,
+   < GCC_PCIE_0_PIPE_CLK>,
+   < GCC_PCIE_1_PIPE_CLK>,
+   < GCC_PCIE_2_PIPE_CLK>;
+   clock-names = "aux", "cfg_ahb",
+   "pipe0", "pipe1", "pipe2";
+
+   vdda-phy-supply = <_l28>;
+   vdda-pll-supply = <_l12>;
+
+   resets = < GCC_PCIE_PHY_BCR>,
+   < GCC_PCIE_PHY_COM_BCR>,
+   < GCC_PCIE_PHY_COM_NOCSR_BCR>,
+   < GCC_PCIE_0_PHY_BCR>,
+   < GCC_PCIE_1_PHY_BCR>,
+   < GCC_PCIE_2_PHY_BCR>;
+   reset-names = "phy", "common", "cfg",
+   "lane0", "lane1", "lane2";
+   };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5547984..d5e2b50f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -446,6 +446,14 @@ config PHY_STIH41X_USB
  Enable this to support the USB transceiver that is part of
  STMicroelectronics STiH41x SoC series.
 
+config PHY_QCOM_QMP
+   tristate "Qualcomm QMP PHY Driver"
+   depends on OF && (ARCH_QCOM || COMPILE_TEST)
+   select GENERIC_PHY
+   help
+ Enable this to support the QMP PHY transceiver that is used
+ with controllers such as PCIe, UFS, and USB on Qualcomm chips.
+
 config PHY_QCOM_QUSB2
tristate "Qualcomm QUSB2 PHY Driver"
depends on OF && (ARCH_QCOM || COMPILE_TEST)
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 848489d..fde9fba 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)  += phy-spear1340-miphy.o
 obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o

[PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-10-19 Thread Vivek Gautam

Qualcomm SOCs have QMP phy controller that provides support
to a number of controller, viz. PCIe, UFS, and USB.
Add a new driver, based on generic phy framework, for this
phy controller.

USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
msm-4.4 kernel @codeaurora[1].
PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
Srinivas [2].

[1] 
https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
[2] https://patchwork.kernel.org/patch/9318947/

Signed-off-by: Vivek Gautam 
Cc: Kishon Vijay Abraham I 
---
 .../devicetree/bindings/phy/qcom-qmp-phy.txt   |   61 ++
 drivers/phy/Kconfig|8 +
 drivers/phy/Makefile   |1 +
 drivers/phy/phy-qcom-qmp.c | 1154 
 4 files changed, 1224 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
 create mode 100644 drivers/phy/phy-qcom-qmp.c

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt 
b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
new file mode 100644
index 000..90214aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -0,0 +1,61 @@
+Qualcomm QMP PHY
+
+
+QMP phy controller supports physical layer functionality for a number of
+controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+Required properties:
+ - compatible: compatible list, contains:
+  "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
+  "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
+ - reg: offset and length of the PHY register set.
+ - #phy-cells: must be 1
+- Cell after phy phandle should be the port (lane) number.
+ - clocks: a list of phandles and clock-specifier pairs,
+  one for each entry in clock-names.
+ - clock-names: must be "cfg_ahb" for phy config clock,
+   "aux" for phy aux clock,
+   "ref_clk" for 19.2 MHz ref clk,
+   "ref_clk_src" for reference clock source,
+   "pipe" for pipe clock specific to
+   each port/lane (Optional).
+ - resets: a list of phandles and reset controller specifier pairs,
+  one for each entry in reset-names.
+ - reset-names: must be "phy" for reset of phy block,
+   "common" for phy common block reset,
+   "cfg" for phy's ahb cfg block reset (Optional).
+   "port" for reset specific to
+   each port/lane. (Optional)
+ - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
+ - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+Optional properties:
+ - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
+   pll block.
+
+Example:
+   pcie_phy: pciephy@34000 {
+   compatible = "qcom,qmp-14nm-pcie-phy";
+   reg = <0x034000 0x3fff>;
+   #phy-cells = <1>;
+
+   clocks = < GCC_PCIE_PHY_AUX_CLK>,
+   < GCC_PCIE_PHY_CFG_AHB_CLK>,
+   < GCC_PCIE_0_PIPE_CLK>,
+   < GCC_PCIE_1_PIPE_CLK>,
+   < GCC_PCIE_2_PIPE_CLK>;
+   clock-names = "aux", "cfg_ahb",
+   "pipe0", "pipe1", "pipe2";
+
+   vdda-phy-supply = <_l28>;
+   vdda-pll-supply = <_l12>;
+
+   resets = < GCC_PCIE_PHY_BCR>,
+   < GCC_PCIE_PHY_COM_BCR>,
+   < GCC_PCIE_PHY_COM_NOCSR_BCR>,
+   < GCC_PCIE_0_PHY_BCR>,
+   < GCC_PCIE_1_PHY_BCR>,
+   < GCC_PCIE_2_PHY_BCR>;
+   reset-names = "phy", "common", "cfg",
+   "lane0", "lane1", "lane2";
+   };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5547984..d5e2b50f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -446,6 +446,14 @@ config PHY_STIH41X_USB
  Enable this to support the USB transceiver that is part of
  STMicroelectronics STiH41x SoC series.
 
+config PHY_QCOM_QMP
+   tristate "Qualcomm QMP PHY Driver"
+   depends on OF && (ARCH_QCOM || COMPILE_TEST)
+   select GENERIC_PHY
+   help
+ Enable this to support the QMP PHY transceiver that is used
+ with controllers such as PCIe, UFS, and USB on Qualcomm chips.
+
 config PHY_QCOM_QUSB2
tristate "Qualcomm QUSB2 PHY Driver"
depends on OF && (ARCH_QCOM || COMPILE_TEST)
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 848489d..fde9fba 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)  += phy-spear1340-miphy.o
 obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
 obj-$(CONFIG_PHY_STIH407_USB)  +=

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-10-19 Thread Vivek Gautam


CC: Srinivas Kandagatla

On 10/19/2016 04:13 PM, Vivek Gautam wrote:

Qualcomm SOCs have QMP phy controller that provides support
to a number of controller, viz. PCIe, UFS, and USB.
Add a new driver, based on generic phy framework, for this
phy controller.

USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
msm-4.4 kernel @codeaurora[1].
PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
Srinivas [2].

[1] 
https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
[2] https://patchwork.kernel.org/patch/9318947/

Signed-off-by: Vivek Gautam 
Cc: Kishon Vijay Abraham I 
---
  .../devicetree/bindings/phy/qcom-qmp-phy.txt   |   61 ++
  drivers/phy/Kconfig|8 +
  drivers/phy/Makefile   |1 +
  drivers/phy/phy-qcom-qmp.c | 1154 
  4 files changed, 1224 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
  create mode 100644 drivers/phy/phy-qcom-qmp.c

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt 
b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
new file mode 100644
index 000..90214aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -0,0 +1,61 @@
+Qualcomm QMP PHY
+
+
+QMP phy controller supports physical layer functionality for a number of
+controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+Required properties:
+ - compatible: compatible list, contains:
+  "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
+  "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
+ - reg: offset and length of the PHY register set.
+ - #phy-cells: must be 1
+- Cell after phy phandle should be the port (lane) number.
+ - clocks: a list of phandles and clock-specifier pairs,
+  one for each entry in clock-names.
+ - clock-names: must be "cfg_ahb" for phy config clock,
+   "aux" for phy aux clock,
+   "ref_clk" for 19.2 MHz ref clk,
+   "ref_clk_src" for reference clock source,
+   "pipe" for pipe clock specific to
+   each port/lane (Optional).
+ - resets: a list of phandles and reset controller specifier pairs,
+  one for each entry in reset-names.
+ - reset-names: must be "phy" for reset of phy block,
+   "common" for phy common block reset,
+   "cfg" for phy's ahb cfg block reset (Optional).
+   "port" for reset specific to
+   each port/lane. (Optional)
+ - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
+ - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+Optional properties:
+ - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
+   pll block.
+
+Example:
+   pcie_phy: pciephy@34000 {
+   compatible = "qcom,qmp-14nm-pcie-phy";
+   reg = <0x034000 0x3fff>;
+   #phy-cells = <1>;
+
+   clocks = < GCC_PCIE_PHY_AUX_CLK>,
+   < GCC_PCIE_PHY_CFG_AHB_CLK>,
+   < GCC_PCIE_0_PIPE_CLK>,
+   < GCC_PCIE_1_PIPE_CLK>,
+   < GCC_PCIE_2_PIPE_CLK>;
+   clock-names = "aux", "cfg_ahb",
+   "pipe0", "pipe1", "pipe2";
+
+   vdda-phy-supply = <_l28>;
+   vdda-pll-supply = <_l12>;
+
+   resets = < GCC_PCIE_PHY_BCR>,
+   < GCC_PCIE_PHY_COM_BCR>,
+   < GCC_PCIE_PHY_COM_NOCSR_BCR>,
+   < GCC_PCIE_0_PHY_BCR>,
+   < GCC_PCIE_1_PHY_BCR>,
+   < GCC_PCIE_2_PHY_BCR>;
+   reset-names = "phy", "common", "cfg",
+   "lane0", "lane1", "lane2";
+   };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5547984..d5e2b50f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -446,6 +446,14 @@ config PHY_STIH41X_USB
  Enable this to support the USB transceiver that is part of
  STMicroelectronics STiH41x SoC series.
  
+config PHY_QCOM_QMP

+   tristate "Qualcomm QMP PHY Driver"
+   depends on OF && (ARCH_QCOM || COMPILE_TEST)
+   select GENERIC_PHY
+   help
+ Enable this to support the QMP PHY transceiver that is used
+ with controllers such as PCIe, UFS, and USB on Qualcomm chips.
+
  config PHY_QCOM_QUSB2
tristate "Qualcomm QUSB2 PHY Driver"
depends on OF && (ARCH_QCOM || COMPILE_TEST)
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 848489d..fde9fba 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)  +=

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

2016-10-19 Thread Vivek Gautam


CC: Srinivas Kandagatla

On 10/19/2016 04:13 PM, Vivek Gautam wrote:

Qualcomm SOCs have QMP phy controller that provides support
to a number of controller, viz. PCIe, UFS, and USB.
Add a new driver, based on generic phy framework, for this
phy controller.

USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
msm-4.4 kernel @codeaurora[1].
PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
Srinivas [2].

[1] 
https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
[2] https://patchwork.kernel.org/patch/9318947/

Signed-off-by: Vivek Gautam 
Cc: Kishon Vijay Abraham I 
---
  .../devicetree/bindings/phy/qcom-qmp-phy.txt   |   61 ++
  drivers/phy/Kconfig|8 +
  drivers/phy/Makefile   |1 +
  drivers/phy/phy-qcom-qmp.c | 1154 
  4 files changed, 1224 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
  create mode 100644 drivers/phy/phy-qcom-qmp.c

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt 
b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
new file mode 100644
index 000..90214aa
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -0,0 +1,61 @@
+Qualcomm QMP PHY
+
+
+QMP phy controller supports physical layer functionality for a number of
+controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+Required properties:
+ - compatible: compatible list, contains:
+  "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
+  "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
+ - reg: offset and length of the PHY register set.
+ - #phy-cells: must be 1
+- Cell after phy phandle should be the port (lane) number.
+ - clocks: a list of phandles and clock-specifier pairs,
+  one for each entry in clock-names.
+ - clock-names: must be "cfg_ahb" for phy config clock,
+   "aux" for phy aux clock,
+   "ref_clk" for 19.2 MHz ref clk,
+   "ref_clk_src" for reference clock source,
+   "pipe" for pipe clock specific to
+   each port/lane (Optional).
+ - resets: a list of phandles and reset controller specifier pairs,
+  one for each entry in reset-names.
+ - reset-names: must be "phy" for reset of phy block,
+   "common" for phy common block reset,
+   "cfg" for phy's ahb cfg block reset (Optional).
+   "port" for reset specific to
+   each port/lane. (Optional)
+ - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
+ - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+Optional properties:
+ - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
+   pll block.
+
+Example:
+   pcie_phy: pciephy@34000 {
+   compatible = "qcom,qmp-14nm-pcie-phy";
+   reg = <0x034000 0x3fff>;
+   #phy-cells = <1>;
+
+   clocks = < GCC_PCIE_PHY_AUX_CLK>,
+   < GCC_PCIE_PHY_CFG_AHB_CLK>,
+   < GCC_PCIE_0_PIPE_CLK>,
+   < GCC_PCIE_1_PIPE_CLK>,
+   < GCC_PCIE_2_PIPE_CLK>;
+   clock-names = "aux", "cfg_ahb",
+   "pipe0", "pipe1", "pipe2";
+
+   vdda-phy-supply = <_l28>;
+   vdda-pll-supply = <_l12>;
+
+   resets = < GCC_PCIE_PHY_BCR>,
+   < GCC_PCIE_PHY_COM_BCR>,
+   < GCC_PCIE_PHY_COM_NOCSR_BCR>,
+   < GCC_PCIE_0_PHY_BCR>,
+   < GCC_PCIE_1_PHY_BCR>,
+   < GCC_PCIE_2_PHY_BCR>;
+   reset-names = "phy", "common", "cfg",
+   "lane0", "lane1", "lane2";
+   };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 5547984..d5e2b50f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -446,6 +446,14 @@ config PHY_STIH41X_USB
  Enable this to support the USB transceiver that is part of
  STMicroelectronics STiH41x SoC series.
  
+config PHY_QCOM_QMP

+   tristate "Qualcomm QMP PHY Driver"
+   depends on OF && (ARCH_QCOM || COMPILE_TEST)
+   select GENERIC_PHY
+   help
+ Enable this to support the QMP PHY transceiver that is used
+ with controllers such as PCIe, UFS, and USB on Qualcomm chips.
+
  config PHY_QCOM_QUSB2
tristate "Qualcomm QUSB2 PHY Driver"
depends on OF && (ARCH_QCOM || COMPILE_TEST)
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 848489d..fde9fba 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY)  += phy-spear1340-miphy.o
  obj-$(CONFIG_PHY_XGENE)

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

[PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

[PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets

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