Re: [PATCH 2/3] scsi:ufs:add ufs node property for hi3660

2017-06-09 Thread Guodong Xu 
Bu Tao,

One other issue: the 'sender' of your patchset is "butao". For
upstreaming purpose, it is recommended to use your full name, in
"first name" + "Surname" format. In your case, you need to specify it
in your commit message:

$ git commit --amend --author="Bu Tao "

You may also want to add that to your .gitconfig to save your future effort.
[user]
name = Bu Tao
email = bu...@hisilicon.com

-Guodong


On Sat, Jun 10, 2017 at 10:44 AM, Guodong Xu  wrote:
> Bu Tao,
>
> 1. Subject line of this patch goes something like "arm64: dts: hi3660:
> add ufs support xxx"
>
> 2. Have you run "./scripts/get_maintainer.pl *.patch" to get the
> correct maintainers to include into your patch review?
> I don't think so. Because this is a dts change, however in your
> email's to/ cc/, there is no DTS reviewers being included. Please fix
> that and resend.
>
> 3. I suppose before sending your patchset, you already tested it
> against tip kernel. For example, where your dts change can be applied?
> If they apply to my dts patchset [1], please mention it in your commit
> message. If they don't, then please tell us where.
>
> [1].  http://www.spinics.net/lists/devicetree/msg178303.html
>
> 4. Re-send, send them as "git format-patch -v2".
>
> -Guodong
>
> On Sat, Jun 10, 2017 at 9:20 AM, butao  wrote:
>> add ufs node for hi3660
>>
>> Signed-off-by: Bu Tao 
>> ---
>>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20 
>>  1 file changed, 20 insertions(+)
>>  mode change 100644 => 100755 arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi 
>> b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> old mode 100644
>> new mode 100755
>> index 3983086bd67b..4ba9cec43d94
>> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> @@ -141,6 +141,26 @@
>> #size-cells = <2>;
>> ranges;
>>
>> +ufs: ufs@ff3b {
>> +compatible = "jedec,ufs-1.1", 
>> "hisilicon,hi3660-ufs";
>> +reg = <0x0 0xff3b 0x0 0x1000>,  /* 0: HCI 
>> standard */
>> +  <0x0 0xff3b1000 0x0 0x1000>;  /* 1: UFS 
>> SYS CTRL */
>> +interrupt-parent = <>;
>> +interrupts = <0 278 4>;
>> +clocks = <_ctrl HI3660_CLK_GATE_UFSIO_REF>,
>> + <_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
>> +clock-names = "clk_ref", "clk_phy";
>> +freq-table-hz = <0 0>, <0 0>;
>> +resets = <_rst 0x84 12>,   /* offset: 
>> 0x84; bit: 12 */
>> + <_rst 0x84 7>;/* offset: 
>> 0x84; bit: 7  */
>> +reset-names = "rst", "assert";
>> +ufs-hi3660-use-rate-B;
>> +ufs-hi3660-broken-fastauto;
>> +ufs-hi3660-use-HS-GEAR3;
>> +ufs-hi3660-broken-clk-gate-bypass;
>> +status = "ok";
>> +};
>> +
>> fixed_uart5: fixed_19_2M {
>> compatible = "fixed-clock";
>> #clock-cells = <0>;
>> --
>> 2.11.GIT
>>

Re: [PATCH 2/3] scsi:ufs:add ufs node property for hi3660

2017-06-09 Thread Guodong Xu 
Bu Tao,

One other issue: the 'sender' of your patchset is "butao". For
upstreaming purpose, it is recommended to use your full name, in
"first name" + "Surname" format. In your case, you need to specify it
in your commit message:

$ git commit --amend --author="Bu Tao "

You may also want to add that to your .gitconfig to save your future effort.
[user]
name = Bu Tao
email = bu...@hisilicon.com

-Guodong


On Sat, Jun 10, 2017 at 10:44 AM, Guodong Xu  wrote:
> Bu Tao,
>
> 1. Subject line of this patch goes something like "arm64: dts: hi3660:
> add ufs support xxx"
>
> 2. Have you run "./scripts/get_maintainer.pl *.patch" to get the
> correct maintainers to include into your patch review?
> I don't think so. Because this is a dts change, however in your
> email's to/ cc/, there is no DTS reviewers being included. Please fix
> that and resend.
>
> 3. I suppose before sending your patchset, you already tested it
> against tip kernel. For example, where your dts change can be applied?
> If they apply to my dts patchset [1], please mention it in your commit
> message. If they don't, then please tell us where.
>
> [1].  http://www.spinics.net/lists/devicetree/msg178303.html
>
> 4. Re-send, send them as "git format-patch -v2".
>
> -Guodong
>
> On Sat, Jun 10, 2017 at 9:20 AM, butao  wrote:
>> add ufs node for hi3660
>>
>> Signed-off-by: Bu Tao 
>> ---
>>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20 
>>  1 file changed, 20 insertions(+)
>>  mode change 100644 => 100755 arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi 
>> b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> old mode 100644
>> new mode 100755
>> index 3983086bd67b..4ba9cec43d94
>> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>> @@ -141,6 +141,26 @@
>> #size-cells = <2>;
>> ranges;
>>
>> +ufs: ufs@ff3b {
>> +compatible = "jedec,ufs-1.1", 
>> "hisilicon,hi3660-ufs";
>> +reg = <0x0 0xff3b 0x0 0x1000>,  /* 0: HCI 
>> standard */
>> +  <0x0 0xff3b1000 0x0 0x1000>;  /* 1: UFS 
>> SYS CTRL */
>> +interrupt-parent = <>;
>> +interrupts = <0 278 4>;
>> +clocks = <_ctrl HI3660_CLK_GATE_UFSIO_REF>,
>> + <_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
>> +clock-names = "clk_ref", "clk_phy";
>> +freq-table-hz = <0 0>, <0 0>;
>> +resets = <_rst 0x84 12>,   /* offset: 
>> 0x84; bit: 12 */
>> + <_rst 0x84 7>;/* offset: 
>> 0x84; bit: 7  */
>> +reset-names = "rst", "assert";
>> +ufs-hi3660-use-rate-B;
>> +ufs-hi3660-broken-fastauto;
>> +ufs-hi3660-use-HS-GEAR3;
>> +ufs-hi3660-broken-clk-gate-bypass;
>> +status = "ok";
>> +};
>> +
>> fixed_uart5: fixed_19_2M {
>> compatible = "fixed-clock";
>> #clock-cells = <0>;
>> --
>> 2.11.GIT
>>

Re: [PATCH 2/3] scsi:ufs:add ufs node property for hi3660

2017-06-09 Thread Guodong Xu 
On Sat, Jun 10, 2017 at 9:20 AM, butao  wrote:
> add ufs node for hi3660
>
> Signed-off-by: Bu Tao 
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20 
>  1 file changed, 20 insertions(+)
>  mode change 100644 => 100755 arch/arm64/boot/dts/hisilicon/hi3660.dtsi

Mode change 755? Err.

>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi 
> b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> old mode 100644
> new mode 100755
> index 3983086bd67b..4ba9cec43d94
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -141,6 +141,26 @@
> #size-cells = <2>;
> ranges;
>
> +ufs: ufs@ff3b {
> +compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs";
> +reg = <0x0 0xff3b 0x0 0x1000>,  /* 0: HCI 
> standard */
> +  <0x0 0xff3b1000 0x0 0x1000>;  /* 1: UFS 
> SYS CTRL */
> +interrupt-parent = <>;
> +interrupts = <0 278 4>;
> +clocks = <_ctrl HI3660_CLK_GATE_UFSIO_REF>,
> + <_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
> +clock-names = "clk_ref", "clk_phy";
> +freq-table-hz = <0 0>, <0 0>;
> +resets = <_rst 0x84 12>,   /* offset: 
> 0x84; bit: 12 */
> + <_rst 0x84 7>;/* offset: 
> 0x84; bit: 7  */
> +reset-names = "rst", "assert";
> +ufs-hi3660-use-rate-B;
> +ufs-hi3660-broken-fastauto;
> +ufs-hi3660-use-HS-GEAR3;
> +ufs-hi3660-broken-clk-gate-bypass;
> +status = "ok";
> +};
> +
> fixed_uart5: fixed_19_2M {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> --
> 2.11.GIT
>

Re: [PATCH 2/3] scsi:ufs:add ufs node property for hi3660

2017-06-09 Thread Guodong Xu 
On Sat, Jun 10, 2017 at 9:20 AM, butao  wrote:
> add ufs node for hi3660
>
> Signed-off-by: Bu Tao 
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20 
>  1 file changed, 20 insertions(+)
>  mode change 100644 => 100755 arch/arm64/boot/dts/hisilicon/hi3660.dtsi

Mode change 755? Err.

>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi 
> b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> old mode 100644
> new mode 100755
> index 3983086bd67b..4ba9cec43d94
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -141,6 +141,26 @@
> #size-cells = <2>;
> ranges;
>
> +ufs: ufs@ff3b {
> +compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs";
> +reg = <0x0 0xff3b 0x0 0x1000>,  /* 0: HCI 
> standard */
> +  <0x0 0xff3b1000 0x0 0x1000>;  /* 1: UFS 
> SYS CTRL */
> +interrupt-parent = <>;
> +interrupts = <0 278 4>;
> +clocks = <_ctrl HI3660_CLK_GATE_UFSIO_REF>,
> + <_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
> +clock-names = "clk_ref", "clk_phy";
> +freq-table-hz = <0 0>, <0 0>;
> +resets = <_rst 0x84 12>,   /* offset: 
> 0x84; bit: 12 */
> + <_rst 0x84 7>;/* offset: 
> 0x84; bit: 7  */
> +reset-names = "rst", "assert";
> +ufs-hi3660-use-rate-B;
> +ufs-hi3660-broken-fastauto;
> +ufs-hi3660-use-HS-GEAR3;
> +ufs-hi3660-broken-clk-gate-bypass;
> +status = "ok";
> +};
> +
> fixed_uart5: fixed_19_2M {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> --
> 2.11.GIT
>

Re: [PATCH 2/3] scsi:ufs:add ufs node property for hi3660

2017-06-09 Thread Guodong Xu 
Bu Tao,

1. Subject line of this patch goes something like "arm64: dts: hi3660:
add ufs support xxx"

2. Have you run "./scripts/get_maintainer.pl *.patch" to get the
correct maintainers to include into your patch review?
I don't think so. Because this is a dts change, however in your
email's to/ cc/, there is no DTS reviewers being included. Please fix
that and resend.

3. I suppose before sending your patchset, you already tested it
against tip kernel. For example, where your dts change can be applied?
If they apply to my dts patchset [1], please mention it in your commit
message. If they don't, then please tell us where.

[1].  http://www.spinics.net/lists/devicetree/msg178303.html

4. Re-send, send them as "git format-patch -v2".

-Guodong

On Sat, Jun 10, 2017 at 9:20 AM, butao  wrote:
> add ufs node for hi3660
>
> Signed-off-by: Bu Tao 
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20 
>  1 file changed, 20 insertions(+)
>  mode change 100644 => 100755 arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi 
> b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> old mode 100644
> new mode 100755
> index 3983086bd67b..4ba9cec43d94
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -141,6 +141,26 @@
> #size-cells = <2>;
> ranges;
>
> +ufs: ufs@ff3b {
> +compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs";
> +reg = <0x0 0xff3b 0x0 0x1000>,  /* 0: HCI 
> standard */
> +  <0x0 0xff3b1000 0x0 0x1000>;  /* 1: UFS 
> SYS CTRL */
> +interrupt-parent = <>;
> +interrupts = <0 278 4>;
> +clocks = <_ctrl HI3660_CLK_GATE_UFSIO_REF>,
> + <_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
> +clock-names = "clk_ref", "clk_phy";
> +freq-table-hz = <0 0>, <0 0>;
> +resets = <_rst 0x84 12>,   /* offset: 
> 0x84; bit: 12 */
> + <_rst 0x84 7>;/* offset: 
> 0x84; bit: 7  */
> +reset-names = "rst", "assert";
> +ufs-hi3660-use-rate-B;
> +ufs-hi3660-broken-fastauto;
> +ufs-hi3660-use-HS-GEAR3;
> +ufs-hi3660-broken-clk-gate-bypass;
> +status = "ok";
> +};
> +
> fixed_uart5: fixed_19_2M {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> --
> 2.11.GIT
>

Re: [PATCH 2/3] scsi:ufs:add ufs node property for hi3660

2017-06-09 Thread Guodong Xu 
Bu Tao,

1. Subject line of this patch goes something like "arm64: dts: hi3660:
add ufs support xxx"

2. Have you run "./scripts/get_maintainer.pl *.patch" to get the
correct maintainers to include into your patch review?
I don't think so. Because this is a dts change, however in your
email's to/ cc/, there is no DTS reviewers being included. Please fix
that and resend.

3. I suppose before sending your patchset, you already tested it
against tip kernel. For example, where your dts change can be applied?
If they apply to my dts patchset [1], please mention it in your commit
message. If they don't, then please tell us where.

[1].  http://www.spinics.net/lists/devicetree/msg178303.html

4. Re-send, send them as "git format-patch -v2".

-Guodong

On Sat, Jun 10, 2017 at 9:20 AM, butao  wrote:
> add ufs node for hi3660
>
> Signed-off-by: Bu Tao 
> ---
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20 
>  1 file changed, 20 insertions(+)
>  mode change 100644 => 100755 arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi 
> b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> old mode 100644
> new mode 100755
> index 3983086bd67b..4ba9cec43d94
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -141,6 +141,26 @@
> #size-cells = <2>;
> ranges;
>
> +ufs: ufs@ff3b {
> +compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs";
> +reg = <0x0 0xff3b 0x0 0x1000>,  /* 0: HCI 
> standard */
> +  <0x0 0xff3b1000 0x0 0x1000>;  /* 1: UFS 
> SYS CTRL */
> +interrupt-parent = <>;
> +interrupts = <0 278 4>;
> +clocks = <_ctrl HI3660_CLK_GATE_UFSIO_REF>,
> + <_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
> +clock-names = "clk_ref", "clk_phy";
> +freq-table-hz = <0 0>, <0 0>;
> +resets = <_rst 0x84 12>,   /* offset: 
> 0x84; bit: 12 */
> + <_rst 0x84 7>;/* offset: 
> 0x84; bit: 7  */
> +reset-names = "rst", "assert";
> +ufs-hi3660-use-rate-B;
> +ufs-hi3660-broken-fastauto;
> +ufs-hi3660-use-HS-GEAR3;
> +ufs-hi3660-broken-clk-gate-bypass;
> +status = "ok";
> +};
> +
> fixed_uart5: fixed_19_2M {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> --
> 2.11.GIT
>

[PATCH 2/3] scsi:ufs:add ufs node property for hi3660

2017-06-09 Thread butao 
add ufs node for hi3660

Signed-off-by: Bu Tao 
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20 
 1 file changed, 20 insertions(+)
 mode change 100644 => 100755 arch/arm64/boot/dts/hisilicon/hi3660.dtsi

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi 
b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
old mode 100644
new mode 100755
index 3983086bd67b..4ba9cec43d94
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -141,6 +141,26 @@
#size-cells = <2>;
ranges;
 
+ufs: ufs@ff3b {
+compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs";
+reg = <0x0 0xff3b 0x0 0x1000>,  /* 0: HCI 
standard */
+  <0x0 0xff3b1000 0x0 0x1000>;  /* 1: UFS SYS 
CTRL */
+interrupt-parent = <>;
+interrupts = <0 278 4>;
+clocks = <_ctrl HI3660_CLK_GATE_UFSIO_REF>,
+ <_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
+clock-names = "clk_ref", "clk_phy";
+freq-table-hz = <0 0>, <0 0>;
+resets = <_rst 0x84 12>,   /* offset: 
0x84; bit: 12 */
+ <_rst 0x84 7>;/* offset: 
0x84; bit: 7  */
+reset-names = "rst", "assert";
+ufs-hi3660-use-rate-B;
+ufs-hi3660-broken-fastauto;
+ufs-hi3660-use-HS-GEAR3;
+ufs-hi3660-broken-clk-gate-bypass;
+status = "ok";
+};
+
fixed_uart5: fixed_19_2M {
compatible = "fixed-clock";
#clock-cells = <0>;
-- 
2.11.GIT

[PATCH 2/3] scsi:ufs:add ufs node property for hi3660

2017-06-09 Thread butao 
add ufs node for hi3660

Signed-off-by: Bu Tao 
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20 
 1 file changed, 20 insertions(+)
 mode change 100644 => 100755 arch/arm64/boot/dts/hisilicon/hi3660.dtsi

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi 
b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
old mode 100644
new mode 100755
index 3983086bd67b..4ba9cec43d94
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -141,6 +141,26 @@
#size-cells = <2>;
ranges;
 
+ufs: ufs@ff3b {
+compatible = "jedec,ufs-1.1", "hisilicon,hi3660-ufs";
+reg = <0x0 0xff3b 0x0 0x1000>,  /* 0: HCI 
standard */
+  <0x0 0xff3b1000 0x0 0x1000>;  /* 1: UFS SYS 
CTRL */
+interrupt-parent = <>;
+interrupts = <0 278 4>;
+clocks = <_ctrl HI3660_CLK_GATE_UFSIO_REF>,
+ <_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
+clock-names = "clk_ref", "clk_phy";
+freq-table-hz = <0 0>, <0 0>;
+resets = <_rst 0x84 12>,   /* offset: 
0x84; bit: 12 */
+ <_rst 0x84 7>;/* offset: 
0x84; bit: 7  */
+reset-names = "rst", "assert";
+ufs-hi3660-use-rate-B;
+ufs-hi3660-broken-fastauto;
+ufs-hi3660-use-HS-GEAR3;
+ufs-hi3660-broken-clk-gate-bypass;
+status = "ok";
+};
+
fixed_uart5: fixed_19_2M {
compatible = "fixed-clock";
#clock-cells = <0>;
-- 
2.11.GIT