Re: [PATCH 2/5] edac: synopsys: Add EDAC ECC support for ZynqMP DDRC

2017-08-07 Thread Michal Simek 
On 7.8.2017 06:03, Borislav Petkov wrote:
> On Fri, Aug 04, 2017 at 02:00:24PM +0200, Michal Simek wrote:
>> From: Naga Sureshkumar Relli 
>>
>> This patch adds EDAC ECC support for ZynqMP DDRC IP
>>
>> Signed-off-by: Naga Sureshkumar Relli 
>> Signed-off-by: Michal Simek 
>> ---
>>
>>  drivers/edac/Kconfig |   2 +-
>>  drivers/edac/synopsys_edac.c | 306 
>> ++-
>>  2 files changed, 302 insertions(+), 6 deletions(-)
> 
> ...
> 
>> @@ -440,9 +706,12 @@ static int synps_edac_mc_init(struct mem_ctl_info *mci,
>>  mci->dev_name = SYNPS_EDAC_MOD_STRING;
>>  mci->mod_name = SYNPS_EDAC_MOD_VER;
>>  mci->mod_ver = "1";
>> -
>> -edac_op_state = EDAC_OPSTATE_POLL;
>> -mci->edac_check = synps_edac_check;
>> +if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
>> +edac_op_state = EDAC_OPSTATE_INT;
>> +} else {
>> +edac_op_state = EDAC_OPSTATE_POLL;
>> +mci->edac_check = synps_edac_check;
>> +}
>>  mci->ctl_page_to_phys = NULL;
>>  
>>  status = synps_edac_init_csrows(mci);
> 
> This hunk doesn't apply cleanly:
> 
> $ test-apply.sh -q 
> /tmp/02-edac-synopsys-add_edac_ecc_support_for_zynqmp_ddrc.patch 
> checking file drivers/edac/Kconfig
> checking file drivers/edac/synopsys_edac.c
> Hunk #11 FAILED at 706.
> Hunk #12 succeeded at 723 (offset -1 lines).
> Hunk #13 succeeded at 754 (offset -1 lines).
> Hunk #14 succeeded at 803 (offset -1 lines).
> 1 out of 14 hunks FAILED
> 
> Please redo your patches against this branch:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git/log/?h=for-next
> 

The patch "EDAC: Get rid of mci->mod_ver" is causing that collision.
Will fix.



> Thx.
> 
>> @@ -458,8 +727,18 @@ static int synps_edac_mc_init(struct mem_ctl_info *mci,
>>  .quirks = 0,
>>  };
>>  
>> +static const struct synps_platform_data zynqmp_enh_edac_def = {
>> +.synps_edac_geterror_info   = synps_enh_edac_geterror_info,
>> +.synps_edac_get_mtype   = synps_enh_edac_get_mtype,
>> +.synps_edac_get_dtype   = synps_enh_edac_get_dtype,
>> +.synps_edac_get_eccstate= synps_enh_edac_get_eccstate,
>> +.quirks = DDR_ECC_INTR_SUPPORT,
>> +};
>> +
>>  static const struct of_device_id synps_edac_match[] = {
>>  { .compatible = "xlnx,zynq-ddrc-a05", .data = (void *)_edac_def },
>> +{ .compatible = "xlnx,zynqmp-ddrc-2.40a",
>> +.data = (void *)_enh_edac_def},
> 
> WARNING: DT compatible string "xlnx,zynqmp-ddrc-2.40a" appears un-documented 
> -- check ./Documentation/devicetree/bindings/
> #414: FILE: drivers/edac/synopsys_edac.c:740:
> +   { .compatible = "xlnx,zynqmp-ddrc-2.40a",
> 
> Please integrate checkpatch.pl into your patch creation workflow.
> 

Thanks,
Michal

Re: [PATCH 2/5] edac: synopsys: Add EDAC ECC support for ZynqMP DDRC

2017-08-07 Thread Michal Simek 
On 7.8.2017 06:03, Borislav Petkov wrote:
> On Fri, Aug 04, 2017 at 02:00:24PM +0200, Michal Simek wrote:
>> From: Naga Sureshkumar Relli 
>>
>> This patch adds EDAC ECC support for ZynqMP DDRC IP
>>
>> Signed-off-by: Naga Sureshkumar Relli 
>> Signed-off-by: Michal Simek 
>> ---
>>
>>  drivers/edac/Kconfig |   2 +-
>>  drivers/edac/synopsys_edac.c | 306 
>> ++-
>>  2 files changed, 302 insertions(+), 6 deletions(-)
> 
> ...
> 
>> @@ -440,9 +706,12 @@ static int synps_edac_mc_init(struct mem_ctl_info *mci,
>>  mci->dev_name = SYNPS_EDAC_MOD_STRING;
>>  mci->mod_name = SYNPS_EDAC_MOD_VER;
>>  mci->mod_ver = "1";
>> -
>> -edac_op_state = EDAC_OPSTATE_POLL;
>> -mci->edac_check = synps_edac_check;
>> +if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
>> +edac_op_state = EDAC_OPSTATE_INT;
>> +} else {
>> +edac_op_state = EDAC_OPSTATE_POLL;
>> +mci->edac_check = synps_edac_check;
>> +}
>>  mci->ctl_page_to_phys = NULL;
>>  
>>  status = synps_edac_init_csrows(mci);
> 
> This hunk doesn't apply cleanly:
> 
> $ test-apply.sh -q 
> /tmp/02-edac-synopsys-add_edac_ecc_support_for_zynqmp_ddrc.patch 
> checking file drivers/edac/Kconfig
> checking file drivers/edac/synopsys_edac.c
> Hunk #11 FAILED at 706.
> Hunk #12 succeeded at 723 (offset -1 lines).
> Hunk #13 succeeded at 754 (offset -1 lines).
> Hunk #14 succeeded at 803 (offset -1 lines).
> 1 out of 14 hunks FAILED
> 
> Please redo your patches against this branch:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git/log/?h=for-next
> 

The patch "EDAC: Get rid of mci->mod_ver" is causing that collision.
Will fix.



> Thx.
> 
>> @@ -458,8 +727,18 @@ static int synps_edac_mc_init(struct mem_ctl_info *mci,
>>  .quirks = 0,
>>  };
>>  
>> +static const struct synps_platform_data zynqmp_enh_edac_def = {
>> +.synps_edac_geterror_info   = synps_enh_edac_geterror_info,
>> +.synps_edac_get_mtype   = synps_enh_edac_get_mtype,
>> +.synps_edac_get_dtype   = synps_enh_edac_get_dtype,
>> +.synps_edac_get_eccstate= synps_enh_edac_get_eccstate,
>> +.quirks = DDR_ECC_INTR_SUPPORT,
>> +};
>> +
>>  static const struct of_device_id synps_edac_match[] = {
>>  { .compatible = "xlnx,zynq-ddrc-a05", .data = (void *)_edac_def },
>> +{ .compatible = "xlnx,zynqmp-ddrc-2.40a",
>> +.data = (void *)_enh_edac_def},
> 
> WARNING: DT compatible string "xlnx,zynqmp-ddrc-2.40a" appears un-documented 
> -- check ./Documentation/devicetree/bindings/
> #414: FILE: drivers/edac/synopsys_edac.c:740:
> +   { .compatible = "xlnx,zynqmp-ddrc-2.40a",
> 
> Please integrate checkpatch.pl into your patch creation workflow.
> 

Thanks,
Michal

Re: [PATCH 2/5] edac: synopsys: Add EDAC ECC support for ZynqMP DDRC

2017-08-06 Thread Borislav Petkov 
On Fri, Aug 04, 2017 at 02:00:24PM +0200, Michal Simek wrote:
> From: Naga Sureshkumar Relli 
> 
> This patch adds EDAC ECC support for ZynqMP DDRC IP
> 
> Signed-off-by: Naga Sureshkumar Relli 
> Signed-off-by: Michal Simek 
> ---
> 
>  drivers/edac/Kconfig |   2 +-
>  drivers/edac/synopsys_edac.c | 306 
> ++-
>  2 files changed, 302 insertions(+), 6 deletions(-)

...

> @@ -440,9 +706,12 @@ static int synps_edac_mc_init(struct mem_ctl_info *mci,
>   mci->dev_name = SYNPS_EDAC_MOD_STRING;
>   mci->mod_name = SYNPS_EDAC_MOD_VER;
>   mci->mod_ver = "1";
> -
> - edac_op_state = EDAC_OPSTATE_POLL;
> - mci->edac_check = synps_edac_check;
> + if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
> + edac_op_state = EDAC_OPSTATE_INT;
> + } else {
> + edac_op_state = EDAC_OPSTATE_POLL;
> + mci->edac_check = synps_edac_check;
> + }
>   mci->ctl_page_to_phys = NULL;
>  
>   status = synps_edac_init_csrows(mci);

This hunk doesn't apply cleanly:

$ test-apply.sh -q 
/tmp/02-edac-synopsys-add_edac_ecc_support_for_zynqmp_ddrc.patch 
checking file drivers/edac/Kconfig
checking file drivers/edac/synopsys_edac.c
Hunk #11 FAILED at 706.
Hunk #12 succeeded at 723 (offset -1 lines).
Hunk #13 succeeded at 754 (offset -1 lines).
Hunk #14 succeeded at 803 (offset -1 lines).
1 out of 14 hunks FAILED

Please redo your patches against this branch:

https://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git/log/?h=for-next

Thx.

> @@ -458,8 +727,18 @@ static int synps_edac_mc_init(struct mem_ctl_info *mci,
>   .quirks = 0,
>  };
>  
> +static const struct synps_platform_data zynqmp_enh_edac_def = {
> + .synps_edac_geterror_info   = synps_enh_edac_geterror_info,
> + .synps_edac_get_mtype   = synps_enh_edac_get_mtype,
> + .synps_edac_get_dtype   = synps_enh_edac_get_dtype,
> + .synps_edac_get_eccstate= synps_enh_edac_get_eccstate,
> + .quirks = DDR_ECC_INTR_SUPPORT,
> +};
> +
>  static const struct of_device_id synps_edac_match[] = {
>   { .compatible = "xlnx,zynq-ddrc-a05", .data = (void *)_edac_def },
> + { .compatible = "xlnx,zynqmp-ddrc-2.40a",
> + .data = (void *)_enh_edac_def},

WARNING: DT compatible string "xlnx,zynqmp-ddrc-2.40a" appears un-documented -- 
check ./Documentation/devicetree/bindings/
#414: FILE: drivers/edac/synopsys_edac.c:740:
+   { .compatible = "xlnx,zynqmp-ddrc-2.40a",

Please integrate checkpatch.pl into your patch creation workflow.

-- 
Regards/Gruss,
Boris.

ECO tip #101: Trim your mails when you reply.
--

Re: [PATCH 2/5] edac: synopsys: Add EDAC ECC support for ZynqMP DDRC

2017-08-06 Thread Borislav Petkov 
On Fri, Aug 04, 2017 at 02:00:24PM +0200, Michal Simek wrote:
> From: Naga Sureshkumar Relli 
> 
> This patch adds EDAC ECC support for ZynqMP DDRC IP
> 
> Signed-off-by: Naga Sureshkumar Relli 
> Signed-off-by: Michal Simek 
> ---
> 
>  drivers/edac/Kconfig |   2 +-
>  drivers/edac/synopsys_edac.c | 306 
> ++-
>  2 files changed, 302 insertions(+), 6 deletions(-)

...

> @@ -440,9 +706,12 @@ static int synps_edac_mc_init(struct mem_ctl_info *mci,
>   mci->dev_name = SYNPS_EDAC_MOD_STRING;
>   mci->mod_name = SYNPS_EDAC_MOD_VER;
>   mci->mod_ver = "1";
> -
> - edac_op_state = EDAC_OPSTATE_POLL;
> - mci->edac_check = synps_edac_check;
> + if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
> + edac_op_state = EDAC_OPSTATE_INT;
> + } else {
> + edac_op_state = EDAC_OPSTATE_POLL;
> + mci->edac_check = synps_edac_check;
> + }
>   mci->ctl_page_to_phys = NULL;
>  
>   status = synps_edac_init_csrows(mci);

This hunk doesn't apply cleanly:

$ test-apply.sh -q 
/tmp/02-edac-synopsys-add_edac_ecc_support_for_zynqmp_ddrc.patch 
checking file drivers/edac/Kconfig
checking file drivers/edac/synopsys_edac.c
Hunk #11 FAILED at 706.
Hunk #12 succeeded at 723 (offset -1 lines).
Hunk #13 succeeded at 754 (offset -1 lines).
Hunk #14 succeeded at 803 (offset -1 lines).
1 out of 14 hunks FAILED

Please redo your patches against this branch:

https://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git/log/?h=for-next

Thx.

> @@ -458,8 +727,18 @@ static int synps_edac_mc_init(struct mem_ctl_info *mci,
>   .quirks = 0,
>  };
>  
> +static const struct synps_platform_data zynqmp_enh_edac_def = {
> + .synps_edac_geterror_info   = synps_enh_edac_geterror_info,
> + .synps_edac_get_mtype   = synps_enh_edac_get_mtype,
> + .synps_edac_get_dtype   = synps_enh_edac_get_dtype,
> + .synps_edac_get_eccstate= synps_enh_edac_get_eccstate,
> + .quirks = DDR_ECC_INTR_SUPPORT,
> +};
> +
>  static const struct of_device_id synps_edac_match[] = {
>   { .compatible = "xlnx,zynq-ddrc-a05", .data = (void *)_edac_def },
> + { .compatible = "xlnx,zynqmp-ddrc-2.40a",
> + .data = (void *)_enh_edac_def},

WARNING: DT compatible string "xlnx,zynqmp-ddrc-2.40a" appears un-documented -- 
check ./Documentation/devicetree/bindings/
#414: FILE: drivers/edac/synopsys_edac.c:740:
+   { .compatible = "xlnx,zynqmp-ddrc-2.40a",

Please integrate checkpatch.pl into your patch creation workflow.

-- 
Regards/Gruss,
Boris.

ECO tip #101: Trim your mails when you reply.
--

[PATCH 2/5] edac: synopsys: Add EDAC ECC support for ZynqMP DDRC

2017-08-04 Thread Michal Simek 
From: Naga Sureshkumar Relli 

This patch adds EDAC ECC support for ZynqMP DDRC IP

Signed-off-by: Naga Sureshkumar Relli 
Signed-off-by: Michal Simek 
---

 drivers/edac/Kconfig |   2 +-
 drivers/edac/synopsys_edac.c | 306 ++-
 2 files changed, 302 insertions(+), 6 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 96afb2aeed18..e2f62dda8944 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -445,7 +445,7 @@ config EDAC_ALTERA_SDMMC
 
 config EDAC_SYNOPSYS
tristate "Synopsys DDR Memory Controller"
-   depends on ARCH_ZYNQ
+   depends on ARCH_ZYNQ || ARM64
help
  Support for error detection and correction on the Synopsys DDR
  memory controller.
diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 65f3b04d5a87..fdf1186151c1 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -22,6 +22,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "edac_module.h"
@@ -99,6 +100,87 @@
 /* DDR ECC Quirks */
 #define DDR_ECC_INTR_SUPPORTBIT(0)
 
+/* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */
+/* ECC Configuration Registers */
+#define ECC_CFG0_OFST  0x70
+#define ECC_CFG1_OFST  0x74
+
+/* ECC Status Register */
+#define ECC_STAT_OFST  0x78
+
+/* ECC Clear Register */
+#define ECC_CLR_OFST   0x7C
+
+/* ECC Error count Register */
+#define ECC_ERRCNT_OFST0x80
+
+/* ECC Corrected Error Address Register */
+#define ECC_CEADDR0_OFST   0x84
+#define ECC_CEADDR1_OFST   0x88
+
+/* ECC Syndrome Registers */
+#define ECC_CSYND0_OFST0x8C
+#define ECC_CSYND1_OFST0x90
+#define ECC_CSYND2_OFST0x94
+
+/* ECC Bit Mask0 Address Register */
+#define ECC_BITMASK0_OFST  0x98
+#define ECC_BITMASK1_OFST  0x9C
+#define ECC_BITMASK2_OFST  0xA0
+
+/* ECC UnCorrected Error Address Register */
+#define ECC_UEADDR0_OFST   0xA4
+#define ECC_UEADDR1_OFST   0xA8
+
+/* ECC Syndrome Registers */
+#define ECC_UESYND0_OFST   0xAC
+#define ECC_UESYND1_OFST   0xB0
+#define ECC_UESYND2_OFST   0xB4
+
+/* ECC Poison Address Reg */
+#define ECC_POISON0_OFST   0xB8
+#define ECC_POISON1_OFST   0xBC
+
+/* Control register bitfield definitions */
+#define ECC_CTRL_BUSWIDTH_MASK 0x3000
+#define ECC_CTRL_BUSWIDTH_SHIFT12
+#define ECC_CTRL_CLR_CE_ERRCNT BIT(2)
+#define ECC_CTRL_CLR_UE_ERRCNT BIT(3)
+
+/* DDR Control Register width definitions  */
+#define DDRCTL_EWDTH_162
+#define DDRCTL_EWDTH_321
+#define DDRCTL_EWDTH_640
+
+/* ECC status register definitions */
+#define ECC_STAT_UECNT_MASK0xF
+#define ECC_STAT_UECNT_SHIFT   16
+#define ECC_STAT_CECNT_MASK0xF00
+#define ECC_STAT_CECNT_SHIFT   8
+#define ECC_STAT_BITNUM_MASK   0x7F
+
+/* DDR QOS Interrupt register definitions */
+#define DDR_QOS_IRQ_STAT_OFST  0x20200
+#define DDR_QOSUE_MASK 0x4
+#defineDDR_QOSCE_MASK  0x2
+#defineECC_CE_UE_INTR_MASK 0x6
+
+/* ECC Corrected Error Register Mask and Shifts*/
+#define ECC_CEADDR0_RW_MASK0x3
+#define ECC_CEADDR0_RNK_MASK   BIT(24)
+#define ECC_CEADDR1_BNKGRP_MASK0x300
+#define ECC_CEADDR1_BNKNR_MASK 0x7
+#define ECC_CEADDR1_BLKNR_MASK 0xFFF
+#define ECC_CEADDR1_BNKGRP_SHIFT   24
+#define ECC_CEADDR1_BNKNR_SHIFT16
+
+/* DDR Memory type defines */
+#define MEM_TYPE_DDR3 0x1
+#define MEM_TYPE_LPDDR3 0x1
+#define MEM_TYPE_DDR2 0x4
+#define MEM_TYPE_DDR4 0x10
+#define MEM_TYPE_LPDDR4 0x10
+
 /**
  * struct ecc_error_info - ECC error log information
  * @row:   Row number
@@ -106,6 +188,8 @@
  * @bank:  Bank number
  * @bitpos:Bit position
  * @data:  Data causing the error
+ * @bankgrpnr: Bank group number
+ * @blknr: Block number
  */
 struct ecc_error_info {
u32 row;
@@ -113,6 +197,8 @@ struct ecc_error_info {
u32 bank;
u32 bitpos;
u32 data;
+   u32 bankgrpnr;
+   u32 blknr;
 };
 
 /**
@@ -171,7 +257,7 @@ struct synps_platform_data {
  *
  * Determines there is any ecc error or not
  *
- * Return: one if there is no error otherwise returns zero
+ * Return: 1 if there is no error otherwise returns 0
  */
 static int synps_edac_geterror_info(void __iomem *base,
struct synps_ecc_status *p)
@@ -219,6 +305,65 @@ static int synps_edac_geterror_info(void __iomem *base,
 }
 
 /**
+ * synps_enh_edac_geterror_info - Get the current ecc error info
+ * @base:  Pointer to the base address of the ddr memory controller
+ * @p: Pointer to the synopsys ecc status structure
+ *
+ * Determines there is any ecc error or not
+ *
+ * Return: one if there is no error otherwise returns zero
+ */
+static int synps_enh_edac_geterror_info(void __iomem *base,
+

[PATCH 2/5] edac: synopsys: Add EDAC ECC support for ZynqMP DDRC

2017-08-04 Thread Michal Simek 
From: Naga Sureshkumar Relli 

This patch adds EDAC ECC support for ZynqMP DDRC IP

Signed-off-by: Naga Sureshkumar Relli 
Signed-off-by: Michal Simek 
---

 drivers/edac/Kconfig |   2 +-
 drivers/edac/synopsys_edac.c | 306 ++-
 2 files changed, 302 insertions(+), 6 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 96afb2aeed18..e2f62dda8944 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -445,7 +445,7 @@ config EDAC_ALTERA_SDMMC
 
 config EDAC_SYNOPSYS
tristate "Synopsys DDR Memory Controller"
-   depends on ARCH_ZYNQ
+   depends on ARCH_ZYNQ || ARM64
help
  Support for error detection and correction on the Synopsys DDR
  memory controller.
diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
index 65f3b04d5a87..fdf1186151c1 100644
--- a/drivers/edac/synopsys_edac.c
+++ b/drivers/edac/synopsys_edac.c
@@ -22,6 +22,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "edac_module.h"
@@ -99,6 +100,87 @@
 /* DDR ECC Quirks */
 #define DDR_ECC_INTR_SUPPORTBIT(0)
 
+/* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */
+/* ECC Configuration Registers */
+#define ECC_CFG0_OFST  0x70
+#define ECC_CFG1_OFST  0x74
+
+/* ECC Status Register */
+#define ECC_STAT_OFST  0x78
+
+/* ECC Clear Register */
+#define ECC_CLR_OFST   0x7C
+
+/* ECC Error count Register */
+#define ECC_ERRCNT_OFST0x80
+
+/* ECC Corrected Error Address Register */
+#define ECC_CEADDR0_OFST   0x84
+#define ECC_CEADDR1_OFST   0x88
+
+/* ECC Syndrome Registers */
+#define ECC_CSYND0_OFST0x8C
+#define ECC_CSYND1_OFST0x90
+#define ECC_CSYND2_OFST0x94
+
+/* ECC Bit Mask0 Address Register */
+#define ECC_BITMASK0_OFST  0x98
+#define ECC_BITMASK1_OFST  0x9C
+#define ECC_BITMASK2_OFST  0xA0
+
+/* ECC UnCorrected Error Address Register */
+#define ECC_UEADDR0_OFST   0xA4
+#define ECC_UEADDR1_OFST   0xA8
+
+/* ECC Syndrome Registers */
+#define ECC_UESYND0_OFST   0xAC
+#define ECC_UESYND1_OFST   0xB0
+#define ECC_UESYND2_OFST   0xB4
+
+/* ECC Poison Address Reg */
+#define ECC_POISON0_OFST   0xB8
+#define ECC_POISON1_OFST   0xBC
+
+/* Control register bitfield definitions */
+#define ECC_CTRL_BUSWIDTH_MASK 0x3000
+#define ECC_CTRL_BUSWIDTH_SHIFT12
+#define ECC_CTRL_CLR_CE_ERRCNT BIT(2)
+#define ECC_CTRL_CLR_UE_ERRCNT BIT(3)
+
+/* DDR Control Register width definitions  */
+#define DDRCTL_EWDTH_162
+#define DDRCTL_EWDTH_321
+#define DDRCTL_EWDTH_640
+
+/* ECC status register definitions */
+#define ECC_STAT_UECNT_MASK0xF
+#define ECC_STAT_UECNT_SHIFT   16
+#define ECC_STAT_CECNT_MASK0xF00
+#define ECC_STAT_CECNT_SHIFT   8
+#define ECC_STAT_BITNUM_MASK   0x7F
+
+/* DDR QOS Interrupt register definitions */
+#define DDR_QOS_IRQ_STAT_OFST  0x20200
+#define DDR_QOSUE_MASK 0x4
+#defineDDR_QOSCE_MASK  0x2
+#defineECC_CE_UE_INTR_MASK 0x6
+
+/* ECC Corrected Error Register Mask and Shifts*/
+#define ECC_CEADDR0_RW_MASK0x3
+#define ECC_CEADDR0_RNK_MASK   BIT(24)
+#define ECC_CEADDR1_BNKGRP_MASK0x300
+#define ECC_CEADDR1_BNKNR_MASK 0x7
+#define ECC_CEADDR1_BLKNR_MASK 0xFFF
+#define ECC_CEADDR1_BNKGRP_SHIFT   24
+#define ECC_CEADDR1_BNKNR_SHIFT16
+
+/* DDR Memory type defines */
+#define MEM_TYPE_DDR3 0x1
+#define MEM_TYPE_LPDDR3 0x1
+#define MEM_TYPE_DDR2 0x4
+#define MEM_TYPE_DDR4 0x10
+#define MEM_TYPE_LPDDR4 0x10
+
 /**
  * struct ecc_error_info - ECC error log information
  * @row:   Row number
@@ -106,6 +188,8 @@
  * @bank:  Bank number
  * @bitpos:Bit position
  * @data:  Data causing the error
+ * @bankgrpnr: Bank group number
+ * @blknr: Block number
  */
 struct ecc_error_info {
u32 row;
@@ -113,6 +197,8 @@ struct ecc_error_info {
u32 bank;
u32 bitpos;
u32 data;
+   u32 bankgrpnr;
+   u32 blknr;
 };
 
 /**
@@ -171,7 +257,7 @@ struct synps_platform_data {
  *
  * Determines there is any ecc error or not
  *
- * Return: one if there is no error otherwise returns zero
+ * Return: 1 if there is no error otherwise returns 0
  */
 static int synps_edac_geterror_info(void __iomem *base,
struct synps_ecc_status *p)
@@ -219,6 +305,65 @@ static int synps_edac_geterror_info(void __iomem *base,
 }
 
 /**
+ * synps_enh_edac_geterror_info - Get the current ecc error info
+ * @base:  Pointer to the base address of the ddr memory controller
+ * @p: Pointer to the synopsys ecc status structure
+ *
+ * Determines there is any ecc error or not
+ *
+ * Return: one if there is no error otherwise returns zero
+ */
+static int synps_enh_edac_geterror_info(void __iomem *base,
+   struct synps_ecc_status *p)
+{
+   u32